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INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS
Int. J. Circ. ¹heor. Appl., 26, 93—102 (1998)
FAULT MACROMODEL FOR SWITCHES IN SWITCHED-CURRENT
CIRCUITS
CHENG-PING WANG AND CHIN-LONG WEY*
Department of Electrical Engineering, Michigan State University, East Lansing, MI 48824-1226, U.S.A.
SUMMARY
Based on possible defects on the layout of a practical non-ideal switch, fault model and test generation of current
copiers, basic building block of switched-current circuits, are presented in this study, where we consider two types of
switches, current switches and voltage switches, which have been commonly used in both switched-current circuits and
switched-capacitor circuits. Both catastrophic and parametric faults of transistors used as switches are considered. Test
sequences are proposed to achieve full testability of both current copiers and switched-current circuits. ( 1998 John
Wiley & Sons, Ltd.
KEY WORDS: switched-current circuits; switches; current switches; voltage switches
1. INTRODUCTION
Due to the exploding markets on telecommunication, multimedia and portable information systems, more
and more mixed-signal devices are being designed, integrated digital and analog on a single chip to improve
performance and reduce board size and cost. The circuit technology used in portable equipment has been
changing from the conventional analog circuit technology to a mixed-signal circuit technology. Lowvoltage/low-power circuit design is strongly needed for both analog and digital circuits to increase operation
time and to decrease the number of batteries and the weight, volume and operating temperature of the
equipment.1 Even though much complicated digital processing circuits, such as audio/video compression
and decompression technologies, have been widely used, analog circuits will remain for processing or
interfacing analog signals. With the trend that analog—digital interfaces are incorporated as a cell in complex
mixed-signal ICs containing mostly digital blocks for DSP and control, the use of the same supply-voltage
for both analog and digital circuits can give advantages in reducing the overall system cost by eliminating the
need of generating multiple supply voltages with DC—DC converters. Therefore, to be compatible with lowvoltage systems, analog signal processing components must be able to operate at supply voltage 2—3 V.
Reducing power dissipation associated with high-speed sampling and quantization is another important key
factor.
Traditionally, the Switched-Capacitor (SC) technique2 has been employed extensively in the analog
interface portion of mixed-signal designs. However, SC circuits are not fully compatible with digital CMOS
processing technology and, as the technology advances further, the drawbacks of SC technique are becoming
more significant.3 Recently, a class of analog circuits wherein current rather than voltage is the primary
signal medium has been received considerable attention. The use of current-mode creates a potential for
speed improvement because stray-inductance effects in such low-impedance SI circuits are much less severe
than those in high-impedance SC circuits.4~8 The same low-cost digital CMOS process for the digital
portion of mixed-signal circuits can also be used for the analog portion with SI technique.
*Correspondence to: C.-L. Wey, Department of Electrical Engineering, Michigan State University, East Lansing, MI 48824-1226,
U.S.A. E-mail: wey@egr.msu.edu
CCC 0098—9886/98/010093—10$17.50
( 1998 John Wiley & Sons, Ltd.
Received 30 September 1996
Revised 18 February 1997
94
C.-P. WANG AND C.-L. WEY
Analog MOS circuits are becoming increasingly sophisticated in terms of checking and correcting
themselves.9 Self-correcting, self-compensating, or self-calibrating techniques eliminate errors traditionally
associated with analog circuits. They have been adopted to eliminate offset and non-linearities, and cancel
the error effect. Self-compensating techniques can be used to cancel non-linearities.10 The self-compensating/calibration techniques may work properly when some component values deviate from their nominal
values within a certain tolerable percentage. For those circuits using SC or SI techniques, however, the
self-compensating/calibration techniques may no longer work properly in the presence of faulty switching
elements unless the switching elements are redundant and assumed to be fault-free11. Based on single
stuck-at fault model for the switching elements, the fault behaviour of the switched-current algorithmic
Analog-to-Digital (A/D) converter in Reference 12 has been reported.11 An alternative A/D converter with
Concurrent Error Detection (CED) capability was proposed to enhance its reliability for real-time operation.
That study assumed that faulty switches are either permanently stuck-at-ON state (S/ON) or stuck-at-OFF
state (S/OFF). The failure of other components can be modeled as the fault of the associated switch. Thus, the
converter can be fully testable. However, the fault models are insufficient when non-ideal switches are
employed. More effective fault models for switches with non-ideal effects should be further developed.
A number of fault models have been developed recently to correctly capture and represent the effect of
physical defects on circuit behaviour in analog and mixed-signal ICs.13~17 An effective fault model should
lend itself to efficient fault simulation and test generation. In this study, an effective fault macromodel for
switches is proposed. To demonstrate its effectiveness of this fault macromodel, test generation of current
copiers, a basic building block of SI circuits,3,4~8 using this model is also presented. However, the switches
are also commonly used in SC circuits, and thus the model is readily adopted in SC circuit testing.
In the next section, the basic structure and operation of current copier is reviewed, and the proposed fault
macromodel for switches is discussed. Section 3 demonstrates the test generation process using the proposed
ault macromodel. Finally, a concluding remark is given in Section 4.
2. PROPOSED FAULT MACROMODEL FOR SWITCHES
This section first reviews the components in a current copier and its operation. It is followed by discussing the
possible defects in a switch based on the manufacture process and its fault behaviors. Finally, an effective
fault macromodel for switch is proposed.
2.1 Current copiers
Current copier is the major building block of SI circuits. The performance of SI circuits is mainly
determined by the performance of copiers they employ.4~8 For example, the SI A/D converters in References
6 and 10 and the S/H circuit in References 7 and 8 each is comprised of three copiers. Current copier, as
shown in Figure 1(a), is comprised of switches S and S , the current-storage transistor M , and the holding
1
2
1
capacitor C. To copy the current I , switches S and S are turned on feeding the I to M and C. The
IN
1
2
IN
1
capacitor charges up to whatever gate voltage is needed by M to support a current equal to I . When both
1
IN
S and S are off, the copier cell is disconnected from the current source; thereafter the copier cell is capable of
1
2
sinking a current I when connected to a load. Thus, the current copier can reproduce the input current
IN
I without the need of well-matched elements. However, the copier suffers from two major error effects due
IN
to (1) non-zero conductance of M and (2) charge-feedthrough of S .3,18 The non-zero output conductance
1
2
results from the channel length-modulation effect and the drain-gate capacitive coupling of M . The
1
charge-feedthrough error effect is caused by the charge stored in the conducting channel of a MOS transistor.
When the gate voltage of S goes down during the turn-off transient, the charge held in the transistor realized
2
S will be forced to leave. Since one end of S is connected to the gate node of M , some charge of S will
2
2
1
2
dump to the gate of M and change the voltage across C. As a result, the current held in M will deviate from
1
1
I . In order to alleviate the error effect due to nonzero conductance of M , a negative feedback structure is
IN
1
Int. J. Circ. ¹heor. Appl., 26, 93—102 (1998)
( 1998 John Wiley & Sons, Ltd.
95
SWITCHED-CURRENT CIRCUITS
Figure 1. Current copiers: (a) basic; and (b) with negative feedback
proposed in Figure 1(b), where an amplifier is inserted between the drain and the gate of M . On the other
1
hand, the charge-feedthrough error effect can be reduced by either increasing the capacitance C, or choosing
appropriate size of switches.5
Switches can be implemented by NMOS, PMOS, or CMOS transistors. The use of NMOS transistor, as
the switch may suffer from the following two error effects: (1) the threshold voltage of the transistor may
clamp the input voltage signal and cause signal distortion; and (2) when the switch is connected to a capacitor
C, turning off the switch will force the charge stored in switch to dump to C and cause an error, referred to as
charge-feedthrough error. On the other hand, the use of CMOS switch with a dummy switch can alleviate the
charge-feedthrough error.19
The current copier implements with two types of switches: current switch and voltage switch. The former
has been commonly used in switched-current circuits, while the latter has been used in both switchedcapacitor and switched-current circuits. As their names imply, the current switch passes current signal, while
the voltage switch passes voltage signal. For example, S is used to pass the currents held in copiers, S used
3
1
to pass I . Thus, they are all implemented by current switches. On the other hand, S , used in copier for
IN
2
calibration, is implemented with voltage switches.
Although mismatched components are allowed in current copiers, the copiers are still susceptible to faulty
switches. Any faulty switches may cause the copier holding an incorrect current.
2.2. Defects and fault behaviours in switches
The proposed fault macromodel for switches is developed based on the inductive fault analysis concept,20
which determines the possible fault types and their probabilities for a given layout by the defect statistics of
manufacture process. Figure 2(a) shows five examples of process defects which affect the circuit behaviour.
We assume that the number of defects per unit area is uniformly distributed over the entire layout because
that the switching element is relatively small comparing with the entire circuit. The distribution of the defect
size follows the one given in Reference 19, as shown in Figure 2(b), and the two-metal, single polysilicon, and
n-well CMOS technology is employed. Thus, the defects include extra and missing layers of metal1, metal2,
polysilicon, and diffusion, and polycontacts and vias. The circuit behaviour due to the defects can be
summarized in Figure 2(c). In addition, some process defects may also cause faults, such as variation of
channel size, error on doping concentration, error on thickness of gate oxide, etc. However, these defects may
result in similar circuit behaviours listed above.
( 1998 John Wiley & Sons, Ltd.
Int. J. Circ. ¹heor. Appl., 26, 93—102 (1998)
96
C.-P. WANG AND C.-L. WEY
Figure 2. Defects: (a) defect layout; (b) distribution; and (c) summary of defects and fault behaviours.
2.3. Fault macromodels for switches
Due to the functionality of the switches used in the copier of Figure 1(b), two types of switches, voltage
switch and current switch, can be identified. Traditionally, a macromodel for switch is commonly used in
both SI and SC circuits switches regardless of their applications, and then the associated fault macromodel is
used for fault simulation and test generation. This study will show that, to simplify the fault macromodel for
efficient fault simulation and test generation, the fault types that cause only minor or no effects should not be
included. Therefore, a fault-free circuit macromodel may be used properly regardless of the applications, the
fault macromodel should developed in accordance with the applications of the circuit.
We first consider the fault macromodel for voltage switches. Let ¹ be the clock pulse width applied to
#-,
the switch. When a fault-free switch is on, the time constant q "R C should be smaller than ¹ for
0/
0/
#-,
sampling the input voltage signal. On the other hand, when the switch is off, the maximum leakage current
I
should be tolerable, i.e., I (I . When a switch is turned on, the on-resistances of both PMOS and
-%!,
-%!,
50NMOS transistors in the switch are connected in parallel. A Type f1 defect will cause a floating drain/source
in PMOS/NMOS transistor and results in an increase of on-resistance, where the off-resistance remains the
same. Thus, the increase of on-resistance due to this defect will cause q '¹ . As a result, the capacitor
0/
#-,
C samples and holds a unsettled, incorrect input voltage when switch is on, where the fault does not affect the
switch when it is off. A Type f2 defect is equivalent to a S/OFF fault in the switch, in which the on- and
off-resistances are the same. In other words, when switch is off, the decrease of off-resistance due to this defect
will cause I 'I , where I "(» —» )/R and » is the voltage sampled/held in C. On the other hand,
-%!,
50-%!,
*/ C 0&&
C
when the switch is on, it acts correctly even in the presence of this defect.
In the presence of a ¹ype f 3 defect, the gate of NMOS transistor is isolated from the PMOS transistor, and
traps some charges, either positive or negative charges. Three cases can be identified for trapping a positive
Int. J. Circ. ¹heor. Appl., 26, 93—102 (1998)
( 1998 John Wiley & Sons, Ltd.
SWITCHED-CURRENT CIRCUITS
97
charge:19 (1) for larger positive charges, it causes a decrease of off-resistance, but the on-resistance remains
the same; (2) for large negative charges, it causes an increase of on-resistance, but the off-resistance remains
the same; and (3) for a small amount of positive or negative charge, it causes a decrease of off-resistance and
an increase of on-resistance. Similarly, isolating the gate of PMOS transistor has the same fault behaviours
exactly opposite to those of NMOS transistor. Similar to the above discussion, the first case causes
q '¹ , while the second case results in I 'I . Case 3 includes both defect effects and causes a larger
0/
#-,
-%!,
50time constant s and an intolerable leakage current. A ¹ype f4 defect may cause an increase of on-resistance,
0/
while a ¹ype f5 defect results in a increase of off-resistance. Based on the fault behaviours of the defects, the
following three fault types are concluded,
Type VS1 fault: Causes an intolerable time constant q and a tolerable leakage current.
0/
Type VS2 fault: Causes a tolerable time constant q and an intolerable leakage current.
0/
Type VS3 fault: Causes an intolerable time constant q and an intolerable leakage current.
0/
In addition to the above three fault types, the charge-feedthrough error occurs at the moment when switch
is turned off. The charge held by the capacitor changes when switch state is changed. Types f1, f2, and f3
defects cause charge-feedthrough problem. Thus, an additional fault type should be included.
¹ype »S4 fault. Cause excess charge flows at the moment when switch state is changed.
Consider the current switches. Let » be the maximum voltage across the switch. In general, » "»
.!9
.!9
DD
(power supply voltage). For a fault-free current switch, its on-resistance R must be sufficiently small so that
0/
the maximum switch current ("» /R ) is larger than the maximum input current, I
and its
.!9 0/
IN(.!9)
off-resistance R has to be sufficiently large so that the maximum leakage current I
("» /R ) is
0&&
-%!,
.!9 0&&
smaller than a tolerance, I . Therefore, an increase of on-resistance, i.e. » /R (I
, results in an error
50.!9 0/
IN(.!9)
current, *I"I —» /R when I '(» /R ) is applied. On the other hand, a decrease of the offIN .!9 0/
IN
.!9 0/
resistance causes the maximum leakage current » /R to be greater than the predetermined current
.!9 0&&
tolerance I . Let » be the equivalent voltage across the switch, where » "I R . Therefore, it produces
50505050- 0&&
an intolerable leakage current, »/R , where » (»(» . Similar to the above discussion for voltage
0&&
50.!9
switch, three fault types can be concluded in a current switch as follows:
Type CS1 fault: Causes an error current when switch is on, and a tolerable leakage current when switch is
off.
Type CS2 fault: Causes an intolerable leakage current when switch is off and no error current when switch
is on.
Type CS3 fault: Causes an error current when switch is on and an intolerable leakage current when switch
is off.
It should be mentioned that the deviation of an output current in a current switch is caused only the
channel resistance, and not influenced by the unbalance of the gate capacitance. The charge-feedthrough
problem will not affect the current switch. This is the reason why both current and voltage switches should be
modeled separately.
2.4. Fault model for current copiers
In a current copier, it is comprised of switches and other components. It has been shown in Reference 11
that the faults on current-storage transistors and holding capacitors can be modeled as the equivalent faults
of the associated switch. It is still valid in this study based on the defects shown in Figure 2(a). More
specifically, the following defects may occur in a current-storage transistor: Breaks on gate polysilicon, i.e.
Type f3 defect, is equivalent to a S/OFF fault on the associated voltage switch, i.e., Type VS1 fault; breaks on
gate polysilicon, i.e. Type f4 defect, is equivalent to a Type CS1 fault; break on metal, either drain or source,
i.e. Type f1 defect, is equivalent to a S/OFF fault on the associated current switch, i.e. Type CS1 fault; short
between drain and gate implies that a S/ON fault on the associated voltage switch, i.e., Type VS2 fault; short
between source and gate, or between drain and source, is equivalent to a S/OFF fault on the associated
voltage switch, i.e. Type VS1 fault. Any defects in active region, i.e., Type f4 defect, is equivalent to a Type CS1
( 1998 John Wiley & Sons, Ltd.
Int. J. Circ. ¹heor. Appl., 26, 93—102 (1998)
98
C.-P. WANG AND C.-L. WEY
fault. Any process deviation causing an increase of on-resistance implies the presence of a Type CS1 fault.
The following defects may occur in the holding capacitors: Any defects causing a decrease of capacitance, or
an open circuit in the capacitor, is equivalent to a Type 4 fault on the associated voltage switch, i.e. Type VS4
fault. Any defects causing an increase of capacitance, or a short circuit in the capacitor is equivalent to a Type
VS1 fault.
The above equivalent faults include both catastrophic and parametric faults for both current-storage
transistors and the holding capacitors in a copier.
3. TEST GENERATION OF CURRENT COPIERS
To demonstrate the effectiveness of the fault macromodel for switches, a simple test generation process is
presented in this section. Note that current copier is the basic building block of SI circuit. The test sequence
applied for testing current copier can be also for SI circuits.
Consider the current copier in Figure 1(b). The circuit including S and M can be treated as an amplifier
2
1
with a switch which acts as a voltage control active load. Figure 3(a) plots the I—» characteristics of M and
1
the load S with and without faults, where the aspect ratio of M is (¼/¸)"6 lm/4 lm. For a fault-free
2
1
current copier, M can store a current of 100 mA when the switch is on and VGS"2.5 V. Figure 3(b)
1
illustrates the behaviours of faulty and fault-free copiers with the application of a test sequence. The test
sequence is comprised of three steps, or six clock cycles, and can detect all types of switch faults, i.e. Types
CS1—CS3 and VS1-VS4 faults. It also shows the test currents with the switching sequences for both switches
S and S at each clock cycle.
2
3
Let » be the initial voltage held in the holding capacitor C, and »
be the maximum voltage across the
CI
#.!9
capacitor. Taking the process variation into account, let » and » be the allowable voltage deviations for
50-1
50-2
both »
and 0, respectively. The corresponding current tolerances are I "b(» —» )*»
and
#.!9
50-1
#.!9 5) 50-1
I "b(» —» )* » , where » is the threshold voltage of M . We first describe the behaviour of the
50-2
#.!9 5)
50-2
5)
1
fault-free copier.
As illustrated in Figure 3(b), In Step 1, both S and S are turned on in the first cycle to copy an input
2
3
current I "0 to M so that the capacitor is discharged, and the current held in M is compared with an
IN
1
1
expected zero-current in the second cycle. In Step 2, an input current I "I is copied to M so that the
IN
3%&
1
capacitor is charged up to »
within the clock cycle ¹ . Thus, the current held in M is compared with an
#.!9
#-,
1
expected current I . Finally, in Step 3, a current I "0 and both S and S are off, a zero-current is expected
3%&
IN
2
3
for fault -free circuit.
Since M is expected to hold a zero-current the end of the second cycle of Step 1, unsuccessful test implies
1
the existence of a Type VS1, VS2, or VS3 fault. More specifically, the presence of a Type VS1 and VS3 fault
causes an intolerable time constant q which may be too short to discharge the capacitor so that the voltage
0/
across the capacitor exceeds » . On the other hand, a Type VS2 and VS3 fault produces an intolerable
50-2
leakage current so that current held in M exceeds I .
1
50-2
If the copier passes the test in Step 1, then the test pattern and clock sequence in Step 2 are applied. At the
end of Step 2, the current held in M is expected to be I , i.e. the voltage across the capacitor is expected to
1
3%&
be between (» —» ) and » . Thus, unsuccessful test implies the existence of a Type VS1-VS4, CS1 or
#.!9 50-1
#.!9
CS3 fault.
An intolerable time constant q caused by a Type VS1 and VS3 fault may be too short to charge up the
0/
capacitor and result that the voltage across the capacitor is below (» —» ). On the other hand, during the
#.!9 50-1
second cycle of Step 2, the test current is changed from I to 0, and the current held in M is expected to be
3%&
1
I . Since the output of the amplifier is zero, the voltage across S is » . As a result, when S is off, an
3%&
3
#.!9
3
intolerable leakage current caused by a Type VS2 and VS3 fault discharges the capacitor so that the voltage
across it is below (» —» ). Even though the test current is changed back to I , the leakage current may
#.!9 50-1
3%&
continuously discharge the capacitor. Since a Type VS4 fault causes excess charge flows at the moment when
S is off, the fault is identified if the voltage across the capacitor exceeds » . A Type CS1 or CS3 fault
3
#.!9
Int. J. Circ. ¹heor. Appl., 26, 93—102 (1998)
( 1998 John Wiley & Sons, Ltd.
99
SWITCHED-CURRENT CIRCUITS
Figure 3. (a) Simulation results of I—» plot of M with load lines for S ; and (b) fault behaviour and switching sequence
1
2
causes the maximum current can be stored in M is reduced. Hence, when I "I is applied, the fault is
1
IN
3%&
identified if the current held in M is less than (I —I ). Finally, unsuccessful test for Step 3 identifies a Type
1
3%& 50-1
CS2 or CS3 fault. The fault causes an intolerable leakage current when S is off, and thus it is identified if
2
a non-zero leakage current is detected. This concludes that the test sequence in Figure 3(b) detects Type
VS1—VS4 and CS1—CS3 faults.
In this test process, a tester is needed to compare the current held in M to 0 in Step 1 and I in Step 2. The
1
3%&
tester, as shown in Figure 4, is comprised of a current copier, a window comparator, and a D-flip-flop. Let
I denote the current held in M . Turning on S and S causes the sink current I "I , and turning on
M1
1
1
2
9
M1
S and S to copy a current (I —I ) to M . Thus, a zero current or I is applied from the input source
9
:
3%& 9
T
3%&
( 1998 John Wiley & Sons, Ltd.
Int. J. Circ. ¹heor. Appl., 26, 93—102 (1998)
100
C.-P. WANG AND C.-L. WEY
Figure 4. Tester and switching sequence
through S when I is to compare to a 0 or a I . Applying a zero current is equivalent to turning off S . This
1
M1
3%&
1
implies that an almost zero current is stored to M in both cases. This also implies that the copier in the tester
1
will store the current difference of I and the sink current I to M . The voltage » is compared with the
3%&
9
T
:
threshold voltages » and » of the window comparator. The output is defined as » "0 if » (» (» , and
1
2
0
2
:
1
» "1 otherwise. The values v, » , and » can be expressed in terms of I as follows;
0
50-1
50-2
50v"» "» "I / [I *(j #j )]
(1)
1
2
503%& /
1
» "I /J2I b
(2)
50-1
503%& /
» "» #J2I /b
(3)
50-2
5)
50- /
If a zero current is stored in M , the voltage » is equal to the offset voltage of the op-amp. This means that
1
:
» must be larger than the offset voltage of the op-amp. On the other hand, if a current equal to or greater
1
than I , by (1), » *» , and thus » "1. Thus, the digital data Q"0 means the comparison is asserted, and
50:
1
0
Q"1, otherwise.
Figure 5 shows the simulation results of the circuit in Figure 3(b), where the transistor size is
¼/¸"6 lm/4 lm, I "100 lA, and » "!» "v"0.1 V. The process parameters are j "1.991479e3%&
1
2
/
2, j "4.921086e-2, » "0.822163, k "4.89376e-5, and b "k *(6/4)"7.3406e-5. By (1)—(3), we obtain
1
5)
1
/
1
I "0.69126 lA, » "5.7 mV, and » "0.9594 V. The switching sequence is illustrated in Figure 4.
5050-1
50-2
Results show that Step 1 takes 1 cycle to initialize the circuit, 2 cycles to force a zero current to be held in N1,
and 1 cycle to compare the result, Step 2 takes 2 cycles to keep I and 1 cycle to compare the result, and
3%&
Step3 takes 2 cycles. Results conclude that Type VS1-VS3 faults can be detected in Steps 1 and 2, Step 2 also
detects Type VS4, CS1 and CS3 faults, and Step 3 detects Type CS2 and CS3 faults.
Int. J. Circ. ¹heor. Appl., 26, 93—102 (1998)
( 1998 John Wiley & Sons, Ltd.
101
SWITCHED-CURRENT CIRCUITS
Figure 5. Fault simulation results with application of test sequence
5. CONCLUSION
Both current and voltage switches which are commonly used in switched-capacitor and switched-current
circuits. This study investigates the fault behaviours of the defects on the layout of a CMOS switch. This
paper presents the fault macromodels for both switches and demonstrates the test generation process for
current copier using the fault macromodels. The fault macromodels include both catastrophic and noncatastrophic faults in the transistor which is used as switch. This study also shows that all non-switch
components can also model as the equivalent switch faults. As mentioned, an effective fault model is one that
correctly captures and represents the effect of physical defects on the circuit behaviour. This study shows that,
by (1)—(3), how effective the fault macromodel can be is determined by the tester. The range of the threshold
voltages, (—» , » ), in the window comparator limits the current tolerance I , and the voltage tolerances
2 1
50» and » . A better comparator is needed if a tighter tolerance is required. A tighter tolerance means an
50-1
50-2
accurate fault model. But, a better comparator is costly. Therefore, there exists a design trade-off between test
cost and fault macromodel. In other words, the fault macromodel can be further simplified when the test
environment is specified.
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