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INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS
Int. J. Circ. ¹heor. Appl., 27, 473}483 (1999)
90 dB, 90 MHz, 30 mW CMOS OTA FOR A HIGH CAPACITIVE LOADR
MARKUS HELFENSTEIN*, QIUTING HUANG AND GEORGE S. MOSCHYTZ
Signal and Information Processing Laboratory, Swiss Federal Institute of Technology Zurich, ETH Zentrum,
Zurich CH-8092, Switzerland
Integrated Systems Laboratory, Swiss Federal Institute of Technology Zurich, ETH Zentrum, Zurich CH-8092, Switzerland
SUMMARY
The design of simple gain-enhancement con"gurations for cascode transistors is presented. Applying one- or two-stage
di!erential ampli"ers or an improved regulated cascode con"guration in the feedback loop of a cascode, allows
high-speed and high-gain super-transistors at low voltage to be designed. These concepts were implemented in
a symmetrical OTA resulting in a measured 90 dB, 90 MHz, 30 mW ampli"er performance for a 14 pF load. Settling
measurements to 0)1% error for a unity-gain con"guration are presented. Copyright 1999 John Wiley & Sons, Ltd.
KEY WORDS: cascode transistors; CMOS; OTA
1. INTRODUCTION
Improvements in CMOS technology, operating at ever-increasing frequencies and lower supply voltages, and
the scaling down of the minimum size of transistors tend to reduce the available voltage swing of analogue
circuits. One way of overcoming this problem is to use low threshold technologies, another is to "nd
improved and simple circuit techniques permitting the dynamic range of analogue circuits to be increased.
The latter will be the subject of this paper.
Trends towards high-speed, high-dynamic range and low-voltage applications on the one hand, and
accuracy, high DC-gain and low power consumption on the other, lead to con#icting requirements. In
CMOS circuits, high speed at a small supply voltage usually necessitates short channels at high currents,
which in turn require wide devices for a good dynamic range, while high accuracy and high gain with low
power consumption demand long and wide channels. Cascoding transistor is a well-known technique to
improve the gain of a single transistor by the intrinsic gain of the cascode transistor (g r in Figure 1(a)).
K Q
However, stacking transistors in series has the drawback of losing voltage swing and is limited by parasitic
paths, such as the resistance of the substrate leakage. Our proposed gain-enhancement circuits enable
transistors at minimum channel length to be used, thereby largely avoiding the DC-gain/bandwidth con#ict.
Although many elaborate and complex circuits using gain-enhancement techniques have been discussed in
recent papers, and the basic concepts go back at least as far as 1979, there has been no mention of
gain-enhancement circuits in widely used op amp implementations. The complexity of the implementations
proposed in recent literature has varied widely. The regulated cascode or &RGC' (Figure 1(b)), involving only
four transistors, is the simplest one, and the super-MOST is the most complex, not only in terms of
transistor count, but also in terms of design. The regulated cascode is the preferred structure and is widely
used where high output impedances are needed, such as in op amp or switched current (SI) circuits. It needs
*Correspondence to: Markus Helfenstein, Signal and Information Processing Laboratory, Swiss Federal Institute of Technology
Zurich, ETH Zentrum, Zurich CH-8092, Switzerland
RPart of this work has previously appeared in Reference 2.
Contract/grant sponsor: KFW Jessi Project.
Contract/grant number: 23021 Eureka EU 127.
CCC 0098}9886/99/050473}11$17.50
Copyright 1999 John Wiley & Sons, Ltd.
Received 22 October 1996
Revised 9 November 1998
474
M. HELFENSTEIN, Q. HUANG AND G. S. MOSCHYTZ
Figure 1. Gain enhancement techniques for CMOS transistors: (a) cascode with di!erential feedback ampli"er, (b) regulated cascode,
(c) regulated cascode with improved minimum output voltage
only the feedback loop implemented by M and M and a current source formed by M . Because it entails
a voltage-swing loss of at least one threshold and one saturation voltage, the designs for high swing cascodes
using the RGC are necessarily bounded. Applying the RGC to SI circuits leads to design formulas that are
di$cult to satisfy (Reference 7, Chapter 6) and, in low-voltage designs, limits the allowable signal range due
to the minimum output voltage of the stacked transistors. The super-MOST, on the other hand, o!ers very
high-output impedances, low minimum output voltage, and wide bandwidth operation, but at the penalty of
complicated design.
In this paper we examine, in terms of complexity, level-shifting, input common-mode, and frequency
requirements, some simple ampli"er structures with respect to their suitability in a gain-boosting feedbackloop. These include an improved version of the regulated cascode, a single-stage OTA, and a Miller ampli"er.
We present experimental results of two high gain, wide bandwidth, and low-power OTAs for a high
capacitive load using gain-enhancement techniques. The methods used to measure these ampli"ers will also
be discussed.
2. SIMPLE GAIN-ENHANCEMENT STAGES
The basic and well-known idea of the gain-enhancement technique is shown in Figure 1(a). Using a local
feedback network to stabilize the drain-source voltage of the main transistor (M in Figure 1) the additional
gain fb is approximately the gain of the feedback loop. As shown in Reference 3 the output resistance of
a cascoded transistor can be calculated as
r "r #r (1#g r (1#fb))
(1)
K where r is the small signal output resistance and g the transconductance of transistor M (i"1, 2). The
G
KG
G
additional term (1#fb) is the gain-boosting factor due to the local feedback loop. Using high fb, transistors
whose e!ective output characteristics are very #at can be produced.
An often used implementation of the feedback circuit is the regulated cascode. Using the RGC, < has to
be at least larger than one threshold voltage. Thus, the minimum allowable output voltage to keep all
transistors in saturation can be a limiting factor in low-voltage designs. In Reference 8 a gain-boosting stage
consisting of cascoded transistors has been designed. Although very untroublesome in terms of design and
transistor count, the minimum output voltage is equally large than in the RGC case. Utilizing only few more
transistors, the regulated cascode can be redesigned with a lower minimum output voltage (Figure 1(c),
Reference 9). In Figure 2, the feedback circuits are simple di!erential-input one- or two-stage ampli"ers with
high gain. Compared to the circuits in References 3 and 4, where either a folded cascode or a super-MOST
Copyright 1999 John Wiley & Sons, Ltd.
Int. J. Circ. ¹heor. Appl., 27, 473}483 (1999)
90 dB, 90 MHz, 30 mW CMOS OTA FOR A HIGH CAPACITIVE LOAD
475
Figure 2. Simple feedback ampli"ers: (a) CMOS one-stage ampli"er, (b) two-stage Miller ampli"er
structure was used, the proposed designs are either more power e$cient or more straightforward, due to the
absence of additional local loops in the feedback ampli"er.
In what follows, we will examine the output level-shifting, the common-mode range, and the frequency
requirements of the improved version of the regulated cascode and of two simple classical di!erential
feedback structures.
2.1. Output level-shifting and input common-mode requirements
For low-voltage battery operation and maximum swing requirements, the RGC can be altered by
changing the n-channel transistor M of the RGC-structure into a p-channel device which is M (Figure 1(c)).
An additional current mirror and an output stage feeds the input signal back to the cascode transistor. By
choosing the appropriate reference voltage < the drain-source voltage < can now be as low as one
Q
saturation voltage. Thus < sums up to
< "< #<
(2)
In theory M can even be diode-connected but at the penalty of a worse common-mode rejection ratio. The
output voltage of the improved RGC becomes < #< , where < can be as small as the saturation
voltage of the main transistor M in Figure 1(c).
Using a one-stage di!erential input ampli"er in the local feedback path (Figure 2(a)), the bias-source
implemented with M calls for careful design. Generally, the reference voltage < has to be slightly larger
than the saturation voltage of the main transistor M . To maintain all transistors in saturation, (3) and (4)
have to hold.
"<
")< #< "< #< #<
(3)
< )< #< !" <
"#< !" < "
(4)
Equation (3) can be readily ful"lled. For transistor M , it is not di$cult to satisfy (4) even for low reference
voltages. Owing to the di!erences between n- and p-threshold voltages, the minimum saturation voltage for
the p-super-transistor is slightly larger than for its n-equivalent.
Referring to Figure 2(b), where a two-stage ampli"er (with Miller compensation) is shown, the input
common-mode range of the PMOS di!erential pair is limited on the ground terminal side by the saturation
voltage of M . For correct operation (5) has to hold, namely:
" < ""< #" < "!< *" <
"
(5)
Copyright 1999 John Wiley & Sons, Ltd.
Int. J. Circ. ¹heor. Appl., 27, 473}483 (1999)
476
M. HELFENSTEIN, Q. HUANG AND G. S. MOSCHYTZ
Table I. Comparison of MOS super transistors
MOS super
transistor
Feedback factors fb
Dominant pole u of the
feedback circuit
<
Additional
transistors, bias
Simple
*
Cascode
0
<
< #<
0
1 FET
1 bias
Regulated
cascode
(RGC)
g r
K *
g
C
g #g
C #C
< #<
3 FETs
1 bias
Modi"ed
RGC
r g
g g
K
K K
(g #g ) (g #g )
K
K K
K
g
K
(g #2g )
g
K
C #C
g #2g
2C
A
Cascode with
two-stage feedback OTA,
Figure 2(b)
g
g
K
K
(g #g ) (g #g )
(g #g ) (g #g )
g C
K A
< #<
< '<
8 FETs
2 bias
Cascode with
folded cascode
g
g
g
C
< #<
< '<
10 FETs
4 bias
Cascode with
feedback OTA,
Figure 2(a)
< #<
< #<
< '<
6 FETs
2 bias
7 FETs
2 bias
On the other hand, < *<
in order for M to stay in saturation. This leads to (6) as a design constraint
for M to stay in saturation, which is not di$cult to meet
< #" < "*< #" <
"
(6)
The output of the ampli"er in Figure 1(a) is required to bias the gate of M , which is above ground, by
< #< . Neither the modi"ed regulated cascode circuit in Figure 1(b) nor the two di!erential feedback
ampli"ers in Figure 2 have any di$culty providing the level shifting from the input to the output. The
common-mode range of both types of di!erential input stage ampli"ers is suitable for the gain-enhancing
application.
Table I gives an overview of di!erent, relatively simple, feedback circuits with their gain-boosting factors
fb (1), the dominant pole u , the minimum possible output voltage <
and the complexity of the addi
tional circuit in terms of transistor count and additional bias lines. As can be seen, the improved RGC
o!ers medium feedback factors at low complexity, whereas the two-stage ampli"er gives very high gain
with medium design overhead. Apart from the RGC, all proposed structures can be designed at minimum output voltages, close to < #< , which makes them ideally suited for a modern low voltage process that operates on a single 3)3 V supply voltage. Especially in switched current circuits, where,
for high-speed and low-voltage applications high gain is needed without restricting output swing, these
simple feedback ampli"ers improve the dynamic range considerably when compared to, for example,
a regulated cascode circuit. The basic design calculation is simpli"ed as well. Using the circuit proposed in
Figure 1(c) a switched current bandpass "lter operating on a single 3 V supply voltage was presented in
Reference 10. Utilizing cascoded transistors with local feedback circuits for the memory transistor and for the
Copyright 1999 John Wiley & Sons, Ltd.
Int. J. Circ. ¹heor. Appl., 27, 473}483 (1999)
90 dB, 90 MHz, 30 mW CMOS OTA FOR A HIGH CAPACITIVE LOAD
477
Figure 3. Output characteristics of di!erent super-transistors: simple transistor, normal cascode, regulated cascode, modi"ed regulated
cascode, cascode with one-stage feedback ampli"er, cascode with Miller feedback ampli"er
bias cell, it is possible to maintain accuracy in switched current designs with battery voltages as low as two
threshold voltages < .
The circuits shown in Figures 1 and 2 have been simulated with HSPICE, using the 1 lm SACMOS
process and the transistor models BSIM2. Figure 3 shows the output characteristics for several supertransistors using cascodes with feedback loops. The saturation current for all con"gurations is in the
mA-range as needed in the OTA-implementation discussed below. To minimize < and to maximize speed,
the size for both transistors M and M was chosen to be 300 lm by 1 lm. As can be seen in Figure 4, for
both the modi"ed regulated cascode and the cascode with the one-stage feedback ampli"er, the output
resistance of the circuits starts to increase drastically for a < round 0)5 V. Due to the relatively large
threshold voltages of the SACMOS process (< "0)7 V, < "!0)8 V), the regulated cascode starts to
operate properly only at 0)9 V resulting in a dynamic range loss of about 1 V for an n- and p-type cell. Thus,
the proposed feedback structures enhance dynamic range signi"cantly.
2.2. Requirements for fast settling
The e!ects of a closely spaced pole-zero doublet due to a feedback loop have been studied extensively in
References 4 and 12. It is known that doublets can degrade the settling performance of an amplifying element
drastically while causing only minor changes in the frequency behaviour in the local feedback circuit. In
order to achieve the required phase margin, the unity-gain bandwidth of the additional gain stage must be
lower than the second pole by a factor two. However, because the doublet is present near the unity-gain
Copyright 1999 John Wiley & Sons, Ltd.
Int. J. Circ. ¹heor. Appl., 27, 473}483 (1999)
478
M. HELFENSTEIN, Q. HUANG AND G. S. MOSCHYTZ
Figure 4. Output resistance of di!erent super-transistors: normal cascode, modi"ed regulated cascode, cascode with one-stage feedback
ampli"er, cascode with Miller feedback ampli"er
Figure 5. Symmetrical CMOS OTA using gain-enhancement techniques and output bu!er
Copyright 1999 John Wiley & Sons, Ltd.
Int. J. Circ. ¹heor. Appl., 27, 473}483 (1999)
90 dB, 90 MHz, 30 mW CMOS OTA FOR A HIGH CAPACITIVE LOAD
479
bandwidth of the gain-enhancement stage, the unity-gain bandwidth of the main ampli"er must, in fact, be
lower than the second pole by a factor substantially greater than two. This can easily be ful"lled because the
load capacitor of the additional ampli"er, which determines the unity-gain bandwidth of the gain-enhancement stage, is much smaller than the load capacitor of the output stage of the OTA, which determines the
unity-gain bandwidth of the main ampli"er.
Figure 6. Die photograph of the op amp with two-stage Miller OTAs as gain enhancing ampli"ers
Figure 7. Measured open-loop gain characteristic for OTA-1 (lower trace) and for OTA-2 (upper trace)
Copyright 1999 John Wiley & Sons, Ltd.
Int. J. Circ. ¹heor. Appl., 27, 473}483 (1999)
480
M. HELFENSTEIN, Q. HUANG AND G. S. MOSCHYTZ
3. OTA-IMPLEMENTATION AND MEASUREMENTS
In this section, the implementation, measurement methods, and results of two symmetrical CMOS OTAs,
integrated on one chip, are discussed. The test chip was intended as a vehicle to study the concepts mentioned
in Section 2. A simple design, in terms of implementation and analysis, for a high-gain, high-bandwidth, and
low power consuming OTA, even for high capacitive loads, was the objective. Furthermore, high slew rate
and large output swing were also required.
The CMOS OTAs were implemented and tested using the 1 lm SACMOS process. We chose the
symmetrical OTA con"guration because of the high slew rate capabilities. All cascodes and the main
current source were realized with either simple one-stage, case (a), or two-stage ampli"ers, case (b)
(Figures 2(a) and (b)). In order to maintain circuit symmetry, the proposed concepts were also applied
to the diode connected transistors in the current mirrors. Each OTA was integrated both in unity-gain
and open-loop con"gurations. To measure the full output swing and settling behaviour under the
unity-gain condition, a load capacitance of 14 pF was integrated, and a fast bu!er in a separate well was
used to decouple the high-impedance output of the OTA from the measurement setup. The circuit, with
the length and width of the main transistors given, is shown in Figure 5, and the die photograph in
Figure 6.
Measuring high gain with good resolution and having circuits with large bandwidth usually leads to
contradictory requirements. Thus, the basic idea is to split the transfer function into three parts in order to
decouple high-gain and high-frequency measurement problems. To perform DC or very low-frequency
measurements, we used a method proposed by Analog Devices, where the device under test (DUT)
operates in a simple loop together with an integrator. To measure the "rst pole of the OTA, we used the
Figure 8. Measured open-loop phase characteristic of OTA-1 (upper trace) and for OTA-2 (lower trace)
Copyright 1999 John Wiley & Sons, Ltd.
Int. J. Circ. ¹heor. Appl., 27, 473}483 (1999)
90 dB, 90 MHz, 30 mW CMOS OTA FOR A HIGH CAPACITIVE LOAD
481
method proposed in Reference 14. The OTA operates as an inverting ampli"er and bu!ers reduce the
in#uence of the output impedance of the OTA and of the measurement setup. Additional calibration
measurements are needed for compensation purposes. The unity-gain bandwidth measurement of the
inverting ampli"er con"guration delivered the same results as extrapolating the curve of the unity-gain
con"guration around 0 dB. The DC-gain of (a) and (b) was measured to be 80 and 90 dB, respectively.
This is close to the results obtained by simulations and calculations using the feedback factors given in
Table I where the gain was larger by 10 and 12%, respectively. Both OTAs have a unity-gain frequency
of 92 MHz (110 MHz in simulations). The plots are shown in Figures 7 and 8. The phase margin for
both circuits was measured to be 553 (623 in simulations). The di!erences between simulations and
measurements compare well with the ones given in Reference 8 and are explainable due to di$culties in
the modelling of the transistors' transition region and in the sensitivity of the circuit with respect to the bias
current.
For slew rate measurements, the DUT operates in a unity-gain con"guration. To compensate for the level
shifter at the output and to subtract the input step from the circuit response, some additional circuitry had to
be built. To achieve high resolution and to have fast settling of the o!-chip components, the AD811 high
performance video ampli"er was chosen for measurement purposes. In doing so, the appropriate feedback
resistors had to be chosen to trade o! between fast settling time with overshoots and slow but accurate
settling.
Figure 9 shows the settling performance for a feedback factor of 1, case (b), by applying a step *<"1 V at
G
the input. The measured settling time for a 0)1% tolerance at the output is 40)8 ns which corresponds to an
Figure 9. Measured settling results for OTA-2. The output signal (upper trace) and the error signal (lower trace) with *< "1 V
Copyright 1999 John Wiley & Sons, Ltd.
Int. J. Circ. ¹heor. Appl., 27, 473}483 (1999)
482
M. HELFENSTEIN, Q. HUANG AND G. S. MOSCHYTZ
Figure 10. Measured settling results for OTA-2. The output signal (upper trace) and the error signal (lower trace) with *< "4 V
Table II. Measured OTA performance
DC-gain
Unity-gain frequency
Load capacitance
Phase margin
CMRR
Settling to 0.1%
Power supply
Power dissipation
Output swing
OTA-1, (a)
OTA-2, (b)
80 dB
92 MHz
14 pF
'553
70 dB at DC
41 ns for *< "1 V
$2)5 V
24 mW
$2)1 V
90 dB
92 MHz
14 pF
'553
70 dB at DC
40)8 ns for *< "1 V
$2)5 V
29 mW
$2)1 V
error of 1 mV. In Figure 10, *< is 4 V, causing normal slewing behaviour and showing a large output swing.
G
The main measured characteristics are summarized in Table II.
4. CONCLUSIONS
Moving towards high-frequency and low-voltage applications will cause circuits based on standard design
techniques, such as switched capacitors and switched currents, to su!er due to reduced dynamic range.
Copyright 1999 John Wiley & Sons, Ltd.
Int. J. Circ. ¹heor. Appl., 27, 473}483 (1999)
90 dB, 90 MHz, 30 mW CMOS OTA FOR A HIGH CAPACITIVE LOAD
483
Handling large currents and high-output impedances at low-output voltages requires new design strategies
and gives rise to one of the key problems in analogue design. This is the reason for our investigation of
gain-boosting techniques with medium area overheads.
It has been shown that by using simple one- and two-stage feedback ampli"ers for the gain-enhancement
technique, the design of a super-MOST can be simpli"ed considerably. Several feedback con"gurations have
been examined and were shown to be useful especially in applications requiring high dynamic range at
low-battery voltage. Even at currents in the mA-range, a high-output resistance at a low-saturation voltage is
achievable.
With this technique, a symmetrical OTA was realized using the 1 lm SACMOS process. For the two-stage
gain-enhancement implementation, a DC-gain of 90 dB with a unity-gain frequency of 92 MHz with a14 pF
load was measured. Fast settling behaviour and an output swing of $2)1 V with an increase in chip area of
only 25% were achieved. The power dissipation for both OTA and biasing networks was only 30 mW, of
which 15% comprised of overheads for the boosting ampli"ers.
ACKNOWLEDGEMENTS
This work was "nancially supported by the KWF Jessi-Project, 2302. 1. Eureka EU 127.
REFERENCES
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Copyright 1999 John Wiley & Sons, Ltd.
Int. J. Circ. ¹heor. Appl., 27, 473}483 (1999)
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