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INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, VOL. 25, 483—502 (1997)
A MACROMODEL OF SAMPLE-AND-HOLD CIRCUITS
U. JO®RGES*, G. JUMMEL, G. MU®LLER AND M. REINHOLD
Institute for Fundamentals of Electrical Engineering and Electronics, Dresden University of Technology, Dresden, Germany
SUMMARY
A concise macromodel of sample-and-hold circuits for the simulator SPICE is proposed. This generalized model is
independent from actual technical realizations and is based upon compromises regarding the representation of exact
circuit structures in the model. Different types of feedback and hold capacitor connections corresponding to the standard
external circuit application are accounted for in the model internally. The macromodel allows one to simulate arbitrary
user circuits with respect to the behaviour in both the time and frequency domains including error parameters and the
temperature dependence of several parameters. Model parameters are extracted for the integrated sample-and-hold
circuit AD585 from Analog Devices as an example. Simulation results and selected diagrams are compared with the
manufacturer’s data. ( 1997 by John Wiley & Sons, Ltd.
Int. J. Circ. ¹heor. Appl., 25, 483—502 (1997)
No. of Figures: 25
No. of Tables: 2
No. of References: 8
1. INTRODUCTION
Sample-and-hold circuits are an important link between analogue and digital signal processing. As memories
for analogue values they have an analogue signal input, an analogue signal output and a digital control input
(Figure 1). Substantial circuit parts are the analogue switch controlled by a digital signal and the hold
capacitor. In addition, sample-and-hold circuits contain input and output buffer amplifiers. Sample-andhold circuits for high accuracy use an overall feedback.1—4
Without any doubt, macromodels of sample-and-hold circuits are necessary for simulating complex
mixed analogue—digital systems. However, powerful simulation models have not been available yet.
Largely independent from various technically realized circuit structures known so far, a generalized
macromodel5,6,7 for this circuit family has been developed which is based upon data sheet parameters.3,4 For
creating the model, techniques known from modelling operational amplifiers have been adapted.
Thus compromises have to be made regarding the exact representation of the circuit structures to
be modelled. Various types of feedback and hold capacitor connections are represented by a single
model structure according to the standard application circuit. The advantage of this approach is that
parameter extraction can be done only from data sheet parameters, even for circuits whose internal structure
is unknown. The model principally contains linear passive elements and controlled voltage and current
sources. The SPICE diode model is used as a non-linear element for voltage limitation and approximation
of characteristics. The sample-and-hold model has its own reference node which is different from the
global reference node ‘0’ in the SPICE simulator for the purpose of implementing the model as a subcircuit
into any arbitrary application circuit.
Noise is mainly caused by aperture jitter and random phase jitter of the sampling clock. The effects of
aperture jitter can be evaluated by modulating the aperture delay with a control voltage signal.
* Correspondence to: U. Jörges, Institute for Fundamentals of Electrical Engineering and Electronics, Dresden University of Technology, Dresden, Germany.
CCC 0098—9886/97/060483—20$17.50
( 1997 by John Wiley & Sons, Ltd.
Received 19 April 1996
484
U. JO®RGES E¹ A¸.
Figure 1. Principle of sample-and-hold circuit for high accuracy
Figure 2. Hold-to-sample transition
2. THEORY OF OPERATION AND PARAMETERS OF SAMPLE-AND-HOLD CIRCUITS
The definitions of the dynamic parameters of the hold-to-sample transition are illustrated in Figure 2. The
acquisition time t
is defined as the period from the hold-to-sample transition of the control signal to the
A#2
time instant where the output signal enters a specified tolerance band around the steady state value following
an input signal step of half the full scale range (FSR). The acquisition time consists of the switching delay t ,
SW
the slewing interval t
and the settling interval t . The definitions of the dynamic parameters of the
S-%8
SS
sample-to-hold transition are illustrated in Figure 3. The sample-to-hold settling time t is the period from
SH
the corresponding clock transition to the instant where the output signal enters a specified tolerance band.
The aperture delay t is the time interval from the clock transition to the instant where the switch actually
A
opens. Table 1 gives all circuit parameters which are covered by the model.
3. FUNCTIONAL BLOCKS OF MODEL
The entire model is divided into functional blocks, each representing a subset of circuit parameters. The
connection of the model blocks described in this section is shown in Figure 17. For the clock input stage and
Int. J. Circ. Theor. Appl., Vol. 25, 483—502 (1997)
( 1997 by John Wiley & Sons, Ltd.
MACROMODEL OF SAMPLE-AND-HOLD CIRCUITS
485
Figure 3. Sample-to-hold transition
Table I. Characteristics of sample-and-hold circuits
Supply characteristics
Supply current
Supply voltage dependence
Power supply rejection
Input characteristics
Input resistance
Input capacitance
Bias current
Temperature dependence
Offset voltage
Temperature coefficient
Output characteristics
Maximum output voltage swing
Maximum output current
Output resistance
Control input characteristics
Min. HIGH voltage level
Max. LOW voltage level
Input currents
Input capacitance
I
S1,/
dI /d»
S
S
PSR
1,/
r
*
C
*
I
IB
I (¹)
IB
»
IO
d» /d¹
IO
»
O.!91,/
I
O.!91,/
r
0
»
H.*/
»
L.!9
I
H,L
C
C-,
¹ransfer characteristics, sampling (tracking) mode
Closed-loop voltage gain
A
V
Gain error
*A
V
Temperature coefficient of gain
dA /d¹
V
Gain—bandwidth product
GBP
Slew rate
SR
1,/
Rise time
t
3
Peak overshoot
p
OS
Acquisition time
t
A#2
¹ransfer characteristics, hold mode
Aperture time
t
A
Effective aperture time
t
A%&&
Aperture jitter
*t
A
Sample-to-hold settling time
t
SH
Peak overshoot voltage
»
OH
Hold step
»
HS
Feedthrough attenuation
A
FT
Cut-off frequency
f
'FT
Leakage current!
I
D
Droop rate!
d» /dt
O
! In most data sheets either the leakage current or the droop rate is given. They can be calculated from each other for a known hold
capacitance value.
for modelling the temperature dependence of the bias and leakage currents several interchangeable model
blocks are available. To associate the model block diagrams with the entire model diagram, the same node
numbers as in Figure 17 are used throughout this section. The elements in the model block diagrams are
designated by the same symbols which are used in the equations whereas in Figure 17 their equivalent
SPICE notation is used.
( 1997 by John Wiley & Sons, Ltd.
Int. J. Circ. Theor. Appl., Vol. 25, 483—502 (1997)
486
U. JO®RGES E¹ A¸.
3.1. Input stage
The input stage (Figure 4) represents the parameters input resistance r , input capacitance C and bias
*
*
current I . The bias current is generated by a current source I which is controlled by the temperature stage
IB
IB
(see Section 3.8). The offset voltage is considered in the output stage (see Section 3.7). For sample-and-hold
circuits with external offset compensation terminals the offset voltage is adjusted such that it is compensated
in the hold mode by the hold step. The subsequent stages are controlled by the voltage across the input
terminals using controlled sources. Node 10 is the reference node of the macromodel.
3.2. Frequency response and slew rate stage
In the frequency response and slew rate stage (Figure 5) the closed-loop gain A , the gain—bandwidth
V
product GBP, the positive and negative slew rates SR and SR , the peak overshoot p and the acquisition
1
/
OS
time t
are modelled.
A#2
The analogue switch is modelled in SPICE by a two-dimensional polynomial controlled current source
representing a voltage controlled transconductance with an on-resistance r "1/g . This source is control0/
0/
led by the voltage at node 30, which is limited to 1 V (see clock-shaping stage, Section 3.5).
G
0
for v "0
C-,
i "g v v "
SW
0/ C-, 45
g v
for v "1 V
0/ 45
C-,
(1)
The current source i with its transconductance g is controlled by the sum of the input voltage and the
2
.2
feedback voltage across the hold capacitor C . The small-signal amplification of this stage is
H
A "g R
0
.2 2
(2)
Figure 4. Input stage
Figure 5. Frequency response and slew rate stage
Int. J. Circ. Theor. Appl., Vol. 25, 483—502 (1997)
( 1997 by John Wiley & Sons, Ltd.
MACROMODEL OF SAMPLE-AND-HOLD CIRCUITS
487
In principle the value of A can be chosen arbitrarily, because the stage is operating as an ideal integrator.
0
The amplification is fixed at A "1000 to minimize the influence of the voltage-limiting diodes D and
0
SR1
D on the slew rate.
SR/
For calculating the large-signal behaviour, the step response is divided into the slewing time t
and the
S-%8
sampling-mode settling time t intervals (Figure 2).8 The switch delay t is modelled in the clock-shaping
SS
SW
stage. During the slewing time one of the diodes, D or D , is conducting. Therefore the voltage across the
SR1
SR/
capacitor C is constant, which results in a constant current charging the capacitor C . The limiting voltages
2
H
» and » together with the time constant q determine the positive and negative slew rates SR and SR .
SR1
SR/
1
1
/
During the subsequent sampling-mode settling time interval the circuit operates in the small-signal region.
C
q "R C " H
(3)
1
0/ H g
0/
» "q SR
(4)
SR1
1
1
» "q SR
(5)
SR/
1 /
The lower absolute value of the slew rate values SR, and thereby the corresponding value of the limiting
voltage » , is used to determine the parameters of the sampling-mode settling characteristic. The acquisition
SR
time of a sample-and-hold circuit is defined in such a way that the sampling process starts when v steps
C-,
from 0 to 1 V, with the input voltage having changed by *º "FSR/2 and the initial voltage being v "0.
I
CH
The sampling-mode settling corresponds to the large-signal behaviour following an input step with an
amplitude *» and the switch being on, neglecting differences during a short period where the circuit is
I
operating in the small-signal region before entering the slewing interval.
The limiting phase is characterized by a linear rise SR in the voltage across the hold capacitor C . At the
H
time instant t"t
the voltage v is no longer limited. The amplitude *» of the input voltage step is
S-%8
C2
I
divided into two regions according to the two regions of the circuit in sampling mode.
*» "*»
#*»
(6)
I
I,S-%8
I,-*/
q SR
*» " 1
(7)
I,-*/
A
0
The transition from the slewing region to the linear region occurs at the time instant t"t
with the voltage
S-%8
across the hold capacitor and its derivative being the initial conditions.
v
(t )"*»
"*» !q SR/A
CH,S-%8 S-%8
I,S-%8
I
1
0
dv
(t)
CH,S-%8
"SR
dt
t/tS-%8
From equations (8) and (9) the slewing time t
is obtained.
S-%8
q
v
(t ) *»
t " CH,S-%8 S-%8 " I! 1
S-%8
SR A
SR
0
The frequency response is described by the second-order transfer function
K
C
D
1
A
p p
(s)
»
1 2
"
G(s)" CH,-*/ " 0
q q s2#(1/q )s#A /q q
(s!p ) (s!p )
» (s)
I,-*/
1 2
1
2
2
0 1 2
with the time constants
q "R C and q "R C @q
1
0/ H
2
2 2 1
( 1997 by John Wiley & Sons, Ltd.
(8)
(9)
(10)
(11)
(12)
Int. J. Circ. Theor. Appl., Vol. 25, 483—502 (1997)
488
U. JO®RGES E¹ A¸.
Thus, the gain—bandwidth product GBP is determined.
GBP"A /2n q
(13)
0
1
Because of the overshoot behaviour in the time domain, the poles p of the transfer function (11) have to be
1,2
complex conjugate.
SC
A BD
A
1 2
1
0!
p "a$jb, with a"!
and b"
1,2
q q
2q
2q
1 2
2
2
For zero initial conditions the step response v
(t) of the system has the form
CH,-*/
a
v
(t)"*»
1!eat cos (b t)! sin (b t)
CH,-*/
I,-*/
b
C
A
BD
(14)
(15)
The first extreme of this function provides the relative overshoot factor p .
OS
p "ena@b
(16)
OS
This yields the ratio k of the time constants q and q .
1
2
n 2
q
1
#1
k" 2"
(17)
q
ln p
4A
1
OS
0
The linear interval follows the slewing interval. The step response (15) is adjusted with the factors k and
1
k to the values of the function and its deriviative at the end of the slewing interval. In order to simplify the
2
following equation, the time is set to t"0 at the end of the slewing interval.
CA B D
v
C
A
BD
a
(t)"*»
1!eat k cos (b t)!k sin (b t)
CH,-*/
I,-*/
1
2b
(18)
v
(0)"0
(19)
CH,-*/
dv
(t)
CH,-*/
"SR
(20)
dt
t/0
Comparing the coefficients in equations (18)—(20) the constants k and k are determined.
1
2
k "1
(21)
1
SR
#k "1!2A k
(22)
k "
1
0
2 a*»
I,-*/
The time-decaying term in (18) describes the settling behaviour. The sampling-mode settling time t as a part
SS
of the acquisition time is approximated by the time instant where the enveloping curve reaches the relative
deviation e from the steady state value *» .
I
a 2
v
(t)"*»
k2#k2
eat
(23)
CH,%/7
I,-*/
1
2 b
K
SC
ABD
2q SR
2
e*» "
e~tSS@2q2,
t "t !t !t
(24)
I I(4A k!1)
SS
A#2
S-%8
SW
0
The slewing time t
is given by (10), the delay t of the switch is dealt with in Section 3.5. There are three
S-%8
SW
equations, (13), (17) and (24), for determining the two time constants q and q . The parameters slew rate, one
1
2
or more acquisition times, relative overshoot and gain—bandwidth product have to be adapted. For example,
Int. J. Circ. Theor. Appl., Vol. 25, 483—502 (1997)
( 1997 by John Wiley & Sons, Ltd.
MACROMODEL OF SAMPLE-AND-HOLD CIRCUITS
489
if the slew rate, the gain-bandwidth product and one acquisition time are selected, the overshoot is fixed.
Contradictions in parameter consistency are eliminated by optimization.
3.3. Stage for modelling feedthrough attenuation
Feedthrough attenuation is modelled frequency dependently (Figure 6). From the cut-off frequency f it
'FT
is falling by 20 dB per decade. The output signal of this stage is coupled to node 42 of the hold capacitor
by the controlled voltage source v via the capacitance C . The effective capacitance at node 42 of the
FT
FT
hold capacitor is set to C*"1 nF. The capacitance C is determined according to the feedthrough
H
FT
attenuation A .
FT
C "C*]10~AFT@20
(25)
H
FT
The inductance ¸ is calculated from the cut-off frequency f .
FT
'FT
¸ "1/2n f R
(26)
FT
'FT FT
The feedthrough attenuation not being able to fall below 0 dB, the following equation also has to be valid.
C
FTg R "1
C* FT FT2
H
The voltage-controlled current source i has a transconductance g .
FT
FT
(27)
3.4. Clock input stage
The clock input stage models the clock input currents I and I as well as the input capacitance C . The
H
L
C-,
logic levels are transformed into normalized currents and fed to the clock shaper (see Section 3.5).
There are various functional block models for the clock input stage. The coupling of the input functional
block model and the clock shaper is accomplished by the current source i at node 63. This source provides
V
a current of 1 mA in the sampling mode and !1 mA for a minimum high-level »
or a maximum
H.*/
low-level »
at the inputs respectively. Figure 7 shows the functional block model for a single asymmetriL.!9
cal input.
Figure 6. Stage for modelling feedthrough attenuation
Figure 7. Functional block model for asymmetrical clock inputs
( 1997 by John Wiley & Sons, Ltd.
Int. J. Circ. Theor. Appl., Vol. 25, 483—502 (1997)
490
U. JO®RGES E¹ A¸.
Figure 8 illustrates the functional block model of the clock input stage for a symmetric input, which is also
intended for modelling an asymmetrical input with a reference input.
3.5. Clock shaper
The clock shaper (Figure 9) consists of a pre-limiter, a delay stage and a limiter. The delay stage models the
aperture time. Furthermore, the aperture jitter can be evaluated using an additional controlling voltage » .
M0$
The delay stage between nodes 66 and 67 is represented by a second-order lowpass filter with the transfer
function (28). With the grading factor set to Q"1·172 the rising and falling edges of the output pulses have
their inflection point at their 50% value. The current source i has a transconductance g .
77
77
»
1/¸ C
VV VV
G (s)" 67"g R
V
VV V s2#(R /¸ )s#1/¸ C
»
63
V VV
VV VV
u2
0
"g R
VV V s2#(u /Q)s#u2
0
0
(28)
Figure 8. Functional block model for symmetrical clock inputs
Figure 9. Clock shaper
Int. J. Circ. Theor. Appl., Vol. 25, 483—502 (1997)
( 1997 by John Wiley & Sons, Ltd.
MACROMODEL OF SAMPLE-AND-HOLD CIRCUITS
The group delay t
',TP
491
of the second-order lowpass filter is determined by
t "1/Qu
(29)
',TP
0
The group delay t
is set to the effective aperture time t
to yield the centre frequency u .
',TP
A%&&
0
u "1/Qt
(30)
0
A%&&
The group delay t of the signal path is calculated from
'
q #q
2
t" 1
(31)
g
A
0
The switch delay t is the sum of the effective aperture time and the group delay of the signal path.
SW
t "t #t
(32)
SW
A%&&
'
The driving voltage v of the switch is limited to a range between 0 and 1 V using a tanh function, which is
C-,
implemented by the bottom circuit in Figure 9.
v "» #v
61
61,0
61,1
The constant part »
of this voltage adjusts the operating point of the diode D at I "10 lA for the clock
61,0
F
0
input voltage v "0. The value of the resistor R is assigned such that the resulting voltage drop at the
IC-,
F
operating point is negligible (R I "1 mV) compared with the forward voltage drop of the diode. The diode
F 0
current is approximately an exponential function in a defined clock input voltage range. The resistor
R limits the input current to reasonable numerical values during an input overload and converts the diode
F
current I into a voltage. Therefore equation (33) is valid for the voltage v across the resistor R with the
DF
62
F
conditions I @I and u AR I , where I is the saturation current of the diode.
S 0
61
F 0
S
v !v
v
62 !1 +R I exp 61,1
v "R I exp 61
(34)
62
F S
F
0
»
»
T
T
The controlled voltage source v obeys a tanh function.
C-,
1 2
1 2
(35)
v2 ]1 V!
v2 v
v "
62
62 C-,
C-,
I R
I R
0 F
0 F
exp(2v
/» )
v
1
61,1 T ]1 V" tanh 61,1 #1 ]1 V
v "
(36)
C-, exp(2v
/» )#1
»
2
61,1 T
T
The voltage » can get arbitrarily close to the limits 0 and 1 V but never exceed them at overload. This is
C-,
one important property of the circuit. The controlled current source I compensates the influence of the
F
minimum conductance G , which is introduced in parallel with the diode by SPICE. The temperature
.*/
dependence of the transfer characteristic caused by » is compensated by the additional control of the voltage
T
source v by » . A modulation of the aperture time is possible by shifting the threshold voltage by » .
F
5%.1
M0$
This facilitates the simulation of the aperture jitter.
C A
A B
B D
A B
A B
C A B D
3.6. Stage for modelling hold-mode settling time and hold step
The hold-mode settling time is modelled using a damped resonant circuit (Figure 10). Its output signal
together with the hold step is transferred onto the hold capacitor (Figure 11). The voltage at node 75 is
calculated from (37) provided that a voltage step of !1 V has been applied to node 30, where g is the
T
transconductance of the controlled current source i .
T
g
1V
» "! T
(37)
75
C s2#(1/R C )s#1/¸ C
T
T1 T
T T
( 1997 by John Wiley & Sons, Ltd.
Int. J. Circ. Theor. Appl., Vol. 25, 483—502 (1997)
492
U. JO®RGES E¹ A¸.
Figure 10. Stage for modelling holdmode settling time
Figure 11. Coupling of hold step and
hold-mode settling wave-form onto hold
capacitor
The inverse Laplace transform provides the voltage v in the time domain.
75
g 1
v (t)"! T exp(!a t)sin(b t)]1 V
(38)
75
C b
T
with
1
1
1
2
a"
and b"
!
¸ C
2R C
2R C
T T
T1 T
T1 T
With the resistor R set to 1 k), the three free parameters g , ¸ and C can be determined if the resonant
T1
T T
T
frequency, the damping factor and the absolute amplitude of the hold-mode settling wave-form are given.
The hold-step voltage » from the controlled voltage source v is capacitively coupled onto the hold
HS
HS
capacitor C via the capacitance C (Figure 11).
H
HS
D» D
(39)
C " HS C*
HS
1V H
SC
A
BD
The value of the hold capacitor C is determined such that the effective capacitance C* at node 42 is exactly 1 nF.
H
H
(40)
C "C*!C !C
H
HS
FT
H
3.7. Output Stage
The output stage models the output resistance r , the maximum output voltages »
, the maximum
0
O.!91,/
output currents I
and the offset voltage » . The polynomial controlled current source i of the
O.!91,/
IO
AV
output stage (Figure 12) adds the offset voltage to the output voltage v of the frequency response stage.
42
Additionally, the non-linear distortion, the gain and its temperature dependence are modelled. The current
source i
models the power supply feedthrough. The output voltage source v is two-dimensionally
PSR
54
controlled by both the voltage v and the reference potential of the sample-and-hold circuit. Thus the output
53
voltage is referred to node 10 of the model. The controlled current source i realizes the output resistance
O
using the voltage drop across the current source itself as the controlling voltage. Limiting the output current
is done by restricting the controlling voltage. The resistor R provides a DC path to node 21 as required in
21
SPICE and is set to 1 G).
3.8. Temperature stage
The temperature stage (Figure 13) provides a Kelvin-proportional voltage »
for modelling linear
5%.1
temperature dependences using the SPICE model (41) of the linear temperature-dependent resistor (b"0).
R(¹)"R(TNOM) [1#a(¹!TNOM)#b(¹!TNOM)2]
(41)
The parameters of the current I and the resistor R are extracted such that the temperature stage provides
T
T
a voltage » "1 V at the temperature ¹ (SPICE-Option TNOM). The temperature coefficient is set to
5%.1
0
a"1/TNOM. The voltage »
works as a linear temperature-controlled input value for any other
5%.1
Int. J. Circ. Theor. Appl., Vol. 25, 483—502 (1997)
( 1997 by John Wiley & Sons, Ltd.
MACROMODEL OF SAMPLE-AND-HOLD CIRCUITS
493
Figure 12. Output stage
Figure 13. Stage for generating temperature-dependent voltage
Figure 14. Functional block model for temperature dependence of drift current
controlled sources in the model. The approximation to a non-linear behaviour is realized using appropriate
polynomial coefficients of the controlled sources.
Another temperature stage with an exponential behaviour consists of the voltage source » , the diode
TD
D and the current source I . The parameter extraction is done for the desired behaviour. The
DT
TGD
exponential dependence of the diode saturation current on temperature is used.
A B
A
B
¹ XTI@n
E (1!¹ /¹)
0
I(» )"I
exp '
T
SO ¹
n»
0
T0
(42)
The bias current and drift current sources are interchangeable functional block models, because the linear
temperature dependence requires voltage control whereas the exponential temperature dependence requires
( 1997 by John Wiley & Sons, Ltd.
Int. J. Circ. Theor. Appl., Vol. 25, 483—502 (1997)
494
U. JO®RGES E¹ A¸.
Figure 15. Stage for modelling supply current
current control of the current source. Figure 14 shows the functional block model for the drift current. The
functional block model for the bias current has the same structure.
3.9. Stage for modelling supply current
In the model the supply current depends on the output current (Figure 15). The output current is assigned
to the positive or negative power supply respectively according to its sign by the diodes D and D . The
IO1
IO/
sources i and i generate the supply currents. The resistors R and R model the quiescent currents.
S1
S/
S1
S/
4. MODEL OF SAMPLE-AND-HOLD CIRCUIT AD585
The sample-and-hold circuit AD585 is used as an example for a complete model in this section.
4.1. Block diagram and complete model
See Figures 16 and 17.
4.2. Subcircuit listing
Int. J. Circ. Theor. Appl., Vol. 25, 483—502 (1997)
( 1997 by John Wiley & Sons, Ltd.
MACROMODEL OF SAMPLE-AND-HOLD CIRCUITS
( 1997 by John Wiley & Sons, Ltd.
495
Int. J. Circ. Theor. Appl., Vol. 25, 483—502 (1997)
496
U. JO®RGES E¹ A¸.
Figure 16. Block diagram. The ports marked with an asterisk are not available in the model
Int. J. Circ. Theor. Appl., Vol. 25, 483—502 (1997)
( 1997 by John Wiley & Sons, Ltd.
( 1997 by John Wiley & Sons, Ltd.
Int. J. Circ. Theor. Appl., Vol. 25, 483—502 (1997)
Figure 17. Complete model
498
U. JO®RGES E¹ A¸.
4.3. Comparison of simulation results and data sheet parameters
See Figures 18—25 and Table II.
Figure 18. Test circuit for simulation
Figure 19. Transfer characteristic
Int. J. Circ. Theor. Appl., Vol. 25, 483—502 (1997)
( 1997 by John Wiley & Sons, Ltd.
Figure 20. Frequency response of open- and closed-loop gain
Figure 21. Small-signal step response, sample-to-hold overshoot and hold step
Figure 22. Slew rate
( 1997 by John Wiley & Sons, Ltd.
Int. J. Circ. Theor. Appl., Vol. 25, 483—502 (1997)
Figure 23. Acquisition time
Figure 24. Aperture time
Figure 25. Temperature dependence of bias current
Int. J. Circ. Theor. Appl., Vol. 25, 483—502 (1997)
( 1997 by John Wiley & Sons, Ltd.
501
MACROMODEL OF SAMPLE-AND-HOLD CIRCUITS
Table II. Comparison between simulation results and data sheet
Parameter
Symbol
Conditions
Data sheet
Min.
Supply characteristics
Supply current
Power supply rejection
Input characteristics
Input resistance
Input capacitance
Offset voltage
Offset voltage
Bias current
Bias current
Output characteristics
Output resistance
max. output voltage
max. output current
Clock characteristics
min. HIGH-voltage
max. LOW-voltage
HIGH input current
LOW input current
Sampling-mode characteristics
Gain
Slew rate
Acquisition time
0.01% error range
0.01% error range
Rise time
Peak overshoot
Gain—bandwidth product
Full power bandwidth
Hold-mode characteristics
Aperture time
Sample-to-hold settling time
Peak overshoot voltage
Hold step
Feedthrough attenuation
Cutoff frequency
Droop rate
Droop rate
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5. CONCLUSIONS
In this paper a generalized macromodel of sample-and-hold circuits for the simulator SPICE based on the
data sheet characteristics has been presented. The model is independent from actual technical realizations
and is based upon compromises regarding the representation of exact circuit structures in the model.
Different types of feedback and hold capacitor connections corresponding to the standard external circuit
( 1997 by John Wiley & Sons, Ltd.
Int. J. Circ. Theor. Appl., Vol. 25, 483—502 (1997)
502
U. JO®RGES E¹ A¸.
application were accounted for in the model internally. The macromodel allows us to simulate arbitrary user
circuits with respect to the behaviour in both the time and frequency domains, including error parameters
and the temperature dependence of several parameters. The efficiency of the model was proved by comparison of simulation results and data sheet parameters of the integrated sample-and-hold circuit AD585 from
Analog Devices. In addition to this paper, the model was used successfully for the considerably different
circuits SHC605, HA5351 and HA2420.
ACKNOWLEDGEMENT
This paper is part of the project ‘Model Library of Complex Analog Components’ sponsored by the German
Ministry of Research and Technology.
REFERENCES
1. F. Moraveij, ‘A high-speed current-multiplexed sample-and-hold amplifier with low hold step’, IEEE J. Solid-State Circuits, SC-26,
1800—1808 (1991).
2. N. Greitschus, ‘Sample-and-hold circuits and their implementation in microelectronics’, Dissertation, Institute for Fundamentals of
Electrical Engeneering and Electronics, Dresden University of Technology, 1992 (in German).
3. ¸inear and ¹elecom ICs for Analog Signal Processing Applications, Harris Semiconductor, Melbourne, FL, USA, 1993—1994.
4. Design-In Reference Manual, Analog Devices, Norwood, MA, USA, 1994.
5. V. Pose, ‘Switch models for sample-and-hold circuits’, Diploma ¹hesis, Institute for Fundamentals of Electrical Engineering and
Electronics, Dresden University of Technology, 1994 (in German).
6. M. Reinhold, ‘Macromodeling for sample-and-hold circuits’, Diploma ¹hesis, Institute for Fundamentals of Electrical Engineering
and Electronics, Dresden University of Technology, 1994 (in German).
7. U. Jörges, G. Jummel, G. Müller and M. Reinhold, ¹he ¹º-Dresden Sample-and-Hold Circuit Model, Model Library of Complex
Analog Components, VDI/VDE Technologiezentrum Informationstechnik G.m.b.H, Teltow, 1995 (in German).
8. J.-Ch. Lin and J. H. Nevin, ‘A modified time-domain model for nonlinear analysis of an operational amplifier’, IEEE J. Solid-State
Circuits, SC-21, 478—483 (1986).
.
Int. J. Circ. Theor. Appl., Vol. 25, 483—502 (1997)
( 1997 by John Wiley & Sons, Ltd.
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