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which may be taken simply as the parallel combination of An
and Rf since RiH is very low in comparison.
Computer predictions based on hybrid n analysis illustrate
the potential of the very low-input-resistance approach. The
predicted bandwidth of the proposed design using BFT24
transistors with a maximum fT of 2-3 GHz and a feedback
resistor of 10 kQ with a stray capacitance Cf of 01 pF remains
between 140 MHz and 195 MHz up to a photodiode capacitance of 7pF with less than 0-5 dB gain peaking. Three openloop poles are indicated at approximately 28, 75 and 135 MHz
in addition to the pole due to the feedback resistor selfcapacitance.7
In comparison the predicted bandwidth of a popular highresistance design3 using identical transistors falls rapidly from
140 MHz to 34 MHz for an identical value of 7pF, passing
through 110 MHz for Cd = 0-8 pF, in excellent agreement with
previously published experimental results.3 For a feedback
capacitance of 0-25 pF, a more realistic value for discrete components, the advantage is almost as great: 67MHz at 7pF
compared to 23 MHz for the high-resistance design.
subsequent stages. This is due largely to the lowering of an
internal pole and the increased feedback ratio that results
from increasing the open-loop voltage gain Av in an attempt
to satisfy the necessary inequality AvCf > Cd.
The penalty of the lower-input-resistance approach is that
of increased noise due to the unity current gain of the CB
input stage. Thermal noise in the CB stage load resistor and
the shot noise of the second stage base current must now be
taken into account. A higher than usual input stage collector
current of 500 fiA is therefore required to optimise the overall
noise behaviour with an input capacitance of 5pF.* Compared to the CC input design under similar constraints the
theoretical noise current spectral density floor is raised from
4-2 x 10~24A2/Hz to 15-3 x 10~24A2/Hz below 1MHz. At
higher frequencies the values converge: 44-6 x 10~24A2/Hz at
100 MHz compared to 44-5 x 10" 24 A 2 /Hz for the highimpedance design. For 140Mbit/s NRZ operation these
figures translate to theoretical sensitivities of — 30-6 dBm for
the proposed design and —31-2 dBm for the CC approach.
The small difference of 0-6 dB is not critical in a local-area
network context and diminishes at higher bit rates as the
sensitivities converge.
Conclusion: A novel low-input-resistance approach to the
design of optical preamplifiers has been described that is very
tolerant of photodiode capacitance. The circuit is well suited
to monolithic fabrication enabling a bandwidth up to
200 MHz to be achieved. The approach is particularly suitable
for cost-effective high-speed local-area networks.
Cf =0 1pF,highR
photodiode capacitance,pF |668/3|
8th December 1986
Digital Communications Group
Department of Electrical Engineering & Electronics
PO Box 88, Manchester M60 1QD, United Kingdom
Fig. 3 Bandwidth comparison of low- and high-input-resistance formulations
Experimental verification was obtained for the case Cf =
0-25 ± 005pF using the proposed circuit and a similarly constructed high-resistance CC design. Results from electrical
pulse tests with a subnanosecond rise time pulse generator
showed very good agreement with the predictions as can be
seen from the experimental points in Fig. 3. The bandwidth of
the low-input-resistance configuration is almost constant
while the high-input-resistance design shows a considerable
reduction at higher values of Cd. The step response of the
amplifier with a capacitance of 4-7 pF added to simulate a
photodiode at the input is illustrated in Fig. 4, showing a
75 MHz response dominated by a Cf of 0-25 pF. Monolithic
fabrication of the circuit would obviously assist in realising its
bandwidth potential of 200 MHz by minimising Cf to a value
closer to 01 pF.
Design studies aimed at improving the performance of the
high-input-resistance designs used in the experimental comparison for higher source capacitance produced serious gain
peaking unless substantially faster transistors displaying an
increased fT in excess of 10 GHz were used in the second and
EL-DIWANY, M. H., ROULSTON, D. J., a n d CHAMBERLAIN, S. G.: ' D e s i g n
of low-noise bipolar transimpedance preamplifiers for optical
receivers', IEE Proc. G, Electron. Circ. & Syst., 1981, 128, pp.
MITCHELL, A. F., O'MAHONEY, M. J., and BOXALL, B. A. : 'PIN-bipolar
optical receiver using a high-frequency high-beta transistor', Electron. Lett., 1983,19, pp. 445-447
SIBLEY, M. J. N., and UNWIN, R. T.: 'Transimpedance optical pre-
amplifier having a common collector front end', ibid., 1982, 18, pp.
SIBLEY, M. J. N., UNWIN, R. T., SMITH, D. R., BOXALL, B. A., a n d
HAWKINS, R. J. : 'A monolithic transimpedance preamplifier for high
speed optical receivers', Br. Telecom Technol. J., 1984, 2, pp. 64-66
MEYER, R. c , and BLAUSCHILD, R. A.: 'A wide-band low-noise
monolithic transimpedance amplifier', IEEE J. Solid State Circuits,
1986, SC-21, pp. 530-533
DARWAZEH, i.: 'Fibre optic receiver design'. M.Sc. thesis, University of Manchester Institute of Science and Technology, 1986
WILSON, B., and DARWAZEH, I.: 'Transimpedance optical pre-
amplifier using a common base input stage'. IEE colloquium on
amplifiers, London, 1986, Digest 1986/94, Paper 7
Indexing terms: Semiconductor devices and materials, Power
semiconductor devices
We have observed a gradual degradation of the output
power not accompanied by drifts in the classical basic static
parameters of a GaAs power MESFET. We report in the
letter that this phenomenon can be explained by the development, during aging, of the gate-lag effect.
Fig. 4 Rise time of amplifier with Cd = 4-7 pF and Cf = 0-25 pF
Introduction: The two most important static parameters
which determine the output power (Po) of a GaAs MESFET
are: (i) the zero-gate-bias current, Idss, and (ii) the gate-todrain breakdown voltage, BVdgo} Such parameters are useful
ELECTRONICS LETTERS 12th February 1987 Vol. 23 No. 4
for the reliability engineer because until now every decrease in
Po appearing during aging was directly correlated to a
decrease in Idss2~5 or BVdgo.6tl In this letter we report life-test
results showing a decrease in Po not accompanied by drifts in
Idss or BVdgo or other basic static parameters. We describe the
electrical behaviour of the degradation and attempt to give
possible physical reasons.
Results: Life tests were conducted on commercially available
power FETs (1W; 12 GHz). 50 devices were supplied by one
manufacturer and issued from the same wafer. The active
layer was obtained by an Si implantation into an undoped
substrate. They were protected with a 3000A-thick plasmaenhanced chemical-vapour-deposited Si3N4 layer (PECVD),
formed at low temperature (250°C), after the fabrication of the
gate and ohmic contacts. Sets of ten devices were submitted to
unbiased and biased life tests, at channel temperatures ranging
A set of 12 basic static parameters8 was measured during
the entire aging experiment, together with a 'maximum' linear
output power (Po/), at 11 GHz, on a fixed tuned amplifier. The
studied sample was homogeneous and Pol was ~ 30 dBm,
obtained with a static drain current of 350mA (^IdsJ2), for
all the devices.
During aging (up to 1000 h), a gradual degradation of Pol
(up to 2 dBm) was observed in about two-thirds of the devices,
independently of the life-test conditions, and at the same time
all the static parameters remained practically unchanged.
The decrease of Pol was not due to some changes in the
fixed tuned amplifier: the output power of the unaged set of
devices which were kept as control samples did not vary
during the course of the experiment. However, we noted that
during the microwave characterisation performed after 1000 h
aging, the degradation of the output power was accompanied
by a decrease of the drain current / ^ [see Fig. 1(A)] and a
strong increase of a positive gate current Igs (5 to 10 mA)
under large-signal conditions. These values of Igs clearly
demonstrated that the gate was forward-biased. Therefore, the
following explanation can be given: as the quiescent level was
maintained at the same drain current, the dynamic drain
current was diminished due to a waveform clipping effect
(when the input power was abruptly switched off, Ids returned
to its static value of 350 mA). Such behaviour was not
observed before aging: (i) Ids remained stable or presented a
slight increase [see Fig. 1(») for Po > 26 dBm], indicating
that avalanche regions were reached; (ii) Igs stayed close to
zero with a negative value.
Regarding the aforementioned results, the output power
loss appeared to be due to a decrease of Idss occurring only
when the device operated under large RF signal conditions. In
other words, the /dss current available for microwave operation is lower than the static Idss current. This phenomenon
can be explained by the development, during aging, of the
gate-lag effect.
The gate-lag effect corresponds to a drain-current transient
in response to a voltage pulse on the gate with little drain-tosource voltage (Vds) variation. Although several research
2 300
output power, dBm
Fig. 1 Typical microwave characterisations
Drain current against output power: before aging (•), after 1000h
aging (A)
groups are studying this parasitic effect limiting the performance of GaAs devices, few results have been published
until now. However, the measurement principles and some
subsequent analysis have been reported by Rocchi.9
Fig. 2 Electrical schematic diagram of gate-lag measurement
Fig. 2 shows the electrical schematic diagram of the measurement we have performed on the FETs. The gate is
switched from the pinch-off voltage Vp to Vgs = 0, in the saturation region of the IdJVds characteristics (Vdd = 7 V). The gate
pulse width, tt, can vary in the range 1 ^s to several seconds
with 10% repetition rate. The drain current response is measured through a 1Q load.
Fig. 3a represents a typical drain current response of an
FET before aging. (Vp = — 3V and was measured at lds =
3 mA: ~ 1 mA per m 1 mm of gate width.) The static value of
^dss (700mA) is instantaneously reached; there is no gate-lag
5 ^J s /di v
Fig. 3 Typical drain-current responses
a Before aging
b After 1000 h aging
Fig. 3b represents an FET after lOOOh in a biased life test.
It showed a 1-5 dBm decrease in Poi and, moreover, the
occurrence of the gate-lag phenomenon: the drain current
switched partially on, from Ids = 0 to Ids =* 600 mA, and then
lags to the static value of Idss (700 mA) with a time constant
~15/zs. A difference of ~ 100 mA is thus found between the
static and the transient values, and it is obvious that lds ca
600 mA is the maximum drain current available for microwave operation.
To investigate more extensively this degradation, we have
made the following measurements: the IdJVds characteristics
have been vertically scanned, at successively Vds = 3, 7 and
10 V, by performing gate-lag measurements from Vp to — 2 V,
Vp to - 1 V, Vp to 0. The difference SI^ between the static
value and the transient value of Ids was measured at each time.
A transient IdJVds characteristic can be then deduced. Fig. 4 is
a schematic representation of the results obtained for the FET
illustrated in Fig. 3b. These results clearly show that almost
all the lag effect (70 mA) is given between Vgs = — 1V and
Vgs = 0. This confirms the lowering of the drain current in the
upper part of the IdJVds characteristics.
Discussion and conclusion: Before aging, there is no gate-lag
effect and the high-frequency excursion will therefore follow
the device static characteristics as represented by the solid
lines in Fig. 4. Thus AB represents the dynamic load line.
After aging, the static characteristics remain unchanged, but a
ELECTRONICS LETTERS 12th February 1987 Vol. 23
No. 4
gate-lag effect is observed which diminishes the dynamic
excursion available to the RF signal (broken lines in Fig. 4).
As the static bias point O is maintained and the measurements made in the same fixed tuned amplifier, the gate will be
forward-biased and a waveform clipping effect will appear
when the device operates beyond A'.
IRVIN, j . c : 'The reliability of GaAs FETs', in DI LORENZO, J. V.,
and KHANDELWAL, D. D. (Eds.): 'GaAs FET principles and technology' (Artech House, Dedham, MA, 1982), Chap. 6, pp. 349-400
DUMAS, J. M., LECROSNIER, D., and BRESSE, J. F.: 'Analysis of surface-
induced degradation of GaAs power MESFETs', IEEE Electron
Device Lett., 1985, EDL-6, pp. 192-194
ZANONI, E.: 'Gate metallization sinking into the active channel in
Ti/W/Au metallized power MESFETs', ibid., 1986, EDL-7, pp.
DUMAS, j . M., PAUGAM, j . , and LE MOUELLIC, c.: 'Evidence of detri-
mental surface effects on GaAs power MESFETs', Electron. Lett.,
1982,18, pp.1094-1095
CANALI, c , FANTINI, F., UMENA, L., and ZANONI, E.: 'Degradation
mechanisms induced by temperature in power MESFETs', ibid.,
1985, 21, pp. 600-601
FUKUI, H.: 'Determination of the basic device parameters of a
GaAs MESFET', Bell Syst. Tech. J., 1979, 58, pp. 771-797
ROCCHI, M. : 'Status of the surface and bulk parasitic effects limiting
the performances of GaAs ICs'. Proceedings of European Solid
State Devices Research Conference, NOBLANC, J. P., and ZIMMERMANN, j . (Eds.): (North-Holland, Amsterdam, 1985), pp. 119-138
Fig. 4 IDS/VDS characteristics
Solid lines represent device static characteristics before and after
aging. Broken lines deduced from gate-lag measurements
Gate-lag effect appeared during aging
Indexing terms: Semiconductor devices and materials, MOS
Radiation-hardened CMOS/SIMOX devices have been produced by combining SIMOX with a newly developed lateral
isolation structure. Even after exposure of these devices up to
2 Mrad(Si) of gamma-ray irradiation, they exhibit sufficient
operational characteristics.
It is the first time we have observed the occurrence of the
gate-lag phenomenon on power FETs during aging.
When the gate-lag effect is observed immediately after processing, it has been shown to be linked to slow surface states.
These states could be induced by free ions in the dielectric
coating or deep traps in the disordered region close to the
GaAs surface in the access regions.9 In fact, we have verified
that the gate-lag effect disappears after etching of SiO2 or
RF-sputtered Si3N4 layers on various devices supplied by different manufacturers. The same result is obtained after 100 to
200 h of ~150°C without bias, all connections of the transistors being short-circuited, f This last experiment, which
demonstrated that the effect can be reversible, strongly suggests that mobile ions are involved.
However, in the case presented in this letter, with PECVD
Si3N4 and after aging, the effect is nonreversible, although the
measured time constants (10 to 50/is) agree with those
observed after processing.9! Owing to the complexity of the
device pattern (multigate geometry, a second dielectric level,
crossover metallisations), we were unable to etch the Si3N4
layer and drive further the failure analysis; however, the degradation mechanism is certainly correlated with the surface
treatment and Si3N4 deposition conditions.
We may thus conclude that: (i) absence of the gate-lag effect
after processing is not a reliability warrant for the FET user;
(ii) the gate-lag measurement is a recommended means of
characterising an FET during reliability investigation.
Introduction: Many kinds of SOI technologies are being
widely studied, especially because of their promising characteristics for the production of latch-up-free, high-packingdensity and radiation-hardened LSIs. In terms of radiation
hardness, CMOS/SOI devices have two major advantages
over conventional CMOS/bulk devices; these are: (i) elimination of radiation-induced latch-up and (ii) reduction of
single-event upset rates. However, to produce a radiationhardened LSI, there are two major problems in CMOS/SOI
devices that need to be solved, i.e. back- and side-channel
leakage currents produced by ionising radiation in n-channel
This letter describes the structure of the radiation-hardened
CMOS/SIMOX devices produced by combining SIMOX1
with a newly developed lateral isolation structure and the
electrical characteristics of these devices after irradiation with
a 60Co gamma-ray source.
Device structure: Cross-sections of n- and p-channel
MOSFETs/SIMOX are illustrated in Fig. 1. The vertical isolation structure that was developed for the «-channel
MOSFET comprises multilayers of highly oxygen-doped
polysilicon and buried oxide, which were formed by oxygen-
1st December 1986
Centre National a"Etudes des Telecommunications
22301 Lannion, France
* On leave from ESEL, University of Bordeaux 1, 33405 Talence,
DILORENZO, J. v., and WISSEMAN, w. R.: 'GaAs power MESFET's:
design, fabrication, and performance', IEEE Trans., 1979,
MTT-27, pp. 367-378
2 DAVEY, j . E., and CHRISTOU, A. : 'Reliability and degradation of III-V
semiconductor devices', in HOWES, M. J., and MORGAN, D. V. (Eds.):
'Reliability and degradation' (Wiley, UK, 1981), Chap. 5, pp.
t DUMAS, j . M. : Unpublished results
ELECTRONICS LETTERS 12th February 1987
Vol. 23
highly oxygen - doped
poly- Si
buried oxide layer
Fig. 1 Schematic cross-sections of radiation-hardened n- and p-channel
Radiation-induced positive and negative charges are indicated by
' + ' and ' —' marks, respectively
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