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Although the worst case delay of this circuit seems to be
due to the eight series-stacking PMOS transistors ( C O ,Go, PI,
GI, P , , G , , P , and G,), nMOS transistors with gate inputs P I ,
P , and P , in the pull-down part actually help the fast charging of the C, node because P I , P, and P, are all high in this
case. This is shown by dotted arrow ‘ A in Fig. 36). (Similarly,
the fastest charging path of the C, node is shown by dotted
arrow ‘B’.) PMOS transistors with gate inputs PI, P , and p 3
in the pull-down part are inserted in parallel with nMOS
transistors with gate inputs P I , P , and P,, respectively to
boost the conductance of the charging path and provide the
full swing. The proposed 4 bit carry look-ahead circuit
requires only 32 transistors including output inverters, compared with 56 transistors of the conventional case, which is a
significant reduction of transistor count and chip area.
The proposed 4 bit carry look-ahead circuit was used to
design a 32 hit CLA. We verified the proposed 32 bit CLA
using an HSPICE circuit simulator with 1.5pm CMOS model
parameters and compared its results with the conventional
CLA (Table 1). Input operands were FFFFFFFF and
Worst case delay
Number of
transistors for
carry look-ahead
Total number
of transistors
00000000 with input carry, which corresponds to the longest
delay. It is shown that the proposed CLA not only has fewer
transistors but also faster speed compared to the conventional
scheme, which is again due to the reduction of chip area.
C IEE 1993
1Sth March 1993
Y.-T. Lee,
Park and C.-M. Kyung (Dept. of Electrical Engineering, Korea Advanced Institute of Science and Technology, 373-1
Kusong-Dong, Yusong-Gu, Taejon 305-701, Korea)
and ESHRAGHIAN, K.: ‘Principles of CMOS VLSI
design’ (Addison-Wesley Puhishing Company, 1985)
2 GONCALVES, N. F., and DE MAN, H. J.: ‘NORA: A racefree dynamic
CMOS technique for pipelined logic structures’, IEEE J . SolidState Circuits, 1983, SC-18, pp. 261-266
3 HWANG, I. s., and FISHER, A. L.: ‘Ultrafast compact 32-hit CMOS
adders in multiple-output domino logic’, l E E E J . Solid-state Circuits, 1989, SC-24, pp. 358-369
WESTE, N. H. E.,
quantised forms is required. An example of such a system is
the time interleaved architecture, which has been used to
obtain high sampling rates in, for example, analogue to digital
conversion (ADC) systems [ 13. However, because of problems
associated with timing jitter, the maximum potential of the
interleaved architecture has not been realised using allelectronic techniques [l]. Optics, on the other hand, is advantageous in realising very high speed and parallelism, with very
low jitter and isolation from electronic switching transients.
Using optical clock distribution, levels of jitter of under 400fs
have been reported [2]. This Letter describes a fully integrated 250 Msample/s optically triggered sample and hold
circuit (OS/H) intended for use in optically controlled, interleaved signal processing applications. The OS,” is fabricated
in a 0.5pm gate length, 20GHz fT, - 1.OV threshold GaAs
MESFET process.
P h o t o d e t e c t o r s : An appropriate photodetector to use in this
application is the metal-semiconductor-metal (MSM) photodiode [3], because of the ease of integration in a standard
GaAs MESFET foundry process [4], high speed and large
active area. An MSM with an electrode spacing and finger
width of 4pm, and an active area of 60 x 60pmZ has been
used, allowing for easy illumination using a 50pm core multimode optical fibre. Samples of these devices have been fabricated and tested by illumination with CW laser light revealing
a responsivity of 0.2A/W a t a wavelength of 830nm. In addition, the waveform resulting from pulsed measurements at
250MHz is comparable to that obtained using a standard
700 MHz electro-optic convertor, suggesting an upper frequency limit for this photodetector well in excess of 250 MHz
and agreeing with results obtained by other researchers using
similar devices [4].
Circuit d e s i g n : Various attempts have been made to achieve
effective optoelectronic (OE) sampling. A simple approach is
the Auston switch [5], which employs a photoconductive
device (such as an MSM) as a series analogue switch, hut the
speed of this circuit is severely limited due to the large
R,, Cbld time constant, and the slow, zero-field turn-off determined by the thermal recombination of the carriers.
An alternative approach involves the embedding of photodetectors in high speed electronic circuitry. For example in
Reference 6, MSM detectors fabricated on an InP substrate
were connected to a balanced current-steering bridge S/H
circuit. This discrete component model operated successfully
at 20 Msample/s. Although the diode bridge circuit has the
advantages of high speed and cancellation of the pedestal 111,
practical implementation is dillicult because it requires ideally
four optical addresses configured as two complementary pairs.
In this Letter, we describe an OS/H requiring fewer components than the bridge circuit and in particular, only one
optical address. This circuit, which is based on a single
MESFET geometry (20pm gate width, 0.5pm gate width), is
shown in Fig. 1, and consists of a MESFET (Jl) operated in
the triode region as a series analogue switch. By applying an
almost constant bias voltage to the MSM photodetector, the
Indexing terms: Photodiodes, Optoelectronics, Sample and
hold circuits
A novel, optically triggered, fully integrated sample and hold
circuit (OS/H) is described, and measured resuls are presented which demonstrate operation of this circuit at
cJ E D 1
slow recombination process observed in the Auston switch is
avoided. The photocurrent is driven through the variable
cascode current source consisting of J3 and 54. When the
photocurrent is larger than I , , the voltage at the drain of 53
(and hence the gate of J I ) rises abruptly. This has the effect of
turning JI on, and allowing Choldto charge to the input
voltage. The gate-source junction of J1 is prevented from
becoming forward biased by the source follower 52 and the
diodes D I and D2. Charging the gate-source parasitic capacitance C, of J I causes clock feedthrough, resulting in a pedestal at the output, but this is minimised by the clamping
network formed by 52, D I and D3. When J1 is switched off,
5, falls to two diode drops (about - 1.4 V, set by DI and D3)
below the voltage on C
The V,. swing of J I , and hence the
pedestal appearing at the output, is therefore independent of
the input signal level and appears as a small DC offset on the
output. The gate-drain parasitic capacitance C,, of J I will
charge and discharge through the input source without having
any significant effect on the output. The ON resistance of a
20pm gate width MESFET (with 5, = OV, Ka = 2.5V) is
-250R, as opposed to the 20-40kR of the Auston switch,
and so with C,,,, = 0.75pF a sampling rate in excess of
250 MHz is possible.
The output is buffered by the circuit of Fig. 2, which is
scaled to provide a 50R output impedance. The design of this
detectors are positioned at least 5Wpm away from the electronic circuitry. The IC is gold-wire bonded to a 400MHz
ceramic package and all D C supplies are decoupled using
surface-mount capacitors. A 250 MHz pulse generator driving
a 30mW, 830111x1 laser diode provides the optical clock, which
is coupled to a 50pm core, multimode fibre. The measured
operation of this circuit with a 50 MHz sinusoidal input signal
sampled at 250 Msample/s is shown in Fig. 4. This shows that
the OS,” is capable of adequately charging the 0.75 p F hold
V D D = 5v
Fig. 4 Measured response of OSIH with 50 M H r input (upper trace)
sampled at 250 Msamplels (lower trace)
capacitor within an acquisition time of 2.4 ns, and the sampled
signal is held with levels of pedestal and droop below
10mV. The measured acquisition time approaches the pulse
generator risetime, suggesting that higher sample rates are
possible with a faster optical drive. The low levels of pedestal
and droop allow a resolution equivalent to about seven bits
for an input signal of 1 V peak to peak, and measurements of
the analogue bandwidth up to 400MHz show a flat response.
Fig. 2 GaAs MESFET unity gain buffer
buffer is complicated by the fact that GaAs MESFETs exhibit
a frequency dependant drain conductance [I]. In a simple
follower circuit this causes the response to a step input to rise
by, 15% over a period of a few milliseconds. T o overcome
this problem, bootstrap feedback is employed. SPICE simulations predict a -3dB bandwidth for these units of - 7 G H z
and measurements up to 5OOMHz support this. The time
domain response of the buffer in response to a 0.5 V peak-topeak square wave input at 50 Hz was measured and shows no
measurable trace of the slow transient effects.
Fabricated ICs and measured results: A photomicrograph of
an IC consisting of two complete OS/Hs is shown in Fig. 3.
The IC measures 2.17 x 1.4mmz, contains 104 MESFETs and
consumes a total power of -0.6W. T o prevent the optical
clock from interacting with the electronic devices, the photo-
Fig. 3 Photomicrograph oJintegrated OSIH
ELECTRONICS LETTERS 29rh April 1993 Vol. 29 N o . 9
Conclusions: A fully integrated GaAs optoelectronic S/H
circuit has been designed, fabricated and evaluated experimentally. The measured results show that sample rates in excess of
250 Msample/s are possible, with levels of pedestal and droop
which are compatible with a resolution of about seven bits.
This OS/H is intended to form the basis of an optoelectronic
solution to the problem of timing errors in high-speed interleaved sampled data systems.
A c k n o w l e d g m e n t : This work was supported by the United
Kingdom Science and Engineering Research Council (SERC).
0IEE 1993
4th March 1993
R. Mason and J. Taylor (Department of Electronic and Electrical
Engineering, Uniuersity College, Torrington Place, London W C l E
7JE, United Kingdom)
wave ~ e c h i o l . ;i99i, LT-9,(3), pp. 341-345
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