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Let the transconductance parameter and the threshold voltage of
M I to M3 be K and V,, respectively. The voltages V , and V , in
Fig. I can be given as
VI - V D =
(2)
f VT
range up to a . 8 V with a nonlinearity error of less than 2%. The
total harmonic distortion of the output voltage was also evaluated
and it is found to be less than 1% for IV, - V21< 0.6V and VI - V,
= 0.8V. The simulated -3dB bandwidth was -12MHz.
Table 1: Aspect ratios of devices in Fig. 1
Devices
p l - M l p - M 6 p r M 8 p ” i - M ” l IMBI-MBI
130/10 15/50
110/30
1200/10
m ] l L b ] 150/10
The voltages V , and V , are the drain and source voltages for transistors M , and M S . respectively. This will keep the drain-source
voltages of M , and M8 constant, which is proportional to the difference between V I and V,. According to eqns. 2 and 3, the difference between the drain currents of M,and M8 will be proportional
to the product of the drain-source voltage and the difference of
their gate voltages. This will result in the multiplication operation
as follows. The difference between the drain currents Id, and Ids in
Fig. 1 can be given as
Id7 - I d 8
= K7(v3 - V4)(VD
VS) = K7(V3 - V4)(vl - &)
(4)
where K, is the transconductancc parameter of M, and M S . The
output voltage V, of this multiplier can be expressed as
Vo = (Id7
Ids)RL = R L ~ ; ( V
- ~V4)(Vl
VZ) (5)
To guarantee linear operation for this circuit, the following constraints should be satisfied:
niax(K,%) < V c + J ~ + V ~ - V ~ i + m i n ( ~(6), ~ )
where VT7is the threshold voltage of M,. Because transistors M ,
and MEare biased with equal source-substrate voltages, they need
not be built in individual wells, which will result in a saving of
chip area.
10
05
0 5
0 0
v1- v2
,v
10
m
Fig. 2 Simulated truns/er curves of multiplier with VI - V, = S . 8 V,
M.2VandRL=lkR
Conclusions: A low voltage CMOS four-quadrant multiplier is presented. SPICE simulation results show that for a power supply of
f1.5V the differential input range is over H . 8 V with a linearity
error of less than 2%. The total harmonic distortion is less than
1% with input range up to K10.6V.The simulated -3dB bandwidth
is about 12MHz. This multiplier is expected to be useful in many
analogue signal processing applications.
0 IEE 1994
28 September 1994
Electronics Letters Online No: 19941427
S.-I. Liu (Department of Electrical Engineering, National Taiwun
University, Taipei, Taiwan 10664, Republic of China)
References
s.c., and GEIGER, R.L: ‘ A f 5 V CMOS analog multiplier’,
IEEE J. Solid-State Circ., 1987, SC-22, pp. 1143-1 146
PENA-FINOL. I., and CONNELLY, J.A.: ‘A MOS four-quadrant analog
multiplier using the quarter-square technique’, IEEE J. Solid-State
Circ., 1987, SC-22, pp. 106&1073
LIU, s.I., and HWANG, v.s.: ‘CMOS four-quadrant multiplier using
bias-offset crosscoupled pairs’, Electron. Lett., 1993, 29, pp. 17371738
LIU, s.I., and HWANG, Y.s.: ‘CMOS four-quadrant multiplier using
bias feedback techniques’, IEEE J. Solid-Stute Circ., 1994, SC-29,
pp. 756752
RAMIREZ-ANGULO, J.: ‘Highly linear four-quadrant analog BiCMOS
multiplier for 21.5 V supply operation’. Proc. IEEE Int. Symp.
Circuits and Systems, 1993, pp. 1467-1470
KIMURA, K.: ‘A bipolar four-quadrant analog quarter-square
multiplier consisting of unbalanced emitter-coupled pairs and
expansions of its input ranges’, IEEE J. Solid-State Circ.. 1994,
SC-29, pp. 46-55
COBAN. A.L.,and ALLEN. P.E.:‘Low-voltage four-quadrant analogue
CMOS multiplier’, Electron. Lett., 1994, 30,pp. 104&1045
LIU, s.I., and CHANG, c.c.: ‘CMOS subthreshold four-quadrant
multiplier based on unbalanced sourced-coupled pairs’, to be
published in I n l . J. Electron.
VISWANATHAN,T.L.: ‘CMOS transconductance element’, Proc.
IEEE. 1986.14. DO. 222-224
10 TSIVIDIS. Y P.: ‘O&ation and modeling of the MOS transistor’
(McGraw-Hill,New York, 1988)
QIN.
Fabrication of submicrometre
parallelogramic-shaped gratings in SiOp
Ming Li, J.C.H. Lin, M.J. Cherrill and S.J. Sheard
Vi - V, changes from -0.85 to 0.85V
DC sweep ( V , - V,)
0 -0.8V
0 4.2v
0 0.2v
0.8V
lndpxing terms: Gratingfilrers. Reucrive ion etching
Simulation results: The following simulation results are obtained
using SPICE together with 2pm p-well process parameters and
MOSFETs with V , = 0.99V, Vr, = 4 8 V , K. = 6.13pAN2, K, =
25.9@V2, 8. = 0.15V-’ and 8, = 0.4V-’. The aspect ratios for all
transistors in Fig. 1 are listed in Table I. The simulation conditions are R, = Ikn, I, = 24.4pAA,IA = OSlpA and the power supply is f1.5V. The following simulations are obtained with the
substrate of all nMOS transistors being connected to the most
negative power supply. Fig. 2 shows the transfer curves of the
multiplier circuit. This multiplier has a linear differential input
2126
The fabrication process of submicrometreparallelogramic-shaped
gratings is reported, which involves an image reversal resist
process and a novel oblique reactive ion etching (RIE)
configuration. A submicrometre parallelogramic grating with 40”
blaze angle is fabricated using this method.
Introduction: Recent study has revealed that gratings with parallelogramic profiles can provide the optimum performance for
waveguide grating couplers [I]. Parallelogramic gratings also have
potential application in grating-coupled surface-emitting (or GSE)
lasers [2].The fabrication of gratings with rectangular or trapezoidal profiles has been widely studied, whereas the fabrication of
submicrometre parallelogramic gratings still remains to be investigated. In this Letter, we report our recent experimental results on
ELECTRONICS LETERS
8th December 1994
Vol. 30
No. 25
the fabrication of submicrometre parallelogramic gratings in SiO,
waveguides.
Fabrication process and results: To fabricate a submicrometre parallelogramic grating it is necessary to generate the partly undercut
profile which forms part of the grating teeth. Resist erosion and
material redeposition, however, hinder the formation of the undercuts. To solve this problem Boyd et al. (31 have proposed a modified RIE process by tilting the sample within a so-called cathode
Faraday cage. A thin, stiff metal mask is employed to avoid the
obvious shadowing problem created by a thick mask and to
reduce mask erosion.
residual photor
a
1-1
1pm rn
Fig. 2 SEM photograph of photoresist grating shadow-coated with AI
b
Image IS taken after 0, plasma
0 7 Dlasrna
C
e
losing the grating contrast. The process, proposed by Anderson et
al. [SI for thick-photoresist holographic lithography, is used in our
experiments for this purpose. As illustrated in Fig. Ib-e, a grating
sample with residual resist (Fig. l a ) is shadow-coated at an angle
of -60" with a thin layer of AI such that only the tops of the grating teeth are covered (Fig. Ib). The residual photoresist is then
removed using a 30s oxygen plasma (Fig. I C ) . Fig. 2 illustrates an
SEM picture of the grating at this stage. A 100 nm-thick layer of
metal is then evaporated normal to the sample surface (Fig. Id),
and the lift-off is finally carried out using solvents such as acetone.
Fig. le shows the schematic diagram of the resulting metal grating.
d
r
Fig. 1 Schematic diagram for fabrication oJ~parallelogramicgratings
a Fabricate gratings in photoresist using holographic exposure
6 Shadow-coat sample with AI
c Remove residual photoresist using 0: plasma
d Coat sample normally with 0.1 pm AI
e Metal lift-off and RIE at an oblique angle
f Stnp off AI, resulting in parallelogramic grating
The schematic diagram for the fabrication of submicrometre
parallelogramic gratings is illustrated in Fig. I. A grating pattern
is recorded using holographic exposure (Fig. l a ) , then the grating
is transferred into a thin layer of metal by lift-off as shown in Fig.
Ib-e, finally the grating is transferred into the substrate using an
oblique RIE process (Fig. l e ) discussed below and the metal layer
is stripped off (Fig. If).
As a metal mask is necessary for the fabrication of the parallelogram gratings, the resist grating needs to he transferred into a
metal layer. To obtain a successful metal lift-off (refer to Fig. Ibe) it is essential to produce an undercut resist profile following the
holographic exposure. Therefore, we employ an image-reversal
process, developed by Moritz [4], in which a reactive amine is
added to positive photoresist. This amine reacts with the resist in
the exposed regions during a post-exposure bake, rendering them
insoluble in the developer, and a subsequent flood exposure allows
development of the previously unexposed regions giving a reversed
image. Thus, 2 - 5 % (in weight) of imidazole is fully desolved in
the Shipley S1400-17 positive photoresist, which is then spincoated onto the substrate at 4000 revimin, and prebaked for 2min
at 85-90°C giving a film thickness of -0.5pm.The sample is
exposed to grating fringes by two-beam interference using an Ar'
laser with an output wavelength of 457.9nm, and then baked
again at -100°C for -40min. The exposed regions of the photoresist are now insoluble in the developer due to the reaction with
the imidazole, and subsequent flood exposure allows us to develop
the unreacted resist, leaving a reversed image. This image-reversed
grating has a tooth profile narrowing from top to bottom (i.e.
undercut), which is ideal for subsequent metal liftoff.
To obtain a metal grating mask, 100nm-thick AI is then evaporation-coated onto the sample surface, and acetone is employed to
lift-off the metal. However, using this simple process, we have
found that the success rate is very low (less than 30%). On some
samples, large areas of AI film were found to peel off. This may be
caused by the poor adhesion between the AI and the substrate due
to the presence of residual resist in the grating grooves. To solve
this problem the residual photoresist must be removed without
ELECTRONICS LElTERS
8th December 1994
Hl p r n
sa
Fig. 3 SEM photograph of parallelogrami~grating made on SiO,
Next. the grating is to be transferred into the SiO, substrate to
form a parallelogramic grating. To obtain oblique etching, a specially-designed Faraday cage is attached to the RIE cathode. The
vertical sides of the cage are made from stainless steel, and the
open top is covered with a stainless steel mesh (with a mesh count
of 4mm ') which forms an angle of 45" with respect to the horizontal base of the cage. The Faraday cage is electrically tied to the
cathode, and hence there is a field-free region inside the cage. The
presence of the Faraday cage deforms the shape of the plasma,
such that the ions are accelerated normal to the mesh surface;
passing through the mesh and the field-free region without changing direction. Because the sample is placed horizontally, the ions
arrive at the sample surface at an angle, leading to the desired
oblique directional etching. Fig. 3 shows an SEM picture of a
grating fabricated by using the proposed process. It is evident that
the grating has the desired parallelogram shape with a blaze angle
of -40". The details of the RIE process are shown in Table 1.
Here the 0, helps to oxidise the AI to form a stiff mask. The etch
Vol. 30
No. 25
2127
rate of SiO, was found to be -0.01 p d m i n with the Faraday cage.
Table 1: Details of RIE process for SiO, etching
Gas content
R F power
DC bias
Pressure
Temperature
CHF3(8sccm)+O,(Ssccm)
+Ar (8sccm)
50m torr
Conclusion: The process for the fabrication of suhmicrometre parallelogramic-shaped gratings has been established. A thin metal
grating mask, which is essential for the formation of the desired
grating shape, is made by a combination of an image-reversal
resist process and a delicate lift-off process. The oblique reactive
ion etch is achieved using a specially designed Faraday cage with a
slanted stainless steel mesh. A 0.65pm-pitch parallelogramic grating with a 40’ blaze angle is successfully fabricated using this
method.
Acknowlrdgmenf: This work is supported by the UK Science and
Engineering Research Council under the LINK Optoelectronics
project SOPHI, and one of the authors, Ming Li, would like to
thank the British Council for an Overseas Research Student
Award. The authors would also like to thank B.M. Annaratone
and J.E. Allen for helpful discussions.
degradation is observed for high hit rates which cannot be tolerated in systems needing converters to he cascaded.
To overcome this extinction ratio degradation and consequently
the BER degradation in optical routing and switching systems, a
new type of AOWC based on SOAs in a Mach-Zehnder interferometer (MZI) using optical crossphase modulation has been proposed and demonstrated at first in hybrid form [5]. A more stable
and compact monolithically integrated version of such an MZI
AOWC was recently reported [6].
In this Letter we present the design, first realisation and static
characteristics of an optimised interferometric AOWC, the threeport MZI.
Device desrgn; To use the MZI configuration for wavelength conversion. i.e. to control the phase difference in the two interferometer arms optically, a certain amount of asymmetry is required in
the MZI. This can be achieved, for example, via different splitting
ratios in the splitters and combiners [5] or through asymmetric
biasing of the amplifier sections in the two parallel branches [6]. A
more effective and very elegant way to achieve the asymmetry
under optical control has recently been proposed theoretically [7]:
an additional input port is foreseen at one branch of a monolithically integrated MZI in order to have direct optical access to the
amplifier section of this branch alone. In this Letter the first
experimental realisation of such an improved integrated device,
the three-port MZI AOWC, is reported. A schematic view of the
three-port MZI when operated in the contradirectional configuration is depicted in Fig. I
0 IEE 1994
14 October 1994
Electronics Letters Online No: 19Y41443
Ming Li, J.C.H. Lin, M.J. Cherrill and S.J. Sheard (Department of
Enpineering Science, University of Oxford, Parks Road, Oxford OX1
3PJ. Unired Kingdom)
optical control of hodprobe input)
References
LI. M., and SHEARD. s J.: ‘Waveguide couplers using parallelogramicshaped blazed gratings’, Opt. Commun.. 1994, 109, pp. 239-245
MATSUMOTO, M : ‘Analysis of the blazing effect in second-order
gratings’, IEEE J. Quantum Electron., 1992, QE28, pp. 20162023
3 BOYD, G D , COLDREN, L.A, and STORZ, F G : ‘Directional reactive ion
etching at oblique angles’, Appl Phys. Lett., 1980, 36, (7), pp. 583585
4 MORITZ. H : ‘Optical single layer lift-off process’, I€E€ Tram.,
1985, ED-32, pp. 672476
5 ANDERSON.
E H , HORWITZ, C.M , and SMITH, HI.: ‘Holographic
lithography with thick photoresist’, Appl. Phys. Letr., 1983, 43, ( Y ) ,
pp. 874-875
I
2
Wavelength converter based on integrated
all-active three-port Mach-Zehnder
interferometer
M. Schilling, K. Daub, W. Idler, D. Baums,
U. Koerner, E. Lach, G. Laube and K. Wiinstel
Indexing terms: Semicunducror quunrum wells, Opticulfrequmcy
conversion
The realisation and first static results of a novel monolithic MachZehnder interferometer (MZI) wavelength converter configuration
in InGaAsP/lnP MQW technology is reported. The compact allactive three-port MZ1 device allows for effective improvement of
the onloff ratio up to 18dB (from 6 to 26dB) due to direct optical
access to one of the interferometer arms by an extra input branch.
This device is very attractive for high-capacity optical networks.
lnrroducfiont All-optical wavelength converters (AOWCs) exploiting the gain saturation modulation in semiconductor optical
amplifiers (SOAs) have now attained ultrahigh-speed performance
handling data rates up to 20Gbitis [ I 4 However, owing to a
tradeoff between onioff ratio and bandwidth an extinction ratio
2128
core)
-=---
p ( P u m P slgnal,data input)
m
Fig. 1 Schematic vien- of three-port M Z I wavelength converter when
operated in conrrudirrctronal configarution
Devicefabrication: Monolithic three-port MZls are realised on InP
substrate applying similar processing technologies as for interferometric Y lasers [8].All portions of the MZI contain the identical
active layer stack which is made from strained quaternary MQW
layers grown by low-pressure MOVPE. The lateral waveguide
structure of the MZI consists of a buried-ridge-stripe (BRS) configuration [9], formed by dry etching and MOVPE regrowth techniques (see, for example, [IO]). For the integrated MZI, separate
contact electrodes with a segment isolation > 50kR are formed to
allow proper biasing of the input and output branches 1-3 as well
as the two 1.2mm-long parallel arms 4 and 5 (see Fig. I ) . After
wafer processing the individual three-port MZI chips are prepared
by cleaving and are mounted on copper studs for characterisation.
The total length is only 3mm due to the very compact all-active
Y-junctions. An antireflective (AR) coating is applied on both end
facets of the device. The SEM perspective of a completed all-active
three-port MZI chip is shown in Fig. 2.
Results: The basic functionality as an integrated interferometer
has been verified first with the novel structure. An example of the
typical characteristic is shown in Fig. 3. When CW light is
launched into the input port 1 of the MZI the optical output
power on port 2 can be electrically controlled through different
biasing of the interferometer arms. More than 30dB variation in
ELECTRONICS LETERS
8th December 1994
Vol. 30
No. 25
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