Enhancing the efficiency of Carry Skip Adder using MBFA-10T K.Kumaran (Author) G.Anantha Bhanumithra Assistant Professor MVIT Puducherry, India Email:kumarank2030@gmail.com Student MVIT Puducherry, India Email:ananthjack38@gmail.com R.Rathi M.Mohana Priya Student MVIT Puducherry, India Email:mohanapriya.muniappan@gmail.com Student MVIT Puducherry, India Email:rathirabani24@gmail.com final output of the circuit is directly attached to VDD or VSS. It is also attached to ground through n-block and VDD through a p-block. In static CMOS, the NMOS transistors will pass logic low whereas the PMOS transistors will pass only high. Pass transistors can be either NMOS or PMOS [1]. The major difference between pass transistors and CMOS circuits are that the PMOS circuit will be networked with the supply voltage. But in case of pass transistors, a FET can pass the signal between the drain terminals and the source terminals. Abstract—The objective of this paper is to reduce the propagation time of carry skip adder(CSA) and also minimize the area by using MUX based full adder (MBFA-10T).The efficiency of the CSA has been improved by replacing the full adders with MUX based full adder circuit. Using this approach the delay, number of required transistors and the area has been diminished while comparing it to the existing one. The results are obtained after design, simulation and timing analysis was done using SPICE tool. From the results it shows that the transistors used in MBFA is only ten, which is less than that of the CMOS Full Adder (FA). Keywords— Carry skip adder (CSA), delay efficient, Area, reduction in transistor count, MUX based full adder. II. I. INTRODUCTION Adder circuit performs the binary operations. It performs the computations in computers and some processors. An adder generates both sum & also it generates a carry. If, value is obtained after addition exceeds the limit, then it will produce a carry. Depending on the total inputs given to the circuit, the adder can be isolated into half adder (HA) and full adder (FA). The half adder has two binary numbers which produces the sum and carry. The FA has three binary numbers where the third input is the carry in, which produces the carry out and sum. There are some complex adders which makes use of the HA and also FA circuit as the primitive block. Hence these adders act as a basic circuit of all the complex adder architectures. Full adder is the primitive unit of all arithmetic operations. It plays a vital role in ALU circuits. Hence it is important to boost the performance of FA, for enhancing the arithmetic unit performance. The Full adder will perform the computing operations by receiving the carry in and produces a 1 bit output and also it produces a carry out. When the final addition is too large, then it will produce a carry. By enhancing the efficacy of full adder, we can enhance the overall efficacy of the circuit. In this modern world, the necessity of all electronic devices is their speed, so it is important to consider the delay factor while designing a VLSI circuit. The delay factor should be very small to construct an efficient device using static CMOS and Pass transistors. Static CMOS circuits use both PMOS and NMOS transistors for their working. In CMOS circuits the c 978-1-5090-5913-3/17/$31.00 2017 IEEE ADDER In case of adder circuits, the rapidness of adding the numbers is given by the time interval required to promulgate the carry produced in one part to other. In a normal adder, the carry produced in one circuit is sequentially sent to other blocks. 84 Each block has to wait for its carry in. This takes much time to calculate the result. For this reason, the propagation time of carry is considered while designing an adder circuit. It should be as small as possible for the sake of improve the rapidity of the adder circuit. Ripple Carry Adder (RCA) uses multiple full adders connected in series with the view to add N bit numbers. Each FA will get two bits of data as inputs along with a carry in bit and produces the sum and carry. The carry that is produced at the end of each FA is provided as an input carry to other full adder circuits which are connected sequentially. Since the carry is propagated in a succession manner, the delay will be more. With the view to improve the delay efficiency of RCA and to enhance the quickness of the addition operation, CSA is used. CSA is an proficient and better adder [2] compared to RCA. It has less delay compared to that of RCA. It consists of a series of FA and a multiplexer. hence the total transistor used in Carry By-pass Adder can be reduced. III. PRIOR WORK In a normal CSA, the length of the RCA will have a great impact towards the speed and time delay of the carry skip adder. Many techniques have been suggested in order to minimize the delay factor of CSA. The technique used in [3] increases the speed of the CSA by using multilevel CSA and in [4], is by decreasing the time taken to promulgate the carry of the skip logic, the speed of the CSA is improved by replacing the 2:1 multiplexer with that of the AOI and OAI compound gates. The series of full adder forms the RCA. The CSA divides the entire block into individual block and propagates the carry from one block to another. The carry which is produced in one FA block will be propagated to other block and finally the carry out is produced. Fig. 2. Conventional 4-Bit FA IV. Fig. 1. Carry Skip Adder Architecture PROPOSED CARRY SKIP ADDER USING MULTIPLEXER BASED FULL ADDER The proposed model using MUX based FA is shown in Fig.2. The number of phases in an adder decides the total transistor for improving the speed of the Skip Adder. The Carry Look Ahead Adder can perform the additions fast. Because it can pre process the values. Thus it can decrease the propagation delay. But the logic circuit of CLA becomes very complicated when the number of bits to be computed is more than 4 bits. This paper aims at depreciate the time taken to promulgate the carry of CSA further by using a MUX based full adder instead of 28 transistors CMOS FA. The time taken to promulgate the carry of the CSA can be reduced by accelerating the carry of the FA circuit. Hence the 28 transistors CMOS FA circuit is replaced by MUX based Full Adder (MBFA). Fig. 3. 1 Bit CSA using MUX Based FA The MBFA consists of 10 transistors. By using the MBFA, the total transistors used to construct FA can be reduced and 2017 International Conference on Nextgen Electronic Technologies 85 Fig. 4. Multiplexer Equivalent Circuit Table 1.Full adder Truth Table Fig. 5. PROPOSED SCHEMATIC DIAGRAM FOR MBFA When the B value in the adder circuit tends to be 0, then the output from the sum will tend to be same to that of output from the second multiplexer. When the value of B tends to be 1, then the output of sum will be the NOT form of the second multiplexer. It generates the expression by changing the B value[5]. The expresion for FA is given by In MUX Based Full Adder, is designed using five identical multiplexers. Each multiplexer consists of two transistors. Thus it has 10 transistors. The CSK consists of another multiplexer. Hence a 1 bit CSK consists of 12 transistors which is less than that of the standard CMOS FA circuit. V. SIMULATED OUTPUT EXISTING MODEL: Sum = Aْْ = Ǥሺْሻ The truth table for FA is given in Table 1.The conventional CMOS based CSA consists of a succession of FA network and a skip logic circuit. The number of total transistors used to construct a CMOS Full adder is 28. CMOS circuit got its own drawback. When the input capacitance value increases, it also decreased the speed of the circuit. Hence the FA network in the CSK is replaced with that of the MUX Based FA. Fig. 6. 1 Bit CSK using normal FA PROPOSED MODEL: A normal VLSI circuit can consume power in three forms. Switching power is due to the capacitance charging and discharging actions. Short circuit power happens when the supply and the ground gets short circuited. Static power happens when the circuit is in ideal state. In the proposed CSA, the adder consumes fewer power compared to that of the CMOS adder, because there is no short circuit power. Fig. 7. 1 Bit CSK using Multiplexer Based FA 86 2017 International Conference on Nextgen Electronic Technologies There are many ways to analyse circuits. In the present work SPICE tool is used to analyze circuits. Using this transient analysis is implemented for the digital circuit. Using the Cool Spice tool, the simulated output of Proposed CSA with MUX Based Full Adder is obtained. The delay and the transistor count are estimated. It is observed that the power and the number of total transistors are found to be less than that of the CMOS Full Adder. VI. FUTURE WORK In this paper, MBFA is used to design the efficient 4-bit CSA. This can be extended for 8-bit and 16-bit Carry CSA. The speed can also be improved by introducing a full adder which has minimum delay. Thus the time taken to promulgate the carry of the Carry Bypass Adder can be decreased further and the speed can also be enhanced VII. CONCLUSION VI. The MUX Based Full Adder has increased the efficacy of the Carry Bypass Adder. The delay has been diminished as compared to the CMOS based full adder circuit. The number of total transistors has also been reduced. The simulation results are obtained and it is compared with the standard CMOS CSK. AREA OUTPUT I.EXISTING MODEL: VIII. REFERENCES [1] [2] Fig. 8. Existing Model Area [3] II.PROPOSED MODEL: [4] [5] Nidhi Tiwari, Ruchi Sharma, Rajesh Parihar, “Implementation of area and energy efficient Full adder cell,” IEEE International Conference on Recent Advances and Innovations in Engineering (ICRAIE-2014), May 09-11, 2014, Jaipur, India M. Lehman and N. Burla, “Skip techniques for high-speed carrypropagation in binary arithmetic units,” IRE Trans. Electron. Comput., vol. EC-10, no. 4, pp. 691–698, Dec. 1961. Vitit Kantabutra, “Accelerated Two-Level Carry-Skip Adders-A Type of Very Fast Adders,” IEEE TRANSACTIONS ON COMPUTERS, VOL. 42, NO. 11, NOVEMBER 1993. Milad Bahadori, Mehdi Kamal, Ali Afzali-Kusha, “High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels,” IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 24, NO. 2, FEBRUARY 2016 Bijoy Babu, Jamshid .M. Basheer, Abdelmoty .M. Abdeen,” Power Optimized Multiplexer Based 1 Bit Full Adder Cell Using .18 ȝm CMOS Technology,” IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 5, Issue 1, Ver. III (Jan - Feb. 2015), PP 29-35 eISSN: 2319 – 4200, p-ISSN No. : 2319 – 4197 Fig. 9. Proposed Model Area I. COMPARISON OF DELAY AND TRANSISTOR COUNT Comparison Table Structure CSA using CMOS FA CSA using MBFA Number of transistor 54 Delay(ns) Area of the circuit 11.16 2448um^2 938um^2 36 10.43 Table.2.Comparison of CSA using CMOS FA and CSA using MUX Based Full Adder(MBFA) 2017 International Conference on Nextgen Electronic Technologies 87

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