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ICNF.2017.7985990

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On trap identification in triple-gate FinFETs and
Gate-All-Around Nanowire MOSFETs using low
frequency noise spectroscopy
D. Boudier, B. Cretu
E. Simoen, A. Veloso and N. Collaert
Normandie Univ, UNICAEN, ENSICAEN, CNRS, GREYC
14000 Caen, France
bogdan.cretu@ensicaen.fr
imec
Kapeldreef 75
B-3001 Leuven, Belgium
Abstract—This paper brings a comparison of the traps
identified in triple-gate FinFETS and Gate-All-Around (GAA)
nanowire (NW) MOSFETs built with the same technological
process. Traps have been identified using low frequency noise
(LFN) spectroscopy, giving information on which process steps
may be improved in order to build better devices.
Keywords—SOI; Gate-All-Around; FinFET; nanowire; low
frequency noise; noise spectroscopy
I. INTRODUCTION
In this work triple-gate FinFETs and Gate-All-Around
(GAA) nanowire (NW) MOSFETs have been studied using
low frequency noise (LFN) measurements. Considering their
electrostatic performances these devices are considered as the
optimal solutions to answer to the International Technology
Roadmap for Semiconductors (ITRS) requirements in term of
CMOS technology downscaling [1]. The LFN spectroscopy is
used as a non-destructive diagnostic tool and provides
information about the traps located in the transistors [2]. It
allows to detect the process steps that can be improved in order
to improve the MOSFET processing. The devices have been
studied in the temperature range from 270 K to 320 K in order
to identify the traps that may deteriorate the transistors noise
performances while working at ambient temperature. This
paper presents the methodology of LFN measurements and
compares results on the identified traps of n- and p-channel
FinFETs and GAA MOSFETs.
II. DEVICES AND EXPERIMENTAL
The studied devices are imec (Belgium) triple-gate
FinFETs and GAA NW MOSFETs built for the sub 10-nm
technological node. They are fabricated on a Silicon On
Insulator (SOI) substrate and are made using nearly the same
technological steps. In this work, a comparative study of these
two types of devices is performed in term of LFN noise
performances. Each transistor has 5 fingers or nanowires of
about 22.5 nm height. The fingers and nanowires width is
20 nm, which gives a total gate width of WG,Fin = 325 nm and
WG,GAA = 425 nm for FinFETs and GAA, respectively. The
gate length is LG = 60 nm or LG = 250 nm.
The gate dielectric is made of a high-k oxide (HfO2) on top
of an interfacial SiO2 layer. Both layers are 1.5 nm thick,
giving an equivalent oxide thickness of EOT = 1.9 nm and a
surface gate oxide capacitance of Cox = 1.79·10-6 F/cm2. The
gate metal is made of EWF (TiN) and W-fill metal depositions.
Full devices details are available in [3].
Low Frequency Noise spectroscopies have been performed
on the devices described above. Measurements are made at
wafer level using a Lakeshore TTP4 probe station and biased in
linear operation regime with a drain-source voltage |VDS| =
20 mV. The temperature has been set from 270 K to 320 K
with 5 K steps with the help of liquid nitrogen and a Lakeshore
331 Temperature Controller.
Output noise voltage Power Spectral Densities (PSDs) Svout
have been measured with a HP 3562A Dynamic Signal
Analyzer and a home-made instrumentation based on a lownoise transimpedance amplifier. The input-to-output gains have
been measured and consequently one can obtain the input
referred gate voltage noise PSD Svg by dividing Svout by the
squared system gain. Moreover the system bandwidth
limitation is cancelled by using this method. The LFN spectra
have been studied and compared at constant drain current ID
values by adjusting the gate voltage VGS, thus identical Fermi
levels are reached for all temperatures.
III. LOW FREQUENCY NOISE THEORY AND METHODOLOGY
A. Low frequency noise model
The low frequency noise measurements are usually inputreferred to the gate noise voltage Svg power spectral density. In
the low frequency range it originates mainly from the resistive
parts of the transistor, i.e. the source and drain regions and the
channel. The LFN is generally due to the contributions of white
noise, flicker (or 1/f) noise and generation-recombination (GR)
noise. The white noise originates from the thermal noise and
the shot noise and is characterized by a constant level Kw in the
frequency domain. The flicker noise of level Kf may be due to
a carrier number fluctuations (ΔN model) [4], to a carrier
mobility fluctuations (Δµ) [5] or to a contribution of both
phenomena (ΔN+Δµ) [6]. It decreases following Kf / fγ, where γ
is a frequency exponent reflecting the uniformity of the gate
oxide traps concentration in the gate depth. Finally the
generation-recombination noise is the consequence of traps
(located in the gate oxide or in the depletion region, which is
978-1-5090-2760-6/17/$31.00 ©2017 IEEE
the silicon film for fully depleted devices) that randomly
capture and release channel carriers. Each GR phenomenon has
a corresponding Lorentzian in the frequency domain, i.e. a
plateau of level Ai followed by a 1/f2 decrease from the
characteristic frequency f0,i [7]. The total gate voltage noise is
the sum of these contributions as seen in
(1)
As seen in Fig. 1 Svg is often multiplied by f as it eases the
parameters extraction. Indeed the bumps top frequency
corresponds to f0,i, its extraction precision is easier on f·Svg
compared to Svg and then gives a higher precision on Ai
estimation.
As can be observed from Fig. 2, all devices are subject to
GR noise. The total noise seems to be higher in the n-channel
GAA with LG = 60 nm, as expected for smaller devices. By
comparing same geometry GAA and FinFETs devices, one can
observe that the noise level at 1 Hz is almost the same for nchannel devices while for p–channel devices seems to be
slightly higher for GAA transistors. The last frequency decade
exhibits the white noise contributions in the PSD.
B. Identification of silicon film traps using low frequency
noise spectroscopy
Once the Lorentzian contributions on the total noise have
been modelled using (1) one can trace the evolution of the
characteristic frequencies f0,i as a function of the gate voltage
VGS at a given temperature. The characteristic frequencies of a
single trap vary following an exponential law f0,i ∝exp(β·VGT).
Lorentzians for which the characteristic frequency is
independent on VGS (for β = 0) are located in the depletion
region (i.e. Si film) [8, 9]. Lorentzians for which frequency
varies with VGS with β in the range of 25-33 V-1 may be
attributed to interface traps [10]. However, due to the very thin
film thickness some traps located in the Si film may present
bias dependence of the Lorentzian characteristic frequency
with a lower exponential factor β, in comparison to reported
values for oxide traps [8]. Nevertheless characteristics
frequencies should vary with the temperature in both cases. In
this work only the first case (traps located in the depletion
region traps with β = 0) has been taken in account.
Figure 3 presents the variation of the Lorentzians
characteristic frequency with temperature (at constant ID),
which is highlighted by the black arrow. The inset presents the
evolution of these Lorentzians characteristic frequency with
VGS (at fixed temperature). One can notice that some points
seem to increase with the gate voltage (shown with red lines)
while others seem to remain constant (green lines).
Considering the estimated values of the exponential factor β
these Lorentzians may be attributed to oxide traps and silicon
film traps, respectively.
Fig. 1. The measured gate voltage noise PSD Svg (in black) has been
modelled (red curve) using the parameters in (1).
Fig. 2. Comparison of f·Svg(f) of different devices at the same temperature
and bias point (|VDS| = 20 mV and |ID| = 2µA).
Fig. 3. Evolution of the Lorentzians characteristic frequency with the
temperature at fixed drain current (ID = 2 µA). Inset: evolution of the
Lorentzians characteristic frequency with VGS at T = 310 K. Red lines show
VGS-dependant Lorentzians (traps in the gate oxide) while green lines
highlight constant Lorentzians (silicon film traps).
For Lorentzians that are associated to silicon film traps one
can identify the nature of these traps by performing a LFN
spectroscopy, i.e. studying the evolution of the characteristic
time constant τi = 1 / (2πf0,i) as a function of the temperature
for at constant drain current ID. The characteristic time constant
of a given trap is a function of the temperature following the
expression
(2a)
(2b)
with (2a) applying to n-channel devices while (2b) applies to pchannel devices [2]. EC, EV and ET are the conduction band
minimum energy level, the valence band maximum energy
level and the trap energy level, respectively. The constant q is
the elementary charge, kB is the Boltzmann constant, h is the
Planck constant, Mc is the number of conduction band energy
minima, me* is the electron effective mass (0.19 x 9.1·10-31 kg)
and mh* is the hole effective mass (0.56 x 9.1·10-31 kg). The
capture cross sections σn and σp stand for n- and p-channel
transistors, respectively.
Fig. 4. Arrhenius diagram of an n-channel GAA NW MOSFET using the
LFN spectroscopy. Three traps have been identified using (2a), their
parameters ΔE and σn are given in the legend.
Applying a linear regression on the Arrhenius diagram
points should give access to ΔE = EC-ET (or ΔE = ET-EV) and
σn (or σp), as seen in Fig. 4. On this graph three traps have been
observed and their parameters have been extracted using (2a).
The obtained values of ΔE and σ should be compared to
data in the literature in order to identify the physical nature of
the traps, their parameters having been found using other
measurements techniques such as Deep Level Transient
Spectroscopy (DLTS). In the case presented in Fig. 4 only the
nature of one trap has been clearly identified: T12 may be
related to Oxygen-Hydrogen vacancy (VOH).
Finally the effective (or surface trap) density Neff can be
extracted for each trap by plotting the evolution of its
Lorentzians plateau level Ai as a function of the characteristic
time constant τi. The expression
(3)
indicates that the Ai of a single trap must increase
proportionally to τi. Having a straight line consequently
confirms that all the points belong to the same type of trap.
Then Neff can be obtained from the slope of this line, knowing
the effective gate width W and length L. The volume trap
density NT can also be extracted knowing that NT = Neff·B/Wd
(Wd being the depletion width). However the value of the
coefficient B, which was usually around 1/3 for large and
planar devices, does not apply well for devices such as GAA
[9, 11]. Even if the repartition of the traps appears to be a
volume phenomenon, only Neff has been extracted in our work
as it requires no assumption on the value of B. This is
illustrated by Fig. 5 on which the characteristics Ai and τi of
identified traps of Fig. 4 have been plotted. The points fit to a
linear regression, which confirms all points of the same color
Fig. 5. Ai vs τi characteristics of the traps identified in Fig. 4. The good
linearity of the points confirms that they belong to the same trap and the
slope gives access to the surface trap density Neff.
originate from the same trap. From the slope the effective trap
densities Neff have been extracted.
C. Comparison of identified traps
Several devices have been studied using LFN spectroscopy.
Some Arrhenius diagrams have been grouped in Fig. 6 using
the same scale in order to facilitate the comparison. On all
transistors two to five silicon film traps appear in the PSDs.
The identified traps are summarized in Table I. For most of
the identified traps their nature have not been recognized.
Nevertheless the traps denoted T12 and T42 may be attributed
to VOH (Oxygen-Hydrogen vacancy) and T43 may be due to
V2H (Hydrogen divacancy). The latter can be explained by
unstable defects such as Frenkel pairs that recombinate or
evolve to a stable state, with Frenkel pairs being produced
The plots of Ai vs τi led to the estimation of the effective
trap density in the range 1011-1010 cm-2. These values are in the
same range as other studies on similar devices [12]. It can be
noticed that the n-channel GAA and FinFET with LG = 250 nm
seem to have a higher trap density, while the p-channel FinFET
appears to be less impacted.
IV. CONCLUSION
Several sub-10 nm multi-gate devices have been
investigated using low frequency noise spectroscopy. Using the
methodology described above silicon film traps located in the
Si film have been identified. Some of them, such as VOH and
V2H, are known while many other traps even if they appear in
different investigated GAA and FinFET devices are from
unknown nature. Dry etching and/or implantation damage
and/or selective epitaxial growth may be the process steps that
created the traps in the silicon film.
Fig. 6. Comparison of Arrhenius diagram of various transistors. The
complete parameters extraction is synthesized in Table I.
during the implantation step. Hydrogen related traps could be
due to the Hydrogen used during the selective epitaxial growth
of the raised source and drain.
Furthermore some traps appear in different devices, such as
traps with ΔE = 0.62 eV (T03 and T22) or 0.52-0.56 eV (traps
designed by * in Table I). These values of ΔE are obtained
using an automatic linear fit regression. Taking into account
the PSD measurement error (about 4%), the Lorentzian
parameter estimation error (less than 10%) and the σn or σp
variation in a range of about one decade and half, it may be
suggested that these ΔE = 0.52-0.56 eV values are related to
the same trap.
TABLE I.
SYNTHESIS OF PARAMETERS OF SILICON FILM TRAPS THAT
HAVE BEEN IDENTIFED USING LOW FREQUENCY NOISE SPECTRSCOPY.
Device
type
LG
Trap
nm
n-GAA
60
n-GAA
250
n-FinFET
250
p-GAA
250
pFinFET
250
T01 (*)
T02 (*)
T03
T04
T11
T12
T13 (*)
T31 (*)
T21 (*)
T22
T41 (*)
T42
T43
T44 (*)
T45 (*)
a.
ΔE
σn or σpa
Neff
eV
cm²
cm-2
K
0.54
0.53
0.62
0.50
0.67
0.32
0.52
0.53
0.54
0.62
0.53
0.32
0.47
0.56
0.52
1.1·10-14
5.8·10-16
1.0·10-14
4.4·10-17
5.3·10-13
2.2·10-17
2.1·10-14
2.1·10-15
9.2·10-16
7.5·10-14
5.6·10-16
1.3·10-17
2.9·10-17
4.1·10-14
4.2·10-15
12·1010
7.4·1010
17·1010
11·1010
24·1010
22·1010
99·1010
17·1010
14·1010
69·1010
5.2·1010
1.1·1010
9.7·1010
3.7·1010
4.7·1010
280-320
295-320
295-320
295-315
300-320
280-305
270-315
270-310
270-300
285-310
270-315
285-295
270-315
270-315
275-320
T range
σn and σp applies to n- and p-channel devices, respectively.
ACKNOWLEDGMENT
The devices studied in this work have been processed in the
framework of imec’s Core Partners Logic Program.
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