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ISIE.2017.8001323

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Control Scheme for a Cascaded Multilevel
Converter Used in Low-Voltage-Ride-Through Tests
of Grid-Connected Wind Turbines
Fernanda Carnielutti∗ , Benhur Tessele† , Jean de Paris‡ , Jorge Massing‡ and Humberto Pinheiro‡
∗ Power
Electronics and Control Research Group - GEPOC
Federal University of Santa Maria - UFSM, Campus Cachoeira do Sul, Brazil
Email: fcarnielutti@yahoo.com
† Grupo de Pesquisa em Automação e Sistemas - GPAS
Federal University of Santa Catarina - UFSC, Florianópolis, Brazil
Email: benhurzi@gmail.com
‡ Power Electronics and Control Research Group - GEPOC
Federal University of Santa Maria - UFSM, Campus Santa Maria, Brazil
Emails: jeanmdp.92@gmail.com, jorgemassing@gmail.com, humberto.ctlab.ufsm.br@gmail.com
Abstract— This paper describes the implementation of a control scheme for a symmetrical cascaded multilevel converter used
as a fault generator for low-voltage-ride-through (LVRT) tests of
grid-connected wind energy conversion systems (WECSs). The
converter is able to emulate the main faults that can happen
in real power systems, with no significant impact on the grid
during the LVRT tests. The proposed control scheme is divided in
two levels: a central unit and local controllers in each converter
power cell. The cells are composed of a back-to-back singlephase full-bridge converter and a local controller, a Digital Signal
Processor (DSP), that controls the DC bus voltage through the
grid-side converter and performs the modulation of the outputside converter. The central controller is also a DSP, that generates
the voltage references and the synchronization signals for the
power cells. Experimental results of LVRT tests are shown to
demonstrate the good performance of the converter and the
proposed control scheme.
I. I NTRODUCTION
The amount of installed wind power in constantly increasing
in many countries around the world. According to the European Wind Energy Association (EWEA), over 13GW from
Wind Energy Conversion Systems (WECS) were installed
across Europe during 2015, with Germany leading the market
[1]. As a result, Power System Operators (PSOs) are beginning
to require the active participation of WECS in the control
of the power system to which they are connected, in a way
such as their dynamic behavior more closely resembles that of
conventional synchronous generators. This task can be accomplished by modern WECSs, as the majority of commercially
available wind turbines are now connected to the grid via static
power converters, allowing variable speed operation and active
participation in the control of the power system to which they
are connected [2].
The control actions that WECS must perform in order
to actively take part in the control of a power system are
comprised of a list of operational requirements presented in
the grid codes of the PSOs [3]–[7]. Among the operational
l-)))
requirements first developed for conventional power plants
(hydro, thermal, etc.), and now being updated for wind power,
are reactive power compensation, primary frequency control
and low-voltage-ride-through (LVRT) capability, this last one
being one of the most important grid code requirements.
During certain types of faults in the grid, the WECS must
remain connected during a specific time interval, and, in some
cases, provide reactive support to help the reestablishment
of the system. For example, Fig. 1 shows the LVRT curve
presented in the German Grid Code [5]. The horizontal and
vertical axis represent, respectively, the time and the amplitude
of the peak line-to-line grid voltage.
In Fig. 1, the fault occurs at time t = 0. As long as the values
of the line-to-line grid voltages remain inside the blue area, the
wind turbine must stay connected to the grid. Inside the lightgray area, the turbine must disconnect, if there are instabilities
in the system. Note that, during a 150ms interval, even with
zero voltage, the turbine must stay connected. Other Grid
Codes present similar operational requirements, with LVRT
curves adapted to the specific characteristics of their respective
power systems.
As a result, wind turbine manufacturers must test and certify
the capacity of their WECS to withstand these operational
requirements. Concerning LVRT, there are four possible ways
to emulate faults in grid for tests of grid-connected wind
turbines [8]. Fault generators using a bidirectional two-level
rectifier/inverter is one of the possible ways to emulate the
faults, and have already been presented in literature [2], [9]–
[13]. However, as for conventional two- or three-level converters the number of levels in the output line-to-line voltages is
limited, large LC filters are needed at their output terminals,
and undesired interactions among the wind turbine controllers
and these filters may arise.
In this context, this paper describes the implementation of a
cascaded multilevel converter used to emulate faults in the grid
g
%Vll
100%
Must stay connected
Power Cell
A1
Limit 1
B1
15%
Must disconnect
Grid
Limit 2
t(ms)
0 150
700
1500
C1
Input 3Φ transformer
45%
di M
sc ay
on
ne
ct
70%
3000
A2
B2
Wind turbine
under test
C2
A3
Figure. 1. LVRT curve presented in the German Grid Code (VDEW, 2007).
for LVRT tests of grid-connected wind turbines. The converter
is able to emulate the main faults that can occur in real power
systems. As multilevel converters reduce the distortions in the
output line-to-line voltages, the output LC filter can be reduced
or even totally suppressed, mitigating its interactions with the
WECS under test.
The symmetrical cascaded multilevel converter presented in
this paper is comprised of three single-phase cells per phase.
Each cell is composed of a grid-side full-bridge rectifier, a DC
bus and a WECS-side full-bridge inverter, as shown in Fig. 2
(back-to-back configuration). Usually, symmetrical cascaded
multilevel converters have in their front-end non-controlled
rectifiers [14]–[16], as this configuration is easier to control.
The back-to-back topology was chosen in this work as, for
the LVRT application, power must flow from the grid to the
WECS and vice-versa. The proposed converter is a 100kVA
prototype, and is a first step towards the implementation of a
new testing system rated for higher powers
The control of the symmetrical cascaded multilevel converter is divided in two levels: a central unit and local
controllers in each cell, as seen in Fig. 3. The cell is connected
to the secondary of the transformer by a filter inductor Lf .
Both the central and local controllers are implemented with a
TMS320F28335 Digital Signal Processor (DSP), from Texas
Instruments. This is a simpler architecture when compared to
[17], for example, where, besides a central controller, the control of each power cell is achieved by means of an association
of a DSP and an FPGA. The proposed converter is a 100kVA
prototype, and is a first step towards the implementation of
a new testing system rated for higher powers, so that larger
WECS can be tested. The proposed control scheme will be
described in Section II of this paper, and Section III brings
experimental results to validate its performance. Finally, the
conclusions are drawn in Section IV.
II. D ESCRIPTION OF THE P ROPOSED S YSTEM
In this Section, the control levels presented in Fig. 3 are
described in detail.
A. Central Controller
The central controller is implemented with a
TMS320F28335 floating point DSP from Texas Instruments,
B3
C3
vag
vbg
Output
sensors
vcg
vcgf
vbgf
vagf
Figure. 2. Grid, symmetrical cascaded multilevel converter and wind turbine
under test.
sr1
iL
Secondary
of the
transformer
sr 3
s3
s1
Lf
Bypass
sr 2
sr 4
iL
vg
Power Cell
s2
vcc
s1 , s2 , s3 , s4
sr1 , sr 2 , sr 3 , sr 4
Local
DSP
SCIrx
SCItx
- Central DSP
Data Package
- Cell Data Package
SCItx
Figure. 3.
s4
Central
DSP
SCIrx
Central
Controller
Control system and communication protocols.
and is responsible for the overall control of the symmetrical
cascaded multilevel converter. It communicates with the
converter power cells through a bidirectional fiber optic
channel. The central DSP has three UART (Universal
Asynchronous Receiver/Transmiter) serial interfaces, and each
one of them is used to communicate with the three cells of a
given phase: phase a with UARTa, phase b with UARTb, and
phase c with UARTc. All UARTs from the central and the
local DSPs are set to a Baud Rate of 2.34MBd, the faster rate
allowed. The bytes in a package are transmitted and received
using the UARTs FIFO (First In, First Out) modules, as can
TABLE I
PARAMETERS FOR A LVRT TEST.
Central
DSP
UARTc
UARTb
UARTa
FIFORx
FIFORx
FIFOTx
FIFORx
FIFOTx
Before/after Fault Parameters
Description
Input value
Positive Sequence (SP)
0-100% of the grid voltage peak
Negative Sequence (SN)
0-100% of the grid voltage peak
Zero Sequence (ZN)
0-100% of the grid voltage peak
Grid Frequency
30-120 Hz
Angle
0-240o
Test total time
0-59min, 0-59s, 0-100 tens of ms
Fault Parameters During the Test
Description
Input value
Type of fault
Symmetric, asymmetric or phase jump
Positive Sequence (SP)
0-100% of the grid voltage peak
Negative Sequence (SN)
0-100% of the grid voltage peak
Zero Sequence (ZN)
0-100% of the grid voltage peak
Phase Jump Angle
0-240o
Fault duration
0-10000ms
FIFOTx
Cell A1
Cell B1
Cell C1
FIFOTx Local DSP FIFORx
FIFOTx Local DSP FIFORx
FIFOTx Local DSP FIFORx
Cell A2
FIFOTx Local DSP FIFORx
Cell B2
FIFOTx Local DSP FIFORx
Cell C2
FIFOTx Local DSP FIFORx
Cell A3
FIFOTx Local DSP FIFORx
Cell B3
FIFOTx Local DSP FIFORx
FIFOTx Local DSP FIFORx
Cell C3
Cell Data Package:
Byte 1
Byte 2
Address
DC Bus Status
Central DSP Data Package:
Byte 2
Byte 1
Address
COMP11
Byte 3
COMP12
Byte 4
COMP21
Byte 5
COMP22
Byte 6
CRC
Figure. 4.
Central DSP, Local controllers in each power cell and data
packages flow and configuration.
be seen in Fig.4.
The packages that the central DSP sends to the cells
contains six bytes, also shown in Fig.4: the cell address, the
comparators for the upper IBGTs s1 and s3 of the inverter
(each comparator is broken in two bytes - COMP11 and
COMP12 for s1 and COMP21 and COMP22 for s3 ) and a
CRC (Cyclic Redundancy Check) byte, used to check if the
package was corrupted during the transfer process. If the
CRC calculated by the cells upon receiving a package is
equal to the CRC that was sent, the cell proceeds to update
the control of the DC bus voltage and the modulation of the
inverter. If the CRCs are different, the local DSP awaits the
arrival of a new package.
The central DSP operates with a 12kHz frequency, while
the cells have two operating frequencies: 2kHz for the
inverters, and 12kHz for the control of the DC bus voltage
by the rectifiers. As a result, the data packages are not
sent to all the cells of a given phase at the same time, but
delayed, representing the phase angle for the Phase-Shift
(PS) modulation [18], that is, 60o in this case. The instant in
which a cell receives its associated package (FIFO receiver
interruption) is used to synchronize the cell to the central DSP,
resulting in the correct phase angles for the PS modulation.
This can be seen in Fig. 5, where the carrier of the central
DSP is shown, as well as the carriers for the cells of phase
a. Here, the arrows represent the FIFO interruptions for
the cells. On the other hand, the central DSP receives the
packages of the power cells, containing its address and the
status of the DC bus voltage, in an interruption associated to
that specific cell.
For the performance of a new LVRT test, the before/after
fault and during fault parameters, listed in Table I, are set
in the central DSP. This enters in Mode 1 of operation and
sends to all power cells a command for their rectifiers to
pre-charge their DC bus capacitors, while the inverters remain
inhibited. After a defined pre-charge period, the cells send
back to the central controller the status of their DC buses. If
all the DC voltages are correct, the central DSP changes the
mode of operation from pre-charge (Mode 1) to execution of
the LVRT test (Mode 2).
During Mode 2, the central DSP sends a command for
the cells to enable their inverters, while the rectifiers keep
regulating the DC bus voltages. The central DSP calculates
the voltage references for the inverter legs of the power cells
before, after and during the emulation of the fault in the
grid. The voltage references are obtained by means of the
carrier-based geometrical modulation described in [19], that,
together with the PS modulation, is able to cancel harmonic
components on the synthesized output line-to-line voltages.
When the LVRT test is completed, the central DSP enters in
Mode 3 (Idle Mode), and waits for another set of parameters
to perform a new LVRT test. It also inhibits both the rectifiers
and inverters of the cells, configuring them to stay idle in
Mode 3 and wait for a new test to be performed.
B. Local Controllers
The local controllers are also TMS320F28335 DSPs, and
are responsible for the control of the DC bus voltage by the
rectifier and for the PWM modulation of the inverter of each
cell. As previously stated, at the beginning of a new LVRT test,
the central DSP configures the cells through the UART/fiber
optic channel to enter in Mode 1 and perform the pre-charge
of their DC buses. When the receiver FIFO in the local DSP
receives an entire package, comprised of six bytes, it generates
an interrupt; the cell checks the CRC byte and the address. If
both are correct, the carriers of the rectifier (12kHz) and of the
inverter (2kHz) are synchronized to the central DSP, and the
local control actions are performed (regulation of the DC bus
voltage and update of the comparators for the inverter IGBTs).
After the DC bus voltage pre-charge period, the cells check
the value of the DC bus voltage and send to the central
DSP their addresses and the status of the DC bus; if all
voltages are correct, the central DSP commands the cells to
start performing the LVRT test (Mode 2), sending the data
Central DSP and
DSPa1 - 2kHz rectifiers - 12kHz
vgf1
Low-pass
filter
(.) 2
vgf2
-1
(.) 2
+
0º
+
vgf
¸
vdc2
60º
vdc2 ref
Notch
filter
2
vdcf
evdc2
+
-
C
2
uPI
PI
120º
Modulator
u ff
´
iref
vgf
ig
-
DSPa2 - 2kHz
Low-pass
filter
+
DSPa3 - 2kHz
vg
u
KP
-+
eig
Comp sr1 Comp sr2
Figure. 6.
Figure. 5. Carrier of the central DSP and of the rectifiers of the cells in 12kHz
and carriers for the inverters of the three cells of phase a, with phase-shift of
60o in 2kHz.
packages described in the previous Section. As already stated,
the inverter switches at 2kHz, and the carriers of the same
phase are phase-shifted of 60o , in order to cancel harmonic
components in the total output line-to-line voltages. Finally,
when the LVRT test is completed, the central DSP enters in
Mode 3, commanding the cells to inhibit both their rectifiers
and inverters. The cells and the central DSP enter in an idle
mode, waiting for a new LVRT test to be performed.
C. DC Bus Voltage Control
The control of the DC bus voltage, vdc , is performed by
the local DSPs of the cells, with a sampling frequency of
12kHz. The block diagram of the control is shown in Fig. 6,
where C is the capacitance of the DC bus capacitor. A signal
proportional to the square of vdc passes through a discretetime notch filter, designed such as to reject frequencies around
120Hz. The outer voltage loop is composed by a PI controller
with an anti-windup, resulting in the control action upi . The
grid voltage at the secondary winding of the transformer, vg ,
is measured and the synchronization signal is obtained by two
discrete-time second-order low-pass filters. The output of the
filters is then normalized, resulting in vgf [20]. The current
reference iref is obtained as the multiplication of upi and vgf .
The inner current loop was implemented by means of a
proportional controller, that transforms the current error eig in
the control action u. To compensate for possible disturbances
caused by vg , the normalized grid voltage vgf is added to
u in a feedforward action, resulting in uf f . This last one
passes through a modulator, where it is modified such as to
assume values between 0 and TPER (the maximum value of
the DSP carrier), resulting in the comparators Compsr1 and
Compsr2 for the rectifier IGBTs sr1 and sr3 (sr2 and sr4
complementary to, respectively sr1 and sr3 ).
Block diagram of the DC bus voltage control algorithm.
In the next Section, experimental results are given to demonstrate the good performance of the proposed system.
III. E XPERIMENTAL R ESULTS
This Section brings experimental results to demonstrate the
good performance of the system during LVRT tests. Fig. 7
shows the prototype of the symmetrical cascaded multilevel
converter. An equipment under test was connected to the
output of the converter through an LC filter with L = 0.9mH
and C = 15μF, in order to emulate a WECS. The DC bus
voltages of the cells were regulated to 100V. The modulation
index m for the pre and post fault intervals is equal to 0.9,
and the amplitudes of the phase voltages during the fault are
calculated according to [2]. The pre-charge period for the DC
bus voltages of the cells is defined as 5s. After this interval, if
all the DC buses are regulated to the correct voltage value, the
central DSP enables the inverters of the cells, and the LVRT
test is performed. The total time was defined as 3s, and, at
half this period, a fault in the grid was emulated, lasting 1.5s.
Fig. 8 shows the three-phase currents at the primary windings of the grid-side transformer, as well as the DC bus voltage
of one of the cells of phase a, during a complete LVRT test
for a B-Type fault (phase-ground). It can be seen that the
converter has a very low impact on the grid, as, during the
transient events of load connection and disconnection (when
the inverter is enabled after the pre-charge period) and during
the beginning and end of the fault (during the performance of
the LVRT test), the grid-side currents have limited transients.
The good performance of the DC bus voltage controller can
also be seen, acting fast during the transients to regulate the
DC bus voltage in the desired 100V value.
Regarding the voltages, Figs.9 and 10 show, respectively,
the phase voltages at the output of the multilevel converter
(vag , vbg and vcg in Fig.2) and on the equipment under test
(WECS), after the LC filter (vagf , vbgf and vcgf in Fig.2),
B1
A1
B2
B3
Power cell
and inductor
Central DSP
and RPI
A2
A3
C1
Figure. 9. Phase voltages at the output of the multilevel converter, showing
the transients at the beginning and end of a LVRT test for a B-Type fault
(phase-ground).
C3
C2
Figure. 7.
converter.
Implemented prototype of the symmetrical cascaded multilevel
Fault emulation
Pre-charge of the
DC bus voltages
Test
Figure. 8. Three-phase currents measured at the primary windings of the
grid-side transformer, and the DC bus voltage of one of the cells of phase a,
during a complete LVRT test for a B-Type fault (phase-ground).
Figure. 10. Filtered phase voltages on the equipment under test, showing
the transients at the beginning and end of a LVRT test for a B-Type fault
(phase-ground).
showing the transients at the beginning and end of the LVRT
test. Figs. 11, 12 and 13 show the same waveforms for a CType fault (phase-phase). In Figs. 10 and 13, it can be seen that
the voltages on the equipment under test are almost sinusoidal.
Fault emulation
IV. C ONCLUSIONS
This paper presented the implementation of a symmetrical
cascaded multilevel converter used for LVRT tests of gridconnect WECS. The converter emulates the main faults that
can occur in real power systems, and is comprised of three
single-phase cells per phase. Each one is made of a grid-side
full-bridge rectifier, a DC bus and a full-bridge inverter at the
output (WECS) side. The control is divided in two levels: a
central control unit and local controllers in each power cell.
Each local Digital Signal Processor (DSP) controls the DC bus
voltage through the rectifier and performs the modulation of
Pre-charge of the
DC bus voltages
Test
Figure. 11. Three-phase currents measured at the primary windings of the
grid-side transformer, and the DC bus voltage of one of the cells of phase a,
during during a complete LVRT test for a C-Type fault (phase-phase).
the inverter. The central controller is also a DSP, that generates
the voltage references for the inverters and is responsible
ACKNOWLEDGMENTS
The authors would like to thank the Power Electronics and
Control Research Group - GEPOC, of the Federal University
of Santa Maria - UFSM, and the National Counsel of Technological and Scientific Development - CNPq.
R EFERENCES
Figure. 12. Phase voltages at the output of the multilevel converter, showing
the transients at the beginning and end of a LVRT test for a C-Type fault
(phase-phase)
Figure. 13. Filtered phase voltages on the equipment under test, showing
the transients at the beginning and end of a LVRT test for a C-Type fault
(phase-phase).
for the synchronization of the converter power cells to the
central timer. Communication protocols were designed and
implemented to interconnect the control subsystems.
Experimental results were presented for the emulation of
B- and C- type faults. It was shown that the converter has a
very low impact on the grid, as, during the transient events
of load connection and disconnection (when the inverter is
activated after the pre-charge period) and during the beginning
and end of the fault (during the execution of the LVRT
test), the grid-side currents have limited transients. The phase
voltages on the equipment under test are almost sinusoidal,
due to the multilevel characteristic of the output voltages of
the symmetrical cascaded multilevel converter implemented.
The proposed converter is a 100kVA prototype, a first step
towards the implementation of a testing system rated for higher
powers.
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