T-Gate: Concept of partial polarization in Quantum dot Cellular Automata Chiradeep Mukherjee, Soudip Sinha Roy Dr. Saradindu Panda Department of Electronics & Communication Engineering University of Engineering & Management Jaipur, India {chiradeep.1234321, soudipsinharoy}@gmail.com Department of Electronics & Communication Engineering Narula Institute of Technology Kolkata, India saradindupanda@gmail.com Prof. Dr. Bansibadan Maji Department of Electronics & Communication Engineering National Institute of Technology Durgapur, India bmajiecenit@yahoo.com Abstract—Quantum Dot Cellular Automata (QCA) plays a pivotal role in the emerging field of Nano electronics as well as in digital finite state machine design arena. Several gates and their proposals exist in this field all of which are recognized for their own characteristics. Majority voter is one of the several schemes of QCA. In this paper, a new gate termed as T-gate is proposed which is validated by thirteen standard functions and two input multiplexer circuit which reflects the reduction in the effective area as compared to the realization of the same by earlier methods. The T-gate can function as a universal logic gate and also as an inverter which can be realized by using fewer numbers of cells. T-gate implementation of 2x1 Multiplexer require no wire crossings and shows noticeable reduction in the cell count. Keywords— T-gate, 2X1 Multiplexer, O-cost (Operation Cost), Area Utilization Factor (AUF) I. INTRODUCTION A s the dimensional scaling of CMOS is approaching its fundamental limit, several new alternatives are being explored like SET (Single Electron Tunneling), Spintronics, Ferromagnetic, Molecular and Quantum devices[1]. Quantum Dot Cellular Automata brings a new paradigm in quantum technology [2-3] which attracts the view, especially in the emerging areas of science & technology. The problem of leakage current has been avoided in this new area of science particularly when the dimensions are shrunk to the level of few nanometers and the operation of the circuit became much faster with the speed of hundreds of Giga Hertz. The Heat dissipation & Power consumption are next to negligible in the Quantum Cellular Automata which avoids the requirements of heat sink in the electronic circuitry. The fundamental nanostructure of Quantum Dot Cellular Automata (QCA) is a cell. A QCA cell comprises of four interacting quantum dots which are placed in the four corners of a square cell. Each of these dots is quantum mechanically coupled to each other by means of tunnel junction. The logical cell can contain two free electrons. When two excess electrons 978-1-5090-1422-4/16/$31.00©2016 IEEE are charged, then due to the Columbic force of repulsion, these excess electrons occupy diagonal position so as to maintain furthest position in a Quantum Cell [4]. Hence the alignment of the electrons is of two types and each of the alignment can be regarded as a polarization P=+1 or -1. Binary information is encoded by the configuration of this electrical charge [5]. The concept of clocked QCA cell is essential for functional gain and complex operation [6-11]. The clock influences the charge stored in a cell to propagate among the cells. This charge transfers takes place by means of Columbic force of attraction and repulsion. Majority gate is one of the most useful building blocks in Quantum Dot Cellular Automata. The disadvantage of majority gate is that it cannot be implemented as inverter and so it is not considered as a universal logic gate [12] and it is not used frequently because existing logic-synthesis tools cannot map the majority function [13]. Another interesting proposal to implement the basic logic circuits is And-OrInverter gate (AOI Gate) [13]. AOI gate has more flexibility with Computer Aided Design tools (CAD) as it can easily be mapped onto the logic-synthesis tools. Universal Logic Gate (ULG Gate) [14], a new model gives a logic box which takes m-input variables and explores n-Boolean functions. These Boolean functions are obtained by permuting the input variables. The ULG system always implements And-Or-Invert system which consists of two majority gate and one 3X3 grid. Though ULG reduction technique requires less wire crossings and it has lower latency, another improved version was introduced in [15] which is popularly known as Universal QCA Logic Gate (UQCALG Gate). In this paper a new logic gate named T-gate is proposed. The function of the logic gate is to implement both types of universal gates i.e. NAND and NOR gates. Though this T-gate is implemented and verified for the thirteen standard functions [11] and basic two-input multiplexer circuit, but it can also be used with majority voter with proper efficiency in terms of output energy. Rest of the paper is organized as follows: section II describes the functionality of T Gate whereas two important parameters Area Utilization Factor (AUF) and OCost are introduced in section III. This section shows the expression and layout of two-input multiplexer is shown in section IV whereas section V analyzes the results obtained in the preceding sections. II. PROPOSED T-GATE The proposed T-gate consists of five quantum cells. Basic block diagram and the schematic for T-gate are shown in the Fig.1. T-gate can be implemented by using four cells but one extra cell is added in the output section to improve the output polarization energy. The working principle of the T-gate depends on multiple neighbor interaction [16] [17]. The polarization of the target cell depends upon the input cell A and the input cell B as mentioned in Fig.1. The terminal cells are the two input cells (cell A and cell B), one output cell Y and the middle cell is the fixed polarization cell [18]. Here the polarization of the target cell and the working of proposed Tgate depend upon the polarization of the Fixed Polarization Cell or F-P cell. The F-P cell may be set at positive or negative polarization. The output of the T-gate depends mainly upon the F-P cell. From truth table of figure 2, it can be shown that the output is same whenever the two inputs are matched. Therefore the outputs for the two like inputs are just the inverted form of the inputs. The radius of effect for the entire work has been set at 65nm. As the two input cells fall within the radius effect of the target cell, the polarization of the target cell also depends upon them. The two input cells and the target cell form an inverter like structure. The influence of the F-P cell is superseded by the two input cells when they have same polarization value. So when the input polarization of the two cells matches, the output is an inverted one. Hence this segment can be regarded as inverter segment. Now according to the truth table as in Fig. 2 when the two inputs does not match for a NAND logic and NOR logic it can be observed that the output is 1 for NAND and 0 for NOR gate. This output polarization energy is managed by the polarity of the F-P cell that is copied towards the output or the target cell. As the two inputs have opposite polarization, their influence towards the target cell is cancelled out. Thus whenever the input polarization of the two input cells does not match the F-P cell polarization is followed on. This segment can be regarded as a buffer segment. The T-gate can behave as a dual gate, it can act like a NAND gate i.e. T+ gate or as a NOR gate i.e. T- Gate. The T-gate operates like a NAND gate when the F-P cell has positive polarization and like a NOR gate when the F-P cell has negative polarization. Fig. 1 T-gate cell layout and block diagram of proposed T-gate The Boolean expression for the gates considering two inputs A & B are: (1) (2) Fig. 2 .NAND and NOR logic truth tables Hence the T-gate acts as a Buffer segment when the input signals have different polarization and as an Inverter segment when input signals have same polarization. Fig.3 shows the superimposed waveform of the inverter section & the buffer section. Cells indexed by A, B and Y constitutes inverter segment of T Gate. This inverter forces the output to be inverted when the polarization of the inputs are different. X and Y labeled cells forms a buffer which boosts the energy of the input signal and passes the same to the target cell. Inverter dominates over buffer when input signals polarizations are same. Fig. 3.Inverter and Buffer segment influencing the output The equations (1) & (2) show that positive bias on F-P cell forces T-gate to operate as T+ gate and the negative bias on FP cell makes T-gate whose block diagrams are shown in Fig.4. Fig.4.T+ gate and T- gate T-Gate works as the NAND gate for positive bias and negative bias gives the output for the NOR gate. The output of the T-gate was found conforming to NAND gate logic for maximum polarization value of +0.43 for the F-P cell. Similarly for NOR gate the value is -0.43. The polarization value of 0.2 was found to be a stable operating point for the logic device. Entire transfer characteristics are shown in Fig. 5 where the region of T + and T- are clearly indicated. Polarization of fixed polarized cell is varied from -1 to +1 and against each point, output polarization has been considered. It is shown that at -0.43, output reaches at +1when the inputs are maintained at logic 0. Region of operations are clearly mentioned in the same figure from which decision of T-Gate, whether to act as NAND or NOR can be obtained. According to the paper by Yuhui Lu et al [18] a sine wave field which is a function of time can be provided as the clocking signal. Therefore a clipped signal can be used as a clocking signal to implement the QCA device with fixed polarization [2]. For the calculation of Area Utilization Factor (AUF) and Operational Cost (O-Cost), building block of each of the existing reduction techniques has been taken under consideration. Area Utilization Factor is defined as the ratio of effective area of the building block under consideration to the cell area (required to construct that basic building block for respective reduction techniques).Operational Cost can be defined as the number of cells in the active device. The rectangular area occupied by the cell-bed plane is effective area. In this work several basic building blocks which are available in QCA such as majority voter & inverter, And-OrInvert Gate, Universal Logic Gate (ULG2.0), (Coupled majority-minority) CMVMIN Gate, and UQCALG Gate are considered. Fig. 5.Operation of T-Gate III. QCA AUF (AREA UTILIZATION FACTOR) & O-COST CALCULATION In order to design QCA circuits, a method for representing the Boolean functions as optimally arranged circuit instantiating several reduction techniques are needed. In earlier work [19] it has been shown that all functions of three variables can be abstracted to thirteen standard functions as listed in the Table I [11]. With three binary variables, a total of eight minterms can be derived. Since each minterm corresponds to a vertex (point) of the Boolean cube, the three-variable Boolean function can be depicted as points on the same cube [11] [1921]. All three literals Boolean functions can be developed and implemented by means of these thirteen functions and that is why these functions are called standard functions. So to verify the functioning of the proposed T-gate it has been used to check the standard functions which ensure verification of all the Boolean functions. Standard functions are implemented in T-gate and then functions are compared with UQCALG [15], Majority Voter-Inverter (MV-INV) [11] and And-Or-Inverter (AOI) [13] reduction techniques as given in table I. Fig. 6.Effective area calculation for T-gate The AUF calculation of the T-gate becomes simpler by taking fig.6 into account. It is given as below: The length of active device= (1+18+2+18+1) nm2=40 nm2 The breadth of active device= (1+18+2+18+2+18+1) nm2=60 nm2, the effective area (At) of T-gate= (60X40) nm2=2400 nm2. So the Area Utilization Factor is given by: TABLE I-ANALYSIS OF EFFECTIVE AREA IN TERMS OF EFFECTIVE AREA OF T-GATE FOR EXISTING REDUCTION TECHNIQUES Boolean Function Average MV+INV Implementation MV INV EA AOI Implementation AOI EA UQCALG Implementation UQCALG EA T-Gate Implementation T-Gate EA 2 0 3At 1 5.12At 2 60At 3 3At 1 3 5 2 4 4 1 1 0 2 3 0 2 3 0 0 1.5At 9.5 At 15 At 3At 11At 13.5 At 1.5At 1.5At 1 2 3 1 2 3 1 1 5.12At 10.24 At 15.36 At 5.12At 10.24 At 15.36 At 5.12At 5.12At 1 2 5 3 1 5 1 4 30At 60 At 150 At 90At 30At 150 At 30At 120At 2 9 12 3 4 14 2 6 2At 9 At 12 At 3 At 4 At 14 At 2At 6At 3 4 3 3 1 3 2 3 7 At 13.5 At 9.5 At 12 At 2 3 2 2 10.24 At 15.36 At 10.24 At 10.24 At 1 4 1 2 30At 120At 30At 60 At 4 8 7 8 4 At 8 At 7 At 8 At 7.80 At 9.45 At 73.84 At 6.30 At If the T-gate effective area is taken as At, then table I shows the average effective area in terms of At for remaining reduction techniques [11] [13] [15]. The AUF of a design is important because the effective area is related to it. Hence, if AUF for a reduction technique increases then effective area also increases. For an ideal case AUF should be 1 as it depicts maximal utilization of cell-bed plane, reduction technique having AUF near to 1 entrusts VLSI designer in terms of effective area. AUF comparisons for several reduction techniques are given in Table II. TABLE II-AUF COMPARISONS FOR VARIOUS REDUCTION TECHNIQUES UQCALG 3.89 IV. MAJORITY 2.22 MAJORITY SEVEN CELL INVERTER 2.64 AOI T-GATE 5.42 1.851 SCALABILITY OF T-GATE WITH MULTIPLEXER DESIGN Conventionally majority NAND gate asks for a majority gate and an inverter whereas a T-NAND lowers the cell requirement than majority NAND. Similarly T-NOR gate is instantly identified by its lower O-Cost and AUF. Adders and multiplexers are elemental circuits for all processor based design on digital systems and circuits. In previous work [15] a universal logic feature of QCA gate structure referred to as UQCALG using CMVMIN (Coupled majority-minority) gate was introduced. The results displayed that UQCALG based QCA circuits were cost-effective in terms of number of cells as compared to the designs based on (Majority voter and Inverter) MI or ULG [11] [14]. Proposed T-gate based designs show improvement in the number of cells requirement as compared to the previous three design methods [11][13][15]. x Two input Multiplexer Using T-Gate Earlier design of two-input multiplexer [22] was designed using majority gates and the O-Cost was 29. Using T-gate the total cell area and the number of cells can be reduced drastically. Applying T-gate in place of the majority gate the required cells to design 2x1 multiplexer is 16. Hence it is found that in certain functions or Boolean expressions the utilization of T-gate in place of majority gate is quite expedient. The expression for two-input multiplexer is (3) Fig. 7 Block diagram and layout of two-input multiplexer implemented in QCADesigner [27] The proposed multiplexer of figure 7 excels earlier designs in all the fields and shows a reduction of 44.4% in the cell count in comparison to the best designs by Roohi et al [23] and R. Chakrabarty et al [22]. Figure 7(b) shows the multiplexer circuit designed by T gate. The proposed T-gate two-input multiplexer is compared with the recent designs presented in [7] [22-26] in terms of effective area and O-Cost. The effective area of two-input multiplexer using T-gate is 21769nm2. No wire crossing is used in the circuit shown in figure 7(b) and the output for the T-Gate two-input multiplexer is evaluated using two clock zones which indicate minimal complexity. Table III shows reduction in effective area and the corresponding improvement when T-Gate multiplexer is compared to the earlier proposed designs. TABLE III- COMPARATIVE ANALYSIS OF 2:1 MULTIPLEXER IN TERMS OF EFFECTIVE AREA Sl. no. 1 2 3 4 5 6 7 Multiplexer Design Effective Area in nm2 T. Teodosio et al.[25] K. Kim et al.[24] M. Askari et al.[26] C. S. Lent et al.[7] R. Chakrabarty et al.[22] A.Roohi et al.[23] Proposed T Gate V. OCost Improvement in Area compared to Proposed TGate 82.12% 121764 75 45924 41 52.59% 40764 34 46.59% 40714 - 46.53% 28124 - 22.60% 28124 27 22.60% 21769 16 - RESULTS & DISCUSSION Proposed T-Gate has bipartite structure consisting of an inverter and a buffer. As inverter consists of three cells out of which two cells have strong influence upon the target cell, the noise immunity of the T-Gate is enhanced .When the polarization range of fixed - polarization cell becomes a major factor, analysis shows that T-Gate works properly within the wide range of F-P cell polarization starting from 0.1 to 0.43 irrespective of the nature of polarization. A useful parameter termed as Area Utilization Factor (AUF) is introduced which includes both effective area and the cell count of the entire layout. From table I an average of 6.30X2400nm2 (6.30At) area for T gate implementation of standard function has been observed which shows improved result compared to the same using Majority Voter-Inverter, AOI, and UQCALG reductions. As processor contains multiplexers as the fundamental blocks, T-gate is used to implement the two input multiplexer block. Worthy improvement in effective area and O-Cost is observed when T-gate is used in two-input multiplexer. It shows O-Cost of 16 from figure 8 and requires effective area of 21769nm2 which indicates sharp 22.6% reduction in effective area when compared to the design proposed by Roohi et al. In other words the high speed quantum tunneling within a fewer number of cells provides an opportunity to the device to work with a better performance. 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