This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. IEEE JOURNAL OF SOLID-STATE CIRCUITS 1 A Tri-Slope Gate Driving GaN DC–DC Converter With Spurious Noise Compression and Ringing Suppression for Automotive Applications Xugang Ke, Student Member, IEEE, Joseph Sankman, Member, IEEE, Yingping Chen, Student Member, IEEE, Lenian He, Member, IEEE, and D. Brian Ma, Senior Member, IEEE Abstract— Targeting on electromagnetic interference (EMI) regulation and ringing suppression issues in automotive applications, this paper presents a gallium nitride (GaN)-based dc–dc converter operating at 10 MHz. A spurious noise compression technique compresses and re-distributes spurious switching noise within a defined frequency sideband, achieving EMI noise reduction at main switching frequency and its harmonics. Meanwhile, a tri-slope gate driver is designed to control voltage and current slew rates of GaN switches for effective ringing suppression, which is adaptive to load and input voltage changes. Tailored for high switching frequency and high-efficiency operation, the dynamic level shifters achieve about 0.8-ns propagation delay and near-zero quiescent current. Fabricated in a 0.35-µm Bipolar-CMOS-DMOS process, the converter accomplishes an EMI noise reduction of 40.5 dBµV and suppresses VSW ringing by 79.3%. The converter retains above 60% efficiency over 96.6% of its 6-W power range, with a peak efficiency of 85.5% at 1.5-W load. Index Terms— Electromagnetic interference (EMI) regulation, gallium nitride (GaN) power converter, ringing suppression, spurious noise compression (SNC), tri-slope gate driving (TSGD). I. I NTRODUCTION I N RECENT years, high-frequency and high-density power converters have seen significant increase in automotive electronics. As power level keeps rising, size and thermal limits have made it perpetually challenging to the silicon technology-based solutions. Gallium nitride (GaN) technology, on the other hand, demonstrates a highly competitive performance as an alternative , . Fig. 1 provides a brief comparison between state-of-art silicon ,  and GaN power switches . With comparable voltage rating, a GaN FET demands much lower figure of merit (as the product of ON-resistance RDS,ON , and gate charge Q G ) and shows no reverse recovery current. Due to the low Q G , Manuscript received April 21, 2017; revised June 11, 2017 and August 2, 2017; accepted August 25, 2017. This paper was approved by Guest Editor Pui-In Mak. (Corresponding author: D. Brian Ma.) X. Ke, Y. Chen, and D. B. Ma are with the University of Texas at Dallas, Richardson, TX 75080 USA (e-mail: firstname.lastname@example.org). J. Sankman was with the University of Texas at Dallas, Richardson, TX 75080 USA. He is now with Texas Instruments, Dallas, TX 75243 USA. L. He is with Zhejiang University, Hangzhou 310027, China. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/JSSC.2017.2749041 it demands much shorter turn-ON transition times, including di /dt transition period (shown as t p1 in Fig. 1) and dv/dt transition period (shown as t p2 in Fig. 1). Hence, a GaN FET is inherently far superior to its silicon counterpart in terms of switching loss , allowing more efficient power conversion at high switching frequency f SW –. However, there are some challenges that severely degrade the performance and reliability of GaN power converters. First, compared to low f SW operation in silicon-based power converters, high- f SW operation in GaN converters incurs much more drastic di /dt and dv/dt transitions, which cause severe electromagnetic interference (EMI) noise. In a GaN converter illustrated in Fig. 1, high- f SW operation incurs highspeed transitions at switching node voltage (VSW ) and drain current (IDH ) of high side GaN FET M H . During the turn-ON switching of M H , VSW ramps up within nanoseconds –. The instantaneous current Ispike , which is much higher than the inductor current I L , is drawn from VIN , charging VSW up and increasing EMI noise. An input filter can reduce EMI , but it greatly increases system volume and cost. Moreover, high- f SW operation causes significant voltage spikes Vspike due to the parasitic inductance and capacitance at the source/drain of M H shown in Fig. 1. This could lead to GaN VDS breakdown or damage to the internal logic FETs. To suppress Ispike and Vspike , a series resistor is typically added at the gate , , as shown in Fig. 2. With a lower driving current (limited by RG ), the drain current IDS in M H takes a longer time to catch up I L , resulting in a longer di /dt transition period from t1 to t2 . Also, a longer time is required for VSW to rise to VIN (VDS of M H drops to zero) in dv/dt transition from t2 to t3 . The turn-ON switching loss PSW_MH in M H during di /dt and dv/dt transition periods is defined as PSW_MH = 1 VIN × I L × t × f SW 2 (1) where t is the overlap time from t1 to t3 in Fig. 2. After VSW reaches to VIN and VGH (VGS of M H ) exits from Miller plateau, a much longer charging time from t3 to t4 is required with RG , resulting in a high conduction loss in M H . In addition, the passive metal gate resistor could cause hot spot or thermal issues under a high driving current (with 0018-9200 © 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. 2 IEEE JOURNAL OF SOLID-STATE CIRCUITS Fig. 1. Brief comparison on silicon and GaN power switches. Fig. 2. Turn-ON switching loss comparison in M H w/o gate resistor RG . on-chip RG ), or cause a false turn-ON of M L when VSW rises (with off-chip RG ) which leads to shoot-through current in the power switches. Second, as f SW rises to several tens of megahertz, spurious switching noise at fundamental frequency ( f 0 ) and its harmonic frequencies (N f0 ) can no longer be handled effectively by a passive LC network or an active spur filter , , . Interleaved converters  reduce the spurs with harmonic cancellation effect, however, multiple inductors and complex clock/phase control are involved. Frequency hopping techniques  were also proposed, however, inevitable VO transient associated with instant changes of f SW narrows down the frequency hopping range and reduces its effectiveness. In this paper, an automotive-use GaN dc–dc converter is presented, which overcomes the EMI challenges in high- f SW operation. A spurious noise compression (SNC) scheme is This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. KE et al.: TSGD GaN DC–DC CONVERTER Fig. 3. 3 Block diagram of the proposed high- f SW GaN-based buck converter. proposed to compress and evenly redistribute the spurious noise within a defined frequency sideband f m , achieving significant EMI noise reduction at main switching frequency f 0 and its harmonics. In the meantime, a tri-slope gate driver is presented to control the slew rates (SRs) of IDH and VSW adaptively, and thus suppress the ringing at VSW . The remainder of this paper is organized as follows. Section II first introduces the system architecture of the proposed converter. Then, two key operation schemes—SNC and tri-slope gate driving (TSGD)—are introduced in due course. Section III presents the design of key circuit modules. The functionality and performance of the proposed work are verified by the experimental results in Section IV. Finally, we conclude this research work in Section V. II. S YSTEM A RCHITECTURE AND O PERATION S CHEMES A. System Architecture Fig. 3 illustrates the system architecture of the proposed converter. Two enhancement mode GaN FETs M H and M L are employed as power switches. To effectively drive the high side switch M H , a nA-I Q dynamic up-level shifter is utilized to transmit drive signals from low-voltage domain to high-voltage bootstrap (BST) domain, and a BST circuit is implemented to generate sufficiently high BST rail voltage (VBST ). To drive low side switch M L , a dual slew-rate gate driver is used to achieve a reliable turn-ON of M L , and meanwhile preventing a false turn-ON of M L during fast dv/dt transition of VSW . And a delay matching cell is developed to compensate additional delay introduced by the up-level shifter. A fixed dead time (tdead ) is ensured between the turn-ON of M H and M L to prevent shoot through. For a given VIN or I O , with an optimal fixed tdead , M L is turned ON when VSW crosses 0 V at the VSW falling edge. Moreover, a pulse-width modulation (PWM) controller is used to generate a proper turn-ON time and regulate an accurate output voltage. Rather than operating at a fixed f SW , the converter employs an SNC scheme to generate a clock signal Vclk , which randomly shifts the switching frequency within a sideband of f m . Meanwhile, a tri-slope gate driver charges VGH up at a variable current (I M ) which helps suppress the ringing effect adaptively. B. Spurious Noise Compression Fig. 4 describes the proposed SNC scheme. An envelope generator in Fig. 4(a) generates a triangular envelope signal VTR , as shown in Fig. 4(b). Meanwhile, a random noise (Vn ) source that is acquired from avalanche noise of the Zener diode D Z is coupled to the envelope signal. The common level of VTR is level shifted by Vdc , achieving a reference Vref (contains noise) as Vref = Vn + VTR + Vdc . (2) As shown in Fig. 4(b), when Vramp reaches Vref , the clock signal Vclk is flipped to “1”. After a fixed delay tpd , the switch S1 is turned ON to discharge Cr . A new switching cycle then starts. Here, a switching period TSW is defined as TSW = 1 Vref = . f SW Iramp (3) Since Vref is a function of Vdc , triangular envelope signal VTR , random noise signal Vn , Vramp hits Vref in a randomized way. Thus, TSW differs in each cycle. Here, Vdc and the dc voltage level of VTR determine main frequency f 0 of the converter. The envelope of VTR determines the frequency modulation band f m . When VTR goes higher, a longer time is required until Vramp reaches Vref . TSW becomes longer, and switching frequency f SW (1/TSW) goes lower. When VTR reaches to the highest point, Vref is at the peak value. At the same time, f SW reaches to lowest point ( f 0 − f m /2). Similarly, when This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. 4 Fig. 4. IEEE JOURNAL OF SOLID-STATE CIRCUITS SNC: (a) System block diagram. (b) Key operation waveforms. VTR goes lower, a shorter time is taken to charge Cr up to Vref , resulting in a smaller TSW . When Vref reaches to valley point, f SW achieves highest value ( f0 + f m /2). To achieve aperiodic distribution of the frequencies, the modulation period (Tmod ) VTR is defined as Tmod = N × TSW (4) where N is an integer. According to Carson’s rule described in  and , the total power of a signal is unaffected by the frequency modulation. Take sine wave with single tone frequency f0 as an example, the modulated signal Vmod (t) is expressed as Vmod (t) = A cos[2π f 0 t + β sin(2π f mod t)] (5) where f mod (= 1/Tmod) is the modulation frequency and β is the modulation index fm β= . (6) fmod In terms of Bessel functions of nth order ( Jn ), the Fourier transform of (5) is given by Vmod (t) = A n Jn (β) cos[2π( f 0 + n fmod )t]. (7) i=0 According to , the spur reduction or amplitude attenuation is defined as 1 2 1 (8) J (β) ≈ 2πβ . 0 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. KE et al.: TSGD GaN DC–DC CONVERTER Fig. 5. 5 (a) Noise spectrum comparison w/o proposed SNC scheme. (b) FFT analysis on Vin_n without/with SNC scheme. Thus, the extent of distribution or the power magnitude (peak value) of the spurs depends on the modulation index β. The higher the β value, the more evenly distributed the spectrum of the spurs. Since the modulated spur power density is concentrated and remains quite high by solely using the periodic triangular envelope VTR . Thus, a random noise signal Vn is at last employed to achieve an aperiodicity of the f SW and evenly distribution of spur energy. In this way, the generic expression of a frequency modulated sinusoidal waveform F(t) with VTR and Vn is given as t F(t) = A cos 2π f 0 t + kω (VT R (t) + Vn (t))dt (9) 0 where A is the amplitude of original signal, kω is a sensitivity coefficient of the modulating signal. Fig. 5(a) demonstrates spurious noise spectrum with and without the proposed SNC scheme. A fast Fourier transform (FFT) analysis of input noise Vn_in with and without SNC scheme is shown in Fig. 5(b). With an amplitude of VTR and Vn at 50 and 1.32 mV, respectively, a nearly 20-dBμV spur reduction is achieved at 10 MHz. Since the total power maintains constant, the spurious noise energy at f 0 and its harmonics (N f0 ) are compressed along frequency domain, resulting in effective EMI reduction. Spurious noise floor drops below the EMI standard limit, eliminating the need of an input filter. Moreover, in comparison with other frequency spread spectrum techniques –, the random noise acquired from Zener diode achieves a random distribution of fSW and evenly re-distributes spurious noise energy. C. Tri-Slope Gate Driving To mitigate VSW and IDH spikes during M H turn-ON transition and reduce high-frequency EMI noise, an adaptive TSGD scheme is presented. Instead of using fixed current (IGH ) gate driving, by sensing I O and VIN , three different driving currents I M1 , I M2 , and I M3 are determined correspondingly to provide a tri-slope charging profile of M H , as shown in Fig. 6. When VPWM goes high, VDH triggers high and is level shifted up to the BST domain by a nA-I Q dynamic up-level shifter. As shown in Fig. 6(b), after VGL goes low, VGH starts to get charged with a current of I M1 , which is proportional to −I O . At high I O with a low modulated I M1 , VGH charges from Vth to Vmp within a period of t p1 until M H enters the Miller plateau region. VGH is charged up to Miller plateau voltage Vmp as Vmp = Vth + Vov (10) where Vov is the overdrive voltage for M H . At this time, IDH reaches to the peak value of inductor current, I L ,peak . Given a gate charging current of IGH , the required charging time (t p1 ) is computed as (Cgs + Cgd ) × Vov . (11) IGH Hence, the SR of IDH can be modulated by adjusting the gate charging current IGH . When VGH is larger than Vmp , M2 turns on to increase the driving current by I M2 which is proportional to −VIN . At low I O with a high I M1 , a less charging time of t p1 ’ (<t p1 ) is modulated before VGH reaches Vmp . t p1 = This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. 6 IEEE JOURNAL OF SOLID-STATE CIRCUITS to the gate driving scheme using passive gate resistor RG , the TSGD completes much faster charging action in t p3 to ensure a lower conduction loss. III. C IRCUIT D ESIGN AND I MPLEMENTATION A. Spurious Noise Compression Clock Generator Fig. 6. M H turn-ON transition with adaptive TSGD. (a) System block diagram. (b) Timing diagram. In the second phase, VSW rises with a gate charge current of I M2 until VSW reaches VIN . When IDH rises higher than I L , VSW is charged up by IDH,avg = IDH − I L . (12) With a parasitic capacitance of CSW at VSW , the charging period (t p2 ) from t2 to t3 is defined as t p2 = CSW × VIN . IDH,avg (13) For low VIN , VSW is charged up to VIN earlier resulting in a shorter t p2 ’ (<t p2 ). In this way, the rising slopes of IDH and VSW are adaptively adjusted. The overshoot voltage spikes and ringing at VSW are greatly suppressed. With a controlled rising slope of IDH and a reduced current spike, the instantaneous current drawn from VIN is minimized, reducing high-frequency EMI noise that injected to VIN . Compared The circuit schematic of the SNC clock generator is illustrated in Fig. 7. To modulate f SW within a sideband, a triangular envelope VTR is generated as follows. A modulation capacitor, Cfm , is charged with a fixed current (Ib ) until it reaches the high reference voltage of V H . Then Cfm is discharged with the same current of Ib till it drops to the low reference voltage of VL , and then the new cycle starts. In this way, a triangular envelope waveform between V H and VL is generated. Random noise is produced from the avalanche noise in the Zener diode D Z , which is in series with a large resistor R Z . Compared to other on-chip noise sources, such as thermal noise generated by resistor or MOSFET, noise from Zener diode not only demonstrates a much higher intensity of noise level but also shows a weak relation with temperature , . The random noise is similar to white noise in nature and is coupled to the envelope signal VTR through capacitor CC . A wide-bandwidth source follower (A in Fig. 7) drives CC . The amplitude of Vn is small compared to VTR . Take 5% modulation range ( f m / f 0 ) as an example, the amplitude of Vn is only 3.1% of the amplitude of VTR (50 mV). Then, the common mode level of VTR is level shifted up with a dc voltage value which equals (I f × Rref ), achieving a reference voltage Vref . The difference between V H and VL determines modulation range ( f m ), while the dc portion of Vref determines f 0 . In the SNC clock generator, a ramp current that is defined by the voltage at Vb charges the capacitor Cr , and a saw-tooth ramp voltage is produced. Vramp hits the reference Vref , generating a clock signal Vclk (at the output of high-speed comparator CMP1) with randomly distributed frequencies over a sideband f m . The rising edge of Vclk triggers the turn-ON of M H , and f SW of the converter is modulated in the same way. To achieve effective EMI noise reduction over different VIN and I O conditions, the f m is adjustable by changing Ram . To achieve a higher f m / f 0 , a smaller Ram is selected externally. Since VTR + I f × Rref , (14) Vref = Ram with a smaller Ram and given VTR , the ac amplitude of Vref becomes larger, achieving a larger f m . The dc level shifting caused by VTR is compensated by an adjustable current I f , achieving a constant f 0 under different f m / f 0 . Typically, Ram is set at a low value to achieve a larger f m . This helps to compress the spurious noise over wide frequency band. B. Adaptive Tri-Slope Gate Driver Fig. 8 shows the circuit schematic of the adaptive tri-slope gate driver. The load current I O and input voltage VIN are detected by the inductor DC resistance and resistor divider, and then converted to respective sensing currents. The sensing This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. KE et al.: TSGD GaN DC–DC CONVERTER 7 Fig. 7. Schematic of the SNC block. Fig. 8. Schematic of the adaptive tri-slope gate driver. Fig. 9. (a) nA-I Q dynamic up-level shifter. (b) nA-I Q dynamic down-level shifter. currents are level shifted up from low-voltage rail to BST rail, achieving the currents of IOSNS and IVIN in high-voltage BST rail. The detailed operation was depicted in Fig. 6(b). During the turn-ON of M H , VGH starts to get charged initially with a current of I M1 , which is defined by the overdrive voltage (VOV,M1 ) in M1 VOV,M1 = R1 × (I B − IOSNS ) − Vth . (15) This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. 8 Fig. 10. Fig. 11. IEEE JOURNAL OF SOLID-STATE CIRCUITS PWM controller. Fig. 13. PCB test board. Fig. 14. Measured efficiency. Dual slew-rate low side gate driver. When VGH is further charged up until it reaches Vmp (Miller plateau voltage), detected by MT 2 , the second charging branch from M2 turns ON. The gate charging current is increased by I M2 , which is defined by the overdrive voltage (VOV,M2 ) in M2 VOV,M2 = R2 × (I B − IV IN ) − Vth . (17) If gm2 is the transconductance of M2 , then I M2 is defined as I M2 = gm2 × VOV,M2 . Fig. 12. Chip micrograph. If gm1 is the transconductance of M1 , then I M1 is defined as I M1 = gm1 × VOV,M1 . (16) With the charging current of I M1 , VGH first reaches to Vth of M H . When VGH goes higher than Vth , M H starts conducting and its drain current IDH rises up. Since I B is fixed, with a higher I O and sensing current IOSNS , VOV,M1 is smaller, resulting in a lower I M1 . Therefore, during the di /dt transition period (t p1 in the waveform), VGH is charged up with I M1 which is negatively proportional to I O (I M1 ∝ −I O ) to realize a modulated slope of IDH . (18) For high VIN and thus a large IVIN , a low I M2 is generated to reduce VSW rising slope, and suppress VSW ringing. When VGH rises above the Miller plateau region and goes slightly higher than 2Vth , V P3 is pulled down by MT 3 quickly to enable a large charge current I M3 from M P3 in the third charging branch. With a much larger charging current during t p3 period, VGH reaches to final value quickly to reduce the conduction loss in M H . C. nA-I Q Dynamic Up- and Down-Level Shifters High-speed level shifters are crucial for effective gate driving in high- f SW converters. However, conventional level shifters suffer from long propagation delay (>10 ns) or consume high static current from BST to ground , . At light load, the static I Q would discharge CBST when the converter This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. KE et al.: TSGD GaN DC–DC CONVERTER 9 Fig. 15. Measured VSW without/with proposed SNC scheme. Fig. 16. (a) Noise test setup and (b) measured noise spectrum w/o proposed SNC scheme. stays in sleep mode that involves no switching actions. When the converter returns to active mode, M H cannot be turned ON effectively due to a low BST voltage. M H can be damaged with a high RDSON under a high thermal generation. Thus, two nA-I Q dynamic up- and down-level shifters with complementary structure are proposed in Fig. 9. The proposed up-level shifter employs a latch-cell structure, which consists of high-voltage drain-enhanced MOS (DEMOS) Md5 , Md6 , and low-voltage nMOS Mn3 and Mn4 . When the input signal (IN_UP) goes high, Mn1 is OFF and Mn2 is turned ON to reset the latch by pulling down the drain of Md6 . Since the p-type transistor Md4 stays on with its gate connected to VSW , the source terminal of Md4 drops down until Md5 is turned ON. The drain voltage of Md5 is pulled high and the p-type transistor Md3 stays on with its gate tied to VSW . Thus, the output signal (OUT_UP) goes up to achieve an effective signal level shifting. Similarly, when IN goes low, Mn1 turns ON to pull down the drain of Md5 , and thus OUT_UP decreases. In the circuit, the cascaded LDMOSs Md1 and Md2 provide high-voltage isolation, and low-voltage This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. 10 IEEE JOURNAL OF SOLID-STATE CIRCUITS Fig. 17. (a) Measured V O ripple and (b) load transient w/o SNC scheme. Fig. 18. Measured VSW ringing suppression w/o proposed TSGD scheme. NMOSs Mn1 and Mn2 ensure fast driving and level shifting. Moreover, to block a direct discharging from VSW to ground, two DEMOS Md3 , Md4 are connected back-to-back with Mn3 and Mn4 . Also, two gate resistors are added for effective gate voltage overstress protection during a charged device model electrostatic discharge event. The up-level shifter consumes a static current of only 4 nA. To down-shift VGH to the low-voltage rail for tdead control, Fig. 9(b) presents a nA-I Q dynamic down-level shifter. Two p-type transistors M p1 and M p2 enable high-speed driving, and DEMOSs Mde1 and Mde2 withstand high voltage for fast level shifting. When the input signal (IN_DN) goes high, M p1 turns ON to pull up the drain of Mde5 . Since the nMOS Md7 stays on with its gate tied to VDRV , the output of this down-level shifter (OUT_DN) goes to high immediately. Similar operation occurs when IN goes low. Here, the high-voltage LDMOS Md7 and Md8 are connected back-toback with M p3 and M p4 to prevent a discharge from VBST to VDRV . With a similar latch-cell structure of DEMOS Mde5 , Mde6 , and pMOS M p3 , M p4 , a static current of only 2 nA is consumed. D. PWM Controller To achieve an accurate output voltage (VO ) regulation, a PWM controller is presented in Fig. 10. VO is regulated to a voltage which is defined by VREF and the feedback resistors (R1 and R2 ) at VFB . The PWM control scheme operates as follows. When VO drops and VFB < VREF , the output of error amplifier Vcomp goes up. A higher inductor sensing current (Isns ) is required to trigger the main comparator (CMP), and thus the inductor current (I L ) ramps higher to compensate VO drop until VO is regulated back. Similar regulation happens when VO ramps high. Since VFB > VREF , Vcomp goes lower, resulting in a smaller I L , and VO is regulated lower. In this way, an accurate VO is achieved. With the fixed frequency peak current mode control, the slope compensation (Islp ) technique is required to ensure the stability over wide operation ranges. With the help of the RS latch, the rising edge of This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. KE et al.: TSGD GaN DC–DC CONVERTER 11 Fig. 19. Measured VGH with proposed TSGD at different levels of I O and VIN . Fig. 20. Measured conductive EMI noise: (a) without SNC&TSGD, (b) only with SNC, and (c) with SNC&TSGD. clock (Vclk ) triggers turn-ON of M H . When I L ramps up, the sensed current Isns is combined with Islp , which is further converted to a voltage (VS ). Until VS goes higher than Vcomp , the RS latch is reset, and VPWM goes low to turn OFF M H . E. Dual-SR Low Side Gate Driver To control the low side GaN FET M L , a dual-SR low side gate driver is presented in Fig. 11. A higher turn-OFF SR is implemented with a large-size (120×) transistor Mpd , in comparison with a lower turn-ON SR with Mph . When M H turns ON, VSW rises up to VIN (12 V, nominal battery voltage) in nanoseconds –. Due to Miller capacitance Cgd of M L , and the parasitic inductance/resistance in the source/gate terminal of M L , the gate (G) of M L is pulled high at high VSW dv/dt transients. The gate voltage jumps higher than Vth of M L , and M L turns ON again, resulting in a large shoot-through current from VIN to ground. This either causes a destructive damage of both GaN FETs due to an unrestricted high current from VIN to ground, or a catastrophic collapse of VIN bus. Two approaches are implemented to solve the issue. First, the ON-resistance of Mpd (120×) is scaled much smaller to reduce the overall resistance from the G to source (S) of M L . Second, multiple bond wires are employed at the gate of M L to reduce the total parasitic inductance/resistance. Furthermore, with a separated source terminal (S R ) of M L , the gate drive loop is separated from drain–source current path of M L which carries a high current. This ensures an effective turn-ON of M L , and minimizes common source inductance to reduce switching loss. IV. E XPERIMENTAL V ERIFICATION A prototype of the proposed GaN dc–dc converter is implemented in a 0.35-μm HV Bipolar-CMOS-DMOS process. The chip micrograph is shown in Fig. 12, with an active die area of 0.86 mm2 , including a 0.6-nF BST capacitor (CBST ). The printed circuit board (PCB) test board is shown in Fig. 13. Two enhancement mode GaN power switches are placed closely to minimize parasitic inductance and resistance. This helps to achieve fast driving transitions and suppress gate voltage overshooting. A 470-nH inductor (L) and a 1-μF capacitor (C O ) are used in the power stage. Fig. 14 shows the measured efficiency, which peaks at 85.5% for a 12-to-5-V conversion, and at 82.1% for a 24-to-5-V conversion. The efficiency stays above 60% over 96.6% of its 6-W power range. With the tri-slope gate driver, VGH slope reduces as I O increases to suppress EMI at the expense of less than 0.8% efficiency. With the SNC scheme, the efficiency reduction is mainly caused by the variable I L and VO ripples. With a low ESR C O (<10 m) and a This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. 12 Fig. 21. IEEE JOURNAL OF SOLID-STATE CIRCUITS Measured V SW with different conditions of I O , VIN , and f m / f 0 . TABLE I P ERFORMANCE C OMPARISON modulation range f m / f 0 of 5%, a peak efficiency reduction is less than 0.2%. Figs. 15 and 16 show the measured VSW and noise spectrum without and with the proposed SNC scheme, respectively. In Fig. 15, with the SNC scheme, it demonstrates a frequency modulation range ( f m / f 0 ) of 5% and 12%. In Fig. 16(a), a line impedance stabilization network (LISN) captures the EMI noise generated from the converter which is then sent to the spectrum analyzer. With the proposed SNC, peak EMI noise is reduced from 84.84 to 64.48 dBμV with a modulation range of 5%, and is further reduced to 33.03 dBμV with a modulation range of 12%. Moreover, VO ripple and load transient response are measured in Fig. 17. With the SNC, a 19.1mV peak-to-peak VO ripple is measured with the f mod of VTR at 20 kHz. In response to a load step-up/down of 0.5 A/100 ns, a 51-mV VO droop is observed when f SW is modulated higher (with the SNC), and a 49-mV VO overshoot is obtained when f SW is nearly same as f 0 . This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. KE et al.: TSGD GaN DC–DC CONVERTER Fig. 18 shows the measured VSW ringing suppression with the TSGD scheme. At 1-A I O and 12-V VIN , VSW ringing is reduced by 79.3%, compared to the case without the TSGD. Specifically, the di /dt transition is modulated longer to achieve a slower rising slope of IDH , and minimizing instantaneous current drawn from VIN and bouncing voltages in the VIN and VSW bond wires. The measured VGH with adaptive tri-slope gate driver in different I O and VIN conditions is shown in Fig. 19. When I O increases, the di /dt transition period (t p1 ) is modulated from 0.9 to 2.5 ns. As VIN increases, the dv/dt transition period (t p2 ) varies from 0.6 to 2 ns. Fig. 20 shows the measured EMI noise spectrum in a frequency range of 2 to 100 MHz, with a resolution bandwidth RBW of 20 kHz. Compared to the conventional design with fixed f SW , peak EMI noise at 10 MHz is reduced from 84.73 to 51.33 dBμV with the SNC scheme ( f m / f 0 = 9%), and is further reduced to 44.23 dBμV with the TSGD. Similarly, peak EMI noise at 90-MHz frequency is reduced from 78.07 to 61.07 dBμV with the SNC scheme, and is further reduced to 55.60 dBμV with the TSGD. At the middle frequency range from 10 to 70 MHz, the EMI noise floor is reduced from 52.32 to 43.62 dBμV with the TSGD. Fig. 21 gives the measured VSW at different I O , VIN and modulation range ( f m / f 0 ). As the converter operates in a wide VIN range of 3 to 40 V and offers a maximum I O of 1.2 A at 10 MHz f SW , it supports different frequency modulation ranges to achieve effective EMI reduction in different I O , VIN conditions. As a summary, Table I compares this design with prior arts. V. C ONCLUSION A TSGD GaN dc–dc converter for EMI-regulated automotive electronics is presented. The SNC scheme provides a random distributed f SW within a sideband of f m , resulting in a sizable EMI noise reduction. With the proposed adaptive TSGD, the SRs of IDH and VSW in high side power switch are modulated according to I O and VIN conditions, achieving an effective VSW ringing suppression. Noise floor at the midfrequency range is also reduced, eliminating the need of an input filter. Experimental results successfully verify the effectiveness of the design techniques. 13  X. Ke, J. Sankman, M. K. Song, P. Forghani, and D. B. Ma, “A 3-to-40 V 10-to-30 MHz automotive-use GaN driver with active BST balancing and VSW dual-edge dead-time modulation achieving 8.3% efficiency improvement and 3.4 ns constant propagation delay,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2016, pp. 302–304.  M. K. Song, L. Chen, J. Sankman, S. Terry, and D. Ma, “A 20 V 8.4 W 20 MHz four-phase GaN DC-DC converter with fully on-chip dual-SR bootstrapped GaN FET driver achieving 4 ns constant propagation delay and 1 ns switching rise time,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2015, pp. 302–303.  X. Ke, J. Sankman, Y. Chen, L. He, and D. B. Ma, “A 10 MHz 3-to-40 V VIN tri-slope gate driving GaN DC-DC converter with 40.5 dBμV spurious noise compression and 79.3% ringing suppression for automotive applications,” in IEEE Int. SolidState Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2017, pp. 430–432.  A. Majid, J. Saleem, H. B. Kotte, R. Ambatipudi, and K. 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Available: https://www.infineon.com/ dgdl/irlb4030pbf.pdf?fileId=5546d462533600a4015356604640258d  Efficient Power Conversion Corp. EPC1001—Enhancement Mode Power Transistor. Accessed: Apr. 2010. [Online]. Available: http://epcco.com/epc/Products/eGaNFETsandICs/EPC1001.aspx  Y. Xiong, S. Sun, H. Jia, P. Shea, and Z. J. Shen, “New physical insights on power MOSFET switching losses,” IEEE Trans. Power Electron., vol. 24, no. 2, pp. 525–531, Feb. 2009. Xugang Ke (S’14) received the B.E. and M.E. degrees in electrical engineering from Zhejiang University, Hangzhou, China, in 2007 and 2010, respectively. He is currently pursuing the Ph.D. degree with the Integrated Power System Laboratory, University of Texas at Dallas, Richardson, TX, USA. In 2010, he joined Texas Instruments, China Design Center, Shanghai, China, as an Analog/Power IC Designer. He involved in designing eight power management ICs, including high-voltage step-up/-down converters, backlighting LED drivers, and LCD bias PMUs until 2014. His current research interests include highfrequency GaN drivers or GaN-based power converters, high-voltage siliconbased power converters. This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. 14 Joseph Sankman (S’05–M’15) received the B.S. degree in electrical engineering from the University of Arizona, Tucson, AZ, USA, in 2010, the Ph.D. degree in electrical engineering from the University of Texas at Dallas, Richardson, TX, USA, in 2014. He joined Texas Instruments, Dallas, TX, USA, in 2015, involve in linear and switch-mode battery chargers. He is currently involved in ultra-lowpower circuits. He has co-authored more than a dozen peer-reviewed conferences and journals. His research interests included energy harvesting circuits and systems and high-performance switch-mode power converters. Dr. Sankman was awarded the U.S. National Science Foundation Graduate Research Fellowship as well as the Texas Instruments/Semiconductor Research Corporation Graduate Fellowship in 2011. He received the Best in Session Award at SRC TECHCON in 2012 and 2013 for his work on piezoelectric energy harvesting. Yingping Chen (S’15) received the M.E. degree in micro-electronics and solid-state electronics from the University of Chinese Academy of Sciences, Beijing, China, in 2012, and the B.E. degree in polymer materials and engineering from the Beijing Institute of Technology, Beijing, in 2008. He is currently pursuing the Ph.D. degree in electrical engineering with the University of Texas at Dallas, Richardson, TX, USA. Between 2012 and 2014, he was an Analog Engineer with Sigma Micro., Beijing, where involved in high-voltage dc–dc converters, LED drivers, and constant-current/constantvoltage ac/dc chargers. In 2014, he joined Dialog Semi., Beijing, where he involved in PMICs. His current research interests include high-frequency/low EMI power converters, and GaN drivers. IEEE JOURNAL OF SOLID-STATE CIRCUITS Lenian He (M’17) received the B.Sc. degree from the Department of Electronic Engineering, Southeast University, Nanjing, China, in 1983, and the Ph.D. degree in Kanazawa University, Ishikawa, Japan, in 1996. From 1983 to 1990, he served as a Principal Engineer/CTO with Suzhou Semiconductor Cooperation, Suzhou, China, where he was responsible for developing CMOS sensors and ICs. From 1996 to 1999, he was a Senior Research Scientist with the Research and Development Center, Toyo Tanso Cooperation, Osaka, Japan. In 1999, he joined Zhejiang University, Hangzhou, China, as an Associate Professor, where he has been a Full Professor with the College of Electrical Engineering, since 2002. He is currently the Professor and the Director of the Institute of VLSI Design, and the Vice Dean of the School of Microelectronics, Zhejiang University. He has authored or co-authored more than 120 papers and three books on analog/power IC design, and holds 18 patents. His current research interests include power management ICs, drivers for LED lighting and backlighting, ac/dc controllers, and data converters. Dr. He received the 1991 Komatsu Green Research Award, the 1994 Yoneyama Research Award both in Japan, the 2005 Excellent Staff Award from College of Electrical Engineering, Zhejiang University, for his teaching and research contributions, the Scientific and Technological Achievements Awards from Zhejiang Provincial Government, and the Teaching Achievements Awards from the State Educational Ministry of China, in 2009 and 2013, respectively. D. Brian Ma (S’99–M’02–SM’07) received the Ph.D. degree in electrical and electronic engineering from the Hong Kong University of Science and Technology, Hong Kong, in 2003. He received the B.S. and M.S. degrees in electronic science from NanKai University, Tianjin, China, in 1995 and 1998, respectively. He was a Faculty Member with Louisana State University, Baton Rouge, LA, USA, from 2003 to 2004 and University of Arizona, Tucson, AZ, USA, from 2004 to 2010. He is currently a Distinguished Chair in microelectronics and a Full Professor of electrical and computer engineering with the University of Texas at Dallas, Richardson, TX, USA, where he is a Founding Director of the Integrated Power System Laboratory. He has authored one book, four book chapters, and over 160 peer-reviewed journal and conference papers. He also holds five U.S. Patents. His current research interests include integrated power electronics, with primary interests on silicon, GaN and SiC-based power IC solutions for big data, IoTs, automobile electronics, and battery powered portable electronics. Prof. Ma was a recipient of the U.S. National Science Foundation CAREER Award in 2009. He also received the University of Arizona AAFSAA Outstanding Faculty Award in 2006, and was a finalist for University of Arizona Accolades Outstanding Faculty Award in 2009. He received numerous research paper or design awards from international conferences and journals. He was awarded the Analog Devices Professorship during 2004–2008, the TxACE Chair Professorship during 2010–2012, the Erik Jonsson Chair during 2012–2017, and the Distinguished Chair in Microelectronics since 2017.