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1.1535932

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Sergey Shkarayev
Mem. ASME,
Department of Aerospace and Mechanical
Engineering,
The University of Arizona,
Tucson, AZ 85721
e-mail: svs@u.arizona.edu
Sergey Savastiouk
e-mail: savastuk@trusi.com
Oleg Siniaguine
e-mail: osiniag@trusi.com
Tru-Si Technologies, Inc.,
Sunnyvale, CA 94086
Stress and Reliability Analysis
of Electronic Packages
With Ultra-Thin Chips
This research concerns itself with a stress and reliability analysis of electronic packages
with ultra-thin chips based on the finite element method. The effect of chip and substrate
thickness, substrate material, presence of underfill, dimensions, and shape of the bump on
stress reduction is analyzed. Obtained results clearly show that chip thinning, when used
with an appropriate design of the entire package, can significantly decrease stresses and
stress intensity factors and improve the reliability of the package. The developed software
provides an effective design tool to quantify the reliability, stresses, and deflections of a
package with ultra-thin chips. 关DOI: 10.1115/1.1535932兴
Introduction
In order to meet the challenges of further miniaturization in
electronic device packaging, a novel chip thinning technology has
been developed in recent years 关1兴. This type of technology provides a damage-free chip surface and makes it possible to introduce thru-silicon interconnects. Decreasing the thickness of the
chip also increases its flexibility, as illustrated in Fig. 1. Thinner
packages also require new expertise, specifically, in the analysis of
stresses and reliability of ultra-thin flip-chip applications.
In the current research, the efficiency of ultra-thin chips for
improvement of the thermo-mechanical performance of electronic
packages has been examined numerically by the finite element
method. This approach allows the determination of the stress field
in the device components, as well as fracture parameters near the
sharp corners formed by dissimilar materials. A design tool in the
form of a software package called Magic Corners has been developed with a seamless procedure for pre and post-processing. Automatic mesh generation algorithms were created, and the software was customized for ultra-thin flip-chip configurations.
Parametric calculations were performed for a number of package configurations and design cases. Obtained results clearly show
that chip thinning, when used with an appropriate design of the
entire package, can significantly decrease stresses and stress intensity factors. Based on this analysis, an increase in the strength
and lifetime of packages with ultra-thin chips is predicted.
stresses induced by material property mismatches. These stresses
may cause failure of a component material due to thermal or mechanical cyclic or impact loading. Geometric and material discontinuities at the corners of adhesive/adherent interfaces cause the
stress singularities. These corners are prone to cracking both in
adjacent components and along material interfaces. To predict the
reliability of the package, we need to know the response of the
structure as represented by stresses in device components and
fracture parameters of their interfaces near the corners.
In order to predict the strength of interfaces between dissimilar
materials, a fracture criterion for adhesive failure mode was constructed by Gradin 关2兴 based on the generalized stress intensity
factors. The experimentally measured critical values for the generalized stress intensity factors need to be determined for failure
prediction based on this criterion. Even without these data, this
criterion can be used for comparative analysis of the newly developing technology. The numerical equality of eigenvalues at the
corners is a necessary condition for comparative analysis of two
distinct configurations. Therefore, in the present paper, comparative analyses of stress distributions and generalized stress intensity
factors are utilized for the prediction of reliability for packages
with ultra-thin chips.
Stress and Reliability Model of Packages
For the purposes of the current analysis, a ball grid array package of generic configuration is considered, as shown in Fig. 2. The
package consists of chip, substrate, and solder bumps. It can be
made with or without underfill. The following geometric parameters are varied during the course of study: substrate thickness, b,
chip thickness, u, and solder bump dimensions, d and h. Two
materials for the substrate are considered: FR-4 and Al2 O3 . In
addition, the effect of the shape of the bump on stress reduction is
also analyzed. There are two configurations of a solder bump included in the analysis: truncated sphere and column 共see Fig. 2兲.
Consider failure mechanisms for a typical electronic package.
Components of the package are made of dissimilar materials
bonded together. Dissimilar materials possess dissimilar mechanical and thermal properties, such as Young’s modulus, E, Poisson’s
ratio, ␯, and coefficient of thermal expansion, ␣. Under thermal
loading, an electronic device experiences high thermo-mechanical
Contributed by the Electronic and Photonic Packaging Division for publication in
the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received by the EPPD Division, October 1, 2001. Associate Editor: B. Michel.
98 Õ Vol. 125, MARCH 2003
Fig. 1 Wafer of thickness 50 ␮m „courtesy of Tru-Si Technologies, Inc.…
Copyright © 2003 by ASME
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Fig. 4 Geometry for the junction of dissimilar materials
without underfill兲, and E and F in packages with underfill兲, and
the closed corner formed by three dissimilar materials 共A-D in
packages with underfill兲. These two configurations are representative of electronic packages. The origin of the polar coordinate
system, (r, ␪ ), is located at the apex of the wedge. The interface
between the adjacent materials i and i⫹1 is specified by angle ␪ i .
The materials are assumed to be perfectly bonded. Each homogeneous and isotropic sector can exhibit elastic-plastic deformation.
For the stresses and displacements at each sector, Savruk et al. 关3兴
derived analytical expressions that can be presented as
Fig. 2 Geometric description of the package
The distributions of normal stresses, ␴ x and ␴ y , and shear
stress, ␶ xy , are used for characterization of the strength of the
device component. These distributions are calculated along characteristic lines: along chip centerline, S 1 , and along solder middle
plane, S 2 共see Fig. 3兲. The conventional finite element method is
suitable for accurate determination of these stresses. However, the
stress gradients become extremely high and the stress field becomes singular near material junctions and geometric discontinuities at corners A-F 共Fig. 3兲. Therefore, stress fields in such regions
require an asymptotic analysis in order to establish the stress singularities. Conventional finite element analyses for this problem
suffered from inaccurate convergence. To eliminate this shortcoming, special enriched elements that capture the singular behavior
of stresses have to be incorporated in the analysis. The formulation of an enriched element is based upon an asymptotic analytical
solution to the stress near the apex of dissimilar materials, which
will be discussed now.
Consider two junctions of dissimilar materials 共Fig. 4兲: the open
two-material corner with traction-free edges 共A-D in packages
␴ ␣␤ 共 r, ␪ 兲 ⫽r ␭ F ␣␤ 共 r, ␪ 兲
u ␣ 共 r, ␪ 兲 ⫽r ␭⫹1 f ␣ 共 r, ␪ 兲 , ␣ , ␤ ⫽r, ␪
冎
(1)
The parameter ␭, dependent on material properties and geometric
configurations, indicates the strength of the stress field near the
junction. Functions F ␣␤ ( ␪ ) and f ␣ ( ␪ ) are explicitly given in 关3兴.
A perfect interface between adjacent sectors requires the continuity of the traction and displacement components. Enforcing the
continuity and boundary conditions with the help of Eq. 共1兲 results
in a system of linear algebraic equations. A nontrivial solution to
this system exists if its determinant vanishes. Then the eigenvalues are determined, and the solution is constructed in terms of one
arbitrary constant 关3兴.
Obtained analytical asymptotic solutions have been incorporated into the finite element method through the enriched elements
and appropriate modifications of the program 关4兴. The formulation
of the special element is well documented by Gifford and Hilton
关4兴. Based on this formulation and using the stress field given by
the first equation in 共1兲, the generalized stress intensity factors 关2兴
can be determined as
K ␪␪ ⫽ lim r ⫺␭ ␴ ␪␪ 共 r, ␪ ⫽ ␪ i 兲
r→0
K r ␪ ⫽ lim r ⫺␭ ␶ r ␪ 共 r, ␪ ⫽ ␪ i 兲
r→0
冎
(2)
These fracture parameters characterize a singular stress field near
the junction along the material interface specified by the angle ␪ i .
A two-dimensional stress analysis of the package with ultra-thin
chips under thermal loading is performed by the finite element
technique described in the foregoing. The problem is treated as
being under plane strain. The current formulation involves twelve
and nine-node isoparametric finite elements. Only half of the
Table 1 Package component material properties
Material
Chip
Underfill
Solder bump-eutectic
Substrate FR-4
Al2 O3
Modulus, E
共GPa兲
Poisson’s ratio,
␯
CTE
(10⫺6 /°C)
165
6.9
17
23.4
270
0.42
0.30
0.35
0.21
0.22
2.4
27.0
25
51
5.2
Fig. 3 Characteristic lines and points
Journal of Electronic Packaging
MARCH 2003, Vol. 125 Õ 99
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Table 2 Stress intensity factors for baseline design cases 1
and 2
Stress
intensity
factor
K ␪␪
K r␪
Corner
1,
2,
1,
2,
Design
case
A
B
C
D
共thick兲
共thin兲
共thick兲
共thin兲
⫺203.6
⫺16.8
80.6
9.6
64.4
18.0
⫺15.7
⫺4.3
149.2
4.2
57.1
2.3
⫺34.4
⫺2.0
⫺8.1
⫺0.4
Fig. 5 Stress distribution in chip
package with appropriate boundary conditions was considered in
the analysis due to the presence of symmetry. The major portion
of the joint is still modeled with conventional elements while
enriched elements surround the corners. The grids used in this
study contained a total number of 750 and 1100 elements with and
without underfill, respectively. Automatic mesh generation algorithms were created for number configurations of the package
with ultra-thin chips. These algorithms were implemented into the
software called Magic Corners.
Numerical Results for Packages With Ultra-Thin Chips
The baseline package, shown in Fig. 2, has four rows of solder
bumps with spacing of g⫽0.25 mm, and the distance from the
chip edge to the center of the solder bump closest to the chip edge
is t⫽0.19 mm. Other dimensions are: length of the chip l
⫽5 mm and substrate length L⫽10 mm. All material properties
used in the numerical modeling are listed in Table 1. The package
is subjected to a uniform temperature change of 100°C, simulating
heating from 20 to 120°C.
A parametric study is performed through variation of the following dimensions: thickness of the chip, u, substrate thickness, b,
solder diameter, d, and heights of bumps, h. The two solder bump
configurations shown in Fig. 2 and the two materials for the substrate presented in Table 2 will be considered as well.
Effect of Chip and Substrate Thickness. First consider design cases without underfill and with solder bumps of truncated
sphere shape. Solder bumps have the following dimensions: d
⫽100 ␮ m and h⫽90 ␮ m. For design case 1, the chip has a thickness of u⫽700 ␮ m, and the FR-4 substrate has thickness b
⫽1000 ␮ m. Thinned chip technology is represented by design
case 2, with respective geometric values: u⫽50 ␮ m and b
⫽200 ␮ m.
The thermal stresses along the line S 1 in the chip are presented
in Fig. 5. Their analysis reveals a 40–50% decrease in magnitude
of maximal and minimal stresses after thinning, indicating an
overall decrease in the chip bending moment. Distributions of
normal stresses, ␴ x and ␴ y , and shear stress, ␶ xy , in the solder
middle plane are presented in Figs. 6共a兲 and 共b兲. Their comparison
demonstrates a significant decrease in the stresses of the solder in
the package with a thin chip.
Adhesive failure is a high probability for the ball grid array
type of package. It makes the analysis of fracture parameters important. For corners A and C, the eigenvalues are ␭⫽⫺0.43, and
for corners B and D, the singularities are stronger, ␭⫽⫺0.499.
Stress intensity factors along the interface at angle ␪ i ⫽180 deg
Fig. 6 Stress distribution in solder bump for baseline design cases 1 and 2—„a… design case 1, thick chip; „b…
design case 2, thin chip
100 Õ Vol. 125, MARCH 2003
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Fig. 7 Stress intensity factors, K ␪␪ , versus chip thickness, u , at various substrate thicknesses, b —„a… corner
C, „b… corner B
for corners A and B and along the interface at angle ␪ i ⫽0 deg for
corners C and D are given in Table 2. Note that positive values of
K ␪␪ correspond to a peeling failure mode and negative values of
K ␪␪ establish a compression of the crack. Based on this consideration, peeling mode failure is more likely to initiate from corners
B and C along adhesive/adherent interfaces. Shear mode failure
controlled by K r ␪ is not influenced by the deformation direction
and, hence, the corners A and B are prone to this type of failure.
Remember, only those corners having the same eigenvalues 共i.e.,
same material and sector angle combination兲 can be compared
against each other. Comparison of the stress intensity factors for
cases 1 and 2 reveals a decrease of the fracture parameters in the
package with a thinned chip and thin substrate in case 2. It clearly
shows a significant improvement in the strength of the package
with both a thinner chip and substrate.
It was also found that deflection of the package with a thinner
chip is significantly higher. Maximal deflections for design cases 1
and 2 are 38 and 300 ␮m, respectively. Such an increase in package deflection can be explained by a faster decrease in the moment of inertia of the package with the thinner chip, even though
stresses decrease. On the other hand, this result indicates that
highly flexible and reliable electronic packages are possible with
ultra-thin chips. Previously, the possibility of flexible chips that
are conformable to a non-planar surface device was demonstrated
with SRAM memory modules less than 150 ␮m thick 关5兴.
Aforementioned results were obtained for a flexible substrate
made of FR-4. Similar calculations were performed for the substrate made of Al2 O3 . Again, two baseline cases with a thick and
a thin chip were considered. Obtained results proved that there is
Fig. 8 Stress intensity factors, K r ␪ , versus chip thickness, u , at various substrate thicknesses, b —„a… corner
A, „b… corner B
Journal of Electronic Packaging
MARCH 2003, Vol. 125 Õ 101
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Table 3 Stress intensity factors for the packages with smaller
bumps of design cases 3 and 4.
Stress
intensity
factor
K ␪␪
Corner
Design
case
3,
4,
3,
4,
K r␪
共thick兲
共thick兲
共thick兲
共thick兲
A
B
C
D
⫺295.9
⫺43.4
117.2
17.2
96.5
29.8
⫺23.6
⫺7.3
218.2
8.3
83.5
3.1
⫺54.6
⫺5.1
⫺12.9
⫺1.2
Table 4 Stress intensity factors for packages with bumps of
column shape of design cases 5 and 6
Stress
intensity
factor
K ␪␪
K r␪
Corner
Design
case
A
B
C
D
5, 共thick兲
6, 共thin兲
5, 共thick兲
6, 共thin兲
⫺67.8
⫺18.0
⫺39.9
⫺11.2
27.8
9.3
⫺21.8
⫺7.6
18.3
⫺10.5
⫺11.0
6.7
⫺7.6
⫺0.5
⫺5.9
⫺0.4
Table 5 Stress intensity factors associated with corners for
packages with underfill of design cases 7 and 8
Stress
intensity
factor
K ␪␪
K r␪
Corner
Design
case
A
B
C
D
E
F
7, 共thick兲
8, 共thin兲
7, 共thick兲
8, 共thin兲
0.2
0.1
⫺2.1
⫺1.6
⫺0.07
0.06
⫺0.7
0.5
⫺0.1
⫺0.02
⫺0.9
⫺0.1
0.4
0.2
⫺3.7
⫺1.9
⫺5.0
⫺5.0
⫺5.6
5.6
⫺3.5
⫺3.9
⫺3.5
⫺3.9
a positive effect of thinning on the thermo-mechanical performance of the package with a substrate made of Al2 O3 .
Design cases 1 and 2 represent two limit configurations. A complete parametric study has been performed through variation of
the thickness of the chip, u⫽700, 600, 400, 200, 100, and 50 ␮m,
and thickness of the substrate, b⫽1000, 600, and 200 ␮m. Stress
distributions and stress intensity factors are obtained for all possible combinations of these parameters. Values of K ␪␪ for corners
C and B 共Fig. 7兲 and K r ␪ for corners A and B 共Fig. 8兲 are selected
for illustration of the results of the calculations. For each value of
substrate thickness, b, the values K ␪␪ at corner C and K r ␪ at
corner A 共see Figs. 7共a兲 and 8共a兲兲 decrease when chip thickness, u,
decreases. Stress intensity factors K ␪␪ and K r ␪ behave differently
near corner B. They decrease for b⭐600 ␮ m and increase otherwise.
The Effect of Bump Configuration. Consider the effect of
bump size in conjunction with thinning. Design cases 3 and 4
were derived from design cases 1 and 2, respectively, by decreasing the size of the bumps to d⫽50 ␮ m and h⫽45 ␮ m, while the
ratio of diameter-to-height of the bump remains the same. Hence,
the eigenvalues remain the same as in cases 1 and 2; stress intensity factors are presented in Table 3.
The design parameter sensitivity study performed by Johnson
关6兴 demonstrated that solder bump height is a very influential
design parameter. The reliability of ball grid array packages improves significantly with a solder height increase. Comparison of
data in Table 2 against Table 3 revealed that the larger bumps of
configurations 1 and 2 provide smaller stress intensity factors for
both thick and thin chips. Thinning of the chip for smaller bumps
has a positive effect on the overall stress field of the package with
smaller bumps, which is more pronounced than the effect of larger
bumps.
The effect of the shape of the solder bumps was studied with
the help of design cases 5 and 6 for column bumps of diameter
d⫽100 ␮ m and of height h⫽90 ␮ m. Eigenvalues for these cases
become smaller: ␭⫽⫺0.25 for corners A and C, and ␭⫽⫺0.41
for corners B and D. Stress intensity factors are given in Table 4.
Comparison of data presented in the table indicates similar improvement in the strength of the package with a thinner chip
共compare case 5 with case 6兲. Thus, the reliability of a package
with an ultra-thin chip can be improved significantly by an appropriate design of the entire package.
The Effect of Underfill. The influence of underfill is studied
with the help of design cases 7 and 8. Geometric parameters of the
packages are kept the same as in cases 1 and 2. The height of
Fig. 9 Variation of stresses along the middle plane of a solder bump in the package with underfill—„a… design
case 7, „b… design case 8
102 Õ Vol. 125, MARCH 2003
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underfill overflow is 0.12 mm. Results of calculations show that
eigenvalues are significantly reduced by the presence of underfill:
␭⫽⫺0.12 at corners A and C, ␭⫽⫺0.11 at corners B and D, ␭
⫽⫺0.028 at corner E, and ␭⫽⫺0.23 at corner F. Stress intensity
factors are given in Table 5. The presence of underfill clearly
shifts the critical region from the solder connection to the intersection of the chip and underfill overflow 共corners E and F兲. These
results were previously noted in reference 关7兴. Stress distributions
along the solder middle plane are shown in Fig. 9. Analysis of
stress intensity factors and stresses in solder for cases 7 and 8
shows that chip thinning has the same positive effect on the reliability of the package with underfill.
Finally, compare the stresses in the solder in the package without underfill and with an ultra-thin chip 共see design case 2 in Fig.
6共b兲兲 and the package with underfill and a thick chip 共design case
7 in Fig. 9共a兲兲. Note that stresses for case 2 are fairly lower than
for case 7. These results indicate that ultra-thin chips may provide
the same level of reliability for a package without underfill as
exists for a package with underfill but with a thick chip.
Summary
1 The present work provides a parametric study of stress distributions and generalized stress intensity factors in electronic
packages with ultra-thin chips under thermal loading.
2 Analysis was performed by the finite element method by taking into account stress singularities near the corners of dissimilar
materials. Automatic mesh generation algorithms were created for
all considered configurations. These algorithms were implemented
into the software called Magic Magic Corners.
Journal of Electronic Packaging
3 Parametric analysis clearly demonstrated a significant improvement in the reliability of packages with ultra-thin chips
when used with an appropriate design of the entire package. The
effect of substrate materials, thickness, and solder bump shape
was studied in detail.
4 Results indicate that ultra-thin chips may provide the same
level of reliability for packages without underfill as exists for
packages with underfill but with a thick chip.
References
关1兴 Francis, D., 1999, ‘‘Thinning Wafers for Flip Chip Applications,’’ The Magazine of High-Density Interconnect, 2共5兲, pp. 22–25.
关2兴 Gradin, P., 1982, ‘‘A Fracture Criterion for Edge-Bonded Bimaterial Bodies,’’
J. Compos. Mater., 16, pp. 448 – 456.
关3兴 Savruk, M. P., Shkarayev, S., and Madenci, E., 1999, ‘‘Stress Near Apex of
Dissimilar Materials with Bilinear Behavior,’’ J. Theoretical and Applied Fracture Mechanics, 31, pp. 203–212.
关4兴 Gifford, N., and Hilton, P., 1981, ‘‘Preliminary Documentation of PAPST—
Nonlinear Fracture and Stress Analysis by Finite Elements,’’ David W. Taylor
Naval Ship Center.
关5兴 Chen, K., Zenner, R., Arneson, M., and Mountain, D., 1999, ‘‘Ultra-Thin Electronic Device Package,’’ 49th Electronic Components and Technology Conference, IEEE, San Diego, CA, pp. 657– 662.
关6兴 Johnson, Z., 1999, ‘‘Implementation of and Extensions to Darveaux’s Approach to Finite Element Simulation of BGA Solder Joint Reliability,’’ 49th
Electronic Components and Technology Conference, IEEE, San Diego, CA,
pp. 1190–1195.
关7兴 Madenci, E., Shkarayev, S., and Mahajan, R., 1998, ‘‘Potential Failure Sites in
a Flip-Chip Package With and Without Underfill,’’ ASME J. Electron. Packag.,
120, pp. 336 –341.
MARCH 2003, Vol. 125 Õ 103
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