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Bias stress instability in organic transistors investigated by ac admittance
measurements
F. V. Di Girolamo, M. Barra, V. Capello, M. Oronzio, C. Romano, and A. Cassinese
Citation: Journal of Applied Physics 107, 114508 (2010);
View online: https://doi.org/10.1063/1.3425795
View Table of Contents: http://aip.scitation.org/toc/jap/107/11
Published by the American Institute of Physics
JOURNAL OF APPLIED PHYSICS 107, 114508 共2010兲
Bias stress instability in organic transistors investigated by ac admittance
measurements
F. V. Di Girolamo,1,2,a兲 M. Barra,1,2 V. Capello,2 M. Oronzio,2 C. Romano,2 and
A. Cassinese1,2
1
CNR-SPIN, University of Naples Federico II, Piazzale Tecchio, 80125 Naples, Italy
Department of Physics Science, University of Naples Federico II, Piazzale Tecchio, 80125 Naples, Italy
2
共Received 16 February 2010; accepted 8 April 2010; published online 3 June 2010兲
In this paper, the bias stress effect 共BSE兲 in organic field-effect transistors has been analyzed by an
alternative experimental approach based on ac admittance 共Y = G + j␻C兲 measurements.
conductance 共C兲 and capacitance 共G兲 curves have been recorded as a function of frequency at
different times of the bias stress experiments and simultaneously fitted through a transmission line
circuit, able to separately model the conducting properties of the channel and contact regions. The
determination of the time behavior of the model fitting parameters is assumed as the starting point
for a quantitative analysis of the BSE occurrence. This experimental procedure clarifies that both
channel resistance 共Rch兲 and contact resistance 共Rc兲 are largely affected by the BSE, while the
channel capacitance 共Cch兲, related to the charge accumulation sheet, and the contact capacitance 共Cc兲
result almost unchanged. © 2010 American Institute of Physics. 关doi:10.1063/1.3425795兴
I. INTRODUCTION
One of the main issues affecting the operation stability
of organic field effect transistors 共OFETs兲 concerns the socalled bias stress effect 共BSE兲. This phenomenon is caused
by the prolonged application of the gate-source 共VGS兲 voltage and consists in the time decay of drain-source 共IDS兲 current at any fixed drain-source 共VDS兲 voltage.1,2 The physical
origin of BSE has been mainly ascribed to the presence of
active trapping sites. These traps are related to intrinsic structural defects 共e.g., grain boundaries,3 organic–dielectric
interface4兲 and/or to defect-attracted impurities 共e.g., water
or oxygen兲.5 So far, two main experimental approaches, both
in dc regime, have been used to investigate the BSE occurrence. The former relies on the analysis of time shift of the
transistor threshold Vth voltage, which can be determined
from the plot of the transfer-curves through geometrical
criteria.1 The latter is based on the direct observation of transistor IDS time decay upon static voltage polarization 共fixed
VDS and VGS兲.6 In both cases, the time behavior of the measured parameters can be modeled by formulas based on the
stretched exponential function.7,8 This occurrence reflects the
dispersive nature of BSE, basically accounting for a wide
distribution of characteristic times in the elementary trapping
processes. The physical localization of these traps 共e.g., at
the interface with dielectric,4 in the film bulk or at the contact regions near the source-drain electrodes9,10兲 have been
studied by different techniques. In particular, the presence of
traps at the interface between the dielectric substrate and the
organic semiconductor has been assessed by considering
metal-insulator-semiconductor 共MIS兲 structures. Indeed,
frequency-dependent admittance measurements, performed
at different bias voltages on MIS capacitors, have been used
to determine the interface state density and the corresponda兲
Author to whom correspondence should be addressed. Electronic mail:
fdigirolamo@na.infn.it.
0021-8979/2010/107共11兲/114508/6/$30.00
ing relaxation times.11 A similar approach has been followed
also to examine the role of the interfacial states in threshold
voltage instability effects.12 On the other hand, inspired by
the general observation that the structural order of organic
films is worse near the transistor electrodes,5 the contribution
of the contact resistances 共Rc兲 to BSE has been recently investigated too. This goal has been mainly pursued by using
Kelvin probe microscopy9 or the so-called transmission line
共TL兲 method.10 Both these techniques have demonstrated
that contact resistances Rc is increased because of the BSE,
being its variation extremely sensitive on the contact configuration 共staggered or coplanar兲 and on the electrode material and geometry.
In this paper, ac admittance measurements have been
directly performed on organic sexithiophene 共T6兲 OFETs,
with the main goal to gain insights about the relevance of Rc
in the BSE. Admittance measurements have been carried out
with shortened source and drain as a function of frequency
and dc bias voltages. The same configuration measurement
has been recently utilized to investigate the dynamic behavior of OFETs and to discriminate the contribution of the active channel and of the drain-source contact regions in the
overall device response.13 Here, we have further developed
this approach by recording admittance measurements at the
different times of bias stress experiments. The subsequent
time evolution of the electrical parameters related to the active channel and to the contact regions suggested an alternative procedure to assess BSE influence.
II. DEVICE FABRICATION AND DC
CHARACTERIZATION
OFETs in bottom-contact 共coplanar兲 bottom-gate configuration have been fabricated in a high vacuum 共Pr
⬇ 10−7 / 10−8 mbar兲 chamber by evaporating T6 films on
107, 114508-1
© 2010 American Institute of Physics
114508-2
J. Appl. Phys. 107, 114508 共2010兲
Di Girolamo et al.
FIG. 1. 共Color online兲 共a兲 Typical transfer-curve in linear region 共VDS
= −5 V兲 for a T6 transistor. In the inset, the time decay of the IDS dc current
due to the BSE 共VGS = −40 V , VDS = −5 V兲.
Si++共500 ␮m兲 / SiO2共200 nm兲 substrates provided of gold
source-drain interdigitated electrodes. More details about the
transistor layout can be found elsewhere.14–16 During the
deposition, the entire chamber was warmed at 100 ° C. The
evaporation rate was 1 nm/min and the film thickness 60 nm.
By this procedure, polycrystalline T6 films, with domains
composed by steplike circular aggregates and showing lateral
size up to 1 ␮m, are obtained.
In these films, T6 molecules are prevalently c-axis oriented 共the molecular long axis is perpendicular to the SiO2
surface兲 in agreement with other results reported in the
literature.16 Electrical characterizations were performed in
vacuum 共10−5 mbar兲 and in darkness. A representative
transfer-curve in linear region 共VDS = −5 V兲 is reported in
Fig. 1共a兲. The charge carries mobility ␮ has been estimated
to be about 1 ⫻ 10−2 cm2 / Vⴱ s by using the standard metaloxide-semiconductor field-effect transistor 共MOSFET兲
equations.17 For most devices, the slope of transfer-curve
reduces at high VGS, similarly to what reported in Fig. 1.
This feature is basically related to the effect of Rc, whose
contribution 共completely neglected in the MOSFET model兲
gets more remarkable when IDS increases and the device total
resistance lowers.18 BSEs on OFET operation have been first
analyzed in dc regime15 by recording the IDS time decay
curves upon static polarization 共VGS = −40 V , VDS = −5 V兲
up to 1000 s. The experimental curves 共IDS versus time兲 have
been fitted by the stretched exponential function 共see the
inset in Fig. 1兲
冋 冉 冊册
I = I0 exp −
t
␶
␤
.
共1兲
Typical stress parameters extracted for the curve in Fig. 1 are
␶ = 5100⫾ 200 s and ␤ = 0.40⫾ 0.05. Since Eq. 共1兲 is rigorously valid only if any Rc effect can be excluded, the aforementioned approach has to be considered suitable to describe
the BSE dynamics only in first approximation.
III. AC ADMITTANCE MEASUREMENTS
The admittance measurements 共Y = G + j␻C兲 have been
performed by electrically shortening the source and drain
FIG. 2. 共Color online兲 Capacitance 共a兲 and conductance 共b兲 measurements
vs dc gate bias 共VB兲 at different frequencies.
electrodes and connecting them to the low terminal of a LCR
meter 共Agilent 4284A兲, while the gate contact is connected
to the high one. Before the ac measurements, the device active area was isolated by scribing the organic material around
it.13 The input signal at LCR meter terminals was given by
the superimposition of a small amplitude ac signal 共Vac
= 0.1 V兲 and dc bias 共VB兲 voltages. Capacitance-frequency
共C-f兲 and conductance-frequency 共G-f兲 curves 关see Figs. 2共a兲
and 2共b兲, respectively兴 have been simultaneously recorded
by sweeping the frequency between 100 Hz and 100 KHz
and setting VB in the range from ⫺40 and 40 V; C-VB and
G-VB curves are collected by exchanging the roles of VB and
frequency 关Figs. 3共a兲 and 3共b兲兴. C-VB curves 关Fig. 2共a兲兴
show some meaningful physical features. First, the capacitance rapidly increases going from the depletion region
共VB = 40 V兲 to the accumulation one 共VB = −40 V兲, resembling the dc current behavior in the transfer-curves. Indeed,
when the device is depleted of mobile charges, the measured
capacitance is given only by the parallel sum of the capacitances between drain-source electrodes and gate contact.
Conversely, when the charges are accumulated at the interface with the oxide layer, a further and strongly frequencydependent capacitive contribution arises. In the quasistatic
limit 共low frequency region兲, the value ⌬C = 关CACC共VB
= −40 V兲 − CDEP共VB = 40 V兲兴 is theoretically equal to the
channel capacitance Cch, given by the product between the
active channel area and the sum of the oxide and interface
capacitances per unit area.13 In the G-VB curves 关Fig. 2共b兲兴,
the formation of the accumulation layer gives rise to a characteristic peak, getting smoother and smoother at increasing
frequencies. The highly dispersive nature of the measured
admittance measurements is represented with more evidence
114508-3
J. Appl. Phys. 107, 114508 共2010兲
Di Girolamo et al.
where ␥ = 1 / L共j␻RchCch兲 and Z0 = 共Rch / j␻Cch兲1/2. In this expression, ZTL represents the input impedance related to the
active channel TL, while ZRC is referred to the RC loops for
the contact regions. An explicit expression for C and G can
be obtained by some simple mathematical manipulations of
Eq. 共2兲. Indeed, by defining
1
␣ = 共CchRch␻兲1/2 ,
2
共3兲
␶ c = R cC c ,
共4兲
FIG. 3. 共Color online兲 Capacitance 共a兲 and conductance 共b兲 curves as a
function of frequency at different VB voltages.
by the C-f and G-f curves 关Figs. 3共a兲 and 3共b兲, respectively兴,
yielding clearer the difference between the accumulation and
the depletion regimes.
The experimental admittance data have been compared
with the theoretical predictions deduced by the equivalent
circuit in Fig. 4共a兲. The transistor active channel is described
by a TL, where the channel capacitance 共Cch兲 and channel
resistance 共Rch兲 are distributed elements. This approach was
initially proposed to accurately describe the response of very
thin gate MOSFET devices and to determine the channel
charge density and mobility.19 More recently, the TL model
was considered to gain insights into the characterization of
bottom-contact polymer thin-film transistors, being extended
with the adoption of two lumped loops 共contact resistance Rc
and capacitance Cc兲 to shape the electrical properties of the
source-drain contact regions.13 According to the configuration of the ac measurements, the electrical short between
drain and source renders the circuit symmetric and an
equivalent open circuit is located exactly in the middle of the
transistor channel. Consequently, by using the impedance
transport formulas, the overall circuit admittance can be written as
Y = G + j␻C =
=
冋
冤
1
ZTL + ZRC
册
Z0
冉 冊
L
tanh ␥ ⫻
2
+
Rc共1 − j␻RcCc兲
1 + 共 ␻ R cC c兲 2
冥
−1
,
共2兲
FIG. 4. 共Color online兲 共a兲 TL model utilized to shape the experimental
admittance curves; 共b兲 active layer capacitance, and 共c兲 conductance measurements 共symbols兲 and fitting curves 共solid lines兲 at different VB.
114508-4
J. Appl. Phys. 107, 114508 共2010兲
Di Girolamo et al.
Rc
,
1 + 共 ␻ C cR c兲 2
␹c =
共5兲
␭R =
1
冑2 ␣
tanh
␭I =
⫻
1
冑2 ␣
tan
⫻
␣
␣
␣
冉
1 + tanh
␣
冑2
− tanh
␣
冑2
− tanh
冉
␣
冑2
1 + tanh
tan
␣
冑2
冑 冉
␣
tan
2
␣
tanh
冑 冊
␣
冑2
2
+ tan
冑 冊
␣
冑2 + tan 冑2 + tanh 冑2 tan 冑2
␣
冉
␣
冑2 tan 冑2
tan
冊
,
C=
,
2
2
␻Cch
␭I␹c共␭R + ␻␶c␭I兲 + Cch␭R关1 − ␻␹cCch共␭I − ␻␶c␭R兲兴
,
关1 − ␻␹cCch共␭I − ␻␶c␭R兲兴2 + 关␻Cch␹c共␭R + ␻␶c␭I兲兴2
共8兲
2
␭R␹c共␭R + ␻␶c␭I兲 − ␻Cch␭I关1 − ␻␹cCch共␭I − ␻␶c␭R兲兴
␻2Cch
.
关1 − ␻␹cCch共␭I − ␻␶c␭R兲兴2 + 关␻Cch␹c共␭R + ␻␶c␭I兲兴2
These formulas are used to fit the capacitance and conductance experimental curves related to the sole channel contribution, which are obtained by subtracting the C and G values
in depletion mode 共VB = 40 V兲 from the C-f and G-f curves
recorded at the different VB voltages. The fitting procedure is
based on the determination of the four parameters: Rch, Cch,
Rc, and Cc. In this study, best fittings of the curves have been
achieved by minimizing the ␹2 through a specialized software routine 关MINUIT 共Ref. 20兲兴, which is able to fit C-f and
G-f curves simultaneously. It should be highlighted that in
the previous reports the data fitting was limited only to the
capacitance data set.13 The procedure discussed above has
been applied to the experimental 共symbols兲 curves reported
in Figs. 4共b兲 and 4共c兲, which represent the channel capacitance and conductance extracted from the data in Fig. 3. The
corresponding fittings are the solid lines in Figs. 4共a兲 and
4共b兲, while the resulting fitting parameters are summarized in
the Table I. As it can be observed, when the OFET is in the
full accumulation region 共VB between ⫺20 and ⫺40 V兲 the
theoretical curves fit reasonably well the experimental data.
The differences between theory and experiments get more
and more evident at higher voltages 共VB = −10 and 0 V兲 when
the accumulation charge sheet is only partially formed 共see
also Fig. 2兲. From Table I, only Rch seems to be largely
dependent on the VB value. Indeed, it varies of about 30%,
共9兲
when VB goes from ⫺40 to ⫺20 V, and shows a linear dependence on 1 / VB, in agreement with the basic MOSFET
model.17 Cch is almost bias voltage independent, while both
contact parameters 共Rc and Cc兲 increase of about 10%. The
device total resistance RTOT = 共Rch + 2Rc兲 extracted from ac
measurements results to be larger than RTOT evaluated by dc
transfer-curves. This discrepancy, less then a factor of 2 at
VB = −40 V, gets more and more relevant for increasing VB.
This occurrence can be partially explained by considering
that ac measurements are performed with shortened drainsource electrodes 共VDS = 0兲, thus neglecting any possible dependence of Rc and Rch on VDS.
For completeness, a further analysis of the experimental
data has been carried out by using an alternative model, recently proposed by Lenski et al.21 In their work, the authors
demonstrated the effectiveness of the TL model in correctly
describing the admittance response of a pentacene fieldeffect device, only if a complex and frequency-dependent
sheet resistance 共Rsh兲 is used to shape the electrical properties of the active channel. In this case, no further Rc-Cc
lumped loop was considered for the contact regions. The
frequency-dependence of the sheet conductance 共Gsh
= 1 / Rsh兲 was modeled in the framework of the so-called universal dielectric response 共UDR兲 by the expression
TABLE I. Fitting parameters obtained for C and G curves versus frequency and at different VB voltages.
Cch 共pF兲
Cc 共pF兲
Rc 共k⍀兲
Rch 共k⍀兲
␹2
冊
C and G can be written as
共6兲
G=
␣
共7兲
␣
2
2
␣
冑2 − tanh 冑2
VB − 40 V
VB = −35 V
VB = −30 V
VB = −25 V
VB = −20 V
VB = −10 V
VB = 0 V
206⫾ 2
752⫾ 36
195⫾ 20
764⫾ 16
1.3
204⫾ 2
763⫾ 36
205⫾ 24
814⫾ 20
1.4
202⫾ 2
773⫾ 36
206⫾ 24
874⫾ 20
1.4
199⫾ 2
792⫾ 36
217⫾ 28
964⫾ 24
1.5
196⫾ 2
820⫾ 40
223⫾ 28
1089⫾ 24
1.6
185⫾ 2
940⫾ 80
254⫾ 40
1800⫾ 20
2.4
141⫾ 2
37⫾ 16
497⫾ 12
1310⫾ 200
4
114508-5
J. Appl. Phys. 107, 114508 共2010兲
Di Girolamo et al.
FIG. 5. 共Color online兲 Comparison between C-f 共a兲 and G-f 共b兲 measurements 共symbols兲 in the full accumulation region 共VB = −40 V兲 and the corresponding fitting curves obtained by Model I 共solid line兲 and Model II
共dashed line兲.
Gsh = Gdc + A ⫻ ␻s ,
共10兲
where Gdc is the dc sheet conductance and s a characteristic
exponent, usually lower than 1. The UDR behavior is a more
general law which was introduced to accurately describe the
electrical conducting properties of various classes of disordered materials, going from purely dielectric compounds to
amorphous inorganic22 and organic23 semiconductors.
The UDR approach has been here followed by fitting the
channel capacitance and conductance curves by the Eqs. 共8兲
and 共9兲, where the contributions related to the contact loop
has been neglected and the channel resistance Rch has been
defined as
Rch =
冉 冊冉 冊 冉 冊冉
L
w
1
L
=
Gsh
w
冊
1
.
Gdc + A ⫻ ␻s
共11兲
It should be noted that no frequency-dependence has been
considered for Cch.21 Fitting curves of C-f and G-f plots in
the full accumulation region 共VB = −40 V兲, obtained by this
procedure 共MODEL II兲 and compared with the results of the
initial model 共MODEL I兲 accounting for the parallel Rc-Cc,
are shown in Figs. 5共a兲 and 5共b兲, respectively.
The best fitting curve by the Model II provides the folA = 共68⫾ 10兲
lowing
parameters:
Cch = 156⫾ 2 pF,
⫻ 10−9 共S*s / rad兲, and s = 0.29⫾ 0.01.
The comparison between the fitting curves reveals that,
differently from Model I, the UDR approach is unable to
provide a good agreement between the theoretical and experimental data, even in the full accumulation region. Hence,
the idea that contact regions carries out a striking role in
FIG. 6. 共Color online兲 Capacitance 共a兲 and conductance 共b兲 measurements
共symbols兲 at VB = −40 V recorded at different times of the bias stress experiment and the corresponding fitting curves 共solid lines兲 by Model I. Conductance curves are shifted, for clarity, by multiplying the data at t = 150 s,
t = 1000 s, and t = 3000 s, respectively, by a factor of 1.5, 2.25, and 3.375.
共c兲 Time variation in fitting ac parameters and of dc total resistance normalized at the initial values.
affecting the device electrical behavior is supported by these
observations and will be even strengthen from here downwards.
IV. ADMITTANCE SPECTROSCOPY INVESTIGATION
OF BSE
Once tested the reliability of the fitting procedure based
on the Model I, it was applied to fit the admittance measurements performed at different times of a bias stress experiment, with the aim to gain more insights into the occurrence
of this type of electrical instability. This characterization has
been performed stressing the devices by the application of
VGS = −40 V for 3000 s and recording several C-f and G-f
curves in the full accumulation region 共VB = −40 V兲 at different times, as shown in Figs. 6共a兲 and 6共b兲, respectively.
114508-6
J. Appl. Phys. 107, 114508 共2010兲
Di Girolamo et al.
TABLE II. Fitting parameters obtained for C and G curves at different times of the bias stress experiment.
Cch 共pF兲
Cc 共pF兲
Rc 共k⍀兲
Rch 共k⍀兲
␹2
t=0 s
t = 150 s
t = 500 s
t = 1000 s
t = 2000 s
t = 3000 s
199⫾ 2
738⫾ 36
185⫾ 20
757⫾ 20
1.2
195⫾ 2
733⫾ 36
205⫾ 24
904⫾ 20
1.4
193⫾ 2
732⫾ 36
218⫾ 24
993⫾ 24
1.6
191⫾ 2
732⫾ 36
228⫾ 28
1062⫾ 24
1.7
190⫾ 2
733⫾ 36
238⫾ 28
1139⫾ 28
1.9
189⫾ 2
734⫾ 36
246⫾ 32
1195⫾ 28
2.0
Figures 6共a兲 and 6共b兲 confirm that the experimental data
can be reproduced with good agreement by the theoretical
fitting curves. The corresponding fitting parameters are reported in Table II and their values, normalized to the initial
value 共t = 0 s兲, are plotted in Fig. 6共c兲. From the analysis of
these data, it comes out that BSE is much more pronounced
for the resistive parameters, while the capacitances seem to
be only slightly affected. In particular, Cc is almost unchanged, supporting the idea that it is basically related to the
formation of a strongly disordered and semi-insulating region near the contacts. On the other hand, the variations in
Rch and Rc after 3000 s of bias stress are about 35% and
25%, respectively. Rch, which is inversely proportional to Vth
in the MOSFET model, experiences the most pronounced
change. However, the change 共25%兲 of Rc is not negligible,
in good agreement with the recent experiments performed by
different approaches.9,10
In Fig. 6共c兲, Rc and Rch curves are also compared with
the variation in RTOT共t兲 = 关VDS / IDS共t兲兴, extracted from the IDS
time decay, obtained in dc regime under VGS = −40 V stress.
The behavior of the parameters deduced by ac analysis is
slightly different form those evaluated in dc regime even in
this case. This discrepancy can be justified by considering
that the microscopic processes relevant in ac and dc transport
are partially different. Indeed, charge elementary motions involved in ac signal transmission cannot give contribution to
the formation of the percolative conducting paths, which instead provides the overall dc electrical transport.21,24 Proceeding along this subject, admittance measurements thus
represent an investigation method capable to give information about the trapping of charges which do not contribute to
percolative paths and are not detectable through dc measurements, eventually clarifying if they have an influence on device response. In this regard, comparing dc and ac stress
properties of devices with different morphologies should be
useful.
V. CONCLUSIONS
In conclusion, admittance measurements have been used
as an alternative tool to probe the OFET response at different
times of bias stress experiments. The experimental capacitance and conductance data have been simultaneously fitted
through a circuit model, with frequency-independent electrical parameters, able to give insights into the conducting
properties of both the active channel and drain-source contact regions. The time variations in contact and channel parameters have been examined, bringing to the conclusion that
bias stress instability degrades the channel Rch and the con-
tact resistance Rc in a comparable way, meanwhile the accumulated charge density is almost unchanged. The striking
role played by contact resistances is also confirmed by the
ineffectiveness of a model considering a frequencydependent channel conductivity in place of the circuital RC
loop accounting for the electrical properties of the film regions near the source-drain electrodes. It follows that, for
practical application, the Rc variations due to the BSE are not
negligible and should be accurately taken into account to
model the transistor response modifications.
ACKNOWLEDGMENTS
The authors wish to thank P. D’Angelo and F. Biscarini
for stimulating discussions. A. Maggio and S. Marrazzo are
also acknowledged for their technical support.
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