close

Вход

Забыли?

вход по аккаунту

?

978-981-10-4603-2 30

код для вставкиСкачать
An Efficient Single-Layer Crossing Based
4-Bit Shift Register Using QCA
Trailokya Nath Sasamal, Ashutosh Kumar Singh
and Umesh Ghanekar
Abstract In co-planar QCA fabrication, QCA wire crossing is a challenging task
as defects appear to be inherent due to two cell types in single layout structure. In
this paper, a compact 2:1 multiplexer is presented which occupies a minimum area
in QCA technology. This work also showcases a successful implementation and
simulation of 4:1 multiplexer, level trigger D flip-flop and 4-bit shift register using
QCADesigner tool. The 4:1 multiplexer and shift register are more robust and enjoy
single-layer wire crossing, which requires only one type of cells. The comparison
results show superiority of the proposed designs over the previous designs in terms
of complexity and delay.
Keywords QCA
Shift register Multiplexer D flip-flop
1 Introduction
Quantum dot cellular automata (QCA) based devices are going to replace CMOS
based devices for its potential improvements. Various QCA-based structures are
explored in [1–8]. QCA architectures for flip-flops and multiplexers have been
presented in [9–15] as these are essential blocks of various digital systems. But
most structures are not robust and vulnerable to fabrication defects due to wire
crossing between the QCA components. This work presents, a robust 4-bit shift
registers using optimal multiplexer and D flip-flop modules.
T.N. Sasamal (&) U. Ghanekar
Department of Electronics & Communication, NIT Kurukshetra,
Kurukshetra, India
e-mail: tnsasamal.ece@nitkkr.ac.in
U. Ghanekar
e-mail: ugnitk@nitkkr.ac.in
A.K. Singh
Department of Computer Applications, NIT Kurukshetra, Kurukshetra, India
e-mail: ashutosh@nitkkr.ac.in
© Springer Nature Singapore Pte Ltd. 2018
R.K. Choudhary et al. (eds.), Advanced Computing
and Communication Technologies, Advances in Intelligent Systems
and Computing 562, https://doi.org/10.1007/978-981-10-4603-2_30
315
316
T.N. Sasamal et al.
The paper is organized as follows. Section 2 presents a review on QCA. In
Sect. 3, optimal design and detailed analysis of basic structures, such as multiplexer
and D flip-flop are given, followed by implementation of an efficient 4-bit shift
register in Sect. 4. Simulated results and comparative analysis are addressed in
Sect. 5. Finally, conclusions are given in Sect. 6.
2 Preliminaries
2.1
QCA Cell and Gates
A QCA cell is a quantum well, which has four quantum dots located at four corners
of a square. Two injected electrons are free to occupy any of the four dots based on
Coulomb repulsion among them. These two electrons position at the two corners
due to repulsion and yield two possible polarizations as shown in Fig. 1. By
applying proper clocks, electrons are able to tunnel through the inter dot barrier by
electrons interaction. Any digital circuits can be made of a combination single QCA
cell. In QCA circuits, majority gates and inverters are the basic building blocks.
Two possible implementations for an inverter are shown in Fig. 1c, d. QCA layout
of a 3-input majority gate is depicted in Fig. 1e. A 3-input majority gate can be
represented as MV(a, b, c) = ab + bc + ca. By fixing one of the inputs to ‘0’ or ‘1’,
an AND gate or OR gate can be realized. Input signals can be made available at the
output end, by placing QCA cells in serial manner, as shown in Fig. 1b.
2.2
QCA Clocking
For proper functioning of QCA circuits, clocks are necessary. This clocking scheme
allows the electrons in a cell to arrange themselves by breaking the inter dot barrier.
Clock
Zone 0
Clock Clock
Zone 1 Zone 2
Clock
Zone 3
Wire
QCA Cell
Quantum
Dot
Tunnel
Junction
Input
A
Output
A’
P= -1
Logic “0”
(a)
Output
A’
A
Input
(c)
F
B
C
Inverter
(d)
A
Electron
P= +1
Logic “1”
(b)
(e)
A
B
C
Fig. 1 a QCA. b Two polarizations of a cell. c QCA wire. d Inverters. e Majority gate
Majority
Voter
An Efficient Single-Layer Crossing Based 4-Bit Shift Register …
317
Generally, it requires four phase clocking scheme. There are four clock zones and
each zone is distinct with 90° phase shifted to one another [16]. Each clock zone
defines four phases: Switch, Hold, Release, and Relax [17].
2.3
QCA Crossing
Till now, there are two different types of crossover are available. These are
co-planar and multilayer. In multilayer crossover, multiple layers are used as in
CMOS circuit design for interconnection between components as depicted in
Fig. 2a. In co-planar crossover scheme, crossing is executed using two different
types of cells as shown in Fig. 2b. Another type of co-planar wire crossing is
addressed in Shin [18]. In this work, wire crossing based on interference of clocking
phases is used, as depicted in Fig. 3.
Fig. 2 Wire crossing.
a Multilayer. b Co-planar
(a)
(b)
90 degree
orientation
Fig. 3 Wire crossing using
single cell
45 degree
orientation
318
T.N. Sasamal et al.
3 Proposed QCA Structures
In this section, we present the basic blocks of a shift register, i.e., multiplexer and D
flip-flop using QCA.
3.1
2:1 Multiplexer
Figure 4a depicts our multiplexer, which employs 3 MV, and 1 inverter in QCA
implementation. This structure comprises only 18 quantum cells. In this structure,
MVs in first level implement two AND gates that are driven by first clocking zone.
The outputs of these MVs are fed to second level MV which is positioned in the
second clocking zone. Select line ‘select’ is used to select one of the inputs, which
also driven by first clock zone. QCA layout for 2:1 multiplexer shown in Fig. 4b
provides a valid output after two clock phases. It comprises only 18 cells that spread
over an area of 0.016 lm2, which has outperformed previous works.
3.2
4:1 Multiplexer
Design of 4:1 multiplexer, even larger multiplexer and incorporating with signal
distribution network (SDN) is a challenging task. For such systems, the complexity
increases in terms of number of wires crossing, so more prone to defects that occurs
due to QCA fabrication of single-layer crossing using two different cells (90° and
45°) in a single layout. In this work, we have considered a robust single-layer
crossing method using single cell (90°). Figure 5 illustrates the QCA layout for 4:1
multiplexer. It includes three 2:1 multiplexer modules, which has a simple structure
that facilitates modularity. Wire crossing is shown by solid squares. Select line S0 is
used to select one of the inputs to 2:1 multiplexers at the first level, where S1 is used
to select one of the outputs from first level. The proposed circuit results a correct
output after eight clock phases and the output cell is driven by forth clock zone.
(a)
(b)
0
I0
MV
1
Select
I1
0
MV
MV
Fig. 4 2:1 multiplexer. a Schematic. b QCA layout
out
An Efficient Single-Layer Crossing Based 4-Bit Shift Register …
319
Fig. 5 QCA layout of 4:1 multiplexer
(a)
(b)
0
D
1
2: 1
MUX2
out
clk
Fig. 6 2:1 multiplexer based level trigger D flip-flop. a Schematic. b QCA layout
3.3
D Flip-Flop
Schematic and layout for level sensitive D flip-flop proposed in this paper are
demonstrated in Fig. 6a, b, respectively. Majority gate at the second level is driven
by third clocking zone and receives inputs from the MVs at the first level. Storing
the input data bit in a loop is implemented using four clocking zones, which allows
data to be holds in the loop until clk = ‘0’. QCA implementation of level trigger D
flip-flop requires 26 cells and area usage is 0.025 lm2.
320
T.N. Sasamal et al.
4 Proposed 4-Bit Shift Register
Shift registers are the essential circuits in digital system particularly useful in binary
division and multiplication with serial and parallel inputs. Figure 7 shows the block
diagram of 4-bit shift register, which comprises four D flip-flops and four 2:1
multiplexers. QCA layout of these four edge trigger D flip-flops is represented by
solid boxes in Fig. 8 [19]. Serial Input Serial Output (SIPO) and Parallel Input
Parallel Output (PIPO) operations are selected by controlling select line of multiplexers, i.e., shift = ‘1’ or ‘0’ respectively. Serial data are shifted right and available
at output lines after each rising edge of the clock signal. QCA layout of proposed
shift register is depicted in Fig. 8. This co-planar implementation involves
single-cell wire crossing, which incurs extra delays, but mitigates defects due to
manufacturing of two different cells in single QCA layout. It includes 889 cells,
spread over an area of 1.4 lm2 and the maximum delay is 9 clock cycles.
D3
Shift-in
D2
2:1
MUX
2:1
MUX
D FF
D0
D1
2:1
MUX
D FF
2:1
MUX
D FF
D FF
clk
shift
Q3
Q2
Fig. 7 Block diagram for 4-bit shift register
Fig. 8 QCA implementation of 4-bit shift register
Q1
Q0
An Efficient Single-Layer Crossing Based 4-Bit Shift Register …
321
5 Simulation Results
Simulator QCADesigner-2.0.3 has been used to verify the designs functionality
[20]. The simulation engine used bistable approximation with default parameters
values. The simulation results of the 2:1 multiplexer are presented in Fig. 9a. For
better readability, we have included only the clock zone 1 at which a valid output is
expected. Table 1 summarizes a comparison between considered 2:1 multiplexers.
It indicates the superiority of the presented 2:1 multiplexer by achieving a minimal
area–delay product (ADP) with lesser complexity.
Fig. 9 a Simulations of 2:1 multiplexer. b Simulations of level trigger D flip-flop
Table 1 Comparison of QCA 2:1 multiplexers
2:1
multiplexer
Area
(µm)2
Cell
count
Delay
Clock
phases
ADP
Crossover
type
[9]
[10]
[11]
[12]
[13]
[14]
[15]
Proposed
0.14
0.14
0.08
0.06
0.07
0.03
0.02
0.016
88
66
46
36
56
27
26
18
1
1
1
1
1
0.75
0.5
0.5
4
4
4
4
4
3
2
2
0.14
0.14
0.08
0.06
0.07
0.022
0.01
0.008
Co-planar
Co-planar
Multilayer
Multilayer
Co-planar
Co-planar
Co-planar
Co-planar
322
T.N. Sasamal et al.
Table 2 Comparison of QCA D flip-flops
QCA D flip-flop (level
trigger)
Area
(µm)2
Cell
count
Delay
Clock
phases
ADP
Crossover
type
[5]
[6]
Proposed
0.08
0.05
0.025
66
48
26
1.5
1
0.75
6
4
3
0.12
0.05
0.01
Co-planar
Co-planar
Co-planar
Fig. 10 Simulation result of proposed 4:1 multiplexer
An Efficient Single-Layer Crossing Based 4-Bit Shift Register …
323
Table 3 Comparison of proposed 4:1 multiplexer with existing designs
4:1
multiplexer
Area
(µm)2
Cell
count
Delay
[13]
0.24
215
1.25
[14]
–
94
[15]
0.24
Proposed
0.24
Clock
phases
ADP
Crossover
type
Maximum
QCA line
length
Minimum
QCA line
length
5
0.3
10
2
1.75
7
–
15
1
161
3.5
14
0.84
>30
1
169
2
8
0.48
Co-planar
(45°, 90°)
Co-planar
(45°, 90°)
Co-planar
(45°, 90°)
Co-planar
(90°)
12
2
Fig. 11 a Simulation of the 4-bit shift register, when shift = ‘1’ (SIPO), b Simulation of the 4-bit
shift register, when shift = ‘0’ (PIPO)
Simulation results of level trigger D flip-flop are illustrated in Fig. 9b. The input
and output waveforms confirm the correct operation of the D flip-flop during clock
zone 3. Table 2 summarizes a comparative analysis of various D flip-flops, and
shows our D flip-flop is better in terms of all design parameters when compared
with previous designs [5, 6].
Simulation results of proposed 4:1 multiplexer are depicted in Fig. 10, which
validates the correct operation of the design. For instance, when the select lines
S0 = ‘0’ and S1 = ‘0’ the multiplexer allows only I0 signal to the output. The output
gets the correct input after 2 clock cycles which is more than the previous designs
[13, 14], due to the inclusion of single-layer crossing using two cells.
324
T.N. Sasamal et al.
However, the proposed design is less sensitive to defects because of single-cell
crossing in single QCA layout. In addition to this, our design is more robust as it
maintains minimum and maximum QCA line length of 2 and 12, respectively, in a
single clock zone. Table 3 shows a comparison of presented design with prior
deigns [13–15] taking all the design parameters and it is worth noticing that the
ADP of proposed 4:1 multiplexer is almost close to the existing ones. Serial Input
Serial Output (SIPO) operation of 4-bit shift register is verified by making enable
signal (shift) = ‘1’ as depicted in Fig. 11a. The input signal on shift-in shifted from
Q3 to Q0 (latched output of D flip-flop) after a delay of 9 clock cycles. When
shift = ‘0’, the shift register operates in Parallel Input Parallel Output (PIPO) mode
and the binary parallel input data are registered as shift register outputs after a delay
of 2.25 clock delays shown in Fig. 11b. The proposed 4-bit shift register requires
area of 1.4 µm2, cell count of 889, and 36 clock phases delay.
6 Conclusion
In this work, a robust design for QCA-based multiplexer and shift register is presented using majority gates. Proposed 2:1 multiplexer achieved lesser QCA area
and faster than the existing designs. Therefore, an optimal 4:1 multiplexer and a
4-bit shift register have been designed using the proposed 2:1 multiplexer. All the
proposed designs are based on co-planar non-crossover wires. Simulations using
QCADesigner tool indicate that the presented designs achieve considerable
improvements in terms of complexity, area usage, and area-to-delay product.
References
1. Navi, K., Sayedsalehi, S., Farazkish, R., Azghadi, M.R.: Five-input majority gate, a new
device for quantum-dot cellular automata. J. Comput. Theory Nanosci. 7, 1546–1553 (2010)
2. Navi, K., Farazkish, R., Sayedsalehi, S., Azghadi, M.R.: A new quantum-dot cellular
automata full-adder. Microelectron. J. 41, 820–826 (2010)
3. Hashemi, S., Tehrani, M., Navi, K.: An efficient quantum-dot cellular automata full-adder.
Sci. Res. Essays 7, 177–189 (2012)
4. Sasamal, T.N., Singh, A.K., Ghanekar, U.: Design of non-restoring binary array divider in
majority logic-based QCA. Electron. Lett. (2016). doi:10.1049/el.2016.3188
5. Vetteth, A., Walus, K., Dimitrov, V.S., Jullien, G.A.: Quantum-dot cellular automata of
flip-flops. ATIPS Laboratory 2500 University Drive, N.W., Calgary, Alberta, Canada T2 N
1N4 (2003)
6. Hashemi, S., Navi, K.: New robust QCA D flip flop and memory structures. Microelectron.
J. 43, 929–940 (2012)
7. Sasamal, T.N., Singh, A.K., Mohan, A.: An optimal design of full adder based on 5-input
majority gate in coplanar quantum-dot cellular automata. Optik 127(20), 8576–8591 (2016)
8. Sasamal, T.N., Singh, A.K., Mohan, A.: Efficient design of reversible alu in quantum-dot
cellular automata. Optik 127(15), 6172–6182 (2016)
An Efficient Single-Layer Crossing Based 4-Bit Shift Register …
325
9. Kim, K., Wu, K., Karri, R.: The robust QCA adder designs using composable QCA building
blocks. IEEE Trans. Comput. Aid. Des. Integr. Circuits Syst. 26, 76–183 (2007)
10. Mardiri, V., Mizas, C., Fragidis, L., Chatzis, V.: Design and simulation of a QCA 2 to 1
multiplexer. In: The 12th WSEAS International Conference on Computers, Heraklion,
Greece, pp. 511–516 (2008)
11. Teodsio, T., Sousa, L.: QCA-LG: A tool for the automatic layout generation of QCA
combinational circuits. In: The 25th IEEE Norchip Conference, Aalborg, pp. 1–5 (2007)
12. Hashem, S., Azghadi, M., Zakerol hosseini, A.: A novel QCA multiplexer design. In: The
International Symposium on Telecommunications, pp. 692–696 (2008)
13. Mardiris, V.A., Karafyllidis, I.G.: Design and simulation of modular 2n to 1 quantum-dot
cellular automata (QCA) multiplexers. Int. J. Circuit Theory Appl. 38, 771–785 (2010)
14. Roohi, A., Khademolhosseini, H., Sayedsalehi, S., Navi, K.: A novel architecture for
quantum-dot cellular automata multiplexer. Int. J. Comput. Sci. 8, 55–60 (2011)
15. Nadooshan, R.S., Kianpour, M.: A novel QCA implementation of MUX-based universal shift
register. J. Comput. Electron. 13, 198–210 (2014)
16. Wang, Y., Lieberman, M.: Thermodynamic behavior of molecular-scale quantum-dot cellular
automata (QCA) wires and logic devices. IEEE Trans. Nanotechnol. 3, 368–376 (2004)
17. Lent, C.S., Liu, M., Lu, Y.: Bennett clocking of quantum-dot cellular automata and the limits
to binary logic scaling. Nanotechnology 17, 4240–4251 (2006)
18. Shin, S.H., Jeon, J.C., Yoo, K.Y.: Design of wire-crossing technique based on difference of
cell state in quantum-dot cellular automata. Int. J. Control Autom. 7(4), 153–164 (2014)
19. Yang, X., Cai, L., Zhao, X.: Low power dual-edge triggered flip-flop structure in quantum dot
cellular automata. Electron. Lett. 46, 825–826 (2010)
20. Walus, K., Dysart, T.J., Jullien, G.A., Budiman, R.A.: QCA designer: a rapid design and
simulation tool for quantum-dot cellular automata. IEEE Trans. Nanotechnol. 3, 26–31 (2004)
Документ
Категория
Без категории
Просмотров
3
Размер файла
835 Кб
Теги
978, 981, 4603
1/--страниц
Пожаловаться на содержимое документа