close

Вход

Забыли?

вход по аккаунту

?

labasapr3 (1) (3)

код для вставкиСкачать
ФБГОУ ВПО "НИУ "МЭИ"
Лабораторная работа №3
по дисциплине
"Инженерное проектирование и САПР"
Выполнила: Гавриков А. О.
Группа: А-08-09
Москва, 2013
1. Код элемента library IEEE; use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
entity arb is
Port ( X : in STD_LOGIC_VECTOR (2 downto 0);
CLK : in STD_LOGIC;
RES : in STD_LOGIC;
Y : out STD_LOGIC_VECTOR (1 downto 0));
end arb;
architecture Behavioral of arb is
shared variable status:integer:=0;
begin
process(CLK, RES) variable I:integer:=0;
begin
if RES='1' then
status:=0; Y<="00";
elsif CLK'Event AND CLK='1' then
I:=status;
ch:loop
exit when i>=2;
if X(I)='1' then Y<=STD_LOGIC_VECTOR(to_unsigned(I,2));
status:=status+1;
if status=3 then status:=0; end if;
exit ch;
end if;
status:=status+1;
if status=3 then status:=0; end if;
I:=I+1;
end loop;
end if;
end process;
end Behavioral;
2. Код теста
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;
ENTITY main_main_sch_tb IS
END main_main_sch_tb;
ARCHITECTURE behavioral OF main_main_sch_tb IS COMPONENT main
PORT( CLK:INSTD_LOGIC; RES:INSTD_LOGIC; X:INSTD_LOGIC_VECTOR (2 DOWNTO 0); Y:OUTSTD_LOGIC_VECTOR (1 DOWNTO 0));
END COMPONENT;
SIGNAL CLK:STD_LOGIC;
SIGNAL RES:STD_LOGIC;
SIGNAL X:STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL Y:STD_LOGIC_VECTOR (1 DOWNTO 0);
BEGIN
UUT: main PORT MAP(
CLK => CLK, RES => RES, X => X, Y => Y
);
-- *** Test Bench - User Defined Section ***
click : PROCESS
begin
CLK<='1'; wait for 20ns;
CLK<='0'; wait for 20ns;
end process;
tb : PROCESS
BEGIN
RES<='0';
X<="010"; wait for 200ns;
X<="111"; wait for 200ns;
X<="110"; wait for 200ns;
END PROCESS;
-- *** End Test Bench - User Defined Section ***
END;
Временные диаграммы
2.1. Временные диаграммы поведенческого моделирования
2.2. Временные диаграммы посттрассировочного моделирования
3. Схемы
4.1 RTL схема4.2 Technology схема
5. Отчеты
5.1 Synthesis report
Release 14.2 - xst P.28xd (nt)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.17 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.19 secs
--> Reading design: total.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
9.1) Device utilization summary
9.2) Partition Resource Summary
9.3) TIMING REPORT
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "total.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "total"
Output Format : NGC
Target Device : xc3s200-4-ft256
---- Source Options
Top Module Name : total
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : LUT
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : Yes
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : Yes
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : Auto
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 100000
Add Generic Clock Buffer(BUFG) : 8
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : Auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Keep Hierarchy : No
Netlist Hierarchy : As_Optimized
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : Maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file "E:/Laby/Poliakov/ZAD_2013/A_9_9/lab22konovalova/antidr.vhd" in Library work.
Architecture poved of Entity rst is up to date.
Compiling vhdl file "E:/Laby/Poliakov/ZAD_2013/A_9_9/lab22konovalova/sdvig.vhd" in Library work.
Architecture behavioral of Entity sdvig is up to date.
Compiling vhdl file "E:/Laby/Poliakov/ZAD_2013/A_9_9/lab22konovalova/total.vhd" in Library work.
Architecture behavioral of Entity total is up to date.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for entity <total> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <rst> in library <work> (architecture <poved>).
Analyzing hierarchy for entity <sdvig> in library <work> (architecture <behavioral>).
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing Entity <total> in library <work> (Architecture <behavioral>).
Entity <total> analyzed. Unit <total> generated.
Analyzing Entity <rst> in library <work> (Architecture <poved>).
Entity <rst> analyzed. Unit <rst> generated.
Analyzing Entity <sdvig> in library <work> (Architecture <behavioral>).
Entity <sdvig> analyzed. Unit <sdvig> generated.
=========================================================================
* HDL Synthesis *
=========================================================================
Performing bidirectional port resolution...
Synthesizing Unit <rst>.
Related source file is "E:/Laby/Poliakov/ZAD_2013/A_9_9/lab22konovalova/antidr.vhd".
WARNING:Xst:737 - Found 1-bit latch for signal <Q>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
Unit <rst> synthesized.
Synthesizing Unit <sdvig>.
Related source file is "E:/Laby/Poliakov/ZAD_2013/A_9_9/lab22konovalova/sdvig.vhd".
Found 1-bit register for signal <y1>.
Found 1-bit register for signal <y2>.
Found 2-bit register for signal <r_s>.
Summary:
inferred 4 D-type flip-flop(s).
Unit <sdvig> synthesized.
Synthesizing Unit <total>.
Related source file is "E:/Laby/Poliakov/ZAD_2013/A_9_9/lab22konovalova/total.vhd".
Unit <total> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# Registers : 3
1-bit register : 2
2-bit register : 1
# Latches : 1
1-bit latch : 1
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
INFO:Xst:2261 - The FF/Latch <r_s_0> in Unit <el2> is equivalent to the following FF/Latch, which will be removed : <y1> INFO:Xst:2261 - The FF/Latch <r_s_1> in Unit <el2> is equivalent to the following FF/Latch, which will be removed : <y2> =========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# Registers : 4
Flip-Flops : 4
# Latches : 1
1-bit latch : 1
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
INFO:Xst:2261 - The FF/Latch <r_s_0> in Unit <sdvig> is equivalent to the following FF/Latch, which will be removed : <y1> INFO:Xst:2261 - The FF/Latch <r_s_1> in Unit <sdvig> is equivalent to the following FF/Latch, which will be removed : <y2> Optimizing unit <total> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block total, actual ratio is 0.
Final Macro Processing ...
=========================================================================
Final Register Report
Macro Statistics
# Registers : 2
Flip-Flops : 2
=========================================================================
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : total.ngr
Top Level Output File Name : total
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : No
Design Statistics
# IOs : 7
Cell Usage :
# BELS : 5
# GND : 1
# INV : 1
# LUT2 : 1
# LUT3 : 2
# FlipFlops/Latches : 3
# FDE : 2
# LDPE : 1
# Clock Buffers : 1
# BUFG : 1
# IO Buffers : 7
# IBUF : 5
# OBUF : 2
=========================================================================
Device utilization summary:
---------------------------
Selected Device : 3s200ft256-4 Number of Slices: 2 out of 1920 0% Number of Slice Flip Flops: 3 out of 3840 0% Number of 4 input LUTs: 4 out of 3840 0% Number of IOs: 7
Number of bonded IOBs: 7 out of 173 4% Number of GCLKs: 1 out of 8 12% ---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
S | IBUF+BUFG | 1 |
el1/Q | NONE(el2/r_s_1) | 2 |
-----------------------------------+------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
Asynchronous Control Signals Information:
----------------------------------------
-----------------------------------+------------------------+-------+
Control Signal | Buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
el1/Q_and0000(el1/Q_and00001:O) | NONE(el1/Q) | 1 |
-----------------------------------+------------------------+-------+
Timing Summary:
---------------
Speed Grade: -4
Minimum period: 2.419ns (Maximum Frequency: 413.394MHz)
Minimum input arrival time before clock: 3.652ns
Maximum output required time after clock: 7.241ns
Maximum combinational path delay: No path found
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'el1/Q'
Clock period: 2.419ns (frequency: 413.394MHz)
Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Delay: 2.419ns (Levels of Logic = 1)
Source: el2/r_s_0 (FF)
Destination: el2/r_s_1 (FF)
Source Clock: el1/Q rising
Destination Clock: el1/Q rising
Data Path: el2/r_s_0 to el2/r_s_1
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDE:C->Q 2 0.720 0.945 el2/r_s_0 (el2/r_s_0)
LUT3:I2->O 1 0.551 0.000 el2/r_s_mux0000<1>1 (el2/r_s_mux0000<1>)
FDE:D 0.203 el2/r_s_1
----------------------------------------
Total 2.419ns (1.474ns logic, 0.945ns route)
(60.9% logic, 39.1% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'S'
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset: 3.652ns (Levels of Logic = 2)
Source: R (PAD)
Destination: el1/Q (LATCH)
Destination Clock: S falling
Data Path: R to el1/Q
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 2 0.821 0.877 R_IBUF (R_IBUF)
INV:I->O 1 0.551 0.801 el1/Q_0_not00001_INV_0 (el1/Q_0_not0000)
LDPE:GE 0.602 el1/Q
----------------------------------------
Total 3.652ns (1.974ns logic, 1.678ns route)
(54.1% logic, 45.9% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'el1/Q'
Total number of paths / destination ports: 6 / 4
-------------------------------------------------------------------------
Offset: 2.791ns (Levels of Logic = 2)
Source: x (PAD)
Destination: el2/r_s_1 (FF)
Destination Clock: el1/Q rising
Data Path: x to el2/r_s_1
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 2 0.821 1.216 x_IBUF (x_IBUF)
LUT3:I0->O 1 0.551 0.000 el2/r_s_mux0000<1>1 (el2/r_s_mux0000<1>)
FDE:D 0.203 el2/r_s_1
----------------------------------------
Total 2.791ns (1.575ns logic, 1.216ns route)
(56.4% logic, 43.6% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'el1/Q'
Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Offset: 7.241ns (Levels of Logic = 1)
Source: el2/r_s_0 (FF)
Destination: y1 (PAD)
Source Clock: el1/Q rising
Data Path: el2/r_s_0 to y1
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDE:C->Q 2 0.720 0.877 el2/r_s_0 (el2/r_s_0)
OBUF:I->O 5.644 y1_OBUF (y1)
----------------------------------------
Total 7.241ns (6.364ns logic, 0.877ns route)
(87.9% logic, 12.1% route)
=========================================================================
Total REAL time to Xst completion: 6.00 secs
Total CPU time to Xst completion: 6.34 secs
--> Total memory usage is 146500 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 1 ( 0 filtered)
Number of infos : 5 ( 0 filtered)
5.2 Translation report
Release 14.2 ngdbuild P.28xd (nt64)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Command Line: C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe
-intstyle ise -dd _ngo -nt timestamp -uc total.ucf -p xc3s200-ft256-4 total.ngc
total.ngd
Reading NGO file "D:/users/lab22konovalova/total.ngc" ...
Gathering constraint information from source properties...
Done.
Annotating constraints to design from ucf file "total.ucf" ...
Resolving constraint associations...
Checking Constraint Associations...
Done...
Checking expanded design ...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Total memory usage is 150032 kilobytes
Writing NGD file "total.ngd" ...
Total REAL time to NGDBUILD completion: 5 sec
Total CPU time to NGDBUILD completion: 3 sec
Writing NGDBUILD log file "total.bld"...
5.3 Map report
Release 14.2 Map P.28xd (nt64)
Xilinx Mapping Report File for Design 'total'
Design Information
------------------
Command Line : map -intstyle ise -p xc3s200-ft256-4 -cm area -ir off -pr off
-c 100 -o total_map.ncd total.ngd total.pcf Target Device : xc3s200
Target Package : ft256
Target Speed : -4
Mapper Version : spartan3 -- $Revision: 1.55 $
Mapped Date : Wed Oct 23 10:46:56 2013
Design Summary
--------------
Number of errors: 0
Number of warnings: 0
Logic Utilization:
Total Number Slice Registers: 3 out of 3,840 1%
Number used as Flip Flops: 2
Number used as Latches: 1
Number of 4 input LUTs: 3 out of 3,840 1%
Logic Distribution:
Number of occupied Slices: 3 out of 1,920 1%
Number of Slices containing only related logic: 3 out of 3 100%
Number of Slices containing unrelated logic: 0 out of 3 0%
*See NOTES below for an explanation of the effects of unrelated logic.
Total Number of 4 input LUTs: 3 out of 3,840 1%
Number of bonded IOBs: 7 out of 173 4%
Number of BUFGMUXs: 1 out of 8 12%
Average Fanout of Non-Clock Nets: 1.86
Peak Memory Usage: 228 MB
Total REAL time to MAP completion: 6 secs Total CPU time to MAP completion: 1 secs NOTES:
Related logic is defined as being logic that shares connectivity - e.g. two
LUTs are "related" if they share common inputs. When assembling slices,
Map gives priority to combine logic that is related. Doing so results in
the best timing performance.
Unrelated logic shares no connectivity. Map will only begin packing
unrelated logic into a slice once 99% of the slices are occupied through
related logic packing.
Note that once logic distribution reaches the 99% level through related
logic packing, this does not mean the device is completely utilized.
Unrelated logic packing will then begin, continuing until all usable LUTs
and FFs are occupied. Depending on your timing budget, increased levels of
unrelated logic packing may adversely affect the overall timing performance
of your design.
Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Timing Report
Section 11 - Configuration String Information
Section 12 - Control Set Information
Section 13 - Utilization by Hierarchy
Section 1 - Errors
------------------
Section 2 - Warnings
--------------------
Section 3 - Informational
-------------------------
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
rate limited output drivers. The delay on speed critical single ended outputs
can be dramatically reduced by designating them as fast outputs.
Section 4 - Removed Logic Summary
---------------------------------
1 block(s) optimized away
Section 5 - Removed Logic
-------------------------
Optimized Block(s):
TYPE BLOCK
GND XST_GND
To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.
Section 6 - IOB Properties
--------------------------
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB |
| | | | | Term | Strength | Rate | | | Delay |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| R | IOB | INPUT | LVCMOS25 | | | | | | |
| S | IOB | INPUT | LVCMOS25 | | | | | | |
| lf | IOB | INPUT | LVCMOS25 | | | | | | |
| sh | IOB | INPUT | LVCMOS25 | | | | | | |
| x | IOB | INPUT | LVCMOS25 | | | | | | |
| y1 | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| y2 | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
Section 7 - RPMs
----------------
Section 8 - Guide Report
------------------------
Guide not run on this design.
Section 9 - Area Group and Partition Summary
--------------------------------------------
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Area Group Information
----------------------
No area groups were found in this design.
----------------------
Section 10 - Timing Report
--------------------------
This design was not run using timing mode.
Section 11 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings
Section 12 - Control Set Information
------------------------------------
No control set information for this architecture.
Section 13 - Utilization by Hierarchy
-------------------------------------
Use the "-detail" map option to print out the Utilization by Hierarchy section.
5.4 Place and Route report
Release 14.2 par P.28xd (nt)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
2-9:: Mon Dec 09 15:08:05 2013
par -w -intstyle ise -ol high -t 1 arb_map.ncd arb.ncd arb.pcf Constraints file: arb.pcf.
Loading device for application Rf_Device from file '3s200.nph' in environment e:\Xilinx\14.2\ISE_DS\ISE\.
"arb" is an NCD, version 3.2, device xc3s200, package ft256, speed -4
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:54 - 'xc3s200' is a WebPack part.
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue
to function, but you no longer qualify for Xilinx software updates or new releases.
----------------------------------------------------------------------
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
-x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
internal clocks in this design. Because there are not defined timing requirements, a timing score will not be
reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock.
Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high".
Device speed data version: "PRODUCTION 1.39 2012-07-09".
Device Utilization Summary:
Number of BUFGMUXs 1 out of 8 12%
Number of External IOBs 7 out of 173 4%
Number of LOCed IOBs 6 out of 7 85%
Number of Slices 5 out of 1920 1%
Number of SLICEMs 0 out of 960 0%
Overall effort level (-ol): High Placer effort level (-pl): High Placer cost table entry (-t): 1
Router effort level (-rl): High Starting initial Timing Analysis. REAL time: 1 secs Finished initial Timing Analysis. REAL time: 1 secs Starting Placer
Total REAL time at the beginning of Placer: 1 secs Total CPU time at the beginning of Placer: 1 secs Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:ca0d551) REAL time: 1 secs Phase 2.7 Design Feasibility Check
INFO:Place:834 - Only a subset of IOs are locked. Out of 7 IOs, 6 are locked and 1 are not locked. If you would like to
print the names of these IOs, please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1. Phase 2.7 Design Feasibility Check (Checksum:ca0d551) REAL time: 1 secs Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:ca0d551) REAL time: 1 secs Phase 4.2 Initial Clock and IO Placement
.........
.........
WARNING:Place:1019 - A clock IOB / clock component pair have been found that are not placed at an optimal clock IOB /
clock site pair. The clock component <CLK_BUFGP/BUFG> is placed at site <BUFGMUX0>. The IO component <CLK> is placed
at site <L14>. This will not allow the use of the fast path between the IO and the Clock buffer. This is normally an
ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN <CLK.PAD> allowing your design to continue.
This constraint disables all clock placer rules related to the specified COMP.PIN. The use of this override is highly
discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in
the design.
Phase 4.2 Initial Clock and IO Placement (Checksum:df77351) REAL time: 3 secs Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:df77351) REAL time: 3 secs Phase 6.3 Local Placement Optimization
.........
Phase 6.3 Local Placement Optimization (Checksum:eb35549) REAL time: 3 secs Phase 7.5 Local Placement Optimization
Phase 7.5 Local Placement Optimization (Checksum:eb35549) REAL time: 3 secs Phase 8.8 Global Placement
..
Phase 8.8 Global Placement (Checksum:2c507227) REAL time: 4 secs Phase 9.5 Local Placement Optimization
Phase 9.5 Local Placement Optimization (Checksum:2c507227) REAL time: 4 secs Phase 10.18 Placement Optimization
Phase 10.18 Placement Optimization (Checksum:2dbd815e) REAL time: 4 secs Phase 11.5 Local Placement Optimization
Phase 11.5 Local Placement Optimization (Checksum:2dbd815e) REAL time: 4 secs Total REAL time to Placer completion: 4 secs Total CPU time to Placer completion: 4 secs Writing design to file arb.ncd
Starting Router
Phase 1 : 46 unrouted; REAL time: 4 secs Phase 2 : 42 unrouted; REAL time: 4 secs Phase 3 : 11 unrouted; REAL time: 4 secs Phase 4 : 12 unrouted; (Par is working to improve performance) REAL time: 4 secs Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 4 secs Updating file: arb.ncd with current fully routed design.
Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 4 secs Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 4 secs Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 4 secs Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 4 secs Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 4 secs Total REAL time to Router completion: 4 secs Total CPU time to Router completion: 4 secs Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| CLK_BUFGP | BUFGMUX0| No | 4 | 0.000 | 1.011 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.
Timing Score: 0 (Setup: 0, Hold: 0)
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing | | Slack | Achievable | Errors | Score ----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net CLK | SETUP | N/A| 2.530ns| N/A| 0
_BUFGP | HOLD | 1.244ns| | 0| 0
----------------------------------------------------------------------------------------------------------
All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
Generating Pad Report.
All signals are completely routed.
Total REAL time to PAR completion: 5 secs Total CPU time to PAR completion: 5 secs Peak Memory Usage: 142 MB
Placement: Completed - No errors found.
Routing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 1
Number of info messages: 2
Writing design to file arb.ncd
PAR done!
Документ
Категория
Рефераты
Просмотров
37
Размер файла
184 Кб
Теги
labasapr
1/--страниц
Пожаловаться на содержимое документа