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Синхронный счётчик со сквозным переносом на синхронных двухступенчатых JK-триггерах с запрещающим ин-вертором

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15 вар
Элемент и-не для 3 элементов
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity n_and is
port(
a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
y : out STD_LOGIC
);
end n_and;
--}} End of automatically maintained section
architecture n_and of n_and is
begin
y <= not(a and b and c) after 1ns;
-- enter your statements here --
end n_and;
Элемент и-не для 2ух элементов
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity n_2and is
port(
p : in STD_LOGIC;
r : in STD_LOGIC;
s : out STD_LOGIC
);
end n_2and;
--}} End of automatically maintained section
architecture n_2and of n_2and is
begin
s<= not (p and r) after 1ns;
-- enter your statements here --
end n_2and;
инвектор
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity N_a is
port(
x : in STD_LOGIC;
nx : out STD_LOGIC
);
end N_a;
--}} End of automatically maintained section
architecture N_a of N_a is
begin
nx<= not x after 1ns;
-- enter your statements here --
end N_a;
jk триггер c запр инвертором
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity JK_trigger is
port(
Ja : in STD_LOGIC;
J : in STD_LOGIC;
C : in STD_LOGIC;
K : in STD_LOGIC;
Ka : in STD_LOGIC;
Q : out STD_LOGIC;
NQ : out STD_LOGIC
);
end JK_trigger;
--}} End of automatically maintained section
architecture JK_trigger of JK_trigger is signal Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8,NC : STd_logic;
component n_and
port(
a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
y : out STD_LOGIC
);
end component n_and; component N_a
port(
x : in STD_LOGIC;
nx : out STD_LOGIC
);
end component N_a;
component n_2and
port(
p : in STD_LOGIC;
r : in STD_LOGIC;
s : out STD_LOGIC
);
end component n_2and;
begin
n_and_1: n_and port map (J,C,Q8,Q1);
n_and_2: n_and port map (K,C,Q7,Q2);
n_and_3: n_and port map (Q1,Ja,Q4,Q3);
n_and_4: n_and port map (Q2,Ka,Q3,Q4);
N_a_1: N_a port map (C,NC);
n_2and_1: n_2and port map (Q3,NC,Q5);
n_2and_2: n_2and port map (Q4,NC,Q6);
n_and_6: n_and port map (Ja,Q8,Q5,Q7);
n_and_7: n_and port map (Ka,Q7,Q6,Q8);
Q<=Q7;
NQ<=Q8;
-- enter your statements here --
end JK_trigger;
конъюнктор для переноса счётчика
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity sum2 is
port(
a : in STD_LOGIC;
b : in STD_LOGIC;
y : out STD_LOGIC
);
end sum2;
--}} End of automatically maintained section
architecture sum2 of sum2 is
begin
y<= (a and b) after 1ns;
-- enter your statements here --
end sum2;
синхронный счётчик
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity schet is generic(
N : integer := 4
);
port(
R : in STD_LOGIC;
C : in STD_LOGIC;
J : in STD_LOGIC;
K : in STD_LOGIC;
Q : out STD_LOGIC_Vector(N-1 downto 0);
NQ : out STD_LOGIC_Vector(N-1 downto 0);
Jk : out STD_LOGIC
);
end schet;
--}} End of automatically maintained section
architecture schet of schet is component sum2
port(
a : in STD_LOGIC;
b : in STD_LOGIC;
y : out STD_LOGIC
);
end component sum2; component jk_trigger
port(
ja : in STD_LOGIC;
j : in STD_LOGIC;
c : in STD_LOGIC;
k : in STD_LOGIC;
ka : in STD_LOGIC;
q : out STD_LOGIC;
nq : out STD_LOGIC
);
end component jk_trigger; signal SQ : STD_LOGIC_Vector(N downto 0); signal J0 : STD_LOGIC_Vector(N downto 0); signal K0 : STD_LOGIC_Vector(N downto 0); signal Q0 : STD_LOGIC_Vector(N-1 downto 0);
begin
J0(0)<='1';
K0(0)<='1'; sum2_1:sum2 port map (J0(0),K0(0),SQ(0));
schet: for i in 0 to N-1 generate
jk_trigger: jk_trigger port map ('1', J0(i), C, K0(i), R, Q0(i),NQ(i));
sum2_2:sum2 port map (Q0(i),SQ(i),SQ(i+1));
J0(i+1)<=SQ(i+1);
K0(i+1)<=SQ(i+1);
Q(i)<=Q0(i);
end generate; -- enter your statements here --
end schet;
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