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Патент USA US2404047

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July l5, 1946.
L. E. FLORY ET AL
2,404,047
ELECTRONIC COMPUTïNG DEVICE
Filed Jan. 21, 1943
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2,404,047
Psrented July 1s, i946
UNITED STATES PATENT CFFICE
2,404,047
ELECTRONIC COMPUTING DEVICE
Leslie E. Flory and George A. Morton, Princeton,
N. J., assignors to Radio Corporation of
America, a corporatlonof Delaware
Application January 21, 1943, serial No. 413,146
7 claims.
(o1. 23S-61)
1
2
, binary multiplicand added tothe same multipli
This invention relates generally to electronic ~ cand once for each occurrence of a binary l in
computers and particularly to electronic appara
tus for counting voltage pulses, and for deriving
the product, or solving quadratic functions of
quantities represented by groups of such pulses.
The basic circuit utilized in adapting the inven
the multiplier, and in which successively added
numbers are stepped along one step on. the inter
mediate product for each term in the multiplier.
The binary system of computation is particu
tion to the various circuits to be described is the
well known “trigger” circuit of the general type
described in “Theory and Application of Vacuum
Tubes," by Herbert J. Reich.
In one of its sim
plest forms, this trigger circuit includes two tri
io
larly suited to electronic .computers since a com
plete binary term of a binary number may be ex
pressed in terms of the conducting or cut-off con
dition oi the anode circuit of a conventional vac
uum tube. vA saving in the number of tubes re
quired for a given number is also possible in a
ratio of 3 to 1 over a numerical system utilizing
a radix of l0. A description of the binary system
of computation may be found in “Elementary
odes in which the grid of the first triode is cou
pled to the anode of the second triode -through
a network comprising a parallel connected re
sistor and capacitor, and the grid of the second 15 Number` Theory,” by Uspenski and Heaslet.
triode is similarly coupled to the anode of the first
In order to operate a counter utilizing the bi
triode through a similar coupling network. The
nary system, it is necessary to adapt the conven
cathodes of both triodes are grounded, either di
tional trigger circuit described heretofore to ef
rectly, or through suitable cathode resistors.
fect a reversal in polarization or activization by
Grid and anode potentials are applied to the re
succeeding applied pulses of a similar nature.
spective electrodes through separate resistors. If
Some of the circuits, described hereinafter, are
desired, a gaseous discharge tube may be con
adapted to this purpose by applyingin a sym
nected across one of the anode resistors to indi
metrical manner negative operating pulses to the
cate circuit operation.
anode circuits of the trigger tubes. Other trigger
In operation, if a negative voltage is applied to 25 circuits utilized herein include grid resistors of
the grid of the first triode, the anode current of
different values in the two tubes of the trigger
the triode will be reduced and the anode poten
circuit. When a control pulse or potential is
tial will become more positive.
Due to the con
applied to the symmetrical point in the trigger
nection through the coupling resistor, the grid
circuit anode circuit, temporary unbalance oc
potential of the second triode will become more 30 curs, the polarization of the trigger tubes is re
positive, causing an increase in the anode-current
versed, and then, after some predetermined time
of the second triode, with a resultant decrease in
interval, the trigger circuit returns to its original
the second triode anode potential. This decrease
stable condition. The instant invention utilizes
in anode potential will, in turn, cause the grid po
“slideback" trigger circuits of this typeïfor step
tential of the first triode to become more nega
ping the product along a product counter which
tive. This action will continue until the anode
comprises a plurality of symmetrical 'trigger cir
current of the iirst triode is cut off. The first
cuits of the type ñrst described. "_I‘lie ‘fslidebac‘k”
triode will remain cut off, and the second triode
trigger circuits also provide the carryover pulses
will remain conducting, until a positive potential
to the next succeeding product trigger circuits as
is applied to the grid of the first triode or a nega 40 the individual product terms change from binary
tive potential is applied to the grid of the second
l to binary 0.
triode.v In either latter instance, the tube oper
Among the objects of the invention are to pro
ating conditions will be reversed and the first tri
vide a new and improved means for counting
ode will become conducting and the anode current
voltage pulses. Another object is to provide a
45 new and improved means for stepping a number
of the second triode will be cut ofi.
One of the features of the instant invention is ` along a counter comprising a plurality of trigger
the utilization of such trigger circuits in cascade
circuits. Another object of the invention is to
arrangement, whereby a predetermined change
provide improved means for utilizing trigger cir
cuits in a novel cascade arrangement for deriving
the trigger circuit will generate a pulse to trigger 50 the product of quantities represented by the num
or activate a succeeding trigger circuit in the cas
bers of pulses in successive series of voltage pulses.
cade arrangement. As many trigger circuits as
Still another object is to provide an improved
desired may be connected in cascade. The in
means for connecting trigger circuits in cascade
stant invention is an improvement on the copend- '
arrangement to provide a continuous counter. A
ing U, S. application of Leslie E, Flory, Serial No. 55 further object is to provide improved means for
467,229, iiled November 28, 1942, which describes
clearing the counter after each operation thereof,
a device for multiplying two or more binary num
for conditioning the circuit for counting succeed
in the polarization or activization of one triode of
bers.
In the copending application, multiplication is
accomplished by deriving the binary sum of a 60
ing applied pulses. Another object is to provide
a new and improved means for deriving the bi
3
2,404,047
4
nary product of successive series of pulses applied
and the second tube 2 becomes completely con
to a thermionic tube trigger circuit. Still an
other object is to provide a new and improved
means for deriving the binary product of the lbi
nary sums of succeeding series of voltage pulses
wherein the multiplicand and multiplier are ap
plied as binary numbers to separate series of cas
ducting. A subsequent negative pulse applied to
the input terminals I5 will cause the stable con
ditions of the trigger tubes I, 2 to 'be reversed
since the circuit is completely symmetrical.
The indicator tube I3 will be illuminated when
caded trigger circuits. «Another object is to pro
vide new and improved means for generating a
predetermined number of voltage pulses in re
sponse to a single actuation of said means.
The invention will be described by reference
to the accompanying drawings of which Fig. 1 is
10
the second tube 2 is conducting, since only under
this condition is there an appreciable voltage drop
across the anode coupling resistor I0. If it is as
sumed that the conducting condition of the first
tube pI represents zero, and the conducting con
dition oi’ the second tube 2 represents I, the re
sult is a binary counter in which zero is indicated
a schematic circuit diagram of a trigger circuit
which forms part of the computer; Fig. 2 is a 15 on the indicator tube I3 when the tube is ex
tinguished, and I is indicated when the tube is
block circuit diagram of the invention; Fig. 3 is
illuminated. ` The second pulse applied ‘ to the
a partial schematic circuit diagram of the in
input terminals I5 will cut of! the second trigger
vention; Fig. 4 is a graph showing a typical multi
.tube 2 and cause the ilrst tube I to again become
plier pulse train utilized in one embodiment
thereof; Fig. 5 is a block diagram' of a stepping 20 conducting. In order to indicate that two pulses
have occurred instead oi' none, it is essential that
pulse circuit; and Fig. 6 is a schematic circuit
a carryover system be employed which will pro
diagram of a preferred embodiment of the circuit
vide a second indication representative of the
of Fig. 5. Similar reference numerals are ap
second term of the binary total. This feature
plied to similar elements throughout the draw
1118s'.
will be described hereinafter in connection with
25 the totalizer circuit included in Figs. 2 and 3. If
Referring to the drawings, Figure 1 comprises
a carryover circuit is desired for the multiplicand
a trigger circuit of the general type described
set-up device. it may be of the type described in
heretofore. The grid al of a ilrst triode I is con
the copending application mentioned heretofore.
nected to the anode p2 o1' a second triode 2
through a network- comprising the parallel con 30 However, to simplify the present description, it
is assumed that a binary multiplicand is directly
nected resistor 3 and capacitor 4. 'I'he anode pI
set up on the multiplicand set-up device. through
of the nrst triode I is connected to the grid g2
the separate input terminals I5, I5', I5", I5'" of
of the second triode 2 through a second network
Fig. 2.
»
comprising the parallel connected resistor 5 and
Figure
2
comprises
a block diagram of an elec
capacitor 6. The cathodes of the ñrst and second
tronic multiplying system wherein a multiplicand
triodes. I, 2 are grounded. A source of negative
is set up as a binary number on a series of trig
bias potential c is connected to the grid gI of
ger circuits of the general type described hereto
the ñrst tube I through a grid resistor 1, and to
fore. 'I'he binary multiplicand is then trans
the grid g2 of the second triode 2 through a sec
ond grid resistor 8. The positive terminal oi’ the 40 ferred to a second binary counter upon which the
bias source c is grounded. Anode potential from
binary product is to be established. The circuits
to be described hereinafter accomplish both the
~ a source B is applied to the anode pI of the ilrst
direct transfer of the multiplicand to the totalizer
tube I through an anode coupling resistor 9, and
and the carryover operation required as each ele
to the ~anode p2 of the second tube 2 through a
second anode coupling resistor I0. The negative 45 ment of the totalizer changes from one to zero
in the binary system.
terminal of the anode potential source B is
grounded. A gaseous indicator tube I3, which
Each of the trigger circuits I, II, III, and IV,
oi' the multiplicand set-up device is connected to
may be a conventional neon tube, is connected
a corresponding transfer amplifier 30, 3|, 32 and
across the second anode resistor I0 to indicate
when the anode current exceeds a predetermined 50 33, respectively, in such a manner that when the
counter trigger circuit is in the binary zero con
value, characteristic of the anode current con
dition, the amplifier tube is beyond cutoff or in
ducting condition of the second tube 2. A choking
operative, and when the counter is in the binary
resistor I4 is connected in series with the posi
tive anode power supply lead to the common ter
I condition, the corresponding amplifier is biased
minals of the anode resistors 9 and III. Nega 55 to the anode current cutoiï condition. Pulses or
tive input control pulses are applied to the input
potentials corresponding to the binary multipli
terminals I 5 between ground and the common
cand, are applied, as described heretofore. to the
terminal of the anode resistors 9 and I0. through
input terminals I5, I5', I5", I5"' of the multipli
an input coupling capacitor I6. Any other de
cand binary set-up device to establish the multi
sired input coupling arrangement may be utilized 60 plicand thereon as a binary quantity on the trig
to equal advantage.
ger circuits I, II, IlI and IV. Pulses 49, 50, which
correspond to the presence of binary I terms of
In operation, if it is assumed that the ilrst tube
the kbinary multiplier are successively applied
I initially is drawing anode current. the second
tube 2 will be biased off. A negative pulse applied
simultaneously to al1 of the respectiveV grid cir
to the input terminals I5, will appear on the 65 cuits oi' the transfer amplifiers 30, 3|, 32 and 33.
anode p2 of the tube 2 and on the grid gl of the
Means for deriving the pulses 49, 5II from a binary
first tube I which will in turn make the potential
multiplier will be described hereinafter. The
on the anode pI of the ñrst tube I more posi
multiplier pulses will therefore be transmitted by
tive, and degenerate simultaneously any of the
only the transfer amplifiers which are connected
original negative pulse applied at pI. A positive 70 to the corresponding multiplicand trigger circuits
pulse will be applied to the grid g2 of the tube
which are in the binary I condition.
2 causing the tube 2 to become conducting. This
The pulses transmitted by the respective trans-y
eßect will increase and continue, because of the
fer amplifiers are next applied directly to the
difference in the potential charges on the ca
trigger circuits XV. XVI, XVII and XVIII, re
pacitors 4 and 8, until the first tube I is olli? Oil',
spectively, of the totalizer which includes the
2,404,047
5
input terminals 54 which are connected to the
input circuits of a limiter-phase inverter circuit
trigger circuits XI, XII, XIII, XIV, XV, XVI, XVII
and XVIII, which are also of the type ilrst de
scribed in Fig. 1. The number of trigger circuits
required in the totalizer will be at least one more
than the sum of the number of binary terms
in the multiplicand and multiplier, respectively.
The precise number of trigger circuits will depend
upon the particular multiplication process which
the circuit is required to perform. Indicator
/n/
5I and a delay circuit 52. The limiter circuit
5I clips the amplitude of all of the multiplier
pulses to equal amplitudes, and reverses their
polarity, as indicated by the pulses 49', 48 and
50’. These equal amplitude pulses are connected
to all of the product trigger circuits, through the
switch s2, by means of the lead a. The pulses
lamps may be connected in the anode circuits of 10 transmitted by the delay circuit 52 are'` applied>
to the input of a peak ampliñer 53, which ampli
the individual trigger circuits of the product
counter in the same manner as described hereto
fies only the peaks of pulses having greater ampli
tudes than the pulse 48, which corresponds to a
fore in Figure 1 for the individual trigger cir
binary zero in the multiplier pulse train. ‘The
cuits of the multiplicand set-up device. Like
wise, the anode circuits of the totalizer may be 15 peak pulses 49 and 50 are connected- to the com
mon input circuits of the transfer amplifiers 30.
connected to apply the binary product directly to
3|, 32 and 33 by means of the lead b. It will
other utilization circuits.
'
>therefore be seen that pulses for each term of
The product carryover operation, necessary
the Ibinary multiplier will be applied to the total
when a product term changes from binary I to
binary 0; and the product shifting which is nec 20 izer trigger circuits, while pulses corresponding
to only binary I terms of the multiplier will be
essary after each term of the multiplier is ap
applied to key the input circuits of the transfer
plied to the circuit, are accomplished, as men
amplifiers 30, 3l, 32 and 33 for transferring the
tioned heretofore. by “slideback” type trigger cir
multiplicand from the set-up trigger circuits I,
cuits 40, 4I, 42, 43, 44, 45 and 46. One of these
“slideback” circuits is connected between each of 25 II, III and, IV to the corresponding portion of
the totalizer counter which includes the trigger
the product trigger circuits XI, XII, XIII, XIV,
circuits XV, XVI, XVII and XVIII.
XV, XVI, XVII and XVIII.
Each time the product trigger circuit XVIII
The essential difference between the “slide
changes from binary I to binary zero, a pulse is
back” or carry-over trigger circuits and the `mul
tiplicand and product trigger circuits described 30 applied to key the carryover trigger circuit 46,
which is of the “slideback” type. The carryover
in Fig. 1, is that in the “slideback" circuit the
trigger circuit 46, in turn, delivers' a keying pulse
grid resistor 8 has considerably higher resistance
to the next product trigger circuit XVII which
than the grid resistor 1, whereby an applied in
changes its polarization by one binary value.
put pulse effects a change in circuit polariza
Similar operation, occurs between the totalizer
tion for a predetermined time interval. such as
trigger circuit XVII and the next totalizer cir
for example, ñve microseconds, and then the cir
cuit XVI because of the action of the next inter
cuit resumes its original stable condition. The
connected carryover trigger circuit 45 and the
time interval will be determined by the values of
remaining carryover trigger circuits 40, 4I, 4‘2, 43
the circuit components. In either type of trig
ger _circuit the input control pulses may be ap 40 and 44 operate similarly on the remaining total
izer trigger circuits XI, XII, XIII, XIV and XV.
plied to grid circuits instead of to the sym
Therefore, if a pulse is aplied to the product trig
metrical point of the anode circuits, to provide
ger circuit XVIII such as always to change its
more positive operation.
polarization to correspond to binary zero. a binary
The carryover trigger circuits sequentially per
form both product carryover and product step 45 I will be transferred to the next product trigger
circuit XVII if the'trigger circuit XVIII was origping operations as the multiplier pulses are ap
inally in a binary I condition, but if the circuit
plied to the circuit. Two methods of setting
up the multiplier and applying the multiplier
pulses to the circuit are:
-
Method I
XVIII was originally in a binary zero condition,
no transfer pulse will be transmitted to the to
The effect of this
50 talizer trigger circuit XVII.
circuit operation is to shift the binary product
one position to the left for each application of a
multiplier pulse to the line a which is connected
having low amplitude pulses corresponding to
directly to each of the product trigger circuits,
binary> 0 terms and relatively high amplitude 55 since this pulse initially changes all of these cir
pulses corresponding to binary I terms, this pulse
cuits‘ to binary zero and then transfers any binary
train may be utilized to accomplish the transfer
I terms to the next succeeding trigger circuit by
of the multiplicand to the totalizer, and also the
means of the carryover circuits 40 to 46, inclu
carryover and shifting operations in the product
sive.
The pulse train 41 is delayed an amount equal
counter during the intervals between the applica ,60
to approximately half the time interval between
tion of successive terms, or pulses, of the multi
the successive pulses 49, 48 and 50 of the train
plier to the circuit. Such a pulse trainl is illus
4'I by means of the delay circuit 52. The pulse
trated in Fig. 4 by the graph 4'I, in which .the
If the multiplier is available as a pulse train
highest term of the binary multiplier corresponds
peaks 49 and 59 amplified by the peak amplifier
to the first large pulse 49, and successive multi 65 53 are thence applied through the lead b to key
plier terms are represented by the pulses 48 and
the transfer amplifier 3U, 3|, 32 and 33 to transfer
the binary multiplicand from the multiplicand
50. The pulse train may be derived from an
electronic switch of the,general type described
set`up device to the trigger circuits XV, XVI,
XVII and XVIII of the totalizer. It will -be seen
in the copending application heretofore men
tioned, by applying different potentials, corre 70 that the multiplicand will be transferred to the
sponding to binary I) and binary I terms of the
totalizer once for each pulse on the line b while
multiplier, to separate target electrodes which
the intermediate product will be stepped one
are sequentially scanned once by the electron
position to the left for each of the shifting pulses
beam from an electron gun.
49', >48, 50' on the line a. The ñnal product will
The pulse train 41 is applied to the multiplier 75 appear on the totalizer after all shifting and
2,404,047
7
transfer pulses have been transmitted1_-by`the-
8
cuits in the` manner described in the copending
application to which referencehas previously been
made. Positive’pulses on the lead b correspond
linesaand b.
While no particular circuits have been de
scribed in detail herein for deriving the multi
ing to binary i terms of the multiplier are ap
plier pulse train 41, it should be understood that
plied through' the capacitor-s 63 and Se to the
control electrodes of the transfer 'ampliñers 32
and 33. respectively. A Ibias potential is derived
such a pulse number train may readily be ob
tained by means of the general type of elec
tronic switching device described in the copend
from the cathode of the second tube of the trigger
circuit III and _applied through a grid resistor
ing application mentioned heretofore, or by any
other means known in the art.
10 85 to the control electrode of the transfer am
Method II
A second method of applying the binary mul-l
tiplier to the circuit described heretofore is to
establish directly the binary multiplier on the to
talizer trigger circuits XI, XII, and XIII in the
plifier 32. A second bias potential is derived from
the cathode of the second tube of the trigger cir
cuit IV and applied through a second grid re
sistor B8 to the control electrode of the transfer
amplifier 33.
The anode of the transfer amplifier 32 is con
on the multiplicand set-up device which includes i nected to the symmetrical point 81 of the anode
circuits of the trigger tubes of the totalizer tris
the trigger circuits I, II, III and IV. If now a
ger circuit XVII. The anode of the transfer am
predetermined number of keying pulses are ap
_plied to the line a, by connecting the movable 20 plifier 33 is similarly connected to the symmetri
cal point 68 of the anode circuits of the tubes
element of the switch s2 to the ñxed switch con
of the totalizer trigger circuit XVIII.
tact 54a, the binary multiplier will be stepped ofi'
The anode of the second tube of the totalizer
the last product trigger circuit 1U.
~
trigger circuit XVII is connected through a ca
Pulses derived from the trigger circuit XI are
pacitor 69 and a resistor 10 to the control elec
applied to the input of a second delay circuit 62,
trode of the second tube of the carryover trans
each time the circuit is in the binary I condi
fer trigger circuit 45. Similarly, the anode of the
tion. These derived binary i pulses are then ap
second tube of the totalizer trigger circuit XVIII
` plied to key the transfer ampliñers 3D, 3l, 32
is connected through a capacitor 1I and a re
and 33, when the switch si is closed to connect
the delay circuit thereto. Thus. as the binary 30 sistor 12 to the control electrode of the second
tube of the carryover trigger circuit 48. The
multiplier is stepped oil’ the totalizer, the multi
anode of the second tube of the carryover trig
plicand is transferred to the totalizer foreach
ger circuit 46 is connected through a coupling
binary i term in the multiplier and the succes
capacitor 13 to the symmetrical point in the
sively transferred multiplicand quantities are
anode circuits ' of the totalizer trigger circuit
added to the intermediate product as the prod
same manner as the multiplicand is established
uct is stepped along the product counter for each
term of the multiplier, irrespective-of the -binary
XVII. Similarly, the anode of the second tube
of the carryover trigger circuit 45 is connected
to the symmetrical point in the anode circuits of
the next succeeding totalizer trigger circuit XVI,
This rarrangement also permits the evaluation
not shown.
of quadratic expressions, such as a+(b+c.r) z, by
Negative stepping pulses, derived as described
applying the multiplier a second time to the
heretofore, or in the manner of Figs. 5 and 6.
product counter and repeating the multiplica
are applied through a capacitor 14 and an iso
tion process just described. As a result of the
lating resistor 18 to the control electrode of the
thus repeated multiplication process, the square
first tube of the totalizer trigger circuit XVII.
of the multiplicand will be multiplied by the
Similarly, the negative stepping pulses `are ap
multiplier, and the ñnal product will be indi
plied through a capacitor 15 and an isolating re
cated directly on the totalizer. To simplify the
sistor 11 to the control electrode of the first tube
circuit design, the intermediate products should
of the totalizer trigger circuit XVIII. It should
preferably be added on a separate counter, not
50 be kunderstood that the multiplicand set-up de
shown.
vice trigger circuits III and IV, and the totalizer
.Any well known means of providing the desired
trigger circuits XVII and XVIII are >of the here
number of stepping pulses may be utilized for
stepping the binary multiplier oif the product
in ñrst described type which utilizes symmetri
value of that term.
cal control electrode circuits having substantially
counter. For example, a desired number oi'
pulses corresponding to the number of terms in 55 equal values of grid resistance. The carryover
the multiplier may be applied to a modi?ed linear
trigger circuits 45 and 46 differ from the multi
plicand and product trigger circuits only in that
electronic counter of the cathode ray type de
scribed in the copending U. S. application of ap
the grid circuits are unsymmetrical, since they
plicants, Serial No. 456,012, filed August 25, 1942.
include grid resistors of different values to pro
Then the linear counter may be “uncounted" to 60 vide the “slideback” operation described hereto
deliver the required number of stepping pulses in
rapid succession. Similarly, an electronic switch,
of the type described heretofore, may be utilized,except that a limiter or clipping circuit should
preferably be inserted between the switch and
the line a to provide similar amplitude stepping
pulses for binary terms of all values.
fore, and the control pulses are applied to the
grid circuits instead of to the symmetrical points
in the anode circuits. .
It should be understood that the speciiic meth
ods of coupling the various trigger circuits and
transfer amplifiers may be varied according to
vaccepted engineering practice, providing the
Figure 3 is a schematic circuit diagram of that
portion of the block diagram of Figure 2 which
proper'voltage and phase requirements are main
tained. While some of the trigger circuits de
includes only the multiplicand trigger circuits III 70 scribed herein utilize triodes, it should also be
and IV, the transfer amplifiers 32 and 33, the
understood that multi-grid tubes may be em
totalizer trigger circuits XVII and XVIII and the
ployed throughout to advantage, since the addi
carryover trigger circuits 45 and 46. As ex-.
tional gain, of such tubes may be desirable from
the standpoints of stability and tolerances of the
plained heretofore, the multiplicand may be es
tablished on the various multiplicand trigger cir- - 75
trigger circuit components.
9,404,047
Figure 5 provides a general means for deriv
ing a predetermined number of stepping pulses
in rapid succession upon application thereto of
an initial starting voltage.
A source of oscillations 88, of waveform 8l,
is connected through a pulse shaping circuit 82
to provide sharply defined negative pulses 83.
l0
ing circuit, while opening the switch si changes
the bias on all trigger circuits of the electronic
counter, to restore the counter to any predeter- .
mined initial count. It should be understood that
the essential difference between the counter of‘
Fig. 6 and the counter circuit disclosed in the
copending Flory U. S. application referred to
These negative pulses are then applied simulta
neously, through a switch s4, to a delay circuit
84 and a-switching circuit 85, such as a multi
vibrator. The switching circuit, in response to
the initial negative pulse applied thereto, pro
heretofore, is that in the instant device the initial
count is provided by reversed bias means in one
or more predetermined trigger circuits, (in this
vides a positive bias potential to unblock an am
multiplying operation is completed, by applying
plifier 86. After the amplifier 88 is unblocked,
the delayed pulses are also applied to the am
plifler input circuit. ‘ The output circuit of the
instance, trigger circuit 89) , while feedback means
are provided in the copending application.
All trigger circuits may be cleared, after each
a high negative control electrode bias simul
taneously to all binary I tubes in the manner
which is described, for example, in the copending
ampliiler is next applied to an electronic counter
application mentioned heretofore, or by removing
81, which may be of the general type described
the grid bias from the binary 0 tubes.
in the copending U. S. application of Leslie E.
Thus the invention described comprises an elec
20
Flory, Serial No. 467,032, filed November 28, 1942,
tronic multiplying device in which a multiplicand
in >which any predetermined number of pulses
is applied to a binary set-up device, and trans
applied thereto will provide a control potential
ferred to totalizer a number of timesY correspond
when the counter is ñlled. When the desired
ing to the occurrence of binary I terms in the
number of pulses are counted, the control poten
tial derived from the counter is applied to the 25 multiplier, while simultaneously the intermediate
product is shifting a number of times equal to the
amplifier to bias off the amplifier anode current.’
number of terms in the multiplier. Provision may
Thus a predetermined number of pulses may be
be made in both the multiplicand set-up device
delivered to a load circuit connected to the am
and totalizer to accomplish carryover operations
pliñer output circuit. 'I‘he number of pulses may
required, and to segregate the carryover
be controlled by changing the electronic counter 30 where
operations from the direct applications of the
as described in the copending Flory application.
multiplicand to the product counter.
The circuit may be cleared for a succeeding _op
It should be understood that the particular cir
eration by disconnecting, or stopping the oscilla
cuits described are merely illustrative of one
tion source, and by returning the counter to its
means for accomplishing the invention. Many of
initial operating condition.
the individual circuits may be modified, and the
Figure 6 provides a specific circuit for the op
coupling and control circuits varied in accord
eration generally described in Fig. 5. The os
ance with accepted engineering practice, with
cillator 80 is of the conventional R.-C. type. Its
out deviating from the spirit and scope of the in
output circuit is connected through the conven
tional pulse shaping circuit 82 to provide the 40 vention.
We claim as our invention:
discrete negative pulses 83. The negative pulses
l. A binary multiplying device for two quanti
are then simultaneously applied to key the switch
ties including a first binary counter circuit hav
ing multivibrator 85 which is a symmetrical trig
ing a plurality of trigger circuits, means for apply
ger circuit of the type described heretofore, and
ing one of said quantities to said counter as a
to key the slideback trigger circuit 84 which pro 45 multiplicand, a second `binary counter circuit hav
vides the required delay for the pulses applied
ing a plurality of trigger circuits, means for
to the second control electrode of the amplifier
transferring said multiplicand to said second
tube 88. A positive bias potential is derived from
counter, means for repeating said transfer a num
the cathode circuit of the switching multivibra
ber of times corresponding to the occurrence of
50
tor 85, in response to actuation thereof by the
binary I terms in said other quantity as a multi
initial negative pulse, and is applied to the ñrst
plier, means including a plurality of normally
control electrode of the amplifier tube 86 to un
stable trigger circuits each adapted to polariza
block the tube for amplification of the delayed
tion reversals for predetermined small time in
pulses. The anode circuit of the amplifier 86
tervals for shifting the count on said second
55
is connected to the electronic counter 8l which
counter circuit one binary place a number of
includes the trigger circuits 88, 89, 80, 9|, 92
times corresponding to the number of binary
connected to provide a control potential when a
terms in said multiplier, and means including said
predetermined number of pulses have been count
second counter and said normally stable trigger
ed. In the particular circuit disclosed, opera
circuits for deriving the binary sum of said re
tion of the switch s3 will provide a control pulse 60 peated multiplicands.
for either six or fourteen applied pulses from the
2. A binary multiplying device including a plu
amplifier 86. The control potential is derived
rality of cascaded trigger circuits, means for
from the movable element of the switch s3 and
polarizing said trigger circuits to represent a
applied to the first control electrode of the am
binary multiplicand, a first source of pulses the
pliñer 8G to block the tube anode current. The 65 number of which is representative of the num
number of pulses required for the control poten
ber of binary terms of a multiplier, a second
tial depends upon the particular trigger circuit
source of pulses the number and occurrence of
connected to the movable element of the switch
which correspond to binary I terms of said multi
s3. The predetermined number of pulses are
plier, a plurality of transfer amplifiers, means
70
then derived from the amplifier anode circuit
including predetermined polarization of said
and applied as stepping pulses to the product
trigger circuits for unblocking predetermined ones
counter of the circuit described in Fig. 2.
of said-amplifiers, a plurality of second trigger
The pulse generator may be cleared by opening
circuits, means for applying said second pulses to
the switches s4 and s5. Opening the switch s4
removes the source of oscillations from the count 75 all of saidampiifiers for transferring said multi
2,404,047
plicand to predetermined ones of said second trig
ger circuits for each occurrence of said» second
pulses, means including a plurality of normally
stable trigger circuits each adapted to polariza~
tion reversals for predetermined small time inter
vals, means for applying said first pulses to shirt
’ the count on said second trigger circuits one bina
ry place a number of times corresponding to the
number of binary terms in said multiplier, and
means including said second trigger circuits and
said normally stable trigger circuits for deriving
the binary sum of said repeated multiplicands.
3. A binary multiplying device for two quanti
ties including a ñrst binary counter circuit hav
ing a plurality of trigger circuits, means for ap
plying one of said quantities to said counter as
a multiplicand, a, second binary counter circuit
having a plurality o1’ trigger circuits, a plurality
of blocking amplifiers, means interposing one of
said amplifiers between corresponding trigger
12
,
cult having a plurality of trigger circuits. a plu
rality of blocking amplifiers, means interposing
one of said ampliiiers between corresponding
trigger circuits of said nrst and said second
counters, means including said first counter for
unblocking said ampliiiers for transferring said
multiplicand to said second counter to establish
a product thereon, a source of pulses ci’ sub
stantially square wave form, means for applying
saidl pulses to all o1' said blocking ampliiiers,
means including a predetermined number of said
pulses for repeating said transfer a number 0f
times corresponding to the occurrence of binary l
terms in said other quantity as a multiplier, a,
plurality of normally stable trigger circuits each
adapted to polarization reversals for predeter
mined small time intervals, means including said
normally stable trigger circuits for shifting said
product on said second counter a number of
times corresponding to the number of binary
circuits of said first and said second counters,
terms in said multiplier, and means including
means including said first counter for unblock
said normally stable trigger circuits responsive
ing said amplifiers for transferring ~said multi
to predetermined polarization of each of said
plicand to said second counter to derive a prod
trigger circuits of said second counter for chang
uct thereon, means for repeating said transfer 25 ing the polarization o! succeeding trigger circuits
a number of times corresponding to the occur
of said second counter for deriving the binary
rence of binary 1 terms in said other quantity as
sum of said repeated multiplicands and said shifta multiplier, means including a plurality of nor
ed products.
,
mally stable trigger circuits each adapted to
The combination of iirst and second groups
polarization reversals for predetermined small 30 of 6.trigger
circuits each operable to either of two
time intervals for shifting said product on said
stable conditions, a third group of trigger cir
second counter a number of times corresponding
cuits each operable to stable and unstable oper-to the number of binary terms in said multiplier,
ating conditions, means interconnecting each
and means including said second counter and
trigger circuit of said ilrst group with a differ
said normally stable trigger circuits for deriving 35 ent
trigger circuit of said second group for trans
the binary sum of said repeated multiplicands.
mitting an electrical pulse to the trigger circuit
4. A binary multiplying device for two quanti
of said second group only when the trigger cir
ties including a ñrst binary counter circuit hav
. ing a plurality of trigger circuits, means for ap
cuit of said first group is in a predetermined one
plying one of said quantities to said counter as 40 of said stable conditions, and means connecting
each trigger circuit of said third group between
a multiplicand, a second binary counter circuit .
having a plurality of trigger circuits. a plurality
of blocking ampliiiers, means interposing one of
said ampliñers between corresponding trigger cir
cuits of said iirst and said second counters, means
including said iirst counter for unblocking said
amplifiers for transferring said multiplicand to
said second counter to establish a product there
on, means for repeating said transfer a number
of times corresponding to the occurrence of binary
l terms in said other quantity as a multiplier,
a plurality of normally stable trigger circuits each
adapted to polarization reversals for predeter
mined small time intervals, means including said
normally stable trigger circuits for shifting said
product on said _second counter a number of times
a different pair of the trigger circuits of said f
second group for transmitting an electrical pulse
from a first to a second trigger circuit of said
'_ second group only when a pulseis applied to said
ilrst trigger circuit while it is in a predetermined
one of said stable conditions.
7. The combination of iirst and second groupsy
of trigger circuits each operable to either of two
stable conditions, a third group of trigger circuits
each operable to stable and unstable operating
conditions, means interconnecting each trigger
circuit of said first group with a different trigger
circuit of said second group for transmitting an
electrical pulse to the trigger circuit of said sec
ond group only when the trigger circuit of said
first group is in a predetermined one of said
corresponding to the number of binary terms
stable conditions, means connecting each trigger
in said multiplier, and means including said nor
circuit of said third group between a different
mally stable trigger circuits responsive to pre
ofthe trigger circuits of said second ygroup
determined polarization of each of said trigger 60 pair
for transmitting an electrical pulse from a ilrst
circuits of said second counter for changing the
to a second trigger circuit of said second group
polariaztion of succeeding trigger circuits of- said
only
when a pulse is applied to said iirst trigger
second counter for deriving the binary sum of
circuit
while it is in a predetermined one of said
said repeated multiplicands and said shifted
stable conditions, means for applying stepping
products.
pulses to the trigger circuits of said second group,
5. A binary multiplying device for two quan
and means for applying to said interconnecting
tities including a iirst binary counter circuitr
means signal pulses having a predetermined re
having a plurality of trigger circuits, means for
lation to said stepping pulses.
applying one of said quantities to said counter
LESLIE E. FLORY.
as a multiplicand, a second binary counter cir 70
GEORGE A. MORTON.
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