Патент USA US2409691код для вставки
Ogt. 22, 1946. . a. A. MORTON EI'AL 2,409,689 ELECTRONIC COIIPUTING DEVICE Filed NOV; 2, 1942 "‘q ‘a _ o | - ‘a r ' R V , 2 Sheets-Sheet 2 v ' V ZSnventor: A», ?eoasa-?mok'ron ° Le/ue E. Fboqg 1., E my“ M 2,409,689 Patented Oct. 22, 1946 UNITED STATES PATENT OFFICE 2,409,689 ELECTRONIC COMPUTING DEVICE \ ~ George A. Morton, Haddon Heights, and Leslie E. ‘ Flory, oai?yn, N. 1., asaig-nors to Radio Corpo ration of America, a corporation of Delaware Application November 2, 1942, Serial No. 464,292 8 Claims. (01; 235-81) 1 This invention relates generally to electronic computers and particularly to electronic appa ratus for counting voltage pulses and for adding, subtracting, or multiplying quantities repre sented by groups oi’ such pulses. The basic circuit utilized in adapting the in vention herein to the various circuits to be de scribed in the well known "trigger" circuit of the general type described in “Theory and Ap 2 of our copending U. 8. application, Serial No. 464,293, ?led November 2, 1942, which describes a cascade trigger circuit arrangement for count ing voltage pulses to derive the binary sum, or difference, of successive series of pulses. The in stant invention, however, is adapted to counting voltage pulses and indicating the product of two groups of pulses as a binary number. The binary system of computation is particu plication oi! Vacuum Tubes,” by Herbal; J. Reich. 10 larly suited to electronic computers since a com plete binary term of a binary number may be In one of its simplest forms, this trigger circuit expressed in terms of the conducting or cut-oft includes two triodes in which the grid of the ?rst triode is coupled to the anode of the second triode through a network comprising a par ., condition of the anode circuit of a conventional vacuum tube. A saving in the number of tubes allel connected resistor and capacitor, and the 16 required for a given number is also possible in a ratio of 3 to 1 over the scale of 10 system. More grid of the second triode is similarly coupled to complete discussions of the binary and similar the anode oi’ the ?rst triode through a, similar systems 0! computation may be round in "Ele coupling network. The cathodes of both triodes mentary Number Theory" by Uspenski and are groimded, either directly, or through suitable Heaslet, “Mathematical Excursions" by H. A. 20 cathode resistors. Grid and anode potentials are Merrill, and “A Mathematician Explains" by M. applied to the respective electrodes through sepa I. Logston. rate resistors. If desired, a gaseous discharge In order to operate a counter utilizing the tube may be connected across one of the anode binary system, it is necessary to adapt the con resistors to indicate circuit operation. In operation, it a negative voltage is applied 25 ventional trigger circuit described heretofore to ‘effect a reversal in polarization or activization by to the grid of the ?rst triode, the anode current succeeding applied pulses oi! a similar nature. of the triode will be reduced, and the’anode po tential will become more positive. Due to the The circuits to be described hereinafter are adapted to this purpose by applying in a sym connection through the coupling resistor, the metrical manner negative operating pulses to the 30 grid potential of the second triode will become anode circuits of the trigger tubes. more positive, causing an increase in the anode Among the objects of the invention are to pro current‘ of the secondtriode, with a resultant vide an improved means for counting voltage decrease in the second triode anode potential. pulses. Another object of the invention is to pro This decrease in anode potential will, in turn, cause the grid potential of the ?rst triode to be 35 vide improved means for utilizing conventional trigger circuits in a novel cascade arrangement come more negative. This action will continue for deriving the product of the numbers of pulses until the anode current of the ?rst triode is cut in successive series of voltage pulses. Still an off. The ?rst triode will remain cut off, and the other obiect is to provide an improved means second triode will remain conducting, until a positive potential is applied to the grid of the 40 for connecting conventional trigger-circuits in cascade arrangement to provide a continuous ?rst triode or until a negative potential is ap counter. A further object is to provide improved plied to the grid of the second triode. In either means for clearing the counter after each opera latter instance, the tube operating conditions will tion thereof, for conditioning the circuit for be reversed and ‘the ?rst triode will become con ducting and the anode current of the second 45 counting succeeding applied pulses. Another ob Ject is to provide an improved means for deriving ’ triode will be cut oil. One or the features of the instant invention is the utilization of such trigger circuits in cas the sum of two or more binary numbers which are successively applied to the circuit as groups of potentials. . A further object is to provide an change in the polarization or activization of one 50 improved means for deriving the diil'erence be tween two binary numbers. Another obiect is to triode of the. trigger circuit will generate a, pulse provide an improved means for deriving the 'to trigger or activate a succeeding trigger cir binary product of two series of pulses applied to cuit in the cascade arrangement. As many trig a thermionic tube trigger circuit. Still another ger circuits as desired may be connected in cas object is to provide an improved means for de 65 cade. The instant invention is an improvement cade arrangement, whereby a predetermined 2,409,689 riving the binary product of the number of pulses in succeeding series of voltage pulses applied to result is a binary counter in which zero is indi cated on the indicator tube 3 when the tube is one or more groups of cascaded trigger circuits, wherein the multiplicand is applied as a binary number to an electronic counter and is added to itself a number of times which is equal to the extinguished, and 1 is indicated when the tube is illuminated. The second pulse applied to the in multiplier. conducting. In order to indicate that two pulses . " put terminals 5 will cut oil the second trigger tube 2 and cause the ?rst tube I to again become The invention will be. described by reference occurred instead of none, it is essential that to the accompanying drawings of which Fig. l is ' ahave carryover system, corresponding to the carry a schematic circuit diagram of a binary counter, 10 over in arithmetic, be employed which will pro Fig. 2 is a block circuit diagram of the invention, vide a second indication representative of the and Fig. 3 is a schematic circuit diagram of a second term of the binary total. preferred embodiment of a typical portion of Fig. It will be seen that the circuit of Fig. 1 employs 2. Similar reference characters indicate similar two identical trigger circuits I and II connected elements in the drawings. 15 in a novel cascade arrangement whereby two Referring to the drawings, Figure 1 comprises terms of a binary number may be indicated. As a trigger circuit of the type described heretofore. illustrated, the circuit comprises two trigger cir The grid al of a ?rst triode I is connected to the cuits of the general type described heretofore, anode p2 of a second triode 2 through a network it should be understood that ‘as many such comprising the parallel connected resistor rI and 20 but circuits as required for the multiplicand may be capacitor cI. The anode pl of the ?rst triode I connected in cascade arrangement in a similar ' is connected to the grid 02 of the second triode 2 manner. The ?rst and second trigger tubes I through a second network comprising the paral and 2, and the ?rst indicator tube 3 correspond lel connected resistor 12 and capacitor c2. The to the ?rst term of the binary number. The cathodes of the ?rst and second triodes I, 2 are 25 third and fourth trigger tubes II ‘and I2 and the grounded through suitable resistors. A source of second indicator tube I3 correspond to the sec negative bias potentialis connected to the grid III ond term of the binary number. The connection of the ?rst tube I through a grid resistor r3, and I8 from the anode M2 is provided for coupling to the grid 02 of the second triode 2 through a to succeeding trigger circuits of similar types. second grid resistor 14. Anode potential is ap The grid of a transfer tube 8 is connected to the plied to the anode pl of the ?rst tube I through anode p2 of the second trigger tube 2 through a an anode coupling resistor 1'8, and to the anode second coupling capacitor 05. The anode of the p2 of the second tube 2 through a second anode transfer tube 8 is connected to the common ter coupling resistor rQ; A gaseous indicator tube 3. which may be a conventional neon tube, is con 35 minal of the anode resistors H 5, rl 6 and H 1 of the second trigger circuit comprising the tubes II nected across the second anode resistor 16 to in and I2. The grids of the 'second and fourth trig dicate when the current exceeds a predetermined ger tubes 2 and I2 are connected respectively value, which depends upon the. anode current through suitable choking resistors rIII and 120 to - ?owing in the second tube 2. A choking resistor H is connected in series with the positive anode 40 a ?xed contact of a reset switch sI. The mov able contact of the reset switch sI is connected to power supply lead to the common terminals of a suitable negative terminal of a potential source the anode resistors r! and r8. Negative input 9 to provide cut-oil’ grid bias for the tubes 2 and control pulses 4 are applied'to the input termi~ I2 when the switch is closed. The positive ter nals B. 5’, which are connected between ground and through an input coupling capacitor c3, to " .i minal of the bias potential source is grounded. In operation, if the reset switch sI is open, the the common terminal of the anode resistors 15 and r6. first trigger tube I is assumed to be conducting In operation, _if it is assumed that the ?rst tube and the second trigger tube 2 to be cut oil, the ?rst negative pulse applied to the input terminals I initially is drawing anode current, the second tube 2 will be biased ed. A negative pulse 4, ap-' 5 will reverse the stable conditions of the trigger plied to the input terminals 5, will appear on the tubes causing the second tube 2 to become con anode p2 of the tube 2 and on the grid gl of the ducting and illuminating the first indicator tube ?rst tube I ‘which will in turn reduce the anode 3. . The second pulse applied to the input ter current in the ?rst tube I. This, in turn, will minals 5 will again reverse the stable conditions make the potential on the anode pl of the ?rst ' > of the tubes I and 2 and the indicator tube 3 will tube I more positive, and degenerate simultane be extinguished. When the second trigger tube ously any of the original negative pulse applied 2 becomes non-conducting upon the application at pl. A positive pulse will be applied to the grid of the second input pulse to the input terminals 92 of the tube 2 causing the tube 2 to become 5, the potential upon the anode p2 thereof be conducting. This e?ect will increase and con tinue, because of the difference in the potential 60 comes more positive which, in turn, applies a positive pulse to the grid of the second transfer tube 8, which is biased normally to anode current cut oil condition. Due to normal phase inver comes completely conducting. A subsequent sion in the transfer tube 8, a negative pulse will negative pulse applied to the input terminals 5 be derived from the anode thereof and applied to will cause the stable conditions of the trigger the second trigger circuit comprising the third tubes I, 2 to be reversed since the circuit is com and fourth tubes II and I2, causing the stable pietely symmetrical. condition of the second trigger circuit II to be The indicator tube 3 will be illuminated when reversed. It will therefore be understood that the second tube 2 is conducting, since only un 70 the ?rst pulse applied to the circuit will cause the der this condition is there an appreciable voltage ?rst indicator tube 3 to be illuminated. The drop across the anode coupling resistor r6. If it second pulse applied to the circuit will cause the is assumed that the conducting condition of the ?rst indicator tube 3 to be extinguished, and ?rst tube pl represents 'zero, and the conducting , cause the second indicator tube I3 to be illumi condition of the second tube 2 represents 1, the 75 nated. A third pulse applied to the circuit Will charges on the capacitors cl and 02, until the ?rst tube I is cut oil’, and the second tube 2 be 9,409,689 - . 5 cause the ?rst indicator tube 3 to be illuminated in addition to the second indicator tube l3. Figure 2 comprises a block diagram of an elec trigger circuit XII. The negative pulse 46, which immediately follows the positive pulse 45, will tronic multiplying system wherein a multiplicand is set up as a binary number on a series of cas caded trigger circuits 1, II, III, IV, and V of the general type described heretofore. The then trigger the first product trigger circuit XI to the binary zero condition by means of the directly transmitted pulse over the connection k. A condition may arise, for example, where suc cessive carryover pulses are applied to successive circuits in which no positive or negative pulses 45, 46 exist due to the fact that the correspond term in the multiplicand is binary zero, and cascaded trigger circuits XI, 2H1, XIII, XIV, XV, 10 ing the corresponding product trigger circuit is ini and XVI, upon which the binary product is de tially also in the binary zero condition. The rived. The circuits to be described hereinafter ?rst pulse on the line 11., connecting, for exam accomplish both the direct transfer of the mui-. ple, the transfer ampli?er 5|! to the trigger cir tiplicand to the product counter and the carry over operation required as each element product 15 cuit XII of the product counter will change the trigger circuit XII from the binary zero to the counter changes from one to zero in the binary binary 1 condition, which will activate the cor system. Each of the trigger circuits 1, II, III, responding transfer ampli?er 5|. A succeeding, binary multiplicand is then transferred to a sec ond binary counter, including a second series of IV, V of the multiplicand counter is connected to a corresponding transfer ampli?er 30, 3|, 32, or a coinciding, carryover pulse on the line n is applied to a transformer TI to apply a second 20 33, 34, respectively, in such a manner that when the counter trigger circuit is in the binary zero condition, the ampli?er tube is inoperative, and when the counter is in the binary 1 condition, the corresponding ampli?er is biased to the anode current cutoff condition. Negative pulses 4 are positive pulse to‘ the transfer ampli?er 5| over the line m. The coincidence of the positive pulse through’the transformer TI and the control volt applied to the multiplicand binary counter to establish the multiplicand as a binary quantity. Pulses l4, the number of which correspond to the value of the multiplier, are derived from a age from the second trigger circuit XII will there fore make the second transfer ampli?er 5| con ducting, and provide a negative pulse in its anode circuit which will be applied to trigger the next succeeding product trigger circuit XIII. Like wise, the coincidence of a pulse on the line n a pulse on the line from the corresponding multiplier pulse source I4’ and applied to the 30 with differentiating circuit, will provide a, carryover terminal 6, which is connected to the respective pulse to the next succeeding product trigger cir grid circuits of the transfer ampli?ers 3|, 32, 33 cuit, even .though the transfer ampli?er is ini and 34. The pulses l4 may be derived in any tially inactive. known manner, such as a telephone dial or other As many trigger circuits as desired may be uti sequential contactor which is connected to inter 35 lized in the multiplicand counter. As explained rupt a source of potential. The multiplier pulses heretofore in Figure l, the successive trigger cir l4 will therefore be transmitted by only the cuits are connected together by transfer ampli transfer ampli?ers which are connected to the ?ers 8, I8, 28 and 38, respectively, for accom corresponding multiplicand trigger circuits which are in the binary 1 condition. The pulses trans 40 plishing the carryover operation incident to set ting up the multiplicand. The number of trigger mitted by the-respective transfer ampli?ers are circuits required in the product counter will be next applied to separate differentiating circuits one more than the sum of the number of binary 40, 4|, 42 43 and 44, respectively, from which terms in the multiplicand and multiplier, respec are derived a positive pulse 45 and a negative tively. Indicator lamps L may be connected in pulse 46, separated by the width of the multi the anode circuits of the individual trigger cir plier pulses l4. These pulses are next applied cuits of the product counter in the same manner directly to the product binary counter compris as described heretofore in Figure 1 for the indi ing the trigger circuits XI, XII, XIII, XIV, and vidual trigger circuits of the multiplicand coun XV, respectively. The positive pulse 45 is uti Likewise, the anode circuits of the product lized to accomplish the carryover operation be 50 ter. counter may be connected to apply the binary tween successive product counter trigger circuits product directly to other utilization circuits. whenever it is applied to one of the trigger cir The product trigger circuits, with their associ cuits which is in the binary 1 condition. The ated carryovertransfer ampli?ers and coupling negative pulse 46 is utilized to trigger the cor comprise a product accumulator. ' responding product binary trigger circuit to the 55 circuits, Figure 3 indicates the apparatus required for next binary number. two binary terms in the multiplicand. The mul Both negative and positive pulses 46 and 45, re tiplicand counter comprises the trigger circuits spectively, are applied to the input of a second ' group of transfer ampli?ers 50, 5|, 52, 53, and 54, I and II and the carryover transfer tube 8. The transfer amplifiers are so connected that they are For example, if the multiplicand is in the form of a plurality of pulses corresponding in number to the numerical value thereof, the pulses are all multiplicand is applied to the counter through respectively, which are connected to the corre 69, one'or both of the input terminals 5, 5', depend sponding product trigger circuits. The second ing upon the nature of the multiplicand source. inoper \tive when the corresponding product trig ger circuit is in the binary zero condition, and are just cut off when the corresponding trigger circuit is in the binary 1 condition. The out puts of the second transfer ampli?ers are con nected by the leads n to trigger the next succeed ing trigger circuits of the product counter. It will therefore be seen that if the first product "' trigger circuit XI is in the binary 1 condition, the transfer ampli?er 50 will be just cutoff. The positive pulse 45 applied to the input of the transfer ampli?er will, therefore, provide a nega tive pulse in the lead n to the second product applied to the input terminal 5, and accumulated on the counter as a binary number. If the mul tiplicand is already in the form of a plurality of separate voltages corresponding in magnitude and arrangement with the binary value thereof, the separate voltages are applied to the separate corresponding input terminals 5, 5', etc. to trans fer the binary multiplicand directly to the cor responding multiplicand counter elements. The product counter comprises the trigger circuits 2,409,080 8 XI, XII which have a different type of carry over transfer tube II, the circuit of which will be described hereinafter. A second product car ryover transfer tube II is shown for the appli cation of carryover pulses to the next succeed ing product trigger circuit, not shown. The grid of the transfer tube 3| is connected ‘ to the input terminal 0 for the multiplier pulses and through a suitable resistor network which includes a voltage divider llto the cathode of the second tube 2 of the ?rst multiplicand trig ger circuit I. The 'anode_of the transfer tube ii is connected through a differentiating circuit comprising the capacitor II and the potentiome ter II to the grid of the product carryover tube 15 II.‘ The anode of the transfer tube II is simi numbers may also be obtained in a similar man ner. ' Thus the invention described comprises an electronic multiplying device in which the multi plicand is applied to a cascaded binary counter and transferred to a second or product binary counter, in which the ?rst binary indications are multiplied a number of times corresponding to the value of the multiplier. Provision has been made in both counters to accomplish binary car ryover operations where required, and to seg regate the carryover operation from the direct application of the multiplicand 'to the product counter. I We claim as our invention: 1. A binary multiplying device including a plu larly connected" through a second differentiating , ' rality of cascaded trigger circuits, means for circuit comprising the capacitor ‘I and the re polarizing said trigger circuits to represent a sistor I! to the cathode of a diode recti?er II. binary multiplicand, a source of pulses the num The anode of the diode recti?er tube ‘I is con 20 ber of which is representative of a multiplier, a nected through a coupling capacitor ‘III to the plurality of blocking ampli?ers, means responsive common terminal of the anode circults~of the to predetermined polarization of said trigger cir tubes of the product trigger circuit XI. A con cuits for unblocking predetermined ones of said trol potential is derived from the cathode of the ampli?ers, means for applying said pulses to all ?rst trigger tube 2| of the'pr'oduct trigger cir of said ampli?ers, means for differentiating the cuit XI, and applied to the control electrode of the carryover transfer tube ‘I through voltage pulses derived from said unblocked ampli?ers, a dividers l1 and I4, whereby the normally high plurality of cascaded second trigger circuits, a plurality of transfer blocking ampli?ers, means responsive to the polarization of each of said negative bias applied to the grid of the tube I0 is reduced to approximately cut-off when the 30 second trigger circuits for unblocking selectively product trigger circuit Xi’. is in the binary 1 ‘a different one of said transfer ampli?ers, means for applying said differentiated pulses to vary The second multiplicand trigger circuit 11 is the polarization of said second trigger circuits similarly connected through a transfer tube II to transfer said multiplicand thereto for each of to a carryover transfer tube 5i and a diode 0 I , and 85 said multiplier pulses, and means for applying then to the second product trigger circuit XII. said differentiated pulses to trigger said second In order to accomplish the carryover operation in trigger circuits in response to said selective un the product counter, a connection is made, blocking of said transfer ampli?ers for providing through the coupling capacitor 12, between the carryover binary numbers. second cathode of the second diode recti?er ti, 40 2. A binary multiplying device for two quan and the anode of the ?rst carryover transfer tube titles including a ?rst binary counter circuit hav ‘ll. The primary winding of the transformer ing a plurality of trigger circuits, means for ap TI is connected in series with the anode cir plying one of said quantities to said counter as cuit of the ?rst carryover transfer tube Ill. The a multiplicand, a second binary counter circuit secondary winding of the transformer TI is con having a plurality of trigger circuits, a plurality nected in any suitable manner to apply a posi of blocking ampli?ers, means interposing one of tive pulse to the control electrode of the second said ampli?ers between corresponding trigger cir carryover transfer tube Ii when coincidental cuits of said ?rst and said second counters, means carryover pulses occur.‘ The functions of the including said ?rst counter for unblocking said diodes are to prevent reaction on preceding trig 50 amplifiers for transferring said multiplicand to ger circuits due to pulses in subsequent binary said second counter, means for applying pulses term trigger circuits. to said transferring means for repeating said All counters may be cleared after each multi transfer a number of times corresponding to said plying operation is completed by applying a high other quantity as a multiplier, and means for negative bias simultaneously to all binary 1 tubes 55 deriving from said second counter voltages char in the manner which is described. in referring acteristic of the binary sum of said repeated condition. to Fig. 1. > - ‘ multiplicands. , The circuit may also be utilized for deriving 3. A binary muitiplylnz device for two quanti directly the sum of two binary numbers. The ties including a ?rst binary counter circuit hav ?rst number is applied as a group of potentials 60 ing a plurality of trigger circuits, means for ap representative of a binary number to the multi plying one of said quantities to said counter as a plicand counter. A single multiplying pulse is multiplicand, a second binary counter circuit then applied to transfer the number to the prod having a plurality of trigger circuits, a plurality uct or ?nal counter. The multiplicand counter of blocking ampli?ers, means interposing one of is then cleared. The second number is then 65 said ampli?ers between corresponding trigger cir applied to the multiplicand counter, and a sec cuits of said ?rst and said second counters, means ond multiplying pulse is applied to transfer it to including said ?rst counter for unblocking said the ?nal counter. The two numbers are then ampli?ers for transferring said multiplicand to added directly in the ?nal counter. If the mul said second counter, means for applying pulses to tiplicand counter is again cleared, the process 70 said transferring means for repeating said trans may be repeated, and the sum of any desired fer a number of times corresponding to said other ' number of binary numbers obtained.‘ By modi fying the carryover circuit in accordance with the- disclosure in the copending application, re quantity as a multiplier, a plurality of transfer ampli?ers, means interposing one of said transfer ampli?ers between successive trigger circuits of ferred to heretofore, the difference of two binary 75 said second counter and between said second 2,409,689 9 10 mitting said potentials once for each of‘ said counter and said blocking ampli?ers, means in cluding said transfer ampli?ers responsive to pre pulses, means for differentiating said transmitted determined polarization of each of said trigger potentials to derive positive and negative half cycles from each of said potentials, and means for circuits of said second counter for changing the transmitting said negative half cycles to said polarization of succeeding trigger circuits of said second group. second counter, and means for deriving from said 7. The combination of ?rst and second groups second counter voltages characteristic of the binary sum of said repeated multiplicands. of electron discharge units, means for establish ing in said ?rst group potentials representative of 4. An electronic computer including a‘ group of electronic tubes connected in pairs to form trig 10 one number, means for applying pulses repre sentative of another number, means for trans ger circuits, means for applying to said circuits mitting said potentials once for each of said different polarizing potentials corresponding to a pulses, means for differentiating said transmitted number, a second group of electronic tubes con potentials to derive positive and negative half nected in pairs to form trigger circuits, means connecting said ?rst and said second groups for 15 cycles from each of said potentials, means for transmitting said negative half cycles to said sec deriving output potentials in response to said ap ond group, and means for transmitting potentials plied potentials, and means for applying pulses to dependent on said positive half cycles to said sec said connecting means for deriving additional ond group when the unitsv of said second group output potentials a number of times correspond ing to a second number to derive on said second 20 are in a predetermined condition. 8; The combination of ?rst and second groups group voltages characteristic of the product of of electron discharge units, means for‘ establish said ?rst and second numbers. ing in said ?rst group potentials representative oi’ 5. An electronic computer including a group of one number, means for applying pulses repre electronic tubes, means for applying to said tubes potentials corresponding to a number to vary the 25 sentative of another number, means for transmit ting said potentials once for each of said pulses, current conditions in said tubes, a second group means for differentiating said transmitted poten of electronic tubes, means connecting said ?rst tials to derive positive and negative half cycles and said second groups for deriving output cur from each of said potentials, means for transmit rents in response to said applied potentials, a number of times corresponding to a second num 30 ting said negative half cycles to said second group, and amplifying means controlled by the units of her to derive on said second group the product said second group so as to transmit potentials of said'numbers in terms of the current condi dependent on said positive half cycles to the units tions in said tubes of said second group. of said second group when the units of said second 6. The combination of ?rst and second groups of electron discharge units, means for establishing 35 group are in a predetermined condition. in said ?rst group potentials representative of one number, means for applying pulses repre sentative of another number, means for trans GEO. A. MORTON. LESLIE. E. FLOR-Y.