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Feb. 27, 1962
F. R. BALlsH r-:TAL
3,023,3 71
PRECISION VARIABLE FREQUENCY GENERATOR
Filed March 7, 1958
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Feb. 27, 1962
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Filed March 7, 1958
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Filed March 7, 1958
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3,023,371
United States Patent() MICC
Patented Feb. 27, 1962
1
2
FIGURE 9 is a diagrammatic illustration of the V.F.O.
register component of FIGURE 1;
3,023,371
PRECISION VARIABLE FREQUENCY
-
FIGURE 9a illustrates’ the manner in whichthe various
A inputs to ilip-ñops 511l and 512 indicated in FIGURE 9
y would be isolated in a circuit carrying out> the logical
GENERATOR
Frank R. Balish, Willoughby, Paul H. McGal-rell, South
Euclid, and Charles C. Miller and Arthur F. Naylor,
diagram of FIGURE 9, this implementation being obvious
Cleveland, Ohio, assignors to Thompson Ramo Wool
to those skilled in the artwithout comment;l
dridge Inc., a corporation of.`Oliìo `
FIGURE 10 is a blockßdiagram of the subtract pulser
Filed Mar. 7, 1958, Ser. No. 719,862
component of FIGURE 1;
„ ' 21 Claims. "(Cl. S31-438)'
This invention relates to a signal generation system and
particularly to a precision variable frequency generator
for supplying any desired frequency within a given range.
Increasing utilization of the frequency spectrum vhas
given rise to a need for equipment capable of generating
10
`
`
FIGURE 11 is a block` diagram of the start control
component of FIGURE 1;
FIGURE 12 is a block diagram illustration of the range
gate and power gate components of the system> of FIG
FIGURES 13a-d represent diagrammatic illustrations
a single frequency output upon demand over a very wide
of digital to analog converter components of the system
frequency Vrange and to a high degree of precision.
`Accordingly, it is an important object of the present
. of FIGURE 1 ;
v FIGURE 14 (Sheet 11) is a diagrammatic illustration
Y inventionrto provide a novel and improved variable fre
of the V.F.O. register change detector component of FIG
quency generator.
20
Afurtlìer object of the invention resides in the provi
sion of a variable frequency generator capable of supply
URE l;
`
`
FIGURE l5 (Sheet 3) illustrates the programmer op
eration for the system of FIGURE 1 in a diagrammatic
ing frequencies over a wide frequency range with great
form;
_ precision and stability.
"
»
FIGURE 15a illustrates the operation of the encoder
readout component in cooperation with the programmer
Another object of the invention is to provide a variable
frequency generator which provides extremely simple and ,
and oscillator-1 in the illustrated system;
rapid frequency selection.
'
FIGURE 16 is a diagrammatic showing of certain de
tails of the V.F.O. arrangement of the illustrated embodi
n Still another‘object of the invention is to provide a
`variable frequency generator of great flexibility which
ment;
'
'
is capable of operation over different portions of the fre 30
FIGURE 17 illustrates a modified V.F.O. and fre
quency spectrum by the addition or omission of standard
quency selector, switch arrangement in accordance with
components without fundamental change in the basic sys
the present invention; and l
'
'
`
tem.
’
FIGURE 17a illustrates the detailed arrangement of
Yet another object of the invention is to provide a
the binary-register Hip-flops in conjunction with the fre
variable frequency signal generator capable of the pre 35 quency selector power gates and frequency selector switch
cise Vgeneration lof frequencies to the limits of available
relay coils for the embodiments of FIGURES 1-,16 or
techniques and circuitry.
FIGURE 17.
Another and further object of the invention is to pro
vide novel combinations of components for the logical
i control of a variable frequency generator.
'
‘
FIGURE 18 illustrates an exemplary R.F. doubler cir
v cuit for the input frequencylrange from 2 megacycles per
40 second to 256 megacycles per second for the system of
Other objects, features and advantages of the present
FIGURE 2;
invention will be apparent _from the following detailed de
FIGURE 19 illustrates an exemplary low frequency
scription, taken in connection with the accompanying- mixer and octave range tunable amplifier for the system
drawings, in which:
l of FIGURE 2;
FIGURE 1 is a block diagram of a variable frequency 45
FIGURE 20 illustrates a typical crystal diode harmonic
generator in accordance with the present invention;
generator
for use as a frequency doubler in FIGURE 2;
FIGURE 2 is a block diagram of the variable frequency
and
.
t
t
.
.
.
.
,_
l oscillator and radio frequency sub-assemblies of the sys
FIGURE 21 illustrates a typical travelling wave tube
tem of FIGURE l;
power
supply for the system of FIGURE 3.
FIGURE 3 is a diagrammatic illustration of a suitable 50
As shown on the drawings:
`
l tunable amplifier for the system of FIGURE 2;
It is believedthat the system of the present invention
FIGURE-4 is a block diagram of the vcontrol oscillators
will be best understood by first referring to the radio fre
component of the system of FIGURE l;
FIGURE 4a (sheet 14) illustrates by way of example
_ quency sub-assemblies component of FIGURElv which
the control of the “1 Low” line in FIGURE 4 from the 55
counter of FIGURE 5;
FIGURES is a block diagram of the binary decimal
counter component of the system of FIGURE l;
, FIGURE 6 is a block_diagram illustrating the binary
is iuustrated in'FIGURE'z.
i.
R.F. SUB-ASSEMBLIES
By way of specific example, avariable frequency gen
decimal to binary converter component of FIGURE 1;
60 erator system has `been illustrated in FIGURE 2 which
FIGURE 7 isV a block -diagram showing of the binary _ „would cover a frequency range from 33 to 12,000 mega
cycles per second. It will be'iapparent from aconsidera
register component of the system of FIGURE l;
tion of the system that if aygenerato'r is desired covering
FIGURE 8 is a block diagram illustration of the octave
a lesser frequency range, certain components of FIGURE
detector, and fallout subtracter components of the system
of FIGURE 1;
65 2. would simply be omitted. Many other variations and
3,023,371
4
3
modifications will be apparent from the following descrip
at 2.00 megacycles per second again. This arrangement
tion.
The illustrated embodiment involves the provision of
an oven controlled one megacycle per second crystal
has particular utility in an automatic system such as illus
trated in FIGURE 1 wherein each time the tuning shaft
produces a transition from 2.99 to 2.00, the net output
oscillator 10, and a series of doubler circuits 11 through
18 connected so that each circuit in the series delivers a
of the system is increased by 1 megacycle per second,
thus providing continuous fine tuning of the system by
frequency twice the preceding circuit. Thus doubler cir
cuits 11 through 18 provide output frequencies of 2, 4,
8, 16, 32, 64, 128 and 256 megacycles per second, re
means of the control knob for the variable frequency
oscillator components.
The basic purpose of the digital control system illus
10 trated in broad outline in FIGURE l is to control the
spectively.
A series of single-pole double-throw coaxial switches
setting of switches 20-27, 52, 77 and 90-97, to produce
20-27 control connection of the frequency sources 10-18
the desired output frequency. The system of FIGURE
l is also capable of automatically tuning the various com
ponents in accordance with the desired output frequency.
with first inputs of a series of frequency mixers 30-37.
The output of each of the frequency mixers 30-37 is
connected to the input of one of amplifiers 40«47. The 15 The basic digital control system as illustrated in FIGURE
l will now be described.
outputs of amplifiers 40-46 are connected to second in
puts of frequency mixers 31-37, respectively.
The second input of the first frequency mixer 30 is
selectively connectible with a pair of variable frequency
oscillators 50 and 51 under the control of a single-pole 20
double-throw coaxial switch S-1 designated by reference
numeral 52.
'
A series of frequency doubler circuits 60-64 are ar
ranged in series with tunable amplifiers 70-74 such that
BASIC DIGITAL CONTROL
The system for automatically adjusting the components
of FIGURE 2 to deliver a desired output frequency from
the RF. sub-assemblies of FIGURE 2 is illustrated in
FIGURE 1. Basically the sub-assemblies of FIGURE 2
are controlled by first generating a binary number corre
the outputs of amplifiers 70-73 are connected to the in 25 sponding to the desired frequency and then utilizing this
binary number to actuate suitable logical circuits asso
puts of doubler circuits 61-64. The input to doubler
ciated
with the components of FIGURE 2. The refer
circuit 60 may be connected either to the output of tun
ence numeral 110 in FIGURE 1 designates a frequency
able amplifier 46 or tunable amplifier 47 depending upon
indicator which is preferably designed to give a visual
the position of single-pole double-throw coaxial switch
presentation in decimal form of the frequency which the
30
S-1 which bears reference numeral 77.
system is programmed to generate, In selecting a fre
Simply by way of example, the generator of FIGURE
quency to be generated by the system a coarse frequency
2 may be provided with a series of output coaxial cables
control
knob represented byline 111 in FIGURE 1 is set
80-87. Cable 80 has been illustrated as being connected
to cause the binary decimal counter 113 to count up or
to the output terminal of a single-pole double-throw co
axial switch 90 having a first input terminal connected to 35 down through the medium of control oscillators 115.
The counting in counter 113 causes a corresponding
the output of amplifier 44 and a second input terminal
change in the integral number displayed by frequency
connected to the output of amplifier 45. Similarly, cable
indicator 110. When the number shown by the frequency
81 is selectively connected with the outputs of amplifiers
indicator
110 corresponds to the desired frequency, con
45 and 46 by means of a coaxial switch 91, cable 82 is
connected with the outputs of amplifiers 46 and 47 by 40 trol 111 is returned to its off position to cause start con
trol 117 to initiate operation of the binary-decimal to
means of a coaxial switch 92, and cable 83 is connected
binary converter 120. This action first presets binary
to the outputs of amplifiers 47 and 70 by means of a co
register 122 to an offset frequency (or the complement of
axial switch 93, for example.
that Value) from the offset frequency preset component
The frequency mixers 30-37 are arranged to hetero
dyne the pairs of signals delivered to the respective first 45 124. The binary-decimal to binary converter 120 then
converts the contents of the binary-decimal counter 113
and second inputs thereof, and to select the sum fre
into a straight binary code. The result is added to the
quency for transmission to the input of the associated
preset value in the binary register 122. By this means
tunable amplifier. Thus, it will be seen that the mixer
30 is capable of adding either a one megacycle per second
the offset frequency is added or subtracted from the de
signal from source 10 or a two megacycle per second 50 sired frequency.
Octave detector 130 now examines the contents of the
signal from source 11 to a signal between 2 and 3 mega
binary register 122 to determine the octave number, n
(Where n equals 0 for a desired frequency below 512
megacycles per second, n equals 1 where the desired fre
megacycles per second. By the same basic procedure,
mixers 31-37 provide outputs in the ranges of 5-~9, 9-17, 55 quency is in the range between 512 and 1024 megacycles
per second, n equals 2 where the desired frequency is in
17-33, 33-65, 65-129, 129-257 and 257-512 megacycles
the range between 1024 and 2048 megacycles per second,
per second, By doubling either the output of amplifier
n equals 3 where the desired frequency is in the range
46 or 47, doubler circuit 60 provides an output between
between 2048 and 4096 megacycles per second, and n
512 and 1024 megacycles per second. Similarly, doubler
circuits 61-64 provide outputs in the ranges 1024~2048, 60 equals 5 where the desired frequency is between 8192 and
cycles per second from the variable frequency oscillator
50 or 51 to provide an output anywhere between 3 and 5
2048-4096, 4096-8192 and 8192-12,000 megacycles per
second, respectively.
Variable frequency oscillators 50 and 51 are connected
12,000 megacycles per second).
After the approximate frequently desired has been ob
tained by means of the coarse frequency control 111 as
indicated by the number appearing at the frequency in
from 2 megacycles per second to 3 megacycles per 65 dicator 110, Vernier frequency control knob 140 is rotated
second, the other oscillator is being tuned from 3 mega
in the proper direction for fine adjustment of the desired
cycles per second to 2 megacycles per second. With the
frequency. Rotation of Vernier control 140 causes a mo
tuning shafts of the oscillators 50 and 51 connected in
tor 142 to drive a shaft 143 in a corresponding direction
this manner continuous rotation of the tuning knob (not
to increase or decrease the setting of variable frequency
shown) in a single direction will enable frequencies to be 70 oscillators 50 and 51 represented by component 150 in
delivered to the second input of the mixer 30 which vary
FIGURE 1.
'
progressively from 2.00 megacycles per second to 2.99
V.F.O. encoder 160 is suitably coupled to shaft 143
megacycles per second, for example, after which by shift
as by means of gears 161 and 162 and shaft 163 and
ing switch 52 continued rotation of the shaft in the same
“back-to-back” so that as one oscillator is being tuned,
direction will provide frequencies to mixer 30 beginning 75 provides a digital code representation of the angular
5
3,023,371
fposition of_ shaft 143. _e The encoder is read on a continual
' `basis under the'control of an encoder readout- 167.
" lA_doubling Vcontrol output from octave detector 130
causes the' reading of the. V.F.O. encoder 160 to be dou
` bled n times and the result to be placed in the V.F.O.
register 170. Subtract pulser 173 now converts the in
tegral number in the V.F.O. register 170 to a series of
pulses which are subtracted from the binary register 122
by counting that register down. The part of the product
' in the V.F.O. register 170 corresponding to the digits to
the right of the decimal point is displayed in the fre- ~
i quency indicator 110. .
,
'
lThe contents of the octave detector 130 are now used
Vag-ain to divide the number in the binary> register 122
6
ycontrol 140 causes the V.F.O. component 150 to reach
either of these end limits, the Youtput. frequency will be
interrupted for a negligible periodof time while a con
version process takes place.
CONTROL OSCILLATORS
The function of the control oscillators shown in detail
in FIGURE 4 is to provide a convenient means of coarse
frequency selection over a wide range of frequencies. The
selection is ot be accomplished by counting the binary
decimal counter up ordown until the desiredfrequency
is reached. A slow, medium and fast rate of counting for
each range is incorporated into the digital control system.
The tabulation below’gives the pulse frequencies for the
vby 2'to the superscript n. If there is a remainder to this 15 slow, medium and fast rates for each of the ranges.
division, fallout subtracter 180, under the control of the
v `octave detector 130 and the binary register 122, converts
this remainder to atrain of pulses which are subtracted
Range, mc.
from the binary decimal'counter 113.
If a remainder did exist, it is necessary to transfer the 20
newwsetting of `lthebinary decimal counter 113 to binary
register`1‘22 and again examine the number_in the binary
register to determine the octave number nl, since the re
krnainder subtraction might have put the command fre
quency inthe next lower octave. A The process of doubling
i the V.F.O. reading n times and subtracting the integral
Slow,
Medium,
Fast,
c.p.s.
c.p.s.
c.p.s.
4
40
________ __
4
4
4
4
4
4
4
40
40
40
40
40
40
40
100
100
400
400
100
400
400
;»V.F.O. number from binary register 122 and dividmg the
number in the binary register by 2 to the superscript n
It will be noted that no fast rate is provided for range
is now repeated. One and only one repeat is ever neces
sary even where remainder subtraction places the corn 30 l. Asterisks indicate that thecount pulses are fed into
the tens decade of the binary decimal counter rather than
mand frequency in the next lower octave.
'the units decade. With this arrangement, a desired fre
During the above process the start control 117 has
quency selection in any range can be changed from the
v disabled digital to analog converters 190, frequency se
low end of the range to the high end in a maximum of
» lector power gates 191 and output switch power gates
Í 192.* The frequency output has been turned olf during 35 about 41A seconds. With reference to FIGURE 4, it is
assumed that the range information is fed into the circuit
'l the conversion process by virtue of the fact that the output
Y» switch power gates 192 have been disabled.
When the conversion process is completed, the fre
via eight wires 920-927, a selected range being indicated
by its associated line being energized through selector
switch arm 14S from a suitable voltagel source 146. The
quency selector power gates 191 cause switches 2li-27 of
40 operator may manually select the desired range by means
FIGURE 2 to assume positions corresponding to the num
' ber in the binary registers 122. Simultaneously the digital
. to analog converters 190` supply tuning voltages to ampli
fiers 40-47 and 741-74 of FIGURE 2, and the output
, of selector arm 145.
Four free running multivibrators (MV) 131-134 pro
vide the necessary counting pulse rates. As shown in the
switch power gates cause one of the output switches 90-97 45 tabulation, the 4 -and> 40 cycle per second frequencies
are employed as the slow and medium rates for all
. to make the proper connection. The R.F. sub-assemblies
ranges. By means of buffer 136 work ng into gate G-17
including the components shown in FIGURE 2 are repre
of FIGURE 4 and buffer 137 working into gate G-IS
U sented by the reference numeral 195 in FIGURE l.
of FIGURE 4, the proper multivibrator output for the
The frequency now being generated is indicated in
part` by the contents of the binary decimal counter 113 50 fast rate is chosen foreach range. (No fast rate is re
quired for range 1 as previously stated.) The outputs
and >in part by the V.F.O. register 170. The V.F.O. en
are connected to the coarse control switch 111 as shown.
coder 160 is continually re-read by the encoder readout
This switch can take any convenient form such. as a ro
167. At'each reading, the encoder output is doubled n
tary selectorswitch or a multiple push button arrange
times under the control of the octave detector 130 and
ment as desired. Manïpulation of switch 111 causes a
the result appears in the VV.F.O. register 170. As the 55 selected pulse rate to be routed to either the plus line
i» V.F.O. setting is varied by means of the tine control 140,
138 for counting up or the minus line- 139 for counting
the change appears in the V.F.O. register 170 and the
down, depending on whether an increase or decrease of
frequency indicator 110. When the V.F.O. register 170
desired frequency has been called for. Pulses on these
changes by one megacycle per second, the binary decimal
lines are connected to respective gates G-l to G-S and
counter 113Y is increased or decreased by the V.F.O. re 60 G-9 to G-16 of FIGURE 4, there being a total of 16
gates of which. 8 are actually shown. The other two
gister change detector 197. It is important to note that
inputs to the gates are the range control lines 926-927
in any of the doubling ranges, this change does not neces
of which lines 920, 924, 925 and 927 are actually
~sarily`mean that switches 20-27 of FIGURE 2 have to
' be changed. For instance, in the highest doubling range 65 shown and the limitcontroll‘nes of which 151-154 and
155-158 are indicated in FIGURE 4. i
v '
where n equals 5, the `eíjiective V.F.O. contribution to the
The high and lowlimit control lines for each range
" output frequency varies from 64 to 127.36 megacycles
are actuated by signals derived from the binary decimal
` ' per second (64 times 1.00 to‘64 times 1.99). Therefore
counter
of FIGURE 5. For example, if it is desired to
i the V.F.O. component 150 can change the output fre
disable the “1 Low”_gate G-9 below 33 megacycles,
quency about 63 megacycles per second in this range 70
a coincïdence or “and” gate 147, FIGURE 4a, may be
i :with no `change in the frequency selector switch positions.
provided which will be disabled when the set output of
The' only time a conversion process has to be initiated
the binary decimal counter of FIGURE 5 is 32. This
is when the V.F.O. component 15€) reaches its end limits.
number corresponds to a 2 in the units decade and a 3
At these points an input indicated by line 300 in FIGURE
in the tens decade in excess three binary code. Single
lis introduced into the start control 117. As the tine 7.5 primed reference numerals 210'-213' designate the paral
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