# Патент USA US3033466

код для вставкиMay 8, 1962 E c. M. KRAMSKOY 3,033,456 APPARATUS FOR MULTIPLYING BINARY NUMBERS Filed May 10. 1957 5 Sheets-Sheet 2 103 TO N CHARACTERS ELEMENTARY MULTIPLIERS ELEM ENTARY PRODUCT ACCUMULATORS 58/ ’|o.oo9/ ‘5% @,~\\ ~\\' ‘ MULTIPLIER \\> _ ‘ Q P REGISTER, STORE AND PULSE D, a DISTRIBUTOR 0 \ \\‘ ' / / Q1 UCT/ cONTROI- AccmouDLAToRs l RESET E 5 \P Q‘ Q‘ 1 H "3 4 4 // <' ,, " \ " / I80 DECIMAL PARTIAL . PRODUCT COUNTER DESTINATION FIG. 2. Ma)’ 8, 1952 c. M. KRAMSKOY 3,033,456 APPARATUS FOR- MULTIPLYING BINARY NUMBERS Filed May 10. 1957 3 Sheets-Sheet 3 C08 C09 DESTINAT FIG. 3. 3,933,456 Fatented May 8, 1962 2 digits to the converting means in response to individual 3,033,456 digits of the multiplier, thereby to form partial products. NUMBERS“; and readily carried into effect, the invention will be de In order that the invention may be clearly understood APPARATUS FGR MULTH’LYHNG BHNARY Charles Mark Kramslroy, Ealing, London, England, as signor to Electric 51 Musical Industries Limited, Hayes, scribed with reference to the accompanying drawings, in which: England, a company of Great Britain Filed May 10, 1957, Bar. No. 658,295 Claims priority, application Great Britain May 12, 1956 9 Claims. (Cl. 235-464) This invention relates to apparatus for multiplying bi . FIGURE 1 illustrates an elementary multiplier accord ing to the present invention for multiplying two single character decimal numbers, each number being coded in 10 nary numbers. In data handling apparatus and in binary digital com puters, the need for multiplying two numbers frequently arises. Apparatus for multiplying two numbers in nor mal binary code are known, but in data handling appara tus for commercial use especially, it is often desirable to express numbers in binary-decimal code or in some other code in which different groups of binary digits represent different characters in a higher than binary scale. It is, of course, possible to transform a number from a binary decima'l code or some similar code into a serial binary code before multiplication and to re-transform the ?nal product after multiplication. Such procedure tends, however, to be wasteful of time and of components. The object of the present invention is to provide im proved multiplying apparatus which is especially adapted for multiplying numbers in a binary-decimal or other similar code, with a view to effecting conversions as ele mentary steps in the multiplication process. According to the present invention there is provided U binary code, FIGURE 2 illustrates diagrammatically apparatus for multiplying in series-parallel mode two decimal num bers each having a plurality of characters, say N and, FIGURE 3 illustrates in greater detail part of the ap paratus shown in FIGURE 2. For simplicity of illustration, the apparatus has been shown diagrammatically in the drawing and short di agonal lines are used throughout to represent magnetis— able cores of toroidal form. vSome such cores are de noted by references C and suf?xes are employed where necessary to distinguish particular cores. The cores are in general arranged in matrices and the cores in any one matrix, for example to the matrix A of FIGURE 1, are laced by two sets of conductors which are usually re ferred to as column and row conductors respectively. Row conductors are denoted throughout by the refer ence X, with suitable suf?xes as required, whereas col-, umn conductors are denoted throughout by reference Y, again with suitable su?ixes as required. In some of the matrices the cores are, in addition, laced by so called diagonal conductors and these conductors are denoted throughout by the references XY. The expression “di~ apparatus for multiplying one group of binary digits by another group of binary digits comprising means for pro ducing a plurality of binary code signals representing agonal” does not of course necessarily imply that the conductors are diagonal in space but merely that they pass partial products of said one group of binary digits with individual digits of the other‘ group of binary digits, means for converting the signal elements representing in of row and column conductors. dividual binary digits in each partial product into char— acter signals, each character signal comprising signal ele ments representing a group of binary digits constituting a character in a higher than binary scale, and means for in a systematic manner through cores at the intersections _ Binary digital signal elements are stored in the cores in well known manner by using the property of remanence magnetism, remanence magnetism of one polarity repre senting a binary digit of value “1” and remanence mag netism of opposite polarity representing a binary digit of summing the corresponding character signals of the par value “0.” The conductors by which the cores are laced tial products. cores or reading such information from the cores. The expression “character” is used herein and in the claims to denote a digit of a number expressed in a high er than binary scale, the expression “digit” having been used always to refer to binary digits. The expression “group” in relation to binary digits has been used herein and in the claims to denote a series of digits of successive ly higher order. Moreover the expression “binary code signal” is used herein and in the claims to denote a sig nal comprising different signal elements representing in~ dividual binary digits, such digits being arranged in some predetermined manner but not necessarily in such a way that successive signal elements represent digits of succes sively higher order. The expression “signal element” is used herein and in the claims to denote the component of a signal representing a single binary digit. There fore when a number in a higher than binary scale is ex pressed in “binary code,” a “group” of binary digits is required to express each “character” in the number, as for example, when a decimal number is expressed in so are employed for recording binary signal elements in the Re cordings of information in particular cores can be effected by applying current pulses of appropriate polarity and of predetermined amplitude (so-called “l” currents) to a sin gle conductor passing through that core or alternatively by simultaneously applying current pulses of appropriate polarity and of half the predetermined amplitude (so called “1/2” currents) to two conductors passing through the particular cores. Such currents change the cores to a combination of magnetisation states corresponding to the data represented by the applied currents. Reading of a recorded signal element is usually effected by applying “1” currents with a sense tending to restore the respective cores to the “0” condition, any corresponding magnetisa tion changes inducing current pulses in other conductors which are laced through the respective cores. The actual technique of reading or writing adopted in particular cases will be apparent in the following description. Although the conductors are represented in the drawing as single called “binary decimal code” when each group of binary lines it will be understood that the conductors are ar digits comprises binary digits of order 2“, 21, 22 and 23. If the multiplicand and the multiplier are expressed for the flow of currents to and from the cores. by means of groups of binary digits with each group representing a character in a higher than binary scale, ranged, by suitable earth returns, to form complete loops Referring to Fl-GURE l, the elementary multiplier shown therein comprises a multiplier register 1 and a multiplicand register 2!- A single character decimal hum; the apparatus preferably comprises a plurality of elemen her, which is to form the multiplicand, is applied to the tary multiplying apparatuses as de?ned in the preced ing paragraph, one for each group in the multiplicand, 70 register 2 in binary code and the register 2 may comprise four two state devices which store signal elements repre each elementary multiplying apparatus having means for senting the four binary digits used to represent the num~ selectively gating the respective group of multiplicand % 3,033,456 v3 her. The multiplier register 1 may be of similar con struction, and as such registers are well known, the regis ters 1 and 2 have been represented merely by means of rectangles. The multiplier register 1 has four output con ductors Y 1 to YD4 which constitute the Y conductors of a store D consisting of four cores CD1 to CD4, through The number of “shifts” corresponds to the number of which cores pass also the output conductors of a four digits in the multiplier. The multiplier and the multipli stage pulse distributor 3. The pulse distributor is driven byclock pulses applied by way of the input lead 4. Fur cand are both spacially arranged so that the order of the binary digit decreases from left to right as seen in the pulse is applied to all the row conductors XAI to XA4 and this causes the multiplier to be set up in the cores CD1 to CD4, and by the same process the multiplicand is set up in the store A in each of the four rows thereof with a shift of 1 binary place from one row to the next. thermore, four row conductors XAll to XAd of a matrix drawing. store A, termed the partial product store, are passed re spectively through the core CD1 to CD4. The register 2 has four output conductors which form diagonal conduc feed driving pulses successively, in synchronism with the The pulse distributor. 3 is then operated to clock, to the cores CDT to CD4 and these pulses reset the cores which are in “1” state, thereby applying the multi plier digits in correct sequence to the row conductor XA1 tors XYl to XY4 of the matrix store A. The store A comprises four rows of cores with each row (but the 15 to XA4 of the store A. It is of course necessary to ensure ?rst) displaced one position to the right with reference that the pulses which represent the multiplier digits have to the preceding row, such a displacement representing a shift of one binary digital place. The cores of the store A are also laced by column conductors Y, which are em ployed for reading signal elements recorded on the cores and it will become apparent in the following that a “1” the correct polarity to reset cores of the store A. In effect, the ?rst pulse from the distributor 3 gates the highest order digit of the multiplier to the conductor XAl. The contents of row 1 of the register A are therefore transferred to the drive unit 9 and thence to the cores B signal element transmitted by the column conductor YAl corresponds to 2°, a “1” signal element transmitted by and C, such content being the highest partial product. the column conductors are transferred to a pulse regen erator or a so-called drive unit 9 which relays the signal conductor YA7 as relayed by the drive unit 9 sets up a “l” in each of the cores CB1, CCl and CCZ of the stores B and C. Core C31 is laced by the third row conductor Assume that the highest order binary digit of the multi YA2 corresponds to 21, and so on to YA7 which corre plier has value “1” and therefore represents 23, namely 8. sponds to 2*‘. 25 If the highest order multiplicand digit is also “1” the prod Signal elements read from the matrix A by means of uct of these two digits is 64. The output on the vertical elements to two binary to binary-decimal conversion stores B and C. The unit 9 is shown merely as a rectan gle, since it may be of any suitable construction, its main function being to “clean-up” or regenerate the pulses from the signals read from the matrix A. In the stores B and C magnetic cores are placed only at the intersection of selected X and Y conductors. Signals relayed by the unit 9 at particular times may include signal elements representing binary digits up to the seventh order and the XBS of the store B and represents 22 namely 4. Similarly cores CC]; and (ICE of the store C are laced by the second and third row conductorsXCZ and XC3 and represent 21+22=6. Therefore the ‘required decimal digits 6 and 4 are set up automatically. A similar result'is produced with the output from each other core in the ?rst row of the matrix A. After the stores B and C have received the ?rst partial product signals are applied to. the conductors 5 and 6 by actuation of the pulse distributor 7 to transfer cores of the stores B and C set up, in a binary code, the corresponding units and tens decimal digits. In the case the partial product from the cores B and C to the accumu of the stores B and C, the X conductors are employed for 40 lators 1t} and 11. reading recorded signals and signals so read are applied to accumulators It} and 11, the “units” and “tens” accumu The second pulse from the distributor 3 is applied to the core CD2 and if the second highest digit in the multi plier is 1, it initiates a transfer of the second partial lators, respectively. These accumulators may be of any suitable construction and form no part of the present in product (that is the multiplicand, shifted one place to the vention, and it is to be understood that provision is made 45 right) to the drive unit 9 and thence to the cores B and C. for a carry from the accumulator iii to the accumulator 11, this provision being represented in the drawing by the Assuming the second highest digit of the multiplier is 1, representing 4, there will be an output in the column connection 14. In order to drive the cores in the stores B conductor YA6 representing 25, namely 32, and this sets and C the output conductors 5 and 6 of a two stage pulse up “1” in the core CB2 of store B and also sets up “1” in distributor 7 are laced selectively through the cores in the 50 the cores CC3 and CC4< of core C. The core CB2 by its stores B and C. It will be noted that some of the row location represents 2 X19" and cores CC3 and CO4 repre Wires of these two stores have two or more cores on them sent 1 X161 and 2 Xltll respectively, and when in due and if two such cores are within four adjacent columns course signals are transferred from the cores B and C to they may be set in the “1” state simultaneously when a the accumulators lit and ll the decimal number 32 is partial product is read from the store A. Therefore they transferred as required. must be. read sequentially to avoid errors in the accumula tor ltlandll and the lacing of the conductors 5 and 6 is selected so that neither conductor passes through two product is dealt with in a similar way. cores in the same row which are within four columns, only two conductors being required (and thus only two stages in the distributor 7) since there are never more than 2 cores within four adjacent columns in any row of the cores B and C. Subject to this limitation, the lacing of the conductors 5 and 6 may be arbitrary. In operation of the elementary multiplier shown in Each other digit of the partial By the same procedure the third and fourth digits of the multiplier are gated respectively to the row conductors XA3 and XA4 of the store A, to transfer the multipli cand with appropriate “shifts” to the cores B and C where they are converted into binary decimal code and in due course transferred to the accumulators 1t} and 11. It is necessary to arrange that the accumulators are in a quiescent state after each entry before a subsequent entry 65 is made. FIGURE I, initially the cores of the stores A, B and C The various steps in the multiplication process described are all in state “0.” The multiplier is set up in the regis~ can be timed automatically by means of a control organ, ter 1 and the multiplicand is set up in the register 2. At an but as this technique is well known to those skilled in the appropriate time, registers l and 2 are read simultaneous art, it has been deemed unnecessary to illustrate the con ly, to apply “’/2” currents selectively to the column con 70 trol organ. ductors of the store D and to the diagonal conductors of summarising the operation of FIGURE 1, it will be the store A, a “1/2” current being applied to a conductor appreciated that there are produced in the column con-v only if the multiplier, or the multiplicand as the case may ductors YAl to YA7 successive binary code signals repre be, has “1” in the respective digital place. Simultaneously senting partial products of the multiplicand with individua With the reading of the registers 1 and 2 a “1/2” current 75 al digits of the multiplier. Thus the binary digits which 3,033,456 5 6 express the multiplicand are applied to the matrix store accumulates the tens characters and so on. There is no A in the parallel mode whereas the binary digits which express the multiplier are applied in the series mode. Each binary code signal constituting a partial product is applied, via the drive unit 9, to the two binary-to-decimal conversion stores B and C. The signal elements represent one-for-one correspondence between the accumulators P and the accumulators Q because, whereas the number of accumulators P is determined by the number of charac ters in the multiplicand, being in fact twice that number of characters, the number of accumulators Q is deter converted into character signals, such character signals mined by the number of characters in the multiplicand and the number of characters in the multiplier, being the being set up in the cores CB and CC. sum of these two numbers of characters. ing individual binary digits in each partial product are Each character After the signal comprises signal elements representing a group of 10 multiplying operation is completed, the product is there fore to be found in the accumulators Q1, Q2 . . . Q8 binary digits constituting a character in the decimal scale. . . . with the characters in parallel form and the refer Furthermore the accumulators 1t} and 11 in the conjunc ence 13 indicates symbolically a magnetic core matrix for converting the product to serial form as far as the 15 decimal characters are concerned. External couplings cessive partial products. are provided between the pairs of accumulators in the In some cases, instead of reading the stores B and C in series P1, P2 . . . to allow for digit carrying as be two steps, by means of the distributor 7, reading may be tween the accumulators 10 and 11 in FIGURE 1. More effected in a single step, in which case the input to the over the accumulators Q1, Q2 . . . are connected in a accumulators 1i} and 11 on some conductors may have tion with the pulse distributor 7 constitutes means for summing the corresponding character signals of the suc any one of three values, namely 0, 1 and 2. Consequently in such a case the accumulators 1t) and 11 require to be constructed to discriminate among these di?erent values. The N character multiplier shown in FIGURE 2 em . ploys a series of elementary multipliers similar to that continuous sequence to allow for digit carrying opera tions, in known manner. In FIGURE 3, the blocks Pn- l, Pit, Pn+1 and Pn+2 represent four of the accumulators in the series P1, P2 . . . (n being assumed to be even). The accumula shown in FiGURE 1 although for simplicity only four 25 tors Pn-l and Pn comprise the two accumulators for are shown, and these are denoted by references M1 to M4. The elementary multipliers are referred to as multi plier planes .and decimal digits are as stated referred to as characters. The multiplicand for the plane M1 is the the plane ' Mn 2 lowest order character (units decimal digit) similarly the 30 whereas the accumulators Pn+1 and Pn-l-Z are the two accumulators for the plane Mn+2 ing to the tens, hundreds, thousands characters . . . . planes M2, M3 and M4 . . . receive inputs correspond The block 15 comprises a multiplier register, store and 2 pulse distributor similar to the elements 1, D .and 3 of Let it be assumed that n is six. The plane FIGURE 1. However in this case provision is made for 35 feeding the binary digits of all multiplier characters in Mn time serial order to the planes M1, M2 . . . . Firstly, the four binary elements of the highest order character '7 is then that in which operations are performed on the are applied successively to the row wires XAl, XAZ, etc. as in FIGURE 1. Secondly the binary elements of the 40 hundreds character of the multiplicand. Let it also be assumed that multiplication by the hundreds character second highest order character are dealt with in the same in the multiplier has just been completed. The accumu way, and so on through all the multiplier characters. lator Pn—1 may then contain a ten-thousands (104) Therefore the multiplier register 1 must have capacity character, and the accumulator Pn may contain a hun for all the multiplier characters, and switching means for feeding the binary digits of the characters in sequence 46 dred-thousands (105) character. Moreover the accu mulator Pn+l may also contain a hundred-thousands to the cores CD]. to CD2. The output of the planes M1 to M4 are accumulated in a series of accumulators (105) character whereas the accumulator Pn+2 may This shows that after any partial multiplying operations, characters ac The orders of the accumulators are indicated in the rawings and the accumulators are denoted by the refer 50 cumulated in the accumulator Pn and Pn-l-l must be (like it) and 11), two for each elementary multiplier. contain a millions character (106). transferred to the same Q accumulator, namely Q6 in ences P1, P2 . . . P8 . . . . The block 16 represents a the example assumed. The three Q accumulators shown shift store for the decimal partial products set up by in FIGURE 3 are denoted by the references multiplying the several characters of the multiplicand by each character of the multiplier. The decimal partial product shift store 16 is controlled by a decimal partial 55 product counter 17 which advances one step for each and multiplying operation involving a multiplier character. The expression “decimal partial product” is used to de Q11 note the partial product of all decimal characters of the 5+4 multiplicand with a single character of the multiplier 60 to indicate that there is no one-for-one correspondence and is to be distinguished from the expression “partial between the order of the characters stored in the Q ac product” used in relation to FIGURE 1 to denote the cumulators shown and that of the characters stored in product of a group of binary digits by an individual the P accumulators shown. Moreover if other values of binary digit. The construction of the shift register 15 11 and/or other multiplier characters are considered, the is illustrated in greater detail in FIGURE 3 and it is 65 generality of this result will be apparent. Therefore the such as to produce successive shifts of the partial prod full construction of the shift store 16 is adequately illus ucts corresponding to the order of the successive multi trated by means of the representative section illustrated plier digits. The characters of each partial product, thus in FIGURE 3. In the store 16 there are two sections, 70 each having as many rows of cores as there are decimal partial products to be dealt with, but only three rows di?’erent characters of successive partial products, after are shown in each section and these are identi?ed by these partial products have been shifted or weighted to shifted, are fed to another series of accumulators Q1, Q2 . . . Q8 . . . which perform the addition of the their row conductors respectively. Thus, the row con ductors XOm, XOm-l-l and XOm+2 are shown in one successive decimal partial products, the accumulator Q2 75 section, which corresponds to the odd numbered ac become in combination a decimal partial product. Thus, the accumulator Q1 accumulates the unit characters in 7 3 cumulators say i’n—l and ‘Pn-I-l etc. (taking it as even), and row conductors XEm-l, XEm and XEm-I-l are These “1A2” currents combine with “1/2” currents fed to row Wires X1, X2, X3 and X4 from a control device 20 shown in the other section, which corresponds to the of the conversion store 18 (FIGURE 3) to record binary elements in different rows of the matrix 18, correspond even numbered accumulators, Pn, Pn+2 etc. Each row includes four magnetic cores for each accumulator such 5 ing binary elements from different accumulators being as Pn. Output conductors from the accumulators are also laced through these cores but in a diagonal fashion stored in the same rows. Consequently each column of four cores in the matrix 18 corresponds to a single as represented in FIGURE 3. In FIGURE 3 only two decimal character. output conductors and only two cores are shown in each sequencer 18a is arranged in any suitable manner to row of the shift store 16 corresponding to each accumu 10 apply read out currents in serial order to the columns. lator, to simplify the illustration, and it will be observed that the inclination of the diagonal conductors is such that the group of cores corresponding to any one ac cumulator, say Pn-l, is shifted by one character “dis tance” from one row to the next. Some of the cores 15 corresponding to the accumulator Pn+1 are denoted in FIGURE 3 by the reference C07, C08, C09 and C010. For reading the character the time This causes the successive characters to be read out in time serial order. The time'sequencer may be a simple counter, synchronised by clock pulses. The device 29 may be a simple gate. What I claim is: signi?cance as the cores CO7 to C010 in the other sec 1. Apparatus for multiplying one group of binary digits by another group of binary digits comprising means for producing a plurality of binary code signals representing partial products of said one group of binary digits with individual digits of the other group of binary digits, con verting means for converting the signal elements repre tion of the store 16. There is a similar relationship be tween other cores in the store 16. To transfer the ele senting individual binary digits in each partial product into character signals, each character signal comprising Similarly, some of the cores corresponding to the ac cumulator Pn are denoted by the references CB5 to CElt), the cores CB7 to CElt) having the same digital mentary partial products from the accumulators P‘ to the signal elements representing a group of binary digits con store 16, the decimal partial product counter 17 (FIG 25 stituting a character in ‘a higher than binary scale, and URE 2) applies a current pulse to and only to the re means for summing the corresponding character signals spective one row conductor in each section of the store 16 after each decimal partial product is formed. Assume of the partial products. 2. Apparatus for multiplying numbers expressed in once more that n is six and multiplication by the hun groups of binary digits with each group representing a dreds character of the multiplier has just been completed. 30 character in a higher than binary scale, comprising means The characters accumulated in Pm and Pn-l-l have both for producing a plurality of binary code signals repre to be transferred to the accumulator ' senting partial products of each group of binary digits in the multiplicand with individual digits in each group of binary digits in the multiplier before taking account of 35 the order of the multiplier characters represented by the respective groups of binary digits, converting means for The decimal partial product counter is therefore re quired to deliver “1/2” current pulses to the row con ductor XOm and to the row conductor XEm. These current pulses may be simultaneous, and during their converting the signal elements representing individual binary digits in each partial product into character sig nals, each’ character signal comprising signal elements representing a group of binary digits constituting a char acter in a higher than binary scale, means for summing the corresponding character signals derived from said converting means to form a plurality of elementary prod cumulated therein. The elementary partial products are uct signals each representing the product of a group of thereby transferred to cores in the store 16 and the “shift” produced by the row selection of the counter 17 45 binary digits in the multiplicand with a group of binary digits in the multiplier, means for weighting said ele is such that the characters of the partial products have mentary product signals to take account of the order the required weights. Similar considerations apply to of the multiplier characters represented by the respec all the other elementary partial products accumulated in tive groups of binary digits, and means for summing the accumulators P and after each transfer to a pair of the weighted elementary product signals to produce a sig rows of the shift store 16, the elementary partial prod nal representing the product of said numbers. ucts suitably Weighted so that in combination they form 3. Apparatus according to claim 1, said converting a decimal partial product are fed into the product ac means comprising a plurality of conductors grouped to cumulators Q by applying suitable currents to the column represent the respective groups of binary digits, and means conductors of the shift store 16. This is achieved by a two stage pulse distributor 19 like the distributor 7, 55 for injecting signals into selected conductors in said groups in response to the signal elements in the partial products. which applies a reading pulse sequentially to column 4. Apparatus according to claim 3 wherein said means conductors in the two sections of the store 16. Since for injecting signals into selected conductors comprises the characters of the multiplier are taken in decreasing order the counter 17 is required to count down, for ex magnetic core means representing the individual binary ample, when multiplication by the hundreds character 60 digits and coupled with the selected conductors, and means has been completed, the decimal partial product has been for inducing predetermined magnetization changes in the transferred to the Q accumulators and all carrying proc respective core means in response to signal elements rep esses have ended, the tens character of the multiplier is resenting binary digits of value “1.” used to gate the multiplicand characters selectively into 5. Apparatus according to claim 4 wherein said core occurrence corresponding half currents are applied selec tively to the output diagonal conductors of the accumu lators P, depending on the values of the characters ac the accumulators P. The counter then applies a “1/2” current pulse to the conductors XOm-l and XEm:_1 to initiate a transfer of the elementary partial products to the rows XOm-l and XEm—1 for the purpose of weighting them before they are ?nally transferred to the means representing some individual ‘binary digits com prises a plurality of cores linked with different conductors. 6. Apparatus according to claim 1 wherein said means for producing a plurality of binary code signals represent 70 ing partial products comprises ‘a plurality of column con accumulators Q as decimal partial products. ductors, one for each binary digit in the partial products, The transfer of the ?nal product from the accumula tors Q1, Q2 . . . to the conversion store 18 is achieved means for gating signals representing binary digits of as follows, Each accumulator Q produces “1/2” currents on its four column conductors in dependence on the value value “1” in the multiplicand to groups of said column conductors selectively in response to the individual digits of‘the binary elements of the respective decimal digit. 75 of the multiplier, said gating meansbeing such that the 3,083,456 locations of the groups of column conductors represent the order of the respective multiplier digits. 7 7. Apparatus according to claim 6 wherein said gating means comprises magnetic cores at the intersections of said column conductors and of row conductors, which correspond to digits of the multiplier, means for inducing sequential signal elements in said row conductors repre senting respectively the binary digits of the multiplier, 10 ing means comprises a plurality of groups of column con ductors, there being one group of column conductors for every character signal output of said ?rst summing means, and there being in each group one conductor for each binary signal required to express the corresponding char acter; two series of row conductors, there being one row conductor in each series for each multiplier character order; a plurality of magnetic cores disposed respectively at the junctions of said column and row conductors so at said intersections and means for inducing simultaneous 10 as to be coupled with said conductors; a plurality of groups diagonal conductors passing selectively through said cores signal elements in diagonal conductors representing re spectively the binary digits of the multiplicand, thereby to gate said last mentioned signals to groups of the column of diagonal conductors, there being one group of diagonal conductors for every character signal output of said ?rst summing means and there being in each group one con ductor for each binary signal required to express the 8. Apparatus for multiplying numbers expressed in 15 corresponding character; alternate groups of diagonal con ductors being laced through the magnetic cores at the groups of binary signals with each group representing a junction of the column conductors and the row conduc character in higher than binary scale, comprising a plural conductors. ity of elementary multipliers, one elementary multiplier for each multiplicand character; each elementary multi tors in one of said series to effect successive column shifts of the respective groups of diagonal conductors; interven plier comprising a plurality of column channels, one for 20 ing groups of said diagonal conductors being laced through the magnetic cores at the junction of the column conduc each possible binary digit in the output of the respective tors and the row conductors of the other of said series to elementary multiplier, a group of input channels \for a effect successive column shifts of the respective groups of signal representing the respective multiplicand character diagonal conductors; means for successively pulsing the in binary code, a plurality of groups of gates, one group of gates for each possible digit required to express a multi 25 row conductors of both series to transfer character signals from said ?rst summing means, via said diagonal con plier character in binary code, said groups of gates being ductors to the magnetic cores coupled with the respective operative to connect said input channels respectively to row conductors, thereby to weight the respective character different groups of said column channels to effect succes signals according to the multiplier character order; and sive column shifts of said input channels, means for selectively operating said groups of gates in succession 30 said distributor comprising means for alternately pulsing the magnetic cores coupled with said two series of row according to signal elements representing individual binary conductors to transfer respective character signals at dif digits of a multiplier character to- induce signals in said ferent times to said further summing means. column channels representing the product of said multi plier and multiplicand characters; said gate operating means being common to said plurality of elementary 35 multipliers to operate simultaneously corresponding ‘groups of gates in the different elementary multipliers; means for accumulating signals induced in the output channels of said elementary multipliers, said accumulating means in cluding means for differently Weighting the respective sig 40 References Cited in the ?le of this patent UNITED STATES PATENTS 2,394,924 2,428,812 2,604,262 2,722,375 2,734,182 2,808,986 2,846,671 2,907,526 Luhn ________________ .._ Feb‘. 12, 1946 Rajchman ____________ __ Oct. '14, 1947 Phelps ______________ __ July 22, Chenus ______________ _.. Nov. 1, Rajchman ___________ _.. Feb. 7, Stone et al _____________ .. Oct. 8, Yetter _______________ __ Aug. 5, 1952 1955 1956 1957 1958 Havens _______________ __ Oct. 6, 1959 nals to accord with multiplier characters of different orders, means for converting individual signal elements in the column channels of said elementary multipliers into character signals, each character signals comprising a group of binary signals representing a character in higher 45 FOREIGN PATENTS than binary scale, said accumulator means including means for separately summing the character signals de 1,101,201 France ______________ __ Apr. 20; ‘1955 rived from each elementary multiplier, means for weight OTHER REFERENCES ing the separately summed signals to accord with multi plier characters of different orders, and further means for 50 Richards: “Arithmetic Operations In Digital Com summing the weighted signals including a distributor to puters,” D. Van Nostrand Co., Inc., 1955, pp. 247-250. “Synthesis of Electronic Computing ‘and Control Cir cuits,” Harvard University Press, 1951, pp. 198-200. “Description of a Magnetic Drum Calculator,” Harvard elementary multipliers. 9. Apparatus according to claim 8, wherein said weight 55 University Press, 1952, pp. 101-114. render said further means responsive at separate times to character signals of the same order derived from different

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