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Патент USA US3037176

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May 29, 1962
M. A. ALEXANDER
3,037,166
QUANTIZINGV CIRCUITS
Filed March 25, 1959
FIG.
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-
1.
4 Sheets-Sheet 1
60°’T
REGISTER
O O I
5o0\
700
FINE GATING
r’ ELEMENTS
100
COMBINING
[
INPUT
‘ ‘
—
CONTROL
'
.__.
sIaNAL
'
'
CIRCUIT
AND
{
_
CIRCUIT
'
FREQUENCY
MULTIPLYING
OUTPUT
MEANS
MEANS
l ‘
'
'
_
.
400J
COARSE
PULSE
GATE
c?’gggc -
GENERATOR
L
150
L 300
200
FIG. 2.
MBINING
CIRCUIT
AN D
OUT PUT
MEANS
sET
'
501
I CONTROL
SIGNAL
COARSE
'
DE LAY LINE
PULSE
410
INVENTOR
MATTHEW A. ALEXANDER
BY
ATTORNEY
May 29, 1962
M. A. ALEXANDER
3,037,166
QUANTIZING CIRCUITS
Filed March 23, 1959
>
‘
4 Sheets-Sheet 2
FIG. 2A.
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FLIP-FLOP
2
STATES AFTERW 3
EIGHT on MORE 4
FINE PuLsEs
ARE RECEIVED
ohm-coupe OH O
DIRECT CODE LOGIC
EIGHT'S COMPLEMENT
O4=F4+F5+F6+F7+F
O4'=F1+F2+F3+F4
F [6. 28.
C OARSE PU L-SES
A
L~INPUT PULSE
FINE PULSES L'--~INPUT PULSE
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F8,
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F21——'————l#
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1'0
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1
(I NHIBITED
1
INVENTOR
MATTHEW A. ALEXANDER
$12415“
ATTORNEY
May 29, 1962
M. A. ALEXANDER
'
-
3,037,166
QUANTIZING CIRCUITS
Filed March 25, 1959'
4 Sheets-Sheet 3
OMBININ
CIRCUIT
AND
OUTPUT
MEANS
FIG. 3.
700
CONTROL
SIGNAL”
com"
SIG
‘COARSE
PULSES
DELAY LINE
410
FIG. 3A.
1
FIF2F3F4
t
o
0
o
0
1
1
1
1
o
1
1
1
o
o
1
1
o
o
0
1
II
III
Iv
F‘COABSE PULSE #1
u
0
0
o
o
1
1
1
o
o
1
1
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0
o
1
o
o
0
o
o
o
0
1
1
0
0
1
o
o
o
o
o
0
o
1
0111
11111011
1001
o
0
o
1
1
1
1
1
1
0
0
0
1
o
0
1
1
o
0
o
o
1
0
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1
1
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1
1
1
d
1
1
1
1
0
0
1
1
0
1
1
1
o
1
1
1
1
0
L COARSE PULSE #2
COARSE PULSE #3
F1 F2 F3 F4
1
411
111
1V
0
2=
o
1
1
1
o
o
1
1
0
o
o
1
11172
02 O1
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Q
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1
1
Oi 01'
o
1
o
1
o
1
1
O
o
1
0
1
-
INVENTOR
O1=F1_(F2.+F4.)
DIRECT CODE
O'=F1.F‘3'
2
COMPLEMENT
MATTHEW A. ALEXANDER
BY
01' = 01
ATTORNEY
3,937,165
Patented May 29, 1962
2
3,037,166
QUANTHZENG CERQUHTS
Matthew A. Alexander, Santa Monica, Calif., assignor to
Computer Equipment Corp, Los Angelles, Calif.
Filed Mar. 23, 1959, Ser. No. 801,035
7 Claims. ((11. 324-68)
This invention relates to quantizing circuits and, more
particularly, to a time-interval quantizer having a resolu
tion capability in the order of millimicroseconds. In fur
ther particular, the invention is concerned with an im
respect to a “B” pulse interval of 20 microseconds and
an interval d¢ of .2 microsecond. ‘If the stop pulse oc
curs .7 microsecond following one of the recirculated “A”
pulses the ?ne quantizing period to be added to the count
of “A” pulses is found to be between .6 and .8 microsec
ond since three cycles of the “A” pulse occur before a
“B” pulse is detected within the d¢ pulse width of the
“A” pulse.
The Goulding technique has the same disadvantage as
the Burbeck technique in requiring a considerable amount
of time following the termination of the interval to be
measured before the precise resolution has been deter
proved method for quantizing to permit a very high de
mined. It also requires a very sharp coincidence between
gree of resolution without requiring complicated elec
two pulses of rather narrow width although the “A” pulse
tronic vernier circuits such as are described in Patent No.
2,738,461 entitled “Method and Apparatus for Measuring 15 can be broader than the “B” pulse.
The present invention avoids the disadvantages inherent
Time Intervals” by D. W. Burbeck, found in Patent Of?ce
in the vernier and the pulse circulation techniques dis
Class 324-68.
cussed above and makes it possible to quantize time in
High-resolution time quantizing has heretofore been
tervals .or voltage levels known to be varying at a pre
di?icult to achieve since the electronic circuits employed
are limited in terms of maximum speed of response. This 20 scribed rate in time with a higher degree of resolution
means that it is not possible, as an example, to quantize
a time interval to obtain a direct resolution of twenty mil
than heretofore possible and, of equal importance, with
such a small delay in time in determining the ?nal high
resolu'tion answer that continuous high-resolution meas
urement may be made. This means, for example, that
megacycle rate. The counter response is limited by the
time required to cascade carry signals to obtain the de 25 time intervals in the order of millimicroseconds may be
measured continuously between successfully occurring
sired count representation--e.g.: a binary count; and is
pulses, no time being wasted in determining each answer
also limited by the maximum trigger response time of
representing the interval between a present pulse and a
the bistable elements or flip-flops employed. The maxi
previously occurring pulse except that required to trans
mum reliable counting rate employing conventional
30 fer the answer from the quantizing system to a place for
counters is in the order of ?ve to ten megacycles.
limicroseconds by counting pulses generated at a ?fty
Many attempts have been made, therefore, to obtain
the desired degree of resolution by supplementing the
utilization.
According to the basic concept of the present invention
a single oscillator is employed to generate coarse pulses
‘designating the major time intervals to be counted by a
the vernier technique of the Burbeck patent, mentioned 35 conventional counter. These coarse pulses are translated
by means of a frequency multiplier, which may constitute
above, two separate series of pulses are generated hav
a tapped delay line, into ?ne pulses having a period there
ing pulse periods of N and N —1 units, respectively. The
between corresponding to the desired resolution. That is,
pulses having the N-unit period may be referred to as
if the time interval between coarse pulses is in the order
coarse pulses and are counted during the time interval
to be measured. The pulses having the N —-1 unit period 40 of .16 microsecond and if the desired resolution is 20
millimicroseconds, then the coarse pulse interval is di
may be referred to as the ?ne or vernier pulses and are
vided by 8 by means of a frequency multiplier or equiva
not ‘generated until the end of the time interval to be
lent circuit.
measured. The coarse pulses are no longer counted at
‘Each ?ne pulse derived from the frequency multiplying
this time but are still generated. A high degree of resolu
tion is obtained by detecting the number of vernier pulses 45 means is then applied to a separate coincidence gate which
also receives certain other signals. The coincidence gate
which are generated before there is coincidence in time
does not operate as the prior art circuits described above
between a coarse pulse and a vernier pulse.
conventional counter function by additional means such
as the vernier circuits mentioned above. According to
the order of ten coarse pulse intervals. Thirdly, a com
since only a single pulse is applied thereto, the other sig
nals being maintained at predetermined control levels
throughout a relatively long interval. Thus the problem
of pulse coincidence inherent in the prior art devices is
obviated.
The output circuit of each coincidence gate is coupled
plicated coincidence technique must be employed since
to a respective storage element such as a ?ip-?op.
a high degree of precision.
Another scheme for solving the problem of high-resolu
tion time quantizing is found in Patent No. 2,740,091 by
S. S. Goulding for “Means for Measuring Time Intervals”
found in Patent Office Class 324-68.
‘In the Goulding system an “A” pulse is generated in
synchronism with a start pulse marking the beginning of
cal gating actuating the ?ip-?ops is arranged such that
the terminating states of all ?ip-?ops considered together
pulse marking the end of the time interval to be measured,
the “B” pulse circulation delay being only ¢ units. The
“A” pulse Width is made to correspond to the interval
millimicroseconds. The coarse pulses in this case corre
This scheme has several disadvantages. Firstly, it is
necessary to produce two di?’erent series of pulses at very
accurately regulated frequencies. Secondly, a consider
able time interval may elapse before a precise vernier
count is known. For ‘high resolution, this may be in
Ac
coincidence in time of two pulses must be detected with 55 cording to the basic technique of the invention the logi
represent the precise time of occurrence of a marking sig
nal which may occur at either the beginning or end of a
time interval.
The invention may also be used to provide an absolute
time measurement of very high accuracy as well as for
measuring the interval between two pulses. That is, the
a time interval to be measured. The “A" pulse is recir
time of occurrence of a single pulse can be speci?ed as
culated through a delay line having a length of ¢+d¢
units. “B” pulses are then ‘generated starting with a stop 65 an absolute time with an accuracy in the order of 20
spond to absolute time intervals.
The direct ?ne pulse translating technique of the inven
tion makes it possible to continuously translate succes
dqh so that the “A” pulses may be utilized to detect the
occurrence of a “B” pulse within the d¢ interval and 70 sive pulse intervals into sets of output signals represent
ing respective intervals. This may be accomplished in
thus permit higher resolution in quantizing. As an ex
either of two basic operating modes. In one mode of
ample of operation, the Goulding system is described with
—
'
3,037,166
operation each line pulse translation provides both a be
ginning and ending code for the interval to be measured.
The beginning code corresponds to the complement of
the ending code of the previously interval, that is if the
generator 200 are also applied to a frequency multiply
ing means 409 which provides a plurality of output sig
nals on respective leads occurring during each coarse
interval is measured in terms of X ?ne pulses for each
pulse interval as is more fully discussed below.
The signals produced by means 409 are applied to a
coarse pulse period and the previous ending measurement
is N ?ne pulses, then the complement for the beginning
corresponding series of ?ne gating elements 500 which
?ne measurement for the next measurement is X——N ?ne
also receive control signals from circuit 100' and are
operative to pass signals to a register 6% according to
pulses. These ?ne pulse measurements are read from the
predetermined input logic. Register 606‘ has its output
?ip-?ops which receive the gated ?ne pulses, in a manner 10 signals applied to combining circuit 700 which receives
more fully described in the detail description below. The.
the output of counting means 309' and produces _a set of
complete interval measurement for each pair of pulses
in the continuous measuring operation of the invention is
computed by adding the coarse count to the beginning
and ending ?ne pulse measurements.
7
According to the other mode of continuous pulse in
terval measurement contemplated by the invention, each
output signals representing either'the absolute time in
terval of occurrence of an input signal or a time dilference
interval between two pulses or input-signals.
15' In this embodiment of the invention, which is adapted
to measure time intervals between successive input sig
nals, a count of the coarse time pulses between each pair
pulse occurrence may be represented as an absolute time
of input signals is generated in counting means 300. This
by combining the coarse count of the interval with the
maybe accomplished, for example, by reading out the
ending ?ne measurement. Then the pulse periods can be 20 counter total and re-setting to zero on receipt of each
measured ‘by subtracting the last measured absolute pulse
input signal to control circuit 1%, or by reading out
time from the next measured pulse time, the difference
the counter total and subtracting therefrom the previous
constituting the precisely quantized pulse separation be
total read out on a succeeding input signal.
tween one pair of pulses. This is then continued by sub
tracting each previous absolute measurement from the
Fine gating elements 500‘ receive continuous input
pulses from frequency multiplying means 400, but regis
next.
ter 600 is operable only for a short time interval follow
ing each input pulse to control circuit ltlti. In each oper
Accordingly, it is an object of the present invention to
provide an improved quantizing circuit having very high
resolution.
Another object is to provide a device for representing
ating interval register 660' produces a code indicating the
time of occurrence, in ?ne time intervals, of the corre
sponding input signal to control circuit 1W. The operat
ing cycle of register 600 can be de?ned, for example, by
the necessity of utilizing the complicated vernier or pulse
a control signal which begins with each input signal and
delay technique ‘known in the ant.
extends for the desired operating time of the register 600,
Another object is to provide a technique for continu
the control signal being utilized to open gates 500 to pass
ously translating a series of input pulses into correspond-. 35 the ?ne time pulses to register 600, whereby register 600
ing sets of output signals representing the precise time
receives input signals only during the time interval when
interval between successive pairs of pulses.
the control signal is high.
Still another object is to provide a time interval measur
7 The starting and ending codes for a pair of input pulses
ing device having a minimum of delay in operation in
to control circuit 109 are combined with the coarse time
determining the precise time of occurrence of the signal
count therebetween in combining circuit 700, which is
or the precise interval between two signals.
coupled to register‘otl‘tr and counting means 300, to pro
The novel features which are believed to be character
duce an output signal representing the time interval be
the precise time of occurrence of an input signal without
istic of the invention, both as to its organization and
method of operation, together with further objects and
tween the two pulses to the nearest ?ne time interval.
This process will be better understood with reference to
advantages thereof will be better understood from the
a speci?c example. Suppose that the time interval be
tween coarse pulses is 0.16 microsecond and the multipli
accompanying drawings. It is to berexpressly understood, 7 cation factor of frequency multiplying means 400 is 8,
however, that the drawings are for the purposes of illus
such that the time interval between each ?ne pulse is 20
tration and description only and are not intended as a
millimicroseconds. Suppose further that a ?rst input
de?nition of the limits of the invention:
50 pulse to'control circuit 100 occurs shortly before the
FIG. "1 is a block diagram illustrating a suitable ar
third ?ne pulse between a pair of coarse pulses, and that
rangement for practicing the invention;
a second input pulse occurs 3.30 microseconds later,
FIG. 2 is a partial schematic diagram illustrating one _ which is equivalent to 20 coarse time intervals +5 ?ne
suitable form for means 500 and 600 of the embodiment
time intervals.
of FIG. 1;
In this example, counting means 300 would count a
FIG. 2A is a chart and set of logical algebra de?ning
total of 19 coarse time intervals before arrival of the
the mechanization of the embodiment of FIG. 2;
second input pulse, which would occur 7 ?ne time inter
FIG. 2B is a composite set of wave forms illustrating
vals following the 19th coarse pulse. The starting code
the operation of the embodiment of FIG. 2;
generated in register 600v would indicate that the ?rst
FIG. 3 is a partial schematic diagram of another ar 60 pulse occurred on a third ?ne time pulse, and that the
rangement of means 500 and 600 of the embodiment of
second pulse occurred on an eighth ?ne time pulse, which
FIG. 1;
‘
correspond respectively to 2 ?ne time intervals and 7 ?ne
FIG. 3A is a chart and set of logical algebra for the
time intervals. In combining circuit 700 the total elapsed
following description considered in connection with the
embodiment of FIG. 3;
’
time is derived from these signals by adding the coarse
FIG. 4 is a block diagram of a system for continu 65 count to the second ?ne time code and the eight’s comple
ously measuring intervals between successive input sig
ment of the ?rst ?ne time code, which is derived by sub
tracting the ?rst code from eight. The total measured
FIG. 4A is a composite set of wave forms illustrating
time is therefore 19 coarse intervals +7 ?ne intervals
the operation of the embodiment of FIG. 4.
+(8—2) ?ne intervals, which equals 20 coarse intervals
Referring now to FIG. 1 it is noted that an input signal 70 and 5 ?ne intervals, or 3.30 microseconds.
which may constitute a pulse or a series of pulses is
This 'process'can be repeated continuously to measure
applied to a control circuit 100‘. Control circuit 100‘ pro
intervals between a series of pulses, with the ending code
duces appropriate signals for actuating a gate 150 which
of one interval being the beginning code for the follow~
receives coarse pulses from a generator 200 and routes
ing interval. In continuous interval measurement appli
them to counting means 300. The pulses produced by 75 cations, two codes would be generated for each input
nals according to the invention;
3,037,166
5
.
.
signal; an ending code, consisting of the number of ?ne
pulse intervals between the input and the previous coarse
pulse, and a beginning code, consisting of the number of
?ne pulse intervals between the input and the following
coarse pulse. Each beginning code will be stored for
one interval, and the ending code generated by each in
put pulse will ‘be added to the stored beginning code of the
previous input pulse to give the total ?ne time count for
6
In addition each of the coincidence circuits in means
590 also receives an inhibiting output signal from the next
higher stage ?ip-?op in register 600, which prevents each
coincidence circuit from passing ?ne time pulses when
the ?ip-?op associated with the next coincidence circuit
is in the “oif” state. Thus ?ip-?op F2 when “on” per
mits a pulse to be passed through gating circuit 501 if
at the same time the control signal is at a high or “on”
the interval, which is added to the coarse count to give
level.
In a similar manner the gating circuit controlling
previous input pulse.
of ?ip-flop F6 and passes a pulse derived from a tap delay
line 418 at ?ne pulse time 5. This ?ne pulse is therefore
applied to the zero-setting input circuit of flip-?op F5 if
the control signal is “on” at that time and if flip-flop
F6 has not already been turned “olf.”
The inhibiting output signals limit the cycle of register
the total time elapsed between each input pulse and the 10 ?ip-?op F5 receives the “on” representing output signal
The concept of ?ne pulse gating according to the inven
tion can be better understood by reference to an illustra
tive embodiment. Accordingly the following discussion
will relate to FIG. 2 which illustrates one suitable ar
rangement of means 508‘ and 600 of the embodiment of
FIG.
"
"
'
66% to seven changes of state regardless of the length of’
the control signal, since the pulses passed through the
coincidence circuits turn the associated ?ip-flop “off,”
line with appropriate taps thereon such that each applied
coarse pulse is translated into eight successive ?ne pulses, 20 which applies an inhibiting signal to the previous coinci
deuce circuit, and blocks subsequent pulses from passing
the ?rst of which may coincide in time with a coarse pulse.
As indicated therein means 4%‘ may constitute a delay
therethrough even if the control signal remains “on.”
This time sequence of pulses is indicated in FIG. 28
Therefore the cycle of register 69% is limited to seven
where the ?ne pulses are numbered 1 through 8, pulse
changes of state, with the ?ipd?op prior to the ?rst coin
number 1 occurring in coincidence with a coarse pulse,
and pulse number 8 occurring one ?ne time increment 25 cidence circuit receiving a ?ne pulse remaining “on” and
all other flip-?ops being turned off. This action can
prior to the following coarse pulse.
be more clearly described with reference to FIGS. 2A
Referring now to both FIGS. 2 and 2B it will be noted
and 2B.
that the control signal is applied to each of a plurality of
FIG. 2A shows all of the possible terminal states of
coincidence circuits in means Still, circuit 561 being con
register ‘6%, with the number column on the left indicat
sidered to be typical. Each coincidence circuit in means
ing the ?rst ?ip-?op set to binary zero following an input
Stltl receive ?ne time pulses from a corresponding section
signal, and each row‘indicating the terminal state of the
of delay line 410‘, the ?ne time pulses being passed
?ip-?ops for the corresponding input signal time. The
through to a corresponding element in register 606‘ when
logical equations show how the 8 register states of the
the control signal is high, or “on,” and being blocked
chart can be translated into binary codes representing
when the control signal is low, or “off.” As described
the time of the input signal in ?ne time intervals follow
above, the control signal is turned “on” by each input
ing one coarse pulse (direct logic) and ?ne time intervals
signal to control circuit 100, and stays “on” for at least
prior to the next coarse pulse (eight’s complement). The
one coarse time interval. Since the delay line 410 re
O and 0’ code columns, on the right of the register ter
ceives continuous coarse pulse inputs, the position of the
coincidence circuit ?rst passing a ?ne pulse indicates the 40 minal state chart, indicate the values of the direct and
complementary codes for the corresponding terminal
time of occurrence of an input signal to control circuit
states of the register.
100. For example, if an input signal is applied to control
circuit 109 two ?ne time intervals after a coarse time
pulse, then all of the coincidence circuits in means 580
Referring now to FIG. 2A the states of ?ip-?ops F1 to
F8 are indicated as they appear after eight or more ?ne
will be opened at that time, but the ?rst ?ne pulse will 45 pulses have been received during an interval when the
control signal is at a high level. It is assumed in this
be received by the third coincidence circuit from the left
example that all flip-?ops F1 through F8 are initially set
in FIG. 2. The position of the ?rst coincidence circuit
receiving a ?ne pulse is utilized to generate a code rep
to a binary 1 or “on” state. If ?ip-?op F1 is ?rst set to
zero by ?ne pulse number 1 then ?ip-?op F8 will be the
resenting the time of the input signal by means more fully
50 only ?ip-?op in the “on" state after eight or more ?ne
described below.
pulses have been received since it is the only ?ip-?op
The ?ne time pulses passed through each coincidence
which is prevented from being turned “off” due to the
circuit of means Silt) are applied to the “off,” or binary 0,
absence of the enabling control of ?ip-?op F1. This
input terminal of an associated flip-?op in register 600.
eifect may be referred to as a “latch~back” control in
Each ?ip-?op in register 6% is initially set to the “on,”
or binary 1, state by a set signal applied when the circuits 55 the sense that each ?ip ?op stage latches back after being
actuated by a ?ne pulse and prevents the previous ?ip
‘are initially energized, and applied periodically following
each input signal to control circuit 100. The set signal is
?op stage from changing state. It will be understood
preferably generated by the trailing edge of the control
of course, that a similar operation may be accomplished
signal, such that register 60?} is reset immediately after
by initially setting the flip-flops to their zero-representing
each operating cycle thereof. The ?ne time pulses passed 60 state and by then turning each ?ip-?op “on” in response
through the coincidence circuits act to turn the ?ip-?ops
to the coincidence of occurrence of the control signal
off in sequence, with the sequence being terminated after
and a respective ?ne pulse.
7 changes of state by a “latch back” circuit, described
FIG. 2B shows the Wave forms of the control signal
below, which leaves the register in a state indicative of the
?rst coincidence circuit receiving a ?ne pulse, thereby 65 and ?ip-?ops for a pair of input signals the ?rst of which
occurs between a 4th and 5th ?ne pulse, and the second
specifying the time, in ?ne time intervals, of the occur
of which occurs between a 2nd and 3rd ?ne pulse. The
rence of the corresponding input signal to control circuit
terminal state of the ?ip-flops for each input signal is
19!}. Thus register 6%, comprising ?ip-?ops F1 through
indicated by the column on the right of each chart, with
F8, is run through a cycle of seven changes of state fol
lowing each input signal to control circuit 100 with the 70 the binary code corresponding thereto indicated as the
output. The register cycle for each input signal begins
?nal state of the register signifying the time, in ?ne time
with the input pulse, which determines the leading edge
intervals, at which the corresponding input signal oc
of the control signal, and ends on the eighth ?ne pulse
curred. Following each cycle the register 6001 is reset by
thereafter, since the coincidence circuit receiving the
a set signal in preparation for the next input signal to
75 eighth ?ne pulse is inhibited by the “latch back” signal
control circuit 100.
3,037,166
7
5
generated in response to the ?rst line pulse following the
IV. Under condition I it is assumed that the control
signal is turned “on” just before the occurrence of coarse
In referring to FIG. 2B where the output wave forms of
?ip-flops F1 through F8 are shown it will be noted that
the ?ip-flop response time may bew commensurate with
pulse number 1 represented by the horizontal line. This
a coarse pulse interval since it is only necessary that the
corresponding ?ip-flop so that after ‘four ?ne pulse inter
vals have passed all ?ip~?ops ‘F1 to F4 have been turned
input signal.
causes ?ip-?op F1 to be turned to'a‘binary one state.
Each successive ?ne pulse then is e?ective to turn on its
output signal produced by the ?ip-?op assume the desired
gating level before the next ?ne pulse is routed to the
“on.” Following coarse pulse number 2 then, assuming
that thecontrol signal still remains “on,” each ?ip-?op
previous ?ip-?op stage. Thus the “on”-representing out—
put signal of ?ip-?op F5 may fall slowly as long as it 10 F1 to ‘F4 is turned “0E,” successively so that after eight
falls below the gating level before the next ?ne pulse
?ne pulse‘ intervals ?ip-?ops ‘F1 through F4 are back in
' number 4 occurs.
the starting state where they are all zeros.
Eight ?ne pulses after the occurrence of the ?rst im
pulse in FIG. 23 leaves the flip-?ops in the states indi
Under condition II it is assumed that the control sig
nal does not turn “on” until just after coarse pulse num
her 1 which means that the ?rst ?ne pulse to be gated
cated in FIG. 2A, row ?ve; that is: 00910000. This con
dition may be translated into complementary binary out~
through is in position two so that ?ip-?op F2 is ?rst
'turned “on” and then F3 and F4. The states of ?ip
?ops F1 to F4 at the time just prior to the occurrence of
put signals 100 (04', O2’, 01') according to the logic of
FIG. 2A. It is assumed in the example of FIG. 23 that
the interval between two input pulses is to be measured.
Consequently ?ip-?ops F1 through F8 are reset to binary
coarse pulse number v3 then are binary l 0 0 0.
In
condition III the control signal turns “on” just before
?ne pulse 3, and in condition IV the control signal turns
one-representing states and then are set to zero by re
spective ?ne pulses following the occurrence of the sec
ond input pulse. This is shown to occur before the occur
rence of ?ne pulse number 3 so that ?ip-?op‘ F3 is ?rst
“on” just before ?ne pulse 4, giving the terminal states
“on” since the enabling signal from ?ip-?op F3 is not
present ‘for its associated gating circuit. The ?ip-states
latched back to the preceding coincidence circuit, and
therefore the control signal must, be terminated by the
third coarse pulse in each. case to preserve the terminal
shown on the bottom of columns III and IV prior to
coarse pulse number 3. In this embodiment the counting
turned “off.” After eight ?ne pulses ?ip-?op F2 remains 25 cycle is not self limiting, since the ?ip-?ops are not
at this time may be translated into the direct binary out
put signals 010‘. The total ?ne measurement to be added
state of the ?ip-flops. It will be noted that different
to the coarse count is then six, or binary 110. Thus, by 30 states are present in ?ip-?ops F1 through F4 just prior
employing the logic shown in the equations of FIG. 2A,
to coarse pulse number 2 in addition to the different
the total ?ne time interval separating adjacent pairs of
states shown just prior to coarse pulse number 3. This
pulses in an input pulse train can be continuously com
means that either coarse pulse number 3 or coarse pulse
puted by the simple process of adding the direct code
number 2 may be employed to detect the states of ?ip
of each signal to the complementary code of the previous 35 ?ops Fl through F4- in order to determine precisely the
signal, the sum of the two codes giving a direct indication,
time of occurrence of the passage of the ?rst ?ne pulse
in binary numbers, of the total ?ne time interval separat
to a corresponding ?ip-?op. If the states of the flip
ing the two input pulses. The total time interval between
?ops are determined prior to coarse pulse number 2, the
the two input pulses is then derived by adding the coarse
control signal will be terminated by coarse pulse number
time count of counting means .304} to the total ?ne interval 40 2 rather than coarse pulse number 3, as described above.
This same technique may, of course, be utilized to de
derived from the above noted logical addition.
Another variation illustrating the use of the basic quan
tizing principle of the invention whereby a coarse pulse
interval may be translated into a series of ?ne pulse in-'
tervals of high resolution is illustrated in partial schematic
diagram in ‘FIG. 3. The operation of this embodiment
will be described with reference being made also to
FIG. 3A where four possible sequences of operation are
shown, the instantaneous state of the ?ip-?ops being shown.
tect the state of ?ip~?ops at any given ?ne pulse following
the third ?ne pulse after coarse pulse number 1, since the
flip-flop states are di?erent for each succeeding ?ne pulse.
In this case the sequence ofrstates of ?ip-?ops F1 through
F4 may appear as under condition I and the gating of
?ne pulses may be terminated at such time as the selected
terminating input pulse is received causing the control sig
nal to turn “01f.” Thus if the pulse period is terminated
three ?ne pulses following the occurrence of coarse pulse
number 2, the states of flip-?ops F1 to F4 would be:
for successive ?ne time inputv pulses, represented by
rows from top to bottom. As will-be seen in the chart of
FIG. 3A, this embodiment employs a ?ne pulse multipli
cation factor of 4, rather than 8. The operating cycle of
the register of this embodiment, however, covers 8 ?ne
time pulses, with the terminal states of the register being
0 0 0 l.
illustrated by the bottom row of the chart, i.e. the row
respectively. 'In this manner four ?ip-?ops are suf?cient
to represent eight quantizing intervals between coarse
pulses. ‘In this case a coarse pulse period corresponds to
that between coarse pulses number 1 and number 3
~ shown in FIG. 3A.
responding direct binary code and complementary binary
code, are summarized in the small chart with rows num
bered I through IV.
'
' i
.
employed with four ?ip-flops with ?ne pulses in positions
5 to 8- being employed to trigger ?ip-flop F1 through F4,
immediately preceding coarse pulse No. 3. Four operat
ing sequences are shown in the chart, each corresponding
to a different starting time for the input pulse, and the,
terminal states for the four sequences, along with the cor
-
It may be noted that an eight-tap delay line may be
i
60
‘Where only four flip-flop conditions are permitted the
derivation is quite straightforward as indicated in FIG.
3A. A more complex derivation is indicated in Table I
below where it is assumed that eight ?ne pulses occur
In the embodiment of FIG. 3 each ?ip-?op is arranged
effectively to “latch-back” upon itself. That is, when the
between the coarse pulses and ?ip~?ops F1 to F4 are
?ip-?op is turned “on” the “on” signal is employed to 65 cycled continuously until receipt of an input pulse which
control the gating for the'next corresponding ?ne pulse
terminates cycling. The terminal state of the ?ip-?ops
for different timing of the input signal are shown in
“o?” signal is employed to control the gating of an “on”;
Table I, below, where the column of numbers on the’ left
turning ?ne pulse of corresponding number. In particular, , indicates the ?ne pulse number corresponding to the time
this means that when ?ip-flop F1 is in the “on” state and 70 of the input signal, and each row indicates the terminal
a ?ne pulse occurs at ?ne timesl, ?ip-?op F1 is turned,
register state ‘for the corresponding input timing. The
“off.” Since, as an illustration, the embodiment of ,FIG.
logical, equations, below, show the logic for translating
3 is assumed to include four ?ip-?ops and only ?ne pulses
the terminal states into direct and complementary bi
are generated, only four starting states . are possible. “ nary codes, and the 0 and 0’ columns on the right indicate
These are illustrated in FIG. 3A as conditions I through 75 the speci?c codes corresponding to speci?c terminal regis
3,037,168
output signals 04, Oz, and O1 is derived should be appar
4A this transfer is binary l 0 0, representing the fact
cut to those skilled in the art as well as the derivation
that the input pulse occurred at the time interval referred
to as t; between ?ne pulses 4 and 5. The signal produced
of ¢ complementary logic for O4’, O2’, and 01'.
TABLE I
F1 F2 F3 F4
0
1
1
1
1
0
0‘
0
0
0
1
1
1
l
0
0
01
0
0
1
1
1
l
0
0
O
0
0
1
1
1
1
by delay 101 may also be employed to clear ?ne regis
0,; O2 O1
O4’ O2’ O1’
0
0‘
0
0
1
1
1
1
0
1
1
1
l
0
0
0
0
0
1
1
0
0‘
1
1
11)
of FIG. 2A, into a binary number which is ‘then trans
ferred to register A. In the case of the example of FIG.
ter states. The manner in which the de?ning logic for
O
1
0
1
0
1
01
1
O
1
l
0
01
1
0
O
1
0
1
0
1
0
1
Direct Code Logic
O4=F4
ter 606‘, if desired. Register 600 can alternately be
cleared by a set pulse generated after the code of de
coder 710 has been transferred to register A.
10
After this transfer operation, the flip-?ops of register
600 are reset and the count in main counter 340 is trans
ferred through a gating circuit 102 forming part of con
trol circuit 160 to a shift register “B” identi?ed also by
number 715, forming part of output means 706. Gat
ing circuit 102 is opened by the output signal of transfer
15
delay 101, and therefore the transfer of the coarse count
to register B coincides in time with the transfer of the
?ne count to register A. Register 715 is actuated by shift
pulses produced by device 103 which also forms part of
Eighfs Complement
02' =FLF3" +'F1'.F3
01': 01
20
control circuit 160' and shift pulses are also applied to a
delay count shift register “D” identi?ed also by number
659 which stores a signal representing the red-tape inter
val. This may be accomplished in a straight-forward
_ manner by entering a binary one in the eleventh sig
ni?cant position on the register to represent 2048 ?ne
Reference is now made to FIGS. 4 and 4A wherein a 25 pulses corresponding to the red-tape interval.
complete system is shown incorporating the basic circuits
of the invention. In the embodiment of FIG. 4 provision
‘ is made to continuously represent the pulse intervals be
tween successive input signals in accordance with the
above described technique of adding the coarse time count
to the direct and complementary ?ne time codes. It is
The next step in operation is to add the contents of
registers A, B, C, and D (620, 715, 631), and 650) by
means of a serial adder 721} which forms part of output
means 760. The number in register “C” identi?ed as
630 is the complement of the ?ne code previously entered
into register “A” at time tj_1. This occurs because in
the continuous operation illustrated in FIG. 4A the end
necessary in such an arrangement to provide for a period
of operation which may be referred to as the “red-tape”
of each pulse interval also constitutes the beginning of
interval during which time a main counter 34)!) for count—
the next interval and therefore any ?ne pulse measure
35
ing the coarse pulses is allowed to rest and settle while
ment which is made constitutes not only the ending in
the carrys therein are being cascaded. The “red tape”
terval for the previous period but the beginning interval
interval occurs during the time period when the main
for the next. It is the measurement at the end of an
counter is reset to zero, i.e. the time period immediately
interval which is translated as a. direct code and entered
following each input signal to the control circuit 100.
During red tape interval, which is assumed in the illus
tration of FIG. 4A to have a duration of 2048 ?ne pulses,
into register “A” (62%)) and this then is complemented
through a device 635 and passed through a gate 64%
under the control of transfer delay 101, to register “C”
(630) at the end of the operation. Since a time lag is
a delay counter 320 is operative receiving its input signals
through a gate ‘310. Gate 310 is operated by the control
involved in translating the direct code of register A into
signal, which in this embodiment is a voltage gate begin
the complementary code in means 635, the complemen
ning with each input signal to the control circuit, and 45 tary code passed through gate 640 to register C is the com
extending longer than the red tape interval in time. When
plementary code of the previous input pulse. Thus im
the control signal is high, gate 310 routes coarse pulses
mediately following the output signal of transfer delay
to delay counter 32h, which is preset to block the coarse
101, register A contains the direct ?ne code of the present
input signal, register C contains the complementary ?ne
pulses during the “red tape” interval, and then to pass
the coarse pulses through gate 3301 to the main counter
code of the previous input signal, register B contains the
after the “red tape” interval ends. Shortly after the “red
coarse count between the two input signals minus the
tape” interval ends, the control signal drops, and coarse
“red tape” interval, and register D contains the count of
pulses ‘are routed directly through gates ‘31d and 33b to
the “red tape” interval. As described above, the sum of
these counts gives the time interval between the two input
the main counter. Thus delay counter 320 acts as a
counting. switch which is normally closed, but which 55 signals to the nearest increment of ?ne time.
Thus serial adder 720 produces an output signal which
opens after receiving 256 coarse pulses. The count of
main counter ‘340 is therefore short by a constant factor
combines registers A, B, C, and D to form a digital
representation of At constituting the high-resolution time
of 256 in each interval measured, and this constant factor
difference measured between pulses occurring at times
is added to each readout of counter 340 by a delay
count register 6511', later to be described. As in the em
bodiments described above the coarse pulses are also
:14 and Z5, in the present example.
After the addition is completed to provide the desired
output signal delay counter 32% is cleared for the next
operation and coarse pulses are then routed to main
nals for a plurality of ?ne gates 5%. Fine gates 500 are
counter 340. In addition the eights complement of “A”
preferably of the self limiting type disclosed in ‘FIG. 2,
which cycle through 7 changes of state regardless of con 65 register 62.0 is transferred to “C” register 630.
From the foregoing description it should now be appar
trol signal length.
ent that the present invention provides an improved tech
The output signals derived through means Stltl are
nique for accomplishing high-resolution quantizing with
applied to register 6% which is coupled to a decoder 710
out the necessity of complex Vernier or pulse-delay tech
forming part of combining circuit and output means 705.
Decoder 7161 is actuated by a suitable transfer delay de 70 niques.
Several illustrations of the basic technique of the in
vice 101 to transfer its signal to .a register “A” identi?ed
vention have been given. In particular it has been shown
by the number 626. The delay of transfer device 101
that the “latch-back” technique of the invention may be
must exceed the time required for register 6% to complete
employed where a series of ?ip-?ops are actuated sequen
a full cycle and arrive at a terminal state. The terminal
state of register 6% is translated, by the direct code logic 75 tially by respective ?ne pulses, each ?ip-?op providing
applied to a delay line 41b providing separate input sig~
1l
3,037,166
a control signal for the adjacent ?ip-?op to prevent it
from changing state in response to ?ne pulses following
the occurrence of an input signal.
It has also been demonstrated that the invention may
be practiced without the “latch-back” technique by trig
gering each flip-?op by respective ?ne pulses. This latter
12
being ‘speci?ed'in terms of a number of coarse pulses‘
having a period of relatively large duration and a number
of ?ne pulses having a period substantially shorter than
said relatively large’ period, there being an integral num
ber of ?ne pulses during each coarse pulse period, said
device comprising: a storage register having a number of
digital posit-ions corresponding to the number of ?ne
pulses in each coarse pulse period; gating means, responsive
to said input signals, for applying said ?ne pulses to re
10 spective digital positions of said storage register to set
said register to a total state representing the precise time
method of operation has been discussed in two‘ general
procedures, one where four ?ip-flops are actuated by
four respective ?ne pulses and another where four ?ip
flops may be actuatedby eight ?ne pulses to subdivide a
coarse pulse interval by eight.
Particular circuits for providing the ?ne gates of ?ip
of application of the ?rst ?ne pulse to a respective digital '
?ops according to the invention have not been described
position; and means for combining the complementary
since they are well known in the computing art. It will
digital representation of the total state of said register
be understood, therefore, that the basic features. of the 15 after said ?rst input pulse is applied with the direct digital
invention do not depend upon any particular type of cir
representation of the'total state of said register after said
cuit element or combination thereof but rather reside in
second input pulse is applied to constitute a total ?ne pulse
the overall concept of ?ne pulse gating as described above,
count to be ‘added to said coarse count to provide said
and as de?ned in the appended claims.
electrical representation.
'
I claim:
'
.
20
4. An arrangement for providing a precise representa
l. A quantizer for producing output signals represent
tion of the number of relatively small intervals which oc
ing the precise time of occurrence of an input signal which
cur between’ a coarse pulse designating a terminal point
occurs between ?rst and second pulses designating the
of a relatively large unit time interval and the occurrence
time boundaries of a relatively large time interval, the
of an input pulse, said arrangement comprising: ?rst means
time that said input signal precedes said second pulse
for
deriving -a series of ?ne pulses corresponding to the
being designated by a number of ?ne timing signals which _
desired
resolution for translating said relatively large
are produced to provide a predetermined number of sub
intervals into relatively small intervals; a’ plurality of
divisions for each of said relatively large time intervals,
electronic gates for receiving said ?ne pulses, respectively,
said quantizer comprising: a control circuit for receiving
for receiving a control signal having ‘an “on” repre
said input signal and producing a control signal which is 30 and
senting
state for a predetermined period following the
“o?” prior to receipt of said input signal and is “on” for
receipt of said input pulse; a plurality of ?ip-?ops coupled
a predetermined period following receipt of said input
to said plurality of electronic gates, respectively, each ?ip
signal; a plurality of storage elements corresponding in
?op
being set to a predetermined state in accordance
number to the number of subdivisions in said relatively
large time interval; means responsive to said control sig 35 'with the signal derived through the ‘associated electronic
gate; and means for translating the ?nal states of said
nal and to said ?ne timing signals for applying each of
?ip-?ops to an output signal set representing the ?ne time
said ?ne timing signals to a respective storage element to
interval between said coarse pulse and said input pulse.
provide a unique representation of the time of occurrence
5. In a precise time measuring system including coarse
of the particular ?ne timing signal with reference to the
preceding input signal; means for terminating the opera~ 40 and ?ne pulse generators, the ?ne pulses being produced
tion of said last-named means to establish a ?nal set of
states for said storage elements, each ?nal set of states
uniquely designating the time of occurrence of the input
signal in terms of the particular ?ne timing signal which
to bear a predetermined ?xed relationship to the coarse
pulses, the combination comprising: a plurality of ?ne
gating elements corresponding in number to the number
of ?ne pulses generated during each coarse pulse interval;
a corresponding plurality of flip-?ops, one coupled to each
was ?rst applied to a respective storage element under
the control of said control signal; and means for produc 45 ?ne gating element, for registering a respective one of said
ing said output signals to represent the number of ?ne
time intervals between said input signal and said second
?ne pulses passed through the associated gating element;
pulse.
a control circuit for actuating said ?ne gating elements
to start to pass respective ?ne pulses to the associated
in terms of a number of coarse pulses designating rela
uniquely designating the precise time of occurrence of the
?ip-?op after receipt of an input signal; means including
2. A quantizing circuit for producing ‘an output signal
set specifying the precise lapse of time between ?rst and 50 a latch-back circuit coupling each ?ip-?op to one other
for causing said ?ip-?ops to assume a total set of states
second input signals, the lapse of time being measured
?rst ?ne pulse to pass to its respective ?ip-?op; and means
tively large unit time intervals, and in terms of the sum
for translating the total set of states of said ?ip-?ops and a
of a ?rst number of ?ne pulses designating relatively small
unit time intervals between the ?rst input signal and the 55 count of said coarse pulses to an output signal set repre
senting the precise time of occurrence of said input signal.
following coarse pulse and a second number of ?ne pulses
6. In combination: ?rst means responsive to ?rst and
designating the relatively small unit time intervals between
second input signals for counting the interval between said
the second input signal and the preceding coarse pulse,
input signals in terms of pulses having a relatively low
said quantizing circuit comprising: a plurality of bistable
devices, one for each of the ?ne pulses produced during 60 frequency rate; second means for multiplying the frequency
rate of said ?rst pulses to provide second pulses having
each relatively large unit interval; a plurality of gating
a relatively high frequency rate; a storage register having
circuits, one for each of said bistable devices, for receiv
a series of stages, one stage for receiving a respective one
ing respective ones of said ?ne pulses; gate control means
of each of the second pulses occurring during each ?rst
responsive to said input signais for causing said ?ne pulses
to pass to respective bistable devices; means for terminat 65 pulse interval; third means for setting the stages of said
register upon receipt of said ?rst input signal to represent
ing the passing of ?ne pulses to said bistable devices ?rst
the number of ?ne pulses which ‘occur between the ?rst
ly after said ?rst number of ?ne pulses, and secondly after
input signal and the following ?rst pulse; fourth means for
said second number of ?ne pulses have been applied to
setting the stages of said register upon receipt of said
said bistable devices; and means coupled to said bistable
devices for translating’ the states thereof to form said 70 second input signal to represent the number of ?ne pulses
which occur between said second input signal and the
sum of ?ne pulses to be combined with the number of
said coarse pulses to designate said lapse of time.
preceding ?rst pulse; and fourth means for combining the
‘3. A time interval measuring device for providing an I
representations of said storage register and the count of
electrical representation of the precise time interval be
said ?rst pulses to produce output signals representing
tween ?rst and second input pulses, said representation’ 75 the interval between said input signal.
8,037,166
13
14
7. A system for continuously measuring the intervals
setting said storage elements in response to the second in
between successive pairs of input pulses, the ?rst pulse in
each pair constituting the second pulse of the previous
put pulse in each pair by applying the ?rst ?ne pulse oc
curring after receipt of said second input pulse to a cor
responding one of said Storage elements, and successive
?ne pulses to successively di?erent storage elements, the
of coarse pulse intervals representing relatively large time
?nal representation of the states of said storage elements
units, and a number of ?ne pulse intervals representing
after a number of ?ne pulses then representing the precise
relatively small time units, each coarse pulse interval be
time of occurrence of said second input pulse in terms of
ing subdivided into a predetermined number of ?ne pulse
said coarse pulses and said ?ne pulses; and means for
intervals, said system comprising: ?rst means for counting
the number of coarse pulse intervals Within each input 10 controlling the operation of said ?rst and second gating
and control means for combining the complementary
pulse pair; a plurality of storage elements, one for each
representation of the setting of said storage elements for
?ne pulse interval within a coarse pulse interval; ?rst gating
the ?rst input pulse of a pair with the direct representa
and control means for setting said storage elements in re
tion of the setting of said storage elements for the second
sponse to the ?rst input pulse in each pair by applying the
?rst ?ne pulse occurring after receipt of the ?rst input pulse 15 input pulse of a pair to constitute the total ?ne pulse addi
tion to the coarse pulse count to constitute the total
ntora corresponding one of said storage elements, and suc
pair, each interval being measured in terms of a number
cessive ?ne pulses to successively'di?erent storage ele
ments, the ?nal representation of the ‘states of said storage
elements after a number of ?ne pulses equal to the coarse
' precise measurement.
References Cited in the ?le of this patent
UNITED STATES PATENTS
pulse interval representing the precise time of occurrence 20
of said ?rst input pulse in terms of said coarse pulses and
2,665,411
said ?ne pulses; second gating and control means for
2,896,160
Frady ______________ __ Jan. 5, 1954
Kronacher __________ __ July 21, 1959
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