Патент USA US3039093код для вставки
June 12, 1962 3,039,083 R. C. MlNNlCK ETAL MULTI-BIT NON-DESTRUCTIVE MEMORY READOUT APPARATUS 2 Sheets-Sheet 1 Filed oct. 28, 1957 H6. Í ,CRÉ-Q. soz/Rcßâß -fg AND X Ano/e555 .saßen/„Es __ö/5L / W/ DE AMB /6 PHASf @fr -ì //7 PHASE ßfr PHASE pff BY / /% , 44m4 June 12, 1962 R. C. MINNICK ETAL 3,039,083 MULTI-BIT NON-DESTRUCTIVE MEMORY READOUT APPARATUS 2 Sheets-Sheet 2 Filed Oct. 28, 1957 fw, Ã'la Z f@ l L INVENTOR. JOHN 5 Núm/07A, JR. A’ /V//v/v/C/f @WA "icc 3,339,983 Patented June 12, 1962 2 3,039,083 MULTl-Bl'l‘ NGN-DESTRUCTEVE MEMORY READGUT APPARATUS Robert C. Minnick, Arcadia, Calif., and .lohn E. Mekota, a core array may be simultaneously interrogated by utiliz ing a plurality of RF signals. The selection of the RF signals is important for the reason that when a number of RF signal-s are applied to a number of selection wires in any particular array, it is essential that the difference well Regulator Company, Minneapolis, Minn., a cor frequencies for any two RF selection signals be different `than the difference frequency of any other two RF selec poration of Delaware Filed 0st. 28, 1957, Ser. No. 692,868 2 Claims. (Cl. Mtl-_174) tion signals. Further, the difference frequencies between any two selection frequencies, other than those for select A general object of the present invention is to provide frequency band so as to avoid interference with valid in formation that may be read from the core array. Jr., Belmont, Mass., assignors to Minneapoiis-Honey a new and improved apparatus for the storage of digital information. More particularly, the present invention ing a particular core, must be outside of a predetermined It is accordingly another more specific object of the present invention tot provide a simultaneous access mem is concerned with an improved digital data storage ory circuit utilizing a plurality of RF signal sources apparatus or memory circuit which is characterized selected so that their difference frequencies may be used by its being capable of providing simultaneous access to to uniquely define a number of locations in the memory a number of storage locations in the memory circuit circuit `and other unwanted signals will be disregarded. without destroying the data stored therein. The foregoing objects and features of novelty which In certain fields of digital data processing, there has 20 characterize the invention as well as other objects of the occurred Vthe need for numerous data processing ma invention are pointed out with particularity in the claims chines to operate upon a particular data processing prob annexed to and forming a part of the present specifica lern. When programmed data processing machines are tion. For a better understanding of the invention, its used, standardization of the orders or directions for the advantages and specific objects attained with its' use, machine permits these orders or directions lto be stored 25 reference should be had to the accompanying drawings in a common location. Further, the operands used may and descriptive matter in which there is illustrated and also be needed in more than one machine and con described ya preferred embodiment of the invention. sequently they may be stored in a common location. Con 0f the drawings: sequently, with a common memory system for a number FIGURE 1 is a diagrammatic representation of a rep of data processing machines, it is' possible to consider 30 resentative memory plane and the associated input and ably reduce the amount of memory circuitry required output circuitry; and for any one installation. FIGU-RE 2 is a further diagrammatic showing of the logical circuitry utilized on the input address selection pair -of operands of an arithmetic operation in order to 35 circuits. Referring ñrst to FIGURE 1, the numeral 10 repre »speed up the processing of that information in a single sents a memory plane which comprises a plurality of data processing machine. Further, it may also be de magnetic storage elements arranged in an array. The sirable to select the control order for tho-se operands, elements of the array `are positioned in rows and columns ‘In another `area in the data processing field, it is some times desirable `to have the simultaneous access of a or possibly the next control order »to be performed after for ease of identification and location. The magnetic these operands have been used, and the simultaneous 40 elements in the array may well be any suitable ferro selection of the next order at the time that the operands are selected yields a further advantage in time in the han dling of any particular data processing problem. inasmuch as simultaneous access may be made to a memory circuit by a number of machines, it may be desired that the information which is read be retained in an active state in the memory circuit so that it will be available the next time an inquiry is made in the memory circuit. Consequently, it is desirable that a simultane ous access system be provided wherein a read out from the memory circuit is nondestructive. It is Iaccordingly a more specific object of the present invention to provide a simultaneous access memory cir cuit utilizing storage elements which may be interrogated by one or more interrogating circuits without destroying the information in the elements. In an article entitled “A Radio-Frequency Non-Dc electric type core material which takes the form of pre formed toroidal cores, deposited cores, or the like. The material of the cores is preferably of the type having a relatively high residual magnetism as characteristically present in materials having a rectangular hysteresis charac teristic. The array l0 may be seen to comprise ñve hor izontal or X axis selection wires, X1, X2, X3, X4, and X5. The «array lll may also be seen to comprise ñve vertical or Y axis selection wires Y1, Y2, Y3, Y4, and Y5. At the intersection of each of these X axis `and Y `axis selec tion wires, there is positioned a magnetic core element which is adapted to be set in one or the other of two stable states. The two stable states of each storage ele ment are conventionally used to indicate the storage of a binary zero or a binary one depending upon the par ticular stable state to which the element may be switched. In order to sense the signals stored in lthe cores of the structive Readout for Magnetic-Core Memories” by Ber array 1li, there is provided a sense winding S which is nard Widrow in the December 1954 Transactions of the adapted to intercept all of the cores of the array. I.R.E., starting at page 12, there is disclosed a memory 60 The array 10 as described thus far may be considered interrogating circuit utilizing two diñering RF signals to be of the basic type disclosed by l. W. Forrester in which are applied to a pair of selection wires uniquely an article entitled, “Digital Information Storage in common to a magnetic core which is placed at the inter section of the two selection wires. A sense wire passed through the core will have a signal on the output which is representative of the difference frequency between the two RF signals land will be of one phase or of a phase 180° displaced therefrom depending upon the state of the residual magnetism of the magnetic core. Three Dimensions Using Magnetic Cores” in the Journal of Applied Physics, volume 22, pages 44-48, lanuary 1951. In a core array of the type discussed by For rester, the writing of information into any one particu lar core may be effected by the simultaneous applica tion of a select signal to the horizontal and vertical select wire which is common to the particular core to be se It has been found that a number of magnetic cores in 70 lected. This generally involves the application of a half 3,039,083 select current to each of the two select wires so that a full select current will be present and will switch the core from one stable state to the other. This type of memory array is frequencies f6 and f1, this is the only core location that provided means for permitting the simultaneous access to The detection circuit D3 may be reading the data at the detector is permitted to interrogate at any one in stant. However, it is possible Ifor more than one de sometimes referred to as a coincident-current memory tector circuit to interrogate the same core. Thus, the circuit. There must be coincidence of signals on the Ul detection circuit D2 may also Ibe interrogating the core select wires common to a core in order to effect a located at the intersection of the X1 and Y1 selection switching of the core. lInsofar as the present invention wires. The inteirogation for the detection circuit D2 is concerned, it is assumed that the cores in the array `will be by way of the frequencies f7 and f2 so that the 10 have been previously Set or reset to indicate the stor difference frequency, which is different than the difference age of information bits in accordance with desired loca lfrequency for the detection circuit D1, may also be read tions in the array. and used to determine the status of the core at that ad As pointed out above, it is desirable that there be dress location. a number of locations in the array at any one instant. some other location such as the core location defined by It is further desired that this access be performed with 15 the intersection of the selection wires X3 and Y5. The out destroying the information which is stored in the Ifrequencies used in this instance will be f8 and f3 so that array. This is achieved in the present invention by utiliz the difference frequency will be passed through the tuned ing RF frequencies which are adapted to 'be selectively amplifier 18 to `detector circuit 23. It will lbe apparent applied to the desired selection wires in the horizontal and from the circuitry illustrated in FIGURE l that the de vertical dimensions in order to produce a difference fre tection circuits D1 and D5 may likewise be observing quency which will be picked up in the sense wire S any one desired core location in the array. and whose phase will be indicative of whether or not a binary one or binary zero has been stored in the core As described in the aforementioned article by Widrow, the phase detector output may take the Vform of a pulse selected. when the phase of the respective difference `frequencies In order to achieve the desired simultaneous access 25 indicates a “one” is present in the core location interro in the present invention, a plurality of RF frequency gated. The phase detector output will be zero or no sources f1-f5 have been provided for selective applica pulse when there is a “zero” stored in the particular tion to the X address select lines X1, X2, X3, X4 and X5. core location interrogated. The vertical selection wires have associated therewith a Referring to FIGURE 2, there is here illustrated a plurality of RF frequency sources having frequency des 30 more detailed logical circuitry rfor selecting a particular ignations fG-fm. The Ifrequency sources and the address core location in the array 10. For purposes of illustra-~ selection circuitry is more fully described in connection tion, only four cores from the array 10 have been illus with FIGURE 2. Continuing in FIGURE 1, the sense trated in FIGURE 2 and these cores are identified by the wire S is connected so that the signals picked up in the numerals 30, 31, 32, and 33. The core 30 is positioned sense Wire S are applied to a wide band amplifier 15 35 at the intersection of the horizontal select wire X1 and which raises the signal levels from the sense wire so the vertical select wire Y1. Core `31 is positioned at the that the signals may be applied to a plurality of tuned intersection of the select wires X1 and Y2. The core 32 amplifiers 16, 17, 18, 19 and 20, all having their inputs is positioned at the intersection of the core select lines connected to the output of the amplifier 15, the latter X2 and Y1 while the core 33 is positioned at the inter being used in those instances Where the signal level from 40 section of the select lines X2 and Y2. the sense Wire requires such. Each select wire has connected thereto ñve “AND” gate The tuned amplifier 16 has its output connected to a circuits, any one of which, when activated by its input gate suitable phase detector 21. The ampliñer 17 has its legs, is capable of passing the desired radio frequency output connected to a phase detector 22. The amplifiers signal through to the selection Wire. Thus, the select 18, 19 and 2.6 each have their outputs connected to phase 45 wire X1 has connected thereto five gating circuits 35, 36, detectors 23, 24 and 25 respectively. Each tuned am 37, 38, and 39. The 4gate 3S has connected to the input pliñer and associated phase detector may be considered thereof two signal lines, the first being from the radio a part of a unit detection circuit. Thus D1 identities frequency source f1 and the other being :from an X1 the dete-ction circuit which includes the ampliíier 16 and address selection line for the detector D1. The gate 36 the detector 21 and may serve as the communicating 50 has two inputs, one being from the second radio `frequency link to a particular data processing apparatus, not shown. source f2 and the other :being from the X1 address se The amplifier 17 and the detector 22 may be considered lection line for the detector circuit D2. The gate 37 has as a part of the detection circuit D2. ’I‘he amplifier 18 two inputs, the ñrst being from the RF source f3 and the of the phase `detector 23 may likewise be considered second being from the address selection circuitry >for the a part of the Idetection circuit D1. Detection circuits D4 55 detector D3 ‘for the X1 line. The gate circuit 38 has an and D5 will 'be seen to comprise the amplifier 19 and input from the RF source f1 and a further input from detector 24, and the amplifier 20 and detector 25, re the detector circuit address selection line for the de spectively. tector D4. The gate 39 has two inputs, one being from _ Each of the tuned ampliñers 16-20 is tuned to pro the R>F source f5 and the other being from the detection vide a very narrow band pass such that `only the difference frequency of two predetermined RF signals from the selection circuitry may pass. Thus, the tuned amplifier 16 will respond only to the dilîerence frequencies defined by the difference between the RF signals jfs-f1. Ampli 60 circuit D5 for the address selection circuitry for the line X1. It will be apparent that other forms of selection circuits maybe used in lieu of the gates which have been illustrated. It will be apparent that the gating circuits for Ithe other :ñer 17 is tuned to respond only to the difference frc 65 selection lines correspond to those of the selection line quency defined by f2-f2. As illustrated in the drawing, X1. It should further be noted that only two RF sig the amplifier 18 is tuned to the diiference frequency be nals are associated with each `detection circuit, in the tween fS-f3, the ampliñer 19 is tuned to the difference manner set forth in FIGURE l. Thus, the detection cir frequency between ,fg-)21, and the amplifier 20 is tuned cuití1 D1 has only the RF sources f6 and ¿f1 associated there to the difference frequency between f10~f5~ 70 wit . In operating the circuit of FIGURE l, it is essential It will :be readily apparent that any one `or more of the that a device associated with a detection circuit interro four cores illustrated in FIGURE 2 may be simultaneously selected by one or more of the ñve detection circuits the circuit D1 is interrogating the core located at the Thus, all of the cores may have selection sig intersection of the selection wires X1 and Y1, and with 75 D1-D5. nals applied thereto. The following table will serve to gate’only one core location at a time. In other Words, if 3,039,083 5 illustrate one manner in which the cores 30-33 may be iyi+1=wi+1+f+(i+1)ö ri-l-1=vvi-l-2f-l-(Wfl-H95]Í interrogated by the circuits illustrated in FIGURE 2: Difference Detection Circuit Desired Core Address Lines 6 These relations can be shown to become: The solutions to these diiference equations are: Frequency Oax/_ganse 1re 30 33 10 32 The final equations represent the result. To illustrate, suppose the number of positions n to be interrogated is 3; then ta‘bulate the magnitude of all the frequency dif ferences of (x1, x2, x3, y1, y2, ys) where acl-:fb x2=f2, 3l 32 It will be readily apparent that this selection may be changed around in any desired manner, or extended to a x3=f3, y1=f6, )72:67, and y3:fg, to equate the Íaib‘le to the ldescription of IFIGURES 1 Iand 2. Using the «fore going equations, the yfollowing table may be developed: Frequency Comparison Table The underlined entries represent frequencies in the complete array where there are a large’num‘ber of cores valid band. The others are outside the band. From this in the array. One of the essential features in utilizing a circuit of 30 table, it will be seen that for detector circuit D1, the X and can not be detected or cause erroneous information axis frequency is f1. The Y axis frequency for the de tector circuit D1 will be f6 or fl-l-f-i-ö. The difference frequency will then be f-i-ö which -is a frequency in the desired band. The other frequencies for differences be tween f6 and f2 or f3 will be outside the desired band. lt will be apparent that the principles set forth in the foregoing table and the limits of the table itself may be extended to a large number of frequency differences and that the principles of the invention are applicable to Y select wires. A given pair of signals (xi, y1) identify apparatus described without departing from the spirit the present type is the proper selection of the RF signals used with the various selection wires. The reason for this will be apparent when it is noted that there is such a large number of radio frequency signals which may be circulating in the memory on any one instant. Thus, the frequency selected must be such that Ithe difference frequencies will always »fall within the `desired band pass and any unwanted frequency will lbe outside of the range to be indicated on the phase detectors, as illustrated in 40Y`a simultaneous access system including a number of points far in excess of the five which have been discussed FIGURE l. The selection of frequencies to :be used in any one type herein. of array 'may lbe generalized in the following manner: While, in accordance with the provisions of the statutes, Assume one or more of .YL-RF frequencies x1, x2, . there has been illustrated and described the best forms xn, to be applied to any one or more of the X select wires, of the invention known, it will be apparent tto those and similarly for n frequencies y1, y2, . . . yn, on the skilled in the »art that changes may be made in the the source i of the interrogation. An appropriate filter on the output line will separate out the information (a phase at frequency lx1-wil) as to the state of the inter of the invention as set fonth in the appended claims and that in some cases, certain features of the invention may be used to advantage without a corresponding use of rogated core. other features. To determine the RF frequencies needed for such a Having now described the invention, what is claimed as complete system, there is no loss in generality in as new and novel and for which it is desired to secure by suming xi+1>xì and yi+1>yi and yi>xì. Further, the Letters Patent ist: results will be determined in terms of the arbitrary fre 55 1. Apparatus for simultaneously and non-destructively quency x1. The n frequencies on the output wires will interrogating -a plurality of electrical storage elements hav be f-l-ö, f-i-Zö, . . . f-l-nö, where f and ö are arbitrary frequencies. The equations which relate the frequencies ing substantially rectangular hysteresis characteristics and being arranged to form a multiple bit digital data storage means comprising first and second oscillating First, the expression for the existence of n valid chan-l 60 signal sources, said ñrst tand second signal sources being are: selected to have an output frequency such that the dif ference frequency is of a first value, third and fourth oscillating signal sources, said third and fourth signal Second, the expression of the condition that difference frequencies resulting from Wires xi and y1 (ieéj) crossing, 65 sources being selected to have an output frequency such that the difference frequency is of a second value dif be outside the valid band: ferent than said first value, said difference frequencies Furthermore, if two external ydevices interrogate the same wire simultaneously, difference frequencies are of said first and second values being within a desired frequency band `and all other difference frequencies be tween the signal sources being outside of said frequency be outside the band. `But we have required that xi+1>x1 to said storage means, each combination of two of said formed ofthe sort Ixf-xjl, and lyi-yjh These also must 70 band, a plurality of selection lines selectively coupled and yi+1>yb so this requirement is expressed by: selection lines uniquely defining the position of a stor age element in said storage means, a plurality of address 75 selection means connected to said selection lines and 3,039,083 7 «adapted to connect'simultaneously selected ones of said oscillating signal sources to the storage elements to be sensed, a single sense line coupled to the storage elements in said storage means, and a plurality of difference fre quency sensitive means connected to said sense line, said frequency sensitive means each being tuned to the dif ference frequencies of said first and second values from said signal sources within said desired frequency band. 2. Apparatus for simultaneously interrogating a plu rality of bistable electrical storage elements having sub 10 st-antìally rectangular hysteresis characteristics and being arranged to form a multiple bit digital data storage means comprising la plurality of oscillating signal sources, said signal sources being selected in operational pairs so that the diiference frequency of each operational pair is dif ferent than the difference frequency of any other opera tional pair and is Within a desired frequency band and all other difference `frequencies of all of said signal sources considered with respect to each of said signal sources other than from each operational pair are outside of 20 sai-d frequency band, a plurality of selection lines for said storage means, each combination of two or" said selection lines uniquely deñning the position of a storage element in said storage means, a plurality of address 8 selection means connected to said selection lines and «adapted to connect selected ones of said operational pairs to the storage elements to be selected, `a single sense line coupled to the storage elements in said storage means, and a plurality of frequency sensitive means connected to said sense line, said frequency sensitive means each being tuned to selected diiference frequencies from said signal sources within said desired frequency band. References Cited in the file of this patent UNITED STATES PATENTS 2,408,692 2,578,133 Shore _________________ __. Oct, 1, 1946 Hawkins _____________ __ Dec. 11, 1951 2,658,942 2,668,283 2,845,611 Durkee _____________ __ NOV. 10, 1953 Mullin _______________ .__ Feb. 2, 1954 Williams ____________ __ July 29, 1958 OTHER REFERENCES “A Radio-Frequency Nondestructive Readout for Mag netic Core Memories” by B. Widrow, published “IRE Transactions-Electronic Computers,” vol. EC-3, issue 4, December 1954, pp. 12~15.