close

Вход

Забыли?

вход по аккаунту

?

Патент USA US3039698

код для вставки
. June 19, 1962
w. J. MOE ET AL
3,039,688
DIGITAL INCREMENTAL COMPUTER
Filed May 16, 1956
9 Sheets-Sheet 1
R_
TIMING
I
ui\
'
‘ i
'
viJ
ARITH,
COMMAND
jsscnou
J23
TQg?kéEQ"
ADDRESS
'22
TRANSLATOR /
I26
'
STORAGE
I24
’
UNIT
OUTPUTS
INPUTS
FIG. 2A
INVENTORS
WALTER J.MOE
BYRON o. sum-H
BY
CLAIR E. MILLER
SEYMOUR R. CRAY
June 19, 1962
w. J. MOE ET AL
3,039,688
DIGITAL INCREMENTAL COMPUTER
Filed May 16, 1956
'9 Sheets-Sheet 2
[VG-Z. ¢0
(252
(0'2
I28
H3
128 0
I38
I34
I29
I09
HO
/464
DELAY
46!
SHAPER /470
LINE
p463
SHAPER /47|
r480
SHAPER 472
/
V
CURRENT
GEN.
CURRENT
GEN
482
CURRENT
GEN.
I
SHA PER /473
/483
I
CURRENT
GEN. _
INVENTORS
T P 80
TP
IO 0
WALTER J.MOE
BYRON D. SMITH
CLAIR E.M|LLER
SEYMOUR R GRAY
TP
3O 0
G:T
I
Bmpué/y 4mg
Jurlae 19, 1962
w. J. MOE ET AL
3,039,688
DIGITAL INCREMENTAL COMPUTER
Filed May 16, 1956
9 Sheets-Sheet 5
6
TF0;
.
" READ Av"
TPAZ TF5I
A
TF8,
AV
TF3l
FIG. 5A V‘
‘J56
Avi
I53
AA /
INVENTORS
' I55S
'4!
BY
WALTER J. MOE
BYRON 0. SMITH
CLAIR E.M|LLER
SEYMOUR R.CRAY
V'H
ATTORNEYS
June 19, 1962
w. J. MOE ET AL
3,039,688
DIGITAL INCREMENTAL COMPUTER
Filed May 16, 1956
9 Sheets-Sheet 4
SAP CARRY
I72
= 1
SAPCARRY ¢3.°l
FIG. 7A
SERIAL
AODER
OUTPU T
INVENTORS
W
B
C
S
A
V
I
L
E
R
A
V
.
T
O
I
E
M
N
R
O
D
E
.
U
E
T
R
BYZW [gag/)4 MwLR. OIOLC mHRA
J6.M
RJ
A.SI
Y.vcm
E
June 19, 1962
w. J. MOE ET AL
3,039,688
DIGITAL INCREMENTAL COMPUTER
Filed May 16, 11956
> 9 Sheets—Sheet 5
.041.3 m) T5 2>
nmm.mM50. 9.
‘
|._Pl!|I(Im37 1:256
_r\Jm-o3
_
__1'
II._VI.I1|
w5.0?_m.m\o928‘lw\.
-_
BN
2.,oh<23_.5 6
INVENTORS\
WAL‘LER J. MOE
BYRON 0.5mm
CLAIR E. MILLER
SEYMOUR R. CRAY
BY
ATTORNEYS
June 19, 1962
w. J. MOE ETAL
3,039,688
DIGITAL INCREMENTAL COMPUTER
Filed May 16, 1956
9 Sheets-Sheet 6
FIG..9.
SAMPLE PROGRAM
DIGIT
PERI
MACHINE
COMMANDS
MINOR CYCLE X-2
MINOR CYCLE X
NOR CYCLEX-l-l
IN
AD
"I 'I
TOA W
Il
FIG. 10.
24
23
22
2'
2°
DIGIT
STORAGE
I lI| I I
POSITION
A DRESS "
INITIAT
INVENTORS'
WALTER J. MOE
BYROND. SMITH
CLAIR E.M|LLER
SEYMOUR R. CRAY
BM law/Mud
ATTORNEYS I
June 19, 1962
3,039,688
W. J. MOE ET AL
DIGITAL INCREMENTAL COMPUTER
Filed May 16, 1956
9 Sheets-Sheet 8
H0. 11. B
c
Ri
24!,
I20 M
v.
a
240'}
Q
\
\\
jllpLjuw/lf '5
353)
V0‘
J) 354\
I
I
360
‘
j SIS)
s|_e~ OF
343)) pj
a ‘
78 37'
342
El
‘362
/
M 364
A
‘
37
STORED
n. AVAILABLE 3'9
]
312
01. on
PHASES
INFOTOBE
324‘
344;
w
v
3'3)
j
"9‘,
l
[PARTIALTRANSLATORI w.
s
i
\ \ \\
I
59
i-la
357‘
\\ \x
j2j2§2j2§2§212f?
R‘H
355)
j
120
\ \\
"9
]
J
j
j
j
3
Q D
(
j
j
I2!’
_'?2
TRANSLATOR ’
‘22A
J 5-,
345 34!
363
I‘
‘2'6 36E1 384’E1a
3 26
35a
/
|-_ .
INVENTORS
WALTER J. MOE
BYRON 0. SMITH
CLAIR E. MILLER
SEYMOUR R. CRAY
Ext/W pal/é)‘ MW
ATTORNEYS
June 19, 1962
w. J. MOE ET AL
3,039,688
DIGITAL INCREMENTAL COMPUTER
Filed May 16, 1956
>
FIG. 12.
'
9 Sheets-Sheet 9
€ 537
547
536
546
*8‘ :\
V
535
‘I
g
534
OUTPS
544
\
i
E," O
V535
543
OCTAL
V532
542
@530
540
INVENTORS
WALTERr J. MOE
BYRON D. SMITH
CLAIR EMILLER
SEYMOUR R.CRAY
BINARY 5gU8TPUTS
944%,! 6”ATTORNEY5
3,039,688
United States Patent 0 "ice
Patented June 19, 1962.
2
1
FIGURE 1 is a functional diagram of our incremental
3,039,688
computer;
DIGITAL INCREMENTAL COMPUTER
Walter J. Moe, St. Paul, and Byron D. Smith, Minneapo
lis, Minn., and Clair E. Miller, San Rafael, Calif., and
Seymour R. Cray, Minneapolis, Minn., assignors to
symbols used in subsequent ?gures to describe the switch
ing network of FIGURE 2;
ration of Delaware
This invention relates generally to incremental com
puters and speci?cally to a new machine logic best suited
FIGURE 3 is a block diagram of a four-phase clock
pulse generator;
FIGURE 4 is a shorthand schematic of a portion of a
10
. magnetic core shift register used to generate a long se
quence of electrical timing impulses;
.
7
FIGURE 5 is a shorthand schematic of an incremental
for control system applications wherein the inputs are
continuously variable.
'
used in our ?rst embodiment;
FIGURE 2A illustrates the electrical circuit shorthand
Sperry Rand Corporation, New York, N.Y., a corpo
Filed May 16, 1956, Ser. No. 585,312
51 Claims. (Cl. 235—152)
,
FIGURE 2 illustrates a logical switching network as
binary adder using a 2’s complement notation;
,3
Several incremental digital computers (commonly 15
termed digital differential analyzers) have been developed.
In these computers the various mathematical operations
are performed by means of digital integrators. Integra
tion is performed by successive incremental rectangular
approximations of the integration process. That is, the
previous value of the output is corrected by adding or
subtracting an output increment and then is multiplied by
FIGURE 5A is a block symbol of the schematic of
FIGURE 5;
.
FIGURE 6 is a shorthand schematic of a complementer
using 2’s complement notation;
-'
FIGURE 6A is a block symbol of the schematic of
FIGURE 6;
I
p
-
FIGURE] is a shorthand schematic of a serial adder
using a 2’s complement notation;
FIGURE 7A is a block symbol of the schematic of
an input increment. The summation of these incremental
FIGURE 7;
rectangles is the approximation of the desired integral.
Inputs and outputs of these integrators are streams of 25
FIGURE 8 illustrates an embodiment of our basic
electrical impulses which represent binary encoded values.
By properly interconnecting a number of these integrators
algorithm;
any continuous function can be solved.
program based on our basic algorithm;
Our invention provides an improved and novel logic
for incremental computers which greatly expands the
FIGURE 10 illustrates a sample computer instruction
code structure used to describe the program of FIGURE
FIGURE 9 is a table illustrating a multiply algorithm
. types of basic operation steps of this class of digital ‘com—
9,
-
FIGURE 11A is part of a mixed block and shorthand
puters. This logic is speci?cally designed for real time
schematic diagram illustrating the implementation of a
few machine commands;
function of independent and dependent variable factors.
The computer employs operations such as scaled incre 35 FIGURE 11B is theremainder of the diagram of FIG-v
UREllA, these making up FIGURE 11 as referred to
mental multiplication and division as basic mathematical
hereinafter, and
7
steps. These operations are performedvby properly se
FIGURE 12 is a shorthand schematic illustrating an
quencing and modifying streams of electrical impulses
electronic translator.
p,
which may represent binary encoded values or abstract
The environment background chosen for the explana
notations. It will be obvious that this logic may be em
tion of our invention in a ?rst embodiment, illustrated
ployed in environments not involved with processes and
- generally in FIGURE 1, is in an airborne ‘control system
real time calculations.
application. However, limitation thereto is not intended
Accordingly it is an object of our invention to pro
and, it will be obvious that this embodiment can be em
vide in a digital incremental computernovel apparatus
45 ployed in other environmental situations.
'
employing new and improved machine logic.
The general theory of operation‘ of our incremental
Another object of our invention‘ is to provide in a
process control where the control over the process is a
computer in a real time control problem is as follows.
Analog inputs (which may be from transducers or the
like), are compared with digital values from the arith
digital incremental computer apparatus for solving several
problems simultaneously or sequentially.
'Still another object of our invention is to provide a '
digital incremental computer wherein the multiplication
metric section 126 in data converter 127. As a result of
time is reduced from one-fourth to one-half of the time
this comparison, input increments are generated with
proper sign to adjust the digital values in accordance
with the input analog values. These increments are
required by previous incremental computers.
Still another object is to provide a digital incremental
computer which is peculiarly adapted to real time control
functions.
A further object is to provide a digital incremental
computer which is drift free, that is, the computer error
is bounded.
A still further object is to provide in a digital incre
mental computer apparatus for scaling a product simul 60
~ ' taneously with computing an increment.
stored as electrical impulses, in the magnetic core memo
ry 124. These increments are used as determined by
the electronically coded program of computer commands
stored on magnetic storage drum 120. Likewise, incre
mental outputs are processed from arithmetic section
126 through data converter 127 to control analog devices
(not shown) involved in the process or sequence being
controlled. As in any internally programmed computer,
means must be provided for entering the program data
Another object is to provide in a digital incremental ,
onto drum 120. Since this does not affect the real time
computer apparatus for retaining a remainder for eventual
operation of our computer and is Well known to those
processing while the input is varying in a manner as to
cause the output to lag.
65 skilled in the art, discussion thereof is thought unneces
sary.
.
Another object is to provide a digital incremental com-‘
The recirculating type of operation in an incremental
puter in which the incremental multiplication is performed
serially in one word length.
'
computer lends itself to the use of a rotating magnetic
Other objects and advantages will become obvious
drum memory 120 as shown in FIGURE 1. In one em
from the appended claims and the following description 70 bodiment the storage capacity of each track is about 1000
of the various features and phases of the exemplary‘em
binary digits represented by their electrical impulse equiv
bodiments according to the, invention, wherein:
I alents.
The time intervals between impulses are called
8,039,688
3
4
preceding operation which eliminates access time require
ments. Electrical circuit timing impulses are acquired
A to its positive polarized state. If a low impedance (not
shown) to ground is presented at terminal 109, all the
current is diverted from winding 131 through the low
impedance and core A remains unchanged. Capacitor
130 provides a slight current impulse delay which makes
the circuit more tolerant. This setting type of input is
represented in shorthand symbols by the arrow 1005 touch
from one track called the “timing track,” on the drum
ing core 100 and attached to terminal 109A which cor
“digit periods.” A track is a circumferential strip on the
drum, wide enough to allow a series of electrical impulses
to be recorded as tiny magnetized points along the strip
each separated by a time space of ?ve microseconds. All
incremental values for an operation are obtained during a
which synchronize all circuitry in the computer with the
drum through clock 119. The electrically encoded com
puter program of commands is taken serially by com
mands from the drum and gives initiates and monitors
all subdoperations required to perform a program, such
responds to terminal 109 of FIGURE 2. The symbol ¢0
10 beside the arrow indicates a setting input if any occurs
during clock phase zero.
Input winding 132 operates in a similar manner while
the resultant effect on core A is to “clear” the core, that
is, to force the magnetic remanence to the negative polar
as, division, transfers, etc., by properly routing the elec
trical pulses from clock 119. The sequence of execution 15 ized state. In the switching networks the inputs to wind
ings 131 and 132 are time separated. The desired imped
of program commands in a given program is ?xed by their
ance at terminal 110 must be presented during ¢1. The
geographical locations on the magnetic storage drum.
shorthand notation of this clearing circuit is shown by
To save computing time, a high speed magnetic storage
the small circle lililC on core 100 which is connected
unit 124 is used to store increments. The direction of each
increment is represented by the presence of an electrical 20 by a line to terminal 110A corresponding to terminal 110
impulse or absence of an electrical impulse (i.e., whether
plus one or minus one). The addresses of these in
crements are interpreted by the electronic address transla
of FIGURE 2. p1 beside the connecting line indicates
the phase during which a clearing input may appear.
Winding 133 is the sense or output winding of core A.
During ¢2 a current impulseis provided to'readout or
sense the state of this core. Current ?owing through isolat
ing diode 134 into winding 133 tends to clear core A.
as the program commands. Electrical coding distinguishes
Assuming core A has been set through winding 131 but
the commands from the addresses. Elements 126 con
not cleared, the switching of core A by the current in
tains circuitry which performs the mathematics by rout
winding 133 causes a large counter
to be induced
ing and comparing various electrical impulses. The four
electrically encoded values R, U, V, and S are processed 30 in winding 133. This makes winding 133 appear as a high
impedance to ground. This high impedance can be re
simultaneously in the manner illustrated in FIGURE 8.
?ected to other circuits through unidirectional current
The basic operation cycle of our machine is called
devices such as diodes 135 and 135'. If core A is in the
a digit period which is the time between two successive
cleared state, the current through winding 133 has little
electrical impulses on the timing track which correspond
to one digit position of a serial computenoperand word. 35 effect on the magnetic state of core A and thus winding
133 appears as a very low impedance to ground. This
A series of four electrical impulses furnish electrical cir
low impedance can be imposed on other circuits through
cuit timing during each digit period. These impulses
diodes 135 and 135’. For example, a similar output
occur during clock phases, ¢0, ¢1, 452, and ¢3, respec
tor 122. The address of each increment is stored on the
drum as electrical impulses on the same set of tracks
‘tively.
The frequency of occurrence of digit periods
determines the rate of information transfer in the com
puter.
The execution of a minor or partial program of com
winding could provide the impedance levels to input cir-'
40 cuits like either of those at terminals 109 and 110 for
windings 131 and 132. Each circuit connected to output
winding 133 must be isolated by a separate unidirectional
mands which usually corresponds to the length of the
operand word under consideration is called a minor cycle.
Various minor cycles in one complete program may vary
in length as the signi?cance of the operands or type of
commands executed. The execution of one complete
program of commands is called a major computation .cycle
current device. Thus the need for both diodes 135 and
135’ assuming a second output circuit is utilized at ter
minal 114. In the shorthand schematic any line, such as
line 106A, without an arrowhead or circle touching a sym~
are, as well as the execution of arithmetic operations,
thereby preventing current from ?owing in winding 139.
accomplished by a series of electrical circuits performing
the logical functions “AND,” “OR,” and “NOT.” These
functions can be accomplished by various types of elec
If both core A and core B are set, then junction 136 sees
bol for a magnetic element designates an output circuit,
and the phase of the output thereon is designated, for
example, for line 100A, p2.
and in our ?rst embodiment takes one drum revolution
A ¢2 current is also applied to connecting input circuits
or about ?ve milliseconds. The number of minor cycles 50
and other output windings associated with the logical
in a major cycle may vary with computational require
function to be performed. The current impulse of ¢2
ments. In one major cycle each variable operand may
flowing through resistor 1281) to junction 136 is diverted
be changed by a small increment while the error func
away from winding 139 if either core A or B is in the
tion, i.e., remainder, may be changed up to the maximum
cleared or low impedance re?ection state. Voltage E1
value of an operand- Also one increment may be utilized
on winding 139 compensates for the small voltage drops
by numerous minor cycles.
’
across the outputwindings of cores in the ‘cleared state
The interpretation or decoding of program commands
tronic ‘or mechanical circuits but are preferably magnetic
logical switching networks.
a high impedance to ground from both output windings
133 and133il and the current impulse through resistor
1280 flows through unidirectional current device 137 and
to winding 139‘ thereby setting core C. The logical func
tion performed by the described circuit is an “AND"
function, which is designated by an “and” sign “8;” in
Referring now to FIGURE 2, three magnetic switching
cores are denominated respectively by letters A, B, and C.
box 103 as a shorthand schematic symbol. Extra output
Numerals 100, 1il1, and 192 in FIGURE 2A designate
circuit connections 114 and 115 of cores A and B are
the ‘shorthand symbols of elements A, B, and C of FIG
shown by numerals 114A and 115A, respectively, in FIG
URE 2, respectively. In FIGURE 2 windings 131 and
URE 2A.
132 provide electrical inputs to core A. If a high imped
time (not shown) to ground is presented at terminal 1139 70 Additional circuits may be added to any one input'wind
ing for supplying inputs thereto as shown by a second
when an electrical current impulse of 450 is applied through
952 input “D” to winding 139 through diode 138 when the
resistor 128 so that current will not flow to terminal 139,
impedance at terminal 113 is high. - Also, terminals E and
current'?ows through diode 129 and winding 131 to po
F provide two inputs to a second input winding 1320 either
tential E1 ‘thereby “setting” core A. By de?nition, the
current “sets” or forces the magnetic remanence of core
> of which may clear core 0. during 933. Each different
5
3,039,688
6
.
input should be isolated by a separate unidirection current
device. The combination of various inputs to one input
winding can be described logically as an “OR” function.
embodiment thereof consists of ?fteen gated impulses.‘
A shorthand schematic of a shifting register circuit for
generating the ?rst four of such gated timing pulses is
That is, any current furnished by any one or a multiplicity
of input circuits to a single input winding will cause the
illustrated in FIGURE 4. The impulse applied to the
magnetic core shift register at terminal 371 is derived
core to be set or cleared. This logical “OR” function is
from an electrically encoded command (termed herein
designated by a plus sign “+” in the box 104 in FIGURE
“initiate minor cycle”) on the storage drum. This derived
electrical impulse clears the arithmetic device (not shown
in FIGURE 4) of the previous data therein, which data
function described requires all inputs to be time-coincident. l0 is called “Read AP.” The notation for this ?rst impulse is
In FIGURE 2A all functions performed by the sche
2A. Input pulses to such an “OR” circuit may be either
time-coincident or time-separated. Note that the “AND”
.
matic are set down in shorthand notation just described, .
TF8o
‘
‘wherein TP designates “timing pulse,” the superscript 0
the logical expression for the circuit as shown is at the
output terminal of shorthand symbol 102 (core C).
designates the clock phase (¢0) during which the timing
for the output from core C, the plus signs designate the
“OR” functions and multiplication symbols designate
01, etc., through ‘()4 for the shift register under considera
tion. Core 376 is set by pulse
When an element is cleared it contains information desig 15 pulse appears and the subscript ()0 denotes the digit period
of the minor cycle. The digit periods are identi?ed by two
nated as “O” which is read “NOT C”; when the element
decimal digits, the first digit period being 00, the second
is set it contains data designated as “C.” In the formula
“AND” functions so that (AB+D)(E+F)=C is read
20
AandBorDandnotEorFequalC.
The switching networks as ‘described above are herein
combined into basic arithmetic operating units such as
adders, etc.
These arithmetic devices are further com- '
bined to form the arithmetic section of our computer.
Other combinations of these switching networks provide
control, data transfer and other functions required of the
computer. Since the data transfer rate is equal to the
frequency of the digit periods, the time required for any
TP3O
and upon being sensed by a ¢1 pulse from clock 119,
develops a second timing pulse
TPéo
'
25 which is distributed by bus 378 to clear out previous data
increments, and transfer the new “Read AP” into the arith
metic device. ,Pulse
TF3‘,
basic unit to process one digit is made equivalent to one 30 also sets core 386 which provides an output pulse
digit period. Also since the described circuits are time
sensitive, care must be taken to make the various networks
mesh together in time. This is accomplished as illustrated
TPio
for delivery over bus 388 upon receipt of a ¢3- pulse.
Similarly, the output of core 396 which is provided during
in FIGURE 3 for each digit period by providing a cyclic
series of four differently phased electrical impulses which 35 ¢0 of digit period 01 sets the next core (not shown) in
provide the circuit timing throughout the computer.
Longer timing cycles are provided by shift registers which
may be composed of switching networks as illustrated in
FIGURE 4. The electrical impulses which are emitted
the shift register and performs other tasks. The shifting
process continues through 11 more cores to provide a
timing pulse TP during three predetermined phase periods
for the remainder of the ?rst ?ve digit periods. The ¢2 '
by the shift registers are called “gated” timing pulses in 40 clock pulse of digit period 001 is not used for reasons more
evident ‘below. Thus core 386 remains set through two
that they are other timing impulses gated by the outputs
clock phases. Similarly, one core for each of the other
from clock 119.
four digit periods remains set for two clock phases and
To provide the four phase pulse clock sequence for
only 15 gated timing pulses are produced by the shift.
each digit period, the electrical signals obtained from the
timing track of magnetic storage drum 120 are serially 45 register.
applied to the clock 119 of FIGURE 1. Referring now
to FIGURE 13, the structure and operation of the clock
will now be described. The timing track signal is received
on line 460 which distributes it to delay line 464 and
shaper 470'. Shap'er 470 can be a standard one-shot multi
vibrator which generates a single one-microsecond square
Since the switching circuits used by us are time sen
sitive, it is desirable to have a circuit in which electrical
impulses may recirculate and thereby temporarily store
data until the precise moment it is desired. Such a cir
cuit is shown in FIGURE 5 in dash lined box 107 and is
termed a “bit register.” A single electrical impulse
(e.g., “Read AV”) is applied to “OR” circuit 200 and
wave. This square Wave is applied to. a vacuum tube
thereby sets magnetic core 201. This impulse is recir
current generator 480 (an ampli?er which produces a cur
culated between cores 201 and 202 by alternately sensing
rent impulse output), which causes a one-microsecond
current impulse to be distributed via bus 490 as a 450 tim 55 and setting the cores ‘based on the four impulse cycle of
the computer. When it is desired that the impulse par- I
ing impulse. These ¢0current impulses may be applied
ticipate in some function, a gated timing pulse of (#2
to magnetic elements as shown in FIGURE 2 by the
designators “<p0.” The electrical impulse in delay line
(e.g.,pulse
464 is delayed 1.25 microseconds from the input succes
sively to tap lines 461, 462 and 463. Thus a ¢1 current 60
which is tapped by line 461 and formed by shaper 471
and current generator 481 begins 1.25 microseconds after ~~~from ‘the shift register of FIGURE 4) probes “AND”
circuit 203. The impulse from core 202 and the timing
¢0 current, a ps2 current begins 1.25 microseconds after a
pulse form a gated impulse on output line 142 represen
(#1 current etc. ¢1 currents are distributed to magnetic
-core elements by bus 491. Similarly, ¢2 _ currents are 65 tative of, for example, the programmed incremental in
put “Read AV” to the incremental adder within chain
provided to bus 492 from shaper 472 and current gen
lines 105 and 106. After the impulse is gated out, a
erator 482, after which 453 currents are present on bus
subsequent gated timing pulse
~
493 as provided by shaper 473 and generator 483.
y
In addition to the electrical impulse distributor of
TPa'.
FIGURE 3, a longer and different predetermined sequence 70.
of timing pulses is necessary upon the initiation of each
clears core 202 thereby erasing the content of the bit
, minor cycle. This sequence clears the arithmetic section
register.
J
'.
.
' ’
126 of all data from the preceding minor cycle and inserts
In FIGURE 5 there ‘is also illustrated a “AV” bit reg
new data into the arithmetic devices. The sequence spans .
ister which is shown in shorthand form within dash
the ?rst ?ve digit periods of each minor cycle and in one 75 lined box 108 including circuitry which accepts a single
3,039,688
InFIGURE 5 the circuit within dashed lined box 105‘
impulse and as a result thereof generates a stream of
is an exclusive “OR” circuit wherein:
impulses. The lower portion of the register 108 includ
ing “OR” circuit 205, magnetic cores 206, 207, and
“AND” circuit ‘208 is termed “AV” bit register I and it
operates in the same manner as register 107 except AV
is continuously circulated between the cores by sensing
and setting during (#1 and ¢3 while “AND” circuit 208
is probed by a timing pulse
where n is the instant digit position of operand V14
:4
:
T1331
as
m is the number of digits in the operand, Vn is the value
10
of the nth digit position of the operand, Kn is the value
of the carry resulting from the addition during the n-—l
digit position, and G9 designates the exclusive “OR”
The output from “AND” circuit 208 is applied to the
logical‘
function. Exclusive “OR” means either input
upper portion of register 1118 which portion includes
but not both inputs will produce an output. An input
“0R” circuit 210 and magnetic cores 2&9, 21:1 and which
is termed “AV” bit register II. The impulse from cir 15 on line 141 is the operand While the input provided by
core 147 represents the additive carry or the subtrac
cuit 2% sets core 209 and then recirculates between
tive borrow. The circuit in dash lined :box 106 deter
cores 2E9 and 211 based on the four impulse cycle of
mines the termination of the carry or borrow. In ex
the computer. In each subsequent four phase cycle
item 299 is sensed and an electrical impulse is sent to
another circuit, such as the illustrated incremental
adder. Then a stream of pulses is started shortly after
“AND” circuit 208 produces an output and is stopped
by applying a gated timing pulse such as
T1331
to clear core 211 prior to read out.
The presence of an impulse in the “Read AV” bit reg
ister 107 is interpreted to mean an increment (:1) is
programmed as AV for the instant minor cycle. A ma
clusive “OR” circuit 1135 both cores 150 and 151 must
be set to produce V1 output through “AND” circuit 152.
Core 152} is unconditionally set every ¢3 by an input on
line 157. The presence of both an input on line 1141
and an input from core 147 to “AND” circuit 145 clears
core 151) thereby ‘preventing an output therefrom dur
ing the following ¢1. Core 151 is set by both or either
of the inputs to “OR” circuit 146 and produces an out
put to “AND” circuit 152 during the following ¢1, and
if only one of the inputs is present, core 150 remains
set, thus producing an output to “AND” circuit 152 and
consequently a V1 output on line ‘156. If neither input
chine command executed in the preceding minor cycle 30 is presented to “OR” circuit 146, core 151 is not set,
caused the AV increment to be transferred from storage
thus no output therefrom or on line 156.
unit 124 of FIGURE 1 to AV register 108 and inserted
When an increment is to be added or subtracted from
an operand, core 147 is set by the output from register
the “Read AV” pulse in register ‘107. The absence of
such a pulse in register 107 is interpreted to mean no
1&7 on line 142. Cores 147 and 149 cooperate to form
a modi?ed bit register. Thus the impulse from core 147
increment is programmed.- In the case Where register
107 contains an impulse, an impulse in register 108
sets core 149 and the information recirculates until either
‘ core is cleared. Thus Kn initially is a series of l’s, then
some condition is met and for the remainder of the
electrical impulse in register 108 means a minus one
increment. In these cases, a AV of i1 is added to the
40 operand word, K1111). The effect of Kn=1 on Vn is to
V1_1 input on line 141 by the basic incremental adder
complement each digit while the effect of Kn=0 is to
circuit 105, 1% to produce an output V, on line ‘156.
leave Vn unaltered.
When no increment is programmed Vi_1 remains un
Assume +1 is to be added to V‘_1. A series of im
pulses are presented to “AND” circuit 158 and to “OR”
changed, i.e., when “Read AV=O, AV efiectivelyzO and
means a plus one increment, whereas the absence of an
circuit 148' by register 1138. An impulse to “OR” circuit
VET-V14
The subscript “i” as herein used represents the “in
stant” or “ith” minor cycle and subscript “i—l” refers
to the next preceding minor cycle, so that “V1” means
148' clears core 143 which would ‘otherwise set-core‘
144. This prevents an output ‘from core 144 so that
core 147 is not cleared thereby during this operation.
the value of the variable V during the ith minor cycle and
The condition of making K =0 is determined by “AND”
“V14” means the value of V during the preceding minor 50 circuit 158. The other input to circuit 158 is from core
150. Thus the ?rst “0” in V1_1 on line 141 will allow
cycle to which AV, or more properly, AV1 is added to
core 154} to remain set, thus core 149‘ is cleared on the
obtain Vi.
‘FIGURE 5A represents in block symbol* the whole
incremental adder illustrated in FIGURE 5 including
the basic adder 105, .196 with bit storage registers 107
?rst digit in which V :0. Arithmetically, if 1 is added
to a binary number, a carry is generated if the LSD
(least signi?cant digit) of the augend is 1a “1” and that
and 108 as used in FIGURE 8. The function of an in
carry is propagated up to the ?rst digit position contain
ing a zero. The ‘remaining more signi?cant digits must
cremental adder is to add the effective AV increment
:1 or 0 on lines 142 and 213 of FIGURE 5 to the vari
remm'n unchanged which is the case when Kn=0u
able V1_1 on ‘line 141. A pulse on line 142 indicates
Now assume —1 is to be added to V14, which is to
there is an incremental change programmed, while a 60 say, +1 is to be subtracted therefrom. Then no impulses
pulse or lack thereof on line 213 respectively indicates
are emitted from register 1%. As \a result “AND” cir
the direction of that change, i.e., whether plus or minus.v
cuit 15%; cannot produce an output to clear core 149.
The “Read AV” and “AV” input lines for convenience
Also core 143 is not cleared by an output from register
are merged into the AV; input line 155 in the block sym
1%. The ?rst digit of V1_1 containing a “1” sets core
bol of FIGURE 5A for use in FIGURE 8 while the tim 65 143 thereby causing Vn+1=0. In subtracting ‘a +1 from’
ing signal input lines are diagrammatically disregarded
a number, a borrow is required from the next signi?cant
digit if the LSD of the minuend is a zero; this borrow
forsake of clarity.
The further arithmetic operation of the adder of FIG
is propagated to each succeeding more signi?cant digit
URES 5 and 5A may best be explained through the use
until a “l” satis?es the bonrow. The remaining most sig
of logical notations. The letters inside the symbol-s for 70 ni?cant digits remain unchanged.
magnetic elements represent the information content
thereof. For example, the content of element 143 is C
when the element is “set” and 6 (NOT C) when the
element is “cleared.”
This is also noted as “l” for set
and a “0” for cleared in the case of binary notation.
The LSD of V1_1 is always changed during either addi—
tion or subtraction. In binary arithmetic the reason for
this is obvious. Also note that if no impulse is being
circulated in register 197, V1_1 remains unaltered re
75 gardless of the output from register 1138.
3,039,688
9
10
The effect of the 'various timing impules on the cir
cuits is as follows:
In the 22 digit position V2=l; V1=1 and K1: 1, there
Pulse 7
fore
TP},l
'
'
clears cores i149 1and 143 prior to transfer of data from
registers 107 and 108 to circuit 106. This clears out
V1_1=01000101
K:
011 l
V‘:
1 10
In all subsequent digit positions Kn=0, therefore
any possible fragments of data from the preceding opera
tion which could effect the computation being initiated.
The MSD (most signi?cant digit) of the previous oper
and, however, may be and is processed by circuit ‘105 at
V1: Vn for these digit positions. The ?nal ‘resultant is '
V1_1 plus one.
V1_1=01000-l0l
the same time circuit 106 is being cleared. On o2 of 10
K=0~000001l .
the digit period 01 “Read AV” is inserted in core 147.
V1: 01000110: V1_1 plus 1
Core 211 in register 108 is cleared during ¢2 which is
Since there are no provisions for end around carry it
after item 209 has inserted the ‘last impulse representing
is obviousto those skilled in the art that this incremental
the AV of the preceding minor cycle into element 106.
During 963 of this same digit period the new AV is trans 15 ‘adder is designed ‘for the 2’s complement binary nota
tion“. It is also possible to use our invention with the
ferred to core 209 by “AND” circuit 208. Increment
one’s
complement notation of course with different im
AV is added to operand V14 beginning with ¢0 of digit
plementation.
period 02. The LSD of the sum V1 is inserted in the next
Referring now to FIGURE 6A block symbol 116 rep
arithmetic device ‘during 461 of digit period 012. The re
resents a complementer C like the one illustrated in
maining two phases of digit period 02 are necessary to
FIGURE 6 and as used in FIGURE 8. The comple
determine whether or not the carry ‘or borrow is to be
menter performs the function of multiplying ‘an input
terminated.
'
operand, such as S, on line 161 by a minus or plus one
The operation of circuit 106 can be expressed as:
25
increment by, respectively, merely complementing or not
complementing the operand. A complement can be de
?ned as a quantity derived from another quantity by one
wherein the plus signs designate “OR” functions and the
multiplication signs designate “AND” functions. In the
case of AV=“1” (increment is_a plus one) the logical
expression for circuit .106 reduces to
of the following rules, where “b” is the radix of the quan
tities: (a) for a complement‘ on “b,” subtract each digit
of the given quantity from “b-l,” add unity to the least
30
signi?cant digit (LSD) and perform all resultant carries;
(b) for a complement on “b-l,” subtract each digit on
'the quantity from “b-l.” In our computer we use the
complement on 2 in the binary system. Rule (a) in a
since An_1=(Vn_1)(K _1) (“AND” circuit 145). If
2’s' complement binary notation reduces to replacing all
AV=“0” (increment is a minus one) the expression re
35 Us with l’s and l’s with O’s, adding 1 to the LSD and
duces to Kn: (K,_1)(Vn_1)+“Read AV”. Combining
performing all resulting carries. We also ‘de?ne the most
the logical expressions for items 105 and 106 we obtain:
signi?cant digit (MSD) as ‘a sign digit, that is, a “0” '
represents a positive number and “1” represents a negative
number. Thus complementing a number representation
0
40 eliectively multiplies the number‘ by, a minus one. vIn
n=m
_
__
our implementation of complementing, the carry is added
to the complement’s LSD in a serial adder following the
_
= z Vn+{Kn—1(An-1+AV) (AV+ 5-1)
“=0
*
+ “Read AV”}
Where “Read AV”=0
complementer. This is explained later.
Case 1
I
The Read AP register in dash lined box 169 of FIG
45 URE 6 is comparable ‘to register 108 of FIGURE 5.
n=m
“OR” circuit 272 and cores, 274, 276 may be termed a
Vi: Z) V“,
n=0'
“Read AP” Bit Register I, while “AND” circuit 273, “OR"
=Vi—1;
circuit 273' and cores 278, 280 denote a “Read AP” Bit
where “Read AV”=1 and AV=1
Case 2 50
Register II. Gated pulse
TF80
on line 281 clears core 280 which erases the data in that
bit register. In the next clock pulse (¢1 of digit period
=Vi—1 plus 1, and
where “Read AV”=1 and AV=0
00) the new “Read AP” is transferred from Register I to
55 Register II by the coincidence of the output of core 276
Case 3
and pulse
"
.
n=m
Vi: 2 Vn'i'i (VD-*1) (Kn-1) +“Read AV”}
n=0
'=Vi_1 minus 1.
~ in “AND” circuit 273. The outputs of core 278 then
60 form a stream of impulses which set core 166 and probe
As an example let V1_1=01O00101. The case where
“Read AV”'=0 is obvious. {Where “Read AV”=1 and
AV=1, the ?rst or n=0 ldigit position on the right end
(so called the 2° digit position) of the resultant V1=0,
as both V0 ‘and “Read AV”-=l. Thus, with AV=1 when 65
“AND” circuit 160 during ¢3 of each digit period during
the minor cycle under consideration. The issuance of
impulses from register 169 designates that increment AP
has been programmed while ‘absence'of impulses there
from designates that AP has not been programmed.
FIGURE 6 also includes in dash lined box 170 a second
V1_1= 01000101
circuit comparable to register 108 of‘ FIGURE 5, except
that .the input is reversed and inhibitory, that is, an im
_
V1:
.
0
pulse will inhibit an output and no impulse will be trans;
ferred
by “AND” circuit 266, while no input will cause
70
In the 21 digit position V1=0; V0=l and Kn_1=l,
an impulse to be transferred. This change can be called
therefore V1=l and K1='1, giving
complementation. A stream of impulses on output line
162 represents AP=0 and no impulses thereon represents
K:
11
AP=1 in an increment, the complementation effects a
75 change of sign. To “clear” data AP from AP bit register
3,089,688
11
I (which includes “OR” circuit 263, cores 264, 265 and
“AND” circuit 266), pulse
12
circuit 166 then has only two inputs, one from register
170 and the other from a gated timing pulse similar to
the one illustrated. Core 166 under such circumstances
is applied to “OR” circuit 263 by line 261 which causes
is unconditionally set during each digit period by a clock
phase. This removes the requirement for a programmed
element 264 to be set so a pulse will circulate between
cores 264- and 265. The timing pulse, as may be noted,
increment to produce an output. In FIGURE 8 items
226 and 227 are complementers of this type.
’ T1332
occurs during the ?rst clock phase after 453 of period 01
Referring now to FIGURE 7 which illustrates an ex
emplary serial adder, line 172 is a carry input line from
at which time data was transferred to AP bit register II
(“OR” circuit 268 and cores 267, 269) and to “AND” 10 a complementer such as the one shown in FIGURE 6;
i.e., the output of “AND” circuit 160 of FIGURE 6 may
circuit 160. This makes core 264 available to receive
be connected to v172 of FIGURE 7. The carry impulse
data for the following minor cycle starting with 452 of
sets core 187 through “OR”. circuit 173. The output of
digit period 02 and is available up to 4:3 of digit period
core 167 cooperates with U11 and Vn variable operand
01 of the next minor cycle at which time the data is trans
ferred by “AND” circuit 266. The availability of each 15 inputs on lines 180 and 181, respectively, to provide the
bit register is governed by similar rules, that is, the register
LSD of the adder sum. A pulse
is available for data insertion between clearing and read
out.
, rra
clears core 168 at the same time as a complementer carry
In FIGURE 6 “OR” circuit 163, “AND” circuits 164,
168 and cores 165, 166 of the complementer form an 20 is received on line 172. This clears out any carry that
could be left over from the preceding computation.
exclusive OR function of the input variable S on line 161
and the incremental multiplier AP as present on input
line 162.
The circuit operates in a manner similar to
The operation of the circuit of FIGURE 7 is in all
other respects the operation of a typical serial binary
adder which is easily expressed by logical notation as:
circuit 105 of FIGURE 5. When the direction of the
increment is represented in the machine as a “O” (cleared 25
state) the increment is a minus one (the machine only
considers integers). Thus when impulses are present on
where the plus signs designate logical “OR” functions,
line 162 the input on line 161, operand S, should be com
the multiplication designates logical “AND” functions,
plemented; however, with no impulses on line 162, the
input on line 161 should remain unchanged. This is 30 It designates the digit position, S is the digit sum, K is the
‘digit carry, and U and V are input operands. In the case
accomplished by the exclusive “OR” circuit (either input
where n=0 (2° digit position), K114 is the carry from a
but not both inputs produces an output). Core 165. is
complementer. In all other respects it is a typical three
set through “OR” function 163 by inputs on either line
input serial adder which is understood by those skilled
161 or 162, While core 166 remains set unless there are
inputs on both lines 161 and 162. When a “Read AP” 35 in the art.
In FIGURE 7 the digit carry circuits including “AND”
circuits 182, 183, 184-, “OR” circuit 185, and core 186 de
termine the adder digit carry (Kn) which is inserted in
core 188. “OR” circuits 189, 193, “AND” circuit 191
both cores 165 and 166 must be set. “AND” circuit 160
provides the carry to a serial ladder at the beginning of 40 and cores 1%, 192 together with the digit carry circuit
determine the digit sum (Sn) which is inserted in core
each operand digit. When the increment (AP) is trans
194-.
ferred to core 267, the output of core 264 is also sent to
In FIGURE 7A the block symbol 195 represents a
“AND” circuit 160 where in cooperation with a timing
signal has been received by register 169, core 166 is un
conditionally set for each digit of operand S via input line
167. To obtain a “1” output from “AND” function 168,
serial adder such as the one illustrated in FIGURE 7
pulse
45 and is so used in FIGURE 8. The dash line 172 is the
TP31
and an output from register 169, ‘an impulse is formed
representing on line 117 an arithmetic carry.
With an
input to line 162, S is not completed and no carry is sent
to a serial adder; without an input on line 162, S is com
plemented and a carry is ‘sent to an adder for addition at
a subsequent time ‘as explained in FIGURE 7. Circuit
171 is the heart of the complementer with registers 169
and 17 0 being the incremental input registers. Of course,
a carry can occur only when an increment is programmed.
A possible ancillary operation of the complementer is
to change the sign of the incremental input AP. The out
put of the complementer 116 of FIGURE 6A then would
be --SAP instead of SAP. This sign change would alter
carry input line from a complementer, while the two in—
put lines 166, 181 carry the Un and V1, digits to be
summed.
The above described arithmetic devices are connected
together as shown in FIGURE 8. The operands U, V,
S, and R are represented by streams of impulses read off
of storage drum 126. During each digit period the data
is transferred from one arithmetic device into another.
These transfers are continuous even though no opera
tions are being performed. Vacant spaces in the operand
tracks 126V, 120U, 120$, 120R are usually ?lled with
O’s. If one operation is being performed during each
minor cycle one operand follows the previous operand
as a continuous stream of coded impulses. The computer
the interpretation of AP from a plus one to a minus one, 60 separates the operands by the use of an electrically en
coded command “Initiate Minor Cycle” obtained from
or vice versa, and requires no carries to- be added.
section 126M on the drum as later explained. This com
Changing the sign of AP can be accomplished by merely
replacing register 170 with a circuit like register 169.
Then‘impulse on line 162 represents a plus one incre
mand inserts an impulse in the shift register of FIGURE
3. The gated timing pulse from this shift register clear
ment. The input operand is then complemented as pre— 65 out the arithmetic devices and’ insert new data in a pre
wired ?xed sequence. No time is sacri?ced to perform
viously explained. Thus the plus one increment operates
the changes in incremental and operand values. Speci?c
as ‘a minus one increment, and vice versa. In FIGURE
examples of some of these changes are illustrated in FIG
8 complementer 226 is such a complementer and vis so
URES 5 through 7.
I
v
indicated by a minus sign‘before the “C” in the box
symbol.
‘
In some complementers ‘it is desirable to provide only
the direction of increment change; hence the “Read AP”
register 169 is omitted. Then the effect of not program
ming an incremental change would be to provide a con—
70 The incremental values are inserted in the proper bit
registers during the preceding minor cycle by machine
operations which are independent of the arithmetic op
, erations. The manner of execution of such operations is
later explained in connection with FIGURES 9, 10, and
The streams of electrical impulses on the storage
, stant minus one increment (instead of a zero). “AND” 75 11.
3,039,688
13
it
drum are physically displaced an integral number of
digit periods so as to be read out during the proper digit
By restricting the change in each variable within the
computer to a change in the least signi?cant digit (LSD)
each major cycle, the above mentioned incremental opera
period. Thus each digit of the four operands is always
read from the drum during clock phase zero.
tions can be accomplished by addition or subtraction.
The exemplary incremental adder of FIGURE 5 may
For a machine handling only integers, this means a change
be used as incremental adder 223 of FIGURE 8. The
of :1 each. major cycle. The size of the increment
output of this incremental adder is transmitted over line
usually should be small enough with respect to the size
240 to data converter '127 (shown in FIGURE 1) and
of the operand so that an error equal to the size of the
to the magnetic storage drum for recirculation to become
increment would be negligible in the output. I his im- .
V1_1 in the next major cycle of computation in the corre 10 plies the operands change a negligible amount each major
sponding minor cycle. Incremental adder 224 may also
cycle.‘ This further implies that to obtain satisfactory
be like the one in FIGURE 5 and operates in a manner
control the response time of the process being controlled
similar to adder 223 but is timed by different clock
must be much longer than a major cycle time. - For our _
phases. For example, the output of adder 223 may be
?rst implementation a process having a time constant
during ¢1, while the output of adder 224 is during ¢0. 15 in the magnitude of seconds can be satisfactorily con
Thus the operation of adder 224 is advanced One clock
trolled. The practical limit of the accuracy of numerical
phase with respect to adder 223. The outputs of adder
solutions is the time required to effect the changes in the
224 are transmitted to complementer 227 and to drum
variables.
track 120U.
.
‘
An incremental computation may be performed in each
The exemplary oomplementer illustrated in FIGURE 20 minor cycle which modi?es one or more operands pursu
ant to an algorithm by incrementally changing both inde
pendent and dependent variables. This‘ change in the.
variables can be called updating.
exemplary adder illustrated in FIGURE 7. Similarly
Three machine numbers (represented as three streams
dash lines 250, 251, and 253 designate carry transmission 25 of impulses) designated as R, U, and V maybe processed
lines from other complementers to other serial adders.
in the arithmetic section 1260f FIGURE 1 ‘during each
The carry transmission circuits are identical except they
minor cycle. They are modi?ed according to the follow
may use different clock phases 'for timing. The carry
ing equations which represent the operation of our new
6 may be used as complementer 225 of FIGURE 8. The
carry from this complementer is applied, as indicated
by dash line 252, to serial adder 229 which may be the
determinating “AND” circuit 160 of FIGURE 6 will
have only two inputs for complementers 226 and 227 of
FIGURE 8 as previously explained.
basic algorithm.
'
.
The serial outputs of adders 228, 229, and 230 form
serial inputs to successive serial ‘adders 229, 230, and 231,
respectively. The clock phase of these outputs is the
same as the clock phase of the inputs to the next serial
The subscript i denotes the ith major cycle of compu
adder which is always ¢1. The output'of serial adder 231
represents the computed relationship of variables in equa
tions designated by the computer program of machine
tation and Greek letter A denotes an incremental value
of an operand; for example, AV, is the increment (a
change in LSD) of operand V in the ith major cycle. The
basic algorithm is illustrated in block diagram form in,
commands. This relationship is called an error function
and is designated R, as is the single line upon which it 40 FIGURE 8. Incremental adder 224 solves Equation '1,
incremental adder 223 solves Equation 2, while the com
appears in FIGURE 8 for storage in the single R- line or "7
register on drum track 120R_ The error function or
plementers 222, 225, 226 and 227 with serial adders 228,
remainder is recirculated through magnetic drum track
229, 230 and 231 solve Equation 3. Each carry generated '
in a complementer consists of an impulse which is in
‘ serted as indicated by ‘dash lines 250, 251, 252 and 253,
“AND” circuit 255 gates the last digit (MSD) of the 45 respectively, into a serial adder’ (in a manner such as
120R to be used in the next major cycle to compute a
new error function ‘or remainder for the same equation‘.
output from serial adder 231 as the sign digit. A gated
timing pulse from the shift register in FIGURE 4 probes
shown in FIGURE 7) just preceding the arrival of the
I operands to that serial adder so that the carry is effec
tively added to the LSD of the operand which except for
“AND” circuit 255 over line 256 during 431 of digit period
R1_1 to adder 231 is a complemented number. "
'
04 thereby transmitting the sign of R1 over line 257 for
storage in the memory unit 124 of FIGURE 1. The sign 50 To insert initial values in the beginning of a new series ‘_
of computational cycles, switches 232 and 233 are
digit of R1 is used to determine increments in other equa~
switched in the V0 and U0 positions respectively and
tions and an increment (usually AW1) in the same equa
switch 234 is opened. V0 and U0 are constants which for
tion in the next major cycle of computation.
the incremental operation to ‘be'performed produce a zero
The function of the above described circuits as an
arithmetic unit is more aptly described through the media 55 error function R0. The normal position for switches 232
and 233 is in the V1_1, UPI closed position, while switch
of mathematical notations." The described circuits pro‘
234 is closed.
vide but one means of implementing the techniques of our
invention.
‘
Basic Algorithm
Our mechanization of incremental techniques is accom
plished by de?ning a basic algorithm around which other
algorithm can be constructed by a program of electrically
encoded commands. Some of the algorithms which canv
be programmed are incremental addition, incremental
subtraction, incremental integration, incremental multi~
plication, incremental division, incremental logarithms
Each track on drum ‘120 has one type of data associated
therewith; i.e., track 120R provides a single delay line type
60 storage for the error functions or remainders, track 1208
stores the scaling constants S, track 120110 stores the ini
tial values of U, track 120U provides delay line type
storage for variables U, track 120Vo stores initial values
of V and track 120V provides delay line type storage for
variables V. Numeral 120M designates all other tracks
on the drum not associated directly withour basic algor
ism.
and incremental exponentials. Incremental operations '
The incremental values used in the algorithm are
differ from regular mathematical operations in that the
selected by the electrically encoded program commands.
complete function is never solved; The operations merely 70 This selection or sequence of selections‘ provides vmodi?
relate outputs. to inputs, that is, the outputs vary as a
cations of the basic algorithm yielding the basic opera
speci?ed function of an input or multiplicity of inputs.
tions of the machine, such as, incremental scaled multi
Thus initial values of inputs, outputs and intermediate
numbers must be inserted in the computer prior to com
The sum produced by incremental adder 223, V1, is
putation,
‘
'
plication.
'
I
a
recirculated through track 120V to become V1_1 in the
sped-see
16
corresponding minor cycle of the i-i-‘l major cycle and is
Substituting the value of SW0 from Equation 6 which
sent to the data converter for comparison with an analog
input or output. In our computer a program command
from one of tracks 129M causes a comparison to be initi
calling RO=‘O, gives:
(11)
SWg+R1<=UOQ1<+ VoT1£+SPi<
expresses the initial conditions into Equation 10 and re
ated via control unit 123 (see FIGURE 1). Thus each
V1 is not necessarily compared with an analog value.
Similarly, the sum produced by incremental ‘adder 224,
U1, is recirculated through the drum storage system on
track 120U to become U14 in the i+1 major cycle. This
sum is also combined with other values in the serial adders
which divided by S is:
(12)‘
p
Wk'i‘Rk/S= (SPE-I- UoQlr‘i‘ VoTk) /S
Equation 12 the computed sum is equivalent to Equa
tion 4 the desired sum whenever the “round off” error
Rk/S is negligible. It can be shown that W is either with
in :1 of the correct solution or is in transition at its max
shown to form a new error function or remainder R, as
expressed by Equation 3. This newly computed error
imum rate toward the correct solution.
function is likewise recirculated through the storage drum
The desired general equation for MUL'HPLIOATION
on track 120R to become error function or remainder
R14 in the i+1 major cycle provided a new problem is 15 is:
not initiated. Other factors contributing to the newly
(13)
W=(UV+SP) /S=UV/S+P
computed error function are the Scale factor S, previous
The quantities U, V, and P are independent variables and
error function R14 and the incremental values AT1, AUi,
the quantity S is any positive or negative constant. To
AP, and AW, as selected by the computer program of
obtain such an equation, the operands and increments are
commands. The sign digit which is the most signi?cant 20 restricted as follows:
digit (MSD) of R1 is transmitted to the magnetic core high
(.14)
(15)
(16)
(17)
AQ1=AV1
ATi=AU1
R,,=0
SW0: UoV0+SPo (initial conditions)
(18)
' Awi+l=iilj fgr R; iiegative
speed storage 124 for future reference in determining cer
tain incremental values as noted in the explanation of
machine operations.
Machine Operations
25
Algorithms for arithmetic and other processes are ob
tained from the basic algorithm, as expressed by Equa
tions 1, 2, and 3, by restricting certain operands and in
1 f r Rt
ositive
crements and by inserting proper initial values.
These 30 The sign of AW1+1 is reversed when S is negative. Incre
ment AW1+1 is programmed as ‘the incremental output of
similar to those described in connection with FIGURE 2..
this machine operation.
functions are performed by logical switching networks
Substituting Equations 14 and 15 in Equation 3 gives:
In all cases the initial error function or remainder Rust);
Further, it is to be noted that in implementing each of
the following incremental computations, there needs to 35 (19) R1=R1_1+UiAV1+Vi_1AU1+SAP1-SAW1
be’ but one register or line for storing any remainder R1,
and since
this being, in the exemplary apparatus of FIGURE 8, on
(20)
drum track 126R.
A‘
( UiVi) = UlVl_' Ui—lVl-1
In incremental ADDITION and SUBTRACTION the
=‘( U1_1'+A U1) (V1-1‘+AVi)'- U1-1Vt-1
40
desired general equation for solution is:
(4)
=V1_1AUi+U1_1AVi-|-AUiAVt
W=<SP+ UOQ.+VOT) /S
.
The quantities S, U0, and V0 can be positive or negative.
: V1__1A U1+ U1AV1
Substituting Equation 20 in Equation 19:
To obtain such an equation, increments are restricted as
follows:
(21)
(5)
Summing over ‘K major cycles of computation:
AU1='AV1=0
R1‘—Ri_1= A(U1V,) +SAP,-—SAW1
(22)
while the initial conditions are
The increment AW1+1 is caused by the sign digit (MSD) 50
of R1 via “AND” circuit 255 (FIGURE 8) to be a plus
one for R1 positive and a minus one for R1 negative when,
as is the usual case, scale factor S (a constant) is positive,
but if S is made negative the signs of the increment are 55 Substituting the value of SWo from Equation 17 into
Equation 23 and recalling RD=O gives: I
reversed. The computer is programmed so that the output
increment of the ith cycle becomes AW,“ in the corre
sponding minor cycle of the i+1 major cycle. Substitut
ing the restricted values from Equation 5 in Equation 3
and using initial values for variable U and V gives equa
tion
(8)
Equation 25 the machine product is equivalent to Equa
tion 13 the desired product whenever the round of error
Rk/S is negligible. As in the case of addition, item be
shown that W is either within :1 of the correct value or
is in transition at its maximum rate toward the correct
/
Ri=Rl~1+UOAQl+ VOAT1+SAP1_SAWl
Summing over k major cycles:
65
solution.
'The desired general equation for incremental DIVI
SION is:
(26)
U: (SW-SP) /V
The quantities W, P, and V are independent variables, the
quantity S a scaling constant, and the quantity U is the
dependent variable. The correct algebraic sign must be
assigned to the quantity V as an initial value since the
dependent variable U becomes'in?nite as V goes through
75
zero.
.
3,039,688
" 17
The operands and increments are restricted as -follows:
’
.'
18
.Summing over k major cycles:
-
(27)
AQ,=AV,
_
q
(28)
AT1=AU1
(29)
Ro=0
(so)
UOVO=SWO—SPO (initial conditions)
( 42)
’
k
-
5
is
k
‘
k
§(Ri—Ri—1)=§A(U?)+SgAPi_S;AWi
'
(43)
-
_
_
.
Eli-.1579:U§~U§+SPk_SP°-sWk+SWn
0
(30a) AW1+1=¥+<1 for R1 positive and —:1 for R1 nega
tive when Sis positive; signs reversed when S is 10 Combining Equations 37' 211N143:
negative '
(44)
+1, for R; positive and Vi negative
Rk=Ui+SPk—SWk
(45)
AUi+1: +1’ for R‘ negaiive and V‘ posjiiive
*1, fol‘ Rt POSltlve and Vi posm"?
.
Uk=‘/S———————Wk_SPk+Rk
Equation 45 the computed square root is equivalent to
15 Equationg33 the “desired square’root whenever Rk can be
—1, for R, negative and V; negative
Increment AUl 1 is programmed to be the output in
+
v
V
7 neglected. The same remarks ‘apply to Uk as in division.
The above operations all produce results without ap
-
I
y
‘
0
goes a change
of
of slgn’ for vahd Opemuons the Slgn’of V1 20 tra ezoidal inte gtion with increments corres ondin
is always known.
-
.
P
algorism is the same as the multiply algorism. The
(
e equa on or
(46)
SWk+Rk= UkVk-L_l_SPk
,
'
U = SW
)
‘
k
(
R —SP
+ k
'
tion.
.
30
W=2/SfUdQ
k
t
k
-
> (47)
-
Wi.=2/s;E%<Ui+Ui_1>/>Qie2/sfUdQ
Equation ‘32 the machine quotient is equivalent to
1=1
Equation 2.6 the desired quotient whenever ,Rk can be
neglected.
1s.‘
'_
following expression for the‘kth major cycle of computa
’
/V
k)
q
As in the case of multiplication, it can be
shown below.
V _U
tion or is in transition at its maximum rate toward the
’
correct solution.
’
U=\/SW—SP
,
(35)
R
(53)
.
45 '
.
0
-
Increment AW1+1 is programmed to be the ouput in
crement of this operation. When S is negative the sign
Substituting Equations 48, 49, and 50in Equation 3:
U§=SW°—SP,, (initial conditions)
.
AW1+1=+1 for R1 positive and ~11 fOl‘ R, nega-
(
tive when S is positive; signs reversed when S
is
negative.
'
)
+1’ “I R‘ negative
' '55
v
'Increment AU1+1 is programmed to be the output 'in-
v
{=1
‘
’
—-SAW
‘
‘
V
»
H
‘
i=1
i
I
I
k
'
Rk—'1j;|°=22%(Ui+Ui.i)AQi---SWk-{—SW° ' ~
.
(57):
65
t
H _ i=1 . l
'
°
Substituting Equations '34 and 35 in Equation 3:
'-
U_A
,
(56)
.
'
i
l
AVi=AUi=—AT;=——AQi and U=v SW-SP]
Ri==R1_1+U1AU1+U‘_1AU1+SAP1——SAW1
UA
‘ 1+. ‘ Q1+ 1 1 Q‘
i0: R ) iw +U )AQ Sim
crement of this operation. If SW--SP_iS negative, the signs
AV1 and AQ1 are reversed; that is,
'
60
i
1
Y
(55)
AUi+1={—1, for Bi positive
and since
R=R_
'
.
(38)
54
Summing over krnajor cycles of‘computation:
7
_
(39)
AWi+1={+1ff°r
Ri Positifle
—1, for Bi negative
0f AW|+1 is reversed.
_ _ _
(37a)
Wo=d?sired Value fol‘ integral with Q=Qo~
'
o:
(37)
A111: AQ‘
RO=PO=AP1=O
(52)
The operands and increments are restricted as follows: >
V°=U°
AQ1=AT1=AV1=AU1
I
40 (51)
a scaling constant, and U is the dependent variable.
-
AVl=AUi
(50)
The quantities W and P are independent variables, S is
(34)
(35)
°_ °
(49)
The desired general equation for SQUARE ROOT is:
‘
'
The algorism for integration restricts the operands as
shown that Uk is either within +1 of the correct solu- 35 (48)
‘~ (33)
g
.The approximation for integration is represented in the
I
32
p
‘5mm 6 5mg I ,I;fresi§§rEGRAeTiI6leqg1:aj
>
Solving for Uk:
.
.
z?eénaif’resent gm desliectlhiogroil tonly Im the extent that
from Equation 19 to Equation 24, above and the latter 25
(24)
.
.
derivation of the basic expression follows the same proof
equation is now stated again.
gr'
to the least count of the independent variable. Therefore,
Except for the choice of dependent variable, the divide
i:
.
1
l
.
l k
_
'Wk+R1</$=2/5§%(Uii-Ui~1>4Qi+Wu _
Equation 57 the machine computed integral represents
the desired integral as described in Equation 47 except
‘for the round oif error term Rk/ S which is minimized as
=<UH+AUi>2— ‘24*
70 in' the previous operations.
=Ui-1AUi+Ui-1AUi+AUiAUi
=U,_,AU,+U,AU,
The desired equation ‘for INTEGRATION of a RE
-
_CIPROCAL lNTEGRAND is:
Substituting Equation 40 in Equation 39 gives:
'( 41)
R,_.RH=A_(Uf)+SAPi-SAWi
(65) i i I
v 75
~ .
7,
Qv=1/2SfdW/ U
Integration of a second form with a reciprocal inte
"3,039,688
is
.
.
.
,
.
.,
.
for Q.
42b
The basic relationship 5shown above “may be obtained
grand can be obtained by'jsolving the following equation
by solving Equation 73 for W.
_
(73)
gel/2s Leg, W
2Q/S=Loge W
(81)
e2Q/S=W
The restrictions placed on the operands‘in the machine
This form is obtained by restricting the operands in
the general machine algorism as listed below.
algorism are the same for this condition as for the loga
The dependent variable in this case
10 is chosen as W instead of Q.
'rithmj operation.
,-
__ +1, for Ri positive
(82)
AW ‘+1_{—— 1, for Ri negative
The sign of AW1+1 is reversed if S isnnegative. Incre
‘(71) ~Qg=value of the integral for the initial conditions
ment AWHI is programmed to be the output increment of
this operation.
(71a) , AW1+1=+1 for'Ri positive and -l for R1 nega
Other basic operations can be generated from the ma
chine algorithm than are presented here. Among these
‘are a number of, operations based on rectangular (rather
tive when S is positive; signs reversed when S is nega
tive.
'
(72)
'
‘
20
; +'l,'for Ri negative
AQ‘+ll_{—l, for R; positive
yield the result shown below. The expression could be
Except for the choice of independent and dependent
solved for any one of the variables in terms ‘of the others.
variables, this algorism is the same as that for the ?rst
integration form.
than trapezoidal) approximations to integration. The
basic machine algorism as it stands, for example, .would
_
Substituting Equation 68 and Equation 69' in Equa
In addition to straightforward solutions in which the
unknown quantity is isolated, the incremental method of
tion3:
V30
Summing over k major cycles of computations,
computation is particularly useful for implicit ‘solutions.
In such a solution the implicit function of the dependent
variable is equated to zero as shown below.
(72c)
The function, F(x), is computed with basic operations
35
p
I
the basic operation is used as a‘ servo similar to analog
‘_
equipment.
The sign of AQ1+1 is reversed if U, is negative. The
Errors In Machine Computation
sign of U never changes as it is the denominator in Equa
tion 65. AQlH is programmed to be the output incre
ment of this operation.
In digital incremental computers there are generally
three types of errors, namely; program errors, round o?
The desired general equation for the LOGARITI-IM is: f'
errors, and drift.
(73)
Q=S/2 Loge W
The basic relationship shown above may be‘ obtained
from expressi'on‘65 by equating the‘ quantitiesU‘and'W.
(65) '
I
Q=11/2sjdW/.W
=‘1/2S Loge W
major cycle of computation. Inqthe ?nal operation for
determining F(x) the result is left at zero and the sign
of ‘R1 used to modify the implicit variable, x, rather than
the solution of the last basic operation. In such a case
Neglecting the effect of the R’s (error functions=0)"i'n
Equation 720, the machine computed integral represents
the integral of Equation 65,.
using the value of the dependent variable from the last
7
V
The incremental function generated by the incremental
computer may not coincide with the function for which
the program was designed. The difference between the
50 desired answer and the computed answer is‘ called pro
gram error. This error is a function of the human pro
The restrictions iplace'diion ‘the operands in ‘the basic
machine algorism are listed below for this condition.
' the computer, and the
gramming,
erations available for use.
quality of machine op
'
.
Round o? error is caused in any digital computer when
' the quantity handled exceeds the modulus of machine ca
pability. In the digital incremental computer this round
01f error in computer inputs is usually no greater than
vplus or ‘minus one and is slightly more on output quanti
ties even assuming the computer is following the transient
conditions properly. The'computer increments must be
(78)
Q°=value of the logarithm ‘for the initial condi
tions
(78a) AW1+1=+l for R1 positive and ——l for R1 nega
tive when S is positive; signs reversed whenS is nega- -
as large as a‘transient occurring in one major cycle to
enable the computer to follow all changes in variables. By
proper-design this error can be kept very small.
The round o? error of outputs from addition, sub
65 traction, multiplication, and integration‘steps 'is the term
Rk/S in the kth majorcycle. This value is usually less
than unity, but it can become as large as three even
AQi+1={— l, for Bi positive
when the computer is properly following the inputs. To
this error small the answer should ‘be as large as
The sign of Q1+1 is reversed if'Wi is negative. 'The'sign p70 keep
possible
with respect to the possible error. For addition
of W cannot change for a valid computation. Q1+1 is pro
grammed to be the output increment of this operation.
This algorithm is a special case __of Equation 65.
The desired equation‘ for an EXPONENTIAL is:
and subtraction the quantity SP+ UOQ +>V°W/ S should be
Likewise for multiplication
UV/S+P, and for integration (2/S)SUdQ must be kept
‘kept as large as possible.
as large as possible. 7 The quantity S is the only quantity
adjustable to accomplish this. Thus scale factor S should
3,039,688
“21
2.2
be just large enough to allow the computer to keep up
minor cycles. The ?rst of the three minor cycles is termed
the preparation cycle, since during this time the binary
pulses representing the required incremental operands hav
with the changes.
>
In the ,“exact” operations round off is the only apprecia
ble error occurring. The round off value is not discarded,
ing effective values of 0 or i1 as programmed are trans
but is retained to minimize this error. The round off 5 ferred to the arithmetic unit 1216 vfrom the command trans
error thus is from the ?nal round off.
In operations using integration, error called “drift" oc
lator and control unit 123‘ and storage unit 124. These
transfers, as noted previously, effect the computation in the
curs which is the accumulation of round off errors. Drift
arithmetic unit of FIGURE 8. Upon completion of this
‘error can be compared to drift occurring in analog in
minor cycle all incremental values are usually in the
tegrators due to errors in instrumentation. vIn analog 10 arithmetic unit. The second of the three successive minor
cycles is termed the computation cycle. In .this cycle the
devices the direction of drift (whether plus or minus)
usually is consistent. In digital integrations the errors
basic algorithm is performed using the programmed in
are likely to be of opposite signs and thus tend to cancel.
cremental values .to modify the variables pursuant to the
Drift is then either predictable or not predictable, that
desired functional relationship. In the embodiment FIG
is either systematic or random. The former can be com
URE 8, it takes ?ve digit periods before the LSD is proc
pensated for in the algorithms while the latter is usually
essed through all of the arithmetic circuits after it is read
negligible.
'
off the drum. Likewise there is a delay of ?ve digit
Simple Machine Operation
periods before the last digit (MSD) is processed from the
‘drum through serial added 231. Thus, assuming an 18
How our computer executes an incremental operation
20 digit word for R1 for example, the last output of the arith
is illustrated in FIGURES 9, 10, and 11. To understand
metic section always lags the initiation of a new- minor
fully the functions performed, more detailed background
cycle by ?ve digit periods. The incremental result, A,
of our embodiment is given. Referring for a moment ‘to
of any incremental computation, even when R, is less
FIGURE 11 which encompasses FIGURES 11A and 11B,
tracks 120M on magnetic storage drum 120 in FIGURE 25 than 18 digits, is always programmed, however, so as not
to be available until the minor cycle following the actual
11B furnish the control electrical impulses to the com
computation. During the sixth digit period (05) of this
puter. Track T actually is two physical tracks. One of
third cycle the incremental results of the previous minor
these tracks has a polarized magnetic spot in each possible
cycle are stored in the storage unit 124- if a digit (storage)
digit position which identi?es the peripheral location of
all digit positions on the drum and indicates to clock 30 address is programmed at this point. If a digit address
is not programmed the increment is not stored. This
119 the beginning of a new digit period. The length
. ?nal minor cycle is called'the storage cycle. The operand
of a digit period is a function of recording density and
digits are stored serially on magnetic storage drum 120
drum surface speed. This time also determines the maxi
as the ‘arithmetic processing produces each digit.
mum rate of data transfer in'lthe computer. Electrical
A major cycle of computation is initiated by a machine
impulses derived from these polarized magnetic spots are
command. This command is located in the digit period
used to time all circuits in the computer providing com
plete circuit synchronism. Each derived pulse generates
preceding the ?rst initiate minor cycle command. Usu
timing impulses occurring respectively during time periods
ally only one major cycle is initiated per drum revolu
tion. The major cycle command synchronizes the start
indicating a machine command or address.
more than one operation can occur during any given
three additional pulses providing a total of four electrical
¢0, ¢1, ¢2, and Q53 per digit period, as heretofore ex 40 ing of the computer with the program so that the com
putation begins with the proper minor cycle. This com
plained. The other physical track has only one magnet
mand does not initiate any machine operations as de?ned
ized spot. This spot provides descrete identi?cation of all
by the Basic Algorithm but is used mainly to identify the
magnetizable spots on the drum. It may be used to
beginning of a program. The major cycle command and
identify the initiation of a new major cycle of computa
machine code representation is illustrated in FIGURE
tion; in one embodiment, however, this latter track is 45 its
10 and will be referred to later.
used only in loading the com-puter.
For purposes of visualizing a ‘speci?c embodiment and
The tracks 2° through 26 are read simultaneously in
how the system' of ‘FIGURE 8 may be employed so that
each peripheral position to form a seven-bit binary code
A method
of decoding or translating these impulses is described later 50 minor cycle, assume that ‘a major cycle is equal, to one
revolution of drum 120 and that there are N minor cycles
in connection with FIGURE 12.
I
per major cycle. At any instant of time, i.e., in any minor
A minor cycle has no de?nite restraints except hard
cycle, say cycle N-lO, while the incremental operands
ware (electrical circuit timing) limitations. The length
are ‘being obtained in preparation for computation during
and function of each individual minor cycle is pro
grammed. The length of a minor cycle in digit periods .55 the following minor cycle N -—9, actual computing on a
different problem may be occurring relative to a diiferent
is usually twice the signi?cance of the operands U, V,
set of incremental operands obtained during ‘a prior minor
and S and equal to the signi?cance of error function R.
In our ?rst embodiment it is possible that one minor cycle
be equal to one major cycle in a minimal program or al
most 500 minor cycles at the other extreme. Once. a 60
minor cycle is initiated by the computer program, it con
tinues until a new minor cycle or a new major cycle is
initiated. For example, if a particular program of com
mands occupies about one-half the periphery of the mag
cycle such as cycle N —ll. Also, during cycle N-lO,
input-output operations can be accomplished. That is,
‘for example, V, may be readout during cycle N —10 to
data converter 127 (FIGURE 1) wherein it is compared
to an analog input to cause a new analog output there—
from and ‘an incremental output to storage unit 124.
Each of the different analog inputs and analog outputs
may be associated with a different phase of an over-all
netic storage drum, the second half of the drum is con 65 problem. For example, in a chemical processing problem,
sidered a part of the last minor cycle even though all
one analog input may be related to one measured input
computation has been completed. In constructing such
quantity while an analog output may control a valve reg
a program the second half of the drum usually,:would
ulating the rate of ?ow or amount of a different quantity.
contain all command codes indicating “no action.”
Other analog inputs and/ or outputs may be similarly re
Usually in any one minor cycleno machine operation
lated to other quantities such as temperature, pressures,
is ever completed. In our ?rst embodiment only a com
parison of an input‘or output quantity with a computed
number can be accomplished in one minor cycle (but usu
ally covers two minor cycles). Each arithmetic operation
output rate, etc. Continuously controlling such variables
under varying conditions may call for incremental solu
tions to several different types of mathematical relation
ships, such as those set‘ forth above under “Machine
utilizing the basic algorithm requires three successive 75 Operations.” Therefore, V1 in one minor cycle may be
Документ
Категория
Без категории
Просмотров
2
Размер файла
3 629 Кб
Теги
1/--страниц
Пожаловаться на содержимое документа