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June 26, 1962
|_. _1. ANDREWS ET AL
3,040,986
MAGNETIC CORE LOGICAL CIRCUITRY
Filed Oc‘b. 11, 1956
lO Sheets-Sheet 1
June 26, 1962
1_. .1. ANDREWS ET AL
3,040,986
MAGNETIC CORE LOGICAL CIRCUITRY
Filed OCT.. l1, 1956
10 Sheets-Sheet 2
June 26, 1962
L. J. ANDREWSv ET AL
3,040,986
MAGNETIC CORE LOGICAL CIRCUITRY
Filed Oct. l1, 1956
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1_. J. ANDREWS ETAL
3,040,986
MAGNETIC CORE LOGICAL CIRCUITRY
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June 26, 1962
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MAGNETIC CORE LOGICAL CIRCUITRY
Filed 00T.. l1, 1956
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United States Pateûf 0 n ice
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3,040,986
Patented June 26, 1962
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arrangement for interconnecting and driving a plurality
of magnetic core registers to perform step-by-step digital
MAGNETIC CORE L GICAL CIRCUITRY
Ladimer J. Andrews, Gardena, Walter G. Edwards, Man
hattan Beach, and James F. Hudson, Hermosa Beach,
Calif., assignors to The National Cash Register Com
pany, Dayton, Ohio, a corporation of Maryland
Filed Oct. 11, 1956, Ser. No. 615,279
32 Claims. (Cl. 23S-176)
processing on data stored therein.
.
It is a further object of this invention to provide
means for performing logical operations, such as addition,
utilizing a minimum number of magnetic cores as com
ponents for computation and control.
A broader object of this invention is to provide a mag
net-ic core circuit mechanization of a Boolean expression
This invention relates to electronic circuits for generat lO characterized by the feature that no additional cores are
ing digital processes on stored data and more particularly
required to include additional logical terms in an existing
to novel circuit arrangements employing magnetic cores
logical function once the terms have been generated.
capable of successively performing logical manipulation
Logical functions can be derived in an existing mechaniza
of the data as the digital process advances.
tion by merely passing a conductor through the proper
Logical functions, which can be defined by Boolean
notation, for example, are mechanized in digital com
sequence of cores in magnetic coupling associationwith
some embodiments, vacuum tubes and diodes, either
severally or in combination. Such facilities are charac
each. lt should be obvious that a system of this nature is
inherently economical and that the economy increases as
more complex functions are to be derived. Specifically,
this economy is a result of the feature of the invention
yterized by various disadvantages. Thus, in the case of
vacuum tubes, limited operating life, high power con
sumption, and circuit complexity are involved. ln the
uct to only the number of conductors that can be induc
tively coupled to the core structure.
puters by basic circuitry and equipment utilizing, in
which limits the number of propositions in a logical prod
A feature of the invention resides in the representation
case of diodes, the introduction of a term as an additional
of a logical proposition as a signal which is coupled to the
condition to a logical function already mechanized re
quires an additional diode; furthermore, as diode networks 25 core structure so as to inhibit the switching of the core
from the false to the true state by its driving currents.
become complex, as in multilevel matrices, the design of
sources which supply operating voltages -for driving these
networks also becomes more complex. Additionally, the
and, by this means, introducing the logical value of the
proposition into the core. An inhibiting signal is arranged
to have the ability to cancel the switching effect of the
electrical characteristics of diodes have been found to
30 driving current but does not itself ever drive the core.
change as they are used for extended periods of time.
As a result, the source of the inhibiting signal is never
It is thus desirable to adopt other constructions, which
are superior in at least these respects, to circuitry arranged
required by the switching action to furnish power, re
to synthesize a logical function.
gardless of the number of cores which comprise its load.
A related feature is that the inhibiting signal is not re
quired to supply power to compensate for power reduc
A basic component of continuously increasing utiliza
tion approaches the ideal for these purposes. This com
ponent is the magnetic core having a substantially rec
`addition to having many characteristics which overcome
the above-stated deficiencies of vacuum tubes anddiodes,
tion of the driving signal. This is because the only time
lan inhibiting signal could be required to furnish such
power is when a core changes state; and, since the func
tion of the inhibiting signal is to prevent core switching,
is possessed of exceptionally long life and electrical prop
the driving current source cannot suffer loss of power.
erties consistent over extended periods of use.
The art is cognizant of the fact that magnetic cores so
Further objects and many of the attendant advantages
of the invention will become apparent by referring to the
following detailed description of the drawings, in which:
tangular hysteresis characteristic. The magnetic core, in
utilized must be driven, i.e., arranged to be switched, to
one or the other state of remanent magnetization, by cur
FIG. l is a block diagram of a serial adder which isY
rents flowing in windings inductively coupled to the core
constructed in accordance with the techniques of the
structure. One known system supplies core drive from
present invention.
FIG. 2 is a schematic diagram of the serial adder shown
other cores and is thereby enabled to arrange cores to
synthesize logical expressions. However, cores are not
in FIG. 1.
FIG. 3 shows a hysteresis loop of the magnetic material
considered to make good drivers in this instance since 50
they do not represent constant current or voltage sources,
employed in the core switches.
FIG. 4 shows a group of waveforms used for serially
in that their output is a function of the number of other
sequencing the operation of the adder circuits shown in
cores comprising their load. Further, for each logical
term, as described by the Boolean equations, to be mecha
FIG. 2.
nized in a circuit, the core-driving-core technique necessi 55 FIG. 5 shows an alternate group of waveforms to those
tates the incorporation of one or more additional cores;
of FIG. 4.
must be coupled tothe driving core by a multiple winding.
FIG. 6 shows a group of waveforms representing the
core flux pattern and the induced voltage in the core sense
Thus, when mechanizing complex functions, in accord
conductor caused by the application of a magnetomotive
and, if the cores are to be the same in size, the conductor
ance with the known technique, the number of cores 60 force of switching amplitude.
required becomes large and the Winding thereof becomes
FIG. 7 is a block diagram of the register transfer cir
intricate, involving a considerable increase in the at
cuit.
FIG. 7a is a set of curves illustrating the operation of
tendant difticulties of construction.
Accordingly, it is an object of this invention to provide
the transfer circuit.
a new and improved magnetic core switching arrangement 65 FIG. 8 shows the network provided for supplying the
for generating logical functions.
Another object of this invention is to provide magnetic
signal wc-l--ws used for controlling the transfer circuit.
core logical circuitry which, in combination with other
input amplifier.
storage cores and a transfer circuit, provides a highly
versatile arithmetic register for use in a large-scale digital 70
flip-flop.
computer.
Another object of this invention is to provide a novel
cuit flip-flop output amplifier.
FIG. 9 is a schematic diagram of the transfer circuit
FIG. l() is a schematic diagram of the transfer circuit
FIG. 10a is a schematic diagram of the transfercir
3,040,986
3
4
FIG. l1 is a schematic `diagram of the transfer circuit
transfer circuits generate inhibiting signals correspond
driver-ampliñer.
ing to their states and the selected storage cores of the
E and F registers and the K register not wound to be in
hibited by these respective signals are set.
FIG. 12 is an example of the additionI of the two
binary numbers referred to in describing how adder cir
cuits according to the present invention operate.
FIG. 13 is a graph of waveforms showing the voltage
at various points of the adder of FIG. 2, while perform~
The »above operation prevails for the general mech
anization of arithmetic processes capable of Boolean ex
pression. Specific mechanization for the process of
serial addition involves only the proper Winding of the
storage cores to effect inhibition of setting with signals
ing addition.
FIG. 14 is an `adder truth table showing the derivation
of the logical equations mechanized by the circuits of
the present invention.
represented by the corresponding logical propositions Vin
FIG. 14a shows how the K register control cores gen
erate the terms of the carry digit Boolean equation.
FIG. 15 isa schematic diagram of a computer register
used »for illustrating the mechanization of various basic
logical operations in accordance with the circuit ar
rangements of the present invention.
FIG. 16 tabulates the operations accomplished by the
circuit of FIG. 15, showing how the E register control
cores `for performing these operations are selected by the 20
the adder equations derived, as Well understood, from
a simple truth table. The logic which controls the gen
eration of these signals is contained in the winding ar
rangement ofthe control cores and it is significant to note
that the transfer circuit for each register is utilized by its
respective storage and control cores in common.
Thus, once the cores and their assignments in the
registers have been established for an arithmetic process,
such as addition, other arithmetic processes, such as sub~
netic cores in the logical circuitry comprised in the
traction, multiplication, etc., may also be mechanized,
utilizing these same cores by merely providing inhibiting
signal windings Iappropriate to the Boolean equations
representing these other processes. It is this character
central processor of a digital computer.
istic of the invention which contributes a versatility in
program control.
The present invention refers to the utilization of mag
Thus the in
vention is embodied in, for example, a computing device 25 the lart not previously contemplated.
comprised in the main of three registers. Each register
Referring now to FIG. l of the drawings, there may
contains two arrays of magnetic cores, one array being
be seen an operational diagram of a serial adder to which
employed for the storage of the binarily coded digits to
the teachings o-f the present invention may be adapted.
be manipulated, `and the other array being employed for
Included in this diagram are the designations of the ele
purposes of performing the manipulation of these digits. 30 ment which will be later shown to accomplish the op
Bach register also includes a transfer circuit, hereinafter
eration in a preferred circuit embodiment.
described, which functions toysequentially read out in
The adder illustrated comprises means to add into an
formation from the arrays, delay this information and
accumulator, the E register storage, order by order, a bi
set it up as inhibiting signals capable of affecting the
nary number setup as an addend in the F register storage,
switching of the cores in the arrays. In the preferred 35 taking into account the carry~in binary digit from the
embodiment, which exemplifies the invention by a cir
previous order, as stored in the K register storage. Four
cuitry arrangement for adding yfour-order binary num
place binary numbers will be considered, although it
bers, the three registers are designated the E register,
should be understood that the principles to be developed
the F register, and the K register. By the use of these
are adaptable to binary numbers of any length within the
registers, as controlled by externally supplied timing Ysig 40 handling capacity of the digital computer of which the
nals and the aforementioned internally generated inhibit
adder may form a part. It should further be understood
ing signals, the particular circuitry arrangement shows
that, in a computer embodiment, the number of register
how a serial addition of the four binary digits of the add
cores and the number of conductors coupling to the indi-Iv
end, as set up in the four storage cores of the F register,
vidual core might be greater than shown if a variety of
can be made to the four binary digits of the augend, as 45 logical functions are to be synthesized so that they can be
set up in the four storage coresV of the E register, utilizing
serially carried out on a time-sharing basis in accordance
the single storage core of the K register in which’to set
with a scheme of computer operations such as is common
up the single bin-ary digit of any Vcarry generated by a
ly represented by a fiow diagram. To illustrate the inven
partial addition. The timing signals of the preferred
tion, therefore, the present showing comprises extracts of
embodiment include ya pair of clock signals and storage 50 equipment relevant to the operation of addition.
core selecting signals.V The latter define digit transfer
For simplicity, it will be assumed that initially the
cycles of equal duration, and essentially serve to sequen-V
storage cores of the E and K registers are cleared and that
tially select the binary digits to be added, commencing
with the least significant. The combination of the clock
. the F register has been filled with digits from a computer
memory, for example. The designations P1, P2, P3, and
signals with the storage core selecting signals establishes, 55 P4 denote signals representing “digit transfer cycles.”
for the digit transfer cycle of each step of a data process,
These signals define sequential cycle timing periods dur
such «as partial addition, a sequence of four equal time
periods within each digit transfer cycle. These four
periods are designated symbolically as period Rs, period
We, period Rc, and period Ws. During periods `R'sV and
Rc, interrogation, i.e., read out, -ofthe storage and'con
trol cores, respectively, Vis done; andV during periods'Wc
and Ws, setting, i.e., writing into, the control and storage
cores, respectively, is done. More particularly, during
ing each of which one of the orders 20, 21, 22, 23 in the
addition takes place. Thus, the first serial operation, oc
curring during the first digit transfer cycle, for which sig
60 nal P1 is effective, is the addition utilizing control circuits
10 of the least significant digit (20 order) of the addend,
as stored in core 1Fs, to the least significant digit (20
order) of the augend, as stored in core lEs, to form the
least significant digit (20 order) of the sum. The se
the four periods of a digit transfer cycle, operations areV 65 quence of core “interrogation” and “set” within the digit
ordered as follows. 'During period Rs, the selected stor
age cores of the E and F registers and the K register are
interrogated :and the transfercircuits are set inl accord
ance with 'the digits read out; duringV period We, theV
transfer cycle, as already outlined, is determined by clock
signals Cs and Cc, the for-mer shown entering all storage
cores and the latter shown entering control circuits 10.
'Ihe clock signals Cs and Cc each combine with the digit
transfer circuits generate inhibiting signals corresponding 70 selector signal P1, Which latter signal passes through both
to their states and the control cores of all registers not'
wound to be inhibited by these 'signals are'set; during
period Rc, the control cores of all registers are interro
gated and all transfer circuits are set in accordance with
the storage and control cores of the 2° order, to properly
sequence the operations to be performed during each low
\ est order digit transfer cycle. The sum digit is set up in
core 1Es and any resultant inter-order carry is stored in
the information read out; and’ during period WS', the 75 core lKs. ' The digit previously stored in core 1F.; of the
3,040.986
6
major hysteresis characteristic, i.e., B-H curve, such as
the one shown in FIG. 3. The states of bistability previ
ously referred to prevail after core saturation, and are the
F register is reset therein, as will also be done during
higher-order additions. That is to say, the F register in
formation, in the present embodiment, is recirculated or
restored, i.e., information read out of, for instance, core
two polarities of core remanent magnetization, here
1Fs, via line 17 is reset therein via line 18. This need not 5 designated “true” and “false,” which will characterize
the core indefinitely if no further energy is applied.
necessarily characterize other embodiments wherein it
The excitation, HM, required to drive a core from
may be desired to clear the F register (set all storage cores
one state of saturation, eg., -BM, to the other, e.g.,
thereof false) or enter other information into the F regis
ter during the addition operation.
-l-BM, is critical, and the application of less than this
The remainder of the four-place addition is handled by 10 critical excitation, although causing nominal excursion,
nevertheless does not essentially change the previously
control circuits 10 sequentially as determined by digit
polarity of saturation. However, upon the application of
selector signals P2, P3, and P4, to produce the ultimate sum
excitation at least equal to the critical value in a direction
inthe accumulator (E register storage cores IES to 4Es),
to cause the core to take on a polarity of saturation op~
any carry-out in storage core 1Ks of the K register, and
the prior addend in storage cores 1Fs to 4Fs of the F 15 posite to that presently existing, the polarity of saturation
will abruptly “switc ,” as from the true state to the false
register.
state along the path of the descending arrow or from the
Referring next to FIG. 2, there is presented the sche
false state to the true state along the path of the ascending
matic of a serial adder operative in accordance with the
diagram of FIG. 1 and embodying the principles of the
invention.
The three registers comprising the adder are designated
the E, F, and K registers, and all are connected to period
signal generator 16 and to driver signal generators 38, 39,
and 40. All of these generators are driven from a com
mon pulse source 15. The E, F, and K registers each in
cludes a plurality of magnetic cores and a transfer circuit
22, 23, or 24, respectively. As shown, th-e magnetic cores
arranged in the E, F, and K registers may be considered
in each case to form two sections, a storage section com
prising groups 2'5, 26, and 27, and a control section com
prising groups 28, 29, and 30, respectively. It may be
noted that the number of cores is different for various
ones of the sections. Thus storage section 27 (K register)
and control section 29 (F register) are comprised of but a
single core each, control section 30 (K register) is com
prised of three cores and the remaining sections are com
prised of four cores each. It will be later shown that the
arrow.
20
Referring again to FIG. 2, in the present system, each
of the conductors supplying signals to the registers is
connected to circuitry capable of generating a “half
current” of energy, i.e., half the excitation required to
change the state of the core, or no excitation, i.e., zero
25 current, at a particular time.
Such conductors, which
pass through and couple a core with the same electrical
sense so that currents therein are cumulative in their
elîect on the core polarity, are so indicated by diagonal
marks across the cores in the same direction, such as
30 diagonals 50 and 51.
Such conductors which are poled
oppositely to these are indicated by diagonal marks of
opposite slope, such as diagonal 52.
Switching, therefore, is done by the coincident applica
tion of half-currents from two sources. As previously
35 stated, these sources are a clock signal Cs or Cc, and a
digital selector signal P1, P2, P3, or P4. Further, core
switching may be prevented by the application, coincident
number of cores required for a storage section corre
with the above, of a half-current from one or another
sponds to the number of binary digits .to be stored in the
register while the number of cores required for a control
section corresponds -to the number of sum terms of the
of several other sources, i.e., an “inhibiting” signal from
one of transfer circuits 22, 23, or 24.
composite logical equation describing the operation of the
A core, if in the true state, will be switched to the false
state by half-currents in the same direction, right to left
register of which the control section is a part.
A plurality of conductors passes through the cores of
in FIG. 2, on one of the conductors 36 and on conductor
3S or conductor 37. A core, if false, will be switched
the registers. Conductors 35, 36, and 37 supply pulse-type
45 true by coincident half-currents from left to right, unless
38, digit selector signal generator 39, and storage clock
otherwise inhibited. If it is understood that currents
from left to right are positive and those from right to left
signal generator 4Q, respectively. It may be seen that con
are negative, it may be seen that, for core 1Es, for in
signals into the cores from control clock signal generator
stance, only a positive half-current on each of the con
ductor 35 is impressed with control clock signal Cc, that
conductor 37 is impressed with storage clock signal CS, 50 ductors carrying signals P1 and Cs flowing simultaneously
can switch the core to the true state, and conversely only
and that the four conductors designated 36, for simplicity,
are each impressed with one of the digit selector signals
P1, P2, P3, and P4. Sense conductors 47, 48, and 49 each
a negative half-current on each of these conductors tlow
ing simultaneously can switch the core to the false state.
It will be further understood that, when a core is to be
pass through all cores of only one register and carry pulse
type signals from the cores to transfer circuits 22, 23, and 55 interrogated, it is supplied an uninhibited full negative
current so that its resulting condition is the false state;
24, respectively. Conductors 41 to 46, inclusive, return
pulse type signals from transfer circuits 22, 23, and 24 to
the cores of all the registers.
In threading lthrough the core array of a register, the
aforementioned conductors may be inductively coupled
to a core or may entirely by-pass a core. Coupling to a
core is by means of a single winding about the core ma
terial in a direction such that, in the case of conductors
supplying signals into the cores, a signal appearing on the
and, that ywhen a core is to be set, it is supplied an un
inhibited full positive current so that its resulting condi
tion is the true state. Thus it follows that a negative half
O current emitted simultaneously from storage clock signal
generator 40 and from digit selector signal generator 39
can interrogate storage cores while a positive half-current
emitted simultaneously from these generators can set
storage cores. Similarly, a positive half-current emitted
simultaneously from control clock signal generator 38
conductor will contribute to changing the core state in a
prescribed direction and, in the case of sense conductors
carrying signals out of the cores, a change in core state
will induce a signal on the conductor. It may be pointed
and from digit selector signal generator 39 can set con
trol cores while a negative half-current emitted simul
out that the well-known device of reversed phase winding
cores.
of sense conductors on successive cores could be em
ployed to maximize the cancellation of “shuttle” voltages
induced by half-select currents affecting cores not fully
selected.
The magnetic material, of which each core is com
taneously from these generators can interrogate control
With further reference to terminology to be employed
herein, it will also be noted that a core in the true state
will be considered to be storing a binary digit “one” and
this state for core 1Es, for instance, will be symbolically
denoted IES, while a core in the false state will be con
posed, is distinguished preferably by having a rectangular 75 sidered to be storing a binary digit “Zero” and this state
3,040,986
8Y
for core 1Es, for instance, will be symbolically denoted»
IES’. When defined in its Boolean notation, i.e., in terms
of the outputs of the transfer circuits, the signal required
the true state, causes the induction of positive voltage
pulse 70. In line III, low-level induced voltages such as
pulse 69 are also produced when core magnetism changes
from saturation BM to remanence BR. Lines IV, V, and
to set this core to the true state will be designaed as les,
while the signal required to interrogate this core to the 5 VI present similar curves for a control core, such as core
false state, which in the present embodiment occurs at
lEc (FIG. 2).
the end of every Ws period, will be designated as cles.
FIG. 2 further indicates that the signals generated by
digit selector signal generator 39, control clock signal
generator 38 and storage clock signal generator 4G are
synchronized via common pulse source 15, which may be
a multivibrator or the like capable of operation at about
a 400 kc. repetition rate. Such sources are familiar and
will not be detailed here.
Additionally, it is observed that an “or” gate 20 is sup
plied with signals Wc and Ws by period signal generator
16.
Generator 16 comprises a network, the outputs of
which are square wave signals ranging from 0 to _l0
volts in amplitude synchronized to appear on the re
spective lines during periods W,z and Ws. This type of
arrangement is also well-known and will not be fu-rther
discussed.
Referring now to FIG. 4, here isV shown the group of
The art is well versed in techniques for generating
square wave signals of current, such as signals Cs, Cc,
and P1 to P4, inclusive. It should therefore suiiice to
point out that each of these is a recurrent square wave
shape with excursions of half-current amplitude, when
present on their respective lines. It should be noted that
the waveshapes of FIG. 4 will be used for illustration
herein. It should also be noted that signal CC is iden
15 tical to signal CS, but is shifted two periods with respect
thereto, and that each of these signals is at the zero
current level for half of the digit transfer cycle, all as
indicated in FIGURES 4 and 5. Further, it should be
observed that signals P1, P2, P3, and P4 appear succes
20 sively on their respective conductors, but whichever is
presently effective is synchronized with the generation of
signals Cs and Cc, as shown. Thus, it follows that in
the exemplary apparatus each of these P signals pre
timing current waveforms, which, when generated syn
vails only during every fourth digit transfer cycle, but
chronously, are capable of sequentially interrogating and 25 is equally effective in establishing, by combining with
setting cores through which the conductors carrying these
Cs and Cc, the four iterative periods Rs, We, Rc, and Ws.
signals are passed. Each is a square waveform of current
It has been pointed out in connection with FIG. 2
having maximum values, such as at regions 54 and 55
that pulse voltages induced on sense conductors 47, 48,
of the signal Cs wave, equal to the positive or negative
and 49, as a result of change in core state, comprise the
half-current. -These maximum values, for each case, exist 30 inputs to transfer circuits 22, 23, and 24, respectively,
for a time period somewhat in' excess of the switching
and that the transfer circuits are identical. These circuits
time required by the core material, and the phasing of
will now be described with reference to the E register
the currents in such that a core is interrogated at a coin
transfer circuit 22 shown in FIG. 7.
cidence of negative half-current of signal Cs or Cc with
Voltage pulses carried by conductor 47 provide an input
a negative vhalf-current of signal P1, P2, P3, or P4, and 35 to amplifier 6i). The phase of each of these pulses is nega
is set at a coincidence of positive half-current of signal
tive, owing to the direction of threading conductor 47
CS or signal Cc with a positive half-current of signal
through the cores. Amplifier 60 is gated by a second input
P1, P2, P3, or P4. Both coincidences occur twice during
signal WC-i-Ws from “or” gate 2t). This latter signal has
the digit transfer cycle, the periods of the occurrence of
the ability to cut ofi conduction in amplifier 60 during
the former being designated Rs (affecting a storage core) 40 periods Wc and Ws and, thus, only signals on line 47
and Rc (affecting a control core) and the periods of the
which occur during periods Rs and Re appear in amplified
occurrence of the latter lbeing designated Wc (affecting
form on line 61. Line 6l connects as one input line to
a control core) and Ws (affecting a storage core).
flip-flop El, and the signal on the line is designated as
FIG. 5 shows an alternate set of waveshapes which
input e1. Flip-flop El is constructed in accordance with
will accomplish the same sequence of interrogation and 45 the familiar arrangement which permits triggering from
setting of cores. In this figure, for simplicity, signals
one of its bistable states to the other by only negative
P1, P2, P3, and P4 are generically designated as signal
going voltage pulses applied alternatively to a pair of in
P. With this arrangement, however, it should be noted
puts. Input el thus has the ability to set this flip-flop
that the sense of the P and CC windings through control
to the true state. Flip-flop El is set to the false state by
cores would be required to be opposite to the sense re 50 an input oel, represented by the logical sum Wc-I- WS. The
quired by the waveshapes of FIG. 4. In other words,
actual triggering occurs as a result of the negative pulse
a coincidence of negative half-currents can set a 'control
core while a coincidence of positive half-currents can’
interrogate a control core.
produced by differentiating the fall of these waveforms,
i.e., at the termination of either of the periods Wc or
Ws by conventional R=C differentiating circuits as shown
FIG. 6 presents a group of waveforms illustrating the’ 55 at 76 in FIGURE l0. Thus, flip-liop El may be triggered
effect on core state of the application of magnetomotive
true during periods Rs and Re as a result of a change in
force of switching amplitude, i.e., a full current flowing
state of one of the E register cores; and, if so, this state
through core windings. Line I shows the total current
will prevail until the end of periods Wc and Ws, respec
-applied to a storage core, such as core lEs (FIG. 2) dur
tively.
ing a digit transfer cycle (FIG. 4), assuming that no in 60 Flip-flop E1 is characterized by two outputs. One out
hibiting currents are present. It is seen that a negative
put, El, on line 74, is high only when the flip-flop is in
full-current amplitude 56 exists during period Rs, a posi
the true state and the other output, El', on line 66, is
tive full-current amplitude 57 exists during period Ws,
high only when the flip-flop is in the false state. Both out
and zero current amplitude 58 exists during periods Wc
puts are amplified and in-verted by identical amplifiers, the
and Rc. The resulting flux pattern for a prior true condi 65 former by amplifier 72 and the latter by amplifier 7l.
tion of the core is shown in line II. It is evident that
the flux pattern variations, such as fall 62 and rise 63,
Considering amplifier 7l as exemplary, it is seen that its
input is also gated by signal Wc-l-Ws. However, due to
are along the hysteresis loop (FIG. 3) in accordance with
the circuit arrangement of amplifier 7l, a signal on line
change in current amplitude. Line III is a graph of the
66 is passed only during periods We and Ws, and conduc
70
voltage induced on conductor 47 of core 1Es (FIG. 2)
tion is cut off during periods Rs and Rc. The output of
as a result of the changing flux pattern. It is noted'tthat
amplifier 71, also designated as output El, is employed
phasing is arranged such that a negative full-current ampli
as the input on line 65 to driver-amplifier 68. Driver
tude 56 (line I), in interrogating a core to the false state,
amplifier 68 provides a current output on line 42 in phase
causes the induction of negative voltage pulse 73, while
with its input, this current being of half core-switching
a positive full-current amplitude S7, in setting a core to 75 amplitude i/Z and is also designated as E1. Driver-ampli
3,040,986
,
.
9
fier 67 is identical to driver-amplifier 68 and provides a
current output i/Z on line -41 when provided with an
input, i.e., when flip-flop Ei is in the false state during
periods Wc and Ws. Thus one of the transfer circuit out
put half-currents, El’ and El, on conductors 41 and 42,
respectively, may appear only during periods Wc and Ws.
Conductors 41 and 42 pass through the register cores
(FIG._ 2), being coupled to selected cores so that these
signals may inhibit the setting of the cores.
FIG. 7a contains curves which further illustrate the
10
core, is passed through amplifier 60` during only periods
Rs or Rc and is reproduced on line 61 as input el to fiip
ñop E1. The gain through amplifier 60 is such that an out
put pulse will be of l0 volts amplitude below reference
ground potential. In summary then, the output of ampli
fier 60 .on line 61 comprises an amplified negative-going
reproduction of any negative-going input pulse of suffi
cient amplitude applied during periods other than Wc
and WS. As is well known, transistor 59 possesses the in
herent property of discriminating against low-level in
operation of transfer circuit 22 for two representative
duced voltages such as pulses 69 of line III of FIG. 6
digit transfer cycles.
E register cores will be assumed during two successive
caused by a core state changing from a condition of satu
ration to a condition of remanent magnetization. It is
interrogation periods, RC and Rs, resulting in the shown
desired that only pulses such as pulse 73 of line III, caused
The successful interrogation of
negative pulses 80 and 82 of the e1 wave on line 61 (FIG. 15 by core switching, be passed through amplifier 60.
7). Amplifier y60 (FIG. 7) is active during these periods
It is thus seen that the true input el to flip-ñop E1 com
and thus pulses 80 and 82 provide true triggering pulses
prises only negative-going pulses which may occur only
84 and 86, respectively, for hip-flop El. However, at
during periods Rs or Rc.
the end of every set period, i.e., at the `fall of pulses Wc
Flip-liep E1, shown schematically in FIG. l0, is seen
and WS, such as 87, 88, and `89, «false triggering pulses are 20 to be of conventional design, having a pair of transistors
produced, such as pulses 90, 91, and 92, respectively,
cross-coupled so as to maintain one mode of conduction
which reset flip-fiop E1 to the false state. Output E1 on
until triggered by a negative-going pulse applied to the
line 74 becomes high in potential coincident with pulses
base electrode of the conducting transistor, at which time
84 and 86 and -becomes low in potential coincident with
the other mode of conduction will prevail. To illustrate,
pulses 91 and 92, and output El’ on line 66 becomes low 25 if flip-iiop »E1 is false, i.e., output E1 on line 74 is at -8
in potential coincident with pulses 84 and 86 and high in
volts and output El' on »line 66 is at +2 volts, a negative
potential coincident with pulses 91 and 92, respectively.
going pulse e1 on line 61 will cause output El to abruptly
Since amplifiers 71 and 72 are cut off during interrogation
rise in potential to -1-2 volts and, simultaneously, output
periods, it is during period WSl of the first digit transfer
El’ will fall to the -8 volt level. Flip-flop E1 is thus trig
cycle and period Wc of the second digit transfer cycle that 30 gered into the true state, and will remain in this state
output E1 on line 65 is high and output 'El' on line 65a is
until triggered false by a negative-going pulse „e1 which
low in potential. It follows that output El, on line 42, is
will occur at the termination of periods We or WS.
likewise high `and output El', on line 41, is likewise low
Outputs El and fEl’ of fiip-fiop E1 are each amplified
in potential during these periods. Thus, as a result of a
and inverted in amplifiers 72 and 71, respectively. These
change of state of an E register control core during 35 amplifiers are identical and for purposes of illustration,
period Rc of the first digit transfer cycle, for instance, an
the latter is shown in FIG. 10a.
inhibiting signal half-current 93 (El) is supplied on line
‘Ampli-fier 71 is seen to provide single stage amplifica
42 at the output of the E register transfer circuit 22 dur
tion of an input on line 166, gated to pass the input only
ing the next period W5; but when there is no change of
when the emitter of transistor 75 is at the 0 volt level,
state of an E register control core, as during period Rc 40 i.e., only during periods Wc or Ws. The output on line 65
of the second digit transfer cycle, there is an inhibiting
is clamped at the -10 volt level during periods Rs or Rc
signal half-current 94 (iEl’) supplied on line 41 at the
and will rise to 0 volts during periods Wc or Ws only if
output of the E register transfer circuit during the next
hip-flop E1 is false.
period Ws.
FIG. ll shows driver-amplifier `6‘8, a conventional two
FIG. 8 shows “or” gate 20, which generates the logical
stage amplifier which serves as a source for the relatively
sum Wc-l- Ws fed as input to transfer circuits 22, 23, and
high half-currents required for inhibiting the switching
24. Inputs WC and WS to “or” gate 20 will lbe understood
of cores. input is on line 65 from amplifier 71 (FIG.
to `comprise square Wave signals clamped between the
10a) and the output, in phase therewith, is also designated
potentials O and -10 volts. This `circuit is well known
as signal El and appears on conductor 42 which threads
to operate such that the output signal Wc-l- WS is at the 50 through -the registers (FIG. 2). Driver-amplifier 67 of
-10 volt level unless one or both of the inputs Wc or 'Wsl
FIG. 7 is identical in all respects to driver-amplifier 68
is at the 0 voit level, for which case the output signal
and provides the inhibiting signal output designated E1'
Wc-l- Ws will also be at 0 volts. The generation of inputs
on conductor 41.
to these networks is by combining the outputs of a pair
In summary, transfer circuits `22, 23 and 24 (FIG. 2)
of flip-hops, the inputs to which are triggered in syn 55 supply half-current inhibiting signals to the E, F, and
chronism with signal CS. Since the circuits for generating
K registers in accordance with a prescribed scheme, `as
such inputs are familiar to practitioners of the art, they
follows. If a core changes state during an interrogation
will not be further discussed, and the symbols Rs, We,
period (period Rs or Rc), an inhibiting signal appears
Rc, and Ws will serve to designate the periods of the digit
during the following set period (period Wc or Ws) on the
60 transfer circuit true output conductor `42, 44, or 46 of
transfer cycle.
The details of the circuits comprising transfer circuits
the register containing the core; if no core changes state
during an interrogation period, then an inhibiting signal
22, 23, and 24 will next be described with reference to E
appears during the following set period on the transfer
register transfer circuit 2x2 of FIG. 7.
Amplifier 60 is schematically shown in FIG. 9 to be a
circuit false output conductor 41, Á43, or 45, respectively;
single stage amplifier with two inputs. One input is pro
and, finally, any changes in state of a core during the set
periods are ineffective in that they are prevented from
vided on conductor 47, on which a negative voltage pulse
entering the transfer circuit.
appears whenever a core of the E register changes state.
An examination of the arrangement of the wiring of
This input is coupled to the base of transistor 59 in ac
the cores in the registers of FIG. 2 will show that the
cordance with the indicated polarity =by means of trans
former 64. The other input, from “or” gate 20, is con 70 cores can be affected by various transfer circruit in
hibiting signals generated during set periods WC `and WS
nected to the emitter of transistor 59 and operates to cut
of a digit transfer cycle. The following tables Ia, Ib, and
off transistor 59 when the emitter is of positive polarity
Ic list the cores for each of the registers and indicate the
with reference to the base, i.e., during peniods Ws or Wc,
inhibiting signal outputs of the transfer circuits with
at which times this input is at 0 volts. Thus, a pulse on
line 47, produced by a change in state of an E register 75 which each core is wound. The tables also show the
3,040,986
l1
'12
`
periods that the inhibiting signals noted are able to
For core IEC to be set at period We, inhibiting signals
aíect the setting of the cores.
E1', F1', or K1’ (Table la) must not be generated. There
It should be noted that the control cores of a register
fore, it is only if all three cores yl’Es, -1Fs, and lKs are
always reside in a “zero” Astate prior to period Wc and can
true at period Rs, that core >113s Will be true at the end
be set into a “one” state at every Wc period if none of 5 of the digit transfer cycle: 1eS=1Es1Fs1Kg In other
the inhibiting signals with which they are wound are
Words, taking into account only control core ilEc, it is
effective, i.e., high in potential during Wc.
only if cores lEs, \1Fs, and .1K3 lare all initially storing
`It should be further noted that the selected storage
“ones” that core lEs will ultimately store `a “one”
cores of the register also are all in a “zero” state prior
For core ZEC to be set at period Wc, inhibiting signals
to period Ws, the ones stored therein having been read
E1', F1', or K1 must not be generated. Therefore, i-t is
out during the previous Rs period, `and thus each of
only if core 1Es is true and cores 11‘Fs and 1Ks are false
these cores can be set into a “one” state during a P
at period Rs that core lEs will be true at the end of the
selected Ws period if none of the inhibiting signals with
digit transfer cycle: 1eS=1Es1Fs'1lKs’. Stated in other
which they are wound are effective, i.e., high in potential
words, taking into account only control core ZEC, if core
during WS.
lEs is initially storing a “one” and cores tlFs and lKs
Table Ia-E Register
are initially storing “zeros,” then core lEs will ulti
mately store a “one”
Cores
Signals which
Period
can inhibit
setting of
setting of cores
core can
For core `3Ec to be set at period Wc, inhibiting signals
E1, F1', or K1 must not be generated. Therefore, it is
only if core lFs is true and cores 1Es »and lKs are false
at periol Rs that core 1Es' will be true at the end of the
occur
'
digit transfer cycle: leS=1Es’1Fs1Ks’. In other Words,
lEc
Control _______________________ __
taking into account only control core 3Ec, if core 1Fs is
intially storing a “one” and cores IîEs and lKs are initial
ly storing “zeros,” then core IES will ultimately store a
“one”
For core 4Ec to be set at period Wc, inhibiting signals
2Ec
3Ec
4Ec
lgs
Storage ....................... ._
2 8
SES
4E3
E1, F1, 'and K1’ must not be generated. Therefore, it is
Table Ib-F Register
Cores
only if core lKs is true and cores IES and lFs are false
30 at period 1Rs that core lEs will be true at the end of the
Signals which
can inhibit
setting of
setting of cores
core can
digit transfer cycle: 1eS='1ES’1Fs'lKS. In other words,
Period
taking into account only `control core 4Ec, if core IKS is
initially storing a “one” `and cores 1Es and lFs are
occur
initially storing “zeros,” then core IES will ultimately
Control _______________________ -_
lFc
W1,
llES
121g:
2 ‘3
store a “one”
The four partial addition terms may be combined to
Z
Storage ----------------------- -> are
Pawî
form the complete expression for the conditions for which
4F3
P4We
a digit ultimately established in the core 1Es will be a
‘Gonezß’
Tab'ie Ic-K Register
40
t
Signals which
Period
Cores
can inhibit
setting of
setting of cores
core can
lEs'lFs SKS
This overall expression is interpreted as meaning that
core llEs will ultimately store a one if all three cores lEs,
lFs, and lKs are already each storing a one or if any one
occur
1K0
Control ....................... _-
2K6
E1’; F1’ ________ _~
We
_
SKc
Storage _______________________ __
1K3
The periods of a'transfer cycle occur, as previously de
of them is already storing a one.
It should be obvious that the same derivation also will
describe the state of the other orders of the iinal sum
since, lin a register, all control cores cooperate to deter
50 mine the state of each storage core in turn. If, there
fore, the gener-al symbols Es, Fs, and Ks are employed
to designate the E, F, and K register storage cores devoted
scribed, in the following order: Rs, Wc, Rc, and Ws.
Thus, in illustration, with reference to the E register cores
-shown in Table la, it should iirst be noted that cores 1E.;
Will go true, i.e., store a “one,” at period P1Ws unless
inhibiting signal E1’ is generated at period PlWs. Signal
to any one order, the above expressionbecomes:
55
E1’ will not be generated at period Ws if at least one of
the cores lEc to éEc, inclusive, was successfully in
terrogated, i.e., a digit one was read out, at the previous
period PIRC. Therefore, one of these control cores must
be set at period P1Wc in order to enable cores lEs to 60
be eventually set true during period =P1Ws.
FIG. 14 presents the generalized adder truth table and it
is noted that the arrangement of control cores and inhibit
ing windings in FIG. 2 is in accordance with the adder
expressions derivable from the table and shown therewith.
The logical function of addition will next be particularly
described with reference to FIGS. 12 and 13 which exem
pli‘fy the `activity of the elements of FIG. 2.
This description applies to each of the remaining cores
rFIG. 12 shows an example of the addition of the
ZES, 3Es, and 4Es, realizing that these cores are `selected
binary number 1011, which is the addend stored in rthe
one at a time by signals P2, P3, and P4, respectively, to be
F register, to the »binary number 0110, which is the
come operative, in turn, with all of the control cores 1Ec 65 augend stored in the E register. The incoming carry, 0,
to 4Ec, inclusive, comprising the E register logic.
is stored in the K register. The four lower order digits
The sequential operation of the circuit elements of FIG.
of the sum 10001 will be established in the E register,
2 will now be generally -analyzed for the ñrst digit trans
the addend, 1011, will 'be re-established in the F register
fer cycle of an addition, P1, in which the linal state of
and the outgoing carry, 1, will be set up in the K regis
core lEs (partial sum) will be Vshown to be a function 70 ter. Inter-order carries generated by the partial addi
of the initial states of the cores IES (augend), `IFS (add
tions for the 2U, 21, and 22 orders will, temporarily, also
end), and lKs (carry), as shown in Table Ia. It will
be set up in the K register as the addition proceeds.
be noted that a core in the ltrue state is considered to be
FIG. 13 contains line graphs of the waveshapes describ
storing a “one” and `a core in the false state is considered
ing the activity of circuit elements of FIG. 2 in the ac
75 complishment of the addition of FIG. 12.
to be `storing a “Zero”
'
3,040,986
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_
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.
.
14
.
As already pointed out, four digit transfer cycles are
required to add the four place binary addend into the ac
cumulator, the digits of the 2° order being added during
cycle P1, the digits ofthe 21 order being added during
ly `stored in the F register can easily be modified to its
“ones” complement during the addition if, yfor instance,
a subsequent computer operation involves a subtraction.
This is accomplished simply by utilizing the opposite
cycle P2, etc. The digits of each order are stored in
separate storage cores, the digits of the 20 order being
stored in cores lEs and lFs, the digits of the 21 order
outputs F1 and F1’ of transfer circuit 23 as inhibiting sig
nals, one for storage cores lFs and 4Fs and the other for
control core lFc. With this circuit arrangement, regard
being stored in cores ZEs and 2Fs, etc. During cycle P1,
less of the initial state of a storage core, its state at the
then, the digit in core lFs is added to the digit in core
end of its corresponding digit transfer cycle will be the
1Es, the sum digit is established in core lEs, the inter
opposite.
10
order carry is established in core 1Ks, and the digit
llt is noted from these illustrations that either output
originally in core liFs is re-established therein.
of 1a transfer `circuit is equally eñ'icient in providing the
Thus referring to period Rs of cycle P1, in the graph
inhibiting signal as long as the transfer circuit operating
of FIG. 13, the waveforms show that during this Rs
specifications «already mentioned are preserved. It is thus
period a digit 0 is read out of core lEs, a digit 1 is read
evident that a wide choice of selection of inhibiting sig
out of core 1Fs, and a digit 0 is read out of core lKs.
nals is permitted and a circuit for mechanizing a logical
As a result of reading these digits out, «the El', F1, and K1’
expression may -be arranged utilizing the most convenient
inhibiting outputs of transfer circuits 22, 23, and 24, re
selection of inhibiting signals.
spectively, are each high in potential, as shown, during
In general, the system of the present invention per
period Wc. The control cores of the registers, as shown
mits the mechanization of any Boolean equation. For
20
in FIG. 2, are so wound that, for this combination of
illustration, observation is directed to FIG. 14a, which
effective inhibiting signals, core '3Ec in the E register and
is the K register control logic circuitry. With specific
core -1Fc in the F register are not inhibited and therefore
reference to the mechanization of, for instance, the ks
are set into a l state during period Wc. Thus the read
equation given in FIG. 14:
ing of these control cores during period Rc results in the
El' F1, and K1’ inhibiting outputs of the respective trans
25
fer circuits being high in potential during period Ws.
The equation is seen to comprise the sum of three product
terms and may be logically manipulated to the equivalent
These effective inhibiting signals therefore function to set,
during period Ws, a 1 representative of the sum digit (2°)
expression :
in core lEs of the E register, to set a 1 which was read
out of core lfFs of the F register back into this core, and 30
ks=<Er+Fso'+~(ES'+KS'>'+<FS'+KS'>'
to leave core lKs in a O state representative of a 0 carry
digit.
Core 1Kc of FIG. 2, then, is seen yto mechanize the sum
The operation of the circuits during cycle P2, during
which the digit in core y2Fs is added to the digit in core
ZES, .taking into account the incoming carry digit in core
1Ks, can ‘be similarly followed in the graph of FIG. 13.
Thus, referring to the waveform for cycle P2 in the graph
of FIG. 13, the waveform-s indicate that during period Rs
(ESCI-FSU since the false outputs of the E and F register
35
transfer circuits 22 and 23 are inhibit wound in this core.
Similarly, core 2Kc mechanizes the sum (Es’-{-Ks’) and
core 3K0 mechanizes the sum (FS’+Ks’). The primes
of these sums 'are mechanized by the inhibit type of
winding in which cturents `act to cancel the effect of cur
of this cycle a digit 1 is read out of core ZES, a digit l
rents in the clock and digit selector signal windings 35
is read out of core 2Fs, and a digit 0 is read out of core 40 and 36, and the formation of the final sum is accom
lKs. As a result of reading these digits out, the E1, F1,
and K1' inhibiting outputs of transfer circuits 22, 23, and
24, respectively, are each high in potential, as shown,
during period Wc. The control cores of the registers,
plished by the common sense winding 49. Thus, consider
the transfer circuit output propositions which are effec
tive in the K register control cores during, `for instance,
period Wc of cycle P2 (FIG. 13). Here the inhibiting
as shown in FIG. 2, are so wound that, for this combina 45 output K1’ is shown to have a positive square wave cur
tion of effective inhibiting signals, core 1Fc and core 1Kc`
rent signal impressed thereon and the inhibiting outputs
are not inhibited and therefore are set into a 1 state.
E1’ and F1' are shown to have no current signals during
Thus the reading of these control cores during period Rc
results in the E1', F1, and K1 inhibiting outputs of the
period Wc. This one inhibiting signal waveform K1’ is
sufficient to prevent cores 2Kc and 3Kc from being
respective transfer circuits being high in potential during
period Ws. These effective inhibiting signals function to
50 ydriven into a true state by the P and Cc positive current
set a 0 representative of the sum digit (21) in core 2Es of
line is not wound about the 1K4` core, this core will be
driven to a true state. It follows that the input to the
waveforms.
However, since Ithe K1' inhibit-ing output
the E register, to set a 1 which was read out of core
2Fs of the F register back into this core, and to set core
K register transfer circuit during the following Rc period,
55
lKs into a l state representative of a carry digit.
which functions to cause output K1 thereof to be high,
The operation of the circuits for adding the higher
will be generated as a result of the switching of core 1K0
order digits can be »similarly explained by referring to
the waveforms of the graph in FIG. 13 for the P3 and P4
back to a zero state.
filled with “zeros”).
logic for the sign digit must be different lfrom the logic
for manipulating the `other digits. Additionally, if, for
It should be noted that all the func-tions of a digital
computer can be defined by Boolean equations in the
‘With reference to the restoration of the information 60 form of a series of sums of products. Thus the circuits
in the F register as exemplified by the circuit of FIG. 2,
of the present invention are capable of easily mechaniz
it should now be clear that the system of the present
ing the processes of a complex large-scale computer by
invention is -in no way limited to this type of operation.
merely inductively linking wires to a core corresponding
To illustrate, assume that it is desi-red that the F register
to all the complemented terms of a product and linking
be filled with “zeros” (cores IFS to 4Fs false) at the 65 a common sense line t0 `all the cores which are to be
completion of the addition. For this to be accomplished,
summed to form the function.
it is only necessary that the inhibiting signal F1' be per
Consider now the four binary digit serial storage por
mitted to affect only cores 1Fs to 4FS, control core 1Fc
tion comprising cores lEs to 4Es of the E register of
not being required at all. With this circuit arrangement,
FIG. 2, extracted and shown with control core logic in
regardless of the initial state of cores 1Fs to 4Fs, when 70 FIG. 15 as incorporated in a digital computer. With re
the addition is completed, these cores will be false (ie,
gard to utilization to perform an arithmetic process, the
cycles.
Further, since, in the binary number system, “ones”
complementing requires only the replacement of “ones”
instance, the same register is to perform the operations
with “zeros” and “zeros” with “ones,” the addend original 75 of recirculation, transfer, complementation, and count
3,040,986
15
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16
’
each having an initial direction of magnetization; a first
driving means for said controlled cores; a second driving
means for said controlling cores; means for simultaneously
supplying to said controlling cores various combinations
of data signals read from said controlled cores by said
ing, some means of program control is necessary. It
may be observed in FIG. 15 that a double diagonal 95
is employed to symbolize signal Cc being coupled twice
through cores IEC, ZEC, and SEC. This is to indicate that
a half-current flowing in two loops of conductor 35 (FIG.
2) about each of these cores will sufiice to switch these
first driving means, said data signals being capable of
cores. This is equivalent to coupling all timing digit sig
inhibiting said controlling cores from being switched to
the iopposite direction of magnetization by said second
nal (P) conductors 36 to the cores with the same polarity.
In construction, a core matrix may ybe arranged in either
driving means; and means for supplying to said controlled
cores control signals read from the controlling cores by
way when, in -accordance with its governing equation, a
core is to be factive during all digit transfer cycles making
up the computer word. Program control here takes the
form of program counter number outputs O, 1, 2, and
said second driving means, said control signals being cap
able of inhibiting said controlled cores from being switched
back to their original direction of magnetization by said
first driving means.
3 comprised of combinations of inhibiting propositions
4. ‘Circuitry for performing logical operations, com
N1', N1, N2', »and N2 which may be derived as the out
puts iof hip-flops or tr‘ansfer circuits associated with a
program counter. These propositions define which of
the above four operations is to be done, iand serve to
prising: a plurality of lbistable lmagnetic core arrays
grouped in pairs; a sense conductor coupled to each pair
of arrays; a first source of read and write signals for
switching cores of said ñrst array for each pair; a second
source of read and write signals for switching cores of
said second array for each pair; and an individual transfer
circuit connected to the sense conductor of each pair of
arrays, each said transfer circuit having a pair of outputs
select the circuitry for accomplishing them as listed in
the table of FIG. 16. Thus, in FIG. l5, when the logical
term NI’NZ' is effective, only core lEc is released for
switching. Since only the proposition El' is coupled to
core lE-c, it is seen that this core provides for the re
circulation oper‘ation. When the term N1N2’ is effec-tive,
coupled to the cores of its own array and other arrays in
it may be observed that core 2Ec operates to transfer 25 a predetermined arrangement.
information, digit by digit, into the E register from the
5. Circuitry for performing logical operations, com
F register. When the term Nl’Nz is effective, core SEC
prising: a plurality of bistable magnetic core arrays
provides for “ones” complementation of the informa
grouped in pairs; a sense conductor coupled to each pair
tion in the E register. It will be further observed that,
of arrays; a first source of read and write signals for driv
if the K register is devoted to the carry digit generated 30 ing cores of the first array of each pair, said write signals
«as the result of an arithmetic operation, and proposi
being separated from said read signals by an interval of
tion K1 is true at the beginning of cycle P2, then, after
time; a second source of write and read signals for driving
the sign digit which is understood to be stored in core
cores of the second array of each pair, the signals of said
lEs is recirculated unchanged by core dEc, cores SEC
second source successively occurring during the time inter
and l6Ec provide for the addition of one unit (under 35 val between the signals of said first source; and a separate
control of term NINZ) to the number stored in cores
transfer circuit connected to the sense conductor of each
ZES, SES, and 4Es; this, of course, is the operation of
pair of arrays, each said transfer circuit having a pair of
counting.
outputs coupled to the cores of its own array and other
arrays in a predetermined arrangement, said transfer cir
While the form of the invention shown «and described
herein is admirably adapted to fulfill the objects pri
marily stated, it is to be understood that it is not intended
to confine the invention to the one form or embodiment
40
cuit being triggered by the signals of said first source read
ing said first array of each pair to generate signals on the
outputs thereof for inhibiting cores of said second array
disclosed herein, for it is susceptible of embodiment in
from being written into by the signals of said second
various other forms.
source, and also being triggered by the signals of said sec
What is claimed is:
45 ond source reading said second array of each pair to gen
l. In a magnetic core system: a first and a second mag
netic core, each having substantially rectangular hysteresis
characteristics, each said core being capable of existing
erate signals on the outputs thereof for inhibiting cores of
said first array of each pair from being written into by the
signals of said first source.
in a true or Afalse state; driving means capable of supply
6. Circuitry for performing logical operations, com~
ing driving currents on successive periods for switching 50 prising: a plurality of bistable magnetic core arrays ar
said first core false, said second core true and then false
andsaid first core true; and transfer circuit means for gen
erating signals for inhibiting the switching of one of said
ranged in pairs; a sense conductor coupled to each pair of
arrays; a first source of periodic read and write square
Iwave signals for driving cores of said first array of each
cores true by said driving means dependent upon whether
pair, said write signals being separated from said read
or not the other of said cores has been switched false.
55 signals by an interval of time; a second source of periodic
2. A circuit for generating a logical process comprising:
read and write square wave signals for driving cores of
a first and a second controlled ybistable magnetic core; a
said second array yof each pair, the signals of said second
plurality of controlling bistable magnetic cores associated
source successively occurring during the time interval be
with each said controlled core, said controlling cores each
tween the signals of said first source; and a separate
having an initial direction `of magnetization; driving means 60 transfer means for each pair of arrays, said transfer means
for switching said cores; means for supplying to said con
trolling cores various combinations of data signals read
by said driving means from said controlled cores, said
data signals being capable of inhibiting said controlling
including a fiip~fiop circuit having a true and false trigger
input and a true and false output, one of the trigger in
puts being connected to the corresponding said sense con~
ductor and the other trigger input being connected to a
cores from being switched by said driving means to the 65 source of trigger signals occurring coincident with the
opposite direction of magnetization; and means for sup
write signals of said ñrst and second sources, said iiip-flo-p
plying to said controlled cores control signals read by
outputs coupled to the cores of its own array and other
said driving means from the controlling cores, said control
arrays in a predetermined arrangement, whereby said flip
signals being capable of inhibiting said controlled cores
flop is triggered to generate a signal on said false output
from being switched by driving means back to their orig 70 at the end of every write signal and is triggered to gener
inal direction of magnetization.
ate a signal on said true output during the following write
3. A circuit `for generating a logical process compris
signal period only if a signal has been read out of one of
ing: a first and a second controlled bistable magnetic core;
said arrays by the intervening read signal.
la plurality of controlling bistable magnetic cores associ
7. A magnetic switching circuit for generating a logical
ated with each said Controlled core, said controlling cores 75 function, comprising: a plurality of bistable magnetic
3,040,986’
17
cores, each having an initial direction ofA magnetization;
a sense line coupling all said cores; a plurality of inhibit
18
storage magnetic core and a plurality of control magnetic
cores each having substantially rectangular hysteresis
ing lines coupling different combinations of said cores;
characteristics, and each said core being capable of exist
drive lines coupling all of said cores; a source of drive
ing in a true or false state; driving means capable of se
current connected to said drive lines and capable of driv
ing said cores into the opposite direction of magnetization
during a first period and then back into the initial direc
tion of magnetization during a second period; and a source
of high or low signals connected to each of the inhibiting
quentially switching said storage core false during a first
period, said control cores true during a second period and
then false during a third period, and then said storage core
true during a fourth period; transfer circuit means having
an input coupled to said storage and control cores, and a
pair of outputs, one of which is coupled to said storage
lines, said drive currents being inhibited during the first
period of said drive source from changing the direction
of magnetization of any core through which a high signal
is sent on one of said inhibiting lines, and said drive cur
rents operating during the second period of said drive
source to drive any core back to its initial direction of
magnetization, thereby generating a signal on said sense
line indicative of the logical function.
8. Apparatus for solving logical operations, comprising:
core and both of which are connected to said control
cores, said transfer circuit means capable of being trig
gered true during said first period in accordance with
data read out of said storage core, said transfer circuit
means being operable during said second period for gen
erating signals on the outputs thereon capable of inhibiting
the switching of any control core coupled to its outputs;
other sources coupled to said control cores and capable of
a plurality of storage bistable magnetic cores for storing
supplying signals for inhibiting the switching thereof dur
data to be operated upon; a plurality of control bistable 20 ing said second period, said transfer circuit means capable
magnetic cores; a first circuit means for simultaneously
of being triggered during said third period in accordance
interrogating said plurality of storage cores to generate
with the data read out of all said control cores, and said
high or low output voltages corresponding to the data
transfer circuit means being operable during said fourth
stored therein; a second circuit means capable of setting
period for generating signals on an output thereof capable
said control cores dependent on combinations of the high 25 of inhibiting the switching of the storage core.
voltage output signals generated in said ñrst circuit means
l2. Apparatus for solving logical operations, compris
by interrogation of said storage cores; a third circuit
ing: a plurality of groups of storage cores for storing data
means for simultaneously interrogating said control cores
to be operated upon; a plurality of groups of control cores,
to generate high or low output voltages corresponding
each associated with one of the groups of storage cores;
to the data stored therein; and a fourth circuit means
individual transfer means associated with corresponding
capable of setting each of said storage cores dependent
groups of storage and control cores, said transfer means
on the output signals generated in said third circuit means
having inputs from its own group of storage and control
by interrogation of said control cores.
cores and outputs connected in various combinations to
9. Circuitry for generating a signal corresponding to
storage and control cores of all groups; driving means
a logical function comprised of a plurality of terms, each
capable of setting said storage and control cores, said
said function defined as the logical sum of a plurality of
driving means being operable to simultaneously interro
logical products, comprising: a bistable magnetic ele
gate a selected core of each group of storage cores and
ment for each logical product of the function; a source of
to trigger its associated transfer means to provide high
and low voltages on the outputs thereof corresponding to
state of said magnetic elements; means to supply a signal 40 the data stored therein, further operable to set each of said
corresponding to the complement of each term appearing
control cores dependent on signals generated on the out
in the function; said latter means coupled to the respec
puts of said transfer means, further operable to then
tive magnetic element such that the signal supplied there
simultaneously interrogato all the cores of each group of
write and read driving signals capable of switching the
by can induce a field therein in opposition to said write
control cores and to trigger its associated transfer means
driving signal; and means including a conductor cou 45 to provide high and low voltages on the outputs thereof
pled to all of the magnetic elements for sensing the value
of the function as a change in state of a core caused by a
read driving signal.
corresponding to the data stored in each group, and also
operable to then set the selected core of each group of
storage cores dependent on the signals generated on the
outputs of its associated transfer means.
l0. Circuitry for mechanizing a digital function de
fined by a logical sum of a plurality of logical products 50
13. A circuit for logically manipulating data, compris
comprising: a plurality of storage magnetic cores capable
ing: a ñrst, second, and third register, each including a
of stability in either a true or false state, each of said
plurality of bistable magnetic elements; means to arrange
cores representing one of the terms of said function; a
iirst current pulse source capable of switching said stor
age cores from the true to false state to read a signal
a first array comprising one or a plurality of the elements
of each said register as storage for digit signals and a
second array comprising one or a plurality of the ele
ments of each said register as a control for said storage
array; a source of read-write driving signals for said
storage and control cores; and a data transfer circuit for
stored therein; a plurality of control magnetic cores
capable of stability in either a true or false state, one of
said control cores for each logical product in the func
tion; a transfer circuit associated with each said storage
each said register, each said transfer circuit functioning to
core for generating signals representing the term read 60 supply inhibiting signals coincident with the write driving
therefrom by said iirst current pulse source, said tansfer
signal in one of said arrays in accordance with data sig
circuits each having a pair of output lines, said output
nals read out of the other of said arrays.
lines corresponding to the complement of the individual
14. A data processing circuit comprising: a first, sec
terms of one of the logical products being coupled to
on, and third register, each having a plurality of mag
each said control core; a second current pulse source
capable of switching each said control core from the
false to the true state if not inhibited by signals from
said transfer circuits; readout means responsive to the
netic elements with substantially rectangular hysteresis
characteristics and two corresponding states of remanent
magnetization, each of said registers also having a trans
fer circuit capable of generating signals on outputs there
from dependent on data read out of said elements; means
change of state of any one of said control cores from the
true state back to the false state for generating a signal 70 to arrange the elements of each said register to form a
representing the function; and a third current pulse source
pair of corresponding arrays in each register; a first driv
capable of switching said control cores from the true
ing means for supplying signals capable of changing the
state back to the false state, to thereby generate the sig
state of magnetization of the elements of one array of
nal on said readout means representative of the function.
each register; a second driving means for supplying sig
l1. A magnetic core register circuit, comprising: a 75 nals capable of changing the state of magnetization of
3,040,986
2v@
the elements of the other array of each register; means
for sensing any changes in states produced in the ele
ments of each of the arrays of said registers by said first
state dependent upon whether or not the other of said
elements has been switched to the second state.
and second driving means to generate signals for trigger
ing said transfer circuits; and means responsive to the
output signals generated by said transfer circuits and in
prising: a plurality of bistable state element arrays ar
ranged in pairs; individual sensing means to sense a change
in state of an element of each pair of arrays; a first source
ductively coupled to the elements of the arrays of the
of read and write signals for switching elements of one
registers in a predetermined arrangement so as to be able
array of each pair; a second source of read and Write
19. Circuitry for performing logical operations, com
to inhibit the changing of state of magnetization of the
elements by said first or second driving means.
15. A circuit for logically manipulating data com
signals for switching elements of the other array of each
pair; an individual transfer circuit for each pair of arrays,
each said transfer circuit being responsive to its asso
prising: a first, second, and third register, each compris
ciated sensing means to generate signals on its output;
ing a plurality of bistable magnetic elements; means to
and means to couple the output of said transfer circuit
arrange a first array of one or a plurality of the elements
to its own pair of arrays and to other pairs of arrays in
of each said register as storage for digits and a second 15 an arrangement determined by the logical operations to
be performed.
array of one or a plurality of the elements of each said
register as control for said storage elements; a four
20. A circuit for generating a logical process compris
period timing signal generator providing pulses for read
ing: a nrst and a second controlled bistable magnetic
ing a storage element of each register during a first
core; at least one controlling bistable magnetic core as
period, of writing into the control elements during a sec 20 sociated with each said controlled core, said controlling
ond period, of reading the control elements during a third
cores each having an initial direction of magnetization;
period, and of writing into the storage element of each
a `first means for switching said controlled cores to said
said register during a fourth period; and a data delay
initial direction of magnetization; a second means for
transfer circuit for each said register operative to sup
switching said controlling cores to the opposite direc
ply pulses for inhibiting the pulses of said timing signal
tion of magnetization; means for inhibiting said control
`generator from writing in one of said arrays during the
ling cores from being switched by said second means to
second and fourth periods in accordance with data read
said opposite direction of magnetization in accordance
out of the other of said arrays during the first and third
with signals read out of said controlled cores by said first
periods, respectively.
means; a third means for switching said controlling cores
16. A circuit for logically manipulating data compris 30 to said initial direction of magnetization; a fourth means
ing: a first, second, and third register, each comprising a
for switching said controlled cores to said opposite di
plurality of magnetic cores; means to arrange a first ar
rection of magnetization; and means for inhibiting said
ray of one or a plurality of the cores of each said reg
ister as_storage for digits and a second array of one or a
controlled cores from being switched by said fourth means
to said opposite direction of magnetization in accordance
with signals read out of said controlling cores by said
plurality of the cores of each said register as control for
third means.
said storage cores; a four-period timing signal generator
providing pulses for reading a storage core of each reg
2l. Circuitry for performing logical operations, corn
ister during a first period, of Writing into the control
prising: a plurality of bistable magnetic core switch ar
cores during a second period, of reading the control cores
rays; a common output means for each pair of arrays; a
during a third period, and of writing into the storage cores 40 source of timing signals; an individual gate having one
of each said register during a fourth period; and a data
input connected to the output means for each pair of
delay transfer circuit for each said register controlled
arrays, each said gate having a control input connected
to generate a first inhibiting signal during a Write pe
to the source of timing signals; a first source of periodic
currents synchronized with `said timing signals and capa
successfully read, and a second inhibiting signal during a 45 ble of switching the cores of one array in each pair; a
second source of periodic currents synchronized with said'
write period as a result of at least one core- of its reg
timing signals and capable of switching the cores of the
ister being successfully read.
17. A circuit for generating a logical process compris
other array in each pair; an individual flip-flop circuit for
each pair of arrays, each said fiip-fiop circuit having a
ing: a first and second controlled bistable magnetic core;
a plurality of controlling magnetic cores associated with 50 pair of outputs and having one trigger input thereto con
nected to the output of its associated gate and the other
each said controlled core, said controlling cores each
riod as a result of none of the cores of its register being
trigger input thereto connected directly to said timing
having an initial direction of magnetization; a first driv
signal source; and means inductively coupling the outputs
ing means for said controlled cores; a second driving
from said fiip-fiop circuits to the cores of the arrays in
means for said controlling cores; means for supplying to
said controlling cores various combinations of data sig 55 accordance with the logical operations to be performed,
whereby data sensed by switching the cores of one array
nals as simultaneously read from said controlled cores by
in each pair by one of said sources of periodic currents
said first driving means, said data signals being capable
is set up in its respective ffip-ñop circuit, such that the
of affecting the switching of said controlling cores to the
outputs thereof serve to selectively inhibit the switching
opposite direction of magnetization by said second driv
ing means; and means for supplying to said controlled 60 of cores in the other array in each pair by the other
source of periodic currents.
cores control signals read from said controlling cores by
22. A generator of a signal representing a logical func
said second driving means, said control signals -being ca
tion,
comprising: first and second pluralities of bistable
pable of affecting the switching of said controlled cores
magnetic cores, each having a substantially rectangular
back to their original direction of magnetization by said
65 hysteresis loop; first and second means to apply magneto
ñrst driving means.
motive driving currents to switch said cores; a timing sig
18. Circuitry for performing logical operations, com
nal combining with the application of the driving currents
prising: a controlled element and a controlling element
to said cores to effect sequential periods of application of
each capable of existing in a first or a second stable
drive to the first condition of saturation to said first plu
state; means capable of switching, on successive periods, 70 rality of cores, to the second condition of saturation to
said controlled element to the second state, said control
said second plurality of cores, and then to the first condi
ling element to the first state, said controlling element
tion of saturation to said second plurality of cores; a cir
to the second state and said controlled element to the
cuit means for each core in said first plurality of cores
first state; and circuit means for generating signals in
having a first output effective on change in state of its
hibiting the switching of one of said elements to the first 75 respective core during the period when said first means
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