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Патент USA US3047749

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July 31, 1962
H. A. R. DE MIRANDA
3,047,739
SHIFT REGISTER UTILIZING FREE CHARGE CARRIER
STORAGE OF‘ CASCADED DELAY NETWORK
COUPLED TRANSISTORS
.1
Filed June 12, 1958
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INVENTOR
HEINE ANDRIES RODRIGUES DE MIRANDA
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etched transistors, which act as electric storage elements,
and employs two sources of clock-pulses set off in time
with respect to one another, said sources delivering the
so-called control pulses. ‘In this circuit arrangement, in
formation registered in the form of free charges in the
3,047,739
SHIFT REGISTER UTILIZIING FREE CHARGE
CARRIER STORAGE 0F CASCADED DELAY
NETWORK COUPLED TRAN§EST©RS
Heine Andries Rodrignes de Miranda, Moiienhutseweg,
Nijmegen, Netherlands, assignor to North American
Phiiips Company, Inc, New York, N.Y., a corpora
‘base-Zone of a first transistor, is shifted to a next transistor
at each clock-pulse, so that two transistors are required
to store the information during the time interval between
two successive clock-pulses from one of the sources.
tion of Delaware
The present invention relates to circuit arrangements
comprising junction transistors of the so-called “deep
etched” type according to patent application Serial No.
Patented July 31, 1962
2
1
Filed Zinne 12, 1.958, Ser. No. 741,497
Claims priority, application Netherlands June 13, 1957
13 Ciaims. ((11. 3®7—88.5)
thee
10
The circuit arrangement according to the present in
vention takes advantage of the fact that, at a voltage equal
to or exceeding the so-called cut-off value of the collector
base voltage, not only the collector-current, but also the
base-current corresponding to a given forward base
679,288, ?led August 20, 1957, acting ‘as electric storage 15 emitter voltage is greatly reduced. This circuit arrange
It concerns in particular an improvement of a
ment comprises a series of at least two “deep-etched”
circuit arrangement described and shown in said applica
tion.
The patent application Serial No. 679,288 concerns
junction transistors comprising a body, in which a con
tact-comprising semi-conductive part of a given con~
junction transistors, the emitter of each transistor of the
series being connected to a point of constant potential
through a load impedance. It has the feature that the
base of a next transistor or" the series is coupled to the
emitter of the preceding transistor through a delaying
network, while the collectors of all the transistors are
simultaneously supplied from the same source of voltage
elements.
ductivity type, termed the base, is separated by closely
opposite junctions from at least two contact-comprising
semi-conductive parts of opposite conductivity type,
termed the emitter-zone and the collector zone respective
ly. The junction transistor according to this patent ap
plication has the feature that, issuing from a boundary
surface of the body adjacent the emitter-contact, a non
conductive part penetrates into the base, which part locally
pulses so that, as a result of a current pulse produced
25 during a voltage pulse through the load impedance of a
preceding transistor of the series, electrical energy is
stored in the corresponding delaying network, which
energy produces a considerable number of free charge
carriers in the base-zone of the next transistor of the series
narrows the current path from the emitter-contact to the 30 only after termination of this voltage pulse.
In order that the invention may be readily carried into
base-contact and approaches the collector to a distance
eifect, one embodiment thereof will now be described in
smaller than the minimum distance from the emitter to
the collector; the arrangement results in the production
of a negative di?erential resistance in the characteristic
detail, ‘by way of example with reference to the ac
companying drawing, in which
FIG. 1 is a schematic sectional view of one embodi
representing the relationship of the collector-current and 35
ment of a “deep-etched” junction transistor, and shows a
of the voltage diiference in the blocking direction between
suggested symbol for a transistor of this type.
the collector-contact and the base-contact at a constant
FIG. 2 shows a group of base- and collector current
voltage difference in the forward ‘direction between the
collector emitter voltage characteristics of a transistor of
emitter-contact and the base-‘contact.
In the hitherto most currently employed embodiment 40 the type represented in FIG. 1, with the emitter-base
voltage as a parameter.
of this transistor, the non-conductive part is constituted by
FIG. 3 shows the wiring diagram of one embodiment
an incision usually obtained by subjecting the assembly,
of the circuit arrangement according to the invention, and
after providing at least the emitter-zone and the emitter
FIG. 4 shows current- and voltage-time diagrams for
contact on the base, to an electrolytic etching treatment
with the use of an etchant forming a low-ohmic transition 45 explaining the operation of this embodiment.
As shown in FIG. 1, a “deep-etched" junction transistor
with the material of the emitter-zone and a high~ohmic
is made up of a plate 1 of semi-conductive material such
transition with the material of the base-zone, the emitter
as germanium or silicon, for example of n-type carrying a
contact being used as an electrode, and a part of the
emitter-zone and a contiguous layer of the base being
base electrode 2 which is conductive in both directions,
etched away, whence the term “deep-etched” junction 50 an emitter 3 and a collector 4 being formed by alloying
transistor.
the material of the plate. Consequently, both the emit
ter 3 and the collector 4 are Zones of a material of op
A circuit arrangement described in the prior patent ap
posite conductivity type, for example p-type. Each of
plication comprises at least one “deep-etched” junction
these zones has connected to it an electrode 5 and 6 re
transistor, in which such a high voltage difference occurs
temporarily across the collector-depletion layer, that the 55 spectively, for example by soldering. From the bound
current path from the emitter to the base-contact is at
ary surface of the plate adjacent the emitter-contact, a
least partially cut o?. This cut-off occurs at a given so
non-conductive part 7 penetrates into the base. This non
conductive part is an incision extending about the emit
called “cut-off” value of the voltage applied between the
ter-contact and formed by etching. As a result the cur
collector-electrode and the base-electrode. In the embodi
ment of said circuit arrangement speci?cally described 60 rent path from the emitter to the base contact is locally
in the prior application, at least one “deep-etched” junc
narrowed, because the non-conductive part '7 approaches
tion transistor functions as an electric storage element, its
collector supply voltage being a control pulse, the ampli
the collector to a distance shorter than the minimum dis
tance between the emitter and the collector. The base
contact 2 is consequently separated from the emitter by
tude of which exceeds its collector-base cut-off voltage,
so that its active base-Zone is at a ?oating potential during 65 the non-conductive part 7 on the one hand and by the
this control pulse. An erase pulse following the control
collector 4 on the other hand, which is indicated by the
symbol shown in FIG. 1.
pulse and having an amplitude smaller than the cutcif
voltage is used to consume any free charges in the base
FIG. 2 shows the collector-current Ia and the base
zone and may be combined together with the control pulse
current lb of a transistor shown in FIG. 1 as a function of
70 the collector-emitter voltage Vce. Above a given value
to form a stepped or saw-tooth pulse.
The aforesaid embodiment described and shown in the
of the collector-emitter voltage both the collector-cur
prior patent application comprises a cascade of deep
rent and the base-curent decrease with increasing voltage.
3,047,739
3
4
Hence, the transistor has an output characteristic with
a negative resistance part and, above a so-called “cut
o? value” of the collector-emitter voltage both the base
through resistor 14, as the case may be, the base-zone
of this transistor consequently receiving a charge VbZll
of free charge carriers, as shown in the sixth line of FIG.
4. Owing to the time constant of the delaying network
12, 13 the charge of the base-zone of the transistor 29
during the ?rst clock-pulse is as yet insuf?cient to produce
current and the ‘collector-current are comparatively low.
This permits a delaying network to be connected between
two successive transistors of a series of transistor and
electric energy to be stored in this network as long as a
voltage is applied between the collector- and the emitter
elcctrodes of the transistors.
One form of the circuit arrangement according to the
invention is shown in FIG. 3. This form comprises a
series of four cascade-connected “deep-etched” transistors
19, 20, 3d and (it) the collectors of which are supplied
through a diode 19 with negative clock-pulses from a
source 13. The emitter ‘of each transistor is grounded
through load resistors 11, 21 and so on respectively and
is coupled to the base of the next transistor through a
delay network made up of series-resistors 12‘, 22 and so
on respectively and parallel-capacitors 13, 23 and so on
respectively. The emitter of the last transistor 46 is con
nected to the output terminals 17 of the circuit arrange
ment, while the base of the ?rst transistor 14} is connected
to a source 16 of negative input pulses. If need be, de
a noticeable ‘current pulse through its emitter-collector
circuit. As a result of the capacitor'13 discharging into
the base-zone of the transistor 20, the number of free
charge carriers in this Zone during the next clock-pulse
has, however, become such that the second clock-pulse
produces a comparatively strong current pulse IeZt)
through the emitter-collector circuit of the transistor 24),
as shown in the last line of FIG. 4.
Similarly as the third and fourth lines of FIG. 4,77the
last three lines of this ?gure also show in dash lines the
variation of the several currents and voltages when using
step clock pulses.
The emitter-current of each tran
sistor subsists during the second pant of the corresponding
clock-pulse but decreases gradually due to the base-Zone
of this transistor becoming discharged.
The discharge of the base-zones of the various tran
sistors between the clock-pulses Vc by a forward leakage
current of the corresponding base-collector-diodes is pre
pending upon the repetition frequency of the clock-pulses,
low-ohmic resistors 14 and so on may be connected in the 25 vented by the recti?er 19.
The sharp peaks of the emitter-current pulses are
base-connections of the transistors 20, 30 and 4%, while
strongly damped by the emitter-capacity of the corre
parallel capacitors 15 and so on of small value may be
sponding transistor, so that the form represented in the
connected in parallel with the load resistors 11 and so on
fourth and last lines of FIG. 4 does not correspond to
depending upon the Width of these pulses.
reality. Yet it may happen, for example in the case
FIG. 4 illustrates the operation of the circuit arrange
of comparatively long clock-pulses that the emitter
ment shown in FIG. 3. The ?rst line represents the
current pulses actually have two comparatively sharp
clock~pulses Vc, which may if desired, be stepped pulses
peaks. This may be undesirable and is avoided by means
or saw-tooth pulses, as indicated in dash-lines and in dot
of a small capacitor 15, 25, and so on, which capacitor
and-dash lines respectively. The second line of FIG. 4
shows an input pulse Ibltl which is supplied from the 35 increases the natural emitter-capacity of the correspond
ing transistors 10, 2t} and so on. The time constant
source 16 to the base of the transistor 19. When this
of the load circuit made up of the resistors 11, 21 and
pulse arrives, there is no voltage in the emitter-collector
circuit of the transistor 19, so that no current passes
so on and the parallel-capacitors 15, 25 and so on, which
at least partly consist of the natural emitter-capacity of
free charge carriers in the base-zone of the transistor 10. 40 the transistor 10, 20 and so on, should be of the order
of the duration of the cloclepulses.
This charge V1119 of the base-Zone, however, cannot leak
The capacitors '13‘, 23 and so on should be capable
away and subsists till the arrival of the next clock-pulse
of becoming rapidly charged by way of the resistors 12,
Vc, as shown in the third line of FIG. 4. 'This clock
22 and so ‘on and of becoming comparatively slowly dis
pulse has a steep leading edge and an amplitude exceeding
charged through resistors 11 and 21, 21 and 22, ‘and so
or equal to the “cuto?c value” of the collector-emitter
on. Hence, the value of resistors 12, 22 and so on should
voltage of the transistors 1% to 4d. Owing to the pres
be much lower than that of the load resistors 11, 21 and
ence of free charge carriers in the base of the transistor
so on. On the other hand, the delay with which the
1d, the clock-pulse Vc produces a current pulse Ieltl
base-zone of the next transistor 20, 3t) and so on becomes
through its emitter-collector circuit. After an initial
high current peak, this current pulse is very rapidly 50 charged should exceed the width of the clock-pulses,
since otherwise the input pulse applied to the base of
limited to the so-called “cut-off value,” and the free charge
the transistor 10 by the ?rst ‘clock-pulse is transmitted
carriers in the base-zone are only temporarily allowed to
even beyond the base of the last transistor 46. The time
leak away to a small extent. At the end of the clock
constant of the circuit made up of the natural capacity
pulse, the collector-emitter voltage decreases abruptly,
through this circuit and the input pulse can only produce
amplitude is produced, accompanied by a partial dis
of the base of the transistors 20, Sill and so on of the
series-resistors 14, '24 and so on connected between this
charge of the base-Zone of the transistor lltl“. Subse
quently, this base-zone becomes discharged more or less
so on and ‘of the capacitors 13, 23 and so on should
rapidly, dependent upon the form of the clock-pulses.
If, for example, the trailing edges of the clock-pulses
Normally, the resistors 14, 24 and so on are constituted
so that a second short emitter-current pulse of greater
base and the common point of the resistors 12, 22 and
consequently likewise exceed the width of the clock-pulse.
‘by the natural resistance ‘of the base-electrode of the
transistors 20!, 3d and so on. If, however, this natural
resistance is too low, it can ‘be increased by a separate
the end of the clock-pulses, subsequent to which it be
resistor, as shown in FIG. 3. Finally, the discharge time
comes slowly further discharged. If the clock-pulse is
followed by a stepped erase pulse haivng an amplitude 65 constant of the delaying network should exceed the time
interval between two successive clock-pulses. In the cir
smaller than the “cut-off value" of the collector-emitter
cuit arrangement shown in FIG. 3, this means that the
voltage, as indicated in dash-lines in the ?rst line of FIG.
time constant equal to the product of the capacity of
4, the base-Zone is allowed to discharge completely dur
the capacitors 13, 23 and so on and the sum of the
ing said erase pulse, as indicated in dash lines in the
third and fourth lines of FIG. 4.
resistors 11 and 12, 21 and 22 ‘and so on should exceed
The capactor 13 becomes charged to a voltage Vc13
the time interval between the clock-pulse.
via the resistor 12 by the current pulse through the resis
The circuit arrangement shown in FIG. 3 constitutes
a shift register so that input pulses are transmitted or
tor 11, as shown in the ?fth line of FIG. 4. After the
clock-pulse, this capacitor slowly discharges through re
shifted one step at each pulse of a series of clock-pulses.
sistors 11 and 12 and into the base-zone of transistor 29 75 In this case, the combination of each delay network and
are slightly less steep than their leading edges, the base
Zone becomes comparatively rapidly discharged during
3,047,739
5
6
the next transistor constitutes a storage unit in which a
element being such that the charge in the base-zone of
each transistor is prevented from being discharged be
tween each of said voltage pulses by a forward base
collector leakage current.
pulse or a charge condition of the base-zone of the pre~
ceding transistor is stored during the time interval be
tween two successive clock-pulses. The circuit arrange
ment as described conseguently has the advanatge that
only one transistor is used to store a given information
dur
a clock-pulse interval and consequently only one
series of clock-pulses need be supplied to the circuit.
What is claimed is:
1. A circuit arrangement comprising a plurality of
transistors connected in cascade and acting as memory
elements, each transistor having emitter, base and col
8. A circuit arrangement as claimed in claim 5, further
comprising a rectifying element connected in series with
said source of voltage pulses in the common supply for
the transistor collectors, the polarity of said rectifying
element being such that the charge in the base-zone of
each transistor is prevented from being discharged be
tween each of said voltage pulses by a forward base
collector leakage current.
9. A circuit arrangement as claimed in claim 5, where
in the value of said series resistors is low relative to
the value of said ‘load impedance, whereby the charging
time of said capacitor through said series resistor is short
relative to the duration of said voltage pulses and its
discharge time through the series resistor and load im
pedance is long relative to the repetition frequency of
lector electrodes and exhibiting a collector cut-oil volt
age at which the current path from tie emitter to the
base electrode is at ‘least partially cut oif and each having
‘a load impedance ‘associated therewith, the emitter of
each transistor being connected to a point of constant po
tential through its associated load impedance, a circuit
connection comprising a delay network between the
base of each transistor and the emitter of the preceding 20 said voltage pulses.
transistor, 2. source of voltage pulses connected to and
10. A circuit arrangement as claimed in claim 9, said
simultaneously supplying the collector electrodes of all
delay network being connected to the base of the succeed
the transistors with voltage pulses having an amplitude
greater than said collector cut-off voltage, whereby elec
trical energy is stored in a corresponding delay network
upon the production of a voltage pulse through the load
impedance of a transistor, said electrical energy produc
ing a substantial number of free charge carriers in the
base-zone or
succeeding transistor after termination
of said voltage pulse.
2. A circuit arrangement ‘as claimed in claim 1, further
comprising ‘a rectifying element connected in series with
said source of voltage pulses in the common supply for
the transistor collectors, the polarity of said rectifying
element being such that the charge in the base-zone of
each transistor is prevented from being discharged be
ing transistor through a connecting resistor, said con
necting resistor having ‘a value such that the charging
time of the base is long relative to the duration of the
voltage pulses and short relative to the repetition fre
quency of the voltage pulses.
11. A circuit arrangement as claimed in claim 10, fur
ther comprising a rectifying element connected in series
with said source of voltage pulses in the common sup
ply for the transistor collectors, the polarity of said
rectifying element being such that the charge in the
base-zone of each transistor is prevented from being
discharged between each of said voltage pulses by a for
ward base-collector leakage current.
12. A circuit arrangement as claimed in claim 9, fur
ther comprising a rectifying element connected in series
tween each of said voltage pulses by a forward base
collector leakage current.
with said source of voltage pulses in the common sup
3. A circuit arrangement as claimed in claim 1, said
ply for the transistor collectors, the polarity of said
delay network being connected to the base of the suc 40 rectif ‘.ng element being such that the charge in the base
ceeding transistor through a connecting resistor, said
zone of each transistor is prevented from being dis
connecting resistor having a value such that the charg
charged between each of said voltage pulses by a for
ing time of the base is long relative to the duration of
ward base-collector leakage current.
the voltage pulses and short relative to the repetition
17. A circuit arrangement comprising a plurality of
PP Or deep etched transistors connected in cascade and acting
frequency of the voltage pulses.
4. A circuit arrangement as claimed in claim 3, further
as memory elements each transistor having emitter, base
comprising a rectifying element connected in series with
and collector electrodes and exhibiting a collector cut
said source of voltage pulses in the common supply for
oil voltage at which the current path from the emitter
the transistor collectors, the polarity of said rectifying
to the base electrode is :at least partially cut off and each
element being such that the charge in the base-zone of
having a ‘load impedance ‘associated therewith, the emit
each transistor is prevented from being discharged be
ter of each transistor being connected to a point of con
tween each of said voltage pulses by a forward base
collector leakage current.
5. A circuit arrangement as claimed in claim 1, where
in said delay network comprises a series resistor and a
capacitor, said series resistor connecting in series the
emitter electrode of the preceding transistor to the base
stant potential through its associated load impedance, a
circuit connection comprising ‘a delay network between
electrode of the succeeding transistor, ‘and said capacitor
connecting said base electrode to a point of constant
potential.
6. A circuit arrangement as claimed in claim 5, said
delay network being connected to the base of the succeed
ing transistor through ‘a connecting resistor, said con
necting resistor having a value such that the charging
time of the base is long relative to the duration of the
voltage pulses and short relative to the repetition fre
quency of the voltage pulses.
7. A circuit arrangement as ‘claimed in claim 6, further
comprising a rectifying element connected in series with
said source of voltage pulses in the common supply for
the transistor collectors, the polarity of said rectifying
the base of each transistor and the emitter of the pre
ceding transistor, a source of voltage pulses connected
to and simultaneously supplying the collector electrodes
of all the transistors with voltage pulses having an am
plitude greater than said collector cut-off voltage where
by electrical energy is stored in ‘a corresponding delay
network upon the production of a voltage pulse through
the load impedance of a transistor, said electrical energy
producing a substantial number of free charge carriers in
the base-zone of the succeeding transistor after termina
tion of said voltage pulse.
References Cited in the ?le of this patent
UNITED STATES PATENTS
2,877,357
Pearshall et a1 _________ __ Mar. 10, 1959
763,734
Great Britain ________ __ Dec. 19, 1956
FOREIGN PATENTS
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