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Патент USA US3047864

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July 31, 1962
M. J. COLEMAN
3,047,854
ELECTRICAL DECODER
Filed Dec. 30, 1958
DIGITAL T0
DIGITAL
SHAFT
ANALOG
1‘
SERVO
ERROR
\42
SERVO MOTOR
45
INPUT
2
/
44
DIGITIZER
45
_
FIXED AC
REFERENCE VOLTAGE
15/1,“;
D3\
50
j‘<1—
-?23
2:
22
0;
D2
20
27
,0:
26
04
24
:5
I4
_
T
T
>
T25
e,
+00
FIG.|
l
0
A
1
_,,
o
l‘
o
l2
|
SIGN __,0
LO BINARY INPUT
*3 INFORMATION
INVENTOR.
mum/2 J. 0025mm
vBY
ATTORNEY
Unite States
atent v- _
3,047,854
CC
Patented July 31, 1962
1
2
FIG.‘ 1 shows an electrical schematic of the teachings
of the present invention applied to the conversion of
3,047,854
ELECTRICAL DECODER
Millard J. Coleman, Vestal, N.Y., assignor tolnterna
tional Business Machines Corporation, New York,
binary electrical information having two orders of binary
signi?cance; and
Filed Dec. 30, 1958, Ser. No. 783,845
3 Claims. (Cl. 340-647)
ventional digital servo system having a digital-to-analog
conversion stage in which the electrical schematic of
N.Y., a corporation of New York
FIG. 2 shows an electricalv block diagram of a con
FIG. 1 may be utilized.
The present invention generally relates to an electrical
decoder and in particular it relates to a new and improved
means for converting binary electricalinformation to an
>Referring to FIG. 1, there are shownthree switching
devices comprising, by way of illustration, conventional
electrical latch circuits forv storing the binary electrical
A.C. analog electrical voltage.
information to be converted. - Speci?cally, latch. 10 may
In the ?eld of electronic digital computers, the out
be utilized to store the sign, latch 11 may be utilized to
put information from the digital computer must usually
store the ?rst order of signi?acnce and latch 12 may be
be converted into an analog quantity before it may be 15 utilized to, store the second, order of signi?cance of the
utilized as readout information or‘function as a control
binary electrical information to be converted.
quantity. Means for converting electrical binary infor
‘Considering negative logic, latches ‘11 and 12 may be
mation to electricalanalog information areknown in the
designed to have, an up voltage level at their 1 output
art, and two generalizedapproaches are utilized for that
and a down voltage level at vtheir‘O output ter
purpose. One of these. approaches is broadly categorized 20- terminal
minal while in a reset condition corresponding to a binary
as voltage summingand the other is known broadly as
“0” in their input. Similarly, latches 11 and 12 may be
current summing. ,Each of these approaches has ad
designed to‘ have a down'voltage level at their 1 output
vantages when used in particular environments. ‘How
terminal and‘ an, up voltage level at their ‘0 output ter
ever, when it- is desired. that the. analog output be in the
while in a set condition corresponding to a binary
form of an A.C.,voltage. havingan amplitude equal to 25 minal
“1” in their input. The'l outputpterminal of latches
the magnitude of the analog and a phase which is indica—
11 and 12are shown connected to diodes ‘D1 and D2, re
tive of the sign of the analog, -these..above-identi?ed
spectively, through resistances_13 and 114, respectively,
generalized approaches become undesirable because of
in order to alter the A.C.. empedance of the variable
the degree of circuit, complication that is necessary.
.A.C.»attenuat0r
to be described hereinafter, in'accord
Accordingly, the present-invention describes a means
ance with the condition of these latches corresponding to
for taking a ?xed A.C. voltage sourceand applying this
their binary electrical‘ input information. Furthermore,
voltage through a variable A.C.. voltage attenuator which
the
0 output terminals of latches 11 and 12 areshown
attenuates the A.C.,voltage ‘of. the, source by an amount
connected to diodes D5 and D6, respectively, so as to
which is dependentupon the condition of electronic D.C.
provide means for assuring that no'A.C. analog voltage
switching circuitry which is in turn. determined by the
electrical binary information ,to be converted. The vari~
able A.C. voltage attenuator may consist of an A.C.
35 exists when both latches are receiving a binary “0*” cor
responding to a decimal one.
Referring again to FIG. 1, a ?xed A.C. reference volt
voltage divider‘ having a??xed impedance portion and a
age is applied to terminal 15 and adi-rect current isola
tion
means comprising capacitor 16 and resistance 17
at the junction at which it is desired to derive the analog 40 connected
to ground. This speci?c type of direct cur
A.C. voltage. ‘ Moreover, the variable impedance portion
rent‘isolation means forms no part of the present inven
may comprise a variable, number of plural parallel im
tion as it might alternately have comprised a transformer
pedance. paths, as determined by the condition of the
with one of the terminals of the secondary connected to
aforementioned switching circuitry.
selectively variable impedance portion serially connected
It is, therefore, a_ primary object of the present inven
tion to provide a new and improved means for converting
binary electrical information to an A.C. analog electrical
voltage.
ground.
45
‘
According to the present invention, this A.C. refer
ence voltage may then rbe applied to a variable A.C.
voltage attenuator consisting of an ‘A.C. voltage divider
having a ?xed impedance portion shown as resistance 18
and a- selectively variable impedance portion shown in
,IIt is an additional object of the present invention to
provide a new and improved means for converting binary 50
cluding the two parallel impedance paths containing D1
electrical information to an A.C. electrical analog volt
and D2~and the inputimpedance of transistor Q1. As
age having an amplitude equal to the magnitude of the
analog and a phase which is determined by the sign of
the analog.
will more fully ‘be described hereinafter, transistor Q1
is being utilized to providea phase ‘change in accordance
withbinary sign input information.
It is another object of the present invention to provide 55
his the A.C. voltage amplitude at junction 19 between
a new and improved means for converting binary elec
the ?xed and variable portions which is controlled by the
trical information to an A.C. analog electrical voltage
latches 11 and 12 through D1 and D2 in accordance with
utilizing a variable A.C. voltage attenuator having an
binary electrical input information. In order to assure
attenuation which is dependent upon the binary electrical
that junction 19, is at a positive voltage level, (it is con
information to be converted.
a
60 nected,ias. shown to a +D.‘C. supply voltage through re
‘It is still another object ofthe present invention to
s1stance'20which forms part of the variable A.C. im
provide ‘a new and improved means for converting binary
pedance portion. ‘The part of the variable A.C. imped—
electrical information to an A.C. analog electrical volt
age which comprises an‘A.C. reference voltage applied
to an A.C. voltage divider having a ?xed and variable im
pedance portion.
.
_
7
Other objects of the invention will be pointed out in the
following description and claims and illustrated in the
accompanying drawings which disclose, by way of ex
amples, the principle of the invention and the best mode
which has been contemplated of applying that principle.
v"In thevdrawings:
ance portion including D1 comprises aseries circuit ‘of
resistance .Z1,.'D1 and >resistance'13 ‘connected between
junction 19 and the 1 output terminal of latclr'll. While
the parhof the variable A.C. impedance-portion includ
ing D2 comprises a series circuit of resistanceZZ, D2 and
resistance 14 connected between junction “19 and the 1
output terminal of latch 12. Furthermore, in order to
70 provide a better control of the biasing conditions of the
diodes, the. common terminal o‘f-the resistance 21 and
D1. isgrounded through resistance 23‘and'the. common
3,047,854
3
4
terminal of resistance 22 and D2 is grounded through
is to prevent any A.C. voltage from passing to the output
resistance 24 as shown.
when latches 11 and 12 are both in a reset condition
corresponding to a binary input equal to “00” and a
decimal equivalent of zero. To obtain this type of opera
tion, the base-emitter junction of Q2 is maintained in a
Accordingly, when both latches 11 and 12 are in their
reset condition corresponding to a binary input informa
tion equal to “00” (having a decimal equivalent of zero),
the 1 output terminal of each will be at an ‘up voltage
Under
slightly back biased condition by the proper selection of
the biasing resistances 34, 35 and 36. Accordingly, when
these conditions, the variable A.C. impedance portion will
have its smallest magnitude and the amplitude of the A.C.
by the application of an up voltage level thereto through
remains in its reset condition corresponding to binary in
put information equal to “01” (having a decimal equiva
D6 receive an up voltage level from latch 11 or 12 when
the binary input information equals a “00” and decimal
level so as to forwardly bias both D1 and D2.
the voltage level at the base of Q2 is not modi?ed
voltage at junction 19 will be the least. On the Other 10 either D5 or D6, Q2 remains in a cut oil condition and
no A.C. voltage is passed therethrough. Neither D5 and
hand, when latch 11 goes to its set condition and latch 12
lent of one), the 1 output terminal of latch 11 goes to
equivalent of one.
variable A.C. impedance portion will increase and the
amplitude of the A.C. voltage at junction 19 will be larger
volts r.m.s. to represent binary input information of “00,"
The following are typical circuit components, param
a down level and the 1 output terminal of latch 12 re 15
eters and voltages which may be utilized in the circuit
mains at an up voltage level so that only D2 remains
of FIG. 1 to‘ obtain A.C. voltages of 0, .0175, .150 and .525
forwardly biased. Accordingly, the magnitude of the
“O1,” “10” and “11,” respectively:
representing a decimal one.
Fixed A.C. reference voltage _______ _.
Similarly, when latch 11 remains in the reset condition
‘+ D.C. supply voltage _____________ _.
and latch 12 goes to the set condition corresponding to
Up voltage level for latches ________ _.
binary input information equal to “10” (having a deci
Down voltage level for latches ______ _.
mal equivalent of two), the 1 output terminal of latch
11 remains at the up voltage level and the 1 output ter 25 Transistors Q1 and Q2 _____________ _.
Diodes D1, D2, D3, D4, D5, D6 ____ _.
minal of latch 12 goes to the down voltage level so that
and based on proper scaling, if the resistances associated
with D2 is greater in relation with the other resistance
values within the variable A.C. impedance portion of 30
the A.C. voltage divider, the amplitude of the A.C. volt
age at junction 19'wil1 be still larger representing a deci
mal two.
Likewise, when both latches 11 and 12 are driven to
their set condition, both D1 and D2 will no longer be 35
forwardly biased, and the magnitude of the variable A.C.
impedance portion will be further increased so that the
amplitude at junction 19 will also be increased corre
sponding to a binary input equal to “11” (having a deci
through transistor Q1 to obtain a phase which is indica
tive of the sign of the binary input information.
Q1
10 volts D.C.
10 volts.
0 volts.
2N167.
1Nl91.
Capacitance 16 ___________________ .._ 1y. farad.
D1 is forwardly biased, while D2 is not. Accordingly
mal eqivalent of three).
The A.C. voltage appearing at junction 19 under the
input conditions just described may not be completely
representative of the analog quantity until it is passed
1.78 volts r.m.s.
40
Resistance 17 _____________________ ...
Resistance 18 ____________________ __
Resistance 21 _____________________ _.
Resistance 23 _____________________ _.
Resistance 13 _____________________ .._
Resistance 22 _____________________ _Resistance 14 _____________________ _.
Resistance 24 _____________________ _.
Resistance 20 ____________________ __
5K ohms.
50K ohms.
6.2K ohms.
3.6K ohms.
3K ohms.
1.8K ohms.
3K ohms.
3.6K ohms.
123K ohms.
Capacitance 28 ___________________ .. .10 farad.
Resistance
Resistance
Resistance
Resistance
Resistance
29 ____________________ .._
27 _____________________ _.
26 _____________________ _.
25 _____________________ .._
40 ____________________ __
42K ohms.
200K ohms.
2K ohms.
2.1K ohms.
68K ohms.
Resistance 31 _____________________ _. 62K ohms.
Capacitance 32- ___________________ __ 1,u farad.
45 Resistance 39_____________________ _. 43K ohms.
is shown as comprising an NPN transistor connected in
Resistance 37 ____________________ __ 75K ohms.
a common emitter phase splitting con?guration. As
shown, resistance 25 acts to provide the collector load
Capacitance 38 ____________________ __ 1n farad.
energized by the +D.C. voltage supply; resistance 26
provides the emitter load; and resistance 27 provides a
bias to the base. Resistance 29 is part of the input
impedance of Q1 and capacitance 28 acts to isolate direct
current therefrom.
Resistance 34 _____________________ _. 50K ohms.
Resistance 35 _____________________ ... 120 ohms.
Resistance 36 _____________________ _. 620 ohms.
In general, the selection of these circuit component
parameters and voltages is a matter of design to provide
the desired scaling required by the particular engineering
The output voltage ‘from Q1 may be taken from either
application. However, the amplitude of the ?xed A.C.
its collector or its emitter. When the output voltage is
reference voltage should be small enough so that diodes D1
and D2 are never driven to conduction thereby when the 1
output terminals of latches 11 and 12 are at the down
voltage level or stop conducting when the 1 output ter
minals of latches 11 and 12 are at the up voltage level.
taken from the emitter, it is in phase with the input
signal being applied to the base. On the other hand,
when the output voltage is taken from the collector,
it is 180 degrees out of phase with the input signal being
applied to the base. The collector is connected to output 60 Moreover, resistances 23, 13, 14 and 24 should be chosen
to produce minimum transit voltages ‘and, while at the
terminal 30 through ‘diode D3, oriented as shown, and the
same time, ‘allow diodes D1 and D2 to modify the vari
emitter is connected to output terminal 30 through diode
able A.C. impedance of the A.C. voltage divider as de
D4, oriented as shown. When the 0 output terminal
of sign latch 10 is at an up level, D3‘ is forwardly biased
scribed hereinabove. Furthermore, resistance 37 and
capacitor 38 should‘ be selected so as to coact with
and D4 is back biased. Terminal 30 is connected to the
capacitor 32 and resistance 31 to provide a short turn-off
collector of Q1. Similarly, when the 0 output terminal
is at a down voltage level, terminal 30 is connected to
time for transistor Q2.
As described, FIG. 1 shows a new and improved means
the emitter of Q1.
The A.C. voltage appearing at terminal 30 is applied
for converting binary electrical information having two
to the base of transistor Q2 through resistance 31 and 70 orders of binary signi?cance into an A.C. analog voltage
having an amplitude equal to the magnitude of the analog
capacitance '32. Transistor Q2, which is shown connected
in a common emitter con?guration, has an output trans
and a phase which is determined by the sign of the analog.
former 33 connected to its collector. Although Q2 and
Such a conversion means may be utilized to provide the
digital-to-analog conversion step within a conventional
related circuit components may act to isolate the output
from the phase changing components, its main function 75 digital servo system such as that shown in FIG. 2. Re—
3,047,854
5
ferring to FIG. 2, conventionally a digital input quantity
is compared with a digital follow-up quantity within a
digital comparator 41 so as to provide an error digital
quantity which is applied to an electronic digital-to-anaiog
converter '42. Converter 42 in turn applies the analog
error quantity to a servo ampli?er ‘43 so as to appropriate
ly energize a servo motor 44 for rotation at a velocity
commensurate with the magnitude of the error and in a
6
capacitor and resistor so as to provide a variable A.C. out
put voltage at the terminal of said capacitor remote from
said common junction, said output voltage having an am
plitude commensurate with the analog of said digital in
formation to be converted.
2. A digital~to-analog converter comprising a source of
binary electrical information to be converted, D.C. switch
ing ‘means responsive to said binary electrical information,
direction determined by the sign of the error. Finally,
an A.C. voltage reference source, a DC. isolation means
if an analog-to-digital converter 45, conventionally known 10 connected thereto including an impedance to ground, a
as a shaft digitizer, is driven by shaft 46 of servo motor
?rst resistance and a second resistance connected in series
with ‘one extremity of said series connection being connect
cation to digital comparator 41 in a manner so as to be
ed to the terminal of said impedance within said D.C. isola
equal and opposite to the digital input thereto and null
tion means which is remote from ground, the other extrem
out the error quantity being derived. When the digital 15 ity of said series connection being connected to a DC. Volt
to-analog converter 42 is constructed according to the
age source, a selectively variable impedance network con
teachings set forth hereinabove in connection with FIG.
nected between said common junction of said ?rst and sec
1, an improved performance of the total digital servo
ond resistances and A.C. ground, the magnitude of said
44, a digital follow-up signal may be derived for appli
system is attained because of the improved time response
variable impedance being controlled by said D.C. switch
within the digital-to-analog converter.
20 ing means in response to said binary electrical information
While the teachings of the present invention have been
to be converted, electronic switching means having on and
described as providing for the conversion of digital in
off switching modes of operation connected to be respon
formation having two binary orders of signi?cance, the
sive to the AC. voltage amplitude at said common junc
same technique could be similarly applied to provide for
tion of said ?rst and second resistances, said switching
the conversion of digital information having three or 25 means being responsive to said D.C. switching means so as
more orders of binary signi?cance.
to be in its closed switch mode only when said binary input
Referring again to FIG. 1, although the switching com
information corresponds to a decimal number of other
ponents utilized to ?nd the binary information to be con
than zero, said A.C. analog output voltage being measured
verted are shown as latches, it is emphasized that any
at the output of said switching means.
other conventional bistable switching components could
3. The digital-to-analog converter as set forth in claim
be substituted therefor. In addition, while FIG. 1 has
2 wherein said variable impedance network comprises
been described based upon the binary electrical informa
plural parallel resistance paths wherein the voltage at a
tion being divided according to negative logic, it should
point within each path is modi?ed in accordance with the
be clear that the circuitry could be modi?ed to operate
binary information stored in said D.C. switching means so
according to positive logic without departing from the 35 that the A.C. voltage amplitude at said common junction of
teachings of the present invention.
'
said ?rst and second resistances is modi?ed in accordance
While there have been shown and described and pointed
therewith.
out the fundamental novel features of the invention as
applied to a preferred embodiment along with several
References Cited in the ?le of this patent
speci?c modi?cations, it will be understood that many addi 40
tional omissions and substitutions and changes in the
UNITED STATES PATENTS
form and details of the device illustrated and in its opera
2,685,084
Lippel _______________ __ July 27,
tion may be made by those skilled in the art, without de
2,736,889
Kaiser _______________ __ Feb. 28,
parting from the spirit of the invention. It is the inten
2,738,504
Gray ________________ __ Mar. 13,
tion, therefore, to be limited only as indicated by the 45 2,839,740
Haanstra _____________ __ June '17,
scope of the following claims:
2,853,699
O‘Neil _______________ __ Sept. 23,
What is claimed is:
2,858,434
Tollefson _____________ __ Oct. 28,
1. A digital-to-analog converter comprising an A.C.
2,872,670
Dickinson _____________ __ Feb. 3,
voltage source, a capacitor, a resistor, said capacitor and
50
resistor being connected in series with the A.C. voltage
FOREIGN PATENTS
source, electronic D.C. switching means including unidi
731,650
Great Britain __________ __ June 8,
rectional devices responsive to the digital information to
be converted, a variable A.C. voltage attenuator providing
OTHER REFERENCES
an attenuation which is dependent on the condition of
1954
1956
‘1956
1958
1958
1958
1959
1955
said D.C. switching means, said variable A.C. voltage at 55 “Electronics Engineering Edition,” Aug. 1, 1958, vol. 31,
pp. 90-93.
tenuator being connected to the common junction of said
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