# Патент USA US3050260

код для вставкиAug. 21, 1962 3,050,251 F, G. STEELE INCREMENTAL COMPUTING APPARATUS Filed Sept. l5, 1957 8 Sheets-Sheet 1 1%@ ÉW MM Aug. 21, 1962 F. G. STEELE 3,050,251 INcmnENTAL COMPUTING APPARATUS Filed Sept. 16, 1957 wmwm 8 Sheets-Sheet 2 Aug. 21, 1962 F. G. STEELE 3,050,251 INCRÈMENTAL COMPUTING APPARATUS Filed sept. 1e. 1957 s sheets-sheet s ÉÄW” Aug. 21, 1962 F, G. STEELE 3,050,251 INCREMENTAL COMPUTING APPARATUS Filed sept. 1e, 195'? ,.4 s sheets-sheet 4 Aug. 21, 1962 F. G. STEELE 3,056,251 INCREMENTAL COMPUTING APPARATUS Filed sept. 1e, 1957 i... _ mv. 8 Sheets-Sheet 5 Aug. Y21, 1962 F. G. STEELE INCREMENTAL COMPUTING APPARATUS Filed Sept. 16, 1957 8 Sheets-Sheet 6 K L________;ï__.__.___________________..__ ______ S Pig )_____________. f Aug. 21, 1962 F. G. STEELE 3,050,251 mem/1mm. COMPUTING APPARATUS Filed sept. 1e, 195'? 8 Sheets-Sheet 8 @lWWW-WWW» 0 11%@ 1%» ßf fm L 425 ß l 4 í .634 3,050,251 4 continued computation. Restoring computation is rathe formation of correspondingly'scaled output digits of out easily accomplished in a GP by storing all constants in VVa permanent memory which cannot be changed and by using a programmed computation which does not utilize put number answers. In the ñrst of a sequence’of opera'-V tion intervals i (where í has the successive values l, 2, 3 . . n) the highest order digit of each of the input num previously computed values of variables, but generates 5 bers is appliedand in response thereto the highest order all Variablesanew at each computation, from the sampled digit of each of the output number answers is formed. values of the input quantities. j ~ Such full restoration is, In the second operation interval z', the second highest in a DDA,.very diíiicult to provide, since in the very order digit of each of the input numbers is `applied and nature of DDA computation numbers are not formed the corresponding digit of each ofthe output number v anew Ábut are only modified slightly _at each iteration inz 10 answers is formed. In continued operation, in response computers is the relative ease with which a program code to each successively scaled digit of the input numbers, the correspondingly scaled output digits are formed. The fact thatthe highest order digits of answers are formed canbeprepared by> untrained personnel. In the use of a iirst and are not subject to change upon subsequent pro» Vaccordance with applied input increments. ' Another commonly comparedfeature of DDA and GP DDA, it is usually relatively easy to go directly from the 15 duction of lower order digits appears to be unique to the mathematical formulation ofthe problem to a diagram present computational system and offers the'very great which specifies the-required interconnection of integrators. . advantage that a computation may be begun as soon as On -the other hand, in coding a GP computer it is neces the first digits of the input numbers are entered and will sary to preparea long list of detailedrstep by step instruc -be completed lat the very time that entry of the last digi tions which are quite'remote from the broad features of 20 of the input numbers has been completed. Y ~In a preferred Vembodiment of the invention, as willbe the »mathematical formulation. Thus, the DDA appears to have aV very real advantage in, this respect. explained hereinbelow, each 4computing block contains a YThe present invention provides a new type of incre Y number and an R number, Vand in each operation in» mental computer which embodies some of the best fea-_ terval i receives successively scaled input digits or incre tures of the DDA and GPY computers. Asrin a DDA, 25’ ments AXÍ and AYi, modiiies its Y and R numbers in numbers are permanently grouped together, stored in ele accordance with these increments, and produces corre mental computing blocks, which receive applied input i11 ~ spondingly scaled outputrincrements AZi. The successive increments have sign and magnitude il or O and have ` the successive scales 2_1, 2r2, 2:"3, etc. (thus having the ` crements and produce corresponding output increments. Computation is programmed through simple interconnec tion of computing blocks for the communication of in 30 scale 2-î in the ith operation interval). These increments, crements between blocks. The equipment requirements thus represent, as will be. fully explained, the successive of the »incremental computer of the present» invention are, digits of numbers expressed in a trinary number system. therefore, about as low as those of a DDA computer. In AY, input increments are Yadded to the Y number, the addition, the ease of program preparation, common to predetermined scaling .of the increment being accom DDA’s, is retained and even enhanced in the incremental 35 plished by adding each successive increment to a succes computer of the present invention. sively lower order digit position of the Y number. The f However, in addition, some of the very best features AX, input increments are used as multipliers of a function of GP computation are retained in the incremental com- . `g(Y, AY), the multiplied function g(Y, AY)AX, being puter of the present invention. Although accomplished added to the R number. The predetermined scaling of through purely incremental operations, all ordinary arith 40 the AX input increments is accomplished by regularly ì ~ metic operations upon numbers may be accomplished at doubling therR number. kThe output increments AZ, are speeds equal or superior to the speed of GP computation; formed in such a manner that » and ,if desired, fully restoring computations may be'pr‘o#V grammed in which transient errors areinevitably cor rected. i 45 ' According to the underlying mathematical foundations of the present invention Vis is recognized that the digits of a number merely represent successively scaled incre ments fwhose summation equals the number. K f Y I ziziegurtraixi]+RW? I 1 ì Y K where AZÍ,.AX„ and AYiiare increments that are succes-Y sively halved in scale. ’ . 1. ' YAn example is provided hereinbelow of the intercon nection of assemblages of such computing blocks for the For ex ample, in _thedecimal number .531, the digits +5, +3 5G performance of multiplication ofrtwo numbers A0 and v . and +1 represent the sign and magnitude of the succes sive scaled increment 5'10-1, 3-10-2, and l-l0-3 whose `sum equals 53%000. Similarly, in the binary number .110, B0, .each supplied as a sequence of successively scaled digits or increments A(A0)i and A(B0)i. The product 1 AOBO ismcrementally »formed in accor-dance with the re. the successive digits +1, +1, and ~0 represent the suc lationship cessively scaled lincrements +1 -2-1, +1-2-2, and +0-2-3 whose sum equals +%. . According to the basic concept of the present inven ` t tion, `computing blocks are provided which are adapted W >Another example is provided in which a number A0 provided »as a sequence of successively scaled digits is for operating upon input increments which regularly vary in scale, to accordingly modify numbers stored Within the 60 multiplied iby a constant A1 stored in the Y register of a „g computingiblocks and to produce correspondingly scaled output increments. More particularly, theV computing Yblocks of the present invention are adapted for operating in a regular fashion upon successively applied digits of numbers, the successivedigits of each number being treat 65 computing block and has added thereto another constant B1 stored in the R register of the block, the output digits formed by this operation being similarly operated upon by constants A2, B2, A3, B3, etc. stored in successive com puting blocks. A final result of the form ed'as successively scaledY increments of the'number. It is shown that through appropriate interconnection of ele is formed. This is an especially useful type of computa mental Ycomputing blocks, all arithmetic operations upon tion, since it can be'sho‘wn that almost all power series numbers may be carried -outV through purely incremental operations upon successively applied digits of the num v70 expansions can be advantageously refritten in a product` expansion of the abovedescribed type; In addition, if all bers. ’ constants B1, B2, B3, etc.=0-,.the`n the abovedescr-ibed com A most unusual feature, found in a preferred embodi putation resolves to the simple cascaded multiplication ment of the incremental computer of the invention, is a l). . Aj.V ` ‘Y ' one-to-one correspondence between application of sucé cessively scaled input digits of input numbers and the 75 Itis an object of the present invention fto provide incre 3,050,251 ' / 6 5 duce a resultant sequence of corresponding successively mental computing apparatus tor operating upon succes scaled output increments A(AB)1 representing successive digits of the product AB in accordance with the relation sively applied input increments of varying scale to produce resultant output increments similarly varying in scale. It is another object of the present invention to provide A(AB)1-`=AA1ABi--l--Á1AB1+B1AA1. Y It is still another object of the present invention to pro incremental computing apparatus yfor operating upon input signals representing the highest order digits of a plurality of input number-s to produce output signals representing rvide cyclically operable incremental computing apparatus ttor multiplying a. number A1 stored in a register, by a number A0 whose »successively lower order digits are rep »the ‘highest order digit of the result of a predetermined resented by lsequentially applied successive decreasingly mathematical operation upon the input numbers. It is another object of the present invention to provide 10 scaled input increments A(A0)1, to produce in response to each input increment a correspondingly scaled output in computing apparatus of the abovedescribed type which is crement A21, the `successive output increments AZ1 repre adapted for further operating upon signals representing senting respectively the- ysuccessive `digits ot fthe product AOAI. the highest ‘order digit of a result 'of a mathematical op eration to produce output signals representing the high est order digit ot a `further resuit of a predetermined 15 mathematical operation upon the ñrst named result. Itis still another object of the present invention to pro vide incremental computing apparatus of the described »type which is `similarly responsivevto sequentially applied input -signals representing corresponding successively lower order digits of input numbers for sequentially producing It is yet another object of the present invention to pro vide an interconnected assemblage of computing blocks for storing a plurality of constants A1, A2 . . . A1 and responsive to the highest order digit or an input number A0 for forming the highest order digit of the product 20 A0A1A2 . . . A1. It is an additional object ‘of the present invention to output signals representing corresponding successively prov-ide an interconnected assemblage of computing blocks lower order digits of the result of a predetermined mathe tor storing a plurality of constants A1, B1, A2, B2 . . . matical operation upon the input numbers. etc., and responsive to the highest order digit of an input vide an incremental computing block responsive to se quan'fítyt ’ ' [(AoAl-I-BilAz-I-B2l etc. ' - l». quentially applied successively scaled input increments The novel Ifeatures which are believed to be character -istic `of the invention both as to its organization and Y It is still another object of the present invention to pro 25 number A0 for forming the highest order digit of the AX1 and AY1 for sequentially modifying stored Y and R numbers in accordance with the applied input increments and for sequentially producing corresponding successively method of operation, together with iur-ther objects and ad 30 vantages thereof will be ‘better understood trom the tfol lowing description considered in connection with :the ac companying drawings in which a specific embodiment of the `invention is illustrated by way of example. It is to applied successively halved-in-scale input increments AX1 be expressly understood, however, thatV the drawings are It is another object of the present invention to provide an incremental computing block responsive to sequentially 35 provided vfor purposes of illustration and description only and are not intended as a `deiinition yor" the limits of the and AY1, for adding each successive AY increment to suc invention. cessively lower order digit position oi the Y number and scaled increments AZ1, whose summation represents a pre determined mathematical function of the input increments. for sequentially producing corresponding successively FIG. l is a ‘block diagram ot an embodiment of an ele mental compu'tlng block in accordance with the present halved-in-scale output increment A21 whose summation is ` 40 invention. proportional to the summation FIG. 2 is a partly block-partly circuit diagram of an 2g assemblage of computing blocks interconnected for «the i performance of a plurality of -cascaded mul-tiplications It is still another object tof the present invention to pro and/or additions. . _ vide an incremental computing block having stored Y and FIG. 3 is `a partly block-partly circuit diagram of an R numbers and responsive to sequentially applied suc other assemblage iof computing blocks interconnected for cessively halved-in-scale input increments AX1 and AY1 the multiplication of two numbers respectively represented for sequentially modifying the stored numbers and pro as two corresponding sequences of sequentially applied ducing correspondingly scaled AZ1 output increments, proper weight being given to each successive AX incre 50 ysuccessively scaled increments. FIG. 4 is a schematic and circuit diagram of an em ment by `successively doubling the R number and proper bodiment of a source of setting signals, utilized in the weight being given to each successive AY1 increment by control of the assemblages of computing ‘blocks shown adding each successive AY increment to successively lower in FIGS. 2 and 3. order `digit positions of the Y number. FIG. 5 ‘is a drawing of a suitable embodiment of a It is yet another object of the present invention to pro 55 source of timing signals, utilized inthe control of the vide apparatus for performing a predetermined mathe assemblages of computing blocks shown in FIGS. 2 matical operation upon input numbers and comprising a plurality of incremental computing blocks having their inputs and outputs interconnected in accordance with the predetermined mathematical operation. It is still another object of the present invention to pro vide incremental computing apparatus for multiplying two numbers A and B represented respectively by a 1st se quence of successively sca-led input increments AA1 and a second sequence of corresponding successively scaled input increments AB1 by combining each pair of corre' sponding input increments to produce a correspondingly scaled output increment A(AB)1. ' and 3. ' ` FIG. 6a is a circuit diagram of an embodiment of a summer circuit contained in the elemental computing block shown in FIG. l. FIG. 6b is a partly block-partly circuit diagram show ing embodiments of a Y register and an associated Y gating matrix utilized in the computing block of FIG. l. FIG. 6c is a partly block-partly circuit diagram of 65 embodiments of an R register, a AZ register, and an associated R gating matrix utilized in the computing block of FIG. l. ' ` FIGS. 7, -8, 9 and V10 consisting of FIGS. 7a through vide incremental computing apparatus tor multiplying two ' 7j, 8a through 8j, 9a through 9e and 10a through 10e, numbers A `and B by producing a íirst sequence of succes 70 are waveform charts illustrating signals appealing in various modes of operation of the assemblages of com sively scaled input increments AA1 representing successive puting blocks shown in FIGS. 2 and 3. digits of the number A, producing `a `second sequence of Referring now to the drawings, there is shown in successively scaled input increments AB1 representing suc FIG. 1 a block diagram of a computing block 10, accord cessive digits of the number B, and combining each pair of 'correspondingly scaled increments AA1 and AB1 to pro 75 ing to the invention, which contains two registers, a Y It is yet another object of the present invention to pro 3,050,251 7 8 register and an R register for storing respectively a ñrst number designated the Y number and a second number designated the R number in permanent association with each other, and which is operable in response to incre mental inputs designated AX and AY for modifying the Y and R numbers and for producing corresponding ' . forms signals representing a modified Y number, VWhich are applied back to the Y register along an input bus 24 to store therein the next Y number, designated Yin. The new number Yi+1 is deiined as a predetermined func tion f(Y1, AYi) of the inputs to Y >gating matrix 16. Matrix 16 also forms signals representing anotherpre determined function g(Y1, AY) which is applied to R ' incremental outputs designated AZ which can be com municated to other similar computing blocks- to serve As will be hereinafter gating matrix 14 over an input bus 25 thereof. In similar manner R gating matrix 1‘4 receives, during described, the computing block shown in FIG. 1 is adapted for operating upon a sequence of incremental each operation i, the applied increment AXi, the signals representing g(`Y1, AYi), and (over an input bus 26) there as AX and AY inputs. inputs which regularly vary in scale, the computing block signals representing the number R1 stored in the R reg ister, and in response to these inputs applies signals back modifying the stored Y and R numbers in full con formity with the changing scale of the input increments, to the R register, over an input bus 27, to store therein ‘ and producing'AZ output increments which correspond 15 a new modified R number RM1, and also applies signals ingly change scale. As will -be demonstrated herein to AZ register 20 to store therein a resultant AZ incre below, many computational operations and in particular ment AZi. all arithmeticoperations can be accomplished through According to the preferred embodiment of the inven appropriate interconnection of elemental computing tion, during each successive operation i of a computa blocks. . 20 tional sequence, the applied input increments AX, and As shown in FIG. l, computing block 10 is adapted AlYi, A2Yi, etc., have one half the scale that they had Vfor receiving certain setting signals SS which may be during the preceding operation, and the outputrincre utiliz/ed periodically, at the beginning of a sequence of ments Zi are similarly halved in scale at each successive computational operations, to set desired initial Values timing interval. More particularly, in a preferred emr of the Y and R numbers into Vthe Y and R registers. 25 bodiment of the invention, which is described herein Such setting signals may be applied from auxiliary stor below, all increments during the ith operation are re age registers or other suitable source of number repre stricted to the values senting signals. Computing block 10 is also adapted for 'gill receiving certain timing signals TS -Which are utilized to ' sequence successive operations of the computing block, 30 as will be hereinafter described. ' where ' or (abbreviatedi-lg) z'=l,- 2, . . . n. Thus, in a computational It will be understood hereafter that a single “com putational operation” of a block 10 comprises the recep tion of a AX input and a AY input and the formation of a corresponding AZ output. In the operation of a sequence, during the »iirst operation, the AX increment (and other increments) may assume the values i-ï/z computing block, initial values are periodically set‘into the computing block. After each setting of initial preciated, any number (scaled between Y-i-‘l and --1) values, an iteration or “sequence” of n (a predetermined crements and, as Will be shown, this makes possible the «accomplishment of most ordinary arithmetic opera integer) computational operations is performed. or 0, and during the second operation may assume the values -l_~% or 0, and so forth. As will readily Íbe ap may be represented by such a sequence or stream of in IFor purposes of convenient reference the successive “opera 40 tions upon numbers, by purely incremental operations tions” performed Vduring a “sequence” are designated as upon such sequences or streams of three valued incre operations í (Where i has the successive values 1, 2, 3, ments. 4 . . . n). ' the input and output increments. = ' ' The following notation will be used in connection with`Y Similar nomenclature is fused to designate During -any operation the Vdesignation of these increments. The scaled values i, va corresponding AX input increment AX, is received; (zi: l or 0) one or more AY input increments 'A1Y1, AZYi . . .’ etc. may be received; and a corresponding AZ output incre Yment AZ, is formed. In accordance with this nomen of these increments will be denoted by the use of the clature, the Y and R numbers stored in a >computing block at'the' V‘beginning of an operation i are designate symbols AXî, AYi, AZi, etc., as was done hereinabove. as numbers Y1 and Ri. The corresponding -absolute or unscaled values (il or 0) of these increments will be denoted by the under lining of these same symbols-as Y The embodiment of computing block 10 shown in ' FIG. 1 includes, in addition the Y’and R registers, the AX1, AYi, AZi, Etc. following elements: >a computing circuit 12 which is seen to include an R gating matrix 14 and a'Y gating matrix Scaled three valued increments, as described herein- ' 16, the computing circuit intercoupling the Y and R above, will be designated as trinary represented incre registers Áand lbeing utilizable for operating upon the i ments, and sequences or streams of successively scaledV tn'nary increments will be designated as a trinary se quence or stream. When such a sequence is used to rep resent a number, it will be said that the number is rep resented in -tm'nary notation or that it is a trinary number. numbers in those registers in accordance with the applied AX and AY increments; a summation network 18 which is operable` for summing the applied increments A1Y1, A2Y1, etc. to form a total increment AY! which is sup plied to Y gating matrix 16; and a AZ register 20 Which is adapted for receiving and storing each AZ, increment as it is formed and for communicating these increments to other computing blocks 10. In any assemblage of com puting blocks 10, the AZ Iregisters 20 may be thought of Y as comprising a single common register for storage of AZ increments-_a common register from which each computing block 10 may obtain desired VAZ increments to serve as its AX and AY inputs. As indicated in FIG. 1, thetotal increment AY, is >applied to Y gating matrix 16, which also receives over an inputibus 22., signals supplied by thewY register which ' Vrepresent the numberYi stored therein. 'In each opera Thus, for example, the sequence of successively pre sented trinary increments of absolute value 0, 0,' +1, -1 is a representation of the number +1/í6 (since %`+%-I-1/s--1A6=-{-%6). It is clear that the successive 'trinary increments can be considered to be digits, pre sented highest order `digit first, of a trinary number Arep resentìng -|-J7í6. To facilitate the formation of trinary increments and in the preferred embodi ment of the invention, numbers »are normally maintained or stored in the Y and R registers of each computing block l0 in a modified dinary notation. lIn -true dinary representation each successive digit of 70 also to conserve storage space, tionV i, in-resp'onse to these inputs, Y gating matrix 16_ 75 a number is represented by a `single bivalue signal having y 3,050,251 10 appropriately scaled values of il. For example, a true dinary representation of the number -i-ëíö is i+1, cessive operations l, 2, 3, 4 . '. ., the corrßpondingly successive Y, increments applied »are '-1, --1, -l-1 (Since -l-l/2-%-%+%e=-l-i/1e)- The AY1=0, Av2: +1, AYP-_1, AYP-1 ytrue dinary representation designated Yd of any number Y may be readily calculated from the normal binary representation Yb of the number by use of the following formula, Formula 1: where the scale of the. successive increments is under stood to be 1/2, 1A, Ms, JAG' . . . etc. where in the calculated Yd number each 0 is considered to have or is replaced by the value --=1. For example, 10 TABLE 1 to recalculate the dinar-y number representing 44%; begin with the ordinary binary number (2) Operation 2 2 (a) -In the calculated Yd, if each 0 digit is considered to have Yi AY; 1 Yr-)LOÜÜÜ . . . ê_1_71=0 2 Yz-nn’tíioo . _ . A_Yr=+1 s ira-)1.0100 . . . ¿ZF-1 4 Yr-nnoio . . . ¿2F-1 5 Ya 15 and then calculate rcp-liga@ . . . =.1o01/100 . . . The following table, Table l, summarizes the formation of successive values of Y1 in response to these increments. Ya Yb=eí6=+~oo11oo . . . - 20 an appropriately scaled Value of ---1, it is seen that the 1.0001 . . . ñrst four digits of Yd are the required dinary digits of the number -l-ëíe and that all digits beyond the fourth cancel each other and may be disregarded. In Table 1, the vertical arrows indicate Ithe varying In the Y -and R registers of the preferred embodiment 25 points at which each successively scaled AY, increment of the invention, numbers are normally held in a modi fied dinary representation, the modification consisting merely of the fact that the displacement of the binal is summed to the corresponding Y1 number. It is seen that, in the dinary notation utilized and for increments successively halved in scale, the point of insertion of the point necessitated by the -abovementioned division by 30 increment is moved or shifted one digit to the right at two is not followed, so that the effective definition of a each timing interval. number Yr held in a register is: Although many methods may be utilized to thus shift the insertion point of successive increments, there is one very simple method, having obvious advantages in ease It is clear that in the preferred embodiment of the invention, eachA register may comprise merely a sequence 35 of the mechanization which is utilized in the preferred embodiment of the invention. According to this method, of storage cells or storage stages, each cell or stage being in order to mark. the successive digit positions at which capable of storing a single bivalued signal representing the corresponding digit of the Y, or R1 number stored insertion is to take place, a 1 Value marker signal is ini in the register. In each operation z', as discussed above, 40 tially automatically set in at the 1/2 scaled digit position these stored signals are modified in »accordance with the inputs to computing circuit 12 to represent the modified numbers Yi+1 of RM1. of the Y number and is moved one digit to the right at each timing interval to thereby indicate the varying points of insertion. Thus, in the actual machine operation the As hereinbefore stated, in the preferred embodiment -successive Y, values shown in Table 1 above would ac of the invention to be described bereinbel'ow, the opera 45 tually appear as follows: ' tions performed upon. the Y and R numbers are similar in some respects to those utilized in an ordinary digital integrator. They include an integration or summation of applied AY increments in the Y register (so thatv f(Y, AY) simply equals Yi-l-AYi); a multiplication of the function g(Y, AY) of the Y number by the AX en_ increment and an addition of the resultant function to the R number; and the formation of a AZ overñow increment which is subtracted from the R register. How- - ever, each of these operations has been radically changed to mechanize the acceptancel of input increments which 55 regularly vary in yscale and to mechanize the formation of AZ output increments which similarly vary in scale. where in each case theinsertion point for each increment More particularly, in the integration or summation to is indicated by lthe l valued signal which is farthest to the Y number of AY increments, which are successively the right, and thus serves as the abovedescribed marker halved in scale, apparatus is provided'for adding each 60 successive AY increment to the Y number at a different position in the Y'register, corresponding to the changing signal. The marker signal is, of course, not treated as an ordinary digit of the Y number- and is, therefore, not allowed to otherwise aiîect arithmetic operations upon scale of `the AY increments. Thus, in a computational sequence, the first AY increment AY1 is added to the Y 65 the Y number. It is appropriate at this point to mention that in the register »at a position corresponding to »a scale of Ve, the specific embodiment of the invention, whose mechaniza~ second AY increment AY2 is added to the Y register at a tion will be hereinbelow described, the form of summer position corresponding to a scale of 1A, and so on, until 18 which is utilized is adapted for summing but two all of the scaled increments have been summed in this manner to the Y number. A brief numerical example 70 AY input increments, AlYi and A2Y1, and operates to produce a total increment AYi which represents the true will illustrate how this operation is carried out. algebraic sum of the applied input increments. The fol Assume that -at the beginning of a computational se lowing table, Table 2, summarizes the described relation? quence the number zero (represented in the machine ship between the values of the input increments and the notation as 1.000 . . .) is set into the Y register as the initial Y, number Y1. Assume further that during suc 75 value of the resultant total increment AY1. 3,050,251 12 isvutilized. Thus in this embodiment the equation which is mechanized is: . where it will be noted that the AX and AY -increments are written in their unscaled forms,y since their predeter mined scaling is made eifective -by the successive dou bling of Ri. It will 4also -be noted that since AXi may have only the values il or 0, addition of [Yeiâ’flïfê A It is seen from Table 2 that in utilizing the described form of summer 18, the total AY increment AY, can to the R number may be accomplished merely by adding or subtracting the quantity assume any of the values +2, +1, V0,k -„l, _.2, scaled by the appropriate values of 21. It will lbe clear, however, that many- other >forms of summer 18 may b‘e utilized; as forexample, Vformswhichwtotal agreater numberof AY increments and/ or whichrscale `down the total incre ment to be in consonance with the inputs. to the. R number or.V by adding kthe number zero to the R number inraccordance with thevalue AXi. Y ' "Equations'deñning the la‘t'yovedèscribed operations per 20 ' That such predetermined scaling is actually made eifec formed in- the preferred- embodiment- of the invention tive is demonstrated by the following algebraic example upon the Y number and upon ythe AY increments are in which the operation of a computing block 10,_mecha~ now provided in summarization of the above discussion nized in accordance with Equation v13 above, is reviewed of these operations. ~ ~ Y AIYf-il or 0' for three successive operations. V(5) Y ' Y i p At the end of operations 1, 2 and 3, the successive values of R2, R3 and R4 will be: 30 AgYir-il OI' 0 35 i: 1 > Restating Equation 8 in iterative form: 40 Considering now the manner in which successively applied AX, increments are made effective at their corre~ »spondingly scaled values, it will> be remembered that, as stated .hereinbefore, in each operation i, a function g(Y, AY) is multiplied by the-correspondingAX incre ment and the resultant function is'added to the R num Now dividing both sidesV by 8 and rearranging terms there is obtained: n f ber@ In addition, a AZ increment is formed and is sub tracted from the R number. ' This manipulation may be generally summarized by the following equation: In the preferred embodiment of the invention, whose ' mechanization is hereindescribed, the function g(Y, AY) is defined, for reasons which will later appear, as: „(Y, AY1=Y1+^-25 <11) `'so that Equation 10 may be rewritten in the form: Rin:R,+|:Y,-;-A-2iii AXì-Azì 60 or writing this in the compressed summation form: <12) (19) However, since AX, and AZ1 are scaled quantities which or in the more general case, for any number n of timing intervals in a computation sequence: Y are halved in each timingginterval, a way must be de viscdrto make this scaling effective., This, as will be shown, can be mechanized by halving the Y number at eachV timing interval or by doubling the Ri number at 21 each timing interval. Either process may be largely accomplished by a simple _shift of the numbers in the Y 70 Many of the arithmetic operations and other computa and R registers relative to one another, that is by a right tional activities whichl can be performed with the de shift of the digits of the Y number relative to the R scribed embodiment of computing 'block 10 may be de number or by a left shift of the R number digits relative duced from Equation 2O developed above. ' to the Y num-ber digits. In the specific embodiment of In discussing these activities, for reasons which will the invention hereindescribed, doubling of the R number 75 become clear, it will be assumed that the register number 3,050,251 13 la ' » digit of the‘result so that it may be ignored. Moreover, R1 is scaled and maintained so that it is bounded by the numbers +1/2 and -1/2, or in other words, so that: since f D E AX 1=X One set of scaling rules which will accomplish this bounding of the R number is described by the following scaling Equations 22 and 23 which express limitations on the magnitudes of the Y number and upon the summa tions of the input increments: .=1 the quantity X may be substituted therefor. In this way Equation ¿28 reduces to the form: n E í=1 AZiÈY1X-i-R1 10 - ‘ ’ . ' thus demonstrating that in the described operational se~ quence, the stream of increments AZ1 Will represent the successive digits of the quantity Y1X-|-R1. and by utilization of the following Rules 24, 25 and 26 15 Formatìon of Y1X.--Note further that if the number R1 set is zero, then Equation 29a further reduces to the which dictate how the overflow increment AZ1 is to be form: formed, so as to always maintain R1 within its bounded values: n E Z i= Y1X If Ri-l-[Yi-l-êâl-i _Agi equals or exceeds -Hé then ¿ZF + 1 . . ' 1 20 (24) ._1 If R51-[Ya 2 _A_2_r.1st>etween a+ and Á (291)) i=1 thus demonstrating that in this case a simple multiplica tion is performed in which the multiplicand Y1 is held constant in the Y register, the digits of the multiplier X are successively applied (highest order digit ñrst) as the 25 successive trinary increments AX1, and the corresponding successive trinary digits of the product Y1X are formed Áas the successive trinary increments AZ1=A(Y1X)1. The number Y1X can 4be obtained in dinary form from the sequence of trinary increments AZì, by summing these 30 increments in accordance with their scale, in the Y regis ter of another computing block. v The manner in which such a multiplication is accom From inspection it will be seen that, in accordance with the foregoing scaling equations, the maximum values of plished is well illustrated by the simple numerical ex ample provided in Table 3 below: 35 TABLE 3 Y1=-|-%-§1.1000 . . z 2R1= will be bounded by il, and, therefore, that after sub traction of the A21 increment, each new 'value R1+1 of 0->1.0000 . . . Xml-lé represented as a stream of applied increments AX; of values the R number will be bounded, as required, by the 40 values il/z . Formation of Y1X+R1.-Referring again to the com putational techniques which can be deduced from Equa~ tions 8 and 20, there will ñrst be described an operational sequence involving only a single computing block 10, in 45 which the sequence AZ increments formed Iby the com puting block represents the quantity Y1X-l-R1. In per forming this computation the number X is represented by the applied sequence of increments AX1, or stated in equation form: 50 Il Z AX1=X (27) i=1 The increments AX1 may thus be viewed as the suc cessive trinary digits of the number X. At the beginning of the‘computation'the numbers Y1 and R1 are initially set into the Y and R registers respec tively. The increments A1Y1 and A2Y1 are connected as zero inputs so that AY1 is zero, and, therefore (in Equa 60 tion 8), Y1 is a constant equal to Y1. Thus, in this in stance Equation 20 reduces to the form: 2n However, since the scaling assures that Rn+1 will not exceed il/z, it is clear that the term 65 In Table 3 above there is provided an example of a multiplication of Y1=+Vz and X:el-V2 (where Y1 is a number initially set into the R register and X `is repre sented ias‘a sequence of applied input increments AX1) to 70 form the product Z=Y1X=(-|-1/z)(+1/z)=-l-1A repre , will not exceed sented by the corresponding sequence of output incre ments AZ1. 1 As indicated in Table 3, the numbens initially set into the Y and R registers respectively are 2R1=0 (represented, ' ,and thus is smaller in magnitude than the lowest order 75 as indicated by the arrow, in modified dinary as 01.0000) 3,050,251 15 i l5 and Y1=‘+1/2 (represented as 1.1000). The quantity the digits to the right and left of the binal points may be X=+Vz is represented as a sequence of applied incre denoted as shown. Rules lfor formation of 2R1+1 andY AZil can then be expressed by the following equations. For the new :digits of ZRHI, which will be designated ments AX1=+1/2, AX2=0, AX3=0, etc. During the iirst operation, operation 1, the quantity as the digits R1+11, Rj+12 . . . RHJD, R1+1n+1, Rî+1n+2i is added to the quantity 2R1=0 to form the quantity (32) 1 ` Since Y1AX1 was represented in the form 1+i/z, and 2R1 was in the for-m 1+0, it is clear that 1 And for the formation of AZi, the value of each incre represented in the form 2+%.. In accordance with ment may be determined in accordance with the follow scaling rules (24), (25) and (26), since ' ing Boolean equations: ziel-Wgr1 20 is equal to +1/2, the corresponding output increment A21 is +1 (representing AZ1=+1/2) and, therefore, in accord »(35) Y ance with Equation 20, the next R number 25 represented in the form 1+(-\V2) as 070.1000). 1n prep aration for the next operation R2 is doubled to form 2R2=2(-1/2 ) =---1 (represented `as 1+ (-1) or 00.0000). i During operation 2, the same manipulations are again repeated. Since of theA number 2R1+1 is always 0, the digit R1+1n+1 is theV opposite or complement of the digit rn and each of the remaining new digits Ri+11 . . . Rn is found as a result 30 of a left shift of the corresponding digits r” . . . r11-1. It is further seen that if r11+1 and rn have diiîerent values, AZi will be +1 or -=1 in accordance with the l or 0 value respectively of rn+2, While rn+1 and rn have the same ' the quantity values, AZi will be 0. ' 35 and is added (inthe form 1.0000) to 2R2. Since 2R2+Y1AX2=_1 is less than -1/2, the corresponding value ofv AZ2 is -l (representing AZ2=--%). subtracting AZZ and dou bling, there is obtained 2R3='0. Therefore, in the continuation of this process it is seen that during succeeding timing intervals onlyvzeroV quan; ' tities are added to the R register, since ‘ 40 Y , The applicability of these formulas may be readily veriñed by reference to the example provided in Table 3. It is seen that, during each operation z', the values of AZi and of 2R1+1 may be obtained by applying these formulas to the digits of 2R1+Y1AX1~ Computing with assemblages of computing blocks. Referring now to FIG. 2, there is shown an assemblage of computing blocks 10-1, 10-2, 10~3 . . . 1li-j and lil-j+1 interconnected for the performance of a plu rality of multiplications and/or additions of the types described hereinabove. As shown in FIG. 2, timing ~ signals TS for the sequencing of these computations are ~ Í ksupplied to each lof the computing blocks by .la source of , and also that all succeeding values of AX, are'zero. Thus it is clear that the product Y1X=+1Ái lis correctly formed Yas the stream of increments AZ1=+1A, AZ2=-%, timing signals 30, While setting signals SS for initially ì setting desired numbers into the Y and R registers of each of the computing blocks, are supplied» to each of the computing blocks by la source of setting signals 31. As indicated in FIG. 2, through cooperative action of sources 30 and 31, at the beginning of a sequence of com~ Such a summation to establish the number Y1X1 in a putational operations, signals representing predetermined register maybe accomplished, as hereinbefore stated, by numbers A1„ A2 A3 . . . Aj are stored -as Y1 numbers of computing blocks 10-1 . . . through lll-j, respec applying the AZ output increments as AY inputs to another computing block. ` tively, and signals representing predetermined numbers B1, B2 B3 . . . Bj are stored as'the R1 numbers of these Recognition formulas for formation of AZi and 2R1+1. computing blocks. The number Y1=0 is stored in com Formation of each AZ increment and the corresponding ' Y values of 2R1+1, as shown in Table 3 for example, maybe 60 puting block 10-j+1. A source of stream signals` 32 is operable during a facilitated by operation in accordance with the following computational sequence for providing signal streams rep simple recognition formulas: resenting predetermined rsequences or streams of incre-Let the digits which represent the number ments and, :as shown in FIG. 2, provides a signal stream of increments A(A0)i representing successive digits of a predetermined number A0, and also provides a stream of zliii-l-lïï’vi'l‘ä:1 _A_Ígi be designated, starting fromthe lowest order digit, as r“, 71, r2, 13 . . . rn, r11-E1, rui-2, where rn is the digit to the n'ght of the binal point and rui-1, r11+2 are` the digits to the left of the binal‘point. Thus, for example, referring back to Table 3, in the number representing: Y' 12R1+Y1A_)§1=-|-y->1" 0 Y Y Y Y ' y Y ïn-l-È Tn+v1 " _ 1` 0 ' 0 -0 :n ( 30) 0 valued increments, Which are utilized as A1Y and A2Y in puts of various computing blocks. The time at which each increment of signal stream 4is produced by source 32 is . determined by timing signals TS applied to source 32 by timing signal ksource 30, these timing vsignals serving to appropriately sequence the operation of source 32. As illustrated in FIG. 2, Y' the stream lof increments ' A(Ao), formed by source 32 is applied to the AX input ` 75 of computing block 10-1. The stream of 0 valued in ' Y 3,050,251 18 17 10-7‘ in accordance with the preferred parallel mode of sequencing is illustrated in the following table, Table 4, crements formed by source 32 is applied to the AlY and A2Y inputs of each of the computing blocks 10-1 . . . wherein the increments yformed by source 32 and block 10-1 through NLS are tabulated for eleven successive of block 10-2, and in the same way the AZ output of 5 operation - through .l0-«11 As further shown in FIG. 2, the AZ out put of computing block 10-1 is coupled to the AX input TABLE 4 PARALLEL SEQUENCING Increment supplied by Operation times 1 2 3 4 5 6 7 8 9 10 11 the corresponding bracketed quantities are: [(AeAr-l-BMAg-i-Brl, [[(AoAr-l-BiNAa-l-BdAs-l-Ba, each block 10-2 through 10-j--1 is coupled to the AX 25 It will be noted, referring to Table 4, that in ac cordance with the described parallel mode of sequencing, input of the succeeding block 10-«3 . . . through 11i-j, many computing blocks may simultaneously be main tained in operation. For example, during the sixth op eration time, all of the computing blocks 16L1 through There are at least two important ways in which the 30 lib-5 are simultaneously in operation, block 10-5 supply respectively. The AZ `output of block 10-1' is connected to the AlY input of block 10-j+1 and the 0 Valued in put stream is connected to the AZY input of block lil-j+1. operations of source 32 and of computing blocks l0 may be sequenced under the control of timing signals pro ing the ñrst or highest order digit of the final answer at the same time that blocks 10-4 through 10~1 are sup vided by source 30. rate (at a rate of one increment per operation time) by plying the second, third, fourth and íifth order digits respectively of their intermediate answers. lt is evident that in this parallel mode of operation, extremely high computational speeds are obtained even for great numbers of successive multiplications and source 32 and are applied as successive AX inputs to additions. In the ñrst and preferred mode of sequencing, desig nated the parallel mode of sequencing, successive incre ments A(A„)i `of the number A', are formed at a rapid 35 A good understanding of the speed of such operations, computing block 10-1. As hereinbefore explained, in response to the ñrst 40 relative to that found in the prior art, may be obtained by considering that special case or situation in which applied increment A(A„)1 and with only one operation each of computing blocks 10 performs only a multiplica time delay, computing block 10-1 forms the correspond tion (rather than a multiplication and an addition). This situation effectively exists when the R1 numbers are ADAl-l-Bl, this increment being applied,- as soon as it is formed, as the AX input -to block lil-2„ which in turn 45 all set in as 0 values-_that is when ing highest order digit A(A„A1-}-B1)1 of the number forms the highest `order digit A[(A0A1+B1)A2+B2]1 of the number (AoAl-i-BQAz-i-BZ. ' In the continuation of In this situation B1=B2=B3 computing block . . . lit-‘l forms A(A0A1-|-O) ' this process, each successive computing block forms the or A(ADA1) and in similar fashion computing blocks highest order digit of the intermediate answer associated lil-2, lità’ . . . lil-j form, respectively, -A(A„A1A2), therewith and applies this digit to the succeeding com A(AOA1A2A3) . . . A(AQA1A2A3 . . . Aj). 'Th1-1S, each puting block, so that after a delay of only y' operation computing block performs only a multiplication. The times from the application of the highest order digit of Vfollowing table, Table 5, compares the time required to the number A0, the highest order digit of the ñnal answer complete a plurality of multiplications, as performed by is formed by. computing block lll-j and is applied as a 55 either corresponding plurality of cascaded computing AY input to block 10~j-l-l for accumulation therein. blocks as shown in FIG. 2, or by a corresponding plu It is clear that in this operation, digits of the final an rality of conventional multipliers. It is assumed that the swer are formed by block 10-j at the same rate at which multiplications are carried out to n significant digits. digits of the input number A0 are applied, each comput ing block~ contributing a delay of only one operation TABLE 5 time between the application of an input digit and the 60 formation of ra correspondingly scaled output digit. This Number of operation times feature is common to »both modes of sequencing. Number j oí required for completion of In the preferred mode of sequencing, however, because multiplîca- of the rapid rate at which input digits A(A0)i are being r» tions per applied, a type of parallel loperation is obtained in which” 65 eventually all or nearly all of the computing blocks are sent into simultaneous operation so that earlier comput ing blocks are operating upon lower `order digits at the same time that later computing blocks are forming higher order digits. This parallel type of` sequencing is 70 best illustrated by considering a speciiic example. Assume hereafter that in FIG. 2, only -ñve computing blocks are cascaded (j=5) and that computation is to formed multiplications Cascaded computing Ordinary multipliers blocks j=1 n n ]:=2 n+1 2n J=3 j=4 n+2 nfl-4 j=n n-l-n 37» 47: n2 be carried out to six significant digits. The way in which digits are formed by source 32 and blocks 10-«1 . . . 75 The great speed disadvantage of conventional multipliers 3,050,251 2@ source 30 will be provided at a later point in the speciñca arises from the fact thatin each such multiplier an entire n digit multiplication must be completed before the result tion, Detailed description of specific embodiments of Y computing blocks 10 and sources 30,731 1and 32 will be can be utilized in a succeeding multiplier (since eachrdigit provided also. ' l is subject to change until the multiplication is completed), while in contrast with the cascaded computing blocks of 5 However, it is useful at this >time to generally pointy the -present invention, the digits -formed `are not subject out one suitableA form of source 32, which acts as a pri' tochange and 4are immediately utilizable by succeeding mary source of input increments. Although it will be computing blocks. come clear that source 32 may have many forms well Y Referringrnow to the second principal mode of seknown to the art, in its preferred form source 32 prin~` quencing, the operations of source 32 and computing 10 cipally `comprises a plurality of computing blocks 10, so blocks 10-1 _ . . through lil-6 (it being assumed as be- operated as to convert numbers periodically stored there-r fore that j=5), in this mode of sequencing input increments A(A0)1 are supplied by source 32 at a slow enough rîateyso that there is no parallelvoperation of the comput- in into required sequences of increments. Thus, for example, as shown in FIG. 2, source 32 is seen to include a computing block 10-0 which is operable ing blocks. Y _ . _ Y 15 under the control of setting signals SS provided by source " In this mode of sequencing, which is referred to hereinY after >as a serial lmode 4oÍ sequencing, after the increment 31 andV timing signals TS provided by source 32 to pro vide the sequence of increments A(A0)1. YAs indicated in A,(A0)1, represen-ting the highest order digit ofthe number FIG. 2, only 0 valued increments kare applied to the AXV - A0 is applied, formation and application of a second in- inputs of block l0-0. The value initially set into vthe R put digit is delayed until all operations upon the tirst 20 register of the block at the'beginning of each computa digit have been completed and the resultant highest order tional sequence is R1=A0 (set in, in the form 2R1=2A0). digit of the final result is formed by block lil-5. In con- The initial values of Y1 and the values of the AY incre tinuing operation, in the same Way, each of the successive ments are not material in this application. However, as input digits is applied ,and each of the corresponding reshown in FIG. 2, AlY and A2Y have 0 values and Y1=0. sultant digits is produced in response thereto. In kthe 25 Since for computing block 10-0, R1==A0 and AX1=0, sequenti-al mode of operation' the computing blocks opby substituting these values in Equation 28 developed erate one after the other, rather than`in any parallel or hereinabove, there is obtained the resultant equation; simultaneous operation. This is illustrated in the follow- l ing table, Table 6, which present-s, for the described serial n _ y ZAZigRIÈAO mode of operation, the increments formed by source 32, 30 and blocks 10-1 through 10-5, during thirteen successive . operation times, it being ‘assumed las before that 1”:5. (38) z-=1 . Y I A . . from which 1t can b“ inferred that' It is also assumed that B1=B2 . . . =B5=0, so that AZ1=A(A0)I only simple multiplications (rather than combined multi- Y ~ (39) . -_ ' _ plic'ations and additions) are being performed, and it is as- 35 thus demODSÍI'fltlllg that ‘block 1.0-0 111 OPel'aÍlOD Wïll PIO lsnmed that input increments A(A0)1 .are applied every duce the requlfed Sequellee 0f meïjemeïlls A(Ash, l'ePfe' ' sevenoperation times during an operational sequence so Senlïmg the Dumber Ao mltleuy Set Inte fhe'R register. - that suii‘icient time is allowed for the completion of operations upon one input digit before application of the next input digit. ' f , Y AS further ShOWIl in FIG- 2, IlChe Stream 0f 0 Valued increments supplied by source 32 is provided by a source , 40 unit 40. It will be appreciated that unit '40 may comprise " TABLE 6 SERIAL SEQUENCING n supp e Operation times y 1 _ 2 ' s 4 5 6 7 Source 32_-___ MAG); Block lll-1_-. _______ __ AtanAl); Block 10-2___ Block nts--- ___ A(AoA1A.z)1 ' »-.Antoni/ina» Block 10-'4- __ l ___ _____________________________________ __ A(AuA1AzA3A4)i ` Operation times Incîaräegts supp e ~ y ' Source 32 s s 1o 11 12 13 A(Ao)n Block 10-1 A(A0A1)s B1oßk1a2__'______' _______________ Block 10-3- ................... -_ __.. ‘ Y _ ___ Ammin), _ A(AuA1AzA3)z :Block 10-4- ____________________________________ _ A(AOA1A2A3A4)z Block 10-‘3 ...... -_ .................. -_ MAoÀiAzAeAtAs): through 10a-j, as `shown in FIG. 2, is now completed. l a computing block 10 operated in the same manner as block 10-0, but with 1R1=0 set in as an initial value. However, in the speciiic form of the invention described - Detailed description of the manner in which Vsuch sequenc hereinbelow, constant valued increments are more easily Y Qualitative discussion of the described parallel and serial modes of sequencing of computing blocks 10-1 ing is ‘obtained under control of timing signals supplied by 75 generated. »In the specific form -of _the invention to be 3,050,251 21 22 described, any increment may be represented by two ' Restating this in mathematical terms, it will be demon strated that for block 10-2 the iinal value Yn+1 of the bilevel voltage signals U and V. Signal U at its high and low voltage levels (voltages VH and VL) represents the plus (-1-) and minus (_) values of an increment while signal V at its high and low voltage levels represents Y number at the end of a sequence of operations is: (41) the 1 and 0 values -of the increment. Thus, as shown in FIG. 2, constant +0 valued increments are represented i=1 by signals U0 and V0 at their high and low levels, respec tively, signal Uo being formed on a conductor connected yto a source (not shown) of high voltage VH and signal 10 V0 being formed on a conductor connected to a source (not shown) of low voltage VL. Complementary signals U0 and V0 may be similarly formed. Before beginning detailed description of speciñc em , . From a consideration of FIG. 3, it is clear that for block 10-2 . ‘ AY,=AZ,-|-Az’1 (42) Where `as indicated in FIG. 3, AZ, is the designation of the output increments produced by block 10-1 and AZ’1 is the designation of the output increments pro duced by block E10-1’. Combining Equations .40 and 42 bodiments of block 10 yand sources 30, 31 and 32, one 15 there is obtained: further important example of computation with assem blages of computing -blocks will be described. In this example two streams of increments are elîectively multi plied by one another to form a stream of increments rep resenting their product. More particularly, a stream of 20 increments, A(A0)i, representing the digits of a number B0, to form -a resultant stream of increments A(AUB0)„ representing the digits of the product AÜBO, these incre ments being accumulated to store the product A0B@ in a register. 25 , From »a consideration of Equation 20 and the substi tution of appropriate input quantities, it is seen that for block 10-1: Referring now to FIG. 3, there is shown an assemblage of computing blocks 10-1, 10-1', and lil-“2. intercon nected for performing the abovedescribed multiplication and similarly for block 10-1': Y( of streams A(AD)1 and MBO), which, as shown in FIG. 3, -are applied thereto by a pair of computing blocks 30 IiP-0 and 1li-0', respectively, contained in source 32. All computing blocks «are sequenced under the control of Substituting these values of EAZ, and EAZ’1 in Equa timing signals TS provided by source 30 While appropri tion 44 and expanding, there is obtained: ate signals SS lfor utilization in the setting of initial con ‘7l 9?, ditions into the computing blocks are provided by source 31. z= l î=1 Yn+1=ZAYi=Z(Áo)iA(Bo)i-i‘(Bo)iA(Ao)i As shown in FIG. 3, blocks 10-0 and 10-0’ are op erated -in the manner hereinbefore described to act as (47) sources of the sequences of increment A(A0)1 and A(B0)ì, respectively. The summation on the right side of Equation 47 may To this end, initial values of R1=A0 and 40 readily be evaluated. By rearranging terms there is R1=B0 are set into the R registers of blocks 10-0 and lil-0', respectively, with O valued increments being ap obtained: .plied as the AX inputs to these blocks. KHFÉ‘ÍAYFÉIMM#Marwua/treuil Increments A(A„)1 are applied to the AlY input of block 10-1 and to the AX input of block lll-1’. Simi 45 _ ~~ larly increments A(B„)1 are applied to the AIY input «Aarem <48) of block `10--1’ and to the AX input of block 10-1. Zero which, from a knowledge of ñnite differences is rec valued increments lare applied to the AZY inputs of blocks ognized to be equivalent to the Storm: ' 10-1 and 10-1'. The AZ outputs of computing blocks 10-1 and 10-1' are connected to the A1Y and A2Y in 50 (49) puts, respectively, of computing block 10-2. As shown in FIG. 3, within block v10-2,-the increments AZ, and AZ',` supplied by these outputs of blocks 10-1 and 10-1’, Where A(A0B0), is the increment to the product Aoßß at the ith interation. It is, therefore, clear that respectively, are summed by summer 18 to produce cor responding total AYi increments which as hereinbefore explained, are accumulated in the Y register of block 10-2. As indicated in FIG. 3, the initial value set in ofthe Y number is Y1=0, so that the value of the Y num ber after n iterations is 55 (50) and, therefore, by substitution in Equation 49 the re ` quired result is obtained, namely, that: 60 ' (40) n ZA (AoBo) i=AoBo z=1 7l Yn+1=ZAYi=ÁoBo i=1 (51) Understanding of the manner in which such a multipli As shown in FIG. 3, zero valued increments are applied cation of two streams of increments is carried out will be to .the AX input of block 10-2 and the initial value set in of the R number is R1=O. 65 facilitated Áby consideration of the numerical example provided below in Table 7. Y ` _ It can now bre-demonstrated that the assemblage of In connection with Table 7, it is assumed that the num- ` computing blocks 10-1, 10-1’ and 10-2, shown in FIG. bers A0 and B0, Which are to Ibe utilized, have the values 3, functions to multiply the numbers A0 and B0 repre sented by the two input streams of increments A(A0)¿ Ao=-l-3%4 and B0=---7A6, .the quantities 2An=2(3%4), and A(B0)1. More particularly, it will be shown that 70 therefore, being initially set into the R register of block 10-0, and the quantity 2B0=2(--%6) being initially set _ the stream of increments AYi, produced by summer d8 into the R register block 10-0’. Table 7 shows quantities in block 10-2, represent the digits of the products AUBO and, therefore, the iinal number Yn+1 accumulated in the „s appearing -in or associated with blocks 10-0, ¿l0-0', 10-1, lil-1', and v10-2 (as shown in FIG. 3) for the first Y register of block 10-2 at the end of an operational sequence will be the product AÜBG. 75 «six computational operations of each of the blocks.

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