close

Вход

Забыли?

вход по аккаунту

?

код для вставки
Nov. 6,- 1962
D. HALTON
3,063,016
BINARY (IOUNTING CIRCUITS
Filed Sept. 8, 1961
2 Sheets-Sheet 2
LEFT}
INVENTO
DONALD HALTON .
BY
3% Z
?rrx
>llnited States 1. atent @?fice
1
3,dh3,®iti
Patented Nov. 6, 1962
2
3,063,016
BINARY COUNTING CIRCUITS
Donald Halton, Liverpool, England, assignor to Auto
matic Telephone & Electric Company Limited, Liver
pool, England, a British company
Filed Sept. 8, 1961, Ser. No. 136,839
Claims priority, application Great Britain Sept. 24, 1960
1 Claim. (Cl. 328-42)
sistor, which restricts the voltage swing on the respective
output leads 0L1 and 0L0 to limits of approximately 6
volts negative and earth potential. Thus, in the “1” con
dition of the circuit, the output lead of the “1” side, 0L1,
is at approximately 6 volts negative, and the output lead
01.0 of “0” side is at approximately earth potential, while
in the “0” condition of the circuit the output potentials
are reversed.
The circuit is intended to be driven by output signals
The invention relates to binary counting circuits.
The type of counter is well known in which the bin
ary element in each stage is controlled by a gate circuit
which has a number of inputs equal to the number of
preceding binary stages, each input being fed from a
10 from coincidence gates which have the same output volt
age conditions as the toggle circuit, i.e. the “signal on”
condition is 6 volts negative and the “signal oil” condi
tion is earth potential. These driving signals are applied
different one of the preceding stages. This type of cir 15 to the 1 and 0 sides of the toggle circuit at leads 1L1 and
IL0 respectively. The driving signals at the input of the
cuit has the great advantage of speed in operation, because
toggle circuit are, however, subject to the control of a
the operation of any one stage is not dependent upon the
strobe pulse source which is connected to each side of
accumulated time delays inherent in the binary circuits of
the toggle circuit via diodes D1 and D2 at leads SL1 and
all the preceding stages. There are, however, certain dis
advantages associated with a counter circuit of this type 20 SLO respectively, and also of feedback signals which are
taken from the two output leads of the toggle circuit to
employing more than a small number of stages. For ex
the opposite input leads via further diodes D3 and D4.
ample, the size of a gating circuit increases as the digital
The strobe pulses provide an accurate timing signal to en
signi?cance of its stage increases, and apart from the ditli
able the operation of the toggle circuit to take place at
culty of making a satisfactory conventional diode gate
with many inputs, the di?’iculty of mounting such gates 25 accurately de?ned instants, while the feedback signals fed
via the diodes D3 and D4 are arranged to prevent an input
signal from being eitective when it is applied to the par
ticular side of the circuit to which the latter has already
physically is soon encountered. In addition to this, the
load o?ered to the output circuits of the early stages in a
large counter can become very great, because of the large
number of gates which have to be driven, and the load
been set, and also to avoid current drain on the strobe
of the succeeding even-numbered element are combined
in a coincidence gate circuit, the output of which is fed
to coincidence gate circuits controlling the next pair of
elements through a device which presents a low imped
ance output to said last-mentioned coincidence gate cir
cuits.
ceived at lead SL1 is coincident with the termination of
the driving pulse at lead 1L1, and is a positive-going pulse,
i.e. lead SL1 is momentarily changed in potential from 6‘
volts negative to earth potential. The strobe pulse there_
fore backs o?? diode D3, and the positive peak of the pulse
di?erentiated by the capacitor C1 and applied to the base
supplied by each stage of the counter is, in general, dif 30 pulse source under these circumstances.
The circuit operates as follows. Assume that the cir
ferent from the load supplied by each other stage.
cuit is in the “0” condition with transistor TXl conduct
It is the object of the invention to provide a binary
ing. If an input signal is applied to lead 1L1, the po
counting circuit capable of operation at high-speed in
tential of this lead becomes 6 volts negative for the dura
which the above disadvantages are obviated.
According to the invention, in a binary counting cir 35 tion of the input signal. With no strobe signal present,
lead SL1 is also at 6 volts negative, and so is the feed
cuit including a plurality of cascade-connected bistable
back path from the collector of transistor TXO. While
elements each of which except the ?rst element is con
these conditions exist, the capacitor C1 is enabled to
trolled by all the preceding elements and by pulses applied
charge, and its charging time is arranged to be shorter
substantially simultaneously to all the elements, the out
puts from the set sides of an odd-numbered element and 40 than the input signal length. The strobe pulse next re
of transistor TXl causes the latter to be cut oit.
In the counting circuit according to the invention only
The
negative peak of the differentiated strobe pulse is blocked
by diode D5, and is therefore ineffective at transistor TX}.
the binary circuits even in a counter With a very large
number of stages, While the gate circuits each have a very 50 The normal toggle action of the circuit takes place to re
a small number of di?’erent loads is supplied by each of
small number of inputs, again even in a very large counter.
The invention will be understood from the following
description of one embodiment, which shows a binary
counter having 16 stages, and therefore capable of a
total count of 65536. It should be read in conjunction
with the accompanying drawings comprising FIGS. 1-3,
p of which
FIG. 1' shows the circuit of a typical toggle circuit suit
able for use as one stage of the counter,
FIG. 2 shows the circuit of a counter according to the
invention, in symbolic form, and
. FIG. 3 ‘is a timing chart illustrating the operation of
verse the condition of the two transistors.
If a further driving pulse is applied to lead 1L1 when
the toggle circuit is in the “1” condition, i.e. when tran
sistor TXO is conducting, there is no change in potential
at lead ILl, because the latter is held at earth potential
by the feedback path from the collector of transistor
TXtP. Diode D1 in the strobe input lead is backed off and
diode D3 in series With the emitter/collector path of
transistor TXt) presents a low impedance to signals of 6
volts negative applied to lead 1L1. The state of charge
of capacitor C1 is therefore unaffected by such a signal,
and because its left-hand plate is already at earth poten
tial, a subsequent strobe pulse is not transmitted to the
base of transistor TXi. It will be appreciated that the
65 main advantage of this arrangement resides in the fact
part of this circuit.
The toggle circuit shown in FIG. 1 is a conventional
bistable circuit comprising two grounded emitter tran
sistors with collectors and bases cross—coupled, the tran~
sistors being arranged to conduct alternately. In the “1”
condition of the circuit, transistor TXl is cut off, and
transistor TX(} is conducting, while in the “0” condition
transistor TXl conducts and transistor TXtP is cut off. A 70
clamping circuit is provided in the collector of each tran
that a strobe pulse source can be connected to a large
number of toggle circuits without being overloaded, be
cause the load presented to the pulse source at any instant
will comprise only those toggle circuits which it is re
quired to switch from one condition to the other.
The toggle circuit shown in symbolic form in the re
maining drawings are all of the type shown in FIG. 1.
3,063,016
3
To simplify the drawing, however, only the inputs for
the driving pulses are shown, i.e. leads 1L1 and IL0 of
the circuit FIG. 1, the strobe input leads, feedback leads
and output leads 0L1, 0L0 being omitted. In the tog
gle circuit symbols designated A, B, C etc., the input leads
to the “l” and “0” sides are shown in the conventional
way marked with arrow heads and entering from the left
hand side, while the output leads extend from the right
hand side. The coincidence gates of these drawings are
also shown by the conventional symbol of a circle con 10
4
occurs on the occurrence of the 14th driving pulse and its
following strobe pulse, and the condition for applying an
input to the follower circuit F3 occurs on the next, i.e. the
15th, driving pulse.
The sequence of operations continues in a similar man
ner to that described, the output of each odd-numbered
follower circuit F1, F3 and F5 providing a drive for the
following pair of toggle circuits until the seventh and
eighth toggle circuits are reached. The even-numbered
follower circuits F2, F4 and F6 always come into opera
tion one strobe pulse earlier than the corresponding fol
lower circuits F1, F3 and F5, at the appropriate stage
of the count. When toggle circuit H is ?rst set, an input
AND gates are employed. In addition to toggle circuits
is applied to the “1” side of toggle circuit X, through a
and gates, the only other elements used are pulse am
gate fed from the “1” output of toggle circuit H, the “1”
pli?er circuits, or, more accurately, impedance conversion
output of toggle circuit G, which is on the point of being
circuits, which are of the cathode follower or emitter fol
reset, and from the output of follower F6 over lead f6.
lower types. These are shown with the conventional am
Although toggle circuit X is thus set at the instant of set
pli?er symbol of a triangle with its apex indicating the di
ting toggle circuit H each time toggle circuit‘H is set,
rection of ampli?cation and their function is to present
there is no danger of subsequent toggle circuits driven
20
a low impedance output to the subsequent gate circuits
from the output of toggle circuit X, being operated pre
where two gate circuits would otherwise be connected
maturely, because the delay introduced in the toggle circuit
directly in series with one another.
itself prevents an output from being obtained from it until
The counter operates as follows. Assume that all the
after the strobe pulse which causes it to be set has ter
toggle circuits are initially in the “0” condition. The
minated. Toggle circuit X includes a feedback circuit
?rst driving pulse appearing on lead DPL is applied to
which causes it to be reset by the strobe pulse next occur
the input leads of both sides of the toggle circuit A. The
ring after it has been set. The introduction of this toggle
pulse causes this toggle circuit to assume its “1” condition
circuit thus effectively eliminates misoperation of the cir
upon the occurrence of the following strobe pulse, and
cuit by the build-up of time delays which might occur if
the next driving pulse on lead DPL causes toggle circuit
taining a number representing the number of input signals
required to open the gate. In the present circuit, only
A to revert to the “0” condition upon the occurrence of
the next strobe pulse. This second driving pulse on lead
DPL will also be applied to the two sides of toggle cir
cuit B, since the two AND gates controlling the input to
this toggle circuit will at that instant be conditioned by
the output of the “set,” or “1,” side of toggle circuit A,
and the second strobe pulse will therefore also be effective
in setting toggle circuit B to its “1” condition. At the in
stant that toggle circuit A takes up its “0” condition and
toggle circuit B takes up its “1” condition, output sig
nals from these two toggle circuits will be applied to the
follower circuit F2 through its input gate, although the
output of this follower circuit is, in fact, ineffective at this
stage of the count.
The next driving pulse on lead DPL again causes tog
gle circuit A to be set to the “1” condition on the occur
rence of the ensuing strobe pulse, and this results in an
more than three follower circuits were used in series.
The second half of the counter, toggle circuits J, K
and so on, can employ only a single chain of follower
circuits, F7, F8 and F9, corresponding to follower cir
cuits F1, F3 and F5 in the ?rst half of the counter, be
cause the build-up of time delays does not become seri
ous until more than three follower circuits are connected
in series. If more than sixteen binary stages were used,
however, a further toggle circuit corresponding to toggle
circuit X would have to be employed at the end of each
section of eight binary stages, and further follower cir
cuits corresponding to followers F2, F4 and F6, each
coming into operation one strobe pulse earlier than the
follower circuits corresponding to F1, F3 and F5, would
have to be provided to drive each toggle circuit such as X.
The timing of the operation of various parts of the
circuit will be better appreciated from the timing chart
of FIG. 3, which, although it does not include all the
stages of the circuit, shows sufficient for the timing of
circuits A and B to the follower circuit F1. The output
the operation to be understood. The various lines of this
from this follower circuit is also ineffective at this stage,
and in the meantime, of course, the input to the follower 50 ?gure correspond to those elements of the circuit which
are similarly designated, the two levels for each line rep
circuit F2 has been terminated. The fourth driving pulse
resenting the set and reset condition of the toggle circuits,
on lead DPL is, however, now applied to toggle circuits
and the “signal on” and “signal off” conditions for the
A, B and C, the input gates for toggle circuit B being
outputs of the follower circuits. In the former case, the
conditioned by the output of the “1” Side of toggle cir
cuit A, and the input gates to toggle circuit C being con 55 set, or “1,” condition of the toggle circuit is represented
by the line being at the lower level, and the reset, or “0,”
ditioned by the output of the follower circuit F1. This
condition is represented by the line at the upper level.
fourth driving pulse, in conjunction with the ensuing
Similarly, for the follower circuits, the line at the lower
strobe pulse, causes toggle circuits A and B to be reset
level represents the “signal on” condition and at the upper
to their “0” conditions, while toggle circuit C is set to
60 level represents the “signal off” position.
its “1” condition.
It will thus be seen that a counter circuit has been pro
The ?fth, sixth and seventh driving pulses are similar
vided
in which the control gates have a maximum of
in effect to the ?rst three, although toggle circuit C is in
three inputs, and in which only a small number of gates
the set condition when these pulses are received. The
is fed by any one toggle circuit.
eighth driving pulse ?nds toggle circuits A, B and C in
I claim:
the set condition, and follower circuit F1 will also be 65
A binary counting circuit comprising a plurality of cas
producing an output. The next strobe pulse will therefore
cade-connected bi-stable elements each of which except
result in the resetting of toggle circuits A, B and C, and
the ?rst element is controlled by all the preceding ele
the setting of toggle circuit D, which has all three inputs
ments and by pulses applied substantially simultaneously
to each of its input gates energised. There is, at this
stage, no input applied to either of the followers F3 or 70 to all the elements, a plurality of coincidence gate cir
cuits, a plurality of circuit devices, the outputs from the
F4, the former of which requires toggle circuits A, B, C
set sides of an odd-numbered one of said elements and
and D to be in the set condition simultaneously, and the
of the succeeding even-numbered one of said elements
latter of which requires toggle circuit A to be reset, and
being combined in one of said coincidence gate circuits
toggle circuits B, C and D to be in the set condition be
the output from which is fed to further coincidence gate
fore it receives an input. This last-mentioned condition
output being applied from the “1” side of both toggle
5
8,063,016
circuits controlling the next pair of elements through one
of said circuits devices Which presents a low impedance
output to said further coincidence gate circuits and the
output from the reset side of the ?rst element and the
output from the set side of the second element and the
outputs from the set sides of the subsequent pairs of ele
ments up to and including the nth pair are each combined
pair-by-pair in a separate coincidence gate circuit, the
separate coincidence gate circuits being connected in cas~
cade by further of said devices and an additional bi-stable 10
element controlled by the separate coincidence gate cir
cuit associated with the nth pair of elements, the output
5
from the set side of said additional bi-stable element being
applied to the next succeeding odd-numbered bi-stable
element.
References Cited in the ?le of this patent
UNITED STATES PATENTS
2,774,868
2,816,223
Havens ______________ __ Dec. 18, 1956
Nelson ______________ __ Dec. 10, 1957
2,853,238
2,956,181
Johnson _____________ __ Sept. 23, 1958
Norman ____________ _._ Oct. 11, 1960
Документ
Категория
Без категории
Просмотров
0
Размер файла
476 Кб
Теги
1/--страниц
Пожаловаться на содержимое документа