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Патент USA US3068462

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Dec. l1, 1962
3,068,452
G. P. SARRAFIAN
MEMORY MATRIX SYSTEM
Filed Aug. 14, 1959
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12 Sheets-Sheet 12
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3,063,452
George P. Sarralian,
l't/iEll/iÜRY
Dailas,
MATRiX
Tex., assigner to Texas lnu
struments incorporated, Dallas, Een., a corporation of
Delaware
Filed Aug. le, i959, Ser. No. 333,743
d Claims. (Cl. Mii-«1174)
The present invention is disclosed in the copending ap
plication Serial No. 784,358 of George Philip Sarratian,
Patented Een. ii, lä?ä
FIGURE 2 illustrates the details of one tier of the stor
age core matrix of the memory system;
FÍGURE 3 shows how the storage core matrix is di
vided into sections;
FÍGURE 4 shows the electrical waveforms used in the
memory system;
FIGURE 5 illustrates the details of the switch core
matrices used for selecting and driving the input conduc
tors of the storage core matrix;
FIGURES 6 and 7 show in block form the details of
Charles L. Kettler, and George T. Baker. in this co
pending application, the advantages of having a memory
the index register decoders, which, in response to binary
numbers stored in the index registers, will select input
into which more than one word could be simultaneously
entered or read out are pointed out. This feature allows
mo-re rapid handling of digital data in that more data can
be transferred into and out of the memory at one time.
double length words need to be stored in the memory to
conductors of the switch core matrices and thereby select
addresses in the storage core matrix;
FÃGURE 8 illustrates in block form the details of the
X and Y drivers, which drive the input conductors of the
switch core matrices;
FlÍGURE 9 illustrates one of the index registers in
maintain a desired accuracy.
block form;
Also the system lends itself ideally to operations where
FlGURE 10 illustrates another of the index registers
The memory is comprised of a plurality of tiers of two 20
in block form;
dimensional coincident current matrices. Digital words
FEGURE 11 illustrates in block form the index register
are stored with one digit in the same relative position in
selection logic, which sto-res commands selecting one of
each tier. rThe location or address in the matrix ‘for a
the index registers and applies the required signals to the
word to be read in or read out is selected by the column
index registers and to the index register decoders;
and row selection and the coincidence of currents at the
FIGURE l2 illustrates in block form the read in cir
intersection of the selected column and row. A plurality
cuits, which control the storing of information in the
of inhibit windings are provided in each tier, each linking
storage core matrix;
the cores of a dilterent part of the tier. These inhibit
FÍGURE 13 illustrates in block form one of the read
windings control what digit will be stored at the selected
address in the respective tiers. By selecting a plurality ot 30 out circuits, which receive the information read out from
the storage core matrix;
the rows and one of the columns in each tier, a plurality
FlGURE 14 illustrates in block form the command
of addresses in memory can be selected. lf these selected
logic for submemory selection, which stores commands
addresses are chosen such that each address is controlled
to read information out of or into selected sections of the
by different sets of inhibit windings, two words or both
storage core matrix and applies to the difîerent parts of
halves of a double length word may be stored simultane
the memory system the signals required to carry out these
ously.
commands; and
The memory is provided with a plurality of output
FIGURE 15 shows in block form the memory program
windings in each tier, each linking the cores of a ditterent
mer which generates the waveforms necessary to carry out
part of the tier. Words are read out of the matrix by
the reading of information out of and into the storage
selecting a column and row in each tier. By coincident
core matrix.
current the word address at the intersection of this column
The memory unit can best be understood by referring
and row will be selected and the word stored at this
to the block diagram of the entire memory unit shown in
selected address will be read out on the respective output
FIGURE 1 in conjunction with the FIGURES 2 through
windings. By selecting a plurality of rows and a column,
l5 illustrating details of the parts of the memory unit.
a plurality of intersections in each tier will receive coinci
The storage core matrix, designated by the reference num
dent current and thus a plurality of addresses may be
her Stil in FÍGURE 1, comprises a stack of 12 tiers of
selected. if these plurality of addresses are selected such
cores, each tier comprising a two dimensional coincident
that each is in a part of the memory which is read out
current matrix being just like the tier illustrated in FiG
in each tier by different sets of read out windings, then a
URE 2.
plurality of Words may be read out simultaneously.
Assuming for purposes of description that the tiers of
The memory is divided into sections with a plurality
cores are stacked vertically, then 12 bit binary words are
of different addresses comprising each section. A corn
stored in the matrix with each bit of each word being
mand signal applied to the memory system will select in
which of the sections of the memory the selected address .,
stored in a corresponding core of a different tier in the
will be. An index register controls the selection of the
particular address in the selected section. When a plu
rality of addresses are selected for read out or storage,
the plurality selected addresses will always be in different
sections. The index register controls the selection of the
plurality of addresses so that they occupy the same relative
position in each section. This feature is desirable, be
matrix, the corresponding cores being the cores which
are vertically aligned in the matrix. The storage cores of
the matrix are of the ferrite type having square hysteresis
loops and thus are capable of assuming two stable states
and require a pulse of predetermined size and direction
cause it results in the two halves a double length word
core.
always occupying the same relative position in two ditîer
ent sections of the memory and thus simplifies the prob
lem of keeping track of the double length word.
Further objects and advantages of the present invention
will become apparent as the following detailed descrip
tion of a preferred embodiment unfolds and when taken
in conjunction with the drawings wherein:
FIGURE 1 shows a block diagram of the memory
system;
to switch them from one state to the other. The state
which the core assumes represents the lbit sto-red in the
Each tier of cores comprises a total of 256 cores and
_ thus the matrix has a capacity of 256 l2 bit words. The
memory is divided vertically into two halves, storing 128
words each and designated the B section and the C sec
tion. The C section is further divided vertically into
four equal parts` storing 32 words each and designated aS
the CA, CB, CC and CB sections. The relative posi
tions of these sections on each tier is shown in FIGURE 3.
As shown in FIGURE 2 each tier of the matrix has 16
assai-sa
4,
columns of cores and 16 rows of cores. The storage cores
are designated generally by the reference number 421.
s.
address or word position in which the binary word to
be stored is in the CA, CB, or B section, the Z1 driver
will apply a current wave form 319, shown in FIGURE
A different one of a series of conductors designated X1
through X16 passes through each column of cores. A
4, to the Z1 conductor of those tiers where a ZERO is to
ditîerent one of a series of conductors Y1 through Y16 C21 be stored in the selected core. if the binary word is to
passes through each row of cores. As groups, the con
be stored in the CC or CD section, the Z2 conductors of
ductors X1 through X11,` shall be referred to as the X con
those tiers in which the selected core is to store a ZERO
ductors and the Y1 through Y16 conductors shall be re
will receive the current wave form 319 from the Z2 drivers
ferred to as the Y conductors.
304,. The wave form 3l9 is applied to the selected Z
To select one of the cores to be switched to the oppo
site state, current pulses are applied simultaneously to one
of the series of conductors X1 through X11,- and to one
of the series of conductors Y1 through Y1G. The current
pulses are chosen to be of such size, that the core which
is commonly threaded by both the X conductor and the
Y conductor will receive sui'iicient power from the corn
bined currents liowing in the X conductor and the Y
conductor to cause the commonly threaded core to change
its state, provided the current pulses have the right polar
ity. The current pulses are chosen to have a small enough
magnitude so that the cores which are threaded by only
one of the selected X or Y conductors do not receive suf
ñcient power to cause them to change their states.
Since all of the tiers are identical, each tier will have
conductors X1 through X16 and Y1 through Y16. All of
the X conductors having the same designation are con
nected together in series and all of the Y conductors hav
ing the same designation are connected together in series.
Each series connected group of conductors which have
the same designation shall be referred to by that designa
tion.
When a word is to be read out from or stored in the
storage core matrix, the switch core matrices, designated
302 in FIGURE l, select the desired group of like desig
nated, series connected X conductors and the desired
group of like designated, series connected Y conductors
and apply simultaneously to each selected series connected
groups, a current wave form lili; shown in FlGURE 4.
The wave form 318 comprises a positive pulse 322 and a
negative pulse 323. ‘When the wave forrn is applied to a ‘A
selected series connected group of X or Y conductors it
is applied with such a polarity that the current of the
positive pulse flows in these conductors in the direction
of the arrows in FIGURE 2. The pulses 322 and 323
are of insuthcient amplitude alone to cause any change of
state in the cores but the core in each tier which is corn
monly threaded by the selected X and Y conductor will
receive enough power from the pulses 322 ilowing in both
conductors at the same time that the wave form 318 is
applied to the selected X and Y conductors. The wave
torni
comprises an elongated positive current pulse
324i which is applied to the selected Z conductors in the
direction indicated by the arrows in FlGURE 2.
FIG
URE 4 illustrates the time relationship between the wave
forms 31S and 2&9. As shown in FIGURE 4, the cur
rent pulse 32d starts in the interval between the pulses
322 and 323 and lasts until after the pulse 323. After
the pulses 3122 have been applied, the selected core in
each tier will be in its ZERO state. Then when the pulses
323 are appiied, the selected core in each tier, which
does not have a pulse 324 applied on its Z conductor, will
be switched from its ZERO state to its ONE state. The
selected cores in those tiers which do have pulses 324
applied on the appropriate Z conductors will not be
switched, because the current flowing in the Z conduc
tors will cancel out part of the current Íiowing in the se
lected X and Y conductors so that the selected core does
not receive sutiìcient power to be switched to its ONE
state. Thus, by pulsing or not pulsing selected ones of
the Z1 conductors if the word is to be stored in the B,
CA, or CB section, or by pulsing or not pulsing selected
ones of the Z2 conductors if the word is to be stored in
the CC or CD sections, any binary word can be stored
in any selected address.
By using both the Z1 and Z2 conductors, a 24 bit word
or two l2 bit words can be simultaneously stored in the
core matrix. rthe selected address in the matrix for one
of the l2 bit words will be in the CA or CB section of
the matrix and the selected address -for the other word
will be in the CC or CD section or the matrix. The
cores of both selected addresses -rnust be threaded by the
same series connected group of X conductors. To carry
out the operation the switch core matrices will apply the
current wave form Slis? to »one of the Y conductor groups
Y1 through YB and one of the Y conductor groups YQ
through Y16 and one of the X conductor groups X1
through X8. Thus, there will be two addresses at which
the X and Y conductors to cause that core to switch to a
the selected X and Y conductors intersect and at these
first predetermined state. This ñrst predetermined state so two intersections two l2 bit words will be stored. When
is used to store the binary numeral ZERO and accord
a 24 bit word is stored in the matrix, the two halves
ingly this first predetermined state will be referred to as
of the word are stored in diiierent positions in the man
the ZERO state. The opposite state of each core is used
to store the binary number ONE and hence this opposite
state shall be referred to as the ONE state. When the
pulses 322 are applied, some of the selected cores may
already be in their ZERO states. These cores will be un
affected by the pulses `§22 and thus after the pulse 322,
all of the selected cores will be in their ZERO states.
Following the application of the pulses 322, the pulses
3213 will be applied to the selected X and Y conductors
and as a result, all of the selected cores would tend to
be switched to their ONE states so that the binary nurn
ner described for two l2 bit words.
In the case of a 24
'Dit word, the CA and CC sections should be elected be
cause of the organization of the read out circuits.
Each tier of the rnatrix has three S conductors, an S1,
and S2 and an S3 conductor. The S1 conductors thread
the cores of the CA and B sections ot the matrix. The
S2 conductors thread the cores of the CB section of the
matrix, and the S3 conductors thread kthe cores of kthe CC
and CD sections of the matrix. The S1, S2, and S3 con
ductors are used to read out words stored in the matrix.
When the cores of the selected address receive the pulses
ber llllllllllll would be stored in the selected address.
To store the desired binary word, the Z or inhibit con
ductors are used. There are two Z conductors, Z1 and
322, the cores which store a ONE will be switched to
their ZERO state and this switching will cause a pulse to
Z2, for each tier.
the cores of the selected address. The cores which store
a ZERO will already be in their ZERO state and there
fore will not be switched and will not induce any pulses
The Z1 conductor in each tier is
threaded through all the cores in the tier which are in
the B section and which are in the CA and CB sections.
The Z2 conductor in each tier is threaded through all the
cores in the tier which are in the CC and CD sections
of the tier. The Z1 conductors of the matrix are pulsed
be induced in the S1, S2, or S3 conductors which thread
in the S conductors threading them. Twelve sense ampli
iiers Sii-t4 amplify the pulses induced in the twelve S1
conductors, twelve sense amplifiers 3&5 amplify the pulsesA
by the Z1 drivers, which are designated in FIGURE 1
induced on the twelve S2 conductors, and twelve sense
by the reference number 393. The Z2 conductors of the
amplifiers 3l@ amplify the pulses induced on the twelve
matrix are pulsed by the Z2 drivers 3M. Ir" the selected 75 S3 conductors. The outputs of the amplifiers 3M, ’dif-5„
6
5
and 3io are applied to the memory read out circuits 3713,
The fact that there are three S conductors in each tier,
makes it possible to read out up to three 12 bit words
simultaneously. When three 12 bit words or one 12 bit
word and one 24 bit word are to be read out, one of the
words will be in the CA section, one will be in the CB
section and the third will be in the CC section.
beginning of the application of pulse 3216 and thus the
pulse 322 will be induced in the output winding of the
switch core. When the pulse 326 ends, the bias current
will switch the switch core back to its original state, and
the pulse 323 will then be induced in the output wind
ing ot the switch core. Thus by the selection of the
The
proper one of the conductors XX1 through XX4 and Xyl
through Xy., any one of the cores of the X switch core
switch core matrices will apply the current wave form
y matrix can be selected, and operated to produce the out
SiS to one of the groups of conductors X1 through X8,
one of the groups Y1 through Y4, one of the groups Y5 10 put pulses 322 and 323. Similarly, one of the cores of
the Y switch core matrix can be selected and operated
through YS, and one of the groups YQ through Y12.
simultaneously with the X cores to produce the pulses
These will be at the same relative position in three dif
322 and 323.
ferent submemory sections speciñed by a single index
Thus, to operate the switch core matrices, the wave
register. Pulses will then be induced in all three S con
ductors of each tier, amplified by the ampliñers 51d, 315, 15 form 321 must be applied simultaneously to one of the
input conductors Y X1 through Yxi, one of the input con
and 3io and applied to the memory read out circuits 3î3.
ductors Xy1 through X51, one of the input conductors
To read out a 24 bit word or two 12 bit words, only two
YX1 through 'YX/1, and one of the input conductors YY1
addresses are selected, one in the CA section and the
through Yy@ The wave form 321 is generated by the
other in the CC section.
The detailed circuitry of the switch core matrices Stil 20 memory programmer, designated 3% in FIGURE l and
applied to the selected input conductors of the switch
is illustrated in FiGURE 5. The switch core matrices
core matrices through the X and Y drivers 395.
comprise 32 permalloy tape-Wound bobbin cores of the
When two 12 hit words are to be enteredl in the storage
type having square hysteresis loops. ri`he outputs from
core matrix simultaneously, the current wave form 321
the switch core matrix positioned at the top of FIGURE
5 drive the series connected groups of conductors X1, 25 will be applied to one or” the input conductors XX1 through
XX1, to one of the input conductors Xy1 and Xyz, one
through X16 of the storage matrix. This switch core
of the input conductors YX1 through YM, one of the
matrix shall be referred to as the X switch core matrix.
input conductors YY1 and Yyg and one of the input con
The outputs from the 16 cores shown at the bottom of
ductors Yyg and YY1. When a 24 bit word is to be
FEGURE 5 drive the series connected groups oi con
ductors Y1 through Y1@` of the storage core matrix. This 30 stored, the input conductors ‘ y1 and Yy3 should be
selected. When three 12 bit words are to be read out
switch core matrix shall be referred to as the Y switch
of the storage core matrix, or one 12 bit word and one
core matrix. The particular series connected group ot
24 bit word, the current wave form 321i will be applied
conductors which each switch core drives is indicated at
to the conductor Yy1, to the conductor Yyg, and to the
the output of each core. A conductor 325 is wound
conductor Yyg as well as one of the conductors YX1
around each one of the 32 switch cores in series. A
through YM, one of the conductors Xy1 and Xyz, and
DC. bias current is applied to the conductor 325 to bias
one of the conductors XX1 through X114. When two
the switch cores well into one of their stable states. Both
i2 bit words or a 24 bit word are to be read out, the
the X switch core matrix and the Y switch core matrix
conductor Yy1 and the conductor Yy3 will receive the
are each arranged into columns and rows of tour. ln ad
dition to the bias winding and the output winding, each
current wave form 332i.
switch core has two additional windings which shall be
referred to as the first winding and the second winding.
In the X switch core matrix, the iirst windings of ail the
ductors YX1 through YM, one of the conductors Xx1
through XXè and one of the conductors Xy1 and Xyz
cores which are in the same column are connected in se~
Of course, one of the con
must also receive the current wave form 321. when two
12 bit wor-ds are to be read out.
winding of all the cores which are in the same rows are
As is described in the copending application Serial
No. 784,358 of George Philip Sarratian, Charles L.
Kettler, and George T. Baker filed December 31, 1958,
connected in series to form four conductors Xy1 through
the operation of the memory system is controlled by a
ries to form four conductors which are designated X111 _'
through Xx@ ln the X switch core matrix, the second
X54, respectively. Likewise, the iirst and second windings
control unit, which carries out this function by giving
of the Y switch core matrices are series connected in
columns and rows to form the conductors Yx1 through
commands in a sequence in accordance with the computer
program. These commands are given to the memory
Yxr and Yy1 through Yyr, respectively.
system by applying signals to different inputs, each of
The X and Y switch core matrices operate in the
same manner and any selected one of the X switch cores
and any selected one of the Y switch cores can be oper
ated to produce simultaneously the current wave form
31S. This operation is done by driving a selected one of
the conductors X111 through XM, a selected one ot’ the
conductors Xy1 through Xyè, a selected one of the con
ductors YX1 through YX1, and a selected one of the 60
which in response to one of the applied signals will
cause the respective command to be carried out.
`
When a binary word is to be stored in or read out of
the storage core matrix, the control unit will give a
command initiating the storing or read out operation and
selecting the section of the memory into or out of which
the word is to be read. The command WBM will cause
a word to be entered into the B section of the storage
conductors YY1 through Yyr simultaneously with a wave
core matrix.
form 321i shown in FIGURE 4. The wave term 321i
comprises an elongated current pulse 326. rThis current
be entered into the CA section of the storage core matrix.
pulse 325, -when applied to the first or second windings
into the CB section of the storage core matrix.
The command WCA will cause a word to
The command WCB will cause a word to be entered
The
of one of the switch cores, will have a polarity to cause 65 command WCC will cause a word to be entered into the
C section of the storage core matrix. The command
a magnetization oi the core in a direction opposite to
WCD will cause a word to be entered into the CD section
that caused by the D.C. bias applied on conductor 325.
of the storage core matrix. The command RBM will
One current pulse 32d alone, when applied to one of the
cause a word to be read out of the B section of storage
windings of one of the switch cores, is insuilicient to
overcome the bias applied to the core over conductor 70 core matrix. The command RCA will cause a word to
be read out of the CA section of the storage core matrix.
325 and therefore the core will remain in the stable
The command RCB will cause a word stored in the CB
state to which it is biased. However, when current
section of the storage core matrix to be read out. The
pulse 326 is applied to both the ñrst and second windings,
command RCC will cause a word stored in the CC
Vthe bias current will be more than cancelled out and
the switch core will switch to the opposite state at the 75 section of the storage core matrix to be read out. The
aoeaaea
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es
command RCD will cause the word stored in the CD
section of the storage core matrix to be read out.
and 437 through Mft each have three inputs and the
AND gates 43S and 435 each have two inputs. When
The particular word position or address in the section
of the memory selected is determined by the binary nurn~
register selection logic 3M will apply a signal to one of
ber stored in one or tive index registers which are desig«
nated generally in FIGURE l by the reference number'
32th. The control unit of the computer will give a
command to select a particular one of the index registers.
Two of the live index registers are used exclusively totl
select addresses in the B section of the storage core
matrix. These two index registers shall be referred to
as the Bi and B2 index registers. The remaining three
index registers are used exclusively to select addresses
in the CA, CB, CC and CD sections of the storage core
matrix. These index registers shall be referred to as
the Ci, C2 and C3 index registers. The commands
SBI and SBZ cause the Bl and B2 registers, respectively,
to he selected and the commands SCi., SC2, and SC3
cause the C1, C2 and C3 registers, respectively, to he
selected. To carry out the process of selecting a desired
address in the selected section of the storage core matrix,7
the correct input conductors of the switch core matrices
must be selected in response to the binary number stored
in the selected index register. This selection of input
conductors is carried out by the B register decoder 3u?
and the C register decoder 3%.
The details of the B register decoder are illustrated in
FIGURE 6. As shown in this ligure, the Bl register'
comprises seven hip-hops ¿Si through @57 to store a
seven digit binary number. The ONE outputs from the
ever either the command Shi or SBZ is given, the index
`vthe
he inputs
input to
of the
eachB of
register
the AND
decoder
gates
over
@Elwhich
through
this sig
nal is applied is designated by the logical symbolism
SBî-kSBZ. The output from the inverter
is applied
to inputs of the AND gates 437 and 439. The output
from the inverter 422 is applied to inputs of the AND
gates
The output from the inverter 423
is applied to inputs of the AND gates
and 443. The
output from the inverter' ¿52e is applied to inputs of the
AND gates lidi and A42. The output from the vinverter
425 is applied to inputs of the AND gates
433.
’Ehe output from the inverter ¿.126 is applied to inputs of
the AND gates 4.3i and
The output from the in
verter 427 is applied to
input of the AND gate 435.
The output from the OR gate ¿iii is applied to inputs
:of the AND gates ¿.133 and ¿id-ti and the output from the
OR gate ¿l2 is applied to inputs of the AND gates 439
and
The output from the OR gate ¿E3 is applied
to inputs of the AND gates ed?. and
and the output
of the OR gate ¿ii-t- is applied to inputs of the AND
:gates lil-i3 and
The output trom the OR gate ¿l5
is applied to inputs of the AND gates 432. and [i3d and
the output from the OR gate ¿lo is applied to inputs of
`the AND gates 433 and 43d. The output from the OR
The
gate AND
47.7 is gates
applied
¿i3-i tothrough
an input
¿53dofand
the ¿537
AND
through
gate 444
flip-hops 451 through 457 are applied to inputs of AND
each will produce an output signal whenever signals are
gates 401 through 4W, respectively. rl‘he AND gates
applied to all three of its inputs and each of the AND
491 through 407 each have two inputs. 'When the com
gates ¿13S and 436 will produce an output signal when
mand SBI is given, the index register selection logic
ever signals are applied to both its inputs. Thus, the
31a (FIGURE l) will apply a signal to the other input 35 AND gates ¿§31 through ¿E4-4i will produce output signals
of each of the AND gates @i through díl'î'. The out
in combinations responsive to the binary number stored
puts from the AND gates ffl-till through @d'7 are applied
in
the Bl register whenever the command SBl is given
to a series of seven OR gates ¿lli through @i7 respectively.
and responsive to the binary number stored in the B2
The B2, register comprises seven hip-flops doi through
register whenever the command SBZ is given. For ex
467. The ONE outputs of the flip-flops del through 467
ample, if the selected register contains the binary num
are applied to inputs of the AND gates 3% through 397
ber lÜlGtlGl, the AND gates 4532, fido, 43o”- and lid?. will
respectively. The AND gates 39E through 397 each have
produce output signals.
two inputs. When the command
is given, the index
The `output signals produced by the AND gates ¿3l
register selection logic 3M will apply a signal to the other
through
will cause the k and Y drivers .W5 to apply
input of each of the AND gates 391 through 397.
the current wave form 321 to selected ones of the input
outputs from the AND gates 39î through 397 are applied
conductors Xxl through XX4, Xyg, Kyi, Yxl through Yxr,
to the OR gates dll through 4317, respectively. When
and Yyl through Yyê, respectively, of the switch core
the command SBl is given, signals will pass from the
matrices 3h12.
ONE outputs of those of the flip-fiops 453. through y¿E57
FIGURE 7 illustrates the details of the C register de
which contain ONE’s through the enabled AND gates
coder. The Cl register comprises five ilip~tlops 457i
41M, respectively and through OR gates ¿iii through
through 47S to store five digit binary numbers. The ONE
417, respectively. When the command SBZ is given,
outputs of the Hip-flops 47?. through 475 are applied to
signals will pass from the ONE outputs of those of the
inputs of the AND gates Sui through 595, respectively.
Hip-flops 461 through 467 which contain ONE’s through
the AND gates 391 through 397, respectively, through
the OR gates 411 through éâi7, respectively. Thus, the
OR gates 411 through 417 will produce output signals
The outputs of the AND gates 5M through 5% are ap
it does not receive a signal at its input.
of the AND gates 5M through 525 are applied to the
plied to OR gates 531; through 535, respectively. The C2
register comprises ñve flip-‘lops 481 through 485. The
ONE outputs of the tlip-ñops ¿i551 through 485 of the OR
in accordance with the ONE’s stored in the hip-hops
register are applied to inputs of AND gates Stil through
451 through y457, respectively, whenever the command
SBl is given, and in accordance with the ONE’S stored 60 SiS, respectively. The outputs of the AND gates 511
through SiS are applied to the OR gates 531 through
in the flip-hops 461 through ¿o7 whenever the command
535, respectively. The C3 register comprises iive ñip
SBZ is given. The outputs from the OR gates fill
ilops @9i through A95, respectively. The ONE outputs
through 417 are applied to the inputs of inverters ft2?.
of the hip-tions doti through 495 are applied to inputs of
through A27, respectively. Each of the inverters @2i
AND gates 521 through 525, respectively. The outputs
through 427 will pro-duce a signal at its output whenever
Thus, the
OR gates 531 through 535, respectively. The AND gates
5M through 5%, Sill through SiS, 52E. through 525 each
in accordance with the ZERO’s stored in the flip-flops
have two inputs. The other inputs of the AND gates Sill
'45E through 457 whenever the command SE1 is given
and in accordance with the ZERO’s stored in the flipdiops 70 through StES will have a signal applied thereto by the
index register selection logic Sli. whenever the co mand
'del through 467 whenever the command SBZ is given.
The outputs from the GR gates dll through A?? and
SG1 is given. The other inputs of the AND
s 511
the outputs from the inverters All through -127 are ap
through 5l5 will have a signal appiied thereto by the
plied in dilter'ent combinations to a series of 14 AND
index register selection logic 3M whenever the command
gates 43l through 444. The AND gates
through 434 75 SC2 is given and the AND gates 52.?. through 525 will
inverters 421 through ¿i127 will produce output signals
3,068,452
l@
it the selected one of the Cl, C2, or C3 registers con
have a signal applied thereto by the index register selec
tains the binary number 10101, the AND gates 552, 556
tion logic Sil whenever the command SC3 is given.
and 558 will produce output signals.
When the command SCi is given, signals will pass from
The signals produced by the AND gates 551 through
the ONE outputs of those of the flip-hops 471 through
550 will cause the X and Y drivers 305 to apply the cur
475 which contain ONE’s through the AND gates Sill
rent wave form 321 to the input conductors XXI through
through 555, respectively, and through the OR gates 53l
Xxl, Xyl, Xy2, and Yxl through Yxi, respectively, of the
through 535, respectively. When the command SC2 is
switch core matrices ¿itil ln this manner, the binary
given, signals will pass from the ONE outputs of those
number stored in the selected index register controls the
of the ilipdiops 431 through 485 which contain ONE’S
through the AND gates Sli through 5l5, respectively, 10 selection of the address in the selected section of the
storage core matrix.
and through the OR gates 531 through 535, respectively.
FIGURE 8 illustrates the details of the X and Y
When the command SC3 is given, signals will pass ‘from
drivers 355. As shown in this ligure, the X and Y
the ONE outputs of those of the fiip-"lops @l through
drivers comprise lo AND gates 35i through 356, the
495 which contain ONE’s through the AND gates 521
through 525, respectively, and through the OR gates 533i 15 outputs of which are applied through amplifiers 331
through 346, respectively, to the input conductors XX1
through 535, respectively. Thus, the OR gates 531V
through XM, Xyl through Xyi, YX, through YX4, and Yyl
through 535 will produce output signals in accordance
through Yyi, respectively, of the switch core matrices
with ONE’S stored in the iiip-tiops @7l through 475 re
spectively, whenever the command SCl is given, in ac
cordance with the ONE’S stored in the iii -tiops 431
392. rlÍhe AND gates 35i through 366 each have two in
puts. To one of the inputs of each ot these AND gates
the current wave form Fall is applied from the memory
programmer 356. The outputs from OR gates 371
through 332 are applied to the other inputs of the AND
through 435, respectively, whenever the command SC2 is
given, and in accordance with the ONE’s stored in the
hip-flops 491 through 495, respectively, whenever the
gates 351 thro-ugh 354 and 359 through 356, respectively.
command SC3 is given.
rt`he outputs from the AND gates 453i through 434 and
The output signals from the OR gates 531 through 535 25 437 through
of the B register decoder 307 are ap
are applied to the inputs of inverters 541 through 545.
plied to the OR gates 37E through 332, respectively.
Each of the inverters Sel through 545 will produce an
output signal whenever it does not receive a signal applied
to its input. Thus, the inverters 54d through 545 will
The outputs from the AND gates ¿£35 and 436 are ap
plied to the other inputs of the AND gates 357 and 35S,
respectively. The outputs from the AND gates 551
30
produce output signals in accordance with the ZERO’s
through 55d- and 557’ through 55d of the C register de
stored in the i‘lip-iiops 471 through 475, respectively,
coder 3dS are applied to the OR gates 37d through 378,
whenever the command SCi is given, in accordance
respectively. The outputs of the AND gates 555 and
with the ZERO’s stored in the flip-flops ¿Si through 435,
556 are applied to the other inputs ot the AND gates
respectively, whenever the command SC2 is given, and
355 and 356, respectively. The command logic for the
in accordance with the ZERO’S stored in the ñip-ilops
submemory selection designated 309 in FiGURE l will
491' through 495, respectively, whenever the command
apply a signal to the OR gate 379 whenever either of the
SC3 is given.
commands WCA or RCA is given. The command logic
The outputs from the inverters Seil through 545 and
for the submemory selection 353 will apply a signal to
the OR gates 53d through 535 are applied in different
40 the OR gate 35@ whenever either the command WCB
combinations to the AND gates 551 through 560. The
or the command RCB is given. The command logic for
AND gates 55,“1 through 554 and 557 through 56h each
the submemory selection 359 will apply a signal to the
have three inputs and the AND gates 555 and 556 have
OR gate 331 when either command WCC or the com
two inputs. Whenever any one of the commands SCîl,
mand RCC is given and will apply a signal to the OR
SC2, or SC3 is given, the index register selection logic
gate 332 when either the command WCD or the com
3.1i will apply a signal to one of the inputs or” each of
mand RCD is given. rEhe current wave form 3.2i will pass
the AND gates 553- through 56d. This signal will be ap
through those of the AND gates 35i through 356 which
plied on the input in FÍÍGURE 7 designated by the logi
have signals applied to their other inputs, through the
cal symbolism SCl-l-SC2+SC3. The output from the
ampiliiers 331 through 346, respectively, to the selected
Oi?. gate 533i is applied to inputs of the AND gates 552
input conductors of the switch core matrices. When;
and 554. The output from the OR gate 532 is applied
ever a word is entered into or read out of the storage
to inputs of the AND gates 553 and 554. The output
core matrix., one of the AND gates 351 through 354 will
from the OR gate 533 is applied to inputs of the AND
receive a signal on its other input, one of the AND gates
gates 555 and Seti. The output from the Ol?. gate 534 is
355 through 353 will receive a signal on its other in
applied to inputs of the AND gates 559 and 569 and the
through 362 will re
55 put, one ot the AND gates
output from the 0R gate 535 is applied to an input of
ceive a signal on its other input and one of the AND
the AND gate 556. The output from the inverter 541
gates 363 through 356 will receive a signal on its other
is applied to inputs of the AND gates 551 and 553. The
input. Thus, one of the input conductors XXI through
output -from the inverter 542 is applied to inputs of the
Xxr, one of the input conductors Xyl through Xy@ one
AND gates 551 and 552. The output from the inverter
of the input conductors YX, through YX4, and one of the
69
543 is applied to inputs of the AND gates 557 and 559.
input conductors YY1 through Yyi will receive the cur
The output from the inverter 5dr-i is applied to inputs of
rent wave form 321.
the AND gates 557 and 55S and the output from the
Whenever two l2 bit words are to be entered into
inverter 545 is applied to an input of the AND gate
the storage core matrix simultaneously, both one of the
555. Each of the AND gates 551 through 554 and 557
commands WCA and WCB and one of the commands
through 56!) will produce an output signal whenever sig~
WCC and WCD must be given. In response to these
nals are applied to all three of its inputs and the AND
commands, the command logic for submemory selection
gates 555 and 55d each will produce an output signal
will apply a signal both to one of the AND gates 353
whenever signals are applied to both of its inputs. The
and 36d and to one ot the AND gates 355 and 366. As
AND gates 55l through 5o@ will therefore produce out
a
result, the current wave form 32d will be applied to
put signals in combinations responsive to the binary nurn 70 both one of the input conductors Yy1 and ‘(3.2 and one of
ber stored in the Cil register whenever the command
the input conductors Yyg and Yyi. Whenever a 24 bit
SCl is given, responsive to the binary number stored in
word is to be entered into the storage core matrix, the
the C2 register whenever the command SC2 is given, and
commands WCA and WCC will be given.
responsive to the binary number stored in the C3 regis
Whenever one l2 bit word and one 24 bit word or
ter whenever the command SC3 is given. For example,
aces/sse
l2
‘three 12 bit words are to be simultaneously read out of
the storage core matrix the commands RCA, RCB, and
RCC must be given. The command logic for subrnem
ory selection will then apply a signal to the AND gates
existing in the lower live stages the information distri
bution unit in the C3 register, is given, the control unit
will apply a signal to the AND gates 57i through 586.
The binary number existing in the lower 5 stages of the
information distribution unit will then pass through the
AND gates 57i through 5S@ to be registered in the ñip
flops @l through 495. Whenever the command RC3,
respectively.
353, 364 and As
365a through
result, theOR.
current
gates wave
379, form and
32?. will
be applied to the input conductors Yyl, Yyg and Yyg.
When two l2 bit words or one 24 bit word is to be read
out from the Storage core matrix, the commands RCA
and RCC must be given. The current wave form 32E.
live stages of the information distribution unit, is given,
will then be applied to the input conductors YY1 and
through
to read the contents of the C3 register out to the lower
the control unit will apply a signal to AND gates 581
Y 3.
yIt will be observed that in all of these simultaneous
read in and read out operations the selected addresses
always will occupy the same relative position in the se
lected sections of the storage core matrix and a single
binary number in the selected index register controls
the addresses Within the selected sections of all the Words
simultaneously entered in or read out.
As described in the copending application Serial No.
to its opposite state.
784,358 of George Philip Sarratian, Charles L. Kettler
and George T. Baker, tiled December 31, 1958, digital
prises five iiip-tlops 473; through 47S.
state, the flipdlop 491 will apply a signal through the en
abled AND gate §91 through OR gate 5% to cause the
flip-‘iop ¿i592 to switch to its opposite state. In like man
ner, each of the preceding dip-flops ¿3532; through 494 will
apply a signal through the enabled AND gates 592 through
respectively, through OR gates 597 through S99, re
pectively, to cause the succeeding dip-flops ¿§93 through
f3, respectively, to switch to their opposite states if the
meding tlip-llop switches from its ONE state to its
The command
t'iops A71 through 475.
If, when this command is given,
the flip-tldp 493 switches from its ONE state to its ZERO
words are transferred to and from the memory system
by means of a central information distribution unit, which
has a capacity for l2 bit words, and the memory accumu
lator bus and the accumulator memory bus, which each
have a capacity for 24t- bit words.
FIGURE 9 illustrates the details of the Cl register,
which, as stated above with reference to FlGURE 7, com
designated WCî is the signal to cause binary numbers
exis ing in the lower tive stages of the information dis
tribution unit to be stored in the Cl register. When the
command signal WC1 is given the control unit will apply
a signal to enable AND gates 561 through 570. The
binary number existing in the lower live stages of the
information distribution unit will then pass through the
AND gates S6?. thro-ugh 570 to be registered in the ñip
The contents of the ilip~ñops 491 through
495 will then pass through the enabled AND gates 581
through 5h“, to the lower live stages of the information
distribution unit.
Whenever the command ICS, to increase the binary
number stored in the C3» register by one, is given the con
trol 'unit will apply a signal to AND gates S91 through
5%. This signal from the control unit will also pass
through OR gate 595 to cause the Hip-flop 491 to switch
Y
L.ERO state when the command lCS is given. ln this
manner, the number stored in the C3 register will be in
reased by one each time the command ICS is given.
When the command DC3, to decrease the binary num
ber stored in the C3 register by one, is given, the control
unit will apply a signal through the OR gate 595 to cause
the hip-’lop dgl to switch to its opposite state. This
signal is also applied to the AND gates otlll to 663. lf
the ílip-ñop 491 is switched from its ZERO to its ONE
The command signal designated ICl will cause the bi 40 state, it will apply a signal through the enabled AND
nary number stored in the Cl register to increase by one.
gate out) through the OR gate 5516 to cause the flip-Hop
When the command ICl is given, the control unit will
492 to switch to its opposite state. Likewise, each of the
apply a signal to the tlip-ñop 437i causing it to switch to
preceding flip-flops M2 through 495 will apply a signal
its opposite state. If the Hip-flop 471. is switched from
through the enabled AND gates Still through 683, re
its ONE state to its ZERO state, it will apply a signal
spectively, through the OR gates 597 through 599, respec
to flip-dop é§72 which will cause the flip~flop 472 to switch
tively, to cause the succeeding ilip-ilops 493 through 495,
to its opposite state. lt the flip-dop 472 is switched from
respectively to switch to their opposite states, if the pre
its ONE state to its ZERO state it will apply a signal to
ceding ilip-llop is switched from its ZERO to its ONE
the llip--ilop 473 and cause the ilipdlop 473 to switch to
state when the command DCS is given. Thus, in this
its opposite state. The Hiphop 473 and the ilip-ñop 474 manner the binary number stored in the C3 register will
likewise cause the ilip-ilops ¿i715 and 4375, respectively, to
be decreased by one whenever the command DCS is
switch to their opposite states if the Hip-Hops 473 and
given.
$76.», respectively, are switched to their ZERO States.
In summary, the number stored in the C3 register can
Thus, the dip-ttops 471 through 4,75 are connected as a
be entered from the lower ñve stages of the information
binary counter and whenever the command lCl is given
distribution unit, it can be read out from the C3 register
the binary number stored in the C1 register will be in
into the lower ñve stages of the information distribution
creased by one.
unit, it can be increased by one, or it can be decreased
The C2 register is exactly the same as a Cl register.
by one.
The command to cause the iive bit binary number existing
As described in the copending application Serial No.
in the lower tive stages of the information distribution unit -
to be registered in the C2 register is `designated WCZ and
the command to cause the binary number registered in
the C2 register to be increased by one is designated ICZ.
The Bl and B2 registers are also similar to the C1
register except that they comprise seven llip-íiops instead
of ñve. The commands WE1 and WBZ will cause the
seven bit binary number existing in the lower seven stages
of the information distribution unit to be registered in
784,358 of George T. Baker, Charles L. Kettler, and
George Philip Sarratian, filed December 31, 1958, the
memory accumulator bus and the information distribu
tion unit use the dual conductor systeml In this System
there are two conductors for each bit. When a ZERO
is transferred, one of these conductors will be positive
and the other will he negative. When a ONE is trans
ferred, the potentials on the two conductors are reversed.
the accumulator memory bus, however, only has one
the El and E2 registers, respectively. The commands
conductor for each bit which conductor will have a posi
lBl and T32 will cause the contents of the El and B2 70 tive potential applied thereto when a ZERO is transferred
registers, respectively, to be increased by one.
and a negative potential when a ONE is transferred.
The details of the C3 register are shown in FIGURE
The memory read in circuits designated 312 in the
li). As stated above with reference to FIGURE 7, the
FIGURE 1 controls which of the Z1 drivers and which
C3 register comprises tive llipuñops 491 through rfi-95.
of the ZT. drivers receive the current wave form 319 .and
When the command WC3, to store the binary number
thus determine in which tiers of the storage core matrix
aosaeea
13
from the AND gates 619 will be applied through the
a ZERO will be stored in the selected address or ad
respective OR gates 621 and the respective cathode fol
dresses. The details of the memory read in circuits are
lowers 622 to the respective Z1 drivers. The Z1 drivers
illustrated in FlGURE 12. There are twelve memory
3263 which receive signals from the respective AND gates
read in circuits, one for each digit of a 12 bit binary
619 will then apply the current wave form 31.9 to the
member. Each memory read in circuit controls the
respective Z1 conductors. Thus, the Z1 conductors in
storing of ONE’s and ZERO’s in the core or cores of the
those tiers of the storage core matrix in which a ZERO
selected address or addresses in a different tier of the
is to be stored at the selected address will receive the
storage core matrix. For convenience, only three of the
current wave form 319, if the selected address is in the
memory read in circuits have been shown as each read
section threaded by the Z1 conductors, and thus ZERO’S
in circuit is identical.
will be stored in the cores of these tiers at the selected
The commands to enter the word existing in the in
address.
formation distribution unit into the storage core matrix,
When the command to store the binary word on the
are WBM, WCA, WCB, WCC, and WCD. When any
information distribution unit in the CC section or the
of these commands are given, the command logic for
submemory selection 369 will apply a signal to AND 15 CD section of the storage core matrix is given, the com~
mand logic for the submemory selection 309 will apply
gates 611 and 612 of each read in circuit. In each read
an enabling signal to the AND gates 611 and 612 and
in circuit the outputs from the AND gates 611 and 612
the binary word existing on the information distribution
are applied through OR gates 613 and 614, respectively,
through cathode followers 615 and 616, respectively, to
unit will be registered in the flip-flops 617. Those ñip
enabling signal is applied from the command logic for
output signal to the respective AND gates 620. The
AND gates 626 will be enabled and therefore will apply
an output signal to the respective Z2 drivers through the
respective OR gates 623 and cathode followers 624. The
Z2 drivers receiving these output signals from the memory
the ONE and ZERO inputs of a ñip-ilop 617. When the 20 llops 617, which then register a ZERO, will apply an
the submemory selection 309 to the AND gates 611 and
612, the l2 bit binary word existing in the information
distribution unit will pass through the AND gates 611
and 612, through the OR gates 613 and 614, and through
read in circuits will then apply the current wave form
the cathode followers 615 and 616 to be registered in
319 to the respective Z2 conductors. Thus, the Z2 con
`the l2 flip-flops 61.7.
ductors in those tiers of the storage core matrix in which
ln each read in circuit the ZERO output from the
a ZERO is to be stored at the selected address will re
flip-flop 617 is applied through a cathode follower 618
to the inputs of a pair of AND gates 619 and 620. The 30 ceive the current wave form 319, if the selected address
is in a section threaded by the Z2 conductors and thus
AND gates 619 and 626 have three inputs and require
ZERO’S will be stored in the cores in these tiers at the
an input signal applied to all three inputs to produce an
selected address.
output signal. A signal will be applied to the second
The conductor or" each stage of the lower half of the
input of each of the AND gates 619 and 620 whenever
accumulator memory bus is applied to the OR gate 623
neither the command WAC nor the command RAC is
in a ditferent read in circuit. The conductor of each
given. The logic for producing this input to the AND
stage of the upper half of the accumulator memory bus
gates 619 and 626 may be similar to that used in the
is applied to the OR gate 621 in a different one of the
command logic for submemory selection 369 or the index
read in circuits. When it is desired to transfer a 24 bit
register selection logic 311, which are described in detail
below. The command logic for submemory selection 369 40 word. from the accumulator to the storage core matrix,
the command RAC will be given. This command will
will apply an enabling signal to the third input of the
cause the 24 bit word registered elsewhere in the com
AND gates 619 whenever any of the commands WBM,
puter to be put on the accumulator memory bus, as is
RBM, WCA, RCA, WCB, or RCB is given. The com
more fully explained in the copending application Serial
mand logic for submemory selection 369 will apply en~
No. 784,358 of George T. Baker, Charles L. Kettler and
abling signals to the third inputs of the AND gates 626
George Philip Sarrañan, filed December 3l, 1958. This
whenever any of the commands WCC, RCC, WCD, or
command will also prevent a signal from being applied
RCD is given. The output from the AND gate 619 in
to the second inputs of the AND gates 619 and 626.
each read in circuit is applied through an OR gate 621
At the same time the command RAC is given, the com
through a cathode follower 622 to a different one of
twelve Z1 drivers, which are designated in FIGURE l 50 mands WCA and WCC will be given. Also, one of the
commands SCll, SC2, or SC3 will be given. Signals will
by reference number 3113. The output from the AND
be applied from the conductors of those stages of the
gate 6211 in each read in circuit is applied through an
lower
half of the accumulator memory bus on which
OR gate 623 and through the cathode follower 624 to
there are ZERO’s through the respective OR gates 623
a different one of twelve Z2 drivers, which are designated
through the respective cathode followers. 624 to the re
31M in FIGURE l.
spective Z2 drivers. These respective Z2 drivers will
The memory programmer 366 applies the current wave
then apply the current wave form 619 to the respective
form 319 to each of the Z1 and Z2 drivers. Each of
Z2 conductors and the lower half of the 24 'oit word will
the Z1 drivers, in response to receiving a signal from the
be stored in the CC section of the storage core matrix
respective read in circuit, will apply the current wave
form 319 to one of the Z1 conductors. Likewise, each 60 at the address selected by the binary number stored in
of the Z2 drivers in response to a signal from the re
spective read in circuit, will apply the current wave form
to one of the Z2 conductors. The Z1 and Z2 drivers
363 and 364 are not shown in detail but could comprise
an AND gate and ampliñer combination similar to that
of the X and Y drivers 365.
When one of the commands WBM, WCA, or WCB
is given, the binary word existing on the information
distribution unit will be registered in the twelve dip-flops
617. Those flip-flops 617, which then contain a ZERO,
will apply an output signal through the respective cathode
followers 613 to the respective AND gates 619. The
AND gates 619 will be enabled and thus an output signal
will be produced from those AND gates 619 which re
the selected index register. Signals will also be applied
from the conductors of those stages of the upper half
of the accumulator memory bus on which there are
ZERO’S through the respective OR gates 621 through the
respective cathode followers 622 to the respective Z1
drivers. These respective Z1 drivers will then apply the
current wave form 619 to the respective Z1 conductors
and the upper half of the 24 bit word will be stored in
the CA section of the memory at the address selected
by the binary number in the selected index register. Two
twelve bit words can be stored in the storage core matrix
in the same manner. When two separate twelve bit
words are simultaneously stored, it is not necessary that
the CA and CC sections of the storage core matrix be
ceive signals from the ñip-llops 617. The output signals 75 selected words.
The CB section of the storage core
-
matrix may be selected instead of the CA section and
the CD section may be selected instead of the CC section.
When a command to read information out from the
storage core matrix to the information distribution unit
is given, provision is made to restore the word read out
in the position in the storage core matrix from which
the word is read. Signals will be applied from the read
out circuits for each tier of the storage core matrix
through the OR gates 613 and 614 of each read in circuit
through the cathode followers 61S and 616 to the flip
fiops 617. The flip-Hops 617 then will register the word
read out from the selected address in the storage core
matrix. The command logic for submemory selection
will apply an enabling signal to the AND gates 619
if the selected address is in the B section or the CA or
CB section of the storage core matrix and thus signals
will be applied to the Z1 drivers for those tiers from
which a ZERO is read out.
The current wave form 319
will then be applied to the Z1 conductors of the tiers
the command REM or RCA is given while at the same
time either the command RCA or the command RCC
is not given. rl`lie outputs from the AND gates 643
and
are applied to the OR gates 642 and 645, re
spectively. The command logic for the submernory selec
tion 339 will apply an enabling signal to the AND gates
641 whenever both the command RCC or the
command RCD is given and either the command RCA
or the command RCC is not given. The output from the
AND gates 6ft and 641 are applied to OR gates 642
and 64S respectively. ln order for the AND gates 633
and
to produce an output signal they must receive
an enabling signal from the command logic for sub
memory selection and this signal will be applied when
ever the command RCB is given. The outputs from the
AND gates 633 and 638 are applied to the OR gates 642
and edd, respectively. The outputs from the OR gates
6ft-2 and odd in each read out circuit are applied to a
different stage of the information distribution unit and
from which a ZERO is read out. If the selected address lO~. CD the outputs are also applied to the OR gates 613 and
Vfrom which the read out takes place is in the CC section
or in the CD section, the command logic for submemory
se‘ection 3€@ will apply an enabling signal to the AND
gates .625.5 and the read in circuits will then apply signals
to the Z2 drivers for those tiers of the storage core
matrix from which ya ZERO was read out.
In response
thereto the Z2; drivers will apply the current wave form
319 to the Z2 conductors of these tiers of the storage
core matrix. The read out operation takes place after
the pulse 322i of the current wave form 31S but before ‘
the _pulse 32d is applied to the Z conductors of those
tiers of the storage core matrix from which a ZERO is
read during the same cycle that the binary word is read
out from the storage core matrix. Thus, the read out
and restoring all takes place during one read out cycle.
There are twelve read out circuits, one for each tier
of the storage core matrix. Each read out circuit is
identical so only one read out circuit has been shown
in FÈGURE 13. The output from each of the twelve
ampliíìers 31d, which amplify the signals induced in the
S1 conductors, is applied to a different one of the read
out circuits. The output from each of the twelve ampli
tìers 315, which amplify the signals induced in the S2
conductors, are applied to a dilïerent one of the read
out circuits. The outputs from each of the twelve ampli
ñers 315, which amplify the signals induced in the S3
conductors, are applied to a different one of the read
out circuits. The output from each of the amplifiers 314,
will be applied to an inverter 632 and an AND gate 631
in one of the read out circuits. The output from each
of the ampliliers 315 is applied to an AND gate 633 and
an inverter 634 in one of the read out circuits. The
output from each of the ampliliers 316 is applied to an
AND gate 635 and in inverter 636 in one of the read
out circuits.
614, respectively, in the memory read in circuit for the
same tier of the storage core matrix. The outputs from
AND gates 631 and 637 in the read out circuit for each
tier of the storage core matrix are applied to a different
stage of the upper half of the memory accumulator bus.
The output from the AND gates 635 and 639 in the
read out circuit tor each tier of the storage core matrix
is applied to a ditterent stage of the lower half of the
ory accumulator bus.
Yv‘v’henever either the command RCA or REM is given,
positive going pulses will be induced in those S1 con
ductors which are
tiers which contain ONE’s at the
selected address. 'ifhese pulses will be caused by the
pulse 322 of the wave form
Those S1 conductors
which are in tiers which contain ZERO’S at the selected
address will have no pulses induced in them at this time.
The induced pulses after being amplified by the respective
amplifiers 31d are applied to the AND gates 631 and in
verters 632 in the respective read out circuits. The in
verters in these respective read out circuits upon receiv
ing the induced pulses will stop applying a signal to the
AND gates 637. The inherent delay in the read out sys
tem vi‘l cause the induced pulses to arrive at the AND
gates «531 and inverters 632 at the time of the pulse 327 of
the wave form 323'. The AND gates 631 which receive
pulses ‘.vill therefore produce output signals at this time.
The inverters 632, which are in `read out circuits for tiers
in which ZlîR-O’s are stored at the selected address, will
not receive pulses at the time the pulse 372 is applied to
the AND gate
and therefore the inverters 632 in these
respective read out circuits will be applying signals to the
AND gates 637 at this time. 'Die AND gates 637 in
those read out circuits for tiers which contain ZERO’s at
the selected address will therefore produce output signals
at this time. Thus, the AND gates 631 and 637 in each
Each of the inverters 632., 634, and 636 in each read
read out circuit will produce output signals in accord
out circuit will produce a signal at its output whenever
ance witr the digit stored at the selected address in the
it does not receive a signal at its input. The outputs
respective tier whenever the commands RCA or REM are
from inverters 632, 63d, and 636 are applied to AND
given.
gates 637 through 639 respectively. The memory pro 60
ln the same manner the AND gates 633 and 633 will
grammer
applies a wave form, designated 32€) in
produce output signals in accordance with the digit stored
FIGURE 4, to each memory read out circuits 313 when
at the selected address in the respective tier whenever the
ever a command to read out from the storage core matrix
command RCB is given. Likewise, the AND gates 635
is given. This wave form contains a pulse 327 which
and
in each read out circuit will produce output signals
has the time relationship shown in FIGURE 4. The 65
accordance with the digit stored at the selected address
wave form 32H3 will be applied to the AND gates 631,
in the respective tier whenever the command RCC or
633, 635 and 637 through 639 in each of the read out
RCD is given.
circuits. rl`he outputs from the AND gates 631 and 637
The output signals produced by t e AND gates o3
are applied to AND gates 643 and 6411 respectively.
and 637 will pass through the AND gates 643 and 643
The outputs from the AND gates 635 and 639 are applied 70 if they are enabled through the OR gates 642 and 6-t5
to AND gates 64d and 641 respectively. The outputs
to the information distribution unit. The output signals
from the AND `gates 633 and 638 are applied to OR
produced by the AND gates 633 and 639 will pass throug'i
gates 6d?. and
respectively. The command logic
the AND gates »5d/«î
641, if enabled, through ti e OR
for the submemory selection 3il9 will apply an enabling
gates
and 64S to the information distribution unit.
signal to the AND gates 6d@ and 643 whenever either 75 Of course, the computer will be programmed so that only
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