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Патент USA US3076160

код для вставки
da» 29,1963
F. ROZNER
3,076,150
TRANSISTOR CIRCUITS
Filed May 20, 1958
2 Sheets-Sheet 1
à0 LT+
LT
Jan. 29, 1963
F. RozNER
'TRANSISTOR CIRCUITS
Filed May 20, 1958
3,076,150
2 Sheets-Sheet 2
30
O-SV
085V
36
25g/g5 35
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39
41
PULSES
BLANK/N6
42
@LAN/(ED
PICTURE
SIGNA L S
R1.
/N VEN 7_0@
ffl/X ROZ/VIP
BY
ATTOA’A/ Y
United States PatentOñlice
« 3,07§,l50
Patented Jan. 29, 1963
l
2
3,076,150
TRANSISTOR CIRCUITS
Felix Rozncr, London, England, assigner to Ferguson
scribed by way of example with reference to the accom
panying drawings in which:
FIG. 1 is a circuit diagram of a common collector
Radio Corporation, London, England, a British company
Filed May 20,1958, Ser. No. 736,482
1 Claim. (Cl. 33o-11)
transistor circuit; and
FIGS. 2 to 5 are circuit diagrams of dilïerent em
bodiments of the invention. y,
Referring first to FIG. 1,~'this shows a common col
The present invention relatesv to transistor circuits.
lector transistor circuit embodying an NPN transistor
There are many circuits which are required to handle
signals at speciñc D.C. levels. If there is a D.C. path 10 11, the emitter of which is connected to an output' ter
minal 12 and through a load resistor 13 ofresistance
a D.C. level can usually be retained. In many cases, ¿A RL to earth. The base of the transistor is connected
through an input circuit, the total impedance of which
'ioweveig it is desirable to employ A.C. couplings in
is represented by the impedance ZB, to an input ter
the circuit and this necessitates the use of additional
minal. The collector is connected to the positive ter
components whose function is to restore the D.C. level.
minal LT-j- of a bias source (not shown), the negative
` According to a first aspect of the present invention,
terminal LT- of said source being connected to earth.
there is provided a D.C. restoring -circuit comprising
Following the generally accepted theory for transistor
`a transistor having a base electrode, a collector elec
circuits the output impedance 201 can be represented ap
trode and an emitter electrode, an input circuit connected
to the base electrode and to which in operation signals 20 proximately as follows:` Y
>between the input and output terminals of the circuit
to be restored to a predetermined D.C. level are applied,
an output circuit connected to the emitter electrode,
and means so biasing the base-collector junction of
the transistor that said junction is reverse biased for in
put signal excursions to one side of said predetermined 25
where:
D.C. level and is forward biased for signal excursions
to the other side of said level. Signal excursions are ' ' ZB is the total impedance >inthe base arm,
thus restored to said D.C. level and signals appear in
a0 is the emitter to collector current gain
the output circuit as D.C. restored signal-s.
In an embodiment according to the said iirst aspect 30 w0/21r is the current gain cut otf frequency,
of the' invention, the output circuit is connected to one
w is the operating frequency.
electrode of a two or more electrode semi-conducting
Since for most modern transistors a0 is
device, the junction formed by said electrode and anoth~
quencies,
A
_
V
j
»
at low fre
v
and
l
about 0.98
there is little diiiiculty in? obtaining a value of Zm of the
signal excursions to one side of a further predetermined 35 order of 100 ohms or less. lOn the other hand, when
D.C. level and forward biased for output signal excur- . _the ltransistor is cut oil, that is to say, when the base~
er of said electrodes being reverse biased for output
_emitter junction is-reverse biased the output impedance
sions to the other side of the further predetermined
level, whereby output signal excursions are limited to
`excursions between said predetermined D.C. level and
said further predetermined D.C. level.
Preferably, said semi-conducting device is a further
transistor having a base electrode, a collector electrode
increases to a value within an order of magnitude of
lMìohm.
40
.
~
Referring now to FIG. 2, this shows a circuit com
prising two NPN transistors 15 and 16, the emitters of
which are connected to eartY through a common load
resistor 17 of resistance RL and to an output terminal
and an emitter electrode, and said output circuit is con
18. The base of the transistor 15 is connected to an
nected to the emitter electrode of the further transistor,
the baseaemitter junction of which is reverse biased for 45 input terminal 19, which is in operation maintained at
a predetermined D.C. potential El. The >base of the
output signal excursions to one side of said further pre
other transistor 16 is `coupled to an input terminal 2t),
determined D.C. level and is forward biased for output
to which in operation an input signal is applied. The
signal excursions to the other side of the further prede
collectors of the two transistors are maintained at a po
termined D.C. level.
tential E0 by connection to the positive terminal LT-l
According to a second aspect of the present inven
of a D.C. bias source (not shown), the negative ter
tion, there is provided a D.C. restorer circuit compris
minal
LT- of said source being connected to earth.
ing a transistor having a base electrode, a collector elec
In operation, signals applied to the input terminal 20
trode and an emitter electrode, an input circ-uit to which
are ampliñed by the transistor 16 and amplified signal-s
in operation signals to be restored to a predetermined 55 appear at the output terminal 18.
D.C. level are applied., an output circuit connected to
Provided the output signal potential does not fall be
the input circuit and to the emitter electrode, the base
low El the base-emitter junction of the transistor 15 is
emitter junction of the transistor being so biased that
reverse biased and the transistor 15 cut on”. In these
said junction is reverse biased for output signal excur
circumstances the output impedance of the transistor 15
sions to one side of said predeterminedrDC. level and 60 is high and the transistor 15 has very little shunting effect
is forward biased for output signal excursions to the
upon the load resistor 17 and the transistor 16. The
other side of said predetermined DLC. level. Signal
transistor 16 thus functions as a common collector ampli
lier.
excursions are thus >limited to the predetermined level
When the signals applied to the input terminal Ztl fall
and signals appear in the output circuit as D.C. restored
signals.
65 to zero, the output signal potential falls to the value El.
At this value, the base~emitter junction of the transistor
In a preferred embodiment, there is provided in corn
15 becomes forward biased and the transistor 15 conducts
bination a D.C. restorer circuit according to the first
.t-o' maintain the output signal potential at the value El.
aspect of the invention and a D.C. restorer circuitlac~
cording to the second aspect of the invention, the two 70 The output signal is thus D.C. restored to a potential El.
It the input signal applied to the input terminal 20 is
,circuits having a common output circuit.
Some embodiments of the invention will now bedev- .
a rapidly changing signal, a delay will be observed in
the clamping »action of the transistor 15. This delay
3,076,150
3
terminal 26, provided it does not exceed the potential E1,
appears 'as a slight overshoot in the case of a pulsed
is transmitted to the output terminal 24, the transistor 21
acting as an emitter follower. If the input signal tends
to drive the base of the transistor 21 above the potential
input signal. Such overshoot can, however, be avoided
by arranging that the values of the circuit components
satisfy a given condition, which can be derived as follows
E1 the base-collector junction becomes forward biased
by considering the expression for the output impedance
ZM of the transistor 15.
and the input impedance drops rap1dly from approxi
mately
If ZB, the total impedance of the base arm of the
transistor 15, is assumed to be of the form
R-pïîî
10
then
to little more than the base resistance, which including
the spreading resistance is of the order of 100-200 ohms.
Zei-:M
15 The base of the transistor 21 will thus maintain a po
tential E1 despite input signal excursions above this level.
The resultant output signal at the terminal 24 is thus
D_C. restored to the potential level El. In like manner,
the input signals subsequently applied to the input termi
20 nals 27 and 28 are D.C. restored to the potential levels
E2 and E3 respectively.
In addition, the output signal resulting from the signal
applied to the input terminal 27 is prevented from falling
below the potential level E1 by the action of the tran
l
25 sistor 21.
In the absence of an input signal at the termi
nal at the terminal 26, the ba-se of the transistor 21 is
held at the potential level E1. Output signals above the
weer
potential level E1 maintain the baseemitter junction of
the transistor 21 reverse biased. Output signals falling
The reactive component of ZM _is inductive when the
below t-he level E1 cause the base-emitter junction to be
imaginary part of the above expression `is positive, that is 30
come forward biased and the transistor 21 conducts and
'to say, if
2
2
‘l(Ro.-l)>(1-u„')(1+‘° RC)
wn
wo
»
wa
restores the potential of the output signal to the potential
level E1.
The output signal at the terminal 24 resulting from
35 the signal subsequently applied to the input terminal 28
or
Ro>l
wo
is D.C. restored by the action of the transistor 23 so as
not to exceed the potential level E3. In addition, this
output signal is held above the potential level E2 by the
eliminated.
action of the transistor 22.
It is possible by use of a circuit such as that shown
in FIG. 3 to combine several signals each within well
defined D.C. levels, without the need for separate D.C.
ment comprising three NPN transistors 21, 22 and 23,
restorers.
By suitable choice of circuit components this condi
tion can be reversed and any overshoot substantially 40
Referring now to FIG. 3, this shows a circuit arrange
It will be appreciated that the transistor 21 does not
terminal 24 and through a common loa-d resistorV 25 to 45 operate under exactly the same conditions as those
assumed for the transistor 11 in FIG. 1 and the transistor
the earthed negative terminal LT- of a D.C. bias source
15 in FIG. 2. The base-collector junction of the tran
(not shown). The bases of the transistor 21, 22 and 23
sistor 11 in FIG. 1 and the transistor 15 in FIG. 2 is
are coupled to input terminals 26, 27 and 28 respectively,
assumed to be reverse biased. The base-collector junc
to which in operation input signals are applied. The
tion of the transistor 21 is, in the circuit of FIG. 3,
50
collectors of the transistors 21, 22 and 23 vare maintained
forward biased. This means that the transistor 21 acts
at potentials E1, E2 and E3 respectively by connection to
the emitters of which are connected to a common output
D_C. bias sources (not shown).
` The circuit shown in FIG. 3 is employed to combine
as an inverted transistor, that is to say, its collector emits
and its emitter collects. The output impedance of the
transistor under these conditions can be expressed as
three input signals and to maintain said signals within
predetermined D.C. levels. To facilitate the description 65 follows:
(peut)
of the operation of the circuit it is assumed that the
potential El is positive with respect to earth by a pre
determined amount and the input signal applied to the
terminal 26 is positive-going with respect to earth and
is required to be D.C. restored or clamped at the po 60
tential E1. Furthermore, the potential E2 is positive with
respect to the potential E1 by a predetermined amount
and the input signal applied to the terminal 27 is positive
going and is to be D.C. restored so that the resultant
1 +551
where
a1 is the new emitter to collector current gain
:o1/2n is the current gain cut-off frequency, and
rc1 is the inverse resistance of the base-emitter junction.
output signal varies only between these potential levels. 65 The output impedance ZM', although considerably lower
The potential E3 is positive with respect to E2 by a pre
than in the case where the base-collector junction is
determined amount and the input Vsignal applied to the
reverse biased, is however, still high enough to make the
terminal 28 is positive-going and is required to be D.C.
shouting effect of the transistor 21 upon the resistor 25
>restored so that the resultant output signal varies only
negligible.
70
between the potential levels E2 and E3. It is further
It may sometimes be desirable to have a voltage ampli
more assumed that> the potential of the terminal LT-l- is
yfier instead of an emitter follower, whose voltage gain
positive with respect to E3. Finally, it is assumed that
the input signals are applied in turn to the terminals 26,
27 and 28.
is just under unity.
In another embodiment of the present invention, there
is provided in combination, a D.C. restorer circuit accord
In operation, the input signal rapplied to the input 75
5
ing to the said second aspect of the invention and an
amplifier including a further transistor having a base
electrode, a collector electrode and an emitter electrode,
the base electrode of the further transistor being con
nected to an input circuit of the amplifier to which in
operation further input signals to be ampliiied are applied,
and the collector electrode of the further transistor being
6
circuit suitable for mixing synchronising, blanking and
picture signals within well-defined levels corresponding to
the above specified levels.
.
The circuit shown in FIG. 5 comprises three transistors
35, 36 and 37, the first two ybeing of NPN type and the
last of PNP type. The emitter of the transistor 37 is
maintained at a potential of V volts with respect to earth
connected to said output circuit.
by connection to the positive terminal LT-{- of a D.C.
i An embodiment of the invention is shown in FIG. 4.
source (not shown). The negative terminal LT- of said
The circuit comprises an NPN transistor 29, the base of
which is coupled to an input terminal 30 to which in 10 source is earthed. The collectors of the transistors 35
and 36 are maintained at potentials equal to 0.3 v. and
Operation signals to be D.C. restored are applied. The
0.35 v. respectively. The emitters of the transistors 35
collector ot the transistor 29 is maintained at a potential
and 36 and the collector of the transistor 3'7 are connected
El by a D.C. source not shown and the emitter is con
nected directly to an output terminal 3l and through a 15 to Áa common output termin-al 3S and through a common
load resistor 39 to the earthcd terminal LT~-load resistor 32 to the earthed terminal ILT- of D.C.
The base of the transistor 35 is coupled to an input
source not shown. The circuit includes a further tran
sistor 33 of PNP type, the base of which is coupled
to an input terminal 34 to which in operation are applied
terminal ¿t0 to which in operation synchronising signals
to be DC. restored are applied. The base of the tran
sistor 35 is coupled to an input terminal 41 to which in
signals to be amplified and mixed with the signals applied 20
operation blanking signals -are applied. The base of the
to terminal 30.
Signals applied to the terminal 30 are as hereinbefore
described D.C. restored to the potential level El by the
Itransistor 37 is coupled to »an input terminal 42 to which
in operation blanked picture signals are applied.
In operation, blanked picture signals applied to the
action of the transistor 29. Signals applied to the ter
minal 34 are amplified by the transistor 33 and appear 25 terminal 42 are amplified by the transistor 37 and appear
‘at the output .terminal 33. During these times, that is to
at the output terminal 31. When the transistor 33 is
driven from its non-conducting state by signals applied
say in the absence of synchronising and blanking pulses
the base-collector junctions of the transistors 3S and 36
are forward biased. The picture signal appearing at the
transistor 33 has completely replaced the emitter current 30 output terminal 38 varies in accordance with input signal
applied .to terminal 42, but is prevented from falling be
in the load resistor 32. After this the potential of the
l-ow the potential level of 0.35 v. by the action of the
output terminal 31 rises and the base-emitter junction of
transistor 35. Thus, the transistor 36 sets the black
the transistor 29 becomes reverse biased.
level of lthe picture signal at 0.35 v. Blanking pulses,
When the input signal to terminal 34 is such as to
which occur just before and terminate just after the syn
allow the potential of the output terminal 31 to fall
ehronising pulses cut-off the transistors 36 and 37. The
below E, the latter is held at the value E1 by the action
output signal at the terminal 38 falls, but is held at the
ot the transistor 29.
potential level of 0.3 v. by the -action of the transistor 35.
in the arrangement of FIG. 4, the transistor 29 oper
This level is the blanking or suppression level. With the
ates as an emitter follower for signals applied to the
terminal 30, when the output signal Iat the terminal 31 40 transistors 36 and 37 cut-ofi, the negative-going synchro
nising pulse applied to the terminal 40 during the blank
is below the potential level E1, and as an inverted tran
ing period is transmitted to the output terminal 38.
sistor when the output signal at the terminal 3l is above
The output signal at the terminal 3S is then a television
the potential level E1.
.
signal composed of picture signals between potential
According -to yet another |aspect of the present inven
levels -of 0.35 v. and V, -blanlring signals between levels
tion, there is provided a transistor circuit comprising a
of 0.3 V. and 0.35 v., and synchronising signals between
nearly symmetrical transistor having a lbase electrode, a 45 zero
and 0.3 v.
f
collector electro-de and an emitter electrode, an input cir
lt
will
be
appreciated
that
in the circuits shown in
cuit connected -to the base electrode and to which in
FIGS. l to 3, the NPN transistors may be replace-d by
operation input signals are applied, an output circuit
PNP transistors provided appropriate changes are also
connected to the emitter electrode, and means for adjust
ing the D.C. potential of »the emitter electrode whereby 50 made to the supply potentials. In the circuits shown in
FÍGS. 4 and 5, if the NPN transistors are replaced by
the transistor can be caused selectively to operate as an
PNP transistors, then the PNP transistors must also be
emitter follower or as a voltage amplifier on said input
replaced by NPN transistors and appropriate changes
signals. By nearly symmetrical transistor is meant Áa
to the supply potentials.
transistor the characteristics of which are such that 55 made
I claim:
to the terminal 34 no change in the potential of the out
put terminal occurs until the collector current of the
m'ì’ao and colœcoo
the terms al, a0, w1 and wo having meanings hereinbefore
specified.
In a direct current restorer circuit the combination
comprising a first transistor including emitter, base and
collector electrodes; a load impedance; a source of vari
able voltage input signals; means coupling said emitter,
In an embodiment according to the last-mentioned
aspect of the invention, the circuit shown in FIG. 4 is 60 base and collector electrodes of said first transistor in a
common collector circuit with said load impedance cou
provided with means for adjusting the D.C. current flow
pled to said emitter electrode and said signal source
ing from the collector of the transistor 33 through the
coupled to said base electrode, an output terminal con
load resistor 32. If the product of the DC. collector
nected to the junction between the emitter of the first
current of the transistor 33 and the resistance RL of the
load resistor 32 is less than El then the transistor 29 65 transistor and the load; a second transistor having a base,
operates as an emitter follower. If the same product is
greater than El then the transistor 29 operates as a volt
a collector, and an emitter, a source of positive constant
to synchronising pul-ses, 30 to 35% to lblanking signals
and 35 to 100% to picture signals. Zero percentage cor
emitter of the first transistor with said load, thereby to
contribute current through said load impedance only
responds to the most negative and 100% to the most posi
when necessary to maintain and in an amount suñicient
direct current potential applied to said base, a direct cur
age amplifier.
rent circuit connection from said collector to a direct
current source, direct current circuit connections from the
In a standard British television signal, if the peak-to
peak voltage is regarded as 100%, then 0-30% is allotted 70 emitter of the second transistor to the junction of the
tive potential of the television signal. FIG. 5 shows a 75 to maintain minimum current ilow through said load
impedance at said constant source potential level and to
3,076,150
7
establish a potential at the output terminal substantially
equal to the steady direct current potential when the
2,759,142
2,761,917
variable potential at the output terminal falls to or is
2,810,024
below the direct current potential.
‘2,816,179
2,859,288
References Cited in the file of this patent
UNITED STATES PATENTS
2,441,880
2,662,938
Goodale _____________ __ May 18, 1948
5
2,927,733
8
Hamilton ____________ __ Aug. 14,
Aronson ______________ __ Sept. 4,
Stanley ______________ __ Oct. l5,
Gittlernan _____________ __ Dec. 10,
Tobias ________________ __ Nov. 4,
Campbell _____________ __ Mar. 8,
1956
1956
1957
1957
1958
1960
OTHER REFERENCES
Shea: Principles of Transistor Circuits, copyright 1953,
Goldstine ____________ __ Dec. 15, 1953 10 page 38, John Wiley and Sons.
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