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Патент USA US3077561

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Feb. 12, 1963
Filed Deo. 9, 1958
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United States Patent O ” ice
Patented Feb. 12, 1953
resistor R2, this .parallel arrangement being connected to
the base of transistor Q1.. An emitter bias ,resistor R3 is
connected with .the source of negative potential to the
emitter of Q1 and to an emitter resistor R1. The collec
tor of Q1 is connected with the base of transistor Q2 of
the next stage. Since transistor Q2 is for positive Volt
Harold B. Nelson, Natick, and Floyd> R. Scripture,
1 Stoughton, Mass., assignorsto the United States of
America as represented by the Secretary of the An'
age applicatoin to a crystal C2, a source of positive poten
Filed Dee. 9, 1958, Ser. No. 779,265
Z> Claims. (Cl. S17-448.5)
i tial B+ is connected through collector load and base
bias resistor R5 to the base of Q2 and also to the crystal
This invention relates to monitoring devices and has 10 under test. The emitter of Q2 is connected to the B+
voltage through a resistor R6 and to ground potential
particular reference to transistor circuitry for monitoring
through a resistor R7. The collector of Q2 connects to
a resistance.
the base of transistor Q3 in the next stage which transis
The device of this invention is intended to be used
tor operates relay K1. The base of Q2 is also connected
with monitors of various components or circuits of a
radar or other electronic system to form an automatic 15 with the B+ voltage by means of its collector load and
base bias resistor R2.
failure prediction system whereby impending equipment
The emitter of transistor Q3 is connected to the B+
failure may be recognized before an actual shutdown of
potential through emitter bias resistor R10 and to ground
the monitored equipment is necessary. Upon recognition
potential through emitter resistor R9. The collector of
of imminent failure, standby units may be substituted
or repairs made, thereby enabling a substantially con 20 Q3 is connected through the coil L1 of relay K1 to B+.
lThe operation of the circuit will now be described, as
tinuous operationot the equipment. ReÍiability of the
suming that a positive test voltage is to be applied to a
monitored components may be considered to be increased
crystal C2. Initally, the monitoring circuit will be operat
ing with transistors Q1 and Q3 biased to cut-off and with
ure. Furthermore, monitoring enables complete analysis
ot system operation which facilitates improvement of 25 Q2 biased to saturation. If, upon connection of C2 to
because components will be replaced prior to actual fail
the circuit, a high resistance is sampled, no change will
occur in the condition of the circuit, the current through
equipment design or compensation in operation to en
hance the equipment reliability. To accomplish the pur~
Q2 remaining at the saturation level and the relay K1
poses of monitoring it is necessary to design the monitor
remaining inoperative.
with a reliability which is greater than the equipment to
As crystal C2 deteriorates, its resistance decreases. If
be monitored.
upon connection of C2 to the circuit, such a decreased
Accordingly, it is an object of this invention to produce
a resistance monitor having good reliabiîity.
resistance is sampled, the base bias voltage of Q2 will
It is also an object of this invention to produce a moni
toring unit which enables substantially continuous opera
tion of monitored equipment by producing a signal on
decrease toward ground potential.
impending circuit failure.
positive base bias for Q3. Upon conduction of Qa, a
voltage will be produced across coil L1 which, upon reach
ing a predetermined value, will cause relay K2 to oper
This tends to make
the base of Q2 more negative than the emitter, and tends
to cut ofi the collector current of Q2, resulting in a more
It is another object of this invention to produce an im“
proved resistance monitor.
It is a further object of this invention to produce an 40 ate. Conduction of Q3 will occur when crystal C2 has
deteriorated so as to reduce its resistance below a certain
To monitor crystal C1, to which a negative test voltage
reduced to a predetermined value.
must be applied, the crystal is connected to the base of
It is a still further object of this invention to produce
improved transistorized resistance monitor capable of pro
ducing a signal when the monitored circuit resistance is
a monitoring unit which utilizes conventional, currently 45 transistor Q1, aS Shown in the drawing, Initially, Q1
and Q3 are at cut-ott, while Q2 is conducting at satura
available components that lend themselves to standard
tion. lf, in testing C1, a high resistance is sampled, the
mass production manufacturing techniques.
circuit will remain in its initial condition and relay K1
These and other advantages, features and objects will
will not be operated. 1f, on the other hand, C1 has de
become more apparent from the following description
taken in conjunction with the illustrative embodiment in 50 teriorated so that a decreased resistance is sampled, the
voltage at the base of Q1 will increase from a negative
the drawing wherein the FIGURE illustrates schematical
value toward ground potential. When the base bias volt
ly a transistor monitor circuit adapted for low voltage
age becomes suñîciently positive with respect to the emit
application to the measured circuit.
ter bias, Q1 will conduct. The collector current through
Referring to the figure, the design presented has been
tailored for checking a crystal located in a circuit 55 Q1 will reduce the base bias voltage at Q2, driving Q2 to
cut-oit and causing Q3 to start conducting. When the
of a radar system'. A study of the failure rate of crystal
resistance of C2 has suñîciently deteriorated, relay K1 will
units indicated a necessity for measuring the D.-C. back
resistance of the crystal, since it was found that the
noise iigure increased rapidly as the back resistance
dropped below approximately 10,000 ohms.
Since an advance indication of impending failure is de
sired, the resistance monitor of this invention is arranged
operate to provide an indication that the measured resist
ance of the crystal has decreased below a certain value.
60 A lamp or some other indicator may be connected to the
relay to provide notiñcation of a low resistance.
Although not limited thereto, the following set of
to give a warning when the back resistance of a crystal
values may be utilized to produce plus or minus l volt
drops to the vicinity of 15,000 to 20,000 ohms.
test voltages utilizing npn transistors in the monitoring
comprises three transistors and associated circuitry and
a relay K1. Transistor Q1 operates when a negative
R1 _______________________________ _. 240K
R2 _______________________________ _. 22K
The transistorized resistance monitor of this invention 65 circuit.
voltage is needed to check a crystal and may be omitted
when only a reversed polarity is required. Transistor
Q1 is connected to a negative potential B- through base 70
bias resistor R1. The crystal C1 to be monitored re
quiring a negative test voltage is placed in parallel with
R2 ______________________________ __
R4 ______________________________ __ 240K
R5 _______________________________ ... 430K.
R6 ___
R2 _______________________________ _. 270K
path to receive the preponderance of the current ñowing
R3 _______________________________ „. 130K.
L1 _______________________________ _. 5K resistance.
from said current source, so that the current flowing from
said source to said relay winding is insufficient to operate
the relay, but becomes of progressively increasing mag
B+ _____________________________ __ 22.5 v.
nitude as the progressive deterioration of said test com
R9 _______________________________ _. 270K.
R10 ______________________________ _. 6.2K.
B-~ _____________________________ __
ponent reduces the current ñow in said first path and corre
spondingly increases the current ñow to said relay wind
ing, until eventually said relay Winding receives suñicient
»22.5 v.
To improve the reliability of the test circuit cooling
means should be provided to avoid overheating of the
Thus, it is apparent that an improved resistance moni
current to operate the relay.
tor operating at low levels across the monitored circuit
has been developed.
2. Apparatus as defined in claim 1, including third and
fourth current paths from said current source to the
grounded emitter sides of the respective transistors, said
third and fourth paths including resistance units of equal
magnitude, which magnitude is substantially less than that
Although the invention has been described with refer
ence to a particular embodiment, it will be understood
of said first-named resistance unit.
to those skilled in the art that the invention is capable 15
of a variety of alternative embodiments Within the spirit
References Cited in the ñle of this patent
and scope of the appended claims.
We claim:
, 1. In combination with a current source and a pair of
Pinckaers ____________ „_ Mar. 25, 1958
Mitchell _____________ __ Aug. 19, 1958
transistors, having grounded emitter electrodes, a pair of
parallel current paths leading from said current source to
Pinckaers ____________ __ Sept. 16, 1958
Frank _______________ _- Dec. 16, -1958>
the collector electrodes of the respective transistors, the
ñrst of said paths including a resistance unit, the second
including a relay winding, and a test component subject
to progressive deterioration, said test component being 25
“Headlight Dimmer,” Radio and Television News,connected to the base electrode of the ñrst of said transis
August 1955, pp. 56, 57 and 122.
tors, and normally operating to cause said first current
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