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Патент USA US3083310

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Marçh 26, 1963
w- s KNowLEs ETAL
3,083,303
DIODE INPUT NOR CIRCUIT INCLUDING POSITIVE FEEDBACK
Filed June 18, 1959
4972/01@ ../. EZ /45‘
INVENTORS.
BY ¿má
ATTO/@ME75 .
United States Patent O Fice
3,083,303
Patented Mar. 26, 196.3
2i
1
a circuit diagram» ofl an embodiment of the invention.
rI’his includes a plurality of input terminals 10, 12, 14,»
to Awhich signals for operatingA the. embodiment of the in
3,083,303.
PîQSiTIyP-î; FEEDBACK
Wiliiarn. Knowies, Malibu, and »Arthur-J; Elias, Canoga.
Park, Los, Angeles, Calii.,_assignors,y by mesne assign,
moon-INPUT Non CIRCUHINCLUDING.
vention mayf- be applied. Three are-shown by way of
example only. More or less. than-this number may» be
used. A .ñrst transistor 16has an emitter 16E, a- collector
16C, and a base 16B. From each one of the input termi
ments, to> Ampex , Corporation, . itedwootil` City Calif., ` a Y
corporation oi' California.
Fileddnne i8, 1959, Ser. No. 821,136
5¿ Ciaims. (Cl. ,Tail-’l-ßßß)`
This. invention relatesto electrical logic circuits and,
more particularly, to »an improvement therein.
nals ‘10, 12», 14, a separate »diode 18, 20, 212 is connected
to theernitter 16E of the transistor. A terminal 24, tov
10 which `a negative operating potential is applied, is. con
nected to the emittenloE thnough a resistor 26. A-resistor
28 connects vthe base 16Baof the transistor 16ï to ground or
lthe point ofV reference potential.
Logic circuits are the elements which- circuit designers
employ in. building up information-handling systemsfor
A second transistor Stlalso has. an. emitterßGE, a col
processing data. One of. the basic logic circuits is .that 15 lector SllC, and a. base, 30B, A resistor älconnects. the
known as a “NOR” circuit.
terminal 24 to the collector 30C; Another resistor 34:
connects the. collector 30C to they base 16B. A resistor
36. in series with adiode 38 connects thecollector 16C.’v
»ofthe- transistory 1.6. to the base` 30B. of 'the transistor 30:
type ofrcircuit has av
plurality of> inputs, and` itsvr function 'is toV provide an.=>
output whenv any one or.- more than.y one ofv its inputs.
excited with :a signal having a> particular polarity.> No
output is received in the> presence .ofi signalsv of other 20 A terminal 4t) to which/a. positive operating. potential is.
applied is connected. through a resistory 42 ,to thebase 30B
thanltlrose having the specified polarity.
Some ofthe diíìiïcultiesexperienced, inthe prior art
of transistor 39".. A terminal 44, to which a positive
potential'. is applied, is connected to the emitter 30E. oiv
with. this. general type of device have beenthat the
amplitudeof Ythe input signal has an effect upon theout
transistor. 30. An output terminal 46.2is connected to the
put signal. Thus, where a minimal amplitude ‘signal is. 25 collector 30C ofy transistor 30. A; clamp. diode 48 con~
necessary, in order tocause «the NOR- circuit to operate,.
nects ,the` collector and »output terminal 4610l a terminal
the outputreceived asa resultvof the> application off
50, to which a negativeclamp, potential isv applied.
signals in the. vicinity ofthe minimal signal may not bef,
.AL diode 52ay is . connected between-_ the base .and .emitter
of. transistor 30..and serves- the~ -functionyotpreventing
suitable for utilization without considerable. additional
circuitryy for shaping- andampliñcation of the output.
Further, large pulse cur-rent inputsignalshave> caused
excessiveback bias betweenß‘base.- andfernitter when the
transistor. Silis vnot conduc.ting.»~.v It doesV this by clamping
thesbaseto thepotentialapplied to the emitter, A diode`
apparatusfailures, a correction ofwhich, in a complex
information-handlingv system,y canbe extremely costly..
54, connected between the collector 30C` andv the junction
An. object ofwthis invention is -t-o» provide anoveland
of. theconnectionbetween resistor 3Q and diode 3S, in
35 combination with diode. 38 and its associated resistors,usefulY logic circuit.
Anotherr'object `of-.f the. presentv invention is. toV pro
yacts to prevent transistor 30 from becoming saturated by
ylimiting the maximum potential applied to `base 30B to`
Videa logic circuit; whichy hasiawide tolerance for. diíier
ent ¿amplitude-input signals.
maintain the transistor 30> conductive.
Yet » another` object»l `of thev presenty invention,> is.'y the-y
In the quiescent state, the transistor 16 is conducting
provision of a novel circuit» which provides a uniform 40 andcurrent ñows through the resistor 2,6;and emitter 16E.
output signal, despite variations> in amplitude . ofthe input
Current for collectorl 16C flows from terminal #t4-,through
signal.
the emitter and baseof transistor 3_9- andl through` diode
These and other objects of this-.inventionare` achieved
68 and current limiting resistorßó. The; collector current
30
in a circuit whichcomprises a first and a- second transistor,
reduces the potential on the base of transistor 30«t0»a¿value
one of> which is Iof ythe NPN type; and the other of- the 45 suñiciently- below the emitter potential. to insure that the
PNP type. The_circuit interconnections are arranged, so
transistor. Stl‘is also conductive near, but notïat, saturation.
that> the first and> second transistors, in theVA absence of an
At this time, `the potential on the outputterminal 46-- is
inputI to` the circuingare maintained conductive.i An input
substantially-i-.S v., the potential being applied to the
signal which is applied to one or more of a plurality of
emitter 30E. Upon the application> of a signal to- any
diodes connected; to theV ernitterg of the- ñ-rsttransistor, 50 one or. more of; the input terminals L10,l 12,` 14, which
effectively steers current awayi frornf the first transistor
signal is positive,.and„which exceeds a predetermined rarn
emitter, whereby it; is rendered _ nonconductive. This ~
renders, the , second.; 'transistorf- nonconductive. The vout-Y
pur. of :the , second-.transient is; clamped in. a. marmer. SQ»
-plitude .asdetermined by the` valuesV .chosen for.r the systemk
components, current; instead ot-llowing intorthe emitter
notfvary; Further, theoutput obtained,` in Ithel presence
of anr input signal,V is standardfand doesç- not vary. By`
utilizing feedback between Vthesecond and ¿first- tra‘rglsistor,~
when .the input signal exceeds a threshold value, regardless
isbeing applied.; As a result, theA transistor 16 iscut oit.
oiy the transistor is .diverted to flow throughthe .one or
that its output, in the absence of an input signal,¿¿does,4 55 more. ofçthe diodes 118,120,22, toïwhichthe input signalY
When this happens, current fvorgthe> collector.- 16C can n.0»
longer'. ‘flow> through .the transistorgâtl; TheV base~30B of
the transistor âjtlgis rapidly rendered positive by the con
of -any excess thereover, ‘the full value of the> output is 60 nection . through , resistor. 42.1to> terminal;` 40.` Transistor 30
obtained. In view` of~ theîcurrent steering.; arrangement
to the input -of the circuit, large current,> pulses cannot
damage. the >transistors employed;
The novel features that-'are considered characteristic
isthus rapidlyrendered nonconductiveralso,f_ As previ->
ouslystated, diode 52 clamps the potential to- which the
base. can. rise. .to v+5 v.. Current'. can t now` flow. . from lthe
terminal 50 through the diode 481and resistor, 32y tothe.
of this invention are :set` forth with particularly in the 65 terminal 24. Diodevllââ` is aclampdiode andfinsures-.that
appended> claims. The invention itself,_1 both as tor its
the terminal» 46» will be at thepotentiali‘applied to the
organization and method of operation, as well‘rgas‘adrdif
diodev 48._ In the> illustration employed# herein, this» is..
tional objects and-advantages thereof, will best be under-4
-5 v.` Assoon as> the signal applied to the-input is
stood from the following description when read in con
nection with the accompanying drawing, which is a 70 dropped below the switching level, theV circuitî irnmedi
ately snaps back to its standby state with both transistors
circuit diagram of an embodiment of the invention.
Reference is now made to the drawing, which shows
being conductive.
3,083,303
The values shown in the drawing for the components
employed in the embodiment of the invention are by way
4
1y connected between said input terminal and said first
of illustration of an operative arrangement, and are not
transistor emitter, a second transistor having an emitter,
collector and base, means including a coupling diode
to be construed as a limitation upon the invention.
coupling said first transistor collector to said second tran
Using
these values, the voltage at the terminal 4,6 was +5 v.
in the absence ot' an input signal and was -5 v. in the
presence of an input signal. Resistors 34 and 28 serve as
a feedback network. The feedback signal which is applied
to the base of transistor 16 serves to standardize the tran
sistor base, means to prevent sai-d second transistor from
saturation including a diode connected between said second
transistor collector and said coupling diode, a third re
sistor connected between said second transistor collector
and the other end tot said tirst resistor, means yfor apply
sition time of the circuit operation. No matter how slowly 10 ing operating potential to said iirst and second resistor
the input voltage changes, the output transition of the
other ends and to said second transistor emitter, an »out
circuit occurs at -full speed. This eliminates the need for
put terminal connected to said second transistor collector,
further lcircuitry for squaring the output voltage, such as
‘ and means for clamping said output terminal to a desired
“Schmitt” trigger circuits, for example. The fact that the
potential value in the absence of an output trom said col
input signal is not applied to the tirst transistor, but in 15 lector.
stead steers current away from it, acts as a safeguard
3. A trigger circuit comprising a first transistor having
against harming an expensive transistor.
an emitter, collector and base, »a ñrst resistor having one
For the purposes of securing a rapid transition time or
end coupled to said tirst transistor emitter, a second re
circuit operation in response to an input signal, it is pre
sistor having one end coupled to said ñrst transistor base,
ierred that a negative signal be applied to the input ter 20 a signal input terminal, an input diode directly connected
minals during the quiescent, or standby, condition. For
between said input terminal and said iirst transistor emit
the embodiment of the invention shown, this was ~-5 v.
ter, a second transistor having an emitter, collector and
This serves the purpose of maintaining a small current
base, a third resistor connected between said second tran
ñowing through the diodes, whereby their inherent capac
sistor collector land said first resistor other end, fmeans
itance is charged and does not delay their response to an 25 coupling said iirst transistor collector to said second tran
input signal. From the symbol employed in the circuit
diagram, it will be noted that the first transistor is of the
sistor base including a tourth resistor and la diode con
nected in series therewith, a feedback resistor connected
between said second transistor collector `and sai-d first
type. This should not be construed as a limitation upon
transistor base, means for applying operating potential to
the invention, since those skilled in the art will readily be 30 said first ‘and second resistor other ends vand to said second
able to interchange the types of transistors employed, as
transistor emitter, an output terminal connected Ito said
well as the necessary bias voltages and diode connections
second transistor collector, ìand means yfor clamping said
without departing from the spirit and scope of this inven
»output terminal to a desired potential value in the absence
rtion. It should also be noted that although this invention
of an output from said collector.
is described as a NOR circuit, this should not be con
v4. A NOR logic circuit comprising a iirst transistor
strued as a limitation upon the invention since it also can
having an emitter, collector and base, ñrst and second re
perform the same functions as, for example, a Schmitt
sistors respectively connected to said íirst transistor emit
trigger circuit; that is, in response to a small or slowly
ter and base, a plurality of signal input terminals, a plural
changing input, which exceeds a predetermined level, pro
ity of diodes respectively connected between said plurality
vide a high level output in the form of a substantially 40 of input terminals and said tirst transistor emitter, a sec
rectangular output pulse with extremely rapid rise-and
ond transistor having an emitter, collector yand base, a
fall times.
`first diode connected between said second transistor base
There has accordingly been shown and described herein
and emitter, `a third resistor connected to said second tran
a novel and useful circuit which is not aflected by the
sistor collector, a fourth resistor connected between said
variations and amplitude of the input signal, either in its 45 ñrst transistor base and said second transistor collector,
transition time or its output.
la fifth resistor having `one end connected to said first
We claim:
transistor collector, a second diode connected between
>1. A circuit for deriving a uniform output signal for a
said fifth resistor other end and sai-d second transistor
Variable input signal comprising a íirst and second tran
collector, a third diode connected between said lifth re
sistor, one of which is of NPN type and the other of PNP
sistor «other end and said second transistor base, means
dior applying operating potential for said transistors to
type, each having an emitter, collector and base, means
for vapplying operating potential to said iirst and second
said íirst, second, and third resistors and said second
transistors to render them conductive including iirst and
transistor emitter, means including a sixth resistor yfor
second terminalsV and a reference potential point, a first
applying »a cutoü :bias to said second transistor base, an
resistor connected between said iirst terminal and said
output ‘termin-al connected to said second transistor col
lector, and means for clamping said output terminal to
iirst transistor emitter, means connecting said second ter
a :desired potential value in the absence of :an output from i
minal to said second transistor emitter, means coupling
said collector.
said ñrst transistor collector to said second transistor base,
5. A NOR logic circuit as recited in claim 4 where
means coupling said first transistor base to said reference
potential point, a second resistor connected between said 60 one lof said lirst «and second transistors is of ‘the NPN
type and the other is of the PNP type.
second transistor collector and said ñrst terminal, an input
diode to which input signals are applied, means for
References Cited in the tile of this patent
directly connecting said input diode to said iirst transistor
emitter with a polarity to conduct current away from said
UNITED STATES PATENTS
NPN type, whereas the second transistor is of the PNP
first transistor emitter upon the application of input signals
thereto, and means for deriving an output from the collec
tor of said second transistor.
2. A transistor trigger circuit comprising Ia first tran
sistor having -an emitter, collector `and base, a first resistor
having one end coupled to said ñrst transistor emitter, a 70
second resistor having one end coupled to said tirst tran
sistor base, a signal input terminal, an input diode direct
2,838,664
2,843,761
Wolfendale __________ __ lune l0, 1958
Carlson ______________ __ July l5, 1958
2,849,626
Klapp ______________ __ Aug. 26, 1958
2,860,258
Hall _______________ __ Nov. ll, 1958
2,903,604
2,947,882
2,976,428
Henle _______________ __. Sept. 8, 1959
Chou _______________ __ Aug. 2, 1960
Parkhill ____________ __ Mar. 2l, 1961
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