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Патент USA US3088105

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April 30, 1963
J. w. DELMEGE, JR
3,088,095
RING CHECKING CIRCUIT
Filed April 24, 1961
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JAMESWDELMEGLJR,
É ßv/ f¿01%"7"
ATTORNEY
United States Patent O
ICC
3,688,095
Patented Apr. 30, 1963~
1
2
3,088,095
to one of the predetermined successive storage units hav
ing a second information item stored therein to inhibit
RING CHECIHNG CIRCUÍT
James W. Delmege, Jr., Sangerties, NX., assigner to In
ternational Business Machines Corporation, New York,
N.Y., a corporation of New York
Filed Apr. 24, 1961, Ser. No. ‘£95,295
13 Ciaims. (Ci. S40-146.1)
the operation of the iirst control means when the iirst
information item is stored in the ñrst storage unit. The
sensing means is activated when the second information
item is subsequently stored in the last storage unit indi
eating that more than one storage funit in the ring has
an information item therein.
Also checking «means may be associated with the ring
This invention relates to checking circuits and more
particularly to an improved circuit for checkingthe opera 10 of storage units in combination with the previously de
scribed checking circuit for detecting when more than
tion of a ring of storage runits.
one storage unit adjacent to another storage unit or sep
Timing devices such as clock pulse generators rare usu- '
arated rby an even number of storage units has an infor
ally comprised of a plurality of storage units in the form
mation item stored therein at the same time. In addi
of bistable devices cascaded together' to form a ring of
tion, checking means may be associated with the ring
bistable devices. The basic component of the clock pulse
of storage units in combination with previously described
generator, namely the bistable device, may comprise ,an
electronic flip-flop circuit having two stable states desi-g
checking circuitry for detecting that the ring of storage
nated as the “one” state and the “zero” state. lInitially a
units has no information items stored therein.
predetermined one of the plurality of flip-flops in the rin'g
The foregoing and other objects, features and advan
is set to the “one” state. The flip-flop setto the “one” state 20 ta-ges of the invention will be :apparent from the follow
produces a D.C. level to condition an associated gate. A
pulse is applied to the ring to sense all of the And gates,
hereinafter designate-d `gates and the gate conditioned by
the D_C. level .produced by the predetermined ñip-iiop in
ing more particular description of a preferred embodi
ment of the invention, as illustrated in the accompany
ing drawings.
FIG. 1 is a block diagram of a clock pulse generator
the “one” state passes the sense pulse which then resets 25 anda preferred embodiment of «a checking circuit accord
ing to the present invention for checking such clock pulse
the predetermined ñip-flop to the “zero” state and sets
i .. the next succeeding Hip-flop to the “one” state. The pulse
passed by the conditioned gate is also delivered to an
generator.
Throughout the following description and in the ac
companying drawings there are certain conventions em
other circuit for utilization as a clock pulse. In' a simi
lar -manner, each succeeding sense pulse applied to the 30 ployed which are familiar to certain of kthose skilled in
the art. Additional information concerning lthese con
ring causes the ilip-flop that is presently in the “one” state
ventions is las follows: In the block diagram figures of
to be reset to the “zero” state and the succeeding Hip-dop
the drawing, a conventional arrowhead is employed to
to be set to the “one” state so that the “one” state steps
indicate (l) a circuit connection, (2) energization with
from iiip-ñop to ñip-ñop of the ring. The clock pulse
deliveredsteps as the “one” state steps from flip-flop to 35 positive pulses and (3) the direction of pulse travel which
lijp-flop.
Accordingly, in `a properly functioning clock pulse gen
erator, one and only one hip-flop is set to the “one” state
to condition an associated gate at the time a sense pulse
is also the Vdirection of control. A diamond shaped ar
rowhead indicates (1) la circuit connection and (2) ener
gization with a D.C. level.
Bold face character symbols
appearing Within a block identify the common name for
is applied to the clock pulse generator, and one and only 40 the circuit represented, that is, FF indicates a hip-flop,
A a positive logical And circuit, Ã :a negative logical
one pulse is passed by the conditioned gate and delivered
as ‘a clock pulse. Occasionally, due to component fail
And circuit, OR a logical Or circuit, and D a delay unit.
Referring now to FIG. 1, the operation of the clock
ure, breakdown, or noise signals creeping in, more than
pulse generator will first be described with a general de
one of the flip-flops may be set t0 the “one” state condi
45
scription. Pulses received on cond-uctor 9 from oscilla
tioning more than one gate so more than one clock pulse
tor 8 sample gates 1t) through 17. Gates 10 through 17
is delivered. This is commonly termed an extra pulse
are conditioned by D.C. levels produced by correspond
condition. Conversely, none of the Hip-flops may be set
ing flip-flops 20 through 27 when set to their “one” state.
to the “one” state so that no gate is conditioned at the
time 'a sense pulse is delivered to the clock pulse genera 50 Normally, only one ñip-iiop is set to “one” and the pulse
received on conductor 9 is passed by the `gate correspond
tor and no clock pulse is delivered. This is commonly
ing to the flip-flop set to “one” to reset that flip-flop to
termed a missing pulse condition.
“zero” and set the next dip-flop to “one” In a similar
Accordingly, it is an object of this invention to provide
manner the “one” state is stepped from hip-flop to flip
an improved checking arrangement for checking the stor
age condition of a ring of storage units.
55 flop around the ring. 'The pulses passed by the condi
tioned gates are also delivered on the lines TPG-TF7
Another object of this invention is to provide an im
to a utilization device for use as clock pulses.
proved checking :arrangement for detecting whether more
The detection of extra or missing pulses will next be
than' one of a plurality of bistable devices are in the “one”
described. Two flip-flops in a clock pulse generator set
state at the same time.
Still another object of this invention is to provide an 60 to their “one” state during the same interval between the
4sense pulses causing the Igeneration of extra pulses are
improved checking arrangement for detecting when the
either ( 1) separated by an odd number of -iiip-flops,
ring of storage units has no information items stored
or (2) are adjacent or separated by -an even number of
therein.
flip-flops. In the preferred'embodiment described here
In accordance with the principles of this invention 1a
checking circuit is provided fora ring of storage units. 65 inafter, conditions (l) and (2) above are detected by
different circuits.
Sensing means are provided for sensing the storage con
The detection of the generation of extra pulses caused ,
dition of the first and last storage units o-f the ring. A
by condition (l) wherein two flip-flops set to “one” dur
first control means is associated with the first storage
unit and is normally effective when ‘a first information
ing the same interval between sense pulses are separated
item is stored therein for controlling the sensing means. 70 by an odd number of flip-'flops will ñrst be described.
A second control means associated with predetermined
The following Table 1 illustrates how the “one” state
storage units successive to the ñrst storage unit responds
of two dip-flops advances around the ring.
A
TABLE 1
gate 57 is delivered on conductor 58 to alarm circuit 60
to indicate that an error has been detected.
Flip-Hops _______ __
0
1
2
3
4
5
G
7
If no error
had occurred gate ‘57 would not be conditioned, no pulse
would be delivered on conductor 58, and no error would
1
0
O
O
1
0
1
0
0
0
0
0
1
0
0
O
0
0
1
0
1
0
0
0
1
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
be indicated.
Thus, any two hip-flops set to their “one” state during
the same interval between the sense pulses and separated
by an odd number of Hip-flops cause a signal to be deliv
ered on conductor S8 to indicate an error as the clock
Assume for the purposes of this description that the 10 pulses are stepped about the ring. Modifications may
be made to the circuitry of the preferred embodiment to
clock pulse `generator has been working correctly up to
construct checking circuitry consistent with the principles
this time, and that, now an error occurs so that the zero
of this invention. For instance, lan And circuit could be
substituted for the And-Not circuit with the D_C. levels
four llip-ilops are separated by an odd number of ñip' 15 from the “zero” side of the tlip-ñops connected to the
And circuit. Also the D.C. levels from the “one” side
llops. Further assume that error detecting flip-flop 59
of all ilip-ilops but the ñrst ilip~ílop could be connected
is reset to its “zero” state so that `gate 57 is deconditioned
to the And-Not circuit and ‘all extra pulse conditions
and And-Not circuit 53 produces a D.C. level to condi
could be detected.
tion gate 55 when all Hip-flops 22, 24 and 26 are reset
20
The detection of the generation of extra pulses caused
to “zero.”
by two ñip-llops or more set to “one” during the same
The four tlip-ilop 24 set to its “one” state produces a
interval `between sen'se pulses and separated by an odd
D_C. level causing And-Not circuit 53 to produce a D.C.
number of tlip-ñops may be described in another man
level which deconditions lgate 5S. The zero and four flip»
ner. if And-Not circuit 53 and gate 55 were not present
flops 20 and 24, respectively, set to their “one” states pro
duce a D.C. level from their “one” side to condition gates 25 llip-llop S9 would alternatively be complemented to its
“one” or “Zero” state so that as one or more “one” states
1l) and 14. A pulse received on conductor 9 from osciland four flip-flops 2l) and 24 are set to their “one” states.
In steps 1 of Table 1 it can `be seen that the zero and
lator 8 samples gates 10 through 17, is passed by -gates
were stepped around the ring eventually dip-flop 59 would
be complemented to its “one” state to condition gate 517
10 and 14 and causes the one and ñve flip-llops 21 and 2S,
so the next pulse passed by gate lll would be passed by
respectively, to be set to “one” and the zero and four llip
ilops 20 and 24, to be reset to “zero” (as shown in Table 30 gate S7 to signal an alarm. The checking circuit without
gate 55 and And-Not circuit 53 would thus periodically
1, step 2). The pulse passed by gate 10' also samples gates
provide
an indication that one or more pulses were circuf ’l
55 and l’57 which are both deconditioned. Therefore,
lating about the ring.
A
flip-flop 59 is not set and no error pulse is delivered on
The addition of And-Not circuit 53 and gate 55 pro
conductor 58 to alarm circuit 60.
35 vides an inhibit or control so that if only one pulse is
If no error had occurred and only the one flip-flop 20
circulating around the ring the checking circuit is inhibited
had been set, gate 55 would have been conditioned by a
from signaling an alarm. Assume that only one pulse is
D.C. level from And-Not circuit 53, and ilipfñop 59
circulating around the ring and llip~ñop 20 is set to “one”
would have been set. Due to the transition time required
to reverse the state of flip-Hop 59 relative to the duration 40 As has been previously described, And-Not circuit 53
produces a D.C. level to condition gate 55 when the
of the input pulse, gate 57 would have been sampled prior
flip-flops it is associated with are all reset to “zero.”
to the transition of the llip-tiop 59 to the “one” state
Gate 10 is conditioned by the D.C. level produced by flip~
and no error alarm would be signaled.
flop 20 set to its “one” state and passes the next sense pulse
The next pulse received on conductor 9 from oscillator
from oscillator 8 to sample gate 55. Gate 55 when con
15 and causes the two and six ilip-tlops 22 and 26, re 45 ditioned by the D.C. level produced from And-Not circuit
53 passes the pulse passed by gate 10 to set ílip-ñop 59
spectively, «to be set to “one” and the one and ñve liip
to its “one” state. Due to the transition time required
ñops 21 and 25, respectively, to be reset to “zero” (as
to reverse the state of ilip-tlop 59 relative to the dura
shown in step 3 of Table 1).
tion time of the input pulse, gate 57 is sampled prior to
The next pulse received on conductor 9 causes the two
and six flip-flops 22 and 26, respectively, to be reset to 50 the transition of flip-flop 59 to the “one” state and no
alarm is signaled. As the “one” stated is stepped around
“zero” and the three 'and seven tlip~flops 23 and 27, re
the ring, flip-flop 59 is complemented to its “zero”
spectively, to -be set to their “one” state (step 4 of
state and as long as only one pulse circulates in the ring
Table 1).
The next pulse received on conductor 9 again samples 55 the process hereinbefore described is repeated and no
error alarm is signaled. However, if an error does occur
gates 10 through 17 and is passed by gates 13 and 17
and two Hip-flops separated by an odd number of ilip
to cause the zero and four flip-flops 20 and 24, respec
llops become set to the “one” state during the same
tively, to be set to “one” and the three and seven ñip
interval between sense pulses the inhibit is disabled as
tlops 23 `and 27, respectively, to be reset to “zero” (step
previously described and an error alarm is signaled.
5, Table 1). The pulse passed by ygate 17 is also applied
The detection of extra pulses caused by two Hip-flops set
to the complement input of flip-flop 59 to set that Hip-flop 60
to their “one” state during the same interval between
to it-s “one” state. Flip-flop 59 thereupon produces a
sense pulses and either adjacent or separated by an even
D.C. level from its “one” side to condition gate 57. The
8 samples ygates `10 through 17, is passed by gates 11 and
D.C. level produced by ilip-ñop 59 from its one side at
number of flip-flops and the detection of missing pulses
caused by the faliure of a Hip-flop to be set to “one” will
this time is indicative of an error condition that two or
more nip-flops are set to their “one” state during the same 65 next be described. The operation of this checking cir
cuitry will first be described with the clock pulse generator
interval between sense pulses. If no error had occurred,
operating correctly.
ñip-ñop 59 would have been in its “one” state and reset
to its “zero” state at this time and gate 57 would not be
Initially assume that Hip-flop 43 is set to its “one” state
and llip-ilop 47 is reset to its “zero” state and that only
The four ñip-ilop 24 set to its “one” state causes And 70 one pulse is circulating in the clock pulse generator and
no error condition exists. Further, assume that the next
Not circuit 53 to produce a D.C. level which decondi
pulse produced by the ring counter is an odd pulse passed
tions gate 55. The next pulse received on conductor 9
by the one of the odd numbered gates, and delivered
is passed by gate 10, samples gate 55, which is decondi
tion'ed, ‘and is passed by gate 57. The pulse passed by 75 to Or circuit 33. The odd pulse from Or circuit 33
samples gate 39 which is deconditioned as llip-llop 43 is
conditioned.
3,088,095
6
5
set to its “one” state. The output of Or circuit 33 is also
applied after delay by delay circuit 41 to the reset side
to “one” at the time a sense pulse is applied to the ring.
While the invention has been particularly shown and
of fiip-flop 43 to set that flip-flop to its “zero” state. The
pulse received on conductor 9 ,after application to the
described with reference to a preferred embodiment there
clock pulse generator is applied to delay circuit 44 and
after suitable delay samples gates 49 and 51. The pulse
is passed by gate 49 conditioned by a D.C. level from
the “zero” side of flip-flop 47. Delay 44 is selected to
the foregoing changes and other changes in forml and de
of, it will be understood by those skilled in the art that
tails may be made therein Without departing from the
spirit and scope of the invention.
What is claimed is:
1. A checking circuit for a ring of storage units each
provide a longer delay than delays 37 and 41 to allow
flip-flop 43 to be reset to “zero” before a pulse is passed 10 of which is capable of storing an information item,
by gate 49. Thereupon the pulse passed by gate 49
~ comprising,
means for sensing the storage condition of the last
samples gate 35 which has been deconditioned as flip
flop 43 has been reset to “zero” The pulse received on
conductor 9 after delay in delay circuit 44 is also .applied
to the complement input of flip-ñop 47 after further delay
by delay circuit 45 to set flip-flop 47 to its “one” state.
The next pulse received >on conductor 9 is passed by an
first control means associated with said first storage
unit normally effective when a first information
item is stored in said first storage unit for con
even numbered gate as an even pulse and delivered to
and second control means associated with predeter
mined storage units successive to said first storage
Or circuit 31. The even pulse samples gate 35 which is
deconditioned as flip-liep 43 is set to “Zero.” The even
storage unit of said ring,
Y
4trolling said sensing means,
unit and rendered effective when one of said suc
»cessive storage units has a second information item
stored therein for inhibiting the operation of said
-fìrst control means when said first information item
is stored in said first storage unit,
by delay circuit 44 samples gates 49 and 51 and is passed
said sensing means activated when said second informa
by gate 51 presently conditioned by the “one” side of
tion item is subsequently stored in said last storage
flip-flop 47 to sample gate 39 which is deconditioned as
unit to produce a signal indicating that more than
hip-flop 43 is set to “one” at this time. Flip-flop 47
one of said plurality of storage units has an in
is then complemented to its “zero” state after delay by
formation item stored therein.
delay circuit 45. Thus, during normal operation of the
2. A checking circuit for a ring of bistable devices
ring counter, ilip-ñop 43 is set and reset to insure that no 30
comprislng,
s pulses from Or circuits 31 and 33 are passed by gates 35
. means for sensing the storage conditions of the last bi
Aand 39. Flipdlop 47 is complemented alternatively to its
stable device of said ring,
“öne” and “zero” states to condition gates 49 or 51 to
first control means for sensing the storage condition
passa pulse from oscillator 8 which during a normal
of said first bistable device normally effective for
35
operation samples deconditioned gates 35 and 39.
controlling sai-d sensing means When said first -bi
Y The `detection of two flip-flops set to their “one” state
stable device is set to the “one” state,
during the same interval between sense pulses and either
and second control means associated with predeter
adiacenti-or separated by an even number of flip-flops will
mined bistable devices successive to said 4first bi
next be described. Assume for instance that the four and
stable device and rendered effective when one of
seven flip-flops 24 and 2.7, respectively, are set to the “one" 40
said successive bistable devices is set to the “one”
state. The next pulse received on conductor 9 is passed
state for inhibiting the operation of said first con
by gate 14 which is conditioned by flip-flop 24 in its “one”
trol means when said ñrst bistable device is also set
state and is also passed by gate 17 which is conditioned
pulse, `after delay by delay circuit 37 is applied to the
“one” side of Hip-flop 43 to set that flip-flop to its “one”
state. The pulse received on conductor 9 after delay
i
by flip-Hop 27 in its “one” state. The pulses passed by
gates 14 and 17 are applied to Or circuits 31 and 33 re 45
spectively, the outputs of which sample gates 35 and
39. Flip-flop 43 has previously been set to its “one” state
or reset to its “Zero” state so either gate 35 or 39 is con
ditioned. Therefore, gate 35 or 39 passes a pulse to Or
circuit 61 which is delivered on conductor 63 to an alarm 50
device I64 to indicate that an error has occurred.
The detection of a missing pulse will next be described.
Assume that flip-liep 43 is reset to “Zero” and flip-flop 47
is set to “one” Assume also that the last pulse delivered
by the ring was an odd pulse and now the pulse circulating 55
in the ring is lost. Thus flip-flop 43 is not set and remains
in its “zero” state producing a D_C. level to condition
gate 39. The next pulse received on conductor 9 after
delay in delay circuit 44 samples gates 49 and 51. Gate
51 (conditioned by the “one” side of flip-flop 47) passes 60
the pulse which then samples and is passed by` gate 39
(conditioned by the “zero” side of hip-flop 43). The
pulse passed by gate 39 is applied to Or circuit 61 and
delivered on conductor 63 to an alarm device 64 to indi
cate that an error condition has been detected in the ring 65
counter.
In summary, checking circuitry has been described
which signals an alarm When two or more ñip-ñops sepa
rated by an odd number of flip-flops are set to the “one”
state during the same interval between sense pulses. Ad
ditional checking circuitry signals an .alarm when two or
more flip-flops adjacent or separated by an even number
of flip-flops are set to the “one” state during the same
interval between sense pulses. Further circuitry has been
described which signals an alarm when no flip-flop is set 75
to the “one” state,
`
said sensing ’means activated when said last bistable
device is subsequently set -to the “one” state to pro
duce a signal indicating that more than one of said
bistable devices are set to the “one” state at the
same time.
`
»
3. A checking circuit for a ring of storage units
comprising,
means for sensing the Aoutput signals of the‘first and
last storage units of said ring,
first control means for sensing the output signal of
said first storage unit normally effective for con
trolling said sensinlg means when a ñrst informa
tion -item is stored in said first storage unit,
second control means associated with pre-determined
storage units successive to said first storage units
and rendered effective when one of said successive
storage units has a second information item stored
therein for inhibit-ing the operation of said ñrst con
trol means When said ñrst information item is stored
in said first storage unit,
said sensing means activated when said second in
formation item is subsequently stored in said last
storage unit `and being effective to produce a signal
if said second information item is subsequently stored
in said Ifirst storage unit,
Y
and means operatively coupled to said sensing means
and responsive to the signal produced thereby for
producing an indication that more than one informa
tion item is stored in the ring of storage units at
the same time.
7
4. A checking circuit for a ring of storage units each
of which is capable of storing an information item,
comprising,
means for sensing the storage condition of the first
and last storage units of said ring,
gating means for sensing the storage condition of said
first storage unit normally effective for controlling
said sensing means if first information item is stored
in said first storage unit,
and an And-.Not circuit associated with predetermined
storage units successive to said first storage unit and
rendered effective when one of said successive stor
age units has a second information item stored
therein for inhibiting the operation of said gating
means when said first information item is Stored 15
to the “zero” state for conditioning said first control
means,
said first control means When conditioned being effec
tive if said first bistable device is set to the “one” state
for controlling said checking circuit to prohibit the
production of an output signal when only one bi
stable device of said ring is set to “one”
8. A control circuit for a checking circuit associated
with a ring of storage units, each of which is capable of
storing an information item,
said checking circuit effective to produce an output sig
nal when one or more of said storage units of said
ring has an information item stored therein,
comprising,
gating means for sensing the storage condition of the
in said first storage unit,
first storage unit of said ring,
said sensing means activated when said second in
and an And-Not circuit associated with predetermined
formation item is subsequently stored in said last
storage units successive to said first storage unit and
storage unit to produce a signal indicating that more
rendered effective when all of said successive pre
than one of said plurality of storage units has an 20
determined storage units have no information items
information item stored therein.
stored therein for conditioning said gating means,
5. A checking circuit for a ring of storage units each
said gating means when conditioned being effective if an
of which is capable of storing an information item,
information item is stored in said first storage unit
comprising,
for controlling said checking circuit to prohibit the
means for sensing the storage condition of the first 25
production of an output signal when only one stor
and last storage units of said ring,
age unit of said ring has an information item stored
gating means for sensing the storage condition of said
therein.
first storage unit normally effective for controlling
9. A control circuit for a checking circuit associated
said sensing means when a first information item is
with a ring of storage units, cach of which is capable of
stored in said first storage unit,
30 storing an information item,
and an And circuit associated with predetermined
said checking circuit effective to produce a signal when
storage units successive to said first storage unit and
one or more of said storage units has an information
rendered effective when one of said successive stor
item stored therein,
age units has a second information item stored there
in for inhibiting the operation of said gating means 35
when said first information item is stored in said
first storage unit,
said sensing means activated when said second in
formation item is subsequently stored in said last
storage unit to produce a signal indicating that more 40
than one of said plurality of storage units has an
information item stored therein.
6. A control circuit for a checking circuit associated
with a ring of storage units, each of which is capable of
storing an information item,
45
said checking circuit effective to product an output
signal when one or more of said storage units of
said ring has an information item stored therein,
comprising,
gating means for sensing the storage condition of the
first storage unit of said ring,
~
and an And circuit associated with predetermined stor
age units successive to said first storage unit and
rendered effective when all of said successive pre
determined storage units have no information items
stored therein for conditioning said gating means,
said gating means when conditioned being effective if
an information item is stored in said first storage
unit for controlling said checking circuit to prohibit
the production of an output signal by said checking
circuit -when only one storage unit of said ring has
an information item stored therein.
10. A checking circuit for a ring of bistable devices,
comprising,
each of which produces an output signal when set to the
first control means associated with the first storage 50 “one” state,
unit of said ring,
and second control means associated with predeter
mined storage units successive to said first storage
unit and rendered effective when all of said succes
sive predetermined storage units have no information 55
items stored therein for conditioning said first con
trol means,
said first control means when conditioned being effec
tive if an information item is stored in said first
storage unit for controlling said checking circuit to 60
prohibit the production of an output signal when
only one storage unit of said ring has an informa
tion item stored therein.
7. A control circuit for a checking circuit associated
with a ring of bistable devices,
65
said checking circuit effective to produce an output
signal when one or more of said bistable devices of
said ring are set to the “one” state,
comprising,
comprising,
means for sensing the output signal of the last bistable
device of said ring,
ñrst control means associated with said sensing means,
second control means for sensing the output signal of
the first bistable device of said ring, said second con
trol means responsive to an output signal from said
first «bistable device and effective to apply a first con
trol signal to the first control means,
said first control means normally effective to apply said
first control signal to said sensing means,
and third control means associated with the bistable
devices successive to said first bistable device and
rendered effective when one of said successive bi
stable devices produces an output signal to apply a
second control signal to inhibit the operation of
said first control means when an output signal is pro
duced by said first bistable device,
said sensing means subsequently responsive to an
output signal from said last bistable device to produce
an indication that more than one signal is circulating
in the ring of bistable devices at the same time.
first control means for sensing the storage condition 70
of the first bistable device of said ring,
and second control means associated with predeter
mined lbistable devices successive to said first pre
11. A checking circuit for a ring of bistable devices,
determined bistable device and rendered effective
each of which produces an output signal when set to the
when all of said successive bistable devices are set 75 “one” state,
:3,088,095
10
9
comprising,
an odd number of bistable devices is circulating in
the ring of bistable devices at the same time,
and means associated with said ring for detecting and
indicating when more than one signal adjacent to
another signal or separated by an even number of
bistable ldevices is circulating in the ring of bistable
means for sensing the output signal of the last bistable
device of said ring,
ñrst control means associated with said sensing means,
Isecond control means for sensing the output signal of 5
the first bistable device of said ring, said second con
`devices at the same time.
trol means responsive to an output signal from said
13. A checking circuit `for a ring of bistable devices,
first bistable device and eliective to apply the lirst
each of which produces an output signal when set to the
control signal to the Íirst control means,
said first control means normally effective to apply said
“one” state,
comprising,
ñrst control signal to said sensing means,
means for `sensing the output signal of the last bistable
third control means associated with the bistable devices
successive to said first bistable device and rendered
device of said ring,
effective when one of said successive bistable devices
produces an output signal to apply a second control
signal to inhibit the operation of said first control
means when an output signal is produced by said ñrst
bistable device,
said sensing means subsequently responsive to an out
put signal from said last bistable device to produce an
indication that more than one signal is circulating
in the ring of bistable devices at the same time,
and means associated with said ring for detecting and
indicating when no signal is circulating in the ring of
25
bistable devices.
l2. A checking circuit for a ring of bistable devices,
each of which produces van output signal when set to the
“one” state,
comprising,
means for sensing the output signal of the last bistable 30
ydevice .orf Said ring,
first control means associated with said sensing means,
second control means for sensing the output signal of
the first bistable device of said ring, said second
control means responsive to an output signal from 35
said first bistable device and effective to apply a iirst
licontrol signal to the first control means, said control
means normally effective to apply said ñrst control
signal to said sensing means,
third control means associated with the even numbered 40
bistable `device successive to said first bistable device
.and rendered effective when one of said successively
even numbered bistable devices produces an output
signal to apply a second control signal to inhibit the
operation of said first control means When an output 45
signal is produced by said first bistable device,
said sensing mean-s subsequently responsive to an output
signal from said last bistable device to produce an
indication that more than one signal separated by
tirst control means associated `with said sensing means,
second control means for sensing the output signal of
the first bistable device of said ring, said second
control means responsive Vto an output signal from
said Ifirst bistable device and effective to apply a first
control signal to the first control means, said control
means normally effective to apply said iirst control
.signal to said sen-sing means,
third `control means associated with the even numbered
bistable device successive to said ñrst bistable device
and rendered effective when one of said successively
even numbered bistable devices .produces an output
signal to apply a second control signal to inhibit the
operation of said ñrst control means when an output
signal is produced by said first bistable device,
said sensing means subsequently re-sponsive to an out
put signal `from said last bistable device to produce
an indication that more thanone signal separated
by an odd number of bistable devices is circulating
inthe ring of bistable devices at the same time,
means associated with said ring for detecting and indi
cating when more than one signal adjacent to an
other signal »or separated by an even number of lbi
stable devices is circulating in the ring lof bistable de~
vices at the same time.
and means associated with said ring for detecting and
indicating when no signal is circulating in the ring
.of bistable devices.
References Cited in the file of this patent
UNITED STATES PATENTS
2,724,104
Wild ____ __K ___________ __ Nov. 5, 1955
2,769,9711>
Bashe ________________ __ Nov. 6, 1956
Abzug _______________ __ Jan. 16, 196-2
3,017,620
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