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Патент USA US3088419

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May 7,. 1963
Filed Nov. 28, 1960
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Patented May 7, 1963
of timing stability over a relatively wide range of oper
ating temperatures.
‘Other objects and many of the attendant advantages
Irvin S. Yavelberg, Tucson, Ariz., assignor to the United
of this invention will be readily appreciated as the same
States of America as represented by the Secretary of
5 becomes better understood by reference to the following
the Navy
Filed Nov. 28, 1960, Ser. No. 72,257
detailed description when considered in connection with
2 Claims. (Cl. 102-702.)
the accompanying drawings wherein:
(Granted under Title 35, US. Code (1952), sec. 266)
FIG. 1 is a schematic diagram of a unijuncion tran
sistor timing circuit in accordance with principles of the
The invention described herein may be manufactured 10 invention; and
and used by or for the Government of the United States
FIG. 2 is a schematic diagram of a modi?ed unijunc
of America for governmental purposes Without the pay
tion transistor timing circuit employing a single DC.
ment of any royalties thereon or therefor;
The present invention relates to timing means, and
power source.
Referring now to FIG. 1, the unijunction transistor 10
particularly to a squib-?ring electronic timing apparatus. 15 may be of conventional type consisting of a small bar of
‘While adaptable for use in many different types of
uniformly doped N-type silicon having ohmic contacts
equipment, the invention is of special utility in missile
identi?ed as B1 (base-one) and B2 (base-two) at its two
destructor fuze apparatus and will be described principal
ends, and a single rectifying PN junction identi?ed as
ly with reference to such apparatus.
emitter E. Unijunction transistor 10 presents a conduction
control feature somewhat similar to that of a gas thyra
air missiles be prevented from endangering objects beyond
tron. In particular, until a control voltage of positive
the target, or property and personnel on the ground be
polarity applied to emitter E assumes a critical threshold
low, and for this reason such missiles must include means
value of the order of six-tenths of the inter-base voltage,
operative to accomplish self-destruction of the missile
emitter E is in eifect reverse-biased, and the unijunction
while still aloft and at a predetermined distance beyond 25 transistor is said to be cut off, essentially so except for a
the launching point or, more conveniently, at a predeter
so-called reverse or back current of comparatively small
mined time after the launching instant, in the event the
magnitude in the emitter circuit. When the critical
missile has passed its intended target. The self-destruc
threshold value of control voltage is reached, however,
tion means requires an explosive charge (conveniently,
the emitter E becomes forward-biased, and the resistance
that already carried in the warhead), and a missile de
between emitter electrode E and base electrode B1 of the
structor fuze apparatus preferably including a destructor
transistor drops sharply to a comparatively low value, en
squib and timing means to effect electrical detonation or
abling destructor squib 11 to be flashed, as will appear.
?ashing of the destructor squib. Simplicity, sturdiness,
Separate DC. power sources 12 and 13 are provided,
It is often of importance that air-to-air or ground-to
compactness and low Weight being at a premium in missile
in the FIG. 1 embodiment, for supplying the unijunction
design, it is particularly advantageous to employ a timing 35 transistor base-to-base voltage, and for supplying capaci
device of unijunction transistor type which makes it pos
tor charging current to the integrating circuit comprising
sible to achieve such characteristics, provided that such
adjustable resistor 14, and capacitors 15 and 16 having
a timing device can also be made to yield substantially
substantially the same capacitance and leakage current
constant timing (for any selected setting) over the wide
characteristics. These power sources 12 and 13 are most
temperature range called for by military speci?cations.
practically and conveniently provided in the form of bat
Unijunction transistor type of timing devices make use
teries, as indicated, and the power circuits are arranged
of an integrating circuit wherein the voltage developed
to remain open until actuation of switches 17 and 18.
across a capacitor as a function of charging time reaches
Switches 17 and 18, forming part of an acceleration-re
a transistor “?ring” value upon expiration of a predeter~
sponsive mechanism 19 which may be of any conven
mined charging interval, hereinafter termed the squib 45 tional type ‘(therefore not shown in detail) such as em
flashing delay-time. For use in missile self-destruction
apparatus as indicated, the squib-flashing delay-time, as
measured from substantially the missile launch instant,
must be comparatively long, say 60 seconds by way of
example. The integrating circuit, further, must be so de
signed that suf?cient energy will have accumulated in the
charging capacitor, at the intended self-destruction in
stant, to effect ?ashing of the destructor squib. It there
fore becomes impractical to employ a charging capacitor
ployed for missile arming, are to be understood as being
thrown into closed condition by mechanism 19, to start
the timing function of the unijunction transistor circuit,
provided the missile functions successfully to execute
rapid acceleration. Relative to the instant at which the
switches 17 and 18 are closed, the control voltage de
veloped across capacitor 16 reaches the ?ring threshold
value after a so-called delay-time dictated by the ohmic
value of resistance provided by adjustable resistor 14, the
of any type other than an electrolytic capacitor of com 55 microfarad values of capacitors 15 and 16, and the mag
paratively large microfarad value, preferably a tantalum
nitudes of the voltages delivered by sources 12 and 13.
capacitor because of its extreme compactness. It has
It has been found that with compensating capacitor 15
been found, however, that over the typical military spec
and ?ring capacitor 16 of exactly the same type and se
i?cation range of temperatures, say —-50° to +150° on
lected to exhibit the same values of capacitance and leak
the Fahrenheit scale, the change in leakage resistance 60 age resistance at normal temperature and, corresponding
(and correspondingly of leakage current), of a tantalum
ly, like characteristics of capacitance and leakage resist
capacitor as heretofore employed in timing devices broad~
ance variations with temperature change, the timing func
tion for any given setting of resistor 14 remains reason
ly of the type hereunder consideration, may be so large
ably constant over the rather wide military speci?cation
as to result in delay-time variations of the order of 100
percent, far too great to be tolerated in missile destructor 65 temperature range indicated above. For example, a test
version of the FIG. 1 circuit, employing a unijunction
fuze apparatus.
transistor of commercially available 2N489 type, sources
It is therefore the principal object of the present in
12 and 13 respectively delivering 15 and 30 volts, tanta
vention to provide a missile destructor fuze apparatus
lum capacitors each of 100 microfarad value and rated
having improved reliability.
70 at say 30 volts, and a series charging resistance of 1.4
It is another object of the invention to provide a uni~
megohms, has exhibited a squib-?ashing delay-time of
junction transistor timing device providing a high degree
approximately 60 seconds with variations of only about
combination: a destructor squib; a unijunction transistor
having an emitter electrode and a pair of base electrodes;
5 percent over the temperature range of —50° F. to
+170° F.
means for providing a predetermined potential gradient
FIG. 2 concerns a modi?cation providing like timing
stability, but presenting further improvement as to com
pactness and low weight by use of a single tapped battery
comprising sections 20 and 21, and a compensating re
in said unijunction transistor between said base elec
trodes and correspondingly establishing a predetermined
value of peak point emitter voltage for ?ring said uni
junction transistor; a series-charging network compris
sistor 22, as illustrated. Battery section 20 serves as the
ing a source of voltage, a switch, a resistor, a compen
source of interbase voltage for unijunction transistor 10,
and battery sections 20 and 21 are additive as to the
sating tantalum capacitor, and a ?ring tantalum capacitor,
20 to a yield voltage of about four-tenths of the addi
tive voltage. Resistor 22 is of suitable ohmic value to
said switch; said ?ring capacitor, squib, and unijunction
battery section 21 as is imposed upon battery section
20 by unijunction transistor 10, in this manner serving
to maintain substantially the same ratio of terminal volt
ages supplied by the battery sections under varying con
?ring capacitor through said squib and said emitter elec
trode when the ?ring capacitor voltage reaches said pre
determined value of peak point emitter voltage; and said
charging voltage applied to the series circuit of resistor 10 to effect charging of said ?ring capacitor to said predeter
mined value of peak point emitter voltage upon expiration
14 and capacitors 15 and 16. Near-optimum battery
of a predetermined time delay initiated upon closing of
compactness is provided by selection of battery section
transistor being connected in circuit to effect ?ashing of
impose a current drain of about the same magnitude on 15 said squib by conduction of discharge current from said
capacitors having balancing temperature-dependent char
acteristics which render said predetermined delay time
substantially independent of ambient temperature changes.
ditions, as necessary to maintain the same timing func
tion for a given setting of resistor 14.
Firing or ?ashing of squib 11 in the FIG. 1 and FIG.
2. A missile destructor fuze apparatus comprising, in
combination: a destructor squib; a unijunction transistor
2 circuits is effected by discharge of capacitor 16 through
having an emitter electrode and a pair of base electrodes;
squib 11, enabled at the instant when the control volt
age developed in the capacitor has reached the critical 25 a battery having a section thereof connected across the
base electrodes of said unijunction transistor to provide a
value, sometimes termed the “?ring” or peak point emit
predetermined potential gradient therebetween and cor
ter voltage, which establishes a forward-bias condition
respondingly establishing a predetermined value of peak
for emitter E. In a typical instance squib 11 may present
point emitter voltage for ?ring said unijunction transistor;
a resistance of approximately 5 ohms and may require
about 5000 ergs of electrical energy to ?ash it. Assum
30 a compensating current-drain resistor connected across the
ing that the peak point emitter voltage required to “?re”
remaining section of said battery; a series-charging net
the unijunction transistor 11 is of the order of say 10
volts, the energy accumulated in capacitor 16 at that
time would be 50,000 ergs, well above the squib-?ash
ing energy requirements in order to insure strong ?ash 35
work comprising said battery, a switch, a resistor, a com
ing and explosive ignition action.
While the FIG. 1 and FIG. 2 circuits provide stability
of squib-flashing delay-time by means of a pair of series
connected like capacitors having compensating leakage
current characteristics, for use in a non-adjustable or 40
narrowly adjustable timer intended to provide substan
tially ?xed rather than widely variable delay-time, it is
also feasible to employ a single capacitor, in place of the
pair of series-connected capacitors, presenting capaci
pensating tantalum capacitor, and a ?ring tantalum ca
pacitor, to effect charging of the ?ring capacitor to said
predetermined value of peak point emitter voltage upon
expiration of a predetermined time delay initiated upon
closing of said switch; said ?ring capacitor, squib and uni
junction transistor being connected in circuit to effect
?ashing of said squib by conduction of discharge cur
rent from said ?ring capacitor through said squib and said
emitter electrode when the ?ring capacitor voltage reaches
said predetermined value of peak point emitter voltage;
and said capacitors having balancing temperature-depend
ent characteristics which render said predetermined de
tance and leakage resistance characteristics which vary 45 lay time substantially independent of ambient temperature
oppositely with temperature and combine to yield the
necessary transistor-?ring control voltage at substantially
References Cited in the ?le of this patent
constant delay-time over the speci?ed operating tem
perature range.
Obviously many modi?cations and variations of the 50
Morison et al. ________ __ Sept. 29, 1959
present invention are possible in the light of the above
teachings. It is therefore to be understood that within
the scope of the appended claims the invention may be
______________ __ Dec. 29, 1956
practiced otherwise than as speci?cally described.
France ______________ __ Dec. 21, 1959
55 1,218,809
What is claimed is:
1. A missile destructor fuze apparatus comprising, in
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