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Патент USA US3089143

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May 7, 1963
3,089,134
J L ROBINS N
METHOD AND SYSTEM FOR ENCODING A SIGNAL
INTO BINARY CODE GROUPS
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METHOD AND SYSTEM FOR ENCODING A SIGNAL
INTO BINARY CODE GROUPS
Filed March 25, 1960
3,089,134
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United States Patent 0 "
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3,089,134
Patented May 7, 1963
2
1
FIG. 2 is a symbolic and block diagram of one system
3.089.134
METHQD ANT) SYSTEM FOR ENCODING A
SlitGNAL KNTQ EINARY CUBE GROUPS
John L. Robinson, Wenonah, Ni, assignor, by mesne as
signments, to Phiico Corporation, Philadelphia, Pa., a
corporation of Deiaware
Fitted Mar. 25, 1960, Ser. No. 17,579
6 Claims. (Cl. 340-347)
according to this invention;
FIG. 3 is a timing diagram which will better enable
an understanding of the operation of the system shown
in FIG. 2;
FIG. 4 is a schematic diagram of one form of ampli~
tude comparator which may be used in the system of
FIG. 2;
,FIG. 5 is a schematic diagram of one form of de
This invention relates to systems for binary encoding 10 coder which may be used in the system of FIG. 2; and
FIGS. 6 to 8 are explanatory of the symbols employed
of a signal, i.e. encoder systems of the type wherein the
instantaneous amplitude of a signal, such as a speech
in FIG. 2.
Referring ?rst to FIG. 1, by way of example, it is
signal, is represented by a binary code group.
assumed that in the binary code employed each binary
More particularly, this invention relates to feedback
or comparison systems, the basic form of which is shown 15 code group or number contains four of the digits or
binary code elements 0 and 1. In such case there are
and described in an article by B. D. Smith, entitled
16 binary numbers as shown, which represent different
“Coding by Feedback Methods,” at pages 1053 to 1058
reference voltage levels and which de?ne small portions
of the Proceedings of the I.R.E. for August 1953.
or sub-ranges of the signal amplitude range. In other
In prior systems of this type, each encoding cycle has
required a number of encoding operations corresponding 20 words, the amplitude range over which the signal varies
is divided into sixteen sub-ranges as indicated, and the
to the number of binary code elements in the binary
amplitude within each of these sub-ranges is represented
code group which represents the instantaneous ampli~
by the lower binary number.
tude of the signal. For example, in a system employa
__ Suppose, for example, that the amplitude of the signal
ing four binary code elements in each binary code group,
each encoding cycle would require four encoding op 25 to be encoded at some given instant is within the ?fth
sub-range as indicated by the broken line. To deter
erations.
mine this and to encode'the signal, the binary numbers
The need for higher speed signal encoding has en
0100, 1000 and 1100 are ?rst decoded to produce three
gendered various proposals to meet this need. However,
reference voltages representative respectively of the am
such proposals have not been entirely satisfactory for
30 plitude levels L1, L2 and L3. Then the signal amplitude
one reason or another.
is compared With each of said voltages and it is deter
One object of the present invention is to provide a
mined that the amplitude of the signal sample is within
high speed encoding system which will satisfactorily meet
the sub-range L1—L2 wherein the ?rst two binary code
the need for such a system.
Another object of the invention is to provide an im
elements of each binary code group are 01.
The results
proved feedback or comparison system wherein high 35 of the comparisons are therefore encoded into the binary
code elements 0 and 1. Then the binary numbers 0101,
speed encoding is achieved by multiple encoding opera
0110 and 0111 within the sub-range L1—L2 are decoded
tions, each of which produces a plurality of binary code
to produce three reference voltages representative respec
elements.
tively of the ‘amplitude levels L4, L5 and L6. The signal
This invention is based on the concept of repetitive
production of plural binary code elements to produce the 40 amplitude is compared with each of the latter reference
voltages and it is determined that the amplitude of the
binary code group representative of the instantaneous
signal is within the sub-range represented by the number
amplitude of a signal. For example, where each binary
0100. The results of the latter comparisons are there
code group comprises four binary code elements, each
fore encoded into the binary code elements 00, thus com
encoding cycle, instead of involving four encoding op
pleting
the encoding of the instantaneous amplitude of
erations, may involve two encoding operations each‘ pro 45
the signal into the binary code group 0100.
ducing two of the binary code elements. Thus the en
From the foregoing description it will be seen that
coding speed is doubled.
the encoding process of the present invention involves
In a system according to this invention, reference volt
ages are produced and are compared with the amplitude
the employment of reference voltages which are succes
of the signal being encoded at any instant may be at
p-n-p transistors, although n-p—n transistors could be em
of the signal being encoded to produce the binary code 50 sively de?nitive of decreasing sub-range portions of the
signal range.
elements. By repetitive comparison of the signal with
Referring now to FIG. 2, there is shown a system for
plural reference voltages, the amplitude of the signal is
encoding successive samples of the amplitude of a signal
determined and is represented by a binary code group.
in the manner described above with reference to FIG. 1.
To explain this further, the amplitude of the signal
varies over a given range, and therefore the amplitude 55 As hereinafter described, the illustrated system employs
any level within said range. By comparing the signal
ployed. With p-n-p transistors, the signal is of negative
binary code elements. Then by comparing the signal
25 and 26 and are supplied to the comparators over con
polarity. The system comprises three comparators 20,
with each of a number of reference voltages represent
21 and 2.2, to each of which the signal is supplied via. the
ing different amplitude levels within said range, it is
determined that the amplitude of the signal is within a 60 input connection 23. The reference voltages for com
parison with the signal are produced by three decoders 24,
certain sub-range, and this information is encoded into
nections 27, 28 and 29. The system further comprises the
with each of a number of reference voltages representing
stonage register 30 which may comprise four bistable cir
different amplitude levels within said sub-range, it is
determined that the amplitude of the signal is within a 65 cuits 311 to 34 for storing four binary code elements. The
system also comprises bistable circuits 35 and 36 whose
vertain portion of said sub-range, and this information
purpose
is to store the results of a set of comparisons
is encoded into binary code elements.
while transferring into the storage register. If the results
The invention may be fully understood from the fol
of a set of comparisons were not stored in bistable circuits
lowing detailed description with reference to the accom
35 and 36 ‘the following might happen: The outputs of
panying drawings wherein:
70 the comparators might change thus changing the contents
FIG. 1 shows a binary code and illustrates the prin
of the storage register. This would change the outputs
ciple on which the present invention operates;
3
3,089,134
of the decoders which in turn would change the outputs
of the comparators, and a type of oscillation could thus
build up.
The other components of the system designated symbol
ically are of the character hereinafter described. Pro
gram ‘or timing pulses P1 to P5 (FIG. 3) for operating the
system are supplied (to the lines in FIG. 2 similarly desig
nated. The pulses may be produced by conventional de
4
FIG. 2 may be of the form shown in FIG. 5 which com
prises transistors 48 to 51, resistors 52 to 55 related as
indicated, and common load resistor 56.
The operation of each decoder will be explained with
reference to FIGURES 2 and 5.
Referring ?rst to FIG
URE 5, it will be assumed that resistor 56 is small com
pared to the resistors 52 through 55 so that the voltage at
the output is not large enough to effect the current through
vices such as ring counters.
any ‘of the branches containing resistors 52 through 55.
Referring to 'FIG. 3, the pulses there shown for use in 10 Furthermore, it will be assumed that: A current i flows in
the system of FIG. 2 are all negative, that is in each of
resistor 55 when transistor 51 is turned on; a current 21'
the ?ve waveforms the upper level represents the inactive
flows in the branch containing resistor 54 when transistor
or normal state of the line while the lower level represents
50 is turned on, etc. If transistors 48 through 51 are
the active state of the line. However, the system could be
thought of as being turned on by binary signals applied
designed for use of positive pulses.
to ‘their bases, the currents through the various branches
With respect to the system components, each of the
add in resistor 56 to provide a voltage at the output which
comparators 2%, ‘2.1 and 22 in the system of FIG. 2 may be
is linearly related to the binary number applied. Tran
of the form shown in FIG. 4 which comprises transistors
sistor 48 receives the most signi?cant bit, transistor 49 the
37 and 33, diodes 39 and 40‘, and resistors v41 to 47, con
second most signi?cant bit, transistor 50 the third most
nected as shown.
signi?cant ‘bit, and transistor 51 the least signi?cant bit.
The operation of each comparator will be explained
For the circuit shown, a One in any digit position may be
with reference to FIGURE 4. Resistors 41, 42, 43, 45,
represented by a negative voltage on the base of the ap
and 46 are relatively large resistors returned to rather high
propriate transistor. The output voltage increases in a
supply voltages; therefore, the currents through these re
positive direction for increasing values of the binary num
sistors will be considered constant. Resistors 41, ‘43, and
ber applied to the bases of transistors 48 through 51.
46 will be assumed to conduct a constant current, i in the
Referring to FIGURE 2 the input lines to the decoders
direction shown in the ?gure, and resistors 42 and 45
are normally at ground so that an active line, or a One,
will be considered to conduct a constant current 1.5i
into a decoder results in a negative voltage at the base
of the corresponding transistor. Thus if lines 68 and
30 69 into decoder 24 go active and lines 79 and 80 are
which is also common to the emitters of the two ‘transistors,
normal, this corresponds to the binary number 1100 in
in the direction shown.
The current through resistor 41 flows into node 111
37 and 38. The current through resistor 41 will ?ow
from node n1 into the emitter of the transistor having the
more negative base voltage. For example, assume that
the signal supplied to the base of transistor 37 is more
negative than the signal supplied to the base of transistor
FIG. 1 and the decoder produces an output voltage repre
sentative of the reference level L3 in FIG. 1.
The symbolic showing in FIG. 2 of the other system
35 components will now be explained in terms of direct
coupled transistor circuits. In practice other types of
38. Transistor 37 will conduct the current from node 11;
coupling could just as well be used; however, the direct
and the emitter of transistor 37 will be positive with re
coupled circuits are chosen for the examples in the in
spect to its base by a small voltage equal to the diode
terests of simplicity.
drop in the transistor. If the base voltage of transistor 38
is positive relative to the base voltage of transistor 37 by 40 ‘ The symboloigy consists of circuit elements connected
by lines. In the illustrated system, p-n-p transistors are
an amount 'equal to or greater than the diode drop of a
conducting transistor then transistor 38 will be cut olf.
When transistor 37 is conducting and transistor 38 is
employed, and a line can be either at ground or at a
which must ?ow to ground through resistor 44. This
go active, and lines normally negative go to ground when
negative potential. The output line of a circuit changes
from its normal to its active value when the circuit is
cut off a current nearly equal to i will ?ow from the
collector of transistor 37 into n2. However, a current of 45 performing its logical function. Lines which are nor
mally at ground are represented by solid lines, and lines
1.51‘ will flow from n2 through resistor 42; therefore, a
which are normally negative are represented by broken
current ‘of 0.51‘ must flow from In; through the zener diode
lines. Lines normally at ground go negative when they
39 ‘to n2. This leaves a net current of 0.5i ?owing into n;;
results in a positive voltage at 113 and also on the left out 50 they go active.
Referring now to FIG. 6(a), there is shown a tran
put line. Referring to the right collector circuit, no cur
sistor 5‘7 and its load resistor 58. The base, emitter and
rent ?ows from the collector of transistor 38; therefore, a
collector lines are designated by letters b, e and c. The
current of 1.5i must ?ow from n; to n5. This leaves a
symbol therefor is shown in FIG. 6(1)). According to
net current of 0.5 i ?owing from n4 which must come from
ground through resistor 47. This results in a negative 55 this symbolic showing, b is normally at ground and c
and e are normally negative, and the transistor is nor
voltage at n.,, and also ‘on the right output line. As will
mally turned off and it is turned on and 0 goes active
be seen from the subsequent description, it is the negative
only when b and e are both active. If the emitter is
output voltage which is effective.
connected to ground, only b needs to go active and the
If the relative polarities of the input voltages are re
versed transistor 37 will be cut off and transistor 38 turned 60 emitter line is omitted from the symbol as shown in
FIG. 6(c).
on, in which case the currents in resistors 44 and 47‘ will
be reversed and the output signals will switch. The out
Referring now to FIG. 7(a), there is shown a circuit
put signals of the comparator, therefore, indicate the rela~
comprising two transistors 59 and 60 in series and a load
tive polarities of the input voltages.
resistor 61. The two base lines are designated b1 and
It is possible, when the comparator input voltages are 65 b2. This circuit is represented by either of the symbols
very nearly equal, to have both transistors 37 and 38 con
shown in FIGS. 7 (b) and 7(0). According to each sym
ducting part of the emitter current; however, as long as the
bol, c is active only when b1 and b2 are both active.
input voltages differ by some small amount the output
vReferring now to FIG. 8(a), there is shown a bistable
voltages will be of the proper polarity, and while the
circuit which may be employed for each of the bistable
output voltages will be reduced in amplitude this will not
circuits in the system of FIG. 2. The circuit comprises
prevent the successful operation of the system.
transistors 62 to 65 and load resistors 66 and 67. When
The reason for the zener diodes in the collector circuits
is to keep a negative voltage on the collectors of the
transistors and thus prevent saturation.
Each of the decoders 24, 25 and 26 in the system of
b1 goes negative, transistor 62 is turned on and conse
quently transistor 64 is turned off, transistor 63 is turned
on, and 01 goes negative. When b2 goes negative, tran
sistor 65 is turned on and consequently transistor 63 is
3,089,134
5
turned off, transistor 64 is turned on, and 02 goes nega
tive.
FIG. 8(b) shows the symbolic representation of the
6
sixteen numbered sub-ranges in FIG. 1, the operation
through an encoding cycle can readily be traced.
From the foregoing description, it will be seen that the
circuit. When line b1 is active, line (:1 is active and re
mains so until line b1 becomes normal or inactive and
encoding process according to this invention comprises
successively producing plural reference voltages, compar
line b2 becomes active. Similarly when line b2 is active,
line 02 is active and remains so until line b2 becomes nor
mal and line b1 becomes active. When line 01 is active,
code group representative of the amplitude of the signal.
ing the signal with each of the reference voltages, and
translating the results of the comparisons into a binary
It should be noted that the precision of a system accord
it is representative of storage of a “zero,” and when 02
is active it is representative of storage of a “one,” as in 10 ing to this invention may be increased either by increasing
the number of code elements which are encoded simul
dicated in the symbolic showing of HG. 8(1)).
taneously or by increasing the number of encoding opera
The operation of the system of FIG. 2 through one
tions. For example, if six binary code elements were
encoding cycle will now be described with the aid of the
employed in each binary code group, the encoding proc
timing diagram of FIG. 3. Assuming again that the
signal amplitude to be encoded is represented by the 15 ess could comprise two encoding operations, each involv
ing the simultaneous encoding of three elements, or the
broken line in FIG. 1, line P1 goes active and conse
process
could comprise three encoding operations each
quently lines 68, 69, 70 and 71 into the decoders go ac
involving the simultaneous encoding of two elements. It
tive. The decoders therefore produce three reference
will be understood of course that the invention contem
voltages corresponding to the levels L1, L2 and L3 in
plates
such embodiments.
FIG. 1. Decoder 24 produces reference voltage L3, de
Therefore, while a single embodiment of the inven
coder 25 produces reference voltage L2, and decoder 26
tion has been illustrated and described, it is to be under
produces reference voltage L1. Since the assumed signal
stood that the invention is not limited thereto but con
amplitude in FIG. 1 is below reference levels L3 and L2,
templates such modi?cations and further embodiments as
the right-hand output lines 72 and 73 of comparators
may occur to those skilled in the art.
2i} and 21 go active; and since the assumed signal am 25
I claim:
plitude is above reference level L1, the left-hand output
1. An encoder system for producing a binary code
line '74 of comparator 22 goes active.
group representative of the instantaneous amplitude of
The next event in the encoding cycle, as shown by
a signal supplied thereto, comprising a plurality of de
the timing diagram of FIG. 3, is that line P3 goes active.
coders, a corresponding plurality of comparators, means
Since line ‘73 is also active, a “zero” is stored in bistable
circuit 35; and since line 74 is also active, a “one” is
stored in bistable circuit 36, as may be seen from the
symbolic showing in FIG. 2. It should be noted also that
for supplying the individual outputs of said decoders re
spectively and simultaneously to said comparators, means
for supplying a signal simultaneously to all of said com
parators, means for translating the outputs of said com
lines '75 and ‘76 are now active.
.
parators into binary code elements, means for causing
The next set of events, as may be seen in FIG. 3, is
said decoders to supply simultaneously a plurality of pre
that lines P2 and P4 both go active and lines P1 and P3
determined reference voltages of different amplitudes to
both go normal. With line 75 active the “zero” stored in
said comparators, whereupon said translating means trans
bistable circuit 35 is transferred to bistable circuit 31,
lates the outputs of said comparators into a ?rst plu
and with line 76 {active the “one” stored in bistable 36 is 40 rality of binary code elements, and means for causing
transferred to bistable circuit 32. Moreover, line 77 goes
said decoders to supply simultaneously a plurality of other
active.
predetermined reference voltages of different amplitudes
Since line P2 is also active at this time, lines 69, 78
to said comparators, whereupon said translating means
and "ill into the decoders go active. And the direct lines
translates the outputs of said comparators into a second
79, 3b, 61 and 82. into the decoders also go active. The
plurality of binary code elements.
decoders therefore produce three reference voltages cor
2. An encoder system for producing a binary code
responding to the levels L4, L5 and L6 in FIG. 1. De
group representative of the instantaneous amplitude of a
coder 24 produces vreference voltage L6, decoder 25 pro
duces reference voltage L5, and decoder 26 produces
reference voltage L4. Since the assumed signal ampli
signal supplied thereto, comprising a plurality of decoders,
tude in FIG. 1 is below all of the reference levels L4, L5 r
ly and simultaneously to said comparators, means for
supplying a signal simultaneously to all of said compara
tors, means for translating the outputs of said comparators
into binary code elements, a register, means for transfer
ring the binary code elements to said register, means for
causing said decoders to supply simultaneously a plurality
and L6, the right-hand output lines 72, 73 and 83 of all
three comparators go active.
The next set of events, as may be seen in FIG. 3, is
that line P4 goes normal and line P3 goes active. Since
line 73 is also active, a “zero” is stored in bistable cir
cuit 35', and since line 83 is also active, a “Zero” is stored
in bistable circuit 36. It should be noted also that lines
'75 and 84 are now active.
a corresponding plurality of comparators, means for sup
plying the individual outputs of said decoders respective
of predetermined reference voltages of different ampli
tudes to said comparators, whereupon said translating
means translates the outputs of said comparators into
The final set of events in the encoding cycle, as may
a ?rst plurality of binary code elements which are stored
be seen in PEG. 3, is that lines P2 and P3 go normal and
in said register, and means for causing said decoders to
line P5 goes active. Since line 75 is also active, the
supply simultaneously a plurality of other predetermined
“Zero” stored in bistable circuit 35 is transferred to bi
reference voltages of different amplitudes to said com
parators, whereupon said translating means translates the
stable circuit 33; and since line 84 is also active the
outputs of said comparators into a second plurality of
“zero” stored in the bistable circuit 36 is transferred to
binary code elements which are stored in said register.
bistable circuit 34. At the same time, line P1 goes ac
3. An encoder system for encoding into a binary code
tive to start the next cycle.
group the instantaneous amplitude of a signal whose am
The binary number 0100 now stands in the register 30‘.
plitude varies within a given range, comprising a plurality
The present invention is not concerned with what is done
with each binary number as it is stored in the register. 70 of decoders, a corresponding plurality of comparators,
means for supplying the individual outputs of said de
It may be read out and put to whatever use is desired,
coders respectively and simultaneously to said compara
as will be understood by those skilled in the art.
tors, means for supplying said signal simultaneously to all
It is believed su?icient to have described the operation
of said comparators, means for translating the outputs of
of the system for one assumed signal level as above set
said comparators into binary code elements, means for
forth. For any other assumed signal amplitude in any of
3,089,134
7
causing said decoders to supply respectively and simultane
ously to said comparators a plurality of predetermined ref
erence voltages respectively representative of different am
plitude levels within said signal range, whereby the out
puts of said comparators are translated into a ?rst plu
rality of binary code elements representative of a sub-1
range within said signal range, and means for causing
8
parators into binary code elements, means ,for causing
said decoder-s to supply respectively and simultaneously
to said comparators three predetermined referance volt
ages respectively representative of di?ierent amplitude
levels within said signal range, whereby the outputs of
said comparators are translated into a ?rst pair of binary
code elements representative of a sub-range within said
signal range, and means for causing said decoders to sup
to said comparators a plurality of other predetermined
ply respectively and simultaneously to said comparators
reference voltages respectively representative of di?erent is three other predetermined reference voltages respectively
amplitude levels within said sub-range, whereby the out
representative of different amplitude levels within said
puts of said comparators are translated into a second plu
sub-range, whereby the outputs of said comparators are
rality of binary code elements representative of a signal
translated into a second pair of binary code elements rep
amplitude within said sub-range.
resentative of a signal amplitude Within said sub-range.
4. An encoder system for encoding into a binary code
6. An encode-r system for encoding into a binary code
said decoders to supply respectively and simultaneously
group the instantaneous amplitude of a signal whose am
plitude varies ‘within a given range, comprising a plurality
group of four elements the instantaneous amplitude of a
signal whose amplitude varies within a given range, com
of decoders, .a corresponding plurality of comparators,
prising three decoders, three comparators, means ‘for sup
means for supplying the individual outputs of said de
plying the individual outputs of said decoders respectively
coders respectively and simultaneously to said compara 20 and simultaneously to said comparators, means for sup
tors, means for supplying said signal simultaneously to
plying said signal simultaneously to all of said compara
all of said comparators, means for translating the outputs
tors, means for translating the outputs of said compara
of said comparators into binary code elements, a register,
tors into binary code elements, a register, means includ
means including a plurality of bistable circuits for trans
ing a plurality of bistable circuits for transferring the
ferring the binary code elements to said register, means 25 binary code elements to said register, means ‘for causing
for causing said decoders to supply respectively and simul
said decoders ‘to supply respectively and simultaneously to
taneously to said comparators a plurality of predeter
said comparators three predetermined reference voltages
mined reference voltages respectively representative of
respectively representative of di?erent amplitude levels
different amplitude levels within said signal range, where
within said signal range, whereby the outputs of said com
by the outputs of said comparators are translated into a 30 parators are translated into a ?rst pair of binary code ele
?rst plurality of binary code elements which are stored in
ments which are stored in said register and which are rep
said register ‘and which are representative of a sub-range
resentative of a sub-range within said signal range, and
within said signal range, and means vfor causing said de
means for causing said decoders to supply respectively
coders to supply respectively and simultaneously to said
and simultaneously to said comparators three other pre
comparators a plurality of other predetermined reference 35 determined reference voltages respectively representative
voltages respectively representative of different amplitude
levels Within said sub-range, whereby the outputs of said
comparators are translated into a second plurality of
binary code elements which are stored in said register and
which are representative of a signal amplitude Within said
sub-range.
5. An encoder system for encoding into a binary code
group of four elements the instantaneous amplitude of a
signal ‘whose amplitude varies within a given ‘range, com
prising three decoders, three comparators, means for sup 45
plying the individual outputs of said decoders respec
tively and simultaneously to said comparators, means for
supplying said signal simultaneously to all of said'corn
parat-ors, means for translating the outputs of said com
of diiferent amplitude levels within said sub-range, Where
by the outputs of said comparators are translated into a
second pair of binary code elements which are stored in
said register and which are representative of a signal am
plitude within said sub-range.
References Cited in the ?le of this patent
UNITED STATES PATENTS
2,736,006
Lang'evin et al _______ _>___ Feb. 21, 1956
2,775,754
Sink ________________ __ Dec. 25, 1956
2,787,418
MacKnight et a1 ________ __ Apr. 2, 1957
2,872,670
2,974,315
Dickinson ____________ __ Feb. 3, 1959
Lebel et al. ___________ __ Mar. 7, 1961
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