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Патент USA US3090046

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May 14, 1963
J. A. KAUFFMANN
3,090,036
MAGNETIC PARTIAL SWITCHING CIRCUITS
Filed 001. 24. 1957
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INVENTOR.
JOHN A‘ KAUFFMANN
“i SIGNAL INPUT 11115
BZMMM
AGENT
May 14, 1963
J. A. KAUFFMANN
3,090,036
MAGNETIC FARTIAL SWITCHING CIRCUITS
Filed Oct. 24. 1957
3 Sheets-Sheet 2
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May 14, 1963
3,090,036
J. A. KAUFFMANN
MAGNETIC PARTIAL SWITCHING CIRCUITS
3 Sheets-Sheet 3
Filed Oct. 24, 1957
FIG. 4
LIB
; IRB
United States Patent
iQQ
Patented May 14, 1963
1
2
3,090,036
FIGURE 2 is a circuit diagram of a magnetic core
Two-Way AND circuit depicting one form of this in
MAGNETIC PARTIAL WITCHING QIRCUITS
John
3,ii99,€l36
,.
Kaniimann, Hyde Park, N.Y., assignor to Inter
vention.
FIGURE 3 is a circuit diagram of a magnetic core
national Business Machines Corporation, New York, CH Three-Way AND circuit depicting another form of this
N.Y., a corporation of New York
invention.
Filed Oct. 24, 1957, Ser. No. 692,131
FIGURE 4 is a circuit diagram of a magnetic core
24 Claims. (Cl. 340-174)
NEITHER NOR circuit depicting yet another form of this
invention.
This invention relates to pulse transfer circuit and
vFIGURE 5 illustrates the relative timing of current
more particularly to circuits which are adapted to perform 10
pulses which are required for operating the circuits of
logical operations on binary digits.
FIGURES 2, 3 and 4.
Logical circuits are employed throughout accounting
equipment and computers for widely different purposes
and are variously known as gates, buffers, coincidence
Referring to FIGURE 1, the curve illustrated com
prises a plot of ?ux density versus applied ?eld for a
circuits and the like. This invention is directed to logical
magnetic core having a substantially rectangular hyster
circuitry employing magnetic components operated in
esis characteristic.
The opposite remanence states are
accordance with a novel mode which is hereafter termed
conventionally employed for representing binary infor
“partial-switching".
mation conditions and are arbitrarily designated as “0”
and “1”. With a “0” stored, a pulse applied to a wind
To demonstrate how this “partial-switching” method
ing linking the core in proper sense causes the loop to be
may be employed, one embodiment of this invention is
traversed and the remanence state “1” is attained when
directed to a Two-Way AND logical circuit, which is a
the pulse terminates. Such a pulse is hereinafter referred
circuit having two input terminals and a single output
to as a “write” pulse. Similarly, the core is read out or
terminal at which a pulse is produced when and only
returned to the “0” state in determining what informa
when a pulse is applied to both input terminals.
To further illustrate how the “partial-switching” 25 tion has been restored by applying a pulse in the reverse
sense to the same or another winding. Such a pulse is
method may be utilized another embodiment of this in
hereinafter referred to as a “read” pulse. Should a “l”
vention is directed to a Three-Way AND logical circuit,
which is a circuit having three input terminals and a
single output terminal at which a pulse is produced
when and only when all three input terminals have a pulse
applied to them.
A further embodiment of this invention is directed to
a NEITHER NOR circuit as an additional illustration of
how this “partial-switching” method may be employed,
which circuit has two input terminals and a single output
terminal at which a pulse is produced when and only
when neither one nor both input terminals have a pulse
applied to them.
Electronic computers employ a large number of
vacuum tubes, and while such tubes may have long life
individually, where large numbers are employed, the like
lihood of failure of one tube is quite great. In many
instance, the failure of only a single tube may completely
disable the unit and as a consequence, there has been a
trend, in computer research generally, to replace vacuum
tube circuit with components which are more reliable,
have longer life and are more economical.
have been stored, a large ?ux change occurs with the shift
from “1” to “0” conditions with a corresponding voltage
magnitude developed on an output winding. On the
other hand, should a “0” have been stored, little ?ux
change occurs and negligible signal is developed on the
output winding.
For any given core, to obtain either the “l” or the “0”
limiting state, as described above, a given amount of flux
change must occur within the core. Assume, however,
that instead of a volt-time product applied to a given
core which is sufficient to fully switch the core to one of
the limiting states, only half this given amount is applied.
Since only half the given amount of volt-time product
is applied, only half the amount of ?ux change will
occur within the core and subsequent to the application
of such a signal, the core will attain a “mid-way”, or
“half-state”, of residual ?ux density which is shown by
“a” in the FIGURE 1. Similarly then, different incre
ments of volt-time product applied will result in different
residual states of ?ux density intermediate the “l” and
“0" limiting states. Consider further, a circuit structure,
wherein two cores, each having substantially the same
Another object of this invention is to provide a new 50 characteristics and having windings with the same number
Accordingly, an object of this invention is to provide a
new and improved arrangement for switching circuits.
and improved arrangement for logical circuits employ
ing magnetic cores.
Yet another object of this invention is to provide new
and improved AND circuits utilizing magnetic elements
for performing the logical operations.
Still another object of this invention is to provide a
new and improved NEITHER NOR circuit utilizing
magnetic elements for performing the logical operation.
Another object of this invention is to provide logical
circuits adapted to receive input pulses over a selectable
time interval and to produce an output indication at a
selectable time.
Other objects of the invention will be pointed out in
the following description and claims and illustrated in the
accompanying drawings, which disclose, by way of ex
ample, the principle of the invention and the best mode,
which has been contemplated, of applying that principle.
In the drawings:
FIGURE 1 is a representation of the hysteresis char
acteristic obtained for a rectangular magnetic material
of type employed.
of turns ‘are connected in series. Assume a given volt
time product is applied which in itself is su?icient to fully
switch any one of the two cores to a limiting state. This
applied signal will then be shared by each of the cores
55 and each core will then attain the “half-state” of residual
flux density upon termination of such a signal. In each
of the embodiments disclosed below the interconnection
of two similar cores, as described, is the particular ar
rangement utilized to perform logical operations. It is
understood however, that further cores may be similarly
added to allow further subdivision, or sharing, of a given
signal, or the amount of the signal may be varied to
accomplish the logic desired.
A dot is shown adjacent one terminal of each of the
windings illustrated in FIGURES 2, 3 and 4, indicating
its windings direction. A write pulse is a positive pulse
which is directed into the undotted end of the Winding
terminal which tends to store a “1,” while a read pulse is
a positive pulse directed into the dotted end of the winding
terminal and tends to apply a negative magnetomotive
force or store a “O.”
0
3,090,086
4
0
The arrangements disclosed employ input and output
coupling magnetic cores and inhibit cores arranged inter
mediate to so called storage magnetic cores which store
certain logical information and these arrangements are
adapted to be interconnected with each other and with
similar type circuitry through such coupling cores.
The function and use of the so called “inhibit cores”
is more fully disclosed and claimed in a copending ap
ferent conditions which may exist.
Assume that at IA
clock pulse time, which is the interval during which input
signals are applied to the circuit and designated input
time as shown in FIGURE 5, no input is available to
either core C1 or C2. Since no input has been received,
the ?ux conditions of the cores in loop A remain the same
and a signal from the clock pulse source IA is directed into
the Winding 15 on the core S3, which signals tends to read
the core S3 in the loop B. Since the core S3 is already
plication, Serial No. 689,827, ?led October 14, 1957, now
abondaned, by John A. Kautfmann and assigned ‘to the 10 in the “0” state, negligible signal will be developed on
same assignee.
The coupling cores and inhibit cores may be fabricated
of ferrite materials like the storage cores; however, it is
not essential that these cores exhibit the rectangular hys
teresis characteristic required of the storage or memory
cores as these devices function as variable impedance ele
ments in controlling the transfer of information pulses,
as will be more evident from the following description.
As shown in the several ?gures, such interconnecting cou
pling cores and inhibit cores are illustrated in each of
the subsequently described and depicted circuits which
are labeled C1, C2, C3, C4, C5, 11, I2 and I3 for clarity.
Also shown are two storage cores S1 and S2 which are
adapted to store information received. The core S1 is
adapted to deliver the information received to another
storage core 5;, of another logical component. The core
S2 is adapted to store information received and to act
in conjunction with core S1 to perform the logic subse
quently described.
Referring to FIGURE t2, the core S1 is provided with 30
a winding 1 interconnected with an output winding 2 on
the core C2, an output winding 3 on the core C1, an input
winding 4 on the core C3 through a diode D1 and an
output winding 5 on the core ‘S2 which interconnection is
the output winding 7 and the core remains in the “0” state.
After the IA clock pulse subsides the IRA clock pulse source
directs a signal into the windings 9 and 10 on the cores C1
and C2, respectively, which tends to read both cores.
Again, since both the cores C1 and C2 are already in the
“0” state under the conditions assumed, no ?uX change
Occurs. The 13 clock pulse source next directs a signal
into the winding 11 on the core S, which signal tends to
read this core. Again no appreciable ?ux change takes
place since the core S1 is already in the “0” state. Sub
sequent to the 1B clock pulse, the IRB clock pulse source
directs a signal into the windings 12, 13 and 14 on the
cores S1, S2 and C3, respectively, which current tends to
read each of these cores.
Again, no appreciable ?ux
change takes place since these cores were initially in the
“0” state.
Under the condition that no information is
transferred into the circuit, as described, no information
is transferred out due to operation of the clock pulse
source.
Assume an input signal is directed into the undottcd
end of the input winding '16 on the core C1. The core
C1 then switches from remanence condition “0” to the
“1” state and in so doing induces a voltage on the output
winding 3 such that the unmarked end is positive causing
hereinafter referred to as loop A. Core ‘C3 is further 35 a counterclockwise current ?ow in loop A. This current
provided with an output winding 6 which is interconnected
flow is such ‘as to read the core C2 and write the cores
with an input winding 8 on the core 0,; through a diode
S1, S2 and C3. Since the core C2 is already in the “O”
D2, wherein the core C4 represents a further coupling core
remanence state negligible voltage drop appears across
that may be coupled to the storage core S3 through wind
the winding 2. The windings 1 and S on cores S1 and
ing 7 series connected to the winding 6. This circuit is 40 S2, respectively, are provided with an equal number
hereinafter referred to as loop B.
of turns and have, in comparison, a greater number of
Storage cores S1 and S2 are adapted to receive informa
turns than the winding 4 on the core C3. The current,
tion pulses transferred to them through the coupling cores
thus, preferentially begins to switch both the cores S1
C1 and C2, which information is in turn transferred from
and S2 to the “1” state, but, since the core C1 is supply
the core 8;, when the proper inputs are realized, through 45 ing the volt-time product to switch each of the two cores,
the coupling core C3 to the following logical stage. The
S1 and S2, each of the cores switch only halfway towards
storage core S3 is representative of a storage core in such
the “1” state and attain a rernanence state substantially
midway between the “O” and “1” conditions or at point
“a” as shown in FIGURE 1. At the conclusion of the
nals are applied to the cores C1 and C2 by means of input 50 input pulse, the core C1 stands in the “l” remanence
windings designated 16 and 17, respectively. The cou
state while the cores S1 and S2 stand in the “half one”
pling cores C1 and C2 are energized from a clock pulse
remanence state ‘as shown by point “a,” in FIGURE 1.
source IRA while the storage cores S1 and S2 along with
Next, the IRA clock pulse source directs a signal into the
coupling core ‘C3 are energized from a clock pulse source
windings 9 and 10 on the cores C1 and C2, respectively,
‘IRE, with storage core S1 further energized from a clock 55 which signal tends to read each of these cores. Since
pulse source IB and storage core S3 energized from a clock
the core C2 is already in the “0” state, it is uneffected,
pulse source IA. A winding 9 is provided on the core C1
while the core C1, which was previously in the “1” state,
and a winding 10 is provided on the core C2, which Wind
is now reset to the “0” state engendering a ?ux change
ings are series connected with the source ‘IRA. Similarly,
which induces a voltage on the Winding 3 with the undot
following stage and thus receives information represent
ing the logical function of Two-Way AND. Input sig
a winding 12 on core S1, a Winding 13 on core S2 and a
ed end positive tending to cause a clockwise current
winding v14 on core C3 are series connected with the
source IRE while a winding 11 on core S1 is connected
flow in the loop A which is blocked and dissipated by
the high back resistance of the diode D1. At the con
clusion of the IRA clock pulse, the IB clock pulse source
with the pulse source IE on the core 8;; is connected with
the pulse source IA.
The sequence of pulses provided by the several clock
pulse sources described above is indicated in FIGURE 5
and may be observed as being the same for each of the
hereinafter described circuits with which such sources
are adapted to operate.
To explain the operation of the circuits disclosed, con
sider ?rst, in all circuits described, as an initial condition,
that all of the cores shown are at a “0” state or at the
lower remanence condition “0” shown in FIGURE 1.
Referring to FIGURE 2, with the initial condition as
above described, let us consider its operation for the dif
directs a signal into the winding II]. on the core S, which
signal tends to read this core. Since the core S1 was
previously in “half one” remanence state, or at point
“a” as shown on the hysteresis loop in FIGURE 1, the
core is switched toward the “O” remanence condition
inducing a voltage on the output winding 1 with the
dotted end positive causing a counterclockwise current
?ow in the loop A which tends to Write the cores S2 and
C3. Since the core S2 is in the “half one” state and
only a “half one” volt-time product is available from
the core S1, this volt-time product is completely dissipated
in the preferential switching of the core S2 from the
3,090,036
56
5
source subsequently directs a signal into the windings
12, 13 and 14 on the cores S1, S2 and C3 respectively,
pulse source directs a signal into the windings 12, 13 and
14 to read each of the cores S1, S2 and C3, respectively.
The core S1 is already in the “0” state, and therefore
remains uneffected. The core S2 is switched from the
‘and is such as to read each of these cores.
“l” to the “0” state and in so doing induces a voltage
intermediate remanence condition to the “1” state.
At
the conclusion of the 13 clock pulse the IRB clock pulse
Since the
cores S1 and C3 are already in the “0” state negligible UK on the winding 5 with the dotted end positive tending to
tiux change takes place. The core S2 however, switches
cause a counterclockwise current flow in the loop A.
The core C3 in switching from the “1” to the “0” State
from the “l” to the “0” state causing a voltage to be
causes a voltage to be induced on the windings 4 and 6
induced on the output winding 5' with the undotted end
with their dotted end positive causing a counterclock
positive causing a counterclockwise current how in the
loop A. This current tends to write the core C3, read 10 wise current ?ow in loop A, and a clockwise current flow
in the loop B. The counterclockwise current ?owing
cores C1 and C2, and write the core S1. Since the cores
in the loop A tends to read each of the cores C1 and
C1 and C2 are already in the “0” state, they are unef
C2 while tending to write the core S1. Since the cores
fected, while the cores C3 and S1 are held in the “0” state
C1 and C2 are already in the “0” state, they are un
by their IRE drives. This leaves all cores in the “0”
state ‘and the circuit is ready for the next cycle of op 15 ei’fected while the core S1 is held in the “0” state by
virtue of the IRB drive. The clockwise current ?ow in
eration, the receipt of a single input having produced no
output. It follows from the above, that a single input
the loop B is blocked and dissipated by the diode D2
directed to the winding 17 on the core C2 will have the
to leave all the cores in the “0” remanence state except
same affect in that no output signal is produced to write
the core 53, into which the information has been stored
20
as described above.
the core S3.
Assume an input signal is now directed into the wind
The circuit disclosed above may be modi?ed to avoid
ings 16 and 17 on the cores C1 and C2 respectively,
the need for the diodes D1 and D2 by replacing the diodes
with resistors. This would necessitate the utilization of
which signal is such as to write each of the cores. The
core C1 in switching from the “0” to the “1” state in
smaller, but longer, reset current clock pulses herein
25
duces a voltage on the winding 3 with its undotted end
noted as the IRA and IRB clock pulses, as disclosed and
claimed in a copending application Serial Number
positive causing a counterclockwise current how in the
loop A. The core C2 in switching to the “1” state in
528,594, ?led August 16,’ 1955, now Patent No. 2,907,987,
duces a voltage on the output winding 2 with the un
on behalf of Louis A. Russell, which application is as
dotted end positive also causing a counterclockwise cur
signed to the same assignee.
Referring to FIGURE 3, the circuit depicted in PI"
rent flow in loop A. This counterclockwise current tends 30
URE 2, is modi?ed by the addition of a coupling core
to write each of the cores S1, S2 and C3. Again the
cores S1 and S2 preferentially start switching from the
C5 and an inhibit core I1 and functions as a Three~Way
“0" to the “1” state and since the volt-time product from
AND circuit. The core S1 is provided with the winding
1 interconnected with the output winding 5 on the core
both the cores C1 and C2 is now available, each of the
cores S1 and S2 are completely switched to the “1” state. 35 S2, input winding 4 on the core C3, output winding 3 on
At the conclusion of the input signals, the cores C1, C2,
the core C1 through the diode D1, output winding 2 on
S1 and S2 are left in the “l” remanence state, with the
the core C2, an output winding '18 on the Core C5 and an
core C3 in the “0” remanence state. Next, the IRA clock
output winding 19‘ on the core I1 which interconnection
pulse source directs a signal into the windings 9‘ and
is hereinafter referred to as loop C. The output wind
lit) on the cores C1 and C2 respectively, which signal 40 ing 6 on the core C3 is interconnected in the same manner
tends to read each of the cores. The cores C1 and C2
as above described for FIGURE 2 and is again referred
are switched from the “1” to the “0” state and in so
to as loop B.
doing, a voltage is induced on the output windings 2 and
Similarly, the storage cores S1 and S2 are adapted to
3 with the undotted end positive tending to cause cur
receive information pulses transferred to them through
45
rent ?ow in a clockwise direction in the loop A. Cur
coupling cores C1, C2, and G5, which information in turn
rent flow in this direction is blocked by the diode D1
is transferred from the core S1, when the proper inputs
and the energy dissipated by its high back resistance.
are realized, through the coupling core C3 to the following
After the cores C1 and C2 have been fully reset to the
logical stage. The storage core S3 is representative of a
“0” state by the IR;L clock pulse, the TB clock pulse
storage core in such following stage and thus receives
source now directs a signal into the dotted end of the 50 information representing the logical function of Three
winding 12 on the core S1 which switches the core from
Way AND. Input signals are applied to the cores C1,
the “1” to the “0” state and in so doing a voltage is
C2 and C5 by means of the input winding 16, 1'7 and
induced on the winding 5 on the core S1 with the dotted
input winding 20‘, respectively. The coupling cores
end positive, causing ‘a counterclockwise current how in
C1, C2, C5 and I1 are energized from the clock pulse
the loop A. This current direction tends to write the 55 source IRA while the coupling cores C3 and I1 along with
cores S2 and C3 while at the same time tends to read
the storage cores S1 and S2 ‘are energized from the clock
the cores C1 and C2. Since the cores C1 and C2 are
pulse source IRE. Storage core S1 is further energized
already in the “0” state, ne'rligible voltage drop appears
from the clock pulse source In along with coupling core
on their windings 3 and 2., respectively. The core S2
11.
The storage core S3 is energized from the clock
is already in the “1” state so here too there is experienced 60 source IA along with the coupling core 11. A winding
negligible voltage drop across the winding 5. The core
21 is provided on the core C5 and a winding 22 is pro
C3, however, is switched from the “0” to the “1” state
vided on the core I1 which windings along with the wind
and in so doing, induces a voltage on the winding 6 with
ing 9 on the core C1 and the winding 10‘ on the core C2
the undotted end positive so as to cause a counterclock
are series connected with the source IRA.
wise current flow in loop B. This current direction tends ’
winding 23 is provided on the core 11 with the winding
to write both the cores 8;; and C4, however, because of
the turns ratio, the core S3 is switched to the “1” state
in preference to the core C4. Thus, a transfer of infor
mation is accomplished only when both inputs are present.
Further transfer from core S3 is delivered through the
core C4 upon application of the next signal to the core
8;, by the IA clock pulse source. After the information
is stored in the core S3 by the TB clock pulse, the IRB
12 on the core S1, the winding 13 on the core S2 and
the winding 14 on the core C3 which windings are series
clock pulse resets the remaining cores of the circuit and '
it is prepared for further input signals. The IRE clock
Similarly a
connected with the clock pulse source IRE. A winding
24 is provided on the core 11 which winding is series
connected to the winding 11 on the core S1 and the clock
pulse source 13. A winding 25 is provided on the core
11, which winding is series connected to the winding \15
on the core S3 and clock pulse source IA.
Assume no input is available to the cores C1, C2 or
3,090,036
?
8
C5. Initially, the IA clock pulse source directs a signal
ing 25 on the core I1 as described above. The voltage
into the winding 25 on the core 11 and the winding 15
on the core S3. This signal tends to write the core 11
and read the core S3. Since S3 is already in the “0”
remanence state negligible flux change will occur, while
dotted end positive is equal and opposite to the voltage
the core 11 will experience a large ?ux change in switch
ing from the “0” to the “1” state. As a consequence of
the ?ux change experienced in the core 11, a voltage is
developed on the output winding 19 such that the un
dotted end is positive tending to cause a clockwise cur
10
rent ?ow in loop C. This clockwise current flow is
blocked and its energy is dissipated by the high back re
sistance of the diode D1. At the conclusion of the IA
clock pulse, the IRA clock pulse source directs a signal
into the windings 9, 10, 21 and 22 on the cores C1, C2, 15
C5 and 11' respectively, which signal tends to read each
of these cores.
The core 11 switches from the “l” to the
“0” state, while the cores C1, C2 and C5 experience negli
gible ?ux change since they were previously in the “0”
induced on the winding K19 on the core I1 with the un
developed on the winding 18 on the core C5 which volt
ages buck and effectively cancel to allow negligible cur
rent ?ow in loop C. After the IA clock pulse subsides,
the IRA clock pulse source directs a signal into the wind
ings 9, 1t), 21 and 2.2 on the cores C1, C2, C5 and 11, re
spectively. This signal tends to read each of the cores
C1, C2, C5 and I1 and reset them to the “0” state. Since
the cores C1 and C2 are already in the “0” state they are
unelfected, while the cores C5 and I1 experience a large
?ux change in switching from the “1” to the “0” state
which change induces a voltage on the output windings
18 and Y19 on the cores C5 and 11, respectively. The volt
age induced on each of the windings 18 and 19 have their
dotted end positive which buck and effectively cancel
allowing negligible current how in the loop C. At the
termination of the IRA clock pulse, all cores are left in
their “0” remanance state. The IB clock pulse source now
directs a read signal into the windings 24 and 11 on the
cores I1 and S1, respectively, and since both the cores I1
and S1 are already in the “0” state, they are unaifected and
no transfer of information takes place. The IRE clock
pulse source subsequently directs a signal into the wind
ings Z3, 12, 13 and ‘14- on the cores 1,, S1, S2 and S3, re
state. The core 11 in switching from the “l” to the 20
“0” state, induces a voltage on the output winding 1%
with the dotted end positive causing a counterclockwise
current flow in the loop C. This direction of current
?ow tends to write each of the cores S1, S2 and C3. The
current preferentially begins to switch the cores S1 and 25
S2 to the “1” state, but since the core 11 is supplying the
volt-time product to switch each of the two cores S1
spectively, which tends to switch each of the cores toward
and S2, the cores switch only half way towards the “1”
state. At the conclusion of the IRA clock pulse, the
core I1 is left in the “O” remanence state while the cores
S1 and S2 are left in the “half-one” remanence state
shown by point “a” in FIGURE 1. Now, the 13 clock
pulse source directs a signal into the windings 11 and 24
on the cores S1 and 11, respectively, which signal tends
to read each of the cores 5; and 11.
Since the core 11
is already in the “0” state, negligible flux change occurs,
while the core 51 is switched from the “half-one” to the
“0” state. Resetting the core S1 to the “0” state causes
a flux change which induces a voltage on the output wind
ing 1 with the dotted end positive causing a counter
clockwise current ?ow in the loop C which tends to
write the core S2 and the core C3. Since the core S2
was previously in the “half-one” state, and only a “half
one” volt-time product is available from core S1 in switch
ing to the “0” state, this volt-time product is completely
dissipated in the preferential switching of the core S2
the “0” state. Again, since all the cores are already in the
“0” state, there is no appreciable ?ux change and no trans
fer of information takes place. No information has been
transferred, as described above, due to the operation of
the clock pulse sources, and all cores are left in the “0”
state, thus, the circuit is ready for the next cycle of opera
tion.
It follows from the above, that an input directed to the
winding 16 on the core C1, or the winding ‘17 on the core
C2 will have the same effect in that no output signal is
produced to write the core S3.
Assume an input is directed into the windings 17 and
20 on the cores C2 and C5, respectively.
The cores C2
and C5 in switching from the “0” to the "1” state induce
a voltage on their output windings 2 and 118 with the un
dotted end positive. This voltage is bucked by the core
11 switching from the “0” to the “1” state, initiated by the
operation of the {A clock pulse source as previously de
scribed, inducing a voltage on the output winding 19 with
the undotted end positive. The algebraic sum of the in
duced voltages is such that current flows in the counter
clockwise direction in the loop C which current starts
pulse source IRE subsequently directs a signal into the
windings 12, 13, 14 and a winding 23 on the cores S1, 50 switching each of the cores S1 and S2 towards the “1” state.
Effectively, there is only a volt-time product available
S2, C3 and 11 respectively, which signal is such as to read
to the “1” state. At the conclusion of the 13 clock pulse,
the core S1 is left in the “O” remanence state and the
core S2 is left in the “1” remanence state. The clock
each of these cores. Since the core S2 is the only core
in the “1” state at this time, it alone switches to the
“0” state to cause an appreciable ?ux change. This ?ux
from one core to switch each of the cores S1 and S2, there
fore both cores switch only to the “half-one” state. At
change induces a volage on the output winding 1 with the
and 11 are left in their “1” remanence state, while the cores
S1 and S2 are in their “half-one” remanence state. The
clock pulse source IRA now directs a read signal into the
dotted end positive which causes a counterclockwise
current ?ow in the loop C which tends to write the cores
the termination of the IA clock pulse, the cores C2, C5
windings 9, 10, 21 and 22 on the cores C1, C2, C5 and 11,
respectively. The core C1 is already in the “0” state and
“0” remanence state and the cores C3, 11 and S1 remain 1n 60 is thus unelfected, while the cores C2, C5 and I1 are each
C3, 11 and S1, while tending to read the cores C1, C2
and C5. The cores C1, C2 and C5 are already in the
switched ‘from the “1” to the “0” state to cause a ?ux
the “0” state due to the IRB drive on their windings 14,
change in each of the cores to induce a voltage on their
12 and 23, respectively. All cores are thus left in the
“0” state and the circuit is ready for the next cycle of
output windings 2, 18 and 19, respectively, With their
operation, no information has been transfer-red into the
dotted end positive. The algebraic sum of these induced
65
circuit, and, as described, no information is transferred
voltages is such that current tends to flow in the clock
out due to operation of the clock pulse sources.
wise direction in the loop C. This current direction in
Assume now an input signal is directed into the un
loop C is blocked and its energy dissipated ‘by the high
dotted end of winding 20 on the core C5. The core C5
back resistance of the diode 131. At the termination of
then switches from remanence condition “0” to the “1” 70 the IRA clock pulse, the cores S1 and S2 are in their
state and in so doing induces a voltage on the output wind
ing 18 such that the undotted end is positive, while, at
the same time, a voltage is developed across the output
winding 19 on the core I1 due to the operation of the IA
clock pulse source directing a write signal into the wind 75
“half-one” remanence state, while all other cores are in
the “0” remanence state. The clock pulse source I3 next
applies a read signal into the windings 24 and 151 on the
cores 1; and S1 respectively. Since the core 11 is already
in the “0” state, it is unetfected, while the core S1 is
3,090,036
id
to write the cores S2 and C3. Again, since the core S2
is in the “halfone” state and only a “half-one” volt
5, while the core I1 is held in the “0” state by virtue of
the IB clock pulse drive. Since the counterclockwise
current flow in the loop C is directed into the undotted
end of the winding 4‘ on the core C3, the core C3 switches
from the “0” to the “1” state causing ‘a large ?ux change
in the core which induces a voltage on the winding 6 with
tiine product is available from the core S1 in switching
the undotted end positive. This induced voltage causes
switched ‘from the “half-one” state to the “0” state to
cause a ?ux change which induces a voltage on the out~
put winding 1 with the dotted end positive causing a
counterclockwise current ?ow in the loop C which tends
a counterclockwise current ?ow in the loop B which is
to the “0” state, the volt-time product is completely dis
directed into the undotted end of the winding 7 on the
sipated in the preferential switching of the core S2 to the
“1” state. At the conclusion of the IB clock pulse, the 10 core S3 and completely switches the core S3 to the “1”
state. At the conclusion of the IB clock pulse, the cores
core S1 is in the “0” remanence state while the core S2 is
8;, C3 and S3 are left in the “1” remanence condition,
in the “l” remanence state. Subsequently, the clock pulse
while the core 8; is left in the “0” remanence condition.
source IRE directs a read signal into the windings 12, 13,
Subsequently, the IRB clock pulse source directs a read
14 and 23 on the cores S1, S2, C3 and 11, respectively.
signal into the windings 23, 12, 13 and 14 on the cores
Since the core S2 is the only core in the “1” state at this
11, S1, S2 and C3, respectively, which switches the cores
time, it is switched from the “l” to the “0-” state While the
S2 and C3 from the “1” to the “0'” state, while leaving
cores S1, C3 and 11 are uneffected. The core S2 in switch
the cores I1 and S1 uneffected since they are already in
ing induces a voltage on the out-put Winding 5 with the
the “0” state. Switching the core S2 from the “l” to
dotted end positive which causes a counterclockwise cur
rent flow in the loop C. This counterclockwise current 20 the “0” state causes a flux change which induces a volt
age on the output winding 5 with the dotted end positive.
flow tends to write each of the cores C3, I1 and S1 while
Switching the core C3 from the “1” to the “0” state in
tending to read each of the cores C1, C2 and C5. Since
duces a voltage on the windings 4 and 6 with their dotted
the cores C1, C2 and C5 are already in the “0” state they
end positive. The algebraic sum of the induced volt
are unelfected while the cores 11, S1 and C3 are held in
ages on windings 5 and 4 on the cores S2 and C3 is addi—
the “0” state by virtue of the IRB drive; thus leaving all
cores in the “0” state without the transfer of a signal to
the core S3 due to the clock pulse sources and readying
the circuit for the next cycle of operation.
it follows from the above, that a write pulse directed
to any two of the input windings 16, 17 and 20 on the
cores C1, C2 and C5 respectively, will have the same effect
as described above, in that no output signal is produced to
write the core C3.
Assume now an input signal is directed into the input
windings 16, 17 and 26 on the cores C1, C2 and C5. Each
of the cores will switch from the “0” to the “1” state to
induce a voltage on each of the output windings 3, 2 and
18 on the cores C1, C2 and C5, respectively, with their
undotted ends positive.
At the same time, a voltage is
induced, due to the IA clock pulse source directing a write
signal into the Winding 25 on the core 11 as previously
tive to cause a counterclockwise current flow in the loop
C. This counterclockwise current ?ow tends to read the
cores C1, C2 and C5 while tending to write the cores I1
and S1. Since the cores C1, C2 and C5 are already in the
“0'” state they are uneifected, while the cores I1 and S1
are held in the “0” state by virtue of the IRB drive on
their respective windings 23 and 121- The voltage in
duced on the winding 6 on the core C3 tends to cause a
clockwise current ?ow in the loop B which current is
blocked and its energy dissipated by the high back resist
ance of the diode D2.
Thus a transfer of information
is accomplished only when all three inputs are present,
and the output from the core S3 is delivered through the
core C4 upon the application of the next IA clock pulse,
While all the cores associated with loop C are left in the
described, on the output winding 19 with the undotted
end positive. The algebraic sum of the induced voltages
“0” state readying the circuit for the next cycle of op
eration.
Referring to FIGURE 4 the circuit illustrated is basical
is such that a counterclockwise current ?ows in the loop
C. This counterclockwise current starts switching the
cores S1 and S2, but now, since the effective volt-time
is thereby provided which is adapted to perform the
product from two cores is available, each of the cores
S1 and S2 are completely switched to the “1” state. At
the
C5,
the
the
ly as depicted in FIGURE 2 with inclusion of a core 12
and a core 13 with their associated windings. A circuit
function of NEITHER NOR. The core S1 is provided
with the winding 1 interconnected with an output winding
17 and on the core 13, an output winding 26 on the core
termination of the IA clock pulse, the cores C1, C2,
I2
the output winding 2 on the core C2, the output winding
50
11, S1 and S2 are left in the “1” remanence state, and
3
on the core C1, the input winding 4 on the core C3
IRA clock pulse source next directs a read signal into
through the diode D1, and the output winding 5‘ on the
windings 9, 10, 21 and 22 on the cores C1, C2, C5
and I1, respectively, which switches each of the cores
from the “1” to the “0” state.
As a result of the switch
ing, a voltage is induced on each of the output windings
3, 2, 1i} and 19 on the cores C1, C2, C5 and I1, respec
tively, with their dotted end positive. The algebraic sum
of the induced voltages is such as to tend to cause a
clockwise current flow in the loop C which is blocked
and its energy is dissipated by the high back resistance of
the diode D1. At the termination of the IRA clock pulse,
core S2 which interconnection is hereinafter referred to
as loop E.
The coupling cores I2 and 13 along with the storage
core 8;, are energized from the clock pulse source IA,
while the coupling cores C1, C2, 12 and I3 are energized
from clock pulse source IRA, with the coupling cores I2
and I3 along with the storage cores S1 energized from the
clock pulse source 13, and the coupling cores 12, I3 and
C3 along with the storage cores S1 and S2 energized from
the clock pulse source IRE. The windings 28, 29‘ and 15
the cores C1, C2, C5 and 11 are left in the “0” reinanence
on the cores I2, 13 and S3, respectively, are series con
state while the cores S1 and S2 are left in the “1” rem
nected
with the source IA, while the windings 9, 1t}, 30
anence state. The IR clock pulse source now directs a
read signal into the windings 24 and 11 on the cores l1 65 and 31 on the cores C1, C2, I2 and I3 are series connected
and S1, respectively, which signal does not effect the core
I1 but switches the core S1 from the “l” to the “0” state
causing a flux change which induces a voltage on the
output winding 1 with the dotted end positive causing a
counterclockwise current ?ow in the loop C. This coun
terclockwise current flow tends to write the cores S2,
C3 and I1 and to read the cores C1, C2 and C5. Since
each of the cores C1, C2 and C5 are in the “0” state, they
are uneffected. The core S2 is already in the “1” state,
with the source IRA. Similarly, the windings 11, 32 and
33 on the cores S1, I2 and 13, respectively are series con
nected with the source IB and the windings 12, 13‘, 14,
34 and 35 on the cores S1, S2, C3, I2 and I3, respectively,
are series connected with the source IRE.
Assume, initially, that no input signal is available.
Initially, a write signal from the clock pulse source IA, is
directed into the windings 28 and 29 on the cores I1 and
I2, respectively, and a :read pulse is directed into the wind—
and negligible voltage drop appears across the winding 75 ing 15 on the core S3. As a consequence of the write
3,090,036
11
12
signal, the cores I2 and I3 switch 'from the “O” to the “1”
the output winding 2 with the undotted end positive, while,
state and in so doing induce a voltage on the output wind
at the same time, as described in ‘the previous example, the
IA clock pulse source directs a signal into the windings 28
and 29 on the core 12 and 13, respectively, which switches
the cores I2 and I3 from the “O” to the “1” state to induce
a voltage on the output windings 26 and 27, respectively,
with their undotted end positive. The algebraic sum of
ings 26 and 27, respectively, with the undotted end posi
tive, tending to cause a clockwise current ?ow in the loop
E which is blocked and its energy dissipated by the high
back resistance of the diode D1. The read signal does not
effect the core S3 since it is already in the “0” state, and
therefore negligible ?ux change occurs in the core. At
these induced voltages is such as to tend to cause a clock
the termination of the IA clock pulse, the IRA clock pulse
wise current ?ow in the loop E. This clockwise current
source directs a read signal into the windings 9, 10, 30‘ 10 ?ow is blocked and dissipated by the diode D1. At the
and 31 on the cores C1, C2, I2 and I3, respectively, which
termination of the IA clock pulse, and the input pulse, the
signal leaves the cores C1 and C2 une?ected since they
cores C3, 12 and I3 are left in the “1” remanence state.
are already in the “0” state, but resets the cores I2 and
These cores are then cleared by the clock pulse source
I3 from the “1” to the “0” state and in so doing induces
IRA which directs a read signal into the windings 9', 1t},
a voltage on the output windings 26 and 27 on the cores 15 30 and 31 on the cores C1, C2, I2 and I3, respectively, to
I2 and I3, respectively, with the dotted end positive, caus
switch each of the cores C2, 12 and I3, from the “1” to the
ing a counterclockwise current flow in the loop E. This
“0” state. The cores C2, I2 and I3 in switching from the
counterclockwise current ?ow tends to switch each of the
cores S1 and S2 from the “O” to the "1” state and, because
“ ” to the “0” state induce a voltage on the output wind
invs 2, 26 and 27, respectively, with their dotted end
the volt-time product of two cores switching is available, 20 positive. The algebraic sum of the induced voltages is
both the cores S1 and S2 are fully switched to the “1”
such as to cause a counterclockwise current ?ow in the
state. At the conclusion of the IRA clock pulse, the cores
I2 and I3 are left in the “O” remanence state while the
loop E which current is directed into the undotted end of
the windings 1 and 5 on the storage cores S1 and S2, re
cores S1 and S2 are left in the “1” remanence state. The
spectively, which starts to switch each of these cores to
clock pulse source IB now directs a read signal into the 25 the “1” state. However, since the algebraic sum of the
windings 11, 32 and 33 on the cores S1, I2 and I3, respec
volt-time product available is equal to that of one core
tively. Since the cores l2 and 13 are already in the “0”
state, they are unefiected, while the core S1 does switch
switching, the storage cores S1 and S2 each switch to only
the “half-one” state. At the termination of the IRA clock
from the “1” to the “0” state and in so doing induces a
pulse, the cores C2, I2 and 13 are left in the “0” remanence
voltage on the output winding 1 with the dotted end posi
state, while the storage cores S1 and S2 are left in the
“half-one” remanence state. The clock pulse source IB
flow in the loop E. This counterclockwise current flow
now directs a read signal into the windings 32, 33 and 11
tends to write the cores S2, C3, I2 and 13 while tending to
on the cores I2, 13 and S1, respectively, which leaves the
read the cores C1 and C2. Since each of the cores C1 and
cores I2 and I3 uneifected since they are already in the
C2 are already in the “0” state and the cores I2 and I3 35 “0” state, but switches the core S1 from the “half-one”
are held in the "0” state by virtue of the IB drive, and
state toward the “0” state and in so doing induces a volt
the core S3 is already in the “1” state; negligible voltage
age on the output winding 1, with the dotted end positive
drop appears on the windings 3, 2, 26, 27 and 5, respec
causing a counterclockwise current flow in the loop‘ E.
tively, allowing the core C3 to switch from the "0” to the
This counterclockwise current ?ow tends to write the
“1” state. The core C3 in switching induces a voltage on 40 cores S2 and C3, but, since the core S2 is in only the “half
tive, which voltage causes a counterclockwise current
its output winding 6 with the undotted end positive, to
one” state, and only half the volt-time product is available
cause a counterclockwise current flow in the loop B. This
from the core S1, this volt-time product is completely dis
counterclockwise current ?ow is directed into the un
dotted end of the winding 7 on the core S3 and fully
switches the core S3 from the “0” to the "1” state. At the
sipated in preferential switching of the core S2 to the “1”
state. At the termination of the 13 clock pulse, all the
termination ‘of the 13 clock pulse, the core S1 is left in
the “0” state, while the cores S2, C3 and 5;, are left in the
“1” state. The clock pulse source IRB subsequently
operates to direct a read signal into the windings 34, 35‘,
12, 13 and 14-‘ on the cores I2, 13, S1, S2 and C3, respec
tively. Since the cores I2, 13 and S1 are already in the
“0” state, they are uneffected. The cores S2 and C3, how
ever, are switched from the “l” to the “0” state which
causes a large flux change to occur in each of the cores.
This ?ux change induces a voltage
on the windinvs
5, 4- .
D
b
cores are left in the “0” state except the storage cores S2
which is left in the "1” remanence state. The subsequent
clock pulse source 1R3 directs a read signal into the wind
ings 34, 35, 12, 13 and 14 on the cores I2, I3, S1, S2 and C3,
respectively, which signal effects only the core S2 to switch
from the “1” to the
state, and in so doing induce a
voltage on the output winding 5 with the dotted end posi~
tive, causing a counterclockwise current how in the loop
E.
This counterclockwise current ?ow is such as to
The counterclockwise current flow in loop E
write the cores C3, 12, I3 and S1 while tending to read the
cores C1 and C2. The cores C1 and C2 are uneiiected
since they are already in the “0” state, while the cores
C3, I2, 1;, and S1 are held in the “0” state by the IRB drive.
At the termination of the IRB clock pulse all cores are left
in the “0” state. Thus since there was an input available
tends to read the cores C1 and C2 while tending to write
the cores I2, 13 and S1. ‘Since the cores C1 and C2 are
to the core C2, no signal was transferred to the storage
core S3 due to clock pulse sources, and the circuit is
already in the “0” state, they are uneffected, while the
cores 12, I3 and S1 are held in the “0” state by virtue of
the IRB drive. The clockwise current ?ow in the loop B
is blocked and its energy is dissipated by the high back
resistance of the diode D2. Thus since neither one, nor
both of the possible inputs were available the circuit de
livered a signal to the core S3 which signal is delivered
through the core C4 in the next cycle of operation when
the IA clock pulse is applied, and all the cores associated
ready for the next cycle of operation.
It again follows, from the above described operation,
and 6 on the cores S2 and C3, respectively, with the dotted
end positive, to cause a counterclockwise current ?ow in
loop E, and tending to cause a clockwise current ?ow in
loop B.
with loop E are left in the “0” remanence state readying
the circuit for the next cycle of operation.
Assume an input signal is directed into the input wind
ing 17 on the core C2. The core C2 switches from the
“0” to the “1” state and in so doing induces a voltage on
that if an input were directed into the winding 16 on the
core C1, the eltect is the same, in that no output signal is
produced to write the core S3.
Assume in the next operation, that an input is directed
into the windings 16 and 17 on the cores C1 and C2, re
spectively. As a result, the cores C1 and C2 switch from
the “0” to the “1” state and in so doing induce a voltage
on the output windings 3 and 2, respectively, with the
undotted end positive. At the same time, as described
above, the cores I2 and T3 are also switched from the “0”
to the’ “1” state, due to the operation of the IA clock pulse
source. The cores I2 and Is in switching to the “1” state
8,090,036
13
induce a voltage on the output windings ‘26 and 27, re
Winding means and said input winding means on said
spectively, with the undotted end positive. The algebraic
third coupling core; a ?rst, a second and a third clock
sum of the induced voltages is such as to effectively cancel
each other and allow negligible current flow. At the con
clusion of the input pulses and the IA clock pulse, the
cores C1, C2, 1; and 13 are left in the “1” remanence
state. The IRE clock pulse source then directs a read
signal into the windings 9, 10, 30 and 31 on the cores C1,
pulse source adapted to deliver a series of pulses displaced
in time; winding means on said ?rst and second coupling
cores connected with said ?rst clock pulse source and
adapted to drive said ?rst and second coupling cores to
ward a zero residual state when energized; winding
means on said ?rst storage core connected with said
C2, I2 and I3, respectively; which switches each of the
second clock pulse source and adapted to ‘drive said ?rst
the dotted end positive. The algebraic sum of the in
duced voltages is such as to again effectively cancel and
allow negligible current flow in the ‘loop E. At the ter
third coupling core connected with said third clock pulse
cores from. the “l” to the “0” state to induce a voltage 10 storage core toward the zero state when energized; Wind
ing means on said ?rst and second storage cores and said
on their output windings 3, 2, 26 and 27‘, respectively, with
mination of the IRA clock pulse the cores C1, C2, C7 and
C8 are ‘left in the r‘0” remanence state, and the IB clock
pulse source now directs a read signal into the windings
32, 35 and 11 on the cores I2, 13 and S1, respectively,
which has no effect since all the cores are already in the
“0” state.
source adapted to drive said ?rst and second storage cores
and said third coupling ‘core toward the zero state when
energized.
2. A logical “and” circuit comprising a ?rst and a
second magnetic storage core each capable of attaining
opposite datum and binary one representing states of
residual magnetization and a partially switched state inter
Subsequently, the IRB clock pulse source 20 mediate thereto, said cores being formed of material hav
directs a read signal into the windings 34‘, 35, 12, 13 and
14- on the cores I2, I3, S1, S2 and C3, respectively, which
has no effect since again all cores are in the “0” state and
again no transfer of energy takes place. Thus, the cir
cuit has performed the logical function of NEfTHER
NOR.
In the interest of providing a complete disclosure de
tails of one embodiment of the invention wherein ferrite
cores are employed, component values and current magni
tudes are given below, which, however, is to be under
stood to be in no way limiting in that other component
values and current magnitudes may be employed with
satisfactory operation.
With the clock pulse currents IA and is delivering a
constant current of 1.9 amperes, the windings 28 and 29
may comprise four turns, the windings 11, 15, 32 and 33
may comprise ten turns; and with the clock pulse currents
IRA and IRE delivering 1.1 amperes, the windings 9, 10,
14, 30, 31, 34 and 35 may comprise ?ve turns while the
windings 1‘2 and 13 may comprise ten turns.
In the
coupling circuits interconnecting the storage and coupling
cores, the windings 1, 5 and 7 may comprise ten turns,
the ‘windings 4, 16, 17 and 18 may comprise ?ve turns and
the windings 2, 3, 6, 26 and 27 may comprise twelve
turns, ‘with the diodes D1 and D2 of low forward imped
ance having a sut?cient recovery time such as an IN 270
diode manufactured by the Transitron Company.
In this particular embodiment each of the clock pulse
currents IA, ERA, IB and IRE may be a one microsecond
pulse having a two-tenths microsecond rise time. Each
of the S and C cores may comprise toroids of magnesium
manganese ferrite composition having an outside diameter
of 0.100 inch, inside diameter of 0.070 inch and a thick—
ness of 0.120 inch. This thickness may be obtained by
ing a substantially rectangular hysteresis characteristic;
control winding means on each of said storage cores;
a ?rst, a second and a third coupling core; input and out
put winding means on each of said coupling cores; circuit
means including an asymmetrical impedance device con
necting the output winding means on said ?rst and second
coupling cores, said control winding means and said in
put winding means on said third coupling core; shift wind
ing means on said ?rst coupling core connected in series
with shift winding means on said second coupling core
adapted to drive said ?rst and said second coupling cores
toward a datum residual state when energized from a ?rst
clock pulse source; shift winding means on said ?rst stor
age core adapted to drive said ?rst storage core toward the
datum residual state when energized from a second clock
pulse source; shift winding means on said ?rst storage
core series connected to shift winding means on said sec
ond storage core and shift winding means on said third
coupling core adapted to drive said ?rst and second stor—
age cores and said third coupling core toward the datum
residual state when energized from a third clock pulse
source.
3. A circuit as described in claim 2 including means
for energizing said shift winding means comprising said
?rst, second and third clock pulse sources, said sources
being actuated in sequence in the order named.
4. A logical “and” circuit comprising a plurality of
magnetic storage cores each capable of attaining selective
states of residual magnetization intermediate a ?rst and a
second limiting state of residual magnetization; a like
plurality of input coupling cores; an output coupling
core; control winding means on each of said storage cores;
input and output winding means on each of said cou
pling cores; circuit means connecting the output winding
stacking four cores each of 0.030 thickness and winding
means on said input coupling cores; said control winding
the stack as a single core unit.
means on each of said storage cores and the input winding
While there have been shown and described and point
means on said output coupling core; shift winding means
ed out the fundamental novel features of the invention
on each of said input coupling cores adapted to be en
as applied to a preferred embodiment, it will be under
ergized simultaneously and to drive said input coupling
s‘ood that various omissions and substitutions and changes 60 cores toward the ?rst residual state; additional shift
in the form and details of the device illustrated and in its
winding means on one of said storage cores adapted to
operation may be made by those skilled in the art without
drive said one of said storage cores toward the ?rst resid
departing from the spirit of the invention. it is the in—
ual state when energized; further shift winding means
tention therefore, to be limited only as indicated by the
on each of said storage cores and said output coupling core
following claims.
What is claimed is:
1. A logical “and” circuit comprising a ?rst and a
second magnetic storage core each capable of attaining
opposite zero and one representative states of residual
magnetization and a state intermediate thereto; control
winding means on each of said storage cores; a ?rst, a
second and a third coupling core; input and output wind
ing means on each of said coupling cores; circuit means
including a diode series connecting the output winding
means on said ?rst and second coupling cores, said control 75
adapted to be energized simultaneously and to drive said
storage cores and said output coupling core toward the
?rst residual state.
5. A logical “and” circuit comprising a ?rst and a sec
ond magnetic storage core each capable of selectively
attaining half states of residual magnetization interme
diate zero and one representing residual states; control
winding means on each of said storage cores; a ?rst, a sec
ond, a third and a fourth coupling core; input and output
winding means on each of said coupling cores; an in
3,090,086
15
hibit core; output winding means on said inhibit core;
circuit means including a diode series connecting the
output winding means on said ?rst, second and third cou
pling cores and said i aiblt core, said control winding
means on said ?rst and second storage cores and
said input winding means on said fourth coupling core;
a ?rst, a second, a third and a fourth clock pulse source
adapted to deliver a series of pulses displaced in time;
Winding means on said ?rst, second and third couplingr
16
cal impedance device coupling the output winding means
on said ?rst, second and third coupling cores and said
inhibit core, said control winding means on said ?rst and
second storage cores and said input winding means on said
fourth coupling core; shift winding means on each of said
?rst, second and third coupling cores and said inhibit core
adapted to be energized simultaneously and to drive said
?rst, second and third coupling cores and said inhibit
core toward the ?rst residual state when energized; addi
cores and said inhibit core connected with said ?rst clock 10 tional shift winding means on said inhibit core and shift
winding means on said ?rst storage core adapted to be
pulse source and ‘adapted to drive said ?rst, second and
energized simultaneously and to drive said inhibit core and
third couplintr cores and said inhibit core toward a Zero
said ?rst storage core toward the ?rst residual state when
residual state when energized; Winding means on said in
energized; further shift winding means on said inhibit
hibit core and said ?rst storage core connected with said
second clock pulse source and adapted to drive said inhibit 15 core; on each of said storage cores and said fourth cou
pling core adapted to be energized simultaneously and to
coupling core and said ?rst storage core toward the zero
drive said inhibit core, each of said storage cores and said
residual state when energized; winding means on said
fourth coupling core toward the ?rst residual state when
inhibit core, said ?rst and second storage cores and said
energized; and shift winding means on said inhibit core
fourth coupling core connected with said third clock pulse
source and adapted to drive said inhibit core, said ?rst 20 adapted to drive said inhibit core toward the second resid
ual state.
and second storage cores and said fourth coupling core
9. A logical “neither nor” circuit comprising a ?rst
toward the zero residual state when energized; winding
and a second magnetic storage core each capable of selec
means on said inhibit core connected with said fourth
clock pulse source and adapted to drive said inhibit
tively attaining half states of residual magnetization inter
core to a one residual state when energized.
mediate zero and one representing residual states; control
winding means on each of said storage cores; a ?rst, a
6. A logical “and” circuit comprising a ?rst and a
second magnetic storage core each formed of a magnetic
material having a substantially rectangular hysteresis char
acteristic and capable of selective attainment of half states
of residual magnetization intermediate ?rst and second
residual states; control winding means on each of said
storage cores; a ?rst, a second, a third and a fourth cou
pling core; input and output winding means on each of
said coupling cores; an inhibit core; output winding
means on said inhibit core; circuit means including an
asymmetrical impedance device connecting the output
winding means on said ?rst, second and third coupling
second and a third coupling core; input and output wind
ing means on each of said coupling cores; :1 ?rst and a
second inhibit core; output winding on each of said inhibit
cores; circuit means including a diode series connecting the
output winding means on each of sm'd first and second
coupling cores and said inhibit cores, said control winding
means on each of said storage cores and said input wind
ing means on said third coupling cores; a ?rst, a second, a
third and a fourth clock pulse source adapted to deliver
a series of pulses displaced in time; winding means on said
?rst and second coupling cores and said ?rst and second
inhibit cores connected with said ?rst clock pulse source
and adapted to drive said ?rst and second Coupling core
cores and said inhibit core, said control winding means
on said ?rst and second storage cores and said input wind
ing means on said fourth coupling core; shift winding 40 and said ?rst and second inhibit core toward a zero resid
ual state when energized; winding means on said first
means on each of said ?rst, second and third coupling
and second inhibit cores and said ?rst storage core con
cores series connected with shift winding means on said
nected with said second clock pulse source and adapted to
inhibit core adapted to drive said ?rst, second and third
drive said ?rst and second inhibit cores and said ?rst stor
coupling cores and said inhibit core toward a ?rst residual
state when energized from a ?rst clock pulse source; 45 age core toward the zero residual state when energized;
winding means on said inhibit cores, said storage cores
shift winding means on said inhibit core series connected
and said third coupling core connected with said said third
with shift winding means on said ?rst storage core adapt
clock pulse source and adapted to drive said inhibit cores,
ed to drive said inhibit core and said ?rst storage core
said storage cores and said third coupling core toward the
toward the ?rst residual state when energized from a
zero
residual state when energized; winding means on said
second clock pulse source; shift winding means on said 50 inhibit cores connected with said fourth clock pulse source
inhibit core series connected with shift Winding means on
and adapted to drive said inhibit cores toward a one resid
each of said ?rst and second storage cores and shift wind_
ual state when energized.
ing means on said fourth coupling core adapted to drive
10. A logical “neither nor” circuit comprising a ?rst
said inhibit core, said ?rst and second storage cores and
and a second magnetic storage core each of said cores
said fourth coupling core toward the ?rst residual state
made of material having a substantially rectangular hys
when energized from a third clock pulse source; shift
teresis characteristic and capable of attaining half states
winding means on said inhibit core adapted to drive said
of residual magnetization; intermediate ?rst and second
inhibit core toward a second residual state in a direction
residual states; control winding means on each of said
opposite to said ?rst state when energized from a fourth
60 cores; a ?rst, a second and a third coupling core; input
clock pulse source.
and output winding means on each of said coupling cores;
7. A circuit as described in claim 6 including means
a ?rst and a second inhibit core; output winding means
for energizing said shift winding means comprising said
?rst, second, third and fourth clock pulse sources where
on each of said inhibit cores; circuit means including an
asymmetrical impedance device connecting the output
in said sources are actuated in sequence in the order
winding means on said ?rst and second coupling cores
65
named.
and said inhibit cores, said control winding means on said
8. A logical “and” circuit comprising a ?rst and a
storage cores and said input winding means on said third
second magnetic storage core each of said cores capable of
coupling core; shift winding means on each of said ?rst
selective attainment of states of residual magnetization
and second coupling cores series connected with shift
intermediate a ?rst and a second limiting state of residual
winding means on each of said inhibit cores adapted to
magnetization; control winding means on each of said
drive said ?rst and second coupling cores and said inhibit
storage cores; a ?rst, a second, a third and a fourth cou
cores toward a ?rst residual state when energized from a
pling core; input and output winding means on each of
?rst clock pulse source; shift winding means on each of
said coupling cores; an inhibit core; output winding means
said inhibit cores series connected with shift winding
on said inhibit core; circuit means including an asymmetri 75 means on said ?rst storage core adapted to drive said
3,090,036
17
inhibit cores and said ?rst storage core toward the ?rst
residual state when energized from a second clock pulse
source; shift winding means on each of said inhibit cores
series connected with shift winding means on each of said
storage cores and said third coupling core adapted to
drive each of said inhibit cores, said storage cores and said
18
necting said control windings; means for selectively ener
gizing said reset windings to establish said cores in the
zero residual state; said signal means adapted to. apply
a signal to said control windings to read in a bit of in
formation and selectively establish said cores in the inter
mediate and one limiting states; and means for resetting
third coupling core toward the ?rst residual state when
energized from a third clock pulse source; and shift wind~
said?rst core to the zero residual state to produce an
ond residual state in a direction opposite from said ?rst
residual state when energized from a fourth clock pulse
rality of magnetic storage cores each capable of attaining
selectively residual states of magnetization intermediate
output in said control winding means the magnitude of
which is indicative of the magnetization force necessary
ing means on said ?rst inhibit core series connected with
shift winding ‘means on said second inhibit core adapted 10 to establish both of said cores in the one residual state.
16. An information controlling device including a plu
to drive said ?rst and second inhibit cores toward a sec
andincluding a ?rst and a second limiting residual state;
11. A circuit as described in claim 10 including means 15 winding means on each of said cores; signal means oper
source.
for energizing said shift winding means comprising said
?rst, second, third and fourth clock pulse sources wherein
ably connected with said winding means; said signal
means comprising ?rst means selectively applying a ?rst
said sources are actuated in sequence in the order named.
signal to said ‘winding means to simultaneously establish
12. A magnetic core circuit comprising a plurality of
said cores in the ?rst residual state; second means apply
ing a second signal to said winding means to read in in
formation by establishing each of said cores in a selective
residual state, and third means applying a third signal
magnetic storage cores each capable of retaining selective
states of residual magnetization intermediate a ?rst and
a second limiting state of residual magnetization; control
winding means on each of said cores; a like plurality of
inhibit cores; output windings on each of said inhibit
cores; a like plurality of input coupling cores; an output
coupling core; input and output winding means on each
of said coupling cores; circuit means including an asym
to said winding means to reset at least one of said cores
to the ?rst residual state and produce an output in a series
connected winding coupling each of said cores the mag
nitude of which is indicative of the magnetizing force
necessary to establish all of said cores in the second resid
metrical impedance device connecting the ouput winding
ual state.
17. An information controlling device including a plu
means on said input coupling cores and said inhibit cores,
said control winding means on each of said storage cores 30 rality of magnetic storage cores each of said cores capable
and said input winding means on said output coupling
core; shift winding means on each of said input coupling
cores and each of said inhibit cores adapted to be ener
of attaining selective residual states of magnetization
intermediate and including a ?rst and a second limiting
residual state and formed of material having a substan
gized simultaneously and to drive said input coupling cores
and said inhibit cores toward the ?rst residual state; addi
tional shift winding means on each of said inhibit cores
and one of said storage cores adapted to be energized
tially rectangular hysteresis characteristic; winding means
simultaneously and ‘to drive said inhibit cores and said one
means to simultaneously establish each of said cores in the
?rst limiting state, second means adapted to apply a second
signal to further ones of said winding means to cause
all of said cores to assume a selective residual state in
of said storage cores toward the ?rst residual state; further
shift Winding means on each of said inhibit cores and said
storage cores and said output coupling core adapted to be
energized simultaneously and to drive said inhibit cores,
said storage cores and said output coupling core toward
the ?rst residual state; and shift winding means on each of
said inhibit cores adapted to be energized simultaneously 45
and to drive said inhibit cores toward the second residual
state.
on each of said cores; signal means operably connected
with said winding means; said signal means comprising
first means adapted to apply a ?rst signal to said winding
representing said information, and third means adapted to
apply a third signal to another one of said winding means
on at least one of said storage cores to reset at least
said one of said storage cores to the ?rst limiting state
and produce an output in said winding means the magni
tude of which is indicative of the ‘magnetizing force neces
sary to establish all of said cores in the second limiting
13. A logical information transfer circuit including a
plurality of magnetic storage means each capable of at
state.
taining selective states of residual magnetization inter 50
18. In an information handling circuit, a ?rst and a
mediate a ?rst and a second limiting state; control means
second magnetic core made of material exhibiting ?rst
on each of said storage means; a plurality of input means;
and second limiting stable states of remanent ?ux density,
circuit means series connecting said control means and
winding means inductively coupled to said cores, means
coupling said input means; signal means operably con
for energizing said winding means during a ?rst and a
nected with said input means; pulse means connected 55 second interval of time comprising, ?rst means energiz
with said storage means; said pulse means being operable
ing said winding means during the ?rst interval of time
to apply a ?rst pulse to said storage means and establish
said storage means in the ?rst limiting residual state; said
for establishing both said cores in a similar stable state
of ?ux density intermediate said limiting states which
conjointly de?nes said information, and second means
signal to said input means and read in information by 60 energizing said winding means during said second in
signal means thereafter being operable to selectively apply
establishing said storage means in a selective residual
terval of time for establishing said ?rst core in said
state; said pulse means being operable to apply a second
?rst limiting state and to read out said information.
pulse to said storage means and establish said ?rst stor
19. In a circuit, a ?rst and a second magnetic core
age means in the ?rst limiting residual state and to pro
each made of magnetic material exhibiting different states
duce an output in said control means indicative of the 65 of remanence intermediate and including a ?rst and a
magnetization necessary to establish all of said storage
second limiting state, a plurality of windings on said
means in said second limiting residual state.
cores, means for energizing said windings during a ?rst
14‘ A circuit as described in claim 13 wherein said
interval of time for Writing in a binary value and during
storage means comprise magnetic storage cores.
a second interval of time for reading out said binary
15. An information controlling device including a ?rst 70 value comprising, ?rst means energizing said plurality
and a second magnetic storage core each capable of attain
of windings during said ?rst interval of time for estab
in g selective half states of magnetization intermediate and
lshing both said cores in intermediate remanence states,
including a zero and a one limiting state; each of said
said cores in said intermediate remanence states jointly
cores having a reset winding and a control winding there
representing said binary value, and second means there
75
on; circuit means including a signal means series con
3,090,036
after energizing said plurality of windings during the
second interval of time for establishing both said cores
in limiting remanence states to read out said binary value.
20. The circuit as set forth in claim 19, wherein both
said cores are established in the same remanence state
during the ?rst interval of time.
21. In a circuit, a ?rst and a second magnetic core
each made of material exhibiting appreciable remanence,
each said core capable of attaining different states of
remanence intermediate and including a ?rst and a second
limiting state, a plurality of windings inductively asso
ciated with each said core, means for energizing the
windings of each core during a ?rst, a second and a third
interval of time comprising, ?rst means energizing said
windings during said ?rst interval of time for establishing
said cores in said ?rst limiting state, second means ener
gizing said windings during the second interval of time
for writing in a binary bit of information and establish
20
said Winding means during the ?rst interval of time for
establishing said cores in either said ?rst or second com
binatorial state to represent a binary value and said last
means energizing said winding means during the second
interval of time for establishing said cores in the third
combinatorial state to read out said binary value.
23. The circuit as set forth in claim 22, wherein the
?rst and second stable states of both said cores are ‘op
posite limiting states of ?ux remanence.
24. In a circuit, a ?rst and a second magnetic core,
said cores formed of material exhibiting appreciable
remanence, each said core adapted to assume a ?rst, a
second and a third stable remanence state, where at least
one of the stable states of each said core is a state other
than a limiting state and another of said states is a limit
ing state, one of the stable states of said ?rst core and one
of the stable states of said second core constituting a ?rst
combinatorial state for both cores, another of the stable
ing both said cores in intermediate states of remanence,
states of said ?rst core and another of the stable states of
and third means energizing said windings during the third 20 said second core constituting a second combinatorial state
interval of time for establishing both said cores in a limit
for both said cores, the remaining stable state of said ?rst
ing state of remanence whereby the state established in
core and the remaining stable state of said second core
said cores during the second interval of time and thus
constituting a third combinatorial state for both said
the binary information represented thereby is read out.
cores, winding means coupling said cores, means for en
22. In a circuit, a ?rst and a second magnetic core,
ergizing said winding means during a ?rst, a second and
said cores formed of material exhibiting appreciable rema
a third interval of time; said last means energizing said
nence, each said core adapted to assume a ?rst, a second
Winding means during said ?rst interval of time for es
and a third stable remanence state, where at least one
tablishing said cores in the ?rst combinatorial state, said
of the stable states of each core is a state other than a
last means energizing said winding means during the sec~
limiting ‘state and another of said states is a limiting 30 0nd interval of time for establishing said cores in the
state, one of the stable states of said ?rst core and one
second combinatorial state whereby the joint states of said
of the stable states of said second core constituting a
?rst combinatorial state for both cores, another of the
stable states of said ?rst core and another of the stable
cores represent a binary value, and said last means en
ergizing said Winding means during the third interval of
time for establishing said cores in the third combinatorial
states of said second core constituting a second com 35 state to thereby read out said binary value.
binatorial state for both said cores, the remaining stable
References Cited in the ?le of this patent
state ‘of said ?rst core and the remaining stable state of
said second core constituting a third combinatorial state
UNITED STATES PATENTS
for both said cores, winding means coupling said cores,
2,753,545
Lund ________________ __ July 3, 1956
means for energizing said winding means during a ?rst 4 O
and a second interval of time, said last means energizing
2,768,312
2,931,014
Goodale et al. _______ _._ Oct. 23, 1956
Buchholz et al ________ __ Mar. 29, 1960
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