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Патент USA US3091673

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May 28, 1963
w. v. TYRLIcK
3,091,664
DELTA MODULATOR FOR A TIME DIVISION MULTIPLEX SYSTEM
Filed April 24, 1961
2 Sheets-Sheet 1
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INVENTOR.
WILL/AM M TYRL/CK
I
May 28, 1963
w. v. TYRLICK
3,091,664
DELTA MODULATOR FOR A TIME DIVISION MULTIPLEX SYSTEM
Filed April 24, 1961
2 Sheets-Sheet 2
OUTPUT
OUTPUT
/
200
_ DELAY
LINE
206
CLOCK
2“)
PULSES
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SUBTRACT
g 306
ADD
300
_I
3|0
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302
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308
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_______D——————C
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3,001,554
United States Patent 0 "
Patented May 28, 1963
2
1
exceeding the magnitude of the second input. Discrimi
nator 102, for instance, may consist of a normally cutoff
3,091,664
DELTA MODULATOR FOR A TIME DIVISION
MULTIPLEX SYSTEM
William V. Tyrlick, Rochester, N.Y., assignor to General
high gain switching ampli?er to which a ?rst input is
Dynamics Corporation, Rochester, N.Y., a corporation
?rst input exceeds
ampli?er is turned
of Delaware
Filed Apr. 24, 1961, Ser. No. 105,122
9 Claims. (Cl. 179-15)
applied tending to switch the ampli?er
input is applied tending to maintain
Therefore, when the magnitude of the
the magnitude of the second input the
on while a second
the ampli?er o?‘.
on, and an output is derived, and when the magnitude of
the second input exceeds the magnitude of the ?rst input,
This invention relates to a time division multiplex 10 the ampli?er is maintained off and no output is derived.
The output from discriminator 102 is applied directly as
switching system and, more particularly, to such a system
a ?rst input to AND gate 104 and is applied through
utilizing delta modulation for transmitting time multi
inverter 106 as a ?rst input to AND gate 108. Clock
plexed information to a receiving point in digital form.
pulses, from a source not shown, are applied as second
It is often necessary to transmit time multiplexed
analog signals from an originating point at which they are 15 inputs to both AND gates 104 and 108.
The output of AND gate 104 is applied as a ?rst input
derived to a receiving point at which they are utilized.
One well known scheme for transmitting this informa
tion is the use of a resonant transfer.
However, the use
to a bistable device, such as flip-?op 110, to effect the
switching of ?ip-?op 110‘ to a ?rst stable condition thereof.
The output from AND gate 108 is applied as a second
of resonant transfer creates the problem of maintaining
the amplitude and power of each time multiplexed sample, 20 input to flip-flop 110 to effect the switching of ?ip-?op 11c’)
as well as the time position thereof. This problem may be
overcome by converting the analog information to digital
information at the originating point, transmitting the
to a second stable condition thereof.
When flip-?op 110 is in its ?rst stable condition, an add
control signal is applied to delay line reversible counter
112. When ?ip-?op 110 is in its second stable condition,
digital information to the receiving point, and converting
the digital information back to analog information. How 25 a subtract control signal is applied to delay line reversible
ever, this is not too practical since a code consisting of
a plurality of bits is necessary to manifest each of the
counter 112. Clock pulses, from a source not shown, are
applied as an input to delay line reversible counter 112.
The output from delay line reversible counter ‘112 is
applied as an input to digital to analog converter 11-45.
makes it possible to transmit the desired information from 30 The output from digital to analog converter 114 is applied
as the second input to discriminator 102.
the originating point to the receiving point with a single
The output from AND gate 104 is also applied through
bit code.
a
transmission path 116 extending to a receiving point
It is, therefore, an object of the present invention to
where
it is applied directly as a first input to: AND gate
utilize delta modulation for transmitting time multiplexed
118 and through inverter 120 as a ?rst input to AND
analog samples from an originating point to a receiving
signal levels of the time multiplexed analog samples.
The present invention, by utilizing delta modulation,
gate 122.
point.
Clock pulses from a source not shown ‘are
applied as second inputs to both AND gates 118 and 122.
The output of AND gate 118 is applied as a ?rst input
This and other objects, advantages and features of the
present invention will become more apparent from the
to a bistable device, Such as ?ip-flop 124, to effect the
following detailed description taken together with the
4:0 switching thereof to a ?rst stable condition and the output
accompanying drawings, in which:
of AND gate 112 is applied as a second input to ?ip‘tlop
FIG. 1 is a block diagram of a preferred embodiment
124 to effect the switching thereof to a second stable condi
of the invention;
tion. In response to ?ip-flop 124 being ‘in its ?rst stable
FIG. 2 is a block diagram of a delay line reversible
condition, an add control signal is applied to delay line
counted shown in FIG. 1; and
FIG. 3 is a block diagram of a half adder subtracter 45 reversible counter 126. In response to ?ip-flop 124 being
in its second stable condition, a subtract control signal is
shown in FIG. 2.
applied to delay line reversible counter 126. Clock pulses
Referring to FIG. 1, there is shown a plurality of lines
from a source not shown are also applied to delay line
consisting of line 1 to line n, on any of which may be
reversible counter 126.
placed an analog signal. As shown, each of the lines is
The output of delay line reversible counter 126 is
applied as a ?rst input to an associated analog signal 50
applied through digital to ‘analog converter 128 and
sampling gate, line 1 being applied as a ?rst input to gate
ampli?er 130 as a ?rst input to a plurality of analog
100-1 and line n being applied as a ?rst input to gate
gates, such as gate 1324 and gate 132—n.
100—n.
Demultiplexing is accomplished by applying timing
In accordance with well known time division multi
55 pulses, such as TPa’ and TPk’, to the analog gates in
plexing practice, each gate is alotted a different time
appropriate time slots. The output of each gate is passed
slot and a respective timing pulse occurring in the appro
through an individual line ?lter, such as line ?lter 1342-1
priate time slot is periodically applied to each gate once
and 13441, to an individual line coupled thereto, such as
each frame period. As shown, timing pulse TPa is applied
line 1’ and line n’.
to gate 100—1 and timing pulse TPk is applied to gate
Referring now to FIG. 2, which shows a block diagram
10042. Each of the gates is opened only in response to 60
of ‘a delay line reversible counter, such as delay line revers
the application of a timing pulse thereto to provide
ible counter 112 and 126, a reversible delay line counter
samples of the signal level of the analog signal applied
consists of a plurality of cascaded stages, only the ?rst
thereto each time a gate is opened.
Thus, time multiplexed samples of the various applied
analog signals appear at the outputs of gates 100—1 65
to 100—n, which are multipled, as Shown, ‘and applied as
a ?rst input to discriminator 102.
Discriminator 102 is a device for comparing the relative
magnitudes of signals applied to a ?rst input and to a
second input thereof and producing a ?xed magnitude
output only in response to the magnitude of the ?rst input
two of which are shown.
Each stage consists of a half adder subtracter and a de
lay line having a delay equal to one frame period. As
shown, the output of delay line 200 of the ?rst stage is
applied as a ?rst input to half adder subtracter 202 and
clock pulses are applied as a second input to half adder
70 subtracter 202.
Half adder subtracter 202 has a sum
output, designated S, a borrow output designated B and
..~
.
3
3,091,664
4
a carry output designated C. The sum output is applied
At the receiving point, delay line reversible counter
as an input to delay line 200‘ to the recirculated. The bor
row output of half adder subtracterw202 is applied as a
second input to half adder subtracter 204 through nor
1=26 integrates the successive :bits supplied over transmis
sion path 116, and through digital to analog converter
128 provides a signal level which follows the signal level
mally closed AND gate 1206, which is opened only in
of the original time multiplexed analog samples. After
demultiplexing by gates 132-1 to 132-11 and smoothing
response to the presence of a subtract control signal, and
OR gate 208. The carry output of half adder subtracter
202 is applied as a second input to half adder subtracter
by line ?lters 134-1 to -1=34-n, the original analog signals
are reconstructed.
204 through normally closed AND gate 210, which is
Although only a preferred embodiment of this inven
opened only in response to the presence of an add con 10 tion has been described in detail herein, it is not intended
trol signal, and OR gate 208.
that the invention be restricted thereto, but that it be
The output of delay line 212 is applied as a ?rst input
limited only by the true spirit and scope of the appended
to half adder subtracter 204.
claims.
In a manner similar to half adder subtracter 202, the
What is claimed is:
sum output of half adder subtracter 204 is applied as an 15
1. In a time division multiplex system having a given
input to delay line 212 and the borrow and carry outputs
frame period, a plurality of analog signal sources, time
of half adder subtracter 204 are applied through AND
multiplex means for sequentially sampling each of said
gates 214 and 216 and OR gate 218, which correspond,
sources each frame period, ?rst means coupled to said
respectively, to A-ND gates 206, 210, and OR gate 208
time multiplex means, said ?rst means including delay
to the next stage of the delay line reversible counter, not 20 means having a delay equal to one frame period for se
shown.
quentially comparing the relative levels of the time multi
The output of the delay line reversible counter is ob
plexed samples of each individual analog signal applied
tained, as shown, at the outputs of the respective delay
thereto during successive frames to produce a momentary
lines, such as delay line 200' and delay line 2112.
output signal having a respective one of ?rst and second
Referring now to FIG. 3, there is shown one embodi 25 predetermined values in accordance with whether the
ment of a half adder subtracter. As shown, a half adder
level of the sample of that individual analog signal dur
subtracter consists of AND gates 300, 302 and 304. The
ing a frame is greater or smaller than the level of the
?rst input to the half adder subtracter is applied direct
sample of that individual analog signal during the previ
ly as a ?rst input to AND gates 302 and 304 and through
ous frame, second means for transmitting successive out
inverter 306 as a?rst input to AND gate 300. The sec 30 put signals to a receiving point, and third means includ
ond input to the half adder subtracter is applied directly
ing demultiplexing means at said receiving point having
as a second input to AND gates 300 and 304 and through
inverter 308 as a second input to AND gate 302. The
said successive output signals applied as an input thereto
for reconstructing said analog signals in accordance with
outputs of AND gates 300 and 302 are passed through
OR gate 310 to obtain the sum output. The borrow out
35
put is obtained at the output of AND gate 300 and the
carry output is obtained at the output of AND gate 304.
Considering the operation of the circuits shown in
the respective values of each of said successive output
signals.
2. The system de?ned in claim 1, wherein said ?rst
means includes a delay line reversible counter having a
delay equal to one frame period for adding clock pulses
FIG. 1, the loop consisting of discriminator .102, AND
applied thereto in response to a concurrently applied add
gate 104, inverter 106 and AND gate 108, ?ip-?op 110, 40 control signal and for subtracting clock pulses applied
delay line reversible counter 112 and digital to analog
thereto in response to a concurrently applied subtract
converter 114 provide means for tracking the signal level
control signal, a discriminator producing a ?xed ampli
of each time multiplexed analog sample applied to dis
tude output pulse only in response to the level of a ?rst
criminator 102. Due to the delay of one frame period
input applied thereto exceeding the level of a second in
provided by ‘delay line reversible counter 1/12, the out 45 put applied thereto, means for applying time multiplexed
put from delay line reversible counter 1:12 manifests in
samples of analog signals as said ?rst input to said dis
binary form the approximate value of the signal level of
criminator, a digital to analog converter coupling the out
a time multiplexed sample existing in a previous frame
put of said counter to said discriminator for applying as
period. This :binary output is converted to an equivalent
said second input to said‘ discriminator a signal level
analog signal level by digital to analog converter 1114 and 50 proportional
to the count manifested by the output of
compared by discriminator 102 to the signal level of the
said counter, and control means coupling said discrimi
corresponding time multiplexed analog sample existing in
nator to said counter for applying an add control signal
a present frame. If the signal level of the time multi
to said counter in response to an output pulse from said
plexed analog sample of the present frame exceeds that
discriminator and for applying a subtract control signal
of the previous frame, the binary number stored in de 55 to
said counter in response to the absence of an output
lay line reversible counter 112 is increased by one unit.
pulse from said discriminator, and wherein said second
This, in turn, causes digital to analog converter 1:14 to
means includes means for transmitting the output of said
apply an incrementally higher analog signal level to dis
discriminator to said receiving point.
criminator 102 during the next frame period. If, on the
3. The system de?ned in claim 2, wherein said control
60
other hand, the analog signal level of the previous frame
means includes a bistable device for producing said add
exceeds the signal level of the time multiplexed analog
control signal in response to a ?rst stable condition
sample of the present frame, the binary number stored in
thereof
and for producing said subtract control signal
delay line reversible counter 112 is reduced by one unit.
in response to a second stable condition thereof, ?rst
This, in turn, causes the digital to analog converter 114
and second AND gates, means for directly applying the
to apply an incrementally lower analog signal level to 65 output
of said discriminator as a ?rst input to said ?rst
discriminator ‘102 during the next frame. It will be seen
AND gate, an inverter for applying the output of said
that delay line reversible counter 1i12 acts as an integrator
discriminator as a ?rst input to said second AND gate,
in which the ‘binary number is equal to the total number
means for applying clock pulses as a second input to
of added units accumulated minus the total number of
both said ?rst and second AND gates, means for apply
subtracted units accumulated. However, the only infor 70 ing the output of said ?rst AND gate to a ?rst input of
mation appearing on transmission path 116 is either the
said bistable device to switch said bistable device to said
presence of a pulse, manifesting an increase in the signal
?rst stable condition thereog, and means for applying the
level of a time multiplexed analog sample, or the absence
of a pulse, manifesting a decrease in the signal level of a
time multiplexed analog sample.
output of said second AND gate to a second input of
said bistable device to switch said bistable device to said
75 second
stable condition thereof.
3,0913%
5
6
4. The system de?ned in claim 3, wherein said sec
ond means includes means for transmitting the output
of one of said AND gates to said receiving point.
5. The system de?ned in claim 4, wherein said one
of said AND gates is said ?rst AND gate.
6. The system de?ned in claim 1, wherein said third
means includes a delay line reversible counter having
a delay equal to one frame period for adding clock
pulses applied thereto in response to a concurrently ap—
of said ?rst AND gate to a ?rst input of said bistable
device to switch said bistable device to said ?rst stable
subtract control signal, control means having said suc~
cessive output signals applied as an input thereto for
applying an add control signal to said counter in re
sponse to an output signal having said ?rst predeter~
mined value and for applying a subtract control signal
to said counter in response to an output signal having
applied thereto in response to a concurrently applied sub
tract control signal, a discriminator producing a ?xed
condition thereof, and means for applying the output of
said second AND gate to a second input of said bistable
device to switch said bistable device to said second stable
condition thereof.
9. The system de?ned in claim 1, wherein said ?rst
means includes a delay means reversible counter having
a delay equal to one frame period for adding clock
plied add control signal and for subtracting clock pulses 10 ‘pulses applied thereto in response to a concurrently ap
plied add control signal and for subtracting clock pulses
applied thereto in response to a concurrently applied
amplitude output pulse only in response to the level
of a ?rst input applied thereto exceeding the level of
a second input applied thereto, means for applying time
multiplexed samples of analog signals as said ?rst input
to said discriminator, a digital to analog converter
said second predetermined value, and a digital to analog
coupling the output of said counter to said discriminator
converter coupled to the output of said counter for
producing a signal level proportional to the count mani 20 for applying as said second input to said discriminator
a signal level proportional to the count manifested by
fested by the output of said counter.
the output of said counter, and control means coupling
7. The system de?ned in claim 6, wherein an output
said discriminator to said counter for applying an add
signal having said ?rst predetermined value is a pulse
control signal to said counter in response to an output
of ?xed amplitude and an output signal having said
second predetermined value is the absence of a pulse. 25 pulse from said discriminator and for applying a sub
tract control signal to said counter in response to the
8. The system de?ned in claim 7, wherein said control
absence of an output pulse from said discriminator, and
means includes a bistable device for producing said add
control signal in response to a ?rst stable condition there
of and for producing said subtract control signal in re
sponse to a second stable condition thereof, ?rst and 30
second AND gates, means for directly applying said out
put signals as a ?rst input to said ?rst AND gate, an
inverter for applying the output of said discriminator as
a ?rst input to said second AND gate, means for ap
plying clock pulses as a second input to both said ?rst 35
and second AND gates, means for applying the output
wherein said second means includes means for trans
mitting the output of said discriminator to said re
ceiving point.
References Cited in the ?le of this patent
UNITED STATES PATENTS
2,510,054
2,662,113
2,759,998
Alexander et al. _______ __ June 6, 1950
Schouten et al. _______ __ Dec. 8, 1953
lLabin et al. __________ __ Aug. 21, ‘1956
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