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Патент USA US3094639

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J1me 13, 1963
Filed Oct. 30, 1958
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BY vézkaau-é
June 18, 1963
Filed Oct.» :50, 1958
4 Sheets-Sheet 4
United States Patent 0
Edward D. Ostrolf, South Sudhury, Alfred G. Marcotte,
Chelmsford, and Herbert E. Miller, West Acton, Mass,
assignors to Laboratory for Electronics, Inc., Boston,
Mass, in corporation of Delaware
Filed Oct. 30, 1958, Ser. No. 770,832
8 Claims. (Cl. 307-885)
Patented June 18, 1963
of generator 12 consists of pulses of constant width and
amplitude occurring at a. frequency which corresponds
to the pulse rate of input signal fx. The output of gen
erator 12 is applied to averaging circuit 13 wherein the
constant area pulses are integrated and a DC signal is
derived having an amplitude proportional to the afore
Said pulse frequency. This signal may be used directly
to control a D.C.-operated servo, or as stated above, it
may serve as the input of a precision modulated cir
The present invention relates to a rate-to-arnplitude
unit. In the latter case, the DC. signal is applied to
converter, in particular a converter for changing a pulse
chopper 14 which, by the application of an external signal
rate which is representative of a measured quantity to
having a predetermined A.C. frequency, converts the DC.
a DC. signal having an amplitude proportional to the
output signal of the averaging circuit into an AC. car
pulse rate. The invention further embraces means for
rier signal whose amplitude is modulated by the level of
providing a carrier signal having a variable amplitude 15 the aforesaid DC. signal. An isolation stage 15 couples
proportional to the pulse rate and a phase reference pro
?lter 16 to the chopper. Filter 16 is tuned to provide the
portional to the polarity of the pulse rate signal.
In navigational systems, particularly systems of the
type using the Doppler eifect, the navigational data re
ceived is frequently in the form of digital pulse signals
having a pulse rate dependent on the measured quantity.
Generally, the data is incapable of being employed in this
form. Nearly all presently available analog computing
systems which utilize Doppler-measured velocities as in
fundamentalrof the aforesaid predetermined A.C. fre
quency as an output thereof, said output being applied to
ampli?er 17.
The ampli?ed output signal appears at
terminal 18 as an amplitude modulated A.C. carrier
FIGS. 2 and 3 illustrate in schematic form one em
bodiment of the circuitry employed herein, identically
put data to provide correction signals for inertial plat
labeled terminals in the two drawings indicating corre
" spending connections. As will be seen, positive polarity
forms, automatic landing aids, bombing or ?re control,
input signal +f; and negative polarity input signal —f,;
automatic navigators or the like, accept input data in the
form of variable amplitude D.C. signals, or as amplitude
modulated carrier signals. Thus, the accurate solution
are received at the input terminals and are applied to
pulse differencing circuit 21.
input signals -]-,fx
and —fx respectively, have respective input pulse rates
of triangulation problems is readily carried out by a 30 dependent on the quantities being measured, eg. Doppler
servo system employing 400 cycle operated resolvers.
velocities. A: DC. control signal, whose polarity is
Alternatively, D.C. servo-operated cosine systems may
determined by the input signal having the higher rate,
be employed using potentiometers in place of resolvers.
is applied to wire 19 whence it is ampli?ed by a DC.
Whereas in the ?rst mentioned servo system amplitude
ampli?er 28 and is used in a manner explained herein
modulated 400 cycle carrier input signals proportional 35 below. Input signals +13, and —f,, are utilized in pulse
to the pulse rate of respective Doppler-measured velocities
differencing circuit 21 to form a signal fx having a pulse
are required, the D.C. servo system utilizes similarly
rate equal to the magnitude of the diiference of the re
derived input data in ‘the form of DC signals having
spective pulse rates of the original input signals. Signal
an amplitude proportional to the pulse rate.
fx is coupled to the base of a transistor ampli?er stage
Heretofore, complex circuits, which were expensive 40 22, the collector of which is resistively coupled to a
?rst D.C. reference potential 31+, +22 volts having been
said signals. Such circuits frequently employ a binary
used in one embodiment of the invention. The emitter
to build and maintain, were used to obtain the afore
multiplier and a forward-backward counter, intercon
is resistively coupled to a second D.C. reference potential
nected so that a reference frequency applied to the multi
B21‘, +4 volts having been used in the aforesaid embodi
plier will be made equal after multiplication to the input 45 ment of the invention. A synchronizer 23 is coupled
rate fx. Asa result, a parallel binary number in the for
to the output of the aforesaid ampli?cation stage. The
ward-backward counter is obtained which is proportional
synchronizer comprises a core 20 having a substantially
to the input rate 15,. The D.C. levels corresponding to the
square loop hysteresis characteristic which carries a plu
One and Zero states of the forward-backward counter
rality of core windings. A ?rst core winding 24 has one
stages are then used to control a ‘bank of switches in a
terminal thereof rcsistively coupled to the base of a tran
precision ladder network which converts a reference
carrier to a carrier signal having an amplitude propor
sistor 25, the other terminal being resistive-1y coupled
to the aforesaid ?rst reference potential. A second wind
tional to isaidbinary number.
ing 26 has one terminal resistively coupled to said ?rst
Accordingly, it is a primary object of the invention to
reference potential, the other terminal being resistively
provide a simple-rate-to-amplitude converter for supply
coupled to the base of a transistor 27. The emitters
ing an output signal whose amplitude is modulated in
of transistors 25 and 27 respectively, are connected to
accordance with the pulse rate of an incoming input
a third D.C. reference potential B31‘, for example +18
signal. Further objects and advantages will become more
volts, while the corresponding collectors are connected
apparent from the ‘following detailed speci?cation with
to respective terminals of core windings 31 and 32. The
reference to the accompanying drawings in which:
other terminals of the aforesaid core windings are refer
enced to ground. The collector of transistor 22 is diode
FIG. 1 is a block diagram of the invention herein;
FIGS. 2 and 3 illustrate in schematic form one embodi
ment of thecircuitry employed; and
coupled to said ?rst terminal of core winding 24. A clock
pulse generator 33 periodically provides ?rst timing pulses
FIG. 4 shows a modi?cation of the averaging circuit of 65 T1 which are diode coupled to said other terminal of core
winding 26. A ?fth core winding 34 has one terminal
FIGS. 2 and 3.
thereof diode coupled to the base of a transistor 36 in
With reference now to FIG. I, the invention herein
is illustrated in block diagram form. An input signal 1",,
?ip~?op circuit 35 comprising transistors
37 respec
tively. The base of each of said last recited transistors
having a pulse rate which varies in accordance with the
is resistively coupled to a fourth reference potential
measured quantity, is applied to a constant area pulse gen 70
84+, e.g. +44 volts. The other terminal of winding 34
erator which operates by reference against timing signals
is directly connected to B41“. The emitters of transistors
derived from a clock pulse generator. The output signal
36 and 37 are connected together and are coupled resis
tively and capacitively respectively, to said fourth refer
ence potential. The collector of transistor 36 is coupled
to the base of transistor 37 by means of parallel resistor
capacitor combination 41, while the collector of transis
tor 37 is coupled to the base of transistor 36 by means
of a parallel resistor capacitor combination 42. Both
collectors are additionally coupled to the aforesaid ?rst
reference potential B1". The base of transistor 37 is
diode coupled through a condenser to the aforesaid clock
pulses, upon being amplitude limited by the operation of
clipping circuit 45, result in constant area pulses. As
such, they are integrated by the RC combination 46 to
provide a DC. signal. The latter has an amplitude which
varies in accordance with the frequency of the aforesaid
constant area pulses. As previously mentioned, the signal
may be used in this form to control a D.C. operated
servo. Alternatively, a 400 cycle excitation is applied
to relay 51 which, in turn, is actuated by the control
pulse generator 33, to receive periodically occurring sec 10 signal on Wire 19. As a result, the DC. signal at the out
put of the integrator is chopped such that an A.C. car
ond timing pulses T2. Each of said last recited pulses
rier signal having an amplitude proportional to the level
occurs a ?xed time interval after the corresponding ?rst
of the aforesaid DC. signal appears at the base of the
timing pulse T1. The output of ?ip-?op circuit 35 is resis
transistor comprising isolation stage 53. This signal is
tor coupled to the base of a transistor 44 (FIG. 3), the
emitter of which is connected to the aforesaid ?rst D.C.
reference potential B1+, while its base is resistor coupled
applied to ?lter 54 which is tuned to the fundamental fre
quency fc, to obtain a signal which is free from harmonics.
The latter is applied to output ampli?er 55, whence it
to a source of negative DC. potential Bf, e.g. —44
appears at output terminal 56 as an amplitude modulated
volts. Transistor 44 forms part of a clipping circuit 45
carrier frequency signal.
which further comprises a resistor 48 coupling the emit
Inasmuch as the characteristic of averaging circuit 46
ter to a pair of Zener diodes 38 and 39. The latter have 20
is non-linear above a certain output voltage level, its
a reverse break-down voltage which is stable and a
operation is con?ned to output voltages which are small
dynamic resistance which is very low after breakdown
compared to the reference voltage. For improved linear
compared to that of resistor 48. The series diode com
ity over a wide dynamic range the averaging circuit may
bination is shunted by a resistor 40 and is connected to
ground. Averaging circuit 46 comprises an RC integrator 25 be modi?ed as shown in FIG. 4, applicable reference
numbers having been retained. A capacitor 61 which is
consisting of a series resistor 49 having one terminal cou
large compared to averaging capactor 50 is inserted in
pled to clipping circuit 45 and the other terminal con
series with resistor 49. An emitter follower 63 has its
nected to a capacitor 50 which is, in turn, connected to
base connected to capacitor 50, while the emitter and
ground. The aforesaid other terminal is further coupled
to a chopper 47 which comprises a diode bridge circuit 48 30 collector are respectively coupled to the aforesaid D.C.
sources B1_ and 81+. A diode 62 further couples the
having one node thereof resistively coupled to the afore
emitter to capacitor 61. The emitter follower is em
said averaging circuit and having the opposite node con
ployed to charge capacitor 50 to a voltage equal to that
nected to ground. The other pair of nodes is connected
across capacitor 61. This arrangement permits the linear
to the contact of a relay 51. The latter is actuated from
pulse di?erencing circuit 21 and is operative to apply 35 charging action of capacitor 61 to a voltage that may be
many times that of the reference voltage of Zener diodes
a predetermined A.C. frequency f0 to the DC. output
38, 39 which determine the amplitude of the input pulse.
of the averaging circuit. In one embodiment, a 400 cycle
The circuit further insures that the charging current per
source was used to provide the aforesaid A.C. frequency.
The chopper output capacitively coupled to the transistor
pulse is independent of the voltage across capacitor 61,
sistor 25 as well as to winding 24 of core 20. The latter
accordingly. In certain applications, the ?ltering func
base of an isolation stage 53 whose emitter and collector 40 it being proportional to the difference, otherwise, be
tween the reference voltage and the voltage across capaci
are respectively coupled to the aforementioned D.C.
tor 50.
sources B1- and B21“. The emitter, in turn, is coupled
Having thus described the invention, is will be ap
to a ?lter 54 which is tuned to the ‘fundamental of fre
parent that numerous modi?cations and departures may
qeuncy fc. The ?lter comprises a parallel LC combina
tion which is capacitively coupled to ground, as well 45 now be made by those skilled in the art. Such modi?ca
tions include the use of the linearizing circuit discussed
as a parallel RC combination coupled to the aforesaid
in connection with FIG. 4. Similarly, the Zener diode
second reference potential Bz'l'. The output of the ?lter
arrangement could be replaced by a clamping diode ref
is connected to an ampli?er 55, whence it is ampli?ed
erenced to a stable power supply. Additionally, the
and applied to output terminal 56.
In operation, pulse signal fx, having an input pulse rate 50 A.C. frequency which determines the carrier frequency
can vary from DC. to megacycle frequencies depending
equal to the magnitude of the difference of the pulse rates
on the output requirements. In the latter case it must
of -|-)‘x and —f,,, is ampli?ed by the circuit which includes
be borne in mind, however, that the ?lter must be changed
transistor 22, whence it is applied to the base of tran
has a substantially square loop hysteresis characteristic 55 tion can be carried out by the servo controlled by the
output signal. In such cases ?lter 55 can be dispensed
and is set regeneratively due to the phasing of the core
with entirely. The invention may be further modi?ed
windings by each arriving pulse of signal f,,. A subse
by substituting a mechanical chopper for its electronic
quently arriving ?rst timing pulse T1 is applied to core
equivalent. Similarly, various embodiments of the pulse
winding 26 and resets core 20, provided the latter is in
differencing circuit are feasible. Where a very narrow
the set state. Upon resetting, an output pulse is derived
constant pulse width is required, the present constant
which is applied to the base of transistor 36 to place the
pulse width circuit could be readily replaced with a mag
latter in a conductive state. Owing to the connection
netic core blocking oscillator. Similar modi?cations, too
of the base and collector of the transistor 36 to the col
numerous to describe, are feasible. Consequently, the
lector and base respectively of transistor 37, the latter
transistor, which is normally conductive, is rendered non 65 invention herein disclosed is to be construed as limited
only by the spirit and scope of the appended claims.
conductive upon the application of a pulse to transistor
What is claimed is:
36. A subsequently arriving timing pulse T2, which oc
curs a predetermined time interval after the occurrence
1. In a rate-to-amplitude converter, a constant area
pulse generator comprising a synchronizer, means for
while transistor 36 ceases to conduct. As a result, the 70 applying an input signal having an input pulse rate to
said synchronizer, said synchronizer being adapted to be
output signal of ?ip-?op 35, which is applied to the base
set by said input pulses, means for periodically applying
of transistor 44, consists of pulses having a ?xed width,
?rst timing pulses to said synchronizer, said synchronizer
each of said pulses being initated by the occurrence of a
in its set state being adapted to be reset by said timing
timing pulse T1 and being terminated by the occurrence of
the corresponding timing pulse T2. These ?xed width 75 pulses to provide output pulses, a ?ip ?op circuit, means
of timing pulse T1, renders transistor 37 conductive again,
coupling said output pulses to said ?ip-?op circuit to
cause said ?ip-flop circuit to be set by said output pulses,
means for periodically applying second timing pulses to
said ?ip-?op circuit, each of said second timing pulses
occurring a predetermined time period after the corre
sponding ?rst timing pulse, said ?ip-?op circuit being
adapted to be reset by said second timing pulses to pro
vide constant width output pulses, means for amplitude
limiting said last recited pulses to provide a constant area
pulse signal, an averaging circuit, and means for apply
ing said last recited signal to said averaging circuit to
provide a direct current signal varying as a function of
the input rate.
2. The apparatus of claim 1 and further comprising a
chopper adapted to apply a predetermined frequency to
said direct current signal to obtain an amplitude modu~
lated carrier signal, a ?lter, and means for applying said
carrier signal to said ?lter to obtain the frequency funda
second transistors, and a ?fth core winding coupled to
said ?ip-?op circuit.
5. The apparatus of claim 4 wherein said ?ip ?op cir
cuit comprises a pair of transistors having respective
emitters thereof connected together, each transistor col
lector being coupled to the base of the opposite tran
sistor of said pair, said ?fth core winding being coupled
to the base of one transistor of said pair, said second
timing signal being coupled to the base of the other tran
sistor of said pair.
6. The apparatus of claim 3 wherein said amplitude
limiting circuit comprises a transistor having its base
coupled to said ?ip ?op circuit, a series diode combina
tion having one terminal resistively coupled to the col
15 l-ector of said transistor, said diode combination being
shunted by a resistor and having the other terminal con
nected to ground.
7. The apparatus of claim 3 wherein said averaging
circuit comprises a series resistance having one terminal
mental thereof as an output.
3. In a rate-to-amplitude converter, a synchronizer, 20 connected to said amplitude limiting circuit, and an
averaging capacitor connected between the other resistor
means ‘for applying a data signal having a data~dependent
terminal and ground.
pulse rate to said synchronizer, means for periodically
8. The apparatus of claim 7 and further comprising a
applying ?rst timing pulses to the output portion of said
series capacitor connected intermediate said limiting cir
synchronizer, a ?ip-?op circuit connected to said syn
chronizer, means for periodically applying second timing 25 cuit and said series resistance, said series capacitor being
large compared to said averaging capacitor, and an
pulses to said ?ip-?op circuit, each of said second tim
emitter follower having its base connected to the junc
ing pulses occurring a predetermined time period after the
tion of said series resistance and said averaging capacitor
corresponding ?rst timing pulse, an amplitude limiting
and having its emitter coupled by a diode to the junction
circuit connected to said ?ip‘?op circuit, and an averaging
30 of said series resistance and said series capacitor.
circuit connected to said amplitude limiting circuit.
4. The apparatus of claim 3 wherein said synchronizer
References Cited in the ?le of this patent
comprises a magnetic core having a square loop char
acteristic, ?rst and second transistors having respective
emitters tied together, said data signal being coupled to
Friedman ____________ __ July 13, 1954
the base of said ?rst transistor, said ?rst timing pulses 35 2,867,767
McGillem ____________ __ Ian. 6, 1959
being coupled to the base of said second transistor, ?rst
Barker _____________ __ Mar. 17, 1959
and second core windings coupled to the base of respec
tive ?rst and second transistors, third and fourth core
windings coupled to the collect-or of respective ?rst and
Vetter _______________ __ Apr. 7, 1959
Hansen ______________ __ May 5, 1959
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