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Integration of ferroelectric thin films in microwave devices

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Abstract
LAM, PETER GAIFUN. Integration of Ferroelectric Thin Films in Tunable Microwave
Devices. (Under the direction of Jon-Paul Maria).
Recent growth in wireless communication industry has led to a growing search
for alternative technologies that can provide higher flexibility and efficiency in the
handling of radio frequency spectrum, and preferably at a similar or lower cost than the
present technologies. Thin film barium strontium titanate has shown great promises for
microwave applications. There are two goals in this thesis: 1) To show a methodology
for integration of BST thin films in microwave devices operating at frequencies above 6
GHz, and 2) To explore the limits of material optimization for increased device
performance.
The integration of BST thin film with a 3rd order combline-based bandpass filter in
the frequency range of 6 to 18 GHz was demonstrated. Alumina substrates with filled
vias were used to support the devices. Optimized (Ba0.7Sr0.3)TiO3 film was deposited
and patterned in alumina substrate. Planar gap capacitors were patterned with a Cr/Au
metal stack while the rest of the device layout was patterned with silver metal and
electroplated with copper. The measured microwave characteristics of the bandpass
filters fall within the specifications of the design but more improvements were needed to
lower the insertion loss and the frequency tunability for devices operating at frequency
above 12 GHz.
The metallization impact on the microwave devices was studied. Two variables
were tested with electroplated copper: 1) Thickness, and 2) geometry with respect to the
gap. Increasing the thickness of the copper decreases the insertion loss of the device.
Metal thickness beyond three skin depths does not impart significant improvement.
Plating distances to the edge of the gap in the capacitor has not effect in the insertion
loss of the filter.
Tunability limit of coplanar gap capacitors was investigated. A series of gap
capacitors with different geometry were tested. In the limit of low capacitance values, a
fringe capacitance is observed, which measured to be in the range of 50-100 fF. The
non-tunable capacitance contributes to the low tunability of the 12-18 GHz range
bandpass filter, where the required capacitance values for impedance matching, 200400 fF, are close to the values of the fringe. A coplanar MIM capacitor structure is
proposed to improve the tunability values. The configuration consists of a sapphire
substrate, followed by the metal coplanar electrodes (Pt/Ti stack deposited by e-beam
evaporation) and then capped with the BST layer.
Tunability values of 50% were
obtained with an electric field of 125 KV/cm for an interdigitated coplanar MIM capacitor.
Integration of Ferroelectric Thin Films in Microwave Devices
by
Peter Gaifun Lam
A dissertation submitted to the Graduate Faculty of
North Carolina State University
in partial fulfillment of the
requirements for the Degree
of Doctor of Philosophy
Materials Science and Engineering
Raleigh, North Carolina
2010
APPROVED BY:
Michael B. Steer
Douglas Irving
Ramon Collazo
Jayesh Nath
Jon-Paul Maria
Chair of Advisory Committee
UMI Number: 3425991
All rights reserved
INFORMATION TO ALL USERS
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In the unlikely event that the author did not send a complete manuscript
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a note will indicate the deletion.
UMI 3425991
Copyright 2010 by ProQuest LLC.
All rights reserved. This edition of the work is protected against
unauthorized copying under Title 17, United States Code.
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ii
DEDICATION
献给我敬爱的父母并小妹妹
To my beloved parents and sister
iii
BIOGRAPHY
Peter Gaifun Lam was born on November 13, 1983 to parents Kwong and Shuyi
Lam in the little town of Cumana, Venezuela. He survived the trials and tribulations of
being the only Asian kid living in a poor neighborhood. Three days after the high school
commencement, his parents sent him with a one way ticket to Greensboro, NC. At the
young age of 16 and with one suitcase in hand, Peter started his new life with the
guidance of family friends, Jeanette and Richard Jou. After spending his first 4 months
learning the intricacies of the English Language, he enrolled at the Guildford Community
Technical College. After three semesters, he transferred to North Carolina State
University and enrolled in the Chemical Engineering program with aspiration for a double
major in Materials Science and engineering. In addition to the rigor of college life, he
spent a semester working in Dr. Lindsey’s lab, learning to synthesize organic molecules.
In the following semesters he continued his undergraduate research with Dr. Spontak,
working with polymers. Due to unexpected circumstances, he was three classes short of
graduating with a double major in 2005. Following his graduation he decided to continue
to pursue a doctorate degree in Materials Science and Engineering under the tutelage of
Dr. Jon-Paul Maria and Angus Kingon, working on ferroelectric thin films for microwave
devices. Peter received his Doctor of Philosophy in May 2010 from North Carolina State
University and accepted a one-year post doc position with Dr. Jon-Paul Maria.
iv
ACKNOWLEDGEMENTS
First and foremost, I would like to thank my adviser and friend Professor JonPaul Maria for providing me the opportunity to grow as a scientist. I am truly grateful for
his support and guidance during the course of my graduate career. I am thankful for his
patience and perseverance to teach me the intricacies of being a good researcher. I
would also like to thank the members of the committee, Professor Michael Steer,
Professor Douglas Irving, and Professor Ramon Collazo, for their valuables inputs and
feedbacks on my research.
None of my accomplishments would have been possible without the help and
support of my colleagues. I consider myself very lucky to have worked and collaborated
with a great group of people including Jon Ihlefeld, Brian Laughlin, Mark Losego,
Spalding Craft, Seymen Aygün, Dipankar Ghosh, Jayesh Nath, Hasan Akyıldız, Anthony
Rice, James Tweedie, David Hook, Your-mom-think-she-is-the-smartest Paisley,
Michelle Casper, Patrick Daniels, Jess Jur, Jim Kupferschmidt, Erin Gross, Wael
Fathelbab Vrinda Haridassan and Zhiping Feng. I am also thankful for the assistance
provided by Joe Matthews, the AIF group, Dan Lichtenwalner, Aaron Johnston-Peck,
and the MSE staff.
I am grateful of all my friends for making grad school so much better. I am
especially thankful of Jeanette and Richard Jou for providing me a home away from
home and Jason Jou for being my big brother.
Last but not least, I am grateful for my dad, my mom, and my sister. They are my
inspiration to be the best I can be. I thank my dad for all his little phone calls; I thank my
mom for being the glue that keeps all of us together despite the large distances that
separate us, and I thank my sister for her patience on my promise, I will take care of you
after I get a job.
v
TABLE OF CONTENTS
List of Tables………………………………………………………………………....viii
List of Figures………………………………………………………………………....ix
Chapter 1
Introduction ................................................................................... 1
1.1
Motivation ............................................................................................... 1
1.2
Frequency Agile Technologies ............................................................... 2
1.3
Research Objective ................................................................................ 4
Chapter 2
Ferroelectricity .............................................................................. 7
2.1
Review of Dielectric Properties of Solids ................................................ 7
2.2
Introduction to Ferroelectricity .............................................................. 14
2.3
2.4
2.2.1
Historical Background ........................................................... 14
2.2.2
Crystal Structure Consideration............................................. 16
2.2.3
Phase Transitions in Ferroelectrics ....................................... 20
Paraelectric Phase ............................................................................... 25
2.3.1
Dielectric Permittivity ............................................................. 27
2.3.2
Tunability ............................................................................... 28
2.3.3
Dielectric Loss ....................................................................... 29
Conclusions .......................................................................................... 33
Chapter 3
3.1
Ferroelectric Integration for Microwave Application ................ 35
Introduction to Barium Strontium Titanate (BST) Thin films .................. 35
3.1.1
Ferroelectric Metal Interfacial Layer ...................................... 35
3.1.2
Stress-Strain Effects.............................................................. 38
3.1.3
Thin Film Deposition Techniques: Sputtering ........................ 41
3.2
Capacitor Configuration: Parallel vs. Coplanar ..................................... 45
3.3
Substrate and Metallization for Varactors ............................................. 46
3.4
Conclusions .......................................................................................... 53
Chapter 4
Experimental Procedure ............................................................. 54
vi
4.1
Barium Strontium Titanate Processing ................................................. 54
4.2
Physical Characterization – BST Test Capacitors ................................ 58
4.3
Photolithography and Liftoff – BST Test Capacitors ............................. 60
4.4
Electrical Characterization – BST Test Capacitors ............................... 63
4.5
Characterization ................................................................................... 68
4.6
Conclusions .......................................................................................... 70
Chapter 5
Bandpass Filter Integration ........................................................ 71
5.1
Tunable Microwave Devices based on BST Thin Films ........................ 71
5.2
Bandpass Filter Array ........................................................................... 73
5.3
Device Integration ................................................................................. 74
5.3.1
Substrate ............................................................................... 75
5.3.2
BST Deposition and Patterning ............................................. 76
5.3.3
Metallization .......................................................................... 77
5.4
Bandpass Filter Results ........................................................................ 87
5.5
Conclusions .......................................................................................... 92
Chapter 6
The Impact of Metallization Thickness and Geometry for X-
band Tunable Microwave Filters..................................................................... 93
6.1
Abstract ................................................................................................ 93
6.2
Introduction ........................................................................................... 94
6.3
Experimental Procedure ....................................................................... 96
6.4
Metal Thickness Effect.......................................................................... 98
6.5
Plating Width Effect ............................................................................ 101
6.6
Conclusions ........................................................................................ 103
Chapter 7
Scaling Issues in Ferroelectric Planar Capacitors ................. 104
7.1
Abstract .............................................................................................. 104
7.2
Introduction ......................................................................................... 105
7.3
Experimental Procedure ..................................................................... 108
7.4
Results and Discussion ...................................................................... 111
vii
7.5
Conclusions ........................................................................................ 117
Chapter 8
Inverted Coplanar Capacitor .................................................... 118
8.1
Abstract .............................................................................................. 118
8.2
Introduction ......................................................................................... 119
8.3
Experimental Procedure ..................................................................... 123
8.4
Results and Discussion ...................................................................... 126
8.5
8.4.1
Platinum Annealing ............................................................. 126
8.4.2
BST Growth ......................................................................... 128
8.4.3
Dielectric Properties of Epitaxial BST .................................. 131
8.4.4
Inverted Planar Capacitor Synthesis ................................... 135
Conclusions ........................................................................................ 140
Chapter 9
Conclusions and Future Work.................................................. 142
9.1
Conclusions ........................................................................................ 142
9.2
Future Work ........................................................................................ 143
References……………………...…………………………………...…………........145
viii
LIST OF TABLES
Table 1-1 COMPARISON BETWEEN DIFFERENT TECHNOLOGIES FOR AGILE DEVICES
[5]..................................................................................................................................... 4
Table 3-1 LATTICE PARAMETERS FOR BST AND TYPICALLY USED SINGLE CRYSTAL
SUBSTRATES AT ROOM TEMPERATURE WITH THEIR RESPECTIVE LATTICE
PARAMETERS AND THERMAL EXPANSION COEFFICIENTS [107,120122,114,123]. ..................................................................................................................45
Table 3-2 METAL RESISTIVITIES [137] .........................................................................................49
Table 3-3 STANDARD REDUCTION POTENTIALS OF METALS. .................................................51
Table 4-1 OPTIMIZED SPUTTER DEPOSITION CONDITIONS. ...................................................56
Table 4-2 LIST OF CHARACTERIZATION TOOLS USED AND TEST PERFORMED. ..................69
Table 5-1 CONDITIONS USED FOR SPUTTER DEPOSITION OF SILVER FILM. ........................82
Table 5-2 MICROWAVE RESULTS FOR TILE A FILTER ARRAY. ................................................89
Table 5-3 MICROWAVE RESULTS FOR TILE B FILTER ARRAY. ................................................89
Table 8-1THERMAL EXPANSION COEFFICIENTS OF SUBSTRATE AND THIN FILM
MATERIALS. ................................................................................................................132
ix
LIST OF FIGURES
Figure 1.1 Schematic of the radio frequency spectrum [1]. .............................................................. 1
Figure 2.1 Schematic of a dielectric sandwiched between two metal electrodes under an
electric bias E. The polarization, P, indicates the direction of the dipoles, and Q
represents the amount of charge accumulated at each electrode.................................... 7
Figure 2.2 Real and complex permittivities contribution from different polarization mechanisms
as a function of frequency. ..............................................................................................10
Figure 2.3 Polarization mechanisms: a) Electronic, b) Ionic, c) Dipolar or Orientational d)
Space charge and Interfacial. .........................................................................................12
Figure 2.4 Classification of ferroelectric material according to crystal symmetry [31].....................17
Figure 2.5 Perovskite structure for barium titanate..........................................................................18
Figure 2.6 Crystal structure of perovskite for tolerance factor: a) Cubic, t =1, b) Tetragonal, t >
1......................................................................................................................................19
Figure 2.7 Relative dielectric constants for a single BaTiO3 crystal for the a-axis and c-axis as
a function of temperature. Taken from Merz [35]. ...........................................................21
Figure 2.8 Simulation of typical polarization-temperature plots for: a) Second-order transition,
and b) First-order transition.............................................................................................25
Figure 2.9 Polarization vs. Electric Field plots for: a) A ferroelectric phase, and b) a paraelectric
phase. .............................................................................................................................26
Figure 2.10 Off-scale plot of the frequency dependence of the mechanism of intrinsic loss for
paraelectric materials where: (1) corresponds to the three-quantum, (2) the fourquantum, and (3) the quasi-Debye mechanisms contributions to the loss tangent, tan
δ. Ωo and Γ0 are the soft mode frequency and the damping (Taken from Tagantsev
et al. [53]). .......................................................................................................................32
Figure 2.11 Curie temperature dependence on the concentration of Ba. (Taken from Tagantsev
et al. [8] which is a modified version from Smolenskii's data [56]). .................................33
Figure 3.1 Schematic for a capacitor with a reduced permittivity layer ............................................36
x
Figure 3.2 Simulated behavior of the effective permittivity as a function of the film thickness [5]....37
Figure 3.3 Schematic of a sputtering system. .................................................................................42
Figure 3.4 Schematic for parallel and coplanar capacitor configurations. .......................................45
Figure 3.5 Relative cost of different substrates [5]. .........................................................................48
Figure 3.6 Skin depth for various metals as a function of frequency. ..............................................50
Figure 3.7 SEM micrographs of a before and after the application of a bias in a gap capacitor
on alumina substrate.......................................................................................................52
Figure 4.1 AFM scan of alumina purchased from Coorstek. ...........................................................54
Figure 4.2 Schematic of the BST sputtering system .......................................................................57
Figure 4.3 Schematic of the furnace used for annealing BST thin films. .........................................58
Figure 4.4 X-Ray plot for an alumina substrate and an annealed BST film deposited in alumina
substrate. The asterisks indicate the peaks belonging to the alumina substrate............59
Figure 4.5 AFM scan of a typical BST thin film in alumina. .............................................................60
Figure 4.6 Schematic for resist profile obtained for a) positive and b) negative photoresist,
before and after metallization. The straight sidewall profile can result in uneven
metal removal, while the overhanging profile allows for clean metal break after liftoff. ...61
Figure 4.7 Process for negative photolithography. 1. The sample is cleaned with acetone and
methanol, 2. a coat of photoresist is spun on the sample and cured for 2 mins at 90
°C, 3. the sample is exposed for 1.5 secs in the aligner with the mask, 4. the sample
is cured again at 115 °C for 90 secs followed by 5. a flood exposure for 90 secs and
6. finally the sample is developed. ..................................................................................62
Figure 4.8 Capacitor configuration used for electrical measurements. There are a total of 40
fingers. Each finger has a length of 200 mm and width of 20 mm. The gap between
fingers is 3 mm. ..............................................................................................................64
Figure 4.9 Typical leakage current measurement for an IDC. .........................................................65
Figure 4.10 C-F plot for an IDC measured from 100 KHz to 1 MHz and zero bias. .........................67
Figure 4.11 C-V plot for an IDC, measured at 1 MHz from –35 V to 35 V. The voltage was
modified to display the electric field instead. ...................................................................67
xi
Figure 4.12 C-V plot for an IDC measured from –173°C to 237°C at zero bias. .............................68
Figure 5.1 Schematic of a third order combline bandpass filter.......................................................72
Figure 5.2 Schematic of filter array. Each tile contains two elements. Each element addresses
a specific frequency range. .............................................................................................74
Figure 5.3 Schematic for a tile. The tile includes two bandpass filters, band 1 and 2. Groundsignal-ground structures were used to measure and characterize the performance of
the filter. Three BST gap capacitors are located at the top of the resonator lanes..........74
Figure 5.4 Optical pictures of a via after spinning photoresist for: A. hollow via, and B. filled via....76
Figure 5.5 Profilometer 3D mapping of the surface of the via: a. as received, and b. after
annealing in air at 900°C for 20 hours. ...........................................................................77
Figure 5.6 Cross section of the metal stack across a resonator line. ..............................................77
Figure 5.7 Schematic of the metallization process for a bandpass filter. The first metallization
step was done for the resonator lines, the biasing lines, the testing structures and
the signal structures. The second step was the metallization for the gap capacitors
and finally the third step was the copper plating of the whole device. .............................78
Figure 5.8 Plot of resistivity vs. deposition pressure for as deposited silver thin film. The
adhesion test consisted on whether the film would peel off under a simple peeling
test with a Scotch tape (3M, Maplewood, MN). ...............................................................79
Figure 5.9 AFM scans for silver thin films deposited at 5 and 20 mTorr. .........................................79
Figure 5.10 Plot of resistivity vs. annealing temperature in air for silver thin film. ...........................80
Figure 5.11 AFM scans of silver thin films annealed at different temperatures. ..............................81
Figure 5.12 Schematic of the dual magnetron sputtering system....................................................83
Figure 5.13 AFM scan for a gold thin film. .......................................................................................84
Figure 5.14 Schematic of the gap capacitor on top of each resonator line. The capacitance
value of the varactor depends on the width of the gap, W, and length of the
electrode, L, of the gap. ..................................................................................................85
Figure 5.15 Optical picture of a gap with gap width measurements. ...............................................85
Figure 5.16 Schematic of the electroplating setup. .........................................................................86
xii
Figure 5.17 Picture of a finished and ready for use Tile A with bandpass filters 1 and 2.................87
Figure 5.18 Typical plot for insertion loss as a function of frequency for a tunable bandpass
filter. ................................................................................................................................88
Figure 5.19 Quality factor contribution from substrate, metal and dielectric as function of the
frequency. .......................................................................................................................91
Figure 6.1 NCSU filter chip schematic showing the two-step metallization layer strategy. Gray
regions correspond to metallization in step one, black regions correspond to
metallization during step two, while dashed circles correspond to metal-filled vias. .......97
Figure 6.2 A cross sectional illustration of a double gap capacitor showing the thicknessdependent electrode experiment. Note that for visual clarity, the vertical and
horizontal scales are different but thicknesses and distances are given for the
pertinent components. ....................................................................................................99
Figure 6.3 The dependence of insertion loss (1/|S21|^2) on metallization thickness for an 8
GHz center frequency bandpass filter. ..........................................................................100
Figure 6.4 Schematic illustration showing the variation in unplated transmission line distance in
the 8 GHz filter. Note that for visual clarity, the vertical and horizontal scales are
different but thicknesses and distances are given for the pertinent components. .........101
Figure 6.5 The effect of unplated transmission line distance on the insertion loss of a bandpass
filter with an 8 GHz center frequency. This plot incorporates data for 4 filters. In the
unplated state, the geometry of the Ag metallization is identical for all devices ............102
Figure 7.1 Calculated capacitance as a function of frequency for 50 Ω impedance matching
assuming a 45 nH inductance. This inductance value is chosen as it represents that
associated with the third order X-band combline filters prepared during this work........106
Figure 7.2 Schematic of the electric field from the side view and top view. ...................................107
Figure 7.3 X-ray diffraction pattern for a BST thin film prepared on ceramic alumina substrate
after an air anneal at 900 °C for 20 hours. Only peaks from the alumina and BST are
present and the intensity ratios indicate random orientation. ........................................109
xiii
Figure 7.4 Voltage dependence of capacitance and loss tangent for a BST gap capacitor with a
2000 µm long gap.........................................................................................................111
Figure 7.5 Capacitance vs. gap width for planar gap capacitors prepared on BST. Data is
shown for zero volts and 35 volts dc bias applied (corresponding to the non- and
fully-tuned capacitor conditions). The b vales correspond to the y-intercepts, thus the
fringe+ stray capacitance associated with the samples and the measurement fixture. .112
Figure 7.6 Capacitance tunability for gap capacitors as a function of gap length. Data sets for
2, 3, and 5 µm gaps are shown simultaneously. Each data point corresponds to an
average calculated from 6 capacitors. In some cases, data points are missing; this
corresponds to sizes for which the complete sets of functional capacitors were not
available. In all cases, tunability numbers are quoted for 35V applied, thus larger
values are reported for small gap widths. .....................................................................114
Figure 7.7 Calculated capacitance values for 3 µm wide gap capacitors as a function of gap
length. Calculations were made using SONNET circuit simulator. ................................115
Figure 7.8 Capacitance and tunability at 35V applied of a 2 µm gap capacitor as a function of
length between 50 µm and 500 µm. .............................................................................116
Figure 8.1 Schematic to-scale illustration of a 150 fF gap capacitor similar in design to those
found in the tunable filters of Lam et al. ........................................................................120
Figure 8.2 Schematic comparison of a conventional vs. inverted planar capacitor. ......................121
Figure 8.3 Process flow for the liftoff of Pt/Ti stack using a silver hard mask. 1. First a blanket
of silver in sputtered on top of the substrate, 2. followed by the patterning of the
silver by photolithography and 3-4. liftoff 5. then the Pt/Ti stack is deposited and
patterned 6. Using a commercial etching solution CR-7purchased from Cyantek
(Fremont, CA). ..............................................................................................................125
Figure 8.4 AFM images of Pt/Ti stacks prepared on miscut c-plane sapphire after deposition
and exposure to increasingly high temperatures. Though some hillocking is
observed at 800 °C, the bulk of the electrode remains stable and is provides the
thermomechanical stability needed for pMIM structures. The scale bar, to the right,
xiv
represents 40 nm for the as deposited Pt, 26 nm for the Pt annealed at 500 °C, and
70 nm for the Pt annealed at 800 °C. ...........................................................................127
Figure 8.5 X-ray diffraction analysis of Pt electrodes as deposited and after exposure to 800
°C. Relative peak intensity and orientation are constant. .............................................128
Figure 8.6 X-ray diffraction analysis for BST films grown on bare sapphire. The set of data
illustrates that epitaxial material grows initially at 600 °C, but temperatures between
700 °C and 750 °C are needed to eliminate all non-epitaxial orientations. ...................129
Figure 8.7 SEM image of 200 nm and 800 nm thick 111-oriented BST epitaxial film on
sapphire. The impact of substrate steps is reflected in the surface microstructure at
200 nm, but completely randomized at 800 nm. ...........................................................130
Figure 8.8 X-ray diffraction analysis for epitaxial BST films spanning a thickness range
between 100 and 1200 nm. ..........................................................................................131
Figure 8.9 Optical microscope images of epitaxial BST thin film surfaces collected as a function
of film thickness. The onset of crack formation occurs between 200 nm and 300 nm. .132
Figure 8.10 Thickness dependence of capacitance and tunability for planar epitaxial BST
capacitors. ....................................................................................................................133
Figure 8.11 Temperature dependence of the capacitance for the thickness series of epitaxial
BST thin films prepared on sapphire substrates. ..........................................................135
Figure 8.12 Capacitance vs. voltage for conventional interdigitated and inverted interdigitated
capacitors. The plots show total and relative capacitance for both geometries. ...........136
Figure 8.13 Cross sectional TEM image of inverted planar capacitor. ..........................................137
Figure 8.14 Selected area diffraction image and pattern for the BST and sapphire substrate.
Indexing the diffraction pattern shown in the upper left indicates epitaxial registration
with sapphire substrate, however, there is substantial mosaic spread..........................138
Figure 8.15 Medium resolution TEM image of the interdigitated electrode edge. The partial
consumption of the sapphire substrate is apparent at this magnification. .....................139
Figure 8.16 High-resolution image of the BST sapphire interface. The presence of precipitate
particles at the reactive interface is apparent................................................................139
1
Chapter 1 Introduction
1.1
Motivation
Radio waves (10kHz to ~ 100 kHz) are a subset of the full electromagnetic radiation
spectrum. This range of frequencies has the advantage of being able to penetrate walls and
non-metallic objects and can be transmitted and received by antennae, which make them
useful for communication, broadcasting, navigation and defense purposes. With the recent
“explosion” of wireless applications, the frequency channels have become crowded by the
applications shown in fig.1.1. Governmental regulations typically guide the allocation of the
spectrum, so a frequency range that may be dedicated to broadcasting in one country may
not be necessarily the same in another country [1]. This creates multiple wireless systems
and standards that are exclusive to specific applied frequency ranges and applications.
Figure 1.1 Schematic of the radio frequency spectrum [1].
From the economic point of view the ideal solution is to find a unifying alternative
rather than remaking or modifying the whole infrastructure for every new application or
standard. Traditionally, the task of handling multiple standards and frequency bands has
been achieved by introducing software modifications and/or adding more hardware
2
components. The latter solution is clearly an inefficient one, since the device size finite and
the addition of more components leads invariably to larger power consumption [2],[3]. An
obvious approach to this problem is to consider agile technologies. Such technologies can
operate at multiple frequencies, and thus minimize device size and complexity. This would
also enable higher power efficiency by reducing the number of components on the board.
The next section will outline the different available technologies to achieve agile devices.
1.2
Frequency Agile Technologies
Frequency-selective application is one of the areas where agile solutions can provide
the greatest benefits in terms of adaptability and system miniaturization. The foundation of
the frequency agility lies in the inherent dependence of the resonant frequency on the basic
elements of a circuit’s inductance and capacitance as shown in the following equation:
fo =
1
Equation (1.2.1)
2π LC
where L is the inductance and C is the capacitance. Tunable capacitors have been
extensively used in RF circuits to achieve agile devices [4]. There are different technologies
that can achieve tunable capacitors and each one of them has their pros and cons. A
summary of the main technologies available at the present moment is discussed below [5]:
•
MEMs: MEMs are miniature versions of mechanical switches fabricated at micron
size ranges. These devices offer very low loss and high tuning speeds. However the
fabrication and packaging of MEMs are complex and device reliability remains an issue.
•
Magnetic: capacitance tuning in magnetic-based devices is based on the external
magnetic field induced resonance. Devices based on ferromagnetic materials typically
exhibit very low loss, high selectivity and large tuning ranges. The main drawback of this
technology is the slow tuning speed compared to the other technologies.
•
Semiconductor: tunability in a semiconductor-based varactor is achieved by the
change in the depletion width when a reverse bias is applied to a PN junction. This
technology offers the most cost effective solution for commercial applications, and in terms
3
of performance it easily bests the competition. For frequencies up to 1 GHz, the
semiconductor based varactor represents the state-of-the-art technology used for tuning
microwave devices. However for frequencies above 10 GHz the loss tends to degrade
drastically. Additionally, for large arrays of semiconductor-based devices the power
consumption and heat dissipation become a liability especially in a dense board.
•
Liquid crystal and optical: Both of these technologies have been tested for potential
microwave application. The research of these two technologies for microwave devices is
still in the infant stage.
•
Ferroelectric: the principle of ferroelectric-based varactor is based on the electric
field dependent permittivity. Devices based of ferroelectric varactors typically offer high
tuning speed, very small power consumption and lower loss compared to semiconductorbased varactors at frequencies above 10 GHz. Additionally, due to the high dielectric
permittivity, the size of the tunable elements based on ferroelectrics may be smaller in
comparison to the other competing technologies.
And the fabrication and integration
processes are relatively simpler than MEMs, however there are still important issues to be
resolved for this technology can be considered seriously for commercialization.
A comparison between the different technologies for microwave agile devices is shown in
table 1.1.
4
Table 1-1 COMPARISON BETWEEN DIFFERENT TECHNOLOGIES FOR AGILE DEVICES [5].
1.3
Research Objective
The use of ferroelectric materials for applications in microwave devices has been
considered as early as in the late 1960s [6],[7]. Despite several successful demonstrations
in the early days, ferroelectric materials were not considered a good candidate for
microwave systems due to the high dielectric losses [5]. However, with the recent advances
in device processing and a deeper understanding of the physics of ferroelectric materials,
the efforts to realize ferroelectric-based microwave devices have intensified, especially in
the last two decades [8]. Nowadays, there are an extensive number of reports on the
integration of ferroelectric materials with ferroelectric devices, and most of them are for
demonstration purposes. However there are only a few reports detailing a comprehensive
synthesis methodology coupled with an optimized material selection process that is suitable
for the present technological and economic demands.
5
The objective of this thesis is to develop a synthesis and integration approach to
fabricate microwave devices based on a ferroelectric material, using traditional IC fabrication
and circuit assembly methodologies and practical materials while still delivering high
performances. The research requires an interdisciplinary collaboration between Electrical
Engineering and Materials Science. Our focus, as Materials Scientists, is to identify the most
suitable materials based on property and physical compatibility, optimize the synthesis of
the ferroelectric, the substrate, and the electrode into a device that can be directly integrated
into a microwave system. Our aim is to demonstrate the possibility of fabricating complete
modular devices that can be made to fit pre-existing microwave systems. In so doing, we
address a number of purely materials science issues, a number of synthesis challenges,
and a number of purely engineering problems.
The thesis is structured into 9 chapters. The literature review is given in chapters 2
and 3. Chapter 2 defines the concept of dielectrics and outlines the fundamentals of
ferroelectric materials. For our research we employed a ferroelectric material in the
paraelectric phase. Thought the material is regarded as a ferroelectric, the material is
employed in the paraelectric phase; the distinction will become clearer in chapter 3. Chapter
4 describes the preparation of the dielectric as well as the photolithography process. We
consider the preparation of the dielectric as an essential part of our research and since the
research is heavily leaned towards device fabrication, a great deal of attention is placed in
the photolithography step. Chapter 5 describes the fabrication and integration of a filter array
composed of 4 bandpass filters. The work done in this chapter can be described as the
“driving engine” of our research. Following chapters deal with the optimizations and
limitations of the integration process implemented in chapter 5. Chapter 6 presents a study
done on the impact of the metallization on the performance of the devices discussed in
chapter 5.
Two factors were studied in this chapter. Chapter 7 introduces a potential
limitation for microwave devices in general integrating coplanar electrodes. In this chapter,
the concept of fringe capacitance is developed and compared to simulations and results in
the literature.
Chapter 8 describes a novel way to integrate ferroelectric materials in
microwave devices. This chapter details the optimization steps required to achieve the novel
structures. Some results are presented which show properties better than the traditional
6
structures. This chapter is considered a preliminary exploration research.
And finally
chapter 8 gives the conclusions and the future research directions.
The technical goals of this project are driven by the need to improve our integration
methodology in order to achieve the required microwave performance at frequency above 6
GHz.
The work presented in thesis aim at improving the foundations laid by previous
researchers for integrating ferroelectric thin films in microwave devices for low frequencies
devices, 1MHz – 1 GHz. We also present a processing path that can be scaled to mass
fabrication for commercialization purpose. The technologies used for our processing are
amenable for large scale production and the materials used are widely available and
relatively low cost.
7
Chapter 2 Ferroelectricity
2.1
Review of Dielectric Properties of Solids
Ferroelectrics are considered insulating materials that possess two or more possible
non-zero polarization states under zero applied electric field; those states are commonly
referred as spontaneous polar orientations. For a material to be considered ferroelectric it
also must be able to switch between the different polarization orientations by the application
of an electric field [9]. Before introducing the theory of ferroelectricity, a brief review of
dielectrics is warranted.
Polarization is considered as the rearrangement of electrically charges under the
presence of an external electrical field [10]. For an insulating material the phenomena can
be, macroscopically, observed as a capacitance value when measured across two metal
plates as shown in figure 2.1.
Figure 2.1 Schematic of a dielectric sandwiched between two metal electrodes under an
electric bias E. The polarization, P, indicates the direction of the dipoles, and Q represents
the amount of charge accumulated at each electrode.
8
The application of an electric field results in a finite displacement of the positive and
negative charges forming electric dipoles. The electric moment acquired by a charged
particle is proportional to the magnitude of the electric field. The measure of the ability of the
material to respond to an electric field is called the polarizibility. The total polarization for a
linear dielectric, P , is defined as the dipole moment per unit volume and is given by
P = Nα E
Equation (2.1.1)
where N is the number of particles per unit volume, α is the polarizibility and E is the
applied field. There are mainly four contributions to the total polarization of a material as
given by
α = α e + α i + α di + α sc
Equation (2.1.2)
where αe is the electronic polarizibility, αi is the ionic polarizibility, αdi is the dipolar
polarizibility and αsp is the space charge polarizibility. All four mechanisms are frequency
dependent as each one of them has different relaxation time ( τ )
Dielectric susceptibility, χ, or the permittivity, ε, is the term used to quantitatively
characterize the ability of a material to store charge. The term relates the polarization and
the electric field as given by
P = χε 0 E = (ε r − 1)ε 0 E
Equation (2.1.3)
where ε0 is the permittivity of vacuum. Associated with a static field, E , for free space there
is an electric field, related to the dielectric and called the dielectric displacement, D . When
a dielectric material is inserted between two plates an increase in the amount of free
charges occurs on the electrodes due to the neutralization by the bound charges from the
dielectric. When an electric field is applied without the dielectric, the term is given by:
D = ε0 E
Equation (2.1.4)
9
After the introduction of a dielectric, the free charges on the electrode increase by the
amount that compensates the dielectric polarization, P , thus the dielectric displacement can
be rewritten as
D = P + ε0 E
Equation (2.1.5)
After expanding the term for P , equation (2.1.4) becomes:
D = ε 0ε r E
Equation (2.1.6)
All of the terms and equations above were defined for an isotropic and homogeneous
dielectric. For a non-isotropic dielectric the equation 2.1.4 can be rewritten in tensor notation
as
3
Di (r ) = ε 0 ∑ (ε r )ij E j (r )
j =1
Equation (2.1.7)
i, j = 1,2,3 = x, y, z
The dielectric constant of a material is dependent on the frequency at which the
material is probed. As mentioned earlier different polarization mechanisms are active at
different frequency ranges, and thus the permittivity is intimately related to the associated
polarization mechanism within a material. For a transient electric field (assuming a
sinusoidal wave, E = E o sin (ωt ) ), the dielectric constant is then treated as a complex term,
which is dependent on the frequency (ω)
ε (ω )* = ε r ' (ω ) − iε r " (ω )
Equation (2.1.8)
where
ε r ' (ω ) = ε ∞ +
and
εs −ε∞
1 + ω 2τ 2
Equation (2.1.9)
10
ε r " (ω ) = (ε s − ε ∞ )
ωτ
1 + ω 2τ 2
Equation (2.1.10)
The real term, ε r ' , is usually identified as the measured dielectric constant ε r , and ε r " is a
measure of the average power loss in the system. Often, the loss is expressed in term of the
phase angle δ given by
tan δ =
εr"
εr '
Equation (2.1.11)
The frequency dependence of the permittivity and the loss is due to the different
polarization mechanisms active within the material. The permittivity is given by the sum of all
the active polarizations at a given frequency, while the loss generally consists of two
contributions; one due to the conduction and the other due to relaxation effects. The
frequency dependence of the real and imaginary parts of the dielectric constant in the
presence of the different polarization mechanism is shown in figure 2.2.
Figure 2.2 Real and complex permittivities contribution from different polarization
mechanisms as a function of frequency.
As shown in figure 2.2 the total polarization contribution to the real term of the
permittivity is additive. The electronic polarization, which is due to the shifting of the electron
cloud with respect to the positive nuclei/core by an applied electric field, is present at all
frequencies, for all materials, up to 1016 Hz (due to their extremely low mass), beyond this
11
range the material behaves as a vacuum, εr ~ 1, χ ~ 0. The contribution due to the electronic
polarization is rather small compared to the other mechanisms due to the small number of
polarizable charges present around the atoms and the limited displacement allowed due to
the large restoring force. Typical permittivity values for materials with only electronic
polarization mechanism are generally around 1 to 5. However for covalent materials such as
silicon, εr = 11.9, where the most prevalent contribution to the permittivity is from the
electronic polarization, the permittivity value is unusually high. This is attributed to the
delocalization of the valence electrons, which are not necessarily fixed in their position. They
can tunnel from bond to bond, and thus when an electric field is applied, the negative
charges shift with respect to the positive ionic cores rather than a single atom.
Ionic polarization is also present in all materials that are not perfectly covalent.
Compared to the electronic mechanism, the ionic polarization responds at a lower
frequency, about the infrared frequency, due to the higher mass of the ions. The polarization
is the result of the change in bond length due to the shifting of the positive and negative ions
under an applied electric field, and for this case the restoring force depends on the ionic
bonds. Generally this mechanism contributes to higher permittivity compared to the
electronic polarization. A typical ionic material like common salt, NaCl, has a permittivity
value close to 6.
For both the ionic and electronic mechanisms, the dipoles are created after an
electric field is applied. In the case of orientational or dipolar mechanism, the polarization is
the result of the re-alignment of permanent dipole moments within the material.
Some
materials, such as water, possess permanent local dipole moments. In liquid water, as the
dipoles are randomly oriented due to thermal agitation, this results in a net polarization of
zero. However when an electric field is applied, the dipoles are forced to align parallel to the
electric field, and thus resulting in a net polarization. This polarization mechanism responds
at even lower frequency than the two previously mentioned mechanisms, around 106 Hz,
partly due of the slow movement of the dipoles within the material. Yet the contribution is
larger compared to the other two mechanisms, for example, water has a permittivity of about
80.
12
The final polarization mechanism is the interfacial or space charge polarization. This
mechanism is due to accumulation of charges around a material singularity, i.e. grain
boundaries, defects, etc. When an electrical field is applied to such a crystal, there is a
displacement of charges, which move until they encounter an insulating boundary. The
accumulation of charges results in a net polarization. Take for example a grain boundary,
when an electric field is applied, grain boundaries generally trap charges moving under the
applied field which leads to a dipole at the interface of the grain, thus the name interfacial
polarization. Generally dipoles involved on this mechanism are very large in term of mass
and also their motion are dramatically slower, so the relaxation time is very long, leading to
low frequency response, around 1 Hz to 1 KHz.
a)
b)
c)
d)
Figure 2.3 Polarization mechanisms: a) Electronic, b) Ionic, c) Dipolar or Orientational d)
Space charge and Interfacial.
13
The peaks in εr” versus ω, in figure 2.2, are called relaxation peaks. As indicated
earlier the imaginary term represents the loss incurred by the material and it is maximized at
frequency ω = 1 / τ , where the angular frequency, ω, determines the rate of energy storage,
and the inverse of the relaxation time, 1/τ, determines the rate of energy transfer to
molecular collisions. At this frequency the two processes occur with the same efficiency, and
thus energy is most efficiently transferred to heat.
When using dielectric material the permittivity and the loss are two important
parameters to consider when designing a device, however they are not the only ones, it is
also important to consider the resistance of the dielectric to conduction at different voltages.
For a given material, the voltage across the dielectric cannot be infinitely increased. There is
an electric field at which the material cannot tolerate, leading to a significant conduction
between the electrodes. This voltage is commonly called the dielectric breakdown. For
gaseous and some liquid dielectrics, the breakdown is not necessarily permanent, so if the
high voltage is removed, the material can return to insulating behavior. However for solids,
breakdown generally leads to permanent formation of a conduction path, which in most
cases renders the material useless.
Dielectric breakdown in solids is an important concern for dielectric research. There
are different types of dielectric breakdown mechanism in solids. The intrinsic or electronic
breakdown, as the name indicates, is related to the intrinsic property of the material and is
caused by liberation of electrons from interatomic bonds. The most common type electronic
breakdown is due to the electron avalanche breakdown. When a large enough electric field
is applied to a material, an electron in the valence band can be accelerated to enough
energy to collide and ionize the host atom of the material. If the energy is large enough this
collision can promote a valence electron to the conduction band, which physically means the
breaking of a bond. The initial collision may be followed by further collisions from the primary
and secondary electrons, which leads to an electron avalanche, causing a significant flow of
current in the material. This breakdown is typically very high, and thus only observed in very
perfect materials. Generally, micro-structural defects locally concentrate electric fields which
leads to breakdown before this mechanism is globally activated. Other type of electronic
breakdowns includes Fowler-Nordheim field emission and tunneling injection.
14
Thermal breakdown occurs when elevated temperatures accompany conduction and
promote localized breakdown and damage. When an electric field is applied, locally elevated
temperatures can occur for two reasons: Joule heating and random molecular collisions. If
the material cannot efficiently release the heat, then further heating occurs leading to failure
in localized spots where the transfer of heat is less efficient, and as these regions grow
further, eventually a conductive a path is created.
External discharge breakdown is due to the presence of contaminants that have
lower dielectric breakdown within the material and thus lead to failure of the material at a
lower electric field than normally observed for contaminant-free material. Contaminants
include: moisture, pollutants, dust, dirt and others. Other dielectric breakdown mechanisms
are: electromechanical breakdown and electrofracture, internal discharges, and insulation
aging. These mechanisms are mostly observed in soft materials.
2.2
Introduction to Ferroelectricity
2.2.1 Historical Background
The earliest record found about ferroelectricity, or rather, the prehistory of
ferroelectricity, was that of the observation of the pyroelectric effect in tourmaline by the
Greek author and Aristotle pupil Teophrastus 23 centuries ago [11]. Teophrastus wrote that
this mineral showed the property to attract straws and bits of wood, as well as copper and
iron [12]. This property was also related to heating/cooling of the mineral. In 1824, Brewster
observed the same property with different crystals and coined the term ‘pyroelectricity’,
indicating the origin of the electricity with the prefix, pyro-, derived from the Greek word for
fire referring to the heating necessary to achieve the observations [13].
Pierre and Jacques Curie discovered the piezoelectric effect in 1880, and their
findings were presented at the meeting of the Society of Mineralogy in France. Using their
prior knowledge in pyroelectricity, the brothers concocted an experimental setup to test 6
different crystals that were previously known to show pyroelectric effects (tourmaline, zinc
blende, boracite, topaz, calamine and quartz) and found that the compression of these
crystals produced an electric polarity [14]. An identical effect was observed in the same
15
direction but with the reverse sign after decompressing the crystals and neutralizing the
original charge. This property was referred as the piezoelectric effect [14].
The next development came with the discovery of ferroelectricity by Valasek in 1921.
He found that applying an electric field to a sample of crystalline Rochelle salt (sodium
potassium tartrate tetrehydrate) resulted in a hysteresis loop shaped similarly to those found
commonly in magnetic materials when plotted against the electrical polarization[15]. From
the early 20’s to about 1940 there were only two known materials to show ferroelectricity,
the Rochelle salt and some other related tartrates [16]. It wasn’t until 1941 when a new
class of ferroelectric material was discovered related to a series of barium oxide-titanium
oxide compositions prepared by Thurnauer and Deaderick [17]. Dielectric constants as high
as 1100 were observed, an amount that dwarfed that of the rutile (TiO2) with an dielectric
constant of 100, which was the material with the highest known value at that point [16].
Further reporting in the field of ferroelectricity in barium titanate was hampered by wartime
restrictions during World War II. It wasn’t until the end of the war that several reports were
published almost successively from different groups.
Wainer and co-workers at the Titanium Alloy Mfg. Company were the first to show a
dielectric constant peak in barium titanate as a function of temperature, which can also be
shifted to lower temperature by replacing the barium atoms with strontium atoms [18]. Their
work was received for publication in January 25 of 1943, but it wasn’t published until 1946.
Independent works published in 1945 and 1946 from Wul and Goldman from USSR and von
Hippel from the US respectively determined the origin of the high dielectric constant in
barium titanate to be an effect due to ferroelectricity [19],[20]. Ogawa in 1944 from Japan
and Coursey and Brand in 1946 from England also made similar discoveries [21],[22].
Works by Rooksby and Megaw demonstrated that the structure of BaTiO3 at room
temperature is pseudocubic [23],[24].
According to Jaffe, there are three steps that led to the discovery and understanding
of ferroelectricity in ceramics. The first step was the discovery of high dielectric constant; the
second step was to recognize that the origin of the high dielectric constant is due to
ferroelectricity, and the final step recognizing that the poling process is responsible for the
16
polarization of polycrystalline material [16]. It wasn’t clearly understood at that time how the
direct and converse piezoelectric effect was possible in crystals that have multiple
orientations. R.B. Gray of the Erie Resistor Company was the first to show that the poling
process can explain the phenomena, where a sufficiently high voltage can be used to
reverse the electric moments of the spontaneously polarized regions in the ceramic [25].
Work by S. Roberts, published in 1947, showed the first poled piezoelectric barium titanate;
he also demonstrated piezoelectric effect in both the longitudinal and transverse direction of
the material with respect to the direction of the applied electric field [26].
Rapid development in the field of piezoelectricity and ferroelectricity continued
extensively, leading to many theoretical studies as well as applications in a numerous areas
including: memory, transducer, sensors, microwave devices, capacitors and others. The
following section gives a brief overview of the theory of ferroelectricity, starting by
considering the crystal structure that is necessary.
2.2.2 Crystal Structure Consideration
Ferroelectricity is defined as the property of a material to exhibit a spontaneous
polarization, which can be reversed by the application of an external of an electric field. The
term ferroelectricity was coined following the analogy with the field of ferromagnetism in
some respects, however the similarity in the name does not imply the same
phenomenon[16]. In the case of ferromagnetic materials, the property arises due to
interactions of magnetic dipoles associated with individual atoms, commonly observed in
ferrous materials, thus the prefix “ferro”. In the case of ferroelectric materials, the dipoles
arise from the interaction of all the atoms within a crystal, and having the prefix ‘ferro” does
not imply the presence of iron in the lattice, though there are some studies on ferroelectric
materials doped with iron [27].
In order to describe the property of ferroelectricity; one must start by discussing the
“intimate” relationship between the crystal structure and the properties that arise as a
consequence of the crystal ordering. Symmetry of a crystal affects both structural and
physical properties. Detailed treatments of the interrelationship between different properties
and the crystal structure are summarized in several books, including Nye, Sirdeshmukh,
17
Nowick, and Newnham [10],[28-30]. According to Neumann’s principle, any symmetry
transformation applied to a physical property of a crystal must also include the symmetry
elements of the point group of the crystal; in other words, the directional dependence of a
physical property must obey the symmetry of the parent crystal. A diagram of ferroelectric
materials based on the symmetry is shown in figure 2.4.
Figure 2.4 Classification of ferroelectric material according to crystal symmetry [31].
18
Considering the 32 crystal classes shown in figure 2.4 [31], the group can be divided
into two categories: centrosymmetric and non-centrosymmetric. Of the 32, 11 are
centrosymmetric and possess no polarity. The rest of the point groups, 21, are noncentrosymmetric, which means they lack an inversion center [28]. Non-centrosymmetric
materials possess one or more crystallographically unique direction axes, which is a
condition required for piezoelectricity. Of the 21 non-centrosymmetric point groups, 20 of
them show the piezoelectric effect. The point group 432 is the lone non-centrosymmetric
material that is not piezoelectric due to combination of other symmetry elements.
As shown in figure 2.2.1, a sub-group of the non-centrosymmetric point group shows
the pyroelectric effect. These 10 crystal classes have only one unique rotation axis and do
not have a mirror perpendicular to that axis, which lead them to being referred as polar
materials as well. These materials possess the unique property to exhibit a permanent
polarization that scales with temperature. Within this material class are the ferroelectric
materials which have permanent electrical dipoles (often within a window of temperatures)
that can be reversed by an electric field.
The ferroelectric materials can be further divided into four categories. The most
technologically important, is the perovskite type, ABO3. A schematic for a typical perovskite
crystal, barium titanate, BaTiO3, is shown in figure 2.5.
Ba
Ti
O
Figure 2.5 Perovskite structure for barium titanate.
19
A perovskite structure belongs to the space group Pm3m. The crystal structure is
commonly constructed of three species as referred by the chemical notation. Where 1, 2, or
3-valent and 3, 4, or 5-valent cation species occupy the A-sites and B-sites respectively.
The O sites are occupied by 2-valent anions. Conventional representation of the perovskite
structure has the B-sites located in the middle of the cell and surrounded by oxygen
octahedral, while the A-sites sit in the corners of the cell. This depiction is useful for
visualizing the effects of changing the cation radii size of the A-sites on the crystal structure.
Assuming a given radius for the B-site, there is a given A-site radii size that allows for the
structure to be cubic. However if the A-sites are substituted with larger cations, then the cell
structure must shift to a tetragonal structure in order to accommodate the larger species.
With the tetragonal distortion the ion occupying the B-site is forced to move along the
elongated axis, which creates a net polarization relative to the oxygen octahedral as shown
in figure 2.6.
a)
b)
Figure 2.6 Crystal structure of perovskite for tolerance factor: a) Cubic, t =1, b) Tetragonal, t >
1.
20
The relationship between crystal structure and ion size of the three species for a
perovskite cell is formally expressed by the Goldschmidt tolerance factor, which is given by
the following equation [32]:
t=
R A + RB
Equation (2.2.1)
2 (R B + R X )
Where RA, RB, and RX are the ionic radii of the A-site, B-site, and anion ions respectively.
For a cubic structure the tolerance factor must equal to one. When the tolerance factor is
greater than one, the cell would distort to a tetragonal structure. And if the tolerance factor is
less than one, the B-site cation would shift along one of the unit cell corners, resulting in a
tilted octahedron.
Some materials exhibit both cubic and tetragonal crystal structures within a certain
temperature range. The transition temperature between these two phases is commonly
referred as the Curie point or the Curie temperature, ΘC, and it is one of the most studied
parameters in ferroelectrics. The next section gives a brief overview of phase transitions in
ferroelectric crystals.
2.2.3 Phase Transitions in Ferroelectrics
The transition temperature from cubic to tetragonal is commonly referred to as the
Curie temperature. In most cases, when the temperature of the material is above the ΘC, a
cubic structure is observed and it does not exhibit ferroelectricity; but if the temperature is
below ΘC, the crystal becomes tetragonal and ferroelectricity is observed. In the cubic phase
the material is commonly regarded to being paraelectric. A telling characteristic of a
paraelectric phase in a ferroelectric material is that of the absence of spontaneous
polarization and a negative temperature coefficient of capacitance. If a material exhibits
multiple phase transitions, the Curie temperature corresponds to the temperature at which
the paraelectric-ferroelectric phase transition occurs [33]. A well known example of a
ferroelectric material with multiple phase transitions is barium titanate, BaTiO3. As shown in
figure 2.7, the Curie temperature for BaTiO3 is about 120°C. Other phase transitions, all of
them bridging additional ferroelectric phases, occur below the Curie temperature [34].
21
Figure 2.7 Relative dielectric constants for a single BaTiO3 crystal for the a-axis and c-axis as a
function of temperature. Taken from Merz [35].
For most ferroelectric materials, the temperature dependence of the dielectric
constant above the phase transition, paraelectric phase, can be modeled fairly accurately by
the Curie-Weiss law as shown in the equation 2.2.2:
ε = ε0 +
C
T − Θ0
Equation (2.2.2)
where ε and ε0 are the relative permittivity and the permittivity of free space respectively. C
is the Curie-Weiss constant, T is the temperature and Θ0 is the Curie-Weiss temperature,
not the same as the Curie temperature. For first order transition Θ0 < ΘC, and for second
order transition Θ0 = ΘC [33].
For most applications utilizing ferroelectrics, the high permittivity value is of great
interests, and as shown in figure 2.7, for BaTiO3, the high permittivity values occur mostly
near the phase transitions, with the highest peak located at the vicinity of the Curie
22
temperature. There are several studies on the paraelectric-ferroelectric transition in the
literature. Among them, Cochran and Anderson proposed a theory for the paraelectricferroelectric transition based on lattice dynamics [33]. According to Cochran, the phase
transition can be regarded as a result of an instability in the crystal for certain vibration
modes, more specifically the transverse vibrational mode, also known as the soft mode
[35],[36]. For a crystal structure to be stable all of the vibration modes must have a finite
frequency, but if a particular mode approaches zero as a function of temperature, the crystal
would transform to a new structure. For a ferroelectric material, Cochran based his study on
BaTiO3, when the temperature approaches the phase transition temperature, Θc, the
frequency of the soft mode would approach to zero, as postulated in equation 2.2.3.
µωT2
= γ (T − Θ c )
R0'
Equation (2.2.3)
Where μ is the reduced mass of the ions, ωT is the soft mode frequency, γ is a temperature
coefficient and R0’ is the restoring “short range” force. The “freezing” of this mode is
characterized by the displacement of the titanium atom to one of the stable locations along
the tetragonal axis.
Lyddane, Sachs, and Teller have shown that:
ω L2 ε (0)
=
ωT2
ε
Equation (2.2.4)
where ωL is the frequency for the longitudinal mode, and ε(0) is the static dielectric constant.
The Curie-Weiss law is reached by combining equations 2.2.3 and 2.2.4. A more interesting
result that arises from the combination is the dependence of the permittivity on the
frequency of the soft mode:
ε∝
1
ωT2
Equation (2.2.5)
As the frequency of the soft mode approaches to zero, the permittivity increases very
rapidly. This result accounts for the “anomalous” high permittivity of the material close to the
23
phase transition temperature as observed experimentally. Fleury and Worlock have verified
the relationship using Raman scattering on SrTiO3 [37].
Another
manner
of
describing
the
phase
transition
uses
macroscopic
thermodynamics. Devonshire developed a phenomenological theory of ferroelectricity based
on the phase transition theories of Landau and Ginzburg. Devonshire’s theory [38-40]
describes the transition using the elastic Gibbs function, G1. The term is expanded in even
powers of the polarization, P, with coefficient terms dependent on temperature, T:
G1 (T , P) = G10 (T ) +
1
1
1
β (T )P 2 + ξ (T )P 4 + ζ (T ) P 6 + ...,
2
4
6
Equation (2.2.6)
where G10, β, ξ, ζ, … are the coefficient terms, G10 is the elastic Gibbs free energy when P =
0.
A stable thermodynamic state is found by finding a minimum value for the free
energy G1. For a crystal that exhibits a spontaneous polarization at certain temperature, P =
Ps, the conditions for a minimum G1 are:
 ∂ 2 G1 
∂E 
 ∂G1 
−1
 > 0, 

 = 0, 
 =χ >0
2 
 ∂P  PS
 ∂P  PS
 ∂P  PS
Equation (2.2.7)
where χ is the dielectric susceptibility. Combining equations 2.2.6 and 2.2.7 results in:
Ps ( β + ξPs2 + ζPS4 ) = 0
Equation (2.2.8)
χ −1 = β + 3ξPs2 + 5ζPs4 > 0
Equation (2.2.9)
There are two solutions for equation 2.2.5. The first solution is Ps = 0, which corresponds to
the paraelectric phase, and the second solution when Ps ≠ 0 corresponds to a ferroelectric
phase.
For the case of paraelectric phase, assuming Ps = 0, the dielectric susceptibility
reduces to:
24
χ −1 = β (T ) > 0
Equation (2.2.10)
For a stable crystal structure in the paraelectric phase, β(T) must have a positive value. The
β(T) term can be expanded using the Taylor series in term of (T-Θc), and by neglecting the
second and higher order terms, we obtain:
β (T ) = β 0 (T − Θ c )
Equation (2.2.11)
Values for β0 can be found in the literature. And by combining equations 2.2.10 and 2.2.11,
we reach the following equation:
χ=
1
β 0 (T − Θ c )
Equation (2.2.12)
by substituting C = 4π/β, then we would reach to the Curie-Weiss law, which can also be
used to describe the dielectric susceptibility in the paraelectric phase.
χ=
C
4π (T − Θ c )
Equation (2.2.13)
For the case of ferroelectric, when Ps ≠ 0, there are two possible solutions, one
corresponding to a first order phase transition, ξ < 0, and the other to a second order phase
transition, ξ > 0. The details of the solution are beyond the scope of this study, however the
plots for both phase transitions of polarization as a function of temperature are shown in
figure 2.8.
25
a)
b)
Figure 2.8 Simulation of typical polarization-temperature plots for: a) Second-order transition,
and b) First-order transition.
The paraelectric-ferroelectric phase transition for BaTiO3 has been given the most
attention due to the vast array of applications that it enables, and that it exists just above
room temperature. The properties of the material, i.e. permittivity, losses, polarization, etc.,
can be tailored to suit multiple applications. However both phases are not necessarily suited
for the same applications; ferroelectric phase materials find more applications in the nonvolatile memory field, where the presence of the spontaneous polarization is used to
represent bits of information, while paraelectric phase materials are commonly used for
applications where low dielectric losses are needed such as microwave devices: the topic of
this work. For this work, the paraelectric phase of barium strontium titanate is used, so
details of the ferroelectric phase will be omitted, and the bulk of the next section will deal
exclusively with the paraelectric phase
2.3
Paraelectric Phase
The paraelectric-ferroelectric transition in BaTiO3 has garnered the most attention
due to the multitude of applications in which the material can be used. The main difference
between the two phases is the lack of a spontaneous polarization in the paraelectric phase.
The presence or absence of spontaneous polarization can be observed by doing either a
26
polarization measurement or a double capacitance-voltage sweep, one voltage sweep for
each direction.
Polarization vs. electric field plot for a material with a ferroelectric phase shows a
hysteresis curve analogous to that found in magnetization vs. magnetic field plots for
ferromagnetic materials. There are several parameters that can be identified from the plot,
see figure 2.9: the remnant polarization, Pr, is the polarization value of the material at zero
bias, also known as the spontaneous polarization, the saturation polarization, Ps, is the
maximum polarization, and the coercive field, Ec, is the field necessary to reverse the
direction of the net polarization of the material.
Figure 2.9 Polarization vs. Electric Field plots for: a) A ferroelectric phase, and b) a
paraelectric phase.
In the case of ferroelectric phase in BaTiO3 regions with the same polarization
direction exist within the same crystals or grains, and are commonly called ferroelectric
domains. These domains play a great role in defining the properties of the ferroelectric
phase. A tremendous quantity of literature can be found discussing this topic alone. For our
purpose this topic will not be dealt with, as we mainly work with the paraelectric phase of the
material where domains do not exist.
The main parameters that are of interest for our study are: dielectric constant,
tunability and dielectric losses. All of them are dependent to each other so in order to
27
optimize these material properties, one must have a thorough understanding of the
mechanisms that contribute to those properties.
2.3.1 Dielectric Permittivity
For an ideal ferroelectric in the paraelectric state, where the dielectric contribution
arises exclusively from the lattice dynamics, the origin of the high permittivity is attributed to
interplay between forces that keep the material in a non-poled state in the absence of an
electric field. In the vicinity of the phase transition, the restoring force that keeps the crystal
from entering the polar ferroelectric state is weak. Consequently, the dielectric is extremely
compliant and leads to high permittivity. [8]. It is worth noting that in the ferroelectric phase a
second contribution associated with the motion of ferroelectric domain walls is present.
Landau put forward a methodology to describe the dielectric response of a
ferroelectric material. The theory is based on the expansion of the Helmholtz free energy, F,
with respect to the vector macroscopic polarization, P. For the case when the polarization
has the same direction as the macroscopic electric field, E, the dielectric permittivity, εr can
be expressed as (for εr >>1):
εr =
1 ∂P 1
1
1
=
= ε (0)
2
ε 0 ∂E ε 0 α + 3βP
1 + 3βε (0)ε 0 P 2
Equation (2.3.1)
Equation 2.3.1 can be used to describe the permittivity with and without a bias. In the
absence of an electric field the polarization term is set to zero, P = 0, to obtain:
ε r = ε r (0) =
1
ε 0α
Equation (2.3.2)
In the case where there is a bias then the polarization is set to Pdc, where Pdc is the value of
the polarization at the given bias.
The coefficient α, is a temperature dependent term, and according to the Landau
theory, it can be expressed as:
28
α=
1 T − Θc
ε0 C
Equation (2.3.3)
where C is the Curie-Weiss constant and Θc is the Curie temperature. For displacive
ferroelectrics the coefficient α can be taken to be valid for a wide range of temperature, from
a fraction of the Debye temperature all the way up to the melting point of the material. For
typical displacive ferroelectrics, values for the Curie-Weiss constant are about 105 K [8].
As shown in equation 2.3.4, the maximum permittivity is observed when the bias is
zero. In the case of ferroelectrics, the high permittivity arises from domain walls movement
and partial domain switching. When a bias is applied the permittivity decreases due to the
reduction of the number of domains and domain walls, as they align with the direction of the
electric field, and consequently the only contribution arises from the ionic and electronic
polarizations at very high bias. In the case of the paraelectric phase, at temperatures close
to the Curie point, where domains are absent, the lowering of the vibration frequency of the
soft mode causes the restoring force, opposing the electric poling, to be weak, and thus
contributing to a large permittivity. Application of a bias would significantly “freeze” those
vibrations thus reducing the permittivity. The property of ferroelectric materials to reduce
permittivity under an applied electric field – often referred to as dielectric tunability - makes
them attractive for agile devices. The following section explains the concept of tunability.
2.3.2 Tunability
The tunability for a material is an arbitrary term used to quantify the change in
permittivity as a function of the applied bias, and it is commonly done in reference to the
permittivity obtained at zero bias, but not necessarily. The tunability is commonly expressed
as:
n=
ε (0)
ε (E )
Another way of expressing the tunability, is the relative tunability:
Equation (2.3.4)
29
nr =
ε (0) − ε (E )
× 100
ε (0)
Equation (2.3.5)
Typically higher permittivity leads to higher tunability. This effect can be clearly
observed if we combine equations 2.3.4 and 2.3.5:
n=
ε (0)
= 1 + 3βε (0 )ε 0 Pdc2 ≈ 1 + 3β (ε (0 )ε 0 ) 3 E 02
ε (E )
Equation (2.3.6)
n ∝ ε (0 )
3
From the equation, we can see that the relative tunability has a fast dependence on
the permittivity value. However with higher electric fields the dependence slows down. In the
limit of very high electric fields, where n >> 1, the tunability is directly proportional to the
permittivity to the power of 1.
2.3.3 Dielectric Loss
The dielectric loss is a critical parameter to consider when optimizing the properties
of the material. Low loss is almost always desired for electronic applications, specially for
high frequency devices, where dielectric losses would lead to signal loss, which decreases
the signal to noise ratio.
The dielectric loss mechanism can be broadly categorized into two major
contributions: extrinsic and intrinsic. In the case of ferroelectric phase, extrinsic losses arise
from several contributions including domain processes, material defects and local polar
regions. While investigating the aging of BaTiO3-ceramics, Plessner [41] and Lewis [42]
postulated that a large contribution to the ferroelectric loss comes from the motion of domain
walls. Interestingly, the motion of domain walls to a more stable and less polarizable states
is thought to be responsible for the permittivity decay in ferroelectrics over a period of time
(aging). Domain walls can be pinned by interactions with point defects and dislocations [43].
Postnikov et al. proposed that the origin of the loss is due to internal friction from the
interaction of domain walls with the point defects [44-46]. Additional information about the
contribution of domain motion to the ferroelectric losses can be obtained by doing
30
measurements at high frequencies. Kittel [47] and then Sannikov [48] proposed a domainwall motion resonance behavior to explain the reduction in permittivity and increase in the
loss tangent at high frequencies. Gentner et al. explained the physical nature of the losses
as the dampening of moving 90° domain walls on point defects for frequencies up to 108 Hz,
and for frequencies above 108 Hz, the point defects play a lesser role, and the damping
results, rather, from the reflection of thermal-lattice waves interacting with the moving 90°
domain walls.
For the case of the paraelectric phase where ferroelectric domains are absent, the
loss tangent is substantially lower, which makes it a good candidate for microwave devices.
However, the absence of domain walls does not imply a lack of extrinsic loss in the
paraelectric phases. Charged point defects, dielectric relaxation and quasi-Debye
contribution induced by random defects are known to contribute to the extrinsic loss [8].
Schlöman [49] proposed a mechanism for the loss contribution due to charged point defects.
When an AC field is applied, charged point defects tend to move resulting in the generation
of acoustic waves at the frequency of the applied field. The loss contribution from the
dielectric relaxation was deduced from the linear frequency dependence of the loss tangent
at the microwave and higher frequencies, which is attributed to the proposed universalrelaxation law [8]. The physical nature of this contribution is attributed to a variation in
charge transport across barriers such as grain boundaries [50], or to oxygen vacancies near
the interface of the depletion layer [51]. And finally, local polar regions induced by various
defects and structure imperfections in the material can contribute to the dielectric loss due to
the quasi-Debye mechanism [8].
At microwave frequencies the intrinsic and extrinsic contributions are comparable, so
the dominating factor would be determined by the quality of the material, hence for a good
ceramic the loss tangent will be mostly dominated by the extrinsic contribution. However in
the presence of an electric bias, most of the defects and impurities in the crystal are
“frozen”, thus the loss tangent is mostly dominated by the intrinsic contribution. Tagantsev
summarized the main loss mechanisms that contribute to the intrinsic loss in paraelectric
materials. The source of the intrinsic loss can be attributed exclusively to the interaction of
the AC field with the phonons in the material. As the frequencies for both mechanisms are
31
unlikely to match, the resulting energy difference after “collision” results in the intrinsic
losses. The intrinsic loss can be further categorized into three mechanisms, based on the
available efficient schemes to absorb the energy. The three mechanisms are: i. threequantum, ii. four-quantum, and iii. quasi-Debye [8],[52],[53].
The three-quantum mechanism involves the interaction of the AC-field with two
phonons. This mechanism is active in the region where the difference in frequencies
between the two phonons are in the order of the AC field and/or of the phonon damping,
which are usually located in the vicinity of the degeneracy lines of the spectrum. Because
the degeneracy of the spectrum is usually controlled by the symmetry of the crystal, the
temperature and frequency dependence of the three-quantum loss mechanism are very
sensitive to the symmetry of the structure [8].
The four-quantum mechanism corresponds to the interaction involving three
phonons. This mechanism was first observed in alkali halide crystals [54]. Due to the less
stringent restriction, in contrast to the three-quantum mechanism, in terms of the energy and
type of phonons that can participate in the process, the mechanism is active on the whole
thermally excited part of the k-vector space, including the region where the three-quantum
mechanism operates as well. And due to this fact, unlike the three-quantum mechanism, the
temperature and frequency dependences of the mechanism are less sensitive to the
symmetry of the crystal [8].
The final contribution to the intrinsic loss is the quasi-Debye mechanism. The origin
of this contribution arises from the relaxation of the phonon distribution of the crystal, after
interacting with an AC field. Applying an AC field on a crystal invariably changes the phonon
distribution within the material. The relaxation of the phonon distribution gives rise to
dielectric loss similarly as the relaxation of the dipoles gives rise to the loss in the Debye
theory, and thus the name quasi-Debye mechanism. This mechanism is not present in
centrosymmetric crystals, however under the presence of an applied bias the symmetry is
broken, thus allowing for the quasi-Debye mechanism to activate [8]. A plot of the
contribution of the three mechanisms as a function of frequency is shown in figure 2.10.
32
Figure 2.10 Off-scale plot of the frequency dependence of the mechanism of intrinsic loss for
paraelectric materials where: (1) corresponds to the three-quantum, (2) the four-quantum,
and (3) the quasi-Debye mechanisms contributions to the loss tangent, tan δ. Ωo and Γ0 are
the soft mode frequency and the damping (Taken from Tagantsev et al. [53]).
A general rule of thumb when fabricating a device is to obtain the lowest level of
losses and the same is true when processing ferroelectric materials. For most applications
with ferroelectric materials there is an inherent tradeoff between permittivity and loss.
Typically high permittivity values in ferroelectric materials lead to higher losses.
The
acceptable amount of loss should be designed according to the particular application. As
pointed earlier, for microwave devices, the common agreement is that lower loss materials
are preferred, and most of the reports found on the literature concur that the use of the
paraelectric phase is paramount for obtaining high quality devices.
For barium titanate,
BaTiO3, which is typically in the ferroelectric phase at room temperature, the paraelectric
phase, can be achieved by cation substitution of the A-site with strontium atoms [18],[55].
Strontium titanate (SrTiO3) is an incipient ferroelectric and forms complete solid solutions
with barium titanate. Increasing the % mol concentration of strontium in the solution leads to
a drop in the Curie temperature of BaTiO3 with a linear dependence, ~ 3.5 °C per mol % of
strontium atoms [16]. A plot of the dependence of the Curie point as a function of the
concentration of barium in the BST is shown in figure 2.11. The highest permittivity, and
33
hence tunability, is observed when approaching the Curie point as shown in figure 2.7. So
for a paraelectric phase the ideal BST composition would be the one that exhibit a Curie
point just below room temperature. However the lower loss is observed when the material is
far away from the Curie point. So this is the point where a decision must be taken to decide
the maximum loss acceptable for the application in mind, and based on that decision, then,
a composition is chosen to obtain the highest tunability with an acceptable amount of loss.
Figure 2.11 Curie temperature dependence on the concentration of Ba. (Taken from
Tagantsev et al. [8] which is a modified version from Smolenskii's data [56]).
2.4
Conclusions
The knowledge in the field of ferroelectric materials is quite extensive, and the most
part the phenomena can be explained using a combination of macroscopic and
phenomenological theories. In this chapter we gave a broad overview of this phenomenon,
which does not necessarily convey the great amount of literature available in this field. The
available knowledge was of course, as with most scientific areas, turned into potential
applications that can better or improve the available technologies. BST is considered a
34
promising material for tunable microwave devices. The strong non-linear dependence of the
permittivity with an applied bias provides a direct way to achieve frequency tunability. . The
next chapter will give an overview on the integration of ferroelectric thin films for microwave
devices.
35
Chapter 3 Ferroelectric Integration for Microwave Application
3.1
Introduction to Barium Strontium Titanate (BST) Thin films
In the previous chapter the concept of ferroelectricity was introduced. The basic
models considered in the previous sections are, in general, valid for bulk single crystals.
However, the properties of epitaxial/textured ferroelectric thin films do not usually follow
those of bulk crystal, and sometimes the differences are very drastic. Parker et al. have
shown conventionally deposited BST thin films with large dielectric peak broadening
accompanied with temperature shift in the Curie point compared to those found in single
bulk crystal [56]. This effect is attributed to a number of causes, some of them are still
debated until today, including an interface layer (a layer with low permittivity located at the
surface of the dielectric region, i.e. grains, crystals, boundaries, etc.), misfit strain between
the film and the host surface due to the difference in lattice constant and coefficient of
thermal expansion, non-stoichiometry, etc.
3.1.1 Ferroelectric Metal Interfacial Layer
Drougard and Landaeur were the first to mention the interface layer effect to explain
the thickness dependence of the switching rate in barium titanate crystals [57]. The dead
layer method has been widely employed to explain the appreciable differences in dielectric
responses of ferroelectric thin film compared to bulk material. However the exact nature of
the interface layers has been under debate for quite some time. The most common
explanations attribute the origin of the dead layer to a reduction in polarization states due to
the interfacial discontinuity along the dielectric-electrode interface [58-63]. Zhou and Newns
proposed a dead layer effect model for a ferroelectric thin film as an extension to the
Thomas theory of ferroelectricity [64], which is itself a dynamical theory based on the
vibrational range available for the transport of the ferroelectric polarization. The theory also
conveys the softening of the ferroelectric mode as the transition temperature is approached,
like the theory proposed by Cochran, explained in the earlier section.
36
Zhou and Newns extended the theory for a thin film case and introduced a term to
account for the existence of a dead layer located at the interface between the dielectric and
the electrode. The capacitance is then modeled as three capacitors in series: the
ferroelectric layer with thickness of d - 2δ and permittivity of εb, and the two dead layers,
each with thickness of δ and permittivity of εd, as shown in figure 3.1. The equation for the
capacitance is given as:
1 4π  d − 2δ 2δ 


=
+
C
A  ε b
ε d 
Equation (3.1.1)
From equation 3.1.1, an effective permittivity for the three layers can be simulated. The
terms of the equation are not pertinent to this thesis, but a plot of the effective permittivity as
a function of the film thickness, d, is shown in figure 3.2. The point to take from the plot is
that the effect of the dead layer is more prominent at very low thickness. And in the limit of
low thickness the εeff becomes proportional to the thickness of the film [58].
Figure 3.1 Schematic for a capacitor with a reduced permittivity layer
37
Figure 3.2 Simulated behavior of the effective permittivity as a function of the film thickness
[5].
Electrical characterization works on the metal-dielectric interface has led some to
believe that this interfacial layer can be attributed to a depletion layer from a Schottky barrier
formed because of the mismatch of the band structure between the metal and the dielectric
[65-67]. Hwang et al. have shown that the nature of the leakage current of a BST/Pt junction
and the reduction of the dielectric constant with decreasing film thickness can be modeled
fairly accurately with a model assuming a Schottky type behavior with a partial depletion
layer of about 1 nm devoid of any space charges [65]. Though both models provide a fairly
correct description of the lowering of the dielectric permittivity in thin films, they do not
provide a complete picture of this particular phenomenon. For example experiments with 75
nm thick freestanding single crystal BaTiO3 film cut from a bulk single crystal and utilizing
symmetric electrodes exhibit dielectric properties similar to those of the bulk crystal [68].
These results suggest that the dead layer may arise from extrinsic defects, strains and grain
boundaries [69]. Zhao demonstrated a substantial decrease in the dielectric constant with
decreasing grain size in dense BaTiO3, attributing the cause to the “dilution” effect of the
dead layer of the grain boundaries [70]. This occurrence is sometimes called the intrinsic
38
size effect, and adds another level of complexity to the study of ferroelectric thin films. The
objective of this section is to convey the difficulty in achieving a consensus in the
explanation of the differences in dielectric properties between thin films and bulk crystals.
3.1.2 Stress-Strain Effects
The dielectric properties of a ferroelectric material are sensitive not only of the
electric field and temperature, but also of the mechanical boundary conditions. A
ferroelectric thin film deposited on a host substrate is subject to stress and strain that have
significant effect on the dielectric properties of the material. It has been previously observed
that hydrostatic pressure on single BaTiO3 bulk single crystal can cause a shift on the Curie
point [71-74]. Merz observed a linear decrease of the Curie point with increasing hydrostatic
pressure, which he attributed to a reduction of the unit cell volume, favoring a cubic
structure, analogous to the substitution of strontium atoms for barium atoms in the crystal
[71],[72],[75]. Similar effect is observed for ceramic BaTiO3, however the values of the
dielectric constant decrease with increased pressure, while the opposite effect is observed
for the single crystal [73],[74],[76]. Samara believed that since the measurement were done
along the c-axis, for single crystal, the hydrostatic pressure would presumably switch some
of the “c-domains” to “a-domains” and thus leading to higher dielectric constant values (the
permittivity value along the a-axis is higher than that in the c-axis). While in ceramics the
measured dielectric constant is, of course, an average value of the permittivity [77].
Application of a 2-dimensional pressure of a ferroelectric material results in a shift of
the Curie point to higher temperature for both bulk single crystal and ceramic [73],[77],[78].
In the case of single crystal ferroelectric, the applied bi-axial pressure causes a contraction
of the axes in the direction of the applied pressure and consequently an expansion of the
axis perpendicular to the direction of the applied stress thus favoring a tetragonal structure
and a polarization along that axis, and thus stabilizing the structure to higher temperature.
Works by Forsbergh and Jaffe have determined a quadratic dependence for the Curie point
with the applied pressure for single crystal and polycrystalline ceramic respectively [77],[78].
Sawaguchi has predicted, rather, a linear dependence of the Curie point with respect to the
pressure [79]. Separate works by Shirane and Hayashi have found the dependence to be
linear, and suggested that the quadratic dependence found by Forsbergh and Jaffe is
39
merely due to the formation and alignment of domains in the materials, which was originally
expected for ceramics but not for single crystal [73],[80].
Thin films, which are clamped to a host substrate, experience biaxial stress due to
the mechanical boundary conditions. Though the stress and strain effects are interrelated,
for thin film, the strain terminology is better suited to describe the dependence on the
dielectric properties of the ferroelectric. The source of strain in a thin film may be due to the
lattice parameter and thermal expansion coefficient differences between the thin film and the
substrate. Both of those effects are well studied in myriad thin film systems. Another source
of strain encountered in thin films used for microwave devices is due to the applied external
DC field. A strain caused by an applied DC field can be originated from two effects: the
converse piezoelectric and the electrostrictive effects. The converse piezoelectric effect can
be considered as the shifting of the ions due to an applied electrical field. If one considers
the interaction forces between neighboring ions to be modeled as a spring, then one can
imagine the DC field having a stronger effect on weak springs than hard springs resulting in
a net change of the lattice constant. The resulting strain, u, is proportional to the applied
electric field as shown:
u = dE
Equation (3.1.2)
where d is the piezoelectric coefficient and E is the electric field. The strain is dependent on
the direction of the external field.
The electrostrictive effect is a term used to describe strain caused by an applied
electric field, and unlike the converse piezoelectric, the strain caused by this effect is not
dependent on the direction of the electric field. The origin of the strain is caused by the
inherent difference between the contraction and expansion spring constants; it is easier for
ions to expand than contract. The small difference results in a net strain that is independent
of the electric field as shown:
u = gE 2
where g is the electrostriction coefficient.
Equation (3.1.3)
40
As indicated earlier the strain has a strong effect on the dielectric properties of the
ferroelectric thin film. The largest effects are, of course, expected in coherent epitaxial films.
For these films the energy to elastically deform and match the substrate is less than the
energy needed to introduce misfit dislocations and relax to the unconstrained equilibrium
values. Coherent films up to a critical thickness of 2-4 nm with a mismatch of 2.2% have
been obtained for barium titanate films on bulk strontium titanate substrate [81]. Choi et al.
have been able to obtain coherent barium titanate thin film up to three times the critical
thickness on dysprosium and gadolinium scandate single crystal substrates [82]. We can
find in the literature several theoretical studies to describe the effect of the strain on the
dielectric properties of the thin film [82-88]. Pertsev et al. was the first to attempt to classify
the phase transformations as a function of the in-plane strain and temperature [83]. For a
paraelectric thin film the in-plane and out-of-plane permittivities, εin and εout, are given by
1


2η
ε in =  − 2ε 0 µ m q11 + q12 −
q12  
1 −η


ε
ε out
1


2η
=  − 2ε 0 µ m 2q12 −
q11  
1 − η 

ε
−1
−1
Equation (3.1.4)
Equation (3.1.5)
where ε is the unstrained permittivity of the film, which is very close to that of the permittivity
of the bulk single crystal without an applied bias field, μm is the in-plane strain assuming a
isotropically strained film, and qij are elements of the electrostriction tensor, the subscript
indicate the axis of operation, 1 and 2 are denoted for the in-plane axes. The strain, μm, due
to the difference in the coefficient of thermal expansion can be represented as:
µ m = µ mR + (α s + α f )(T − TR )
Equation (3.1.6)
where μmr is the misfit strain at a temperature R, and αs and αf are the thermal expansion
coefficients of the substrate and film respectively [8],[89]. The strain effects are very much
dependent on the manner the film is deposited as well as the choice of the substrates. The
next section will give a brief overview of the deposition methods used to grown ferroelectric
thin films.
41
3.1.3 Thin Film Deposition Techniques: Sputtering
The most widely used processes for ferroelectric thin film fabrications can be
categorized into two types: chemical and physical methods. Chemical methods rely on the
reaction of precursors components during the deposition to synthesize the thin films. The
most typically used chemical deposition methods are: chemical solution deposition (CSD)
[90-93] and metal-organic chemical vapor deposition (MOCVD) [94-96]. As for the physical
deposition methods, the two most commonly techniques employed are: pulse laser
deposition (PLD) [97],[98] and magnetron sputtering [99-102]. RF magnetron sputtering is
by far the most employed technique for fabrication of ferroelectric thin film, in parts, because
of their compatibility with standard semiconductor technology and also the high quality films
that can be obtained. Our discussion in this section will be focused on the sputtering
technique, since all of our thin films are manufactured using this method.
Bunsen and Grove were the firsts to obtain metal thin films by sputtering using a
discharge tube in 1852. Sputter deposited thin films are now widely used for applications in
many areas from electronic devices to reflective coatings for mirror finish windows in
buildings[103]. Sputtering is considered as one of the most promising techniques to
fabricate high quality ferroelectric thin films for microwave tunable devices. The method can
offer high uniformity over large area, as well as compatibility with standard IC processing,
both necessary for scalability and low cost [5]. A typical magnetron sputtering system is
shown in fig. 3.3. The deposition is carried under vacuum, typically at pressures between 1100 mTorr, with an inert gas species such as argon.
42
Figure 3.3 Schematic of a sputtering system.
Magnetron sputtering is one of the many glow discharge-sputtering methods used to
deposit thin films. Magnets are used to enhance the overall deposition yield, as the
magnetic fields confine the ionizing species closer to the target and thus increasing the
deposition rate.
The sputtering process can be divided into two steps: first the discharge step, where
a high enough DC voltage is applied to get a breakdown and consequently a discharge in
the chamber to ignite a plasma. The breakdown can occur via a dielectric arc, creating a
conductive path in an otherwise insulating medium. The second step consists of the target
bombardment and film deposition. During the discharge step in the presence of a magnetic
field (magnetron sputtering), the electrons follow an orbital motion around the magnetic field
lines. These electron motions increase the chances of collision between electrons and
molecules. One of such collisions can strip an Ar atom of an electron resulting in an ion. The
resulting Ar+ ion can either continue colliding with other ions or it can collide with the target
and, by momentum transfer, eject target atoms that eventually land at the surface of the
substrate due to the difference in potential between the target and the substrate. The
43
discharge is done with voltages upward of 1000 Volts, and is maintained by the subsequent
collisions from the secondary electrons that result from collisions with the gas and the target.
Sputtering insulating material cannot be done using a DC voltage as the discharge
extinguishes due to the accumulation of positive charges at the surface of the target. And to
remove those charges, an excessively large voltage is required, around 1012 V. However the
problem can be overcome, noting that the impedance of a dielectric drops with frequency.
Thus an AC plasma can be used to pass currents through the insulating target. There are
two plasma behaviors that occur as function of frequency, roughly separated at 1 MHz. For
low frequencies, < 1 MHz, the plasma essentially behaves like that of a DC plasma, with
complete discharge at each electrode in each half cycle. In this situation both electrodes
alternate as cathode and anode. For high frequency, > 1 MHz, the higher frequency causes
extended electron motions allowing them to gain additional energy boost and consequently
no secondary electrons emitted from the cathode are necessary to sustain the discharge.
The study of plasma discharge and sputtering is an extensive field, and the summary
given in this section is pertinent only as a reference for the experimental data. There are
several references that go into greater detail about the sputtering process [104-106]. Film
quality and, to certain degree, the dielectric properties of the thin film can be optimized by
changing the sputtering parameters. The most drastic effects have been observed by
changing these parameters: the gas sputtering species, deposition pressure, substrate
material, and deposition temperature. For example, it was reported that increasing the total
deposition pressure from 22 mTorr to 58 mtorr caused a change of the film stoichiometry,
(Ba+Sr)/Ti, from 0.73 to 0.98 respectively resulting in an overall increase of the permittivity,
tunability and loss tangent. The atmosphere used for the deposition was a 1:5 ratio of O2:
Ar, and additionally the same authors pointed out that the ratio in the range from 1:1-1:5 did
not have a significant effect on the stoichiometry of the deposited film [107]. In terms of
dielectric properties, it is believed that the addition of oxygen helps to improve the quality of
the film by reducing the number of oxygen vacancies [108],[109] however, concrete
evidence for these effects are specious at best. Shen et al. have found that the permittivity
maximum and the leakage minimum can be achieved using a 1:1 O2:Ar ratio for BST films.
Oxygen can also be removed by following the deposition with a post-annealing step in an
44
oxygen rich atmosphere. Fukuda et al. have shown that BST films annealed at 500 °C in an
oxygen atmosphere have a two order of magnitude lower oxygen vacancy density than the
as-deposited films [110].
Typically the choice of substrate and the temperature at which the film is deposited
play a great role in determining the microstructure of the material, and consequently the
quality of the films. Optimized BST films deposited in silicon wafers typically exhibit a
polycrystalline structure with, tunability of about 3:1 and loss tangent of 1 % [107]. The
permittivities of the films tend to increase with increased deposition temperature. Work by
Baniecki et al. shows permittivities varying from 100 to 600 with BST films deposited at 350
°C to 650 °C respectively [111]. The increased of permittivity with temperature is attributed
to the increase of crystallinity of the material with higher deposition temperature. However
high temperature deposition can cause resputtering of the thin film. The optimum
temperature that gives the best compromise between high crystallinity and reduced
resputtering is that of about 300-350 °C [112].
Using substrates with comparable lattice constant of that of the dielectric or using a
“mediating” sacrificial layer can achieve epitaxial BST films [113-118]. Epitaxial growth of
BST thin film has been demonstrated on lanthanum aluminate, LaAlO3, magnesium oxide,
MgO, strontium titanate SrTiO3 and sapphire substrates. It is well known that tuning the
strain between the film and the substrate can modify the properties of lattice-matched
epitaxial films.
Strain engineering has been used in the semiconductor industry for
advanced devices and also for interface study.
For ferroelectric materials, it has been
demonstrated the possibility to tune the dielectric properties of the film by modifying the
mechanical strain of the interface between the thin film and the substrate [119-125]. Table
3-1 shows the lattice parameter for BST 70/30 and the substrate used for epitaxial growth as
well as their respective thermal coefficient of expansion.
45
Table 3-1 LATTICE PARAMETERS FOR BST AND TYPICALLY USED SINGLE CRYSTAL SUBSTRATES AT
ROOM TEMPERATURE WITH THEIR RESPECTIVE LATTICE PARAMETERS AND THERMAL EXPANSION
COEFFICIENTS [107,120-122,114,123].
3.2
Substrate
Lattice Parameter (nm)
TEC (х 10-6 °C –1)
BST 70/30
0.3965
10.5
MgO
0.4211
8.00
LaAlO3
0.3787
10.0
SrTiO3
0.3904
9.00
Sapphire (c-plane)
0.4758
8.4
Capacitor Configuration: Parallel vs. Coplanar
Typically there are two choices for capacitor configurations used for microwave
devices: parallel, where the dielectric is sandwiched between two metal electrodes, and
coplanar, where the electrode lies at the surface of the dielectric. A schematic for both
configurations is shown in fig. 3.4.
Figure 3.4 Schematic for parallel and coplanar capacitor configurations.
Both configurations have been used for microwave devices [101],[126]. Coplanar
capacitors are preferred for obtaining sub-picofarad capacitance values, as only a portion of
the electric field probes the dielectric and substrate. The lower capacitance values come at
46
a price of lower tunability compared to parallel capacitors since the capacitance from the air
and substrate are not tunable. In terms of fabrication, coplanar capacitors typically require a
single photolithography step. As for disadvantages, in addition to low tunability, coplanar
capacitors require higher handling voltages and simulation of the structure is difficult due to
the complexity of the interaction of the electric field with the different layers. Parallel
configuration capacitors typically exhibit higher tunability at lower applied voltages, and the
structure can be more easily modeled unlike the coplanar configuration. However there are
some disadvantages: it is difficult to obtain low capacitance values, and it requires at least
two lithography steps, which include alignment operations [127]. Since our devices are
designed to operate at frequencies beyond 6 GHz, capacitance values needed are in the
range of 0.1-1 pF. For a MIM configuration, assuming a BST layer with dielectric constant of
800 and thickness of 1 µm, it would require an area of about 150 µm2, the level of tolerance
for fabricating devices in this dimensions is enough to drastically change the value of the
capacitance, which makes it unfit for applications where a designed capacitance value is
absolutely required. For a coplanar configuration, the capacitance value is determined by
several parameters, but the main one is the perimeter of the electrode, which is in the order
of 0.5 to 1 mm, and the tolerance level for fabricating on this dimension lead to minimal
variation in the capacitance value.
In the next section we will detail the substrate choice
and metallization.
3.3
Substrate and Metallization for Varactors
Wide varieties of substrates have been used to support ferroelectric thin films. Single
crystal substrates like LaAlO3 and MgO are relatively more expensive or not readily available
in large sizes. More practical alternatives include sapphire, alumina, silicon, glass and fused
quartz. Modified glass (like that used for LCD technology) is not a good alternative since the
processing temperature for barium titanate, typically above 600 °C, approaches that of the
glass softening temperature. Fused quartz, which is made by melting high-purity, naturally
occurring quartz crystal at around 2000 °C, exhibits softening/melting above 1000 °C.
However the TEC of fused glass is about 20 times lower than that of BST, which is not
amenable for thin film integration.
47
Silicon substrates have been the traditional choice for many tunable devices using
parallel capacitors configuration, where the poor microwave properties of the silicon are
screened by the bottom metal electrode, and thus it has little effect on the capacitor
response [96],[107],[128-130]. Using silicon substrate is advantageous, since most of the IC
processes are equipped to handle the integration with little or few modifications. However
integration of coplanar capacitors in silicon has not shown the same success, since the poor
microwave qualities of the silicon is exposed to the electric field, thus resulting in a increase
of the loss tangent of the overall structure. The poor microwave quality of the silicon is
associated with the relatively low resistivity of the material. High-resistivity silicon has been
used, however when annealed at large temperature, temperatures typically associated with
deposition and annealing of BST, the resistivity decreases due to surface effects such as
charge accumulation at the interface between the native oxide layer, SiO2, and the silicon.
Passivation of the surface of the silicon layer has also been explored as a potential solution,
but it requires an additional processing step [131],[132].
Aluminum oxide or alumina (Al2O3), which is the polycrystalline form of sapphire, has
been widely used in the microwave industry due to its low cost, it is availability, it is
compatible with most existing fabrication processes and in terms of dielectric properties, it
has low permittivity and low loss tangent, both critical for high quality microwave devices.
Additionally the coefficient of thermal expansion of alumina is appropriately similar to that of
barium strontium titanate. The main drawback of alumina is that it has a poor thermal shock
resistance due to the low thermal conductivity [5]. Finally, though less mentioned in the
context of microwave devices, it is interesting to highlight the work by Laughlin et al. He
demonstrated the possibility to integrate ferroelectric thin films on smooth copper foil
substrate that is amenable for integration with microwave devices. The integration
processing of the BST thin film in copper is not as simple, however, as multiple fabrication
steps are required and careful control of the annealing atmosphere is necessary to prevent
the oxidation of the copper. Loss tangent of 0.007 was obtained for capacitors fabricated in
copper substrates [133].
48
Figure 3.5 Relative cost of different substrates [5].
Typically the metal of choice used for integration ferroelectric thin films in microwave
devices is platinum. Platinum, being a noble metal, is resistant to oxidation, and
commercially available platinized silicon can sustain temperatures up to 800 °C [134]. In
coplanar capacitors the metal electrode is deposited following the processing of the
dielectric, thus thermal stability is typically not an issue unless the device is designed for
operation at high temperature. When discussing the properties of the metal for microwave
devices, one must take into account the effect of the skin depth.
49
δ =
Equation (3.3.1)
ρ
πfµ
Table 3-2 METAL RESISTIVITIES [137]
Material
Resistivity (μΩ cm)
Silver
1.59
Copper
1.68
Gold
2.44
Aluminum
2.65
Tungsten
5.28
Nickel
6.93
Palladium
10.5
Platinum
10.6
Chromium
12.5
Titanium
42.0
Skin depth is defined as the distance at which the amplitude of the traveling plane
wave decreases by 1/e [135]. The skin depth, δ, depends on three factors: the frequency of
operation, f, the magnetic permeability, μ, and the resistivity, ρ, as shown:
50
Figure 3.6 Skin depth for various metals as a function of frequency.
As a rule of thumb, the required metal thickness for a microwave device is about 3
skin depths. Platinum can be used for coplanar electrodes but because of the high resistivity
it would require about 2.5 times more metal than that of copper, see fig. 3.6. Since platinum
is about 8000 X more expensive than copper, there is a good reason to avoid using platinum
if future commercialization is considered. The three lowest resistivity metals are considered
good candidates for microwave devices, however none of them adhere well to an alumina
substrate as deposited. So to overcome this problem, a thin chromium layer is most often
used to enhance the adhesion of the top metal layer to the alumina substrate [136]. Chopra
believes that the adhesion of the metal film to a ceramic substrate occurs via a bonding with
a metal oxide layer, so the adhesion strength is closely related to the free energy of
formation of the metal oxide [103]. In the case of chromium, then, its oxide, Cr2O3, is
51
responsible for the strong adhesion to the alumina substrate [137]. Our research found that
annealing thin film silver at 500°C increases the adhesion strength to an alumina substrate,
however there is not stable silver oxide at that temperature, so the mechanism of adhesion
is unclear. Adams et al. made similar observations when annealing thin silver film in
parylene substrates [138]. Clearly silver is a strong candidate for metallization, it has the
lowest resistivity, it is widely available, it is not prohibitively expensive, and it does not
require an adhesion layer. However, silver is prone to electromigration when exposed to an
electric field under the presence of moisture as shown in fig. 3.7 [139],[140]. Silver has the
tendency to form dendrites when a bias is applied leading to an electrical short and
consequently failure of the device.
Table 3-3 STANDARD REDUCTION POTENTIALS OF METALS.
Standard Reduction Potentials for Various Metals
Au → Au +3 + 3e −
+
Ag → Ag + e
−
Cu → Cu +2 + 2e −
Al → Al +3 + e
1.80 V
0.80 V
0.34 V
-1.76 V
Solubility Product
Al +3 → Al (OH ) 3
Ag + → Ag 2 O
10-20
10-3
The electrochemical corrosion of metal can be understood by considering the
standard reduction potentials for different metals as shown in table 3-3. Gold has a very high
potential, so it is harder to oxidize, while aluminum having a negative potential, oxidizes
readily. Copper oxidizes more easily than silver, but it does not form dendrites as readily as
silver. Despite its easy oxidation, aluminum forms a stable self-passivating layer which
prevents further oxidation due to the effective insolubility of its hydroxide as shown in table
3-3. Silver oxide is readily soluble in water, so in the presence of moisture and a bias, it can
easily move from one electrode to the other end of the electrode, forming dendrites. The
52
migration of silver is dependent upon the electric field, quality of the dielectric, moisture
content in the surrounding environment and diffusivity of the silver ions in the dielectric. After
a period of time the dendrites will grow long enough to bridge the two ends of the electrodes
leading to an electrical failure [141]. Kupferschmidt et al. found this to be problematic only
when working with electrodes separated between 2-10 μm. Problems were not encountered
when metal silver was patterned for large area lines, as long as the separation between the
two closest adjacent silver lines was larger than 100 μm.
Figure 3.7 SEM micrographs of a before and after the application of a bias in a gap
capacitor on alumina substrate.
So the best candidates for coplanar electrodes narrow down to either copper or gold.
Copper is the preferred choice if low cost is a priority. It is only in the last two decades that
copper has been considered a serious candidate for circuit interconnects, as processing
techniques has improved to mitigate copper oxidation and increase mechanical reliability
[142]. The advantage of using copper over traditionally used metal stacks like TiN and AlCu
can be more appreciated when scaled down to sizes in the range of microns, where a
improvement in resistivity means a reduction of capacitance between interconnects and
therefore a lower cross talk between adjacent lines [143]. For microwave devices, as noted
earlier, platinum is often used for metallization due to the high resistance to corrosion and
stability up to high temperature, however due to the its high cost and etch resistance there is
53
a push to replace platinum with copper. Ghosh et al. developed a process to integrate BST
thin films with coplanar electrodes using a metallization stack consisting of a chromium
adhesion layer followed by a copper layer and capped with a thin platinum layer to prevent
oxidation. They demonstrated that the performance of their varactors were about the same,
if not better, than similar varactors integrated using noble metals (Pt and Au) [126].
3.4
Conclusions
Thin film technology has become the standard for most device-based applications.
Sputtering is a technique that is widely used for deposition of thin films, and for our case, it
provides a reliable and consistent tool to deposit BST films. The integration of the BST films
into microwave devices is non-trivial. A number of factors must be considered when working
with high frequencies devices, especially the metal layer. A key for a seamless integration
of BST is material compatibility. Each of the material components in the device must be
processed without any deleterious effects to the rest of the device. The next chapter we will
detail the processing used for the integration of BST films in microwave devices. Chapter 5
will detail the processing flow used for fabricating a bandpass filter.
54
Chapter 4 Experimental Procedure
4.1
Barium Strontium Titanate Processing
Polycrystalline alumina substrates were purchased from Coorstek (Golden, CO). The
substrate thickness is 0.4 mm and they are polished to a roughness of less than 25 nm.
The root mean square (RMS) roughness of the alumina substrate were measured to be
about 4.6 nm over an 8 μm by 8 μm area measured via atomic force microscopy (AFM).
Figure 4.1 shows an atomic force microscopy image of the surface of a polished alumina
substrate purchased from Coorstek.
Figure 4.1 AFM scan of alumina purchased from Coorstek.
Prior to deposition, the substrates were rinsed with acetone to remove any dust or
particulates at the surface, followed with a methanol rinse. After drying off the methanol, the
substrates were bonded to a 3 inch diameter fused quartz glass that supports the sample
during deposition, using a small amount of conductive liquid silver paint purchased from Ted
55
Pella (Redding, CA). Then the quartz glass was heated in at hot plate at 115 °C (Fisher
Scientific Isoterm Hot Plate, Pittsburgh, PA) for 30 minutes in order to cure the paint. After
that, the sample was loaded into the chamber, and using a combination of a rotary vane
mechanical pump (ULVAC) and a turbo molecular pump (Blazers TPU 330), the chamber
was evacuated to a base pressure of about 1 μTorr. The procedure to obtain the base
pressure is as follow: after loading the sample, the chamber is sealed off by closing the main
door and the venting valve. At this point the mechanical pump is pumping exclusively on the
turbo pump, which is connected to the deposition chamber through a gate valve (which
remains in the closed position during the venting of the chamber). The same mechanical
pump is used to rough the chamber, but first, the backing valve is shut off in order to isolate
the turbo pump and then the roughing valve connecting the mechanical pump is switched
open. The low vacuum pressure is observed with a convectron gauge. Once the pressure
reached 50 mTorr, the roughing valve is switched closed, and then the backing valve and
the gate valve are opened in that order. The high vacuum regime pressure is monitored
with a Granville-Phillips ion gauge (Chelmsford, MA). In order to vent the chamber, the gate
valve to the turbo pump is switched to a close position and then the venting valve is opened.
Similar pumping procedure was used for all other sputtering deposition systems discussed
in this thesis. See figure 2 for more details about the pumping procedure.
A RF magnetron sputtering gun, from Kurt Lesker (Clairton, PA) was used to deposit
barium strontium titanate. As shown in diagram in fig. 4.2, the gun is tilted 30° from the
plane of the substrate and the distance from the center of the gun to the plane of the
substrate is about 8.5 cm. The off-axis sputtering was used to increase film uniformity (in
conjunction with a rotating substrate) and reduce bombardment of negative ions accelerated
towards the substrate. A 3.85 inch diameter by 0.125 inch thick Ba0.70Sr0.30TiO3 (Kurt Lesker)
target was used. The BST target was bonded to a 4 inch cup shaped copper backing plate
with a vacuum rated elastomer (Kurt Lesker). That composition was chosen because it gives
us the best balance between tunability and dielectric loss at room temperature [144]. The
quartz glass was placed on the sample stage inside the chamber. The sample stage holds
the glass above the heater, so the stage can move independently of the heater. The heater
was made of graphite and coated with boron nitride. The temperature was monitored with a
56
S-type thermocouple and controlled with a PID controller, Eurotherm type 820 (Leesburg,
VA). The stage was rotated at a speed of about 5 rpm via a 12V dc motor. The substrate
was heated by radiation heat through the quartz glass.
The plasma was initiated and maintained with a 13.56 MHz RF power supply and a
flow of pure argon (UHP Ar 99.999%). The RF energy was delivered with an RFX-600
power supply purchased from Advanced Energy (Fort Collins, CO). The flow of the argon
gas was controlled using MKS Instruments (Andover, MA) mass flow controller. The total
pressure of the chamber during deposition was controlled by partially closing the gate valve.
The deposition rate was calibrated using a Dektak 3030 profilometer (Santa Barbara, CA).
Typical thickness used for our capacitors ranged from 0.45 to 1 µm.
Ghosh et al. have previously optimized the sputtering conditions for thin film BST on
alumina substrates [126]. The same conditions were reproduced to verify the quality of the
films obtained. Some of the conditions were adjusted to accommodate a new BST target,
i.e. in some cases, new targets required lower power to achieve the same deposition rate as
compared to the previous target. A summary of the conditions used is shown in the table 41.
Table 4-1 OPTIMIZED SPUTTER DEPOSITION CONDITIONS.
Parameter
Value
RF Power
250 Watts
Deposition Pressure
10 mTorr
Target to substrate distance
8.5 cm
Argon flow rate
20 sccm
Deposition temperature
300 ºC
Ramp rate
30 ºC
Deposition rate
9 nm/min
57
Figure 4.2 Schematic of the BST sputtering system
After deposition the substrate were placed on a Protherm (Ankara, Turkey) furnace.
The temperature was ramped up to 900 ºC with a rate of 30 ºC. The samples are typically
annealed at 900 ºC for about 20 hrs for full densification and crystallization. After annealing,
the films were left to cool down to room temperature. A schematic of the furnace used is
shown in figure 4.3. The annealing conditions used for the BST thin films followed that of
the conditions given by Ghosh [126]. He has shown that 900ºC was the optimum annealing
temperature, and complete crystallization of the BST films required at least 20 hrs of
heating.
58
Figure 4.3 Schematic of the furnace used for annealing BST thin films.
4.2
Physical Characterization – BST Test Capacitors
A series of characterization tests were performed on the BST films in order to verify
the structure and properties of the BST films. X-Ray diffraction analysis was used to
determine the crystal structure and the quality of the BST thin film. Atomic force microscopy
(AFM) was used to obtain high-resolution images of the surface of the BST, which allowed
us to assess the morphology and the roughness of the surface.
The x-ray measurements were made using a Bruker AXS D-5000 diffractometer
equipped with an area detector. A 0.8 mm collimated Cu-Kα with a wavelength of 1.54 Å XRay beam was used for the measurements. The output of this tool gives a “map” of the
diffracted intensity where the horizontal axis shows the 2θ Bragg angle, and the vertical axis
shows the out of plane tilt which is denoted in the X-Ray software as χ. A θ-2θ plot is
obtained by integrating the counts over the χ axis. The data from the X-Ray plots were
compared against powder diffraction data found in the JCPDS software, version 2.14
(Newtown Square, PA).
59
An x-ray plot for an optimum BST film is shown in fig. 4.4. An X-Ray plot of the
alumina substrate was obtained for a baseline comparison, which helped us discern the
BST reflections from the alumina reflections, also any unaccounted peaks from an unknown
phase would become obvious through the analysis. The data found for the BST films are
consistent to the ones found in the JCPDF X-Ray databank for a random polycrystalline
BST powder. No secondary peaks were observed, which would indicate the presence of
additional crystalline phases.
Figure 4.4 X-Ray plot for an alumina substrate and an annealed BST film deposited in alumina
substrate. The asterisks indicate the peaks belonging to the alumina substrate.
The XRD characterization can only give us qualitative information about the crystal
structure.
A useful tool to characterize the microstructure of the material is to use AFM.
The surface morphology of RF sputtered polycrystalline barium strontium titanate thin films
show a granular structure as seen in fig. 4.4. From the AFM scan we typically measured
60
grain sizes of about 70 nm and RMS roughness of about 3.5 nm over a 1 in by 1 in area,
which compares favorably with the films obtained by Ghoes [144].
The measured
roughness is about 1 nm less than the roughness measured in the alumina substrate.
Previous works from Ghosh have shown a significant increase in grain size with higher
annealing temperature. The increase in grain size led to higher tunability as well [144]. Full
characterization using transmission electron microscopy (TEM) or scanning electron
microscopy (SEM) in cross section has been performed in the preceding theses of Laughlin
and Ghosh for the instrumentation and the process conditions used in this thesis. As the
subject of this thesis is primarily associated with integration and filter preparation, a similarly
detailed structural analysis was not conducted. The quality of the sputtered dielectric as a
function of processing conditions is mature and well known and the material structure,
properties, and morphology are comparable the that presented in previous studies [144].
Figure 4.5 AFM scan of a typical BST thin film in alumina.
4.3
Photolithography and Liftoff – BST Test Capacitors
Photolithography was used for patterning the coplanar capacitor metal electrodes. It
was also used for masking purposes for etching either the dielectric or the metal.
61
Photomasks were acquired from Photoscience Inc. (Torrance, Ca). A liftoff technique was
developed to pattern the test capacitors.
A negative imaging resist, Clariant AZ5214E (Muttenz, Switzerland) was used.
Patterning using a negative resist creates an overhanging ledge, as supposed to a straight
edge typically obtained with positive resist. The overhanging structure allows for a sharp cut
between the metal deposited on the film and the metal deposited on top of the resist, which
makes it more amenable for liftoff. A schematic for both cases are shown in figure 4.6.
Figure 4.6 Schematic for resist profile obtained for a) positive and b) negative photoresist,
before and after metallization. The straight sidewall profile can result in uneven metal
removal, while the overhanging profile allows for clean metal break after liftoff.
In most cases, the photoresist process followed the same steps. The samples were
rinsed with acetone to remove any dust or organics from the surface, and followed with a
methanol rinse. Following the rinsing, the samples are dried on a Fisher hotplate at 115 °C
for 5 minutes. After the drying step, the sample is placed on a spin coater (Model WS-400A6npp/Lite, North Wales, PA) and a generous coat (enough to cover the whole substrate) of
photoresist is applied on the surface. The sample was then spun at 4700 RPM for 50
seconds to obtain a 1.5 μm thick resist layer, and then soft-cured on the hotplate at 90 °C for
2 minutes. After curing, the sample is then loaded onto the aligner for exposure under the
patterning mask. The aligner used was a MJB 3 Karl Suss Aligner (Garching, Germany), set
at 250 watts of power with exposure wavelength of 365 nm. The photoresist can be
62
processed either positively (the unexposed resist region crosslinks) or negatively (the
exposed resist region crosslinks) depending on the exposure time. If positive processing is
required, the exposure time used is between 6 to 10 seconds depending on the substrate
and thickness of the resist. Opaque substrates and thicker resist require longer exposure
times. The patterning is then developed by dipping the sample into a commercial developing
solution, MF 319, to remove the uncrosslinked resist. For negative processing, the resist is
exposed to a maximum of 2 seconds, depending on the substrate and then placed on the
hotplate at 115 °C for 90 seconds. After the second curing, the sample is placed in the
aligner once more for flood (no mask) exposure for 90 seconds. Then the patterns are
revealed with a developer solution Microposit MF-319 (Rohm and Haas, formerly Shipley
Company, Philadelphia, PA) to reveal the patterns.
A diagram flow for negative
photolithography is shown in figure 4.7.
Figure 4.7 Process for negative photolithography. 1. The sample is cleaned with acetone and
methanol, 2. a coat of photoresist is spun on the sample and cured for 2 mins at 90 °C, 3. the
sample is exposed for 1.5 secs in the aligner with the mask, 4. the sample is cured again at
115 °C for 90 secs followed by 5. a flood exposure for 90 secs and 6. finally the sample is
developed.
Typically a metal deposition step follows after the photolithography processing, in
some cases the photolithography was also used to define etching patterns either for the
dielectric or metal where the photoresist was used to protect the desired structure from
63
etching. Following the metal deposition, the removal of the photoresist, and the metal on
top of it, hence liftoff, was performed using acetone in a petri dish. For most liftoffs, dipping
the sample into acetone was enough to remove all the unwanted metal, however in some
cases where there in an incomplete removal, a short time, less than minute, in the
ultrasonicator (putting the sample in a beaker with acetone) can finish off the last remaining
bits of unwanted metals. As the sample was removed from the petri dish or any container
where the liftoff was performed, the sample was rinsed with acetone to prevent the bits of
metals from sticking back to the surface of the substrate. After the acetone rinse the sample
was rinsed in methanol and dried with in-house nitrogen gas.
4.4
Electrical Characterization – BST Test Capacitors
Electrical measurements were performed on BST test capacitors to characterize the
dielectric properties of the BST thin film. Typical coplanar capacitors used for microwave
devices have an interdigitated structure, see figure 3.4. The capacitance and tunability
values depend on many parameters including the number of fingers, the length and width of
each of the finger, the width of the gap, etc. A full characterization on the dependence of
each one of those parameters on the capacitor characteristics can be found in the Ghosh’s
full thesis [144]. In this thesis, the electrical characterizations were performed to ensure
constant performance from capacitor to capacitor and from film to film, and to identify the
relationships linking capacitor dimension, capacitance, and tunability. This data is non-trivial
to collect and model, but is required when designing microwave devices, especially in our
case where minimal variation in capacitance was critical. For our reference electrical
measurements a BST thickness of 0.45 µm was used.
For this study, coplanar interdigitated capacitors (IDC) are fabricated to test the
dielectric properties of the BST thin films. The configuration and dimensions of the IDC
capacitor used for testing is shown in figure 4.8. The IDC structure has many fingers with
dimensions much greater than the gap width. This configuration provides a large capacitor
perimeter, thus a negligible fringe contribution making it ideal for dielectric property
measurements. This geometry provides 10s of pF capacitance, thus is not useful at the
64
microwave frequencies of interest. The IDCs were patterned with platinum metal using a
combination of a single photolithography step and liftoff. The platinum metal was deposited
by RF magnetron sputtering to a thickness of 100 nm. The deposition was done using a 2
inch magnetron gun with a power density of 3.7 Watts/cm2, which gave us an approximate
deposition rate of about 1.2 nm/sec. The sputtering conditions used were: a 10 sccm flow of
UHP argon and a deposition pressure of 30 mTorr. The distance of the sample from the
target was about 5.5 cm.
Figure 4.8 Capacitor configuration used for electrical measurements. There are a total of 40
fingers. Each finger has a length of 200 mm and width of 20 mm. The gap between fingers is
3 mm.
The leakage current was measured using a Keithley 617 electrometer. The
parameters used for the leakage current consisted of 10 measurements per voltage
averaged with two seconds wait between voltage step increases. Each measurement point
consisted of a 0.25 V step. Typical leakage currents obtained for IDCs are about 10-10 A for
fields up to 150 KV/cm (Typically, in the literature, for coplanar electrodes the field is
calculated as the voltage over the gap width), as shown in fig. 4.9, and approximating the
capacitor area to be the projected perimeter of the coplanar electrode, which is about 104
cm2, the leakage density is about 10-6 A/cm2, which is comparable to those found in the
literature.
65
Figure 4.9 Typical leakage current measurement for an IDC.
The dielectric properties of the films were measured using a HP 4192A impedance
analyzer. Several different tests were performed using this tool including capacitancevoltage test, capacitance-frequency test and capacitance-temperature test. The impedance
analyzer can measure responses up to 10 MHz and can deliver dc voltages from –35V to
35V.
For the capacitance-temperature test the sample is placed on a controlled
temperature stage. The whole stage can be sealed off under vacuum as low as 10 mTorr
(achieved through a combination of a rotary vane pump and a liquid nitrogen cold trap,
which consisted of a stainless tube filled with zeolite externally cooled with liquid nitrogen.
The temperature of the stage is monitored via a RTD temperature sensor and controlled
with a K-20 programmable temperature controller purchased from MMR Technologies
(Mountain View, CA).
The films exhibit very low loss tangent and minimal capacitance dispersion with
respect to the frequency up to 1 MHz as shown in figs. 4.13. Measurements from Ghosh et
al. in comparable varactors have shown similar behavior up to 1 GHz [126]. Typical
tunability values obtained for the capacitors are usually around 30%. The tunability limit of
30% is understood considering that the electric field probes the non-tunable elements of the
66
capacitor as well, i.e. the substrate and the air. Low dispersion in the dielectric constant of
BST (demonstrated by numerous research groups) values and the loss tangent with
frequency allow us to evaluate materials and design microwave devices, that are intended
for much higher frequencies, using this low frequency analysis.
The transition temperature for the thin films was typically broad with the peak located
at about 20 °C. The broadness of the peak is attributed to the fine-grained morphology of
the BST film and to the simultaneous sampling of the linear capacitance from air and
substrate. Furthermore, it is understood that the population of very fine grains (sub 50 nm)
contributes a temperature dependence that is frustrated with respect to temperature in
comparison to the larger crystals. Consequently, the superposition of all of all grains results
in a broad effective transition [145],[146].
This measurement is useful for evaluating
applications where the device is not necessarily temperature-controlled, therefore another
level of design is needed in order to account for the variation in the capacitance with
temperature. Our research is focused in the early stage of the integration, thus we maintain
an awareness of temperature dependencies, but we do not at this stage incorporate this
information to device or system design. As the research moves toward specific application
and reliability studies, this importance of this data will be increased. Furthermore,
temperature dependent data gives the opportunity to characterize the phase transition,
perhaps the most important crystallochemical aspect of ferroelectric materials. Throughout
this work, monitoring the phase transition and its diffuseness provides an important means
of material evaluation. The figures below show the three characteristic responses of BST
capacitors prepared in this work.
67
Figure 4.10 C-F plot for an IDC measured from 100 KHz to 1 MHz and zero bias.
Figure 4.11 C-V plot for an IDC, measured at 1 MHz from –35 V to 35 V. The voltage was
modified to display the electric field instead.
68
Figure 4.12 C-V plot for an IDC measured from –173°C to 237°C at zero bias.
4.5
Characterization
BST films, metal electrodes, substrates, and integrated devices were characterized
to ensure appropriate structure and electrical properties. The complete suite of
characterization tool used is shown in the following Table 4.2. These instruments were
available in our laboratories, those of our collaborators, and at NCSU shared facilities.
69
Table 4-2 LIST OF CHARACTERIZATION TOOLS USED AND TEST PERFORMED.
Test
Equipment
Purpose
Atomic Force Microscopy
Nanosurf easyScan 2 Afm
Microstructure
(AFM)
(Liestal Switzerland)
Scanning Electron
JEOL 6400F FESEM (Tokyo,
Microscopy (SEM)
Japan)
Transmission Electron
JEOL 2000FX
Interface analysis
Leica Wetzlar (Wetzlar,
Microstructure
BST Etching quality check
Microstructure
Microscopy (TEM)
Optical microscope
Germany)
Profilometer
Veeco Dektak 150 (Chadds
Ford, PA)
Electrical Test
HP 4192A LF Impedance
Analyzer (Miami, Fl)
MMR SB-100 Seebeck
measurement system and
Thermal Stage (Mountain
Processing quality checking
Deposition rate and thickness
Via 3D mapping
Capacitance-Voltage Test
Capacitance-Temperature
Test
Leakage current test
View, CA)
Keithley 617 electrometer
(Cleveland, Oh)
4-point Probing
Keithley 2182A (Cleveland,
Metal resistance
Oh)
X-Ray Diffraction Test
Bruker AXS (Madison, Wi)
Crystal structure
Crystal quality
70
4.6
Conclusions
We showed in this chapter details in two key processing steps, dielectric deposition
and photolithography.
BST films deposited by RF sputtering in our laboratories exhibit
dielectric properties comparable to those observed in the literature. Photolithography is a
well-matured technology in the IC industries. Though our photolithographic tools are not
state-of-the-art, we can consistently obtain high quality metal patterning with 3 µm
resolution.
71
Chapter 5 Bandpass Filter Integration
5.1
Tunable Microwave Devices based on BST Thin Films
The integration of BST thin films has been demonstrated in a number of microwave
devices with successful results. There are some companies that are presently attempting or
pursuing commercialization of this technology for microwave tunable devices. Thus, in some
cases, ferroelectric microwave devices have moved beyond the realm of research, into a
stage where the focus is to optimize and develop processing techniques that are amenable
to commercial best practice. Some of the microwave devices where BST material has been
integrated to include:
•
Tunable phase shifters [127],[147-149];
•
Tunable filters [94],[126],[150-152];
•
Voltage-controlled oscillators [153-155];
•
Power amplifiers [156],[157];
•
Antennas and tunable matching network [158-160]
The present research focuses on microwave bandpass tunable filters. A bandpass
filter transmits a band of frequencies while attenuating the remainder. As explained in
chapter 1, the permittivity control with a voltage in ferroelectric materials affords a simple
manner to tune the capacitance in a LC circuits allowing the filter to operate in multiple
frequency ranges, which conveniently reduces the size of the device and the energy
consumption.
Bandpass filters in the current work evolved from a previous collaborative effort with
the Steer and Kingon groups at NCSU and two previous dissertations of Ghosh and Nath
[151],[152]. The filter is based in a 3rd order combline bandpass Chebyshev filter. The order
indicates the number of resonators present in the filter, in this case as shown in fig. 5.1. This
type of filter uses multiple adjacent resonators that couple between each other. The
dimensions of the resonators determine the operating frequency of the filter. The number of
72
resonators and the distance between them determine the range of frequency that is allowed
to pass, pass band. Increasing the number of resonators narrows the bandwidth of the
bandpass but increases the insertion loss [161]. The insertion loss is considered as the ratio
of the power received at the end of the line of the device to the power transmitted into the
line. For the design of Nath and coworkers, 3 resonators gave the optimum combination of
bandwidth and insertion loss. The filter was designed using the MFilter synthesis tool in the
Genesys suite from EDA, Eagleware (Santa Clara, Ca). Works by Nath et al. demonstrate
the integration of similar bandpass devices for frequencies range of 1-3 GHz. Nath et al.
have shown a bandpass filter result using discret BST varators with 16% frequency tuning
from to 2.44 to 2.88 GHz with an insertion loss of 5.1 dB to 3.3 dB respectively, and a
bandwidth of 400 MHz [151],[152].
Figure 5.1 Schematic of a third order combline bandpass filter.
The device presented on this thesis is a further development of Nath’s bandpass
filter scaled to higher frequencies with 2 major processing improvements:
1.
Via interconnects are used for direct grounding, thus circumventing the use of epoxy
and/or ground straps, and enableing much lower inductance interconnection. Via
interconnect technologies have been previously investigated for high density packaging in
silicon integrated circuits [162]. In our case the vias were filled to provide an even flat
73
surface compatible with subsequent lithography and deposition processing steps.
Subsequent to our work, a variety of fillings have been reported; Clem and Sigman et al.
have reported a similar device using via filled with copper-tungsten alloy, which required
careful control of the annealing atmosphere to prevent the oxidation of both metals
[163],[164]. For our purpose we chose a filling based on gold, which does not require any
special atmosphere during the dielectric deposition and subsequent annealing steps.
2.
The second improvement integrates directly the ferroelectric varactors with the
microwave substrate. This integration is enabled by the via technology and eliminates the
need to bond discrete varactors into the device. A potential complication of this method is
the need prepare three varactors with the same capacitance, the same tunability, and
excellent voltage tolerance. This requirement is not impossible, but it does require an
additional level of process control.
We note that these integration aspects represent engineering advances that
are novel to the field of integrated ferroelectric thin films. The NCSU groups of Maria
and Steer pioneered these methods which to date have been copied and adopted by
others. The objective of this chapter is to present our novel methodology to fabricate a fully
integrated device for frequency agile microwave circuits based on BST. Although the
present study is applied to the fabrication of a bandpass filter, similar strategies can be
utilized in other devices.
5.2
Bandpass Filter Array
Our technological task is to deliver a fully functional bandpass filter able to operate in
the range from 6 to 18 GHz with a bandwidth of 700 MHz and insertion loss of about 7 dB.
This range cannot be addressed by a single element. Assuming a capacitance tunability for
our varactors to be in the order of 25%, we found that it was necessary to design 4 separate
filters to access the whole frequency range. The frequency allocation per element is shown
in figure 5.2. The filters are grouped physically on two substrates or tiles, with two frequency
bands per tile. The physical representation is shown in figure 5.3.
74
Figure 5.2 Schematic of filter array. Each tile contains two elements. Each element addresses
a specific frequency range.
Figure 5.3 Schematic for a tile. The tile includes two bandpass filters, band 1 and 2. Groundsignal-ground structures were used to measure and characterize the performance of the
filter. Three BST gap capacitors are located at the top of the resonator lanes.
5.3
Device Integration
The integration of the bandpass filter can be divided into three steps: the substrate
processing step (mostly outsourced to outside commercial parties), the dielectric processing
step, and the metallization step.
75
5.3.1 Substrate
The alumina substrates were purchased from Coorstek, and machined to the
required dimensions by LPT-Inc. The vias were laser drilled (LPT-Inc., OR) with a diameter
of 150 μm. The purpose of these vias is a conduction path between the fully metallize device
ground plane (substrate back side) and the front face metallization lines as needed. Two
methods were tested to achieve this interconnection: the first method consisted on through
hole sputtering using chromium for adhesion and then followed by a layer of gold. The
advantage of this method is that the step can be performed in conjuction to the metal
deposition for the device and the backplate as well as the electroplating step, however the
presence of open holes in the substrate presented a challenge for spinning an even layer of
resist, which is necessary to achieve successful photolithographic patterning, especially at
small dimensions. The second method is to fill the via with a conductive material providing
the necessary grounding as well as a flat surface for the lithography steps. The vias were
filled by Hybrid-Tek with a propietary mixture containing gold and glass frit. The filling is
screen printed and fired in air at 900 º C, and then polished to obtain a flat profile. The filling
mixture was chosen to withstand the dielectric deposition as well as the annealing step in air
at
900 º C. A comparison of resist profile around a via is shown in figure 5.4. The
appearance of interference fringes in the resist layer at the periphery of the open via
indicates a thickness gradient. These fringes are nearly eliminated in the case of a filled via.
These fringes are particularly important to avoid because in some cases, gap capacitors are
located in their field. A resist layer with variable thickness does not crosslink or develop
uniformly and makes fine features nearly impossible to define.
76
Figure 5.4 Optical pictures of a via after spinning photoresist for: A. hollow via, and B. filled
via.
5.3.2 BST Deposition and Patterning
The barium strontium titanate was deposited by RF magnetron sputtering at 300 º C
for 45 minutes resulting in a thickness of 0.45 μm. The via-ground connections need to
contact the device, so an etching step was required to remove the BST from the top of the
vias. The BST was patterned using photolithography and etched off with a 1% HF solution
removing the BST layer from all regions besides the immediate vicinity of the gap
capacitors.
The etching solution was prepared by diluting 2 ml of 50% by volume of
hydroflouric acid in 100 ml of deionized water. The etching was done in two repeating
steps, a dipping step where the sample was dipped into the HF solution for 4 minutes
followed by a drying step in a controlled hotplate, set at 115 ºC for 3 minutes, those steps
are repeated until a total etching time of 16 minutes was achieved. The drying step was
used to prevent the photoresist from being removed by the HF solution. We had observed
that prolonged etching time would result in the removal of the small photoresist strip.
Subsequently the substrate was annealed in air at 900 º C for 20 hours to fully densify and
crystallize the dielectric. It is important to consider and measure the extent to which the BST
deposition and annealing impacts the via filling metal. Profilometer maps were collected
from the via top surface before and after annealing. Fig. 5.5 shows the results. In general,
77
we observe some minor material densification and redistribution that results in a more
homogeneous and smoother surface profile.
Figure 5.5 Profilometer 3D mapping of the surface of the via: a. as received, and b. after
annealing in air at 900°C for 20 hours.
5.3.3 Metallization
The metallization step consisted of three steps. The first step consisted of defining
the resonator lines, the biasing line, the measurement structures and the test structures, we
called this step the device metallization step. The second step consisted in defining the gap
capacitors, and we define this step as the varactor metallization step. And the third step was
to electroplate the whole device with copper, and thus the copper-plating step. A cross
section of the metal stack across a resonator line is shown in figure 5.6. A schematic of all
of the metallization process is shown in figure 5.7.
Figure 5.6 Cross section of the metal stack across a resonator line.
78
Figure 5.7 Schematic of the metallization process for a bandpass filter. The first metallization
step was done for the resonator lines, the biasing lines, the testing structures and the signal
structures. The second step was the metallization for the gap capacitors and finally the third
step was the copper plating of the whole device.
5.3.3.1 Device Metallization
Silver was used as the base-layer metal of choice for the bandpass filter pattern in all
regions except for the gap capacitors. The small gaps, high electric tuning fields, and the
propensity for silver electromigration predicated this selection. Silver metal was deposited by
RF magnetron sputtering. The sputtering was done using a 2 in silver target purchased
from Kurt Lesker loaded into a AJA ST-20 (North Scituate, MA) magnetron gun.
The
deposition was optimized to achieve the lowest resistivity possible while still retaining good
79
adhesion. A series of experiments were performed to optimize the resistivity of the films.
The two parameters that have the most impact on the resistivity of the films were the
deposition pressure and the annealing temperature. The lowest resistivity silver film was
obtained at a deposition pressure of 25 mTorr and with annealing in air at 500 °C for 30
minutes as shown in fig. 5.8 and 5.10. Deposition of silver at pressure above 20 mTorr
resulted in better adhesion and lower resistivity, which can be attributed to low residual
stress in the films, and an increase in grain size respectively. Marechal et al. have shown
that silver films deposited by RF-magnetron sputtering at higher pressure, above 20 mTorr,
typically exhibit lower residual stress that those deposited at lower pressures [165].
Figure 5.8 Plot of resistivity vs. deposition pressure for as deposited silver thin film. The
adhesion test consisted on whether the film would peel off under a simple peeling test with a
Scotch tape (3M, Maplewood, MN).
Figure 5.9 AFM scans for silver thin films deposited at 5 and 20 mTorr.
80
The resistivity of the film tends to decrease with increasing grain size as shown in
figures 5.9 and 5.11. Grain boundaries are known to contribute to the scattering of electrons
in thin film materials, so by increasing the grain size the proportion of grain boundaries to
the volume of the material decreases and thus the resistivity on the films would decrease
[166],[167].
Figure 5.10 Plot of resistivity vs. annealing temperature in air for silver thin film.
Increasing the deposition pressure resulted in a modest grain growth, however
annealing the films resulted in a much more dramatic grain size increase. Silver films
annealed at 500°C, reach a grain size of about 3.5 μm. The grain size was measured using
the linear intercept method. This increase is accompanied by resistivity values approaching
that of bulk silver. All of the annealed films were able to pass the peeling tape test, which we
used as a quick and easy way to ensure complete adhesion of the silver film to the
substrate.
81
Figure 5.11 AFM scans of silver thin films annealed at different temperatures.
The patterning of the silver film was performed by a combination of photolithography
and etching. By using etching instead of liftoff, a thicker metal can be deposited. Liftoff can
be done with liftoff as well, but it would require more viscous photoresists to achieve higher
thickness, which typically requires more complex curing processes and also harsher
chemicals for removal (as supposed to acetone) which can damage the material in the
substrate.
82
The sample was blanketed with a 1.2 µm of silver deposited by sputtering using the
conditions shown in table 5-1. Then the film was annealed in a furnace at 500 ºC for 30
minutes in air. The patterning was performed using a single photolithography step, similarly
as explained in the experimental procedure. Then the sample was etched in a commercial
etching solution CR-7 (Cyantek, Freemont, CA). For a 1.2 µm thick silver film, it took about 3
to 4 minutes to etch the unwanted silver completely. After the etching the sample was
rinsed in water to remove the leftover etching solution and then rinsed with acetone to
remove the photoresist.
Table 5-1 CONDITIONS USED FOR SPUTTER DEPOSITION OF SILVER FILM.
Parameters
Conditions
Power density
5 Watts/cm2
Gas and flow
10 sccm of Argon
Deposition pressure
25 mTorr
Target to sample distance
6 cm
Deposition rate
~ 0.25 µm/min
5.3.3.2 Varactor and Back Plane Metallization
A dual sputtering gun system as shown in fig. 5.12 was used for the metallization,
which allows us to deposit the adhesion layer and the top metal layer without breaking
vacuum, thus limiting the surface oxidation of the adhesion layer. The depositions of these
metals were optimized to give us the best adhesion possible. The test was performed
similarly as the one used for testing the adhesion of the silver film. The test was performed
by laying a piece of Scotch tape on top of the metal stack and quickly peeled off. An
adhesion test is considered successful if the tape remained clean after the peeling.
Typically we used a combination of 70 nm of chromium followed by 350 nm of gold
for our coplanar capacitors, giving a total thickness of about 420 nm, which was within the
83
suggested thickness for good liftoff using a 1.5 µm thick resist. Deposition for both metals
was done with 10 sccm of argon at 10 mTorr. The deposition rate for chromium was about
45 nm/min and for gold it was around 70 nm/min. A liftoff step with acetone was used to
define the capacitors. After liftoff the same metal stack was deposited in the back of the
substrate for grounding purpose.
Figure 5.12 Schematic of the dual magnetron sputtering system.
The gold films obtained as deposited showed resistivity values of about 5.7 μΩ cm,
which is about two and half times higher than that of the bulk. The high value can be due to
the high proportion of grain boundaries to grain volume as shown in fig. 5.13. Further
optimization to reduce the resistivity values of this metallization is possible, but the need to
preserve an oxide-free Cr surface make this objective challenging, i.e., the inability to
increase the temperature during or following deposition. The gold metallization dimensions
are small in comparison to the total filter, thus the contribution to overall resistance is minor.
Reducing the resistivity would be beneficial in future device generations.
84
Figure 5.13 AFM scan for a gold thin film.
It is paramount for the proper operation of the bandpass filters that the capacitances
values for the varactors close to the designed values as well and also consistent with each
other. For gap capacitors, there are two factors that determine the capacitance value, which
are the length of the gap and the width between the electrodes as shown in figure 5.14. The
tolerance factor for the photomask is about 0.5 µm, so clearly for a gap width of 3 µm, this is
the area where the source of capacitance variation may arise.
The photolithography
process itself also carries a tolerance factor, and in order to measure that deviation we took
an optical picture of the gap and measured several gap widths as shown in figure 5.15. For
all gap capacitors we observed a maximum ± 0.5 µm gap width deviation of the designed
value, 3 µm. The gap width of 3 µm was chosen because it gave us the best compromise
between tuning and easiness of processing. Wider gap width would increase the tuning
voltage, which is not desired for devices. However narrower gap width would increase the
difficulty of processing as the dimensions reach the resolution limit of the aligner itself.
85
Figure 5.14 Schematic of the gap capacitor on top of each resonator line. The capacitance
value of the varactor depends on the width of the gap, W, and length of the electrode, L, of
the gap.
Figure 5.15 Optical picture of a gap with gap width measurements.
5.3.3.3 Copper Plating
To minimize the resistive component of microwave loss, it is advantageous to
increase the metal thickness to multiple skin depths in all areas possible. To accomplish
this, a copper electroplating process was developed to build up metallization thickness of all
regions except the immediate vicinity of the gap capacitor (since the gap width is on the
order of microns). It is possible to reach this thickness range with a combination of
86
photolithography and liftoff, however the processing becomes more difficult, in particular
considering the need to achieve resistivity values that are very low. A simpler method is to
use electroplating. We developed a process to electroplate copper as shown in figure 5.16.
For the electroplating step the sample is completely dipped into a commercial copper
electroplating solution (Technic Inc., CA) and rotated at a speed of about 100 RPM, with a
small DC motor. This speed was optimized to replenish the copper ions around the sample
but without creating a vortex that would limit the plating rate. A block of bulk pure copper
(Technic Inc., CA) was used to deliver the plating ions. The sample and the copper block
are connected to a power supply that can deliver a constant current. We determined that a
current density of 25 mA/cm2 gives us the lowest possible conductivity for electroplated
copper (about 2.7 μΩ cm). The areas adjacent to the gap capacitors were masked with a
photoresist layer using a photolithography step in order to prevent the bridging of the gaps
during plating. The optimal thickness and an experiment to determine that value is the
subject of Chapter 6. A photograph of a finished Tile A with bandpass filters 1 and 2 is
shown in figure 5.17.
Figure 5.16 Schematic of the electroplating setup.
87
Figure 5.17 Picture of a finished and ready for use Tile A with bandpass filters 1 and 2.
5.4
Bandpass Filter Results
The microwave characteristics of the filter were measured on a HP 8510 C Network
analyzer using a 150 μm pitch ground-signal-ground probe. The setup was initially calibrated
using a CS-5 calibration substrate. Biasing of the capacitors was done using a HP 4142 B
parameter analyzer. The insertion and the return loss were extracted from the raw data as a
function of the frequency. Typical insertion loss versus frequency plot is shown in figure
5.18. From this plot we obtained several important characteristics of the device including:
•
The operating frequency, which is the frequency at which the device is designed to
operate. This is the center of the frequency band that is allowed to pass through the device.
•
The insertion loss, which indicates the ratio of the output power to the input power for
the operating frequency. Ideally, one would want an insertion loss value of zero.
88
•
The bandwidth or passband, which is the range of frequencies that is allowed to pass
with a threshold signal strength.
•
The rejection band, which indicates the lowest insertion loss observed for the
rejected range of frequencies. Higher values for this parameter indicate a better rejection
performance for the filter.
Figure 5.18 Typical plot for insertion loss as a function of frequency for a tunable bandpass
filter.
89
Table 5-2 MICROWAVE RESULTS FOR TILE A FILTER ARRAY.
f0 (GHz)
Bandwidth (MHz)
Insertion Loss (dB)
Tunability (GHz)
Designed band1
6.0
700
7.00
1.50
Measured band 1
6.0
350
10.7
1.37
Designed band 2
7.5
700
7.00
2.50
Measured band 2
7.7
477
11.0
2.25
Table 5-3 MICROWAVE RESULTS FOR TILE B FILTER ARRAY.
f0 (GHz)
Bandwidth (MHz)
Insertion Loss (dB)
Tunability (GHz)
Designed band3
10.0
700
7
3.30
Measured band 3
10.5
600
17
1.50
Designed band 4
13.3
700
7
4.70
Measured band 4
13.5
800
11
1.65
For all 4 bands, the measured center of frequencies and bandwidths are within the
desired specifications of the designed values, though, for bands 1 and 2 the bandwidth
values are about 300 MHz lower, which is easily tuned by adjusting resonator coupling. The
insertion losses are higher than desired for all 4 bands. Both bands 1 and 2 exhibit tunability
values close to the designed values, however for band 3 and 4 the values are substantially
lower.
This process of filter fabrication can be viewed as a tremendous technological
success. From a materials preparation and device integration perspective, we produced the
following advances:
1.
Successfully integrated via-interconnects. The use of via for ground plane
connections provides a low resistance pathway required for reducing the insertion loss in the
device. We have demonstrated that a via filled with a combination of glass frit and gold can
withstand the thermal processes during the fabrication process.
2.
We have demonstrated the feasibility to design and process a microwave device
from the ground up.
This monolithic integration was enabled by the ability to directly
integrate the BST varactors into the device. We have shown that by using our processing
90
techniques, which in no way can be considered state of the art, we can obtain BST
varactors with minimal variation in the capacitance and tunability values.
3.
Finally we have provided a processing “recipe” that can be used to integrate BST
thin films with microwave devices.
The highlight of our integration processing is that all of
the materials used are relatively cheap and the techniques used are easily scalable to large
production. We have managed to deliver a completed device ready to be mounted on a
circuit board.
Filter preparation and test also identified several key pathways to meeting our
performance goals, these include: 1) lowering insertion losses and 2) increasing varactor
tunability.
There is a host of sources that can contribute to insertion losses, these include the
substrate, the dielectric, and the metal. For high frequencies the insertion loss is mostly
dominated by the contribution from the metal elements due to finite resistance as shown in
figure 5.13, and due to an effectively fixed and frequency independent dielectric loss tangent
(in our frequency range of interest). The quality factor for a device is given as the sum of the
contributions from the substrate, the dielectric and the metal. The quality factors for the
substrate and the dielectric are given by the inverse of the loss tangent, and have been
experimentally show to vary little with frequency [168]. For the metal the quality factor is
given by the inverse of the product of the frequency, capacitance and sheet resistance
[169]. As such, Fig. 5.19 teaches that overall reductions in insertion loss can occur by
reducing the overall device resistance.
QTotal = Qsubs + QBST + Qmetal
QTotal =
1
1
1
+
+
Tanδ subs Tanδ BST fC p RS
Equation (5.4.1)
Equation (5.4.2)
91
Figure 5.19 Quality factor contribution from substrate, metal and dielectric as function of the
frequency.
An overall assessment of device metallization suggests that reducing insertion loss is
possible if we can lower the resistivity of all metal elements (in all cases, we observe
resistivity values higher than bulk), and if we can increase the thickness of the overall metal,
with attention to potentially strategic locations in the vicinity of the gap capacitors.
Furthermore, simulations suggest that design modifications associated with our biasing lines
can reduce IL by as much as 1 dB.
Also another way of lowering the insertion loss worth mentioning is to modify the
design of the filter so as to widen the passband. There is an inherent, but not necessarily
direct, dependence between the bandwidth and the insertion for a bandpass filter that we
92
have been able to observe. The effect cannot be generalized for all cases in other devices
or even a different filter design.
As shown in table 5.3 the measured frequency-tunability values for both bands 3 and
4 are much smaller than the designed values. A contributing cause for this problem is a
reduction in the capacitor tunability. These filters were prepared upon an assumption that
gap capacitors could be scaled to values consistent with the entire X-band. These early
results proved this assumption incorrect. Consequently, this thesis involved a study of gap
capacitor capacitance values and the tunability values as a function of gap length and width.
The results of this investigation are discussed in chapter 7.
5.5
Conclusions
We have demonstrated an integrated bandpass filter array for the frequencies range
of 6 to 18 GHz, using innovative processing and integrating techniques, while relying in low
cost and scalable materials and tools. The performances of the filters are not truly aweinspiring, but the aim of this thesis was to prove the possibility to integrate BST thin films in
ferroelectric devices. We believe that further optimization in the design of the device can
increase the performance. In the next three chapters we will show further optimizations,
from the material side perspective, to reduce the insertion losses and increase the tunability
of the capacitors.
93
Chapter 6 The Impact of Metallization Thickness and Geometry for X-band
Tunable Microwave Filters
Peter G. Lam, *Zhiping Feng, *Vrinda Haridasan, Angus I. Kingon, *Michael B. Steer, and
Jon-Paul Maria
North Carolina State University, Departments of Materials Science and Engineering and
*
Electrical and Computer Engineering, Raleigh NC, 27695-7919
6.1
Abstract
The impact of dc resistance on the performance of X-band filters with ferroelectric varactors
was investigated. Two series of combline bandpass filters with specific geometries to isolate
sources of conductor losses were designed and synthesized. A combining the changes in
filter geometry with microwave measurements and SONNET simulations quantitatively
identified the dependency of insertion loss on metallization thickness and local regions of
thin metallization. The optimized 8 GHz bandpass filters exhibited insertion losses of 6.8 dB.
These filters required three skin depths of overall metal thickness to achieve this loss. The
integration scheme required thin regions of metal in the immediate vicinity of the varactors. It
is shown through experiment and simulation that short (i.e., 15 µm) of thin metallization can
be tolerated provided that it is located in regions where the resonant microwave current is
low.
(Published in the IEEE Transactions on Ultrasonics Ferroelectrics and Frequency Control)
94
6.2
Introduction
Barium Strontium Titanate, BaxSr1-xTiO3 (BST), thin films have been successfully
integrated in a variety of devices. One of the most attractive implementations is occurring in
tunable microwave circuits, where the permittivity of a BST non-linear dielectric element is
voltage tunable allowing for high speed modulation of resonant frequency. The ability to
span a range of frequencies offers tremendous potential reductions in system size since in
principle one tunable subsystem can replace numerous ones that operate at a series of
fixed bands.
This property enables frequency-agile devices such as phase shifters
[170],[148], antennas [171], and filters [94],[151] to be built.
There is substantial literature discussing processing of BST thin films for microwave
circuits, but substantially less that focuses on integration strategies and their impact on
device performance. A number of authors have reported on bandpass filters incorporating
BST thin films, especially in the low end of the gigahertz frequency spectrum.
These
tunable filters typically show insertion losses between 3-7 dB, center of frequencies between
0.2 GHz and 1.8 GHz, and a fractional bandwidth of 30% [94],[172-175]. They are typically
integrated with discrete varactors based on a metal-insulator-metal (MIM) configuration
where the dielectric is sandwiched between two metal electrodes. This configuration is
consistent with very low tuning voltages, but the micron range dielectric thickness produces
large capacitance values that limit application to the low GHz range.
Higher frequency bandpass filters require lower capacitance for appropriate
impedance matching. This can be easily achieved with a planar capacitor configuration,
where the counter-electrodes are deposited on the dielectric top surface. The planar
capacitors can range in geometry from a simple gap to a more sophisticated comb. Several
literature examples of filters using these planar structures show insertion losses between 57 dB with center of frequencies between 1.6-2.4 GHz, with a bandwidth of about 400 MHz
[151],[152].
In this frequency range discrete IDC varactors can be integrated into the
bandpass filters using surface-mounting strategies.
Discrete planar varactors provide
several advantages such as reduced fabrication complexity, compatibility with polymer
based filter packages, and batch fabrication and testing of individual elements prior to filter
integration.
However, filter assembly by discrete integration severely limits the upper
95
frequency boundary. For instance, with increasing center frequency the resonator line
dimensions approach a size range where discrete assembly is problematic: the narrow
resonator width and small contact pads magnify any errors in capacitor location. These
errors will change the resonator electrical length and manifest in substantial contributions to
loss. In addition, microwave circuits become increasing sensitive to conductor losses with
increasing frequency. This demands that metal lines, electrodes, and contacts offer as low a
resistance as possible, and though great advances have been made in automated pick-andplace assembly, none of these surface mounting techniques can offer the nearly ideal
contacts possible using thin film deposition and lithographic patterning of high purity metals.
A number of university and national laboratory groups have been pursing integrated filter
synthesis
strategies
in
recent
years
and
demonstrated
substantial
performance
improvements and access to frequency bands above 10 GHz [164],[176],[177]
Nath et al. implemented a plated via method and pre-drilled ceramic alumina
substrates [152],[178] which eliminated the use of conductive epoxy or wire bond
connections – the vias enable fabrication of a “filter-chip” that can be directly probed or
inserted into a microwave system. Lam et al. further improved this approach by
implementing pre-filled vias with noble metal based glass frit that is compatible with BST
deposition and facilitates more reliable lithographic processing. Sigman et al. have shown
similar band pass filter results in Ku-band and X-band, 8.75 GHz and 14.3 GHz respectively.
Their devices are similarly based on a combline design with barium strontium titanate planar
capacitors and use vias for grounding as proposed by Nath [152]. The devices performed
with insertion losses of 8-10 dB before biasing, and 4-6 dB after biasing for the Ku-band and
X-band respectively. Sigman’s filters exhibited a bandwidth of about 1.7 GHz [164]. It is,
however, important to appreciate the relationship between bandwidth and insertion loss.
Generally speaking, the rules of filter design demand that bandwidth cannot be arbitrarily
reduced without simultaneous increases in insertion loss.
In this report we utilize a monolithic integration strategy for a BST-based tunable
bandpass filter, and directly explore the impact of two aspects on microwave performance:
1) metal thickness of the resonator lines, and 2) the presence of thin segments which couple
the resonator to the interdigitated tunable capacitor. The improved reliability of the filled-via
96
process that enables a focused investigation of basic device parameters like metal thickness
and line geometries, and the identification of design rules for efficiency, and practical
guidelines for integration goals.
6.3
Experimental Procedure
All devices in the present study were fabricated on Coorstek alumina substrates with
both sides polished.
Alumina substrates are preferred given the low cost, the similar
coefficient of thermal expansion (CTE) (Alumina CTEroom
dielectric (BST CTEroom
temp
temp
~ 8.2 ppm) to that of the
~ 9 ppm) [9], its isotropic and low dielectric constant at high
frequency (less that 9.9 at 1 MHz) and also its low loss tangent (tan δ = 0.0001 at 1 MHz).
These latter properties allow us to neglect the contribution of the substrate to the total
device loss. Blank alumina substrates were laser machined by LPT Inc. to achieve the
desired chip size and via locations. Via holes were 250 µm in diameter, and filled with an
Au-based frit by Hybrid-Tek Inc. The via filling process involves a 900 °C air heat treatment,
thus a large thermal processing window for subsequently deposited BST layers.
RF magnetron sputtering technique from a stoichiometric target was used to deposit
Ba0.7Sr0.3TiO3; this composition provides a favorable balance between dielectric tunability
and loss tangent in the vicinity of room temperature. Alumina substrates with filled vias were
heated to 300 °C inside the sputtering chamber. When the system pressure fell below 5x105
Torr, sputtering was initiated in pure flowing Argon at a pressure of 1×10-2 Torr.
Photolithography was used to mask the BST film directly over the future IDC locations and
the remaining dielectric was removed by etching with a 1% HF solution. After etching, the
substrate with patterned BST is annealed at 900 °C in air for 20 hours in order to fully
crystallize and densify the dielectric thin film. The final BST thickness used for this study is
0.5 µm.
The filter metallization is prepared in two stages: stage one forms the resonator lines,
contact pads, and biasing lines, while stage two forms the IDCs and the biasing lines. A
schematic illustration of the filter chip is shown in Fig. 6.1.
97
Figure 6.1 NCSU filter chip schematic showing the two-step metallization layer strategy. Gray
regions correspond to metallization in step one, black regions correspond to metallization
during step two, while dashed circles correspond to metal-filled vias.
This two-step metallization procedure was introduced to overcome the challenges
associated with feature sizes that span many orders of magnitude. For instance, gap widths
of 4 µm and resonator lines of 3000 µm are required for the filter chip. It is a particular
challenge to expose and develop the resist simultaneously and uniformly in a single step
process. Typically, the finer features become overexposed and overdeveloped when the
larger fields are adequately exposed and developed.
Stage one metallization consisted of 1.2 µm of blanket dc magnetron sputtered silver
over the alumina substrate with previously patterned and annealed BST pads. The silver
was patterned by etching using a 4:1:1 methanol, peroxide, ammonium hydroxide solution.
Stage two metallization consisted of a 30 nm chromium adhesion layer followed by 350 nm
of gold. Both layers were formed by dc magnetron sputtering without exposure to
atmosphere between layers, and were patterned by lift-off.
Back metallization was
performed similarly with a layer of Cr followed by 200 nm of gold. Finally, a photoresist mask
that covered only the gap capacitors was formed. Subsequent immersion in a Cu
electroplating bath allowed thick copper deposition on all exposed metal surfaces. Additional
98
details regarding the metallization preparation and the selection criteria for each layer are
available in the references.
The bandpass filter in the study is based on a third-order combline design with three
transmission line resonators, each exhibiting an electrical length designed to achieve the
target center frequency. The BST capacitors are been placed at the end of each resonator
for tuning (see Fig. 6.1). By altering the capacitance values of the loading capacitors, the
electrical length of resonators are changed and frequency tuning of the pass band is
achieved. Optimizing the electrical lengths by using Advanced Design System ADS leads to
a high tuning range and a miniaturization of overall circuit size.
In the design, each
capacitor was subsequently split with the center point providing a convenient bias point at
the common terminals of the pair. A large valued resistor is introduced in bias line to isolate
it from microwave energy and reduce its effect on the microwave performance. A 50 ohm
microstrip line is designed for the input and output of the filters. CPW test pads are added
at the end of the input and output for microwave characterization. The filters were measured
using a vector network analyzer with 250m pitch coplanar waveguide (CPW) probes and
Short-Open-Load-Thru (SOLT) calibration. A detailed description of the S-Parameters
analysis can be found in the Nath’s thesis [185].
Using these synthesis, fabrication, and measurement methods, two sample sets
were prepared that enabled two fundamental aspects of filter design to be explored and
quantified: 1) the effect and impact of overall metallization thickness, and 2) the effect and
impact of locally thin metallization regions in the filter layout. Though it is clear how both
aspects will generically affect filter performance, at these high frequencies, and with these
high dielectric constant materials, simulation and quantification of these effects remains a
substantial challenge. Consequently, we turn to direct experimental verification of these
trends.
6.4
Metal Thickness Effect
A set of filters with systematically varied metallization thickness was synthesized to
determine the quantitative relationship between metal thickness and microwave insertion
99
loss.
Filter metallization consists of sputtered silver lines and sputtered Cr/Au gap
capacitors with subsequent plating of Cu metal. The initial filter in the series features only
the original Ag and Au, while the remaining five have additional Cu plating. The copper
plating series involves a single filter sample that undergoes five subsequent measurement
and plating copper cycles. This is accomplished by leaving the protective photoresist cap on
the gap capacitors during measurement. In so doing, we eliminate to the greatest extent
possible variability associated with the limitations of process control. We note that the gap
capacitors for this measurement are filled with photoresist. However, filters with and without
PR covering the gaps indicate a negligible difference in capacitance and filter performance.
Fig. 6.2 illustrates the general experiment. Note that the lateral and vertical dimensions of
this figure are not to scale. For this particular experiment, the width of residual thin
electrode, i.e., the distance between the edge of the plated region and the gap capacitor
was 50 µm. This width was chosen to minimize the parasitic effect that can occur for very
thick electrodes separated by very short distances to form an air capacitor in parallel to the
IDC. The impact of this thin region is the subject of the second experiment.
Figure 6.2 A cross sectional illustration of a double gap capacitor showing the thicknessdependent electrode experiment. Note that for visual clarity, the vertical and horizontal
scales are different but thicknesses and distances are given for the pertinent components.
The S parameters of the filter were measured for each step in the fabrication process
for the difference thickness of the metal layer in the resonators. The trend between insertion
100
loss (1/|S21|^2) and metallization thickness is shown in Fig. 6.3. As expected, the thickness
of the metal layer has a dramatic effect on the insertion loss of the bandpass filters when the
thickness of the metal layer is very thin. The insertion loss decreases with increasing metal
thickness, and approaches saturation at a value of about -7.5 dB at about 2.5 μm of
accumulated metal. The data indicate that additional increases in thickness would not
provide further reductions.
The top horizontal axis in Fig. 6.3 gives the effective number of skin depths present
for each metal thickness. The effective skin depth was calculated by adding the skin depths
of the silver and copper layer, these values were calculated at 8 GHz using the measured
resistivity values of the Ag and Cu layers: 2 µΩ·cm and 4 µΩ·cm respectively. The
measured results show that a minimum of three skin depths is necessary to minimize the
contribution of dc resistivity to microwave loss.
# of skin depths
1.5
2
2.5
3
3.5
-7.0
-7.5
S
21
-8.0
-8.5
-9.0
-9.5
-10.0
1
1.5
2
2.5
Metal thickness (µm)
Figure 6.3 The dependence of insertion loss (1/|S21|^2) on metallization thickness for an 8
GHz center frequency bandpass filter.
101
6.5
Plating Width Effect
In an ideal scenario, all metal lines would be deposited or plated until approximately
three skin depths of metal are accumulated. However, combining this thickness with a 2 µm
to 4 µm gap capacitor would create a parasitic air capacitor in parallel to the BST that would
dramatically reduce tunability. Consequently, it is necessary to have a short distance of thin
metallization in the immediate vicinity of the gap. In the previous thickness experiment, a 50
µm span of thin metal was used. However, with little alignment difficulty, substantially
smaller distances can be accommodated. Since the results of our study in part 1 show the
dramatic effect of the metal layer of the resonators in the insertion loss of the bandpass
filters, it is possible that some of the additional loss stems from these regions of thin metal.
To experimentally identify their impact, a series of filters were fabricated using a range of
plating masks that provided for 15, 25, 50, and 75 µm of thin metal line on either side of the
double gap capacitor. Fig. 6.4 illustrates the sample set. Again, it is important to note that for
clarity, the vertical and horizontal scales in Fig. 6.4 are not the same. All filters in this series
were Cu-plated plated to a final total thickness of 2.5 μm in one plating step, with an initial
sputtered silver metal layer of ~1.2 μm.
Figure 6.4 Schematic illustration showing the variation in unplated transmission line distance in
the 8 GHz filter. Note that for visual clarity, the vertical and horizontal scales are different but
thicknesses and distances are given for the pertinent components.
The plating width sample series were fabricated for filters with the same 8 GHz
center frequency. The insertion loss values for the unplated and plated states are shown in
Fig. 6.5.
102
-6
-6
S21
-7
-7
plated
-8
-8
-9
-9
-10
-11
-11
Band 1
8 GHz
-12
-13
-10
unplated
0
50
100
-12
150
-13
Unplated width (µm)
Figure 6.5 The effect of unplated transmission line distance on the insertion loss of a bandpass
filter with an 8 GHz center frequency. This plot incorporates data for 4 filters. In the unplated
state, the geometry of the Ag metallization is identical for all devices
The effects of local plating width on the gap capacitors on the insertion loss of the
devices are less severe than that of global metallization thickness for the entire filter. There
is a modest trend linking the unplated width of transmission line before the gap capacitor,
however, changing this width by a factor of five produces an increase in insertion loss of
approximately 0.5 dB in the 8 GHz filter. It is important to note at this point that filter-to-filter
variations produce changes in insertion loss of similar magnitude, thus it is possible that
filter performance is effectively insensitive to the existence of thin metallization regions of
this scale, and this location at the filter.
At first consideration, the comparative insensitivity of filter performance to regions of
thin metallization is unexpected, however, when the λ/8 design strategy is considered, these
results can be understood. The strategy stores a majority of the electromagnetic energy on
the transmission while still obtaining filter tuning from variation of the BST varactor
capacitance. The design maximizes the effect of capacitance variation on filter center
frequency. The resonator dimensions are chosen to be λ/8 of the filter center frequency,
thus under resonant conditions, the microwave current is maximum where the resonator
103
connects to the via, and minimum at the opposite end—at the BST varactor location. As
such, a comparatively small fraction of microwave energy is stored in the vicinity of the
varactors where the conductor losses will be higher due to the unplated region. In the worstcase scenario, the unplated width corresponds to only 4% of the resonator length.
The 8 GHz filter was simulated in SONNET to separate the relative contributions to
device loss. Using a varactor Q of 23 (a value measured on similar discrete BST varactors)
σCu = 2.3x107 S/m, and σAg = 6.2x107 S/m, the simulations predict a total device loss of 7.1
dB, loss due to plated metallization regions = 1.8 dB, and loss unplated regions = 0.5 dB.
These values are comparable to the measured results where total loss for the filter with 150
µm of unplated metal was ~ 7.2 dB, which was reduced by 0.4 dB to 6.8 when the unplated
distance was reduced to 15 µm.
6.6
Conclusions
The impact of dc resistivity on the insertion loss of microwave bandpass filters was
investigated. These property-performance relationships were identified though assessment
of 8 GHz bandpass filters with combline geometry, λ/8 design rules, and BST varactors. Two
series of filters were prepared that allowed the isolation of specific sources of conductor
loss: 1) overall metallization thickness, and 2) locally thin regions of thin metallization.
Establishing experimental guidelines for required metallization thickness and the tolerance
to locally thin regions provides valuable guidelines for filter design, within the practical
limitations of device synthesis. These guidelines are particularly pertinent to microwave
filters that require a combination of very large and very fine features, which can be
challenging to fabricate simultaneously with arbitrary metallization thickness. Filter analysis
shows that roughly three skin depths of metal provide the lowest contributions to insertion
loss; above three skin depths returns are diminishing. In addition, analysis shows that thin
regions of metallization can be present with only minor contributions to device loss, provided
that those regions where resonant energy storage levels are low.
104
Chapter 7 Scaling Issues in Ferroelectric Planar Capacitors
Peter G. Lam*, Zhiping Feng**, Vrinda Haridasan**, Michael B. Steer**, Angus I. Kingon*,
and J-P. Maria*
*North Carolina State University Department of Materials Science and Engineering
**North Carolina State University Department of Electrical and Computer Engineering
7.1
Abstract
We report on the geometric limits associated with tunability of interdigitated capacitors,
regarding specifically the impact of a parasitic non-tunable components that necessarily
accompany a ferroelectric surface capacitor, and can predominate the voltage dependent
response as capacitor dimensions are reduced to achieve the small capacitance values
required for impedance matching at the X-band. We present a case study of simple gapcapacitors prepared and characterized as a function of gap width (i.e., the distance between
electrodes) and gap length (i.e., the edge-to-edge gap distance). Our series of
measurements reveals that for gap widths in the micron range, as gap lengths are reduced
to meet sub-pF capacitance values, the non-tunable parasitic elements limit the effective
tunability. These experimental measurements are supported by a companion set of
microwave models that clarify the existence of parallel parasitic elements.
(To be published)
105
7.2
Introduction
Ferroelectric materials have been long considered for frequency agile devices due to
their strongly nonlinear field dependent permittivity which allows for resonant frequency
tuning in devices based on LCR circuits [5]. Ferroelectric thin films present several
advantages over conventional semiconductor materials that make them very attractive for
high frequency tunable devices, including low loss, fast tuning speed, and small physical
dimensions [94],[151],[95]. Due to these advantages, ferroelectric thin film have been
explored for many high frequency devices, including those based on AlGaN/GaN high
electron-mobility transistors (HEMT) [179], phase shifters [127],[170], and phased array
antennas [171]. Though numerous authors have explored the possibilities for ferroelectric
varactors and addressed a number of material property concerns, comparatively few have
investigated the challenges associated with translating these prototypical concepts into
system-compatible devices. Perhaps of greatest importance is an appreciation for several
practicalities associated with X-band frequencies. Understanding these concerns is critical
since the advantages of ferroelectric varactors become most pronounced (with regard to
competing technologies) in the higher frequency regimes. In this report, the authors address
one of these practical issues – the need to fabricate tunable ferroelectric varactors with Cmax
values in the range of 0.5 pF to 1.0 pF, while maintaining a minimum of 2:1 voltage
tunability.
In most general terms, the resonance frequency a microwave device is inversely
proportional to its overall capacitance. As such, to achieve 50 Ω impedance at frequencies
in the X-band (i.e., 8 GHz to 12 GHz), capacitance values commonly need to be in the range
of 1 pF or lower. Figure 7.1 shows the calculated relationship between capacitance and
frequency for a circuit with 45 nH inductance. As seen in Fig. 7.1, for military applications,
which are commonly in the X and Ku bands, capacitance values are in the range of 10s to
100s of femtofarads.
For BST a film with high electric field tunability, permittivity values approach, and in
some cases exceed 1000. While these large values are generally desirable for device
miniaturization, they present practical difficulties with respect to preparing metal-insulatormetal capacitors in the pF range. For instance, a 1 pF capacitor prepared from a BST layer
106
of permittivity 1000 and 500 nm thickness, would have lateral dimensions of 7 µm x 7 µm.
These values are not particularly small in the context of microelectronics, however, for
microwave devices which require electrode thicknesses > 3 µm (to minimize resistance loss)
and lateral electrode dimensions spanning microns to cm, reliable lithographic patterning
u
X-band
C-band
1
K -band
C (pF)
(Z = 50 ½, L = 45 nH)
and alignment of three-layer structures is non-trivial.
350 fF
0.1
70 fF
0.01
10
20
Frequency (GHz)
30
Figure 7.1 Calculated capacitance as a function of frequency for 50 Ω impedance
matching assuming a 45 nH inductance. This inductance value is chosen as it represents that
associated with the third order X-band combline filters prepared during this work.
Furthermore, the resonator components of microwave structures have a center
frequency that is very sensitive to capacitance; thus, for filters with multiple resonators, the
center frequencies much match to ensure low insertion loss. In the scenario where MIM
capacitor dimensions exist in the range of several microns, the precision of conventional
contact lithography and etching (i.e., ± 0.5 µm) can produce substantial capacitance
variations. For the 7 µm x 7µm case, a -0.5 µm error leads to a 14% error in capacitance.
The subsequent resonant frequency mismatch leads to substantial circuit element loss.
The alternative interdigitated capacitor (IDC) geometry is arguably better suited for
this capacitance range. In this case, the capacitor counter electrodes are located on a
common dielectric surface separated by a µm-range gap. As a consequence, the field is
spread between the substrate, the dielectric and the medium surrounding the fingers, which
107
usually is air or a low K passivation dielectric. Collectively, this results in lower overall
capacitance values and tunability, and larger applied voltages to achieve a similar electrical
bias. Fig. 7.2 illustrates these parallel capacitive components.
Figure 7.2 Schematic of the electric field from the side view and top view.
This geometry affords excellent control of total capacitance as the gap lengths are on
the order of 100 µms, and only one layer of lithographic patterning is needed to define gap
length and width. However, the parallel air capacitors that result from poor field confinement,
will limit tunability as the gap length decreases. In principle, this effect should be
addressable by electromagnetic simulation, however, the small gap dimensions and large
dielectric contrast between BST and air make quantitative simulations particularly difficult.
Most current simulation softwares are unable to handle such complex structure due to the
lack of proven methodology to accurately describe the electric field within the different
layers. Consequently, we tested the set of gap capacitors and studied the dependence of
capacitance and tunability as a function of electrode dimensions.
108
7.3
Experimental Procedure
The barium strontium titanate was deposited on ceramic alumina substrates
(Coorstek, Golden CO) by RF magnetron sputtering at 300 º C for 45 minutes resulting in a
thickness of 0.45 μm. A stoichiometric Ba0.7Sr0.3TiO3 target (Kurt J. Lesker Inc.) was used as
the source material. The BST was patterned using photolithography and etched off with a
1% HF solution - removing the BST layer from all regions besides the immediate vicinity of
the gap capacitors is important for minimizing insertion loss in a fully processed filter thus we
introduce this step to duplicate the in-service boundary conditions. Subsequently the
substrate was annealed in air at 900 º C for 20 hours to fully densify and crystallize the
dielectric. A typical x-ray scan of barium strontium titanate on alumina after annealing is
shown in figure 7.3. The entire family of BST peaks indicates polycrystal material with
random orientation. A more detailed report of the BST deposition, its optimization, and
characterization can be found in the references [11].
109
Figure 7.3 X-ray diffraction pattern for a BST thin film prepared on ceramic alumina substrate
after an air anneal at 900 °C for 20 hours. Only peaks from the alumina and BST are present
and the intensity ratios indicate random orientation.
Interdigitated simple gap capacitors were prepared by one lithographic step with
pattern formation by lift off. Photoresist AZ5214E was spin cast to a layer thickness of 1500
nm and exposed using a contact aligner for 8 seconds. The resist was baked on a hot plate
at 90 °C for 2 minutes in air. The substrate was immersed in developer (MF319) for 60
seconds to develop the pattern. Blanket metallization was subsequently deposited by first
sputtering a 70 nm layer of chromium followed by a 350 nm layer of gold. Layer thicknesses
were determined by a Dektak 150 stylus profilometer. Both layers were deposited in a loadlocked dual magnetron system without exposure to atmosphere between the layers. This
step is critical to maximize adhesion and to avoid peeling during lift off – especially for fine
110
gap features. Lift off was performed in acetone and assisted by ultrasonication. Using this
method, gap widths could be controlled only to within ±0.5 µm. Consequent to this
variability, regardless of the mask used, all gap dimensions were verified by measurement
with an optical microscope and calibration standard to ensure consistency of comparison.
Lift off was chosen for this process because of the difficulty of wet chemical or dry etching
the transition metal / noble metal electrode stack without damage to the BST surface
between the resulting gaps. Using these techniques and instruments, arrays of simple gap
capacitors were prepared where gap length and gap width were varied between 10 and
5000 µm and 1.5 and 5 µm respectively. The substrate dimension (2.54 cm x 2.54 cm) was
large enough to accommodate three devices of each capacitor size, thus one capacitor size
data set can be collected for a single BST deposition. The smaller gap capacitors were
connected to contact pads 600 µm x 400 µm to enable electrical access via needle probes.
The voltage dependence of the capacitance for all devices was measured using an HP
4192A impedance analyzer at 1 MHz between -35 V and +35 V applied dc bias.
Representative tunability data for the BST films is shown by capacitance vs. field data from
a gap capacitor in Fig. 7.4. The large gap length of this structure ensures minimal impact
from edge effects. The field axis is the quotient of applied bias and gap width, which is in
this case 2 µm.
3.0
0.10
2.5
0.08
2.0
0.06
1.5
0.04
1.0
0.02
0.5
-30 -15 0 15 30
Gap Length (µm)
Loss Tangent
Capacitance (pF)
111
0.00
Figure 7.4 Voltage dependence of capacitance and loss tangent for a BST gap capacitor
with a 2000 µm long gap.
7.4
Results and Discussion
The process described above was used to prepare sets of gap capacitors for which
the capacitance was varied systematically by controlling gap length. Sets of gap capacitors
with 2 µm, 3 µm, and 5 µm were fabricated. The gap length spans a range between 10 and
4000 µm, and in so doing changes dramatically the relative contributions of the capacitance
from the BST layer, i.e., that between the electrode gap, the non tunable fringe capacitance
from the substrate and air between the electrode gap, and the non tunable fringe
capacitance associated with the non-linear field distribution occurring at the gap corners.
Fig. 7.4 shows a plot of capacitance vs. gap length for three sets of simple gap capacitors
with constant gap widths of 2 µm, 3 µm, and 5 µm respectively and gap lengths that vary
from 25 µm to 5000 µm. This data set represents an average of the three capacitors of a
given size over three separate BST samples, thus nine capacitors averaged for each gap
length. This Data is shown for the cases of 0 V and 35 V dc bias applied. We select both
conditions as they provide two trend lines from which we can estimate the capacitance
112
behavior with dimensional scaling. The plots in figure 7.4 clearly show that capacitance
values below 0.5 pF can be produced with gap lengths in the 102 µm range - a length scale
that is easy to achieve lithographically, and insensitive to µm-range limits of precision. Sub
pF values are also seen to be accessible for 2 µm gap widths, which are important for cases
where tuning voltages need minimization. We note that gap widths are small, i.e., in the
range of several microns, however this dimension can be established by a single lift-off
lithography step and not dependent on precise alignment to features on additional levels,
thus higher accuracy (with respect to a target capacitance value) can be maintained in
comparison to a 3-layer MIM approach.
Figure 7.5 Capacitance vs. gap width for planar gap capacitors prepared on BST. Data is
shown for zero volts and 35 volts dc bias applied (corresponding to the non- and fully-tuned
capacitor conditions). The b vales correspond to the y-intercepts, thus the fringe+ stray
capacitance associated with the samples and the measurement fixture.
113
At this point, it is important to note that extrapolated capacitance values at zero
length are not 0 pF. This is the first indication of the parasitic capacitor elements, and the
need to characterize their impact on voltage tunability. In both cases, zero and 35 V bias,
the data sets are fit to linear functions using least squares to extrapolate the “zero-length”
capacitance. For the fitting operation, the data points for 2000 and 4000 µm were not used.
Because it is difficult to prepare a uniform gap of 2 µm or 3 µm over a 4000 µm distance,
there is either substantial scatter in the capacitance values or insufficient number of
functional capacitors to obtain a confident average. A superior fit was achieved using the
truncated range. It is important to note that after bridge calibration (including the needle
probes used for capacitor contact) there is a constant stray capacitance of 0.01 pF. Thus,
the intercept capacitance associated with each capacitor set should be reduced by this
amount to reflect the best estimate of the fringe contribution. In all cases, the fringe
component is found to be between 50 fF and 60 fF.
This non tunable fringe capacitance contribution associated with electrode corners is
independent of electrode length and will reduce tunability as the relative BST contribution
becomes smaller. Dielectric tunability was measured by comparing capacitance values at
zero bias and ± 35 V applied dc. Tunability is defined as the ratio between the difference of
the capacitance value at zero bias to the capacitance value at 35 V as shown in equation 1.
Tun(%) =
C 0V − C 35V
× 100
C 0V
Equation (7.4.1)
Figure 7.6 shows the results of tunability measurements as a function of gap length
for capacitors with 2, 3, and 5 µm gap widths. From the data we see that capacitive
tunability is effectively saturated at gap lengths above ~ 1 mm, with a steep drop as lengths
are decreased. We note that tunability values are taken at 35 V applied, thus lower electric
fields are applied at the higher gap widths and tunability maxima are consequently lower. By
considering the data of Figures 7.5 and 7.6 for the case of a 3 µm gap we see clearly that
250 fF capacitors, a value required for the center of X-band, and approximately 200 µm in
114
length exhibit a measured tunability of ~ 25%. This represents a 40% reduction from the
reference value.
70
Tunability (∆C/C
max
)
60
50
40
30
20
2 micron gap
3 micron gap
5 micron gap
10
0
0
1000 2000 3000 4000
Gap Length (µm)
Figure 7.6 Capacitance tunability for gap capacitors as a function of gap length. Data sets
for 2, 3, and 5 µm gaps are shown simultaneously. Each data point corresponds to an
average calculated from 6 capacitors. In some cases, data points are missing; this
corresponds to sizes for which the complete sets of functional capacitors were not available.
In all cases, tunability numbers are quoted for 35V applied, thus larger values are reported
for small gap widths.
This data suggests a serious deterioration of tunability value as the capacitance
values fall below ~ 1.5 pF, or about a 1000 µm long 3 µm wide gap. This presents a
potential practical limitation to tunable ferroelectric devices operating at frequencies in the Xband and beyond. At this point it is necessary to recognize that RF measurement fixtures
contain finite stray capacitance that falsely detracts from the measured tunability. Our open
and short calibrations suggest these to be in the range of 10 fF, however, given the
implications of these findings on microwave systems, a corroborating calculation is
warranted. To verify the experimental methods, SONNET simulations were conducted for
planar capacitors with the same dimensions as those prepared in this study. The
115
calculations predict the capacitance of a gap capacitor as a function of gap length at 1 MHz.
In a manner analogous to our experiments, the calculations were extrapolated to zero length
to identify the fringe capacitance. The results of these calculations are shown in Fig. 7.7.
The extrapolation indicates a fringe capacitance of 50 fF, in excellent agreement with the
experimental findings, in particular when considering the 10 fF uncertainty in our HP4192A
impedance bridge at 1 MHz.
Capacitance @ 35V (pF)
0.20
0.15
0.10
0.05
0.00
-0.05
0
250
500
Gap Length (µm)
750
Figure 7.7 Calculated capacitance values for 3 µm wide gap capacitors as a function of
gap length. Calculations were made using SONNET circuit simulator.
The results of these experiments and calculations suggest a disconcerting limitation
to tunable microwave devices that incorporate ferroelectric varactors. The gap geometry that
is needed to achieve using practical lithographic tools fF-range capacitance values presents
an inescapable fringing capacitance that detracts from the accessible tunability. The
dielectric and its intrinsic tunability remain unchanged, but the field distribution results in
parasitic non-tunable capacitive elements in parallel. In the range of 1 pF, these elements
become significant in their impact on observable tuning. If accurate, this result should not be
limited to this work. The same treatments and extrapolations should be observable in the
literature. This aspect can be tested considering the report of Velu et al. who prepared 30
116
GHz tunable phase shifters with ferroelectric BST thin films with the composition 1:1 Ba:Sr
[180]. The films were prepared by solution deposition on sapphire substrates and their
properties are comparable to those of the BST used in this work. Velu integrated an
interdigital gap capacitor with a 1 µm gap width a gap length of approximately 45 µm, though
the interdigitated design makes direct length comparison difficult. The capacitance value of
this structure was 130 fF at zero bias. The small gap widths used by Velu allowed access to
very high bias fields and maximum tunabilities of 45%. However, for comparison, we use the
measured tunability of 25% at 17 V/µm, our maximum field for a 2 µm gap capacitor. Figure
7.8 shows the capacitance and tunability vs. gap length for lengths below 50 µm. In the
present case, a capacitance value of 130 fF would be achieved at a gap length of ~ 75 µm.
This longer distance in comparison to Velu is consistent with the wider gap. Our 1 MHz
measurements predict a tunability of ~ 20% when the fringing capacitance it taken into
consideration. Given the measurement uncertainty , the current values and those reported
by Velu are in remarkable agreement and validate the trends and their explanations.
Figure 7.8 Capacitance and tunability at 35V applied of a 2 µm gap capacitor as a function
of length between 50 µm and 500 µm.
117
7.5
Conclusions
We demonstrate using experimental and computational approaches that fringing
fields in planar ferroelectric capacitors contribute parallel capacitive contributions that are
mostly non tunable by the application of dc fields. When these capacitors are scaled
geometrically to a size range needed for integration with X-band and Ku-band applications,
the fringe components detract substantially from the measured tunability and limit the overall
frequency tunability that can be observed in a microwave circuit element. For the case of a
simple gap capacitor with a 2 µm gap, a saturation tunability approaching 60% can be
achieved for gap lengths in the range of 1 mm. When this capacitor is scaled to 500 fF, thus
a length of ~ 250 µm, the measured tunability at 35 V bias falls by nearly 50%. These results
quantitatively explain in part the general inability of the microwave community to replicate
the degree of frequency tuning observable in the low GHz range at X-band frequencies.
Furthermore, these results demonstrate the need for alternative designs (like an inverted
planar structure) that minimize the fringing effects.
118
Chapter 8 Inverted Coplanar Capacitor
Peter G. Lam*, Zhiping Feng**, Vrinda Haridasan**, Dan Lichtenwalner*, Michael B. Steer**,
and J-P. Maria*; *North Carolina State University Department of Materials Science and
Engineering; **North Carolina State University Department of Electrical and Computer
Engineering
8.1
Abstract
The authors report a novel approach to planar capacitor design and fabrication that
overcomes the limits associated with capacitance tuning in ferroelectric varactors intended
for X and Ku-band operation. To enable this approach, we developed a process to prepare
planar gap capacitors with an inverted geometry where the biasing electrodes are buried.
We first developed a Pt bottom electrode and Ti adhesion on c-plane sapphire by electron
beam evaporation. AFM analysis indicates stability to temperatures approaching 800 °C.
Reactive ion etching with Cl-chemistry was optimized to pattern the bottom electrodes. A
high temperature sputter deposition process was optimized for BST. At temperatures above
750 °C epitaxial material was observed routinely without the need for template layers. Using
this set of synthesis capabilities, we prepared sets of planar capacitors with 3 micron gaps
using the conventional and inverted geometries. Capacitance vs. voltage analysis shows a
nearly 50% increase in tunability for a given electric field for the inverted structures These
data suggest that the inverted geometry directs more electric field into the tunable dielectric,
produced more tuning for a given voltage applied, and in turn provides an avenue for
overcoming the scaling issues that limit tunable ferroelectric devices in the X and Ku bands.
(To be published)
119
8.2
Introduction
Capacitors using a coplanar configuration allow one to achieve the low capacitance
values required for devices operating at high frequency as understood by the need to
impedance match to a 50 Ω load. The low capacitance value is attributed to the distribution
of the applied electric field in parallel across low-dielectric constant layers, i.e. air and
substrate and the high permittivity barium strontium titanate (BST) film as shown in figure
8.1. This reduction in capacitor permittivity is accompanied by a reduction in tunability as
compared to the parallel plate configuration, where the majority of the field is distributed
across the dielectric. Tunabilities as high as 10:1 have been observed for BST capacitors
using parallel plate configuration, while planar capacitors exhibit values closer to the range
of 2:1 [181].
The effect of the reduced tunability is even more severe when planar capacitors are
scaled to the sub pF range. For applications in higher microwave and millimeter wave
frequencies, the required capacitance values are typically in the range of hundreds of fF [5].
In geometries that offer such small capacitance values the fringing capacitance associated
with electrode corners and the air or low-K material that covers the capacitor gap becomes
comparable the dielectric capacitance. This effect has been investigated by Lam et al who
showed that for a simple gap capacitor with 2 µm electrode separation distance, capacitor
tunability values are reduced by 50% for a gap length of 250 µm, which provides a zero bias
capacitance of ~300 fF. This effect produces a practical limit on the frequency tunability for
devices that are intended to operate in the X and Ku bands. Lam et al. [ref this thesis]
demonstrated this limit in a 4-component filter bank that covered a frequency range between
6 GHz to 18 Ghz. In the 2 upper frequency bands, frequency tuning was substantially
smaller because of the comparatively larger parasitic fringing components to the gap
capacitors that loaded each resonator. The measured frequency tunability values were 50%
lower than the design predictions Velu et al. reported similar effects attributed to fringe
capacitance, and though not directly discussed, the generally small tuning ranges of
published results of tunable devices in the 10 GHz range suggest the widespread nature of
this issue. Fig. 8.1 shows a to-scale schematic of a gap capacitor used to load the
resonators in the combline filters fabricated by Lam et al. This is a 150 fF structure, which in
120
combination with 45 nH of inductance provides an impedance of 50 Ω at 12 GHz, the upper
boundary of the X-band. The fringing fields schematically represented in the figure 8.1
constitute a substantial component of the capacitance and are expected to reduce the
capacitance tunability sharply with respect to a longer and “saturable” structure.
Figure 8.1 Schematic to-scale illustration of a 150 fF gap capacitor similar in design to those
found in the tunable filters of Lam et al.
The ideal solution is to increase the confinement of the electric field in the dielectric
layer. Two traditional ways of achieving this effect are by increasing the tuning voltage
and/or reducing the width between the gaps, both of which effectively increase the electric
field. The tuning voltage is limited by the particular application, and for most cases a lower
tuning voltage is preferred. Reducing the gap width achieves the same effect, however, as
pointed out earlier, a smaller gap size require higher resolution tools to handle micron and
sub-micron widths, which are not necessarily cost effective for commercialization.
Furthermore, sub micron gap widths become increasingly problematic for metallization
thicknesses that approach 1 skin depth (required aspect ratios become greater than unity),
121
and the quality/uniformity of the substrate surfaces become much more important; ceramic
alumina is unlikely to be viable. As an example, Vélu et al. have shown an interdigitated
coplanar capacitor with 1 μm gap width, obtained via electron beam lithography, exhibiting a
tunability of 40% at a tuning voltage of 40V, which measures to an electric field of 400KV/cm
[180].
We propose a novel capacitor configuration that eliminates completely the air
capacitance, and reduces the relative fraction of no-tunable fringe capacitance. The basic
principle of this configuration is to reverse the metal and dielectric layers. So instead of
depositing the electrode on top of the dielectric, we propose a stack where the electrode is
first patterned on the substrate and then followed with the BST layer on top. A schematic of
the stack is shown in figure 8.2. We call this configuration a planar metal-insulator-metal
capacitor, or an inverted IDC. We note that this structure will not eliminate the fringe
capacitor elements at the electrode edges, but the amount of electric field in the BST will be
dramatically increased, thus the relative fraction of fringe will be lower. The primary
challenge associated with this configuration is an electrode-substrate combination that can
sustain the high processing temperature required to fully crystallize and densify the BST
layer.
Figure 8.2 Schematic comparison of a conventional vs. inverted planar capacitor.
122
The combination of thermal expansion mismatch, the deposition temperature
excursion, and the propensity of noble metals to hillock make this level of thermomechanical
stability challenging to achieve. A stack of platinum with a thin titanium adhesion layer is the
most commonly used metal combination for BST parallel plate capacitors. Typically this
stack is deposited by e-beam evaporation and can sustain high temperatures.
Pt/Ti
deposited by e-beam in sapphire has been known to be able to resist degradation up to
temperature of 700 ºC [182],[183].
There two challenges that must be overcome to achieve this configuration:
1. The first challenge is to pattern the coplanar capacitor in the platinum/titanium layer.
Patterning by photolithography and liftoff is not an option since the substrate is heated to
temperature above 300ºC to optimize stability of the titanium and platinum layers. It is
widely known that platinum metal is particularly challenging to etch due to its high
chemical resistance.
Wet etching requires very corrosive chemicals, such as aqua
regia, which consist a mixture of hydrochloric acid and nitric acid diluted in water [184].
In this work, a number of methods were considered for platinum etching including
reactive-ion etching (RIE), ion milling, and wet etching. An alternative approach using
lift-off from a silver hard mask is also explored.
2. The second challenge is to optimize the deposition of the BST film with lower thermal
budget that preserves the integrity of the metal layers. Our previous processes used a
lower temperature deposition and a 900 °C final anneal which Pt layers will not survive.
For this purpose we performed a series of experiments to obtain the optimum conditions
for depositing BST in sapphire with appropriate dielectric properties.
A substrate
temperature in the range of 700 °C circumvents the need for annealing after deposition
and exists within the realm of conditions that Ti/Pt can endure.
The focus of this study is mostly related to solving both of the challenges in order to
produce the planar-MIM capacitor.
The process of materials selection and synthesis
optimization are discussed in detail. Electrical property data was collected for successfully
fabricated pMIM capacitors and is compared to a number of conventionally prepared
structures. Additional work will be required to fully finish this chapter. As of now this chapter
123
is considered a work in progress, but due to the lack of time, a thorough investigation will be
shown elsewhere.
8.3
Experimental Procedure
The substrate for this application is c-plane sapphire. Sapphire was chosen instead
of ceramic alumina because of its smoother surface. Polished ceramic alumina can be
acquired with a surface roughness of ~ 25 nm rms, but the surfaces are populated with grain
boundary grooves that previous experience shows can promote Pt hillocking upon heating.
A Pt/Ti electrode stack was fabricated by electron beam evaporation in an SVT molecular
beam epitaxy (MBE) chamber. The stack consisted of a 10 nm thick titanium layer followed
with a 100 nm thick platinum layer. The deposition was done in a 1-inch diameter wafer cplane sapphire (Monocrystal PLC, Stavropol, Russia) that is miscut 4° perpendicular to the
m-plane. This miscut was chosen due to availability at the time of the experiments. Future
studies will be required to in order to assess the effect of the degree of miscut on the growth
of BST on sapphire. The substrates were pre-annealed in 1 atm of oxygen at 1100 ºC for 3
hours, using a ramp rate of 30ºC/min to achieve a surface with uniform steps.
X-Ray
diffraction of the metal stack indicated the film to be <111>-oriented platinum.
The capacitor structures were patterned using photolithography and etching following
the same photoresist and processing conditions described in chapter 4. A number of
techniques were used to pattern the platinum electrodes, however none of them gave
satisfactory results. Wet etching with diluted aqua reqia (3 parts of 37% hydrochloric acid: 1
part of 70% nitric acid: 2 parts of de-ionized water) was the most effective, despite being
very slow. The low concentration was needed to preserve the photoresist. The measured
etching rate is about 3 nm/min, and over etching of the gap width was effectively
unavoidable.
Dry etching techniques were explored subsequently.
The same photoresist was
used to mask the capacitor patterns. Ion beam milling etching was done using a simple
Kauffman source ion beam etcher (Ion Beam, Commonwealth Scientific Corporation,
Alexandria, VA). The etching was done with a flow of 3 sccm of UHF Argon, with a total
124
pressure of 5.5 x 10-4 Torr, and a power of 800 V and 10 mA. The measured etching rate
was about 7 nm/min. The sample was adhered to a cooling stage with thermal grease to
minimize temperature rise from ion collisions with the surface. Again, this step was needed
to preserve the photoresist integrity. Reactive ion etching (RIE) was done in a Trion RIE
etcher (Clearwater, FL) using a combination of 25 sccm of chlorine, Cl2, and 20 sccm of
boron trichloride, BCl3. The etching conditions used were: total pressure of 35 mTorr, ICP
power of 300 Watts, and RIE power of 100 Watts. The measured etching rate was between
7 to 8 nm/min. Both techniques were successful in etching a blanket film of platinum;
however when using photoresist as the etching mask, the high temperature of each resulted
in resist burn-in. The burn-in photoresist was hard to remove even with a long annealing
time in air at 700 ºC. The solution was to etch for a short period of time before the onset of
burn-in, typically 1 minute for RIE and 4 minutes for ion milling, and let the sample cool
down for about 5 minutes and then the same process is repeated until complete etching was
achieved.
We developed an alternative technique that was more consistent and relatively
easier to produce. This technique consisted in using a metallic lift-off mask, as opposed to a
photoresist. The sacrificial metal must meet the requirements of survivability at the Pt/Ti
deposition temperature of 300 °C and must also easy to etch using chemicals that are inert
with respect to Pt and Ti. Both of those requirements can be met using silver metal, which
we have optimized previously. The silver metal can withstand temperature up to 700 ºC
(above this range dewetting is problematic), and can be easily etched using a number of
mild acids as discussed in chapter 5. A combination of photolithography and etching was
used to pattern the silver lift off mask, and was followed by the deposition of the Pt/Ti stack.
Then a liftoff process was used to define the capacitor structures. A schematic of the
process flow used is shown in figure 8.3.
125
Figure 8.3 Process flow for the liftoff of Pt/Ti stack using a silver hard mask. 1. First a blanket of
silver in sputtered on top of the substrate, 2. followed by the patterning of the silver by
photolithography and 3-4. liftoff 5. then the Pt/Ti stack is deposited and patterned 6. Using a
commercial etching solution CR-7purchased from Cyantek (Fremont, CA).
In parallel to the Pt patterning effort, a process for elevated temperature sputtering of
Ba0.7Sr0.3TiO3
films
on 430-μm-thick
c-plane polished
miscut
sapphire
substrate
(Monocrystal, Russia) was developed. Prior to deposition, the substrates were pre-annealed
in 1 atm of oxygen at 1100 °C for three hours and then rinsed with a combination of acetone
and methanol. Since the BST is grown on bare sapphire between the electrode gaps, the
substrate pretreatments were identical for the growth optimization. The substrate was then
loaded into the chamber and heated up to the desired temperature with a ramp rate of 10°C
per minute, monitored with a pyrometer (Raytek, Santa Cruz, CA) and a thermocouple,
before deposition.
Sputter deposition was performed with a power density of about 1
Watt/cm2, which resulted in a deposition rate of about 1.7 nm/min. The films were deposited
at pressure of 10 mTorr, with a flow rate of 20 sccm of Argon. Those conditions were
identified and optimized by Losego to obtain epitaxially grown BST in previous investigations
[185].
A series of films were deposited with varying deposition temperature and film
thickness. After deposition, the film was cool down to room temperature at a rate of 3°C per
minute. Film crystallinity was characterized by X-ray diffraction (XRD). The planar surface
126
capacitors were patterned using photolithography and liftoff. The capacitor layout consisted
of interdigitated fingers and simple gap capacitors.
The electrical characterization tests were performed using a Hewlett Packard 4192A
LF Impedance Analyzer for the capacitance-voltage (CV) and the capacitance- temperature
(CT) measurements. The current-voltage measurements were done using a Keithley 617
programmable electrometer. CV measurements were collected between –35V to 35V, in
steps of 0.5V, at 1 MHz with an oscillator of 0.05 V. For the CT measurements, the sample
is placed on a commercial miniature sample heater (MMR Tech. Inc., California), and heated
to 235°C in rough vacuum. Capacitance values were taken as the sample cooled down to 173°C at a rate of 5°C per minute. For the current-voltage measurements, a voltage sweep
was applied from -50 V to 50 V, in increments of 0.25V, with a pre-test relaxation time of 10
seconds and a delay time of 2 seconds between measurement points, and averaged over
ten points.
Permittivity values are more useful to make meaningful comparisons between
samples. However, unlike MIM capacitors, the calculation of the permittivity is not
straightforward. There are several methods available to calculate the permittivity of planar
capacitors, for our case the permittivity was extracted using conformal mapping and partial
capacitance techniques [186-188].
8.4
8.4.1
Results and Discussion
Platinum Annealing
A series of Pt/Ti films deposited on sapphire were annealed at different temperatures
up to 800ºC in air for 1 hr and ramp rate of 10 ºC/min, the same excursion used for
deposition of BST, to ensure the chemical and mechanical integrity of the films. Initial
optical inspections of the films annealed up to 800ºC did not reveal evidence of delamination
or any other mechanical failures. AFM analysis of the electrodes shows complete stability
up to 500ºC. After exposure to 800ºC, the films start showing signs of roughening and
coarsening as illustrated in figure 8.4. The measured RMS roughness of the as-deposited
platinum film is about 3.45 nm. The RMS value decreased to a value of 1.86 nm at 600ºC
127
and increased back up to 4.22 nm at 800ºC. This indicates a relaxation of the platinum film
when annealed to temperature up to 600ºC. This result is consistent with previous finding
that at temperatures above 600ºC Pt surfaces become rough, and are associated with the
onset of hillocking [189]. The highest peak values, associated with hillocks for the sample
annealed at 800 °C, were about 20 nm.
Hillocks are considered detrimental for MIM
capacitor configuration due to shorting as the hillocks bridge the gap between the
electrodes. In our case the growth direction of the hillocks is orthogonal to the gap, so their
formation is less problematic. The stability identified in these Pt/Ti electrode stacks appears
to be consistent with the engineering requirements of these pMIM structures.
Figure 8.4 AFM images of Pt/Ti stacks prepared on miscut c-plane sapphire after deposition
and exposure to increasingly high temperatures. Though some hillocking is observed at 800
°C, the bulk of the electrode remains stable and is provides the thermomechanical stability
needed for pMIM structures. The scale bar, to the right, represents 40 nm for the as deposited
Pt, 26 nm for the Pt annealed at 500 °C, and 70 nm for the Pt annealed at 800 °C.
X-Ray diffraction analysis of the platinum film annealed at 800ºC does not show any
additional peaks besides the Pt (111) peak, which indicates the absence of any second
phases.
128
Figure 8.5 X-ray diffraction analysis of Pt electrodes as deposited and after exposure to 800
°C. Relative peak intensity and orientation are constant.
8.4.2
BST Growth
BST sputtering on sapphire was optimized with a series of experiments with varying
deposition temperature.
X-Ray diffraction analysis of the films grown as a function of
temperature show a transition from polycrystalline to epitaxial crystal between 700 °C and
750 °C. So at temperature of 750ºC the BST films appear fully epitaxial, the high deposition
temperatures combined with the slow deposition rate (as compared to deposition on ceramic
alumina) allow for sufficient surface diffusion and growth of the substrate-defined orientation
[104]. From the perspective of our capacitor application, epitaxial material is preferred as it
generally provides the optimally dense microstructure. Consequently, we define 770 °C as
our target deposition temperature. 20 °C higher than the temperature onset of epitaxial
growth and 80 °C below the stability limit of Pt electrodes. The morphology of the epitaxial
BST film shows wormlike structures, as shown in figure 8.7.
129
Figure 8.6 X-ray diffraction analysis for BST films grown on bare sapphire. The set of data
illustrates that epitaxial material grows initially at 600 °C, but temperatures between 700 °C
and 750 °C are needed to eliminate all non-epitaxial orientations.
There are a number studies of epitaxial barium titanate and barium strontium titanate
thin film grown on single crystals, primarily substrates like SrTiO3, LaAlO3, and DyScO3
[84],[190],[191]. As these studies are motivated primarily by the concept of strain
engineering ferroelectric properties, cubic, and preferably perovskite structures are
preferred. However, to the best of knowledge of the authors, there are only a few number of
studies
reported
on
growth
of
epitaxial
barium
strontium
titanate
in
sapphire
[114],[115],[118], and those reports suggest either difficulty or inability to achieve epitaxy
between BST and c-plane sapphire.
130
Figure 8.7 SEM image of 200 nm and 800 nm thick 111-oriented BST epitaxial film on sapphire.
The impact of substrate steps is reflected in the surface microstructure at 200 nm, but
completely randomized at 800 nm.
Yamada and coworkers have reported an epitaxial growth of Ba0.3Sr0.7TiO3, by
magnetron sputtering, thin film on c-cut sapphire using a 0.9 nm thick titanium nitride layer
as a sacrificial template layer. According to Yamada the presence of the sacrificial layer
contributed to the enhancement of the permittivity and tunability of the dielectric [118]. It is
interesting to note that provided sufficient temperature, BST films were readily and
reproducibly grown by RF magnetron sputtering.
To ensure an appropriate basis for capacitor comparison, the BST dielectric
properties on sapphire were characterized as a function of film thickness. We know from the
work of Ghosh et al.[144] shows that tunability depends on film thickness because of an
increasing field concentration in the tunable dielectric in planar geometry. The manifestation
of this effect on sapphire is necessary to know and to compare with ceramic alumina. We
note that investigations of sputtering temperature are not included in this work. It is clear that
the nonlinear dielectric properties of BST and other ferroelectrics improve with crystal
quality, which improves with temperature. As such, we utilize the highest temperature that
our substrate/electrode stack can tolerate.
131
8.4.3 Dielectric Properties of Epitaxial BST
A series of films were grown with different thickness, from 100 nm to 1200 nm. As
shown in the X-Ray plot, single orientation epitaxial BST films with (111) orientation is
observed up to a thickness of 600 nm. Films with higher thickness start to show additional
BST orientations.
This effect can be explained by the fact that with thicker films the
“memory” of the sapphire is reduced, and due to the large lattice mismatch which causes a
strong structural mosaicity, the accumulation of growth defects eventually leads to random
nucleation events.
Figure 8.8 X-ray diffraction analysis for epitaxial BST films spanning a thickness range between
100 and 1200 nm.
Optical observations of the films at different thickness show cracking, with the onset
occurring between 200 nm and 300 nm, as shown in figure 8.9. The formation of cracks can
be attributed to a catastrophic film relaxation during growth due to the accumulation of strain
energy arising from the lattice mismatch between the film and the substrate and also to the
mismatch of the coefficient of thermal expansion, CTE, between the film and the substrate,
during the cooldown. In the case of BST films deposited on polycrystalline alumina
substrates, the onset of cracking occurs at about 1 micron [144]. Yamada et al. speculates
132
that the lattice mismatch for BST 111 deposited on c-plane sapphire is about 1 % [118].
The CTE mismatch between the BST and the alumina substrate is about 2 ppm, and
between BST and sapphire is about 4 ppm. Sapphire has a strongly anisotropic CTE, ~2
ppm smaller parallel in the c-plane as opposed to the perpendicular direction. In ceramic
alumina, the anisotropy is directionally averaged, and the net thermal expansion coefficient
takes an intermediate value. The average CTE mismatch with BST is smaller, and the onset
of cracking occurs at larger thicknesses. The larger CTE of BST (about 10 in the
temperature range of interest) results in tensile strain upon cooling from the deposition
temperature, and the “crazed” network of cracks visible to optical microscopy. The CTE
values for both of the substrates are shown in table 8.1.
Figure 8.9 Optical microscope images of epitaxial BST thin film surfaces collected as a
function of film thickness. The onset of crack formation occurs between 200 nm and 300 nm.
Table 8-1THERMAL EXPANSION COEFFICIENTS OF SUBSTRATE AND THIN FILM MATERIALS.
Substrate
BST
Ceramic alumina
Sapphire (parallel to the c-plane)
Coefficient of thermal expansion
-6
10.5 ×10
-6
8.8×10
-6
8.0×10
133
Since the crack orientation is perpendicular to the electrode gap, electrical
measurements can still be made in their presence. A summary of tunability at 100 kV/cm for
the thickness series of epitaxial BST capacitors is shown in Figure 8.10. The onset of
cracking does not seem to have a pronounced effect on the dielectric properties of the film,
but given the very low onset thickness, where very little field is in the BST, a dramatic effect
may not be expected. In general, the expected trend of increasing capacitance with
thickness is observed, but the maximum tunability is lower than for the case of ceramic
alumina, and there is considerable scatter.
The low tunability is explicable by the
contribution of cracks, which should behave as a second phase with a permittivity of unity.
For comparison, the tunability of BST on alumina at 450 nm dielectric thickness and a 3 µm
gap with 100 kV/cm applied dc bias is routinely ~ 30%. Thus the epitaxial materials exhibit
substantially lower nonlinearity. The data points for 500 nm and 1000 nm epitaxial BST
exhibit dramatically higher tuning. It needs to be noted that these samples has gap widths ~
2 µm. The smaller gap width (despite approximate field normalization, i.e., 100 kV/unit
length of gap) is responsible for this increase.
Figure 8.10 Thickness dependence of capacitance and tunability for planar epitaxial BST
capacitors.
134
The relative quality of these materials can be evaluated by the temperature
dependence of the permittivity. Generally speaking, the transition temperature between
ferroelectric and paraelectric phases and the relative width of the transition are excellent
indicators that are in general independent of geometric factors. As such, they can be used
as independent indicators of film quality. Figure 8.11 shows the temperature dependent
capacitance for the thickness series. The data are normalized against the maximum
capacitance at the phase transition. All temperature dependencies are similar suggesting
dielectric properties that are not strong functions of thickness and that the variability
observed in tuning is attributable to variations in gap width. The 500 nm sample has a
slightly less diffuse transition, but this again is attributed to the smaller gap that increases
the oscillator electric field used during capacitance measurement.
Consequent to this analysis we identify the ability to prepare epitaxial BST thin films
on sapphire using synthesis conditions that are consistent with the temperature tolerance
limits of our Pt/Ti substrate stack. The BST films are populated with thermal expansion
mismatch induced cracks that detract from both capacitance and tunability, however, the
dielectric properties are sufficient to go forward and test the ability to prepare inverted planar
capacitors and to determine if there is an advantage to the proposed geometry associated
with larger observable tunabilities.
135
Figure 8.11 Temperature dependence of the capacitance for the thickness series of epitaxial
BST thin films prepared on sapphire substrates.
8.4.4 Inverted Planar Capacitor Synthesis
Upon optimization of epitaxial BST film in sapphire, the next focus is to process the
coplanar MIM capacitor. A number of attempts were made at preparing pMIM structures
using each of the electrode patterning methodologies discussed in the experimental section.
In all cases fabrication was successful and the electrical property data was similar for all
cases. The reactive ion etching technique with Cl chemistry was provided the most
consistent results and greatest ease of process. The electrical and structural data discussed
below corresponds to structures fabricated using RIE patterned electrodes.
The BST was deposited at the optimum temperature found for epitaxial deposition in
sapphire, 770°C, and deposited to a thickness of 500 nm, using the standard heating and
cooling rate. The thickness was chosen to be consistent with the thickness of BST typically
grown in alumina substrate. A photolithography and etching combination (1% HF) was used
to open “windows” through the BST allowing probe access to the platinum bottom electrode
and measurement of capacitor properties. To make the optimal comparison, we choose high
capacitance interdigitated structures with a large electrode perimeter, and to the extent
136
possible, we produced capacitors with identical planar geometry and a 3 µm electrode
spacing. Figure 8.12 shows capacitance data vs. voltage for the conventional and inverted
structures. The data is presented as total capacitance vs. voltage and relative capacitance
vs. voltage to highlight the comparison.
Figure 8.12 Capacitance vs. voltage for conventional interdigitated and inverted
interdigitated capacitors. The plots show total and relative capacitance for both
geometries.
137
The data in Fig. 8.12 clearly show the substantial improvement by utilizing the
inverted architecture. Since the dielectric is effectively unchanged, the roughly 50%
improvement in tunability can be attributed to the distribution of the electric field. We note
that the dielectric in the inverted structure is cracked (as shown in Fig. 8.9). Consequently,
the full benefit of the inverted geometry remains untapped. When the cracking issue is
overcome, the difference in performance should be more dramatic still. The ultimate
tunability for this geometry should approach that of a MIM capacitor which is about 90%
[192], but since a fraction of the field goes through the substrate a lesser value is expected.
It is, however, difficult to make an objective estimation of the ultimate tunability value of this
capacitor, and for that further experiments and optimization are required.
Transmission electron microscopy analysis was performed on the film in order to
assess the integrity of the electrode and dielectric layers after deposition. The TEM sample
was prepared using focused-ion beam milling at the Analytical Instrumentation facility (AIF)
at NCSU. The TEM analysis was collected using a JEOL 2000FX TEM. Fig. 8.13 gives a low
magnification image of the entire structure. The TEM image is taken from a perspective
parallel to the electrode fingers. White arrows indicate the electrode edges that define the
capacitor gap. From this image, the 3 micron electrode spacing is confirmed.
Figure 8.13 Cross sectional TEM image of inverted planar capacitor.
The TEM image in Fig. 8.13 shows that the BST grows with a columnar
microstructure as expected. However, the volume of material within the capacitor gap is too
small to detect using x-ray diffraction. It is important to know if the epitaxial orientation seen
138
on normal sapphire is preserved. The wide field TEM image shows a rough interface,
presumably from reactive ion etching damage, and it is a concern as to the impact of this
modification on BST dielectric properties. Selected area diffraction was conducted on the
BST between the metal electrodes to identify the orientation, the results are shown in Figure
8.14. The diffraction pattern and its analysis reveal a <111> BST orientation parallel to the
sapphire c-plane. Figure 8.15 shows a higher magnification image of the BST/Sapphire
interface. From this image the extent of surface modification is evident. In some areas, the
removal of substrate material extends several tens of nanometers below the original
surface.
Figure 8.14 Selected area diffraction image and pattern for the BST and sapphire substrate.
Indexing the diffraction pattern shown in the upper left indicates epitaxial registration with
sapphire substrate, however, there is substantial mosaic spread.
In Figure 8.16 an even higher resolution image is shown. Examination of this image
reveals the presence of what appear to be second phase particles on the order of 10 nm in
diameter. From previous results [Ghosh [144]] and published phase equilibria, we know that
139
BST and alumina will react at temperatures above 950 °C. This sample, however, never
experienced those conditions. We speculate that surface modification from RIE processing
resulted in a substoichiometric surface condition that is substantially more reactive than a
pristine sapphire surface. Consequently, reactions producing second phases occurred
during BST synthesis. The impact of these phases is not known, but with near certainty, it
cannot be a desirable effect. Perhaps more sophisticated patterning and etch stopping
methods are needed to preserve a more ideal growth surface.
Figure 8.15 Medium resolution TEM image of the interdigitated electrode edge. The partial
consumption of the sapphire substrate is apparent at this magnification.
Figure 8.16 High-resolution image of the BST sapphire interface. The presence of precipitate
particles at the reactive interface is apparent.
140
Another final benefit of using coplanar MIM capacitor is that the dielectric can
function as both the tunable material and as a passivating layer covering the
electrode/dielectric interface with the potential to, increase device reliability. Kuperschmidt
has shown that reducing the IDC gap width, hence increasing the electric field, results in a
decrease of capacitor reliability and hence lifetime. Our initial measurements suggest this to
be the case. Inverted capacitors were exposed to 100 V (across a three µm gap) and left in
that condition overnight. Comparison of C-V curves collected before and after this voltage
application are unchanged with respect to both capacitance and loss tangent. When similar
tests are performed for conventional structures, breakdown always occurs, apparently
following a surface mechanism.
8.5
Conclusions
The authors developed a process flow for preparing planar gap capacitors with an
inverted geometry featuring buried biasing electrodes. The process requires a robust Pt
bottom electrode and Ti adhesion layer that can withstand a temperature excursion
consistent with BST deposition. In this case, such electrodes were prepared c-plane
sapphire by electron beam evaporation. AFM analysis indicates stability to temperatures as
high as 800 °C. Three electrode etching strategies were explored for patterning the Pt/Ti
electrode stack: ion beam etching, reactive ion etching with Cl-chemistry, and hard mask lift
off. Of the three, RIE provided the best results. A high temperature sputter deposition
process was optimized for BST. At temperatures above 750 °C epitaxial material was
observed routinely. The epitaxial structure could be preserved to thicknesses approaching 1
µm, above which random nucleation events were detected by X-ray diffraction. In this study
epitaxial material was not required, but occurs naturally without the need for template layers.
Electrical property analysis indicates that the epitaxial BST, despite a thermal expansion
mismatch induced cracking issue, performs similarly to material prepared on ceramic
alumina. Sets of planar capacitors were prepared with 3 micron gaps using the conventional
and inverted geometries. Capacitance vs. voltage analysis shows a nearly 50% increase in
tunability for a given electric field, even in the presence of BST cracks. Collectively these
141
data suggest that the inverted geometry directs more electric field into the tunable dielectric,
produced more tuning for a given voltage applied, and in turn provides an avenue for
overcoming the scaling issues that limit tunable ferroelectric devices in the X and Ku bands.
If additional engineering improvements are applied to overcome cracking and etching
issues, the full benefit of this approach will be realized.
142
Chapter 9 Conclusions and Future Work
9.1
Conclusions
This research addresses material engineering issues related to the integration of
ferroelectric thin films for microwave tunable devices. This thesis presents several innovative
technical contributions to the improvement of BST-based microwave bandpass filters. The
work presented in here demonstrates a processing methodology using conventional
technologies and low cost materials. A study of the tunability limitation of conventional
coplanar capacitor was conducted and a novel capacitor configuration is proposed.
A
summary of the thesis outcomes is listed below:
•
The use of filled through-hole for grounding to the back plane was demonstrated.
The use of filled vias solved several integrating issues, and improved the overall
performance of the devices.
•
The use of a two-step metallization process mitigated photolithographic issues
associated with uneven developing of the low-resolution patterns and the gap
capacitors.
•
RF sputtered silver thin film was optimized to provide both low resistivity, in the order
of the bulk value, and complete adhesion without employing an intermediate
adhesion layer. Electromigration of the silver in the vicinity of the gap capacitor was
identified as the source of low reliability in the devices. Employing Cr/Au layer for the
biasing of the gap capacitor solved this issue.
•
A complete bandpass filter array in the frequency range of 6 to 12 GHz was
demonstrated. The performance of the devices was within the design range.
•
Fringe capacitance was identified as the culprit for low microwave tunability values in
bandpass filter for frequencies above 13 GHz. The value of the fringe capacitance
was measured to be about 70fF for gap capacitors. Accompanying Sonnet
simulations support this result.
143
•
A coplanar MIM capacitor configuration is proposed to increase the tunability of BSTbased capacitors. Several processing issues were identified with this configuration,
and pertinent solutions are demonstrated. A novel technique using a silver hard
mask was proposed for patterning platinum electrodes.
•
Key parameters for epitaxial deposition of BST in c-plane sapphire were identified.
Electrical characterization of capacitors in epitaxial BST showed results comparable
to those found in BST deposited in alumina.
•
Finally a coplanar interdigitated MIM capacitor was demonstrated. The novel
configuration showed tunability values higher than traditional capacitor fabricated in
polycrystalline alumina substrate.
9.2
Future Work
The most immediate attention should be given to the fabrication and optimization of
coplanar MIM capacitors. Several issues need to be solved including the optimization of
platinum patterning, and mitigation of the crack in the BST. Potential solutions to the latter
issue should include the use of alternative substrates with a CTE closer to that of the BST,
such as SrTiO3 or ZrO2.
After optimizing the fabrication of coplanar MIM capacitor, the next step should be a
thorough reliability study on the new capacitor configuration. Successful application of this
new configuration could become a significant breakthrough in increasing the reliability of
microwave devices.
The fringe capacitance associated with gap capacitors is due mostly to the
geometrical configuration of the electrode. Alternative geometric configurations should be
investigated to elucidate the link to the geometry (for example, whether sharp corners
contribute more than round corners) of the capacitor and identify easier solutions to mitigate
this effect. This study can also provide the necessary data so the fringe capacitance can be
modeled based on the geometry of the capacitor.
144
Due to the inaccuracy of present models used to determine the capacitance values
for coplanar capacitor and to the high complexity of the system, it is difficult to make a
judgment on the impact of the quality of the material on the tunability of the capacitor. A
comprehensive study is required to elucidate this question, and provide an answer as to the
degree of BST optimization required before any improvement is obtained due to the
limitation of the geometry.
145
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