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Silicon -on -sapphire technology for microwave power applications

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UNIVERSITY OF CALIFORNIA, SAN DIEGO
Silicon-onrSapphire Technology
for M icrowave Power Applications
A dissertation submitted in partial satisfaction o f the
requirements for the degree Doctor o f Philosophy
in Electrical Engineering (Applied Physics)
by
Matthew A. Wetzel
Committee in charge:
Professor Peter M. Asbeck, Chair
Professor John E. Crowell
Professor Frances Heilman
Professor Lawrence E. Larson
Professor S.S. Lau
2001
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UMI Number: 9997569
Copyright 2001 by
Wetzel, Matthew Arthur
All rights reserved.
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Copyright ©
Matthew Wetzel, 2001
All rights reserved
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The dissertation o f M atthew Wetzel is
approved, and it is acceptable in quality and
form for publication on microfilm:
Chair
University o f California, San Diego
2001
iii
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To m y parents, who have taught m e m ore
than I can put into words. And to m y
wife for her love and support.
iv
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Table of Contents
Signature P age..............................................................................................................iii
Dedication...................................................................................................................... iv
Table o f Contents......................................................................................................... v
List o f Figures...............................................................................................................ix
List of Tables................................................................................................................. xvii
Acknowledgements...................................................................................................... xviii
Vita
............................................................................................................................. xxiii
Publications................................................................................................................... xxiii
A bstract..........................................................................................................................xxiv
1
INTRODUCTION...............................................................................................1
1.1 Motivation..............................................................................................................1
1.2 CMOS Scaling...................................................................................................... 3
1.3 SOS versus Bulk Silicon...................................................................................... 6
1.4 Large Periphery M OSFETs................................................................................. 15
1.5 Scope o f Dissertation............................................................................................18
1.6 References..............................................................................................................20
2
HIGH FREQUENCY DIGITAL CM OS........................................................23
2.1
Introduction............................................................................................................23
2.2 Scaled CMOS Technology................................................................................... 24
2.3
Frequency Divider Circuit Design...................................................................... 26
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2.4
Measurement Results and Analysis....................................................................32
2.5
Estimated Performance o f SOS MOSFET Circuits...........................................36
2.6
Conclusions for Chapter 2 ................................................................................... 37
2.7
References..................................
2.8
Acknowledgements...............................................................................................39
3
LARGEFET DEVICE DESIGN AND C H A R A C T ER ISTIC S.................40
3.1
Introduction............................................................................................................40
3.2
Large Device Design Considerations..................................................................41
3.3
Device Design....................................................................................................... 46
38
3.3.1 Standard Layout.................................................................................................... 47
3.3.2 Waffle Layout....................................................................................................... 48
3.3.3 Spaceship Layout.................................................................................................. 51
3.4
RF M easurements................................................................................................. 53
3.4.1 Measurement approach........................................................................................ 53
3.4.2 Results.................................................................................................................... 54
3.5
Conclusions for Chapter 3 ...................................................................................56
3.6
References..............................................................................................................56
3.7
Acknowledgements...............................................................................................57
4
THERM AL M O D ELIN G O F CMOS ON S A P P H IR E ..............................58
4.1
Introduction............................................................................................................58
4.2
Effects o f S elf-Heating........................................................................................ 59
4.3
Evidence o f Self-Heating in S O S ....................................................................... 62
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4.4
Comparison o f SOI and SOS Thermal R esistance............................................ 67
4.5
Thermal Resistance o f S O S .................................................................................. 71
4.5.1 Simulation............................................................................................................... 71
4.5.2 Measurement o f Thermal Resistance...................................................................75
4.6
Temperature Dependence o f SOS M O SFETs....................................................79
4.7
SOS Device Characteristics.................................................................................. 82
4.7.1 DC Measurements.................................................................................................. 82
4.7.2 AC Measurements.................................................................................................. 85
4.8
Conclusions for Chapter 4 .................................................................................... 88
4.9
References............................................................................................................... 89
5
LARGE FET ANALYSIS.................................................................................. 91
5.1
Introduction.............................................................................................................91
5.2
Determination of Frnax............................................................................................92
5.3
Composite Model................................................................................................... 94
5.3.1 Device Technology................................................................................................ 94
5.3.2 Detailed M odeling................................................................................................. 95
5.3.3 Simplified Lumped Element Model..................................................................... 100
5.3.4 Discussion............................................................................................................... 104
5.4
Distributed M odel.................................................................................................. 108
5.4.1 Device Technology................................................................................................ 109
5.4.2 Problem Setup and Solution................................................................................. I l l
5.4.3 Model Verification................................................................................................. 114
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5.5 Analysis o f Transmission Line M odel............................................................... 126
5.5.1 Wave Propagation............................................................................................... 126
5.5.2 Simulated structures............................................................................................ 134
5.5.2.1
Gate and Drain on Same S ide........................................................................135
5.5.2.2 Multiple Probe P ad s........................................................................................137
5.6
Conclusions for Chapter 5 .................................................................................. 139
5.7
References............................................................................................................. 140
5.8
Acknowledgements.............................................................................................. 140
6
POWER AM PLIFIER............................................................. ......................... 142
6.1
Introduction........................................................................................................... 142
6.2
Effects o f Scaling on Power Am plifiers............................................................ 143
6.3
Class A and B Amplifier Operation....................................................................146
6.4
Design and Implementation................................................................................ 151
6.5
Experimental R esults........................................................................................... 158
6.6
Discussion............................................................................................................. 167
6.7
Conclusions for Chapter 6 ...................................................................................173
6.8
References............................................................................................................. 174
7
CONCLUSIONS AND FUTURE W ORK.....................................................176
7.1
Summary o f Dissertation.....................................................................................176
7.2
Future W ork.......................................................................................................... 178
Appendix A. Distributed Calculation of Large FET Small Signal Parameter 182
Appendix B. Circuit Board Characterization........................................................191
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List of Figures
Figure 1-1. Cross-sections o f NMOS and PMOS transistors on bulk silicon and SOS
showing (A) latch-up model for bulk silicon, (B) parasitic capacitances for bulk
silicon, (C) thin film silicon-on-sapphire............... k................................................... 8
Figure 1-2. Depletion charge for long and short channel MOSFETs in (A) bulk silicon
and (B) SOS technology..............................................................................................11
Figure 1-3. Impact ionization in channel region in (A) bulk silicon results in substrate
currents while in (B) SOS results in charge build-up underneath channel, lower
the threshold voltage.................................................................................................... 13
Figure 1-4. Simulated DC curve showing kink effect o f partially depleted device.... 13
Figure 1-5. Measured data from NMOS 0.5pm x 120pm device.
is varied from
0V to 3.5V..................................................................................................................... 14
Figure 1-6. Cutoff frequency, f t, versus gate width for different layout strategies
17
Figure 1-7. Maximum oscillation frequency, fmax, versus gate width for different
layout strategies............................................................................................................ 17
Figure 2-1. Ft and Fjnax o f NMOS device. (Data courtesy o f Keith Jenkins at IBM T J.
Watson Research Center)............................................................................................ 25
Figure 2-2. DC characteristics o f 0.1x20pm NMOS device.......................................... 26
Figure 2-3. DC Characteristics o f 0.1x20pm PMOS device..........................................26
Figure 2-4. Operation o f 2:1 frequency divider circuit....................................................28
Figure 2-5. Circuit schematic o f frequency divider circuit. Latching stage enclosed
with dashed boxes........................................................................................................ 29
Figure 2-6. Die Photograph o f frequency divider circuit................................................30
Figure 2-7. Rise time o f output voltage for different WL to W R ratios with a large
capacitive load.............................................................................................................. 31
Figure 2-8. Test setup for frequency divider...................................................................33
Figure 2-9. Minimum single-ended input power required by circuit............................ 34
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Figure 2-10. DC power consumed by output buffer (top) and by logic core plus
current sources (bottom )............................................................................................... 35
Figure 2-11. Input (top) and output (bottom) waveforms with clock o f 26.5GHz.......35
Figure 2-12. Estimated node capacitance in frequency divider flip-flop........................37
Figure 3-1. Small signal model o f a MOSFET................................................................. 42
Figure 3-2. Simplified schematic o f transistor layout showing delay that can cause
destructive power combining........................................................................................44
Figure 3-3. Power lost from combining two sine waves that are out o f phase............. 44
Figure 3-4. Standard layout. Left: diagram of interconnect strategy. Right: Die
photograph o f standard device with 4400pm effective gate width.......................... 48
Figure 3-5. Waffle Layout. Left: diagram o f interconnect strategy. Right: die
photograph o f waffle device with 4320pm effective gate width.............................. 50
Figure 3-6. Spaceship layout. Left: Diagram o f interconnect strategy. Right: Die
photograph o f spaceship device with 2400pm effective gate w idth........................ 52
Figure 3-7. Left: 3600pm spaceship transistor with gate feeding from the middle.
Right: 3900pm spaceship transistor with gate feeding from the sides................... 53
Figure 3-8. F t and Fmax versus gate width for NMOS devices. Measured with
Vds=Vgs=2.0 Volts........................................................................................................55
Figure 3-9. Ft and Fm& versus gate width for PMOS devices. Measured with
Vds=Vgs—2.5 Volts...................................................................................................... 55
Figure 4-1. Simulated MOSFET I-V curves with and without self-heating (thermal
resistance is 300W/K)....................................................................................................60
Figure 4-2. Simulated Ft versus temperature for silicon MOSFET................................60
Figure 4-3. Current density comparison for 100pm, 600pm, 2400pm, and 4400pm
NMOS standard layout transistors (data corrected for series resistance in
measurement setup)........................................................................................................63
Figure 4-4. Current density comparison for 240pm, 620pm, 4160pm and 4320pm
NMOS waffle layout transistors (data corrected for series resistance in
measurement setup)........................................................................................................64
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Figure 4-5. Current density comparison for 2400pm, 3600pm, and 3900pm NMOS
spaceship layout transistor (data corrected for series resistance in measurement
setup)...............................................................................................................................64
Figure 4-6. Normalized drain current for standard NMOS layouts o f 100pm, 600pm,
2400pm and 4400pm. No correction made for voltage drop in measurement
setup................................................................................................................................ 66
Figure 4-7. Normalized drain current for standard NMOS layouts o f 100pm, 600pm,
2400pm and 4400pm. Voltages corrected for voltage drop in measurement setup.67
Figure 4-8. Representative layer structures used for SOI and SOS MOSFETs. Top
oxide layer is representative of interlevel dielectrics or passivation....................... 68
Figure 4-9. SOI and SOS thermal resistance assuming uniform power dissipation in
cube with cross-section o f 1cm2...................................................................................68
Figure 4-10. Comparison o f simple calculation and simulation o f SOI and SOS
thermal resistance for a 0.35pm x 25pm MOSFET...................................................69
Figure 4-11. Top view o f simulated device structures. All gates are 0.35pm x 50um.
(a) 100pm gate width device, (b) 600pm gate width............................................... 73
Figure 4-12. Simulated thermal resistance for 100pm, 600pm, and 2400pm standard
layout. Compared with ideal scaling o f thermal resistance from the 100pm
device.............................................................................................................................. 75
Figure 4-13. Liquid crystal measurement setup with cross-polarized lenses and
thermal plate...................................................................................................................77
Figure 4-14. Measured and simulated thermal resistance. Simulation shown with
open symbols, measurements with filled symbols.....................................................78
Figure 4-15. Measured and interpolated threshold voltage versus temperature for
0.35pm x 100pm NMOS SOS device.........................................................................80
Figure 4-16. Measured and predicted saturation current versus temperature for
0.35pm x 100pm NMOS SOS device.........................................................................81
Figure 4-17. Measured and predicted f t versus temperature for 0.35pm x 100pm
NMOS SOS device........................................................................................................82
Figure 4-18. DC current density o f standard layout NMOS SOS device after
correction for self-heating.............................................................................................83
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Figure 4-19. DC current density o f waffle layout NMOS SOS device after correction
for self-heating.............................................................................................................. 84
Figure 4-20. DC current density o f waffle layout NMOS SOS device after correction
for self-heating.............................................................................................................. 84
Figure 4-21. Comparison o f measured thermal resistance (open symbols) and thermal
resistance used to correct for self-heating effects (solid symbols)...........................85
Figure 4-22. DC current density for SOS NMOS devices. Measurement not corrected
for resistance in setup....................................................................................................86
Figure 4-23. DC current density for SOS NMOS devices derived from the AC
conductance technique.................................................................................................. 86
Figure 4-24. Ft and Fmax measured at a constant device temperature o f 100°C for
standard layout NMOS transistors.............................................................................. 88
Figure 5-1. MAG/MSG and unilateral gain versus frequency for 0.5pm x 120pm SOS
MOFET (fabricated by Peregrine).............................................................................. 93
Figure 5-2. Cross-section o f device fabricated at SSC San Diego. Device has metal
T-gate to reduce gate resistance and 0.35pm effective gate length......................... 95
Figure 5-3. Composite model of3900pm wide spaceship layout..................................97
Figure 5-4. Layout of3900pm spaceship device.............................................................98
Figure 5-5. Simulated and m easured^ and /max versus gate width for the spaceship
style layouts................................................................................................................... 99
Figure 5-6. Measured H21 (current gain) and theoretical prediction.
measured H21 increases with increasing frequency, resulting in lowerf
Slope of
100
Figure 5-7. Model o f transistor output with transmission line on drain.......................101
Figure 5-8. Measured and modeled H 2 1 for a 2400pm wide device............................ 103
Figure 5-9. Measured (solid) and modeled (open) H21 for 2400pm spaceship style
FET............................................................................................................................... 105
Figure 5-10. Measured (solid) and modeled (open) power gain (MAG/MSG and
unilateral gain) for 2400pm spaceship style FET.................................................... 106
Figure 5-11. Measured (lines) and modeled (symbols) s-parameters for 2400pm
spaceship style FET from 0.5GHz to 25GHz...........................................................107
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Figure 5-12. Measured (lines) and modeled (symbols) s-parameters for 2400pm
spaceship style FET from 0.5GHz to 25GHz......................................................... 107
Figure 5-13. Cross-section o f device fabricated at Peregrine Semiconductor used to
verify the distributed model......................................................................................109
Figure 5-14. Traditional small signal model o f MOSFET...........................................110
Figure 5-15. Small signal model o f MOSFET with polysilicon depletion..................I l l
Figure 5-16. One section o f distributed model. Y-box represents the small-signal yparameters of the active device................................................................................ 112
Figure 5-17. Boundary conditions: source terminals grounded, Vgs(x=0)=Vg,
Vds(x=L)=Vd, Ig(x=0)=Ig, Ig(x=L)=0, ld(x=0)=0, Id(x=L)=Id....................... 113
Figure 5-18. Linear layout style used for model verification...................................... 114
Figure 5-19. Layouts for the 432pm, 1296pm, and 2160pm devices. Interconnects go
in a straight line so as to be modeled by a transmission line. Only difference in
layouts is length o f interconnect transmission line..................................................115
Figure 5-20. Measured (symbols) and modeled (lines) Y 11 o f 1296pm wide NFET.l 18
Figure 5-21. Measured (symbols) and modeled (lines) Y11 o f 2160pm wide NFET.l 18
Figure 5-22. Measured (symbols) and modeled (lines) S l l , S12, and S22 o f 432pm
gate width NFET from 06GHz to 25GHz................................................................ 120
Figure 5-23. Measured (symbols) and modeled (line) S21 of432pm gate width NFET
from 06GHz to 25GHz............................................................................................... 121
Figure 5-24. Measured (symbols) and modeled (lines) S l l , S12, and S22 o f 864pm
gate width NFET from 06GHz to 25GHz................................................................ 121
Figure 5-25. Measured (symbols) and modeled (line) S21 o f 864pm gate width NFET
from 06GHz to 25GHz............................................................................................... 122
Figure 5-26. Measured (symbols) and modeled (lines) S l l , S12, and S22 o f 1296pm
gate width NFET from 06GHz to 25GHz................................................................ 122
Figure 5-27. Measured (symbols) and modeled (line) S21 o f 1296pm gate width
NFET from 06GHz to 25GHz................................................................................... 123
Figure 5-28. Measured (symbols) and modeled (lines) S l l , S12, and S22 o f 2160pm
gate width NFET from 06GHz to 25GHz................................................................ 123
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Figure 5-29. Measured (symbols) and modeled (line) S21 o f 2160pm gate width
NFET from 06GHz to 25GHz.....................................................................................124
Figure 5-30. Measured (symbols) and modeled (lines) current gain (H21) versus
frequency...................................................................................................................... 125
Figure 5-31. Measured (symbols) and modeled (lines) unilateral gain........................125
Figure 5-32. Measured (symbols) and modeled (lines) f t andjmax versus gate width.126
Figure 5-33. Simplified transmission line model............................................................127
Figure 5-34. Voltage distribution on gate and drain line for two modes o f frill
distributed transmission line model............................................................................128
Figure 5-35. Attenuation constant, a , versus frequency for the two propagation
modes............................................................................................................................. 129
Figure 5-36. Attenuation for mode 1 and 2 for a 300pm long transmission line
compared to the difference in power gain between the 432pm and 2160pm
transistors.......................................................................................................................130
Figure 5-37. Group velocity o f two propagation modes relative to free space velocity
(c)....................................................................................................................................131
Figure 5-38. Phase velocity o f two propagation modes relative to free space velocity
(c)....................................................................................................................................131
Figure 5-39. Gate voltage as a function o f position along coupled transmission lines
for 2160pm transistor...................................................................................................133
Figure 5-40. Drain voltage as a function o f position along coupled transmission lines
for 2160pm transistor...................................................................................................133
Figure 5-41. Gate and drain connection on same side rather than opposite sides
135
Figure 5-42. Power gain for 432pm and 2160pm transistors with gate and drain
connections on same side and on opposite side........................................................ 136
Figure 5-43. Example o f large transistor layout with many probe pads...................... 137
Figure 5-44. Power gain (MAG/MSG) for 432pm and 2160pm transistors connected
as fabricated and with m any four probe pads............................................................138
Figure 6-1. On resistance drain-source breakdown voltage versus drawn gate length
for SPAWAR SOS NMOS devices............................................................................145
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Figure 6-2. Left: Load line o f class A amplifier. Right: Ideal voltage and current
waveforms o f class A amplifier at full power and h a lf power............................... 147
Figure 6-3. Left: Load line o f class B amplifier. Right: Ideal voltage and current
waveforms o f class B amplifier at full power and half power............................... 149
Figure 6-4. Efficiency o f class A and B based on load line analysis o f device data
shown in Figure 6-2 and Figure 6-3.......................................................................... 150
Figure 6-5. Extraction o f on-resistance for SOS power amplifier device fabricated at
Peregrine Semiconductor (Lg=0.5|nn, Wg=4012frm).............................................. 152
Figure 6-6. Circuit schematic o f NMOS power amplifier............................................ 153
Figure 6-7. Maximum output power and drain efficiency based on load line analysis. 157
Figure 6-8. Photograph o f NMOS power amplifier. Total board size is 4 inches by 6
inches and is mounted on an aluminum block..........................................................157
Figure 6-9. Input match o f SOS power amplifier with Vd=2V.....................................158
Figure 6-10. Power amplifier output match with Vd=2V..............................................159
Figure 6-11. Power amplifier gain versus frequency with Vd=2V...............................160
Figure 6-12. Power amplifier measurement setup......................................................... 160
Figure 6-13. Gain and output power versus input power.............................................. 161
Figure 6-14. Output power and drain efficiency versus input power.......................... 162
Figure 6-15. Output power and power added efficiency versus input power.
163
Figure 6-16. Two tone linearity measurement. Fundamental and third order
intermodulation power versus fundamental input power........................................164
Figure 6-17. CDMA output signal from SOS NMOS power amplifier. Output power
is —10.4dBm.....................................................................................
165
Figure 6-18. CDMA output signal from SOS NMOS power amplifier showing
spectral regrowth. Output power is 19.7dBm..........................................................165
Figure 6-19. Measured ACPR. SOS amplifier meets the IS-95 specification up to an
output power o f 20dBm.............................................................................................. 166
Figure 6-20. Output power and PAE versus CDMA input power............................... 167
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Figure 6-21. Simulated (lines) and measured (symbols) gain and output power versus
input pow er................................................................................................................. 169
Figure 6-22. Simulated (line) and measured (symbols) drain efficiency versus input
pow er...........................................................................................................................169
Figure 6-23. Simulated (line) and measured (symbols) PAE versus input pow er.... 170
Figure A -l. Small signal model o f FET without effects from interconnects............. 183
Figure A-2 Two units o f the distributed model. The box labeled Y is the active FET
model without any parasitics..................................................................................... 184
Figure A-3. Simplified view o f transmission line structure with specified boundary
conditions.................................................................................................................... 187
Figure B -l. SMA launcher matching structure..............................................................192
Figure B-2. S l l o f 50 microstrip line with no stubs, with single open-circuit stub,
and with two open-circuit stubs................................................................................ 193
Figure B-3. S21 o f 50 microstrip line with no stubs, with single open-circuit stub,
and with two open-circuit stubs................................................................................ 193
Figure B-4. Structures used for determining length o f line for a shorted quarter
wavelength line........................................................................................................... 196
Figure B-5. S l l o f two quarter wavelength test structures compared to 50 through
line................................................................................................................................197
Figure B-6. S21 o f two quarter wavelength test structures compared to 50 through
line................................................................................................................................198
Figure B-7. Minimum in S21 frequency response corresponds to half wavelength.
1730 mils is estimated to be the correct length for 1GHz quarter wavelength.... 198
Figure B-8. Photograph o f test circuit board with quarter wavelength bias lines and
50 through structure................................................................................................ 199
Figure B-9. Schematic o f PA output circuit without matching elements................... 200
Figure B-10. Photograph o f board used to test output matching and verify board and
surface mount models................................................................................................ 200
Figure B -l 1. Modeled and measured S l l for output half o f PA circuit.....................201
Figure B-12. Modeled and measured S21 for output half o f PA circuit.....................201
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List of Tables
Table 5-1. Calculated and optimized values o f parasitics..............................................119
Table 6-1. Circuit element values used in power amplifier........................................... 154
Table 6-2. Comparison o f measured and simulated performance................................ 170
Table 6-3. Comparison o f different technologies for pow er amplifiers.
denotes
amplifiers for linear modulation schemes such as CDM A and W -CDMA...........171
Table A -l. Description o f variables and parameters used in distributed solution
183
Table A-2. Values used in fitting the equations to measured data................................190
Table B -l. Physical transmission line parameters to model SM A launcher...............192
Table B-2. Parameters used in ADS microstrip substrate definition............................195
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Acknowledgements
I would like to acknowledge here as many people as possible who have helped
me along the road to m y Ph.D.
Without them, this work would not have been
possible.
First I would like to express my gratitude to m y advisor, Professor Peter
Asbeck. He has given me countless hours o f advice and help without complaint. He
has helped me with everything from spelling and gram m ar, to mathematics, RF
measurements, microwave theory, and device physics. H e has also patiently explained
the faults o f some o f m y less developed ideas and concepts. I could not have asked for
a better Ph.D. advisor.
Next I would like to thank Professor Larry Larson for his advise on power
amplifier design and implantation. I had many usefully hours o f discussion with you.
I also enjoyed helping him fulfil one o f his dreams o f being a professor with our talk at
Cafe Roma.
I would also like to thank the rest o f the committee. I greatly appreciate their
time and effort to come to my qualifying exam and defense, as well as time spent
reviewing m y (somewhat long) thesis.
Without Dr. Isaac Lagnado at SPAWAR Systems Center in San Diego, this
silicon-on-sapphire project at UCSD would most likely not have existed. Dr. Lagando
has not only provided the funding for this project, but also has provided technical
advice and helped to bring me together with many other researchers (at IBM,
Oklahoma State University, and many others). He has helped to provide access to an
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advanced 0.1 pm CMOS process at IBM and helped me get space on a MOSIS
maskset at Peregrine Semiconductors.
Paul de la Houssaye, also o f SPAWAR Systems Center in San Diego, was
instrumental in my learning about silicon-on-sapphire devices and processing. I owe
Paul a debt o f gratitude for helping m e get m y first maskset taped out, and for helping
me get the wafers processed before the fab shut down. Paul was m y main point of
contact at SPAWAR, and always treated me kindly and helped to get things done.
I would also like to thank Ella for helping me dice m y sapphire wafers. I think
less than 10% o f m y cuts were on actual dicing streets.
Many other people at
SPAWAR have helped out in fabrication and testing. I can not mention them all here.
In the end, the difference between having an oscillator and having an amplifier
came down to Ziv Alon o f Conexant.
I am very grateful that he spent a whole
afternoon with me to experiment with my amplifier and teach me some techniques for
stabilizing it. Without his help, chapter 6 may have been entitled “power oscillators”
(or my graduation postponed by a month).
I would also like to thank my friends and family for putting up with my long
hours o f work in the past couple years, especially in the last few months. I would
especially like to thank m y wife Jennifer.
She has been extremely understanding
about my long hours spent at school (6.5 days a week). Without her love, support, and
understanding, I would not have had the strength to complete this work. I will work
hard to justify her faith in me for these last few years. I would also like to thank my
parents, who have taught me more than I could ever learn in school. I only wish my
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father would have made it to see this day. I know he is very proud o f me, but I am
equally proud o f the life he has lead. He will be sorely missed by all who knew him.
Next I would like to acknowledge the people who have helped me in the lab on
a daily basis. First the “old” group. I owe it to Robb Johnson, my predecessor, for
getting me stuck in silicon-on-sapphire research for so many years. He made it look
so easy. Thanks for providing me with excel charts for extracting device parameters,
layouts o f SOS MOSFETs as a starting point, and helping to explain the SOS process
and devices to me. I need to thank Pin-Fan “Ed” Chen for teaching me how to make
RF measurements. Without his help and hours o f patient tutelage, I would have been
utterly lost in our measurement lab. Ed also taught me how to use our circuit board
router, making it possible for me to waste hours o f my life trying to get m y power
amplifier to stop oscillating. Gary Hanington was always willing to stop and help
someone in the lab, even with things as unrelated to his thesis as SOS. I already miss
his unique way o f dealing with life’s many problems and I miss his many stories.
Gary always had a personal life story no matter what the subject was, and his stories
were always very entertaining. Andre Metzger was also willing to help out (when not
frantically working on taping out a mask, or when traveling to Europe). I appreciate
his helping to get me in the door for a day at Conexant, and for his help around the lab.
Although Nick Farcich may not think so, he has been a great help to me as well. Nick
has been a sanity check for some o f m y more ridiculous ideas, helping to filter them
before I look like an idiot discussing them with Professor Asbeck. In addition to many
other things, Nick has also helped out with some o f my “grunt” work without
xx
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complaint (e.g. helping to carry coffee and other items to m y oral exams and running
around looking for professors at the time o f m y exams).
In the next generation o f students, I would like to thank Masaya Iwamoto for
his help with the ADS simulator. He has also helped me by talking through some o f
m y amplifier design problems.
Good luck with taking over the measurement
equipment. I would also like to thank Becky Welty for helping me “de-scum” some o f
m y SOS chips. Although our research did not overlap, discussions in the lab did help
to guide some o f m y thinking. To Weishan Sun and Mahim Ranjan, I want to wish all
the best and to confess to them that I would probably leave with an M.S. i f I had to do
it all over again (although I ’m told by many that this attitude will change as the details
o f my time at UCSD fades in my memory).
And to Jeff Hinrichs, Jeff Keyzer, Peter Law, David Keogh, and Adam
Conway, the newest generation o f students, I want to leave some advice. I f you want
to graduate in a timely manner, do the following: focus on your thesis research from
the start, document everything well so you won’t have to repeat it in the last year o f
your research, and take advantage o f what UCSD has to offer and occasional take a
fun class (like French or surfing).
Some o f the material in chapter 2 is as it appears in "A 26.5 GHz Silicon
MOSFET 2:1 Dynamic Frequency Divider", IE EE M icrowave and Guided Wave
Letters, Oct. 2000, vol. 10, pp. 421-423. I would like to acknowledge the co-authors
L. Shi, K. Jenkins, P.R. de la Houssaye, Y. Taur, P.M. Asbeck, I. Lagnado. I was the
primary investigator and primary author for this publication. Some o f the material in
xxi
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chapter 5 is as it appears in "Layout Parasitic Effects on Microwave Characteristics o f
Large Periphery Transistors", IE E E Topical Workshop on Power Am plifiers fo r
Wireless Communications, San Diego, CA, Sept. 2000. I would like to acknowledge
the co-authors P. R. de la Houssaye, P. M. Asbeck, and I. Lagnado. I was the primary
investigator and primary author for this publication. Some o f the material in chapter 3
and chapter 5 is as it appears in "Prospects o f CMOS Power Amplifiers on Thin Film
SOS for Wireless Applications," F irst Annual UCSD Conference on Wireless
Communications, San Diego, CA, March 1998. I would like to also acknowledge the
co-authors o f this publication R.A. Johnson, P.F. Chen, B. Xavier, P.R. de la
Houssaye, P.M. Asbeck, I. Lagnado. I was also the primary investigator and primary
author o f this paper.
To anyone I may have missed, your help is truly appreciated and will not soon
be forgotten.
xxii
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Vita
December 1993
B.S. Physics, University o f California, Davis
1994 - 1996
Teaching Assistant, Department o f Electrical and Computer
Engineering, University o f California, San Diego
December 1996
M.S. Electrical Engineering, University
Diego
1996 - 2000
Graduate Student Researcher, University o f California, San
Diego
January 2001
Ph.D. Electrical Engineering, University o f California, San
Diego
o f California,
San
Publications
M. Wetzel, L. Shi, K. Jenkins, P.R. de la Houssaye, Y. Taur, P.M. Asbeck, I. Lagnado, "A
26.5 GHz Silicon MOSFET 2:1 Dynamic Frequency Divider", IEEE Microwave and
Guided Wave Letters, Oct. 2000, vol. 10, pp. 421-423.
M. Wetzel, P. R. de la Houssaye, P. M. Asbeck, and I. Lagnado, "Layout Parasitic Effects
on Microwave Characteristics o f Large Periphery Transistors", IEEE Topical Workshop on
Power Amplifiersfo r Wireless Communications, San Diego, CA, Sept. 2000.
PE. Chen, R.A. Johnson, M. Wetzel, P.R. de la Houssaye, G.A. Garcia, P.M. Asbeck, I.
Lagnado, "Silicon-on-Sapphire MOSFET Distributed Amplifier With Coplanar
Waveguide Matching", 1998 IEEE Radio Frequency Integrated Circuits (RFIC)
Symposium.
M. Wetzel, R A . Johnson, PE. Chen, B. Xavier, P.R. de la Houssaye, P M . Asbeck, I.
Lagnado, "Prospects of CMOS Power Amplifiers on Thin Film SOS for Wireless
Applications," First Annual UCSD Conference on Wireless Communications, San Diego,
CA, March 1998.
M. Wetzel, M.C. Ho, PM . Asbeck, P. Zampardi, C.E. Chang, C. Farley, and M E. Chang,
"Modeling Emitter Ledge Behavior in AlGaAs/GaAs HBTs," 1997 GaAs Manufacturing
Technology Conference, San Francisco, CA, June 1997.
xxiii
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Abstract of the Dissertation
Silicon-on-Sapphire Technology for
Microwave Power Applications
by
Matthew A. Wetzel
Doctor o f Philosophy in Electrical Engineering (Applied Physics)
University o f California, San Diego, 2001
Professor Peter M. Asbeck, Chair
Silicon-on-sapphire (SOS) MOSFETs offer many advantages such as reduced
device and interconnect capacitance, availability o f complementary devices with high
microwave gain, and excellent device isolation, which make SOS technology a
worthwhile choice for many applications. To meet future wireless communications
demands, two areas must be addressed:
aggressive scaling o f device dimensions,
which can reduce power consumption and increase speed; and development o f power
devices for radio frequency (RF) power amplifiers (PAs). RE PAs pose a number o f
device and modeling challenges. The objective o f this dissertation is to demonstrate
the inherent speed o f 0.1pm scaled CMOS technology and to characterize power
MOSFETs for use in RF PAs.
A 0.1pm gate length CMOS technology was used to demonstrate the speed
advantages o f deep sub-micron MOSFETs. A 2:1 digital dynamic frequency divider
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was designed and tested with operating frequency from 6.5GHz to a record 26.5GHz
(55% faster than the previous MOSFET record o f 17GHz using a 0.25pm process).
Large power MOSFETs were found to have microwave gain that decreased
sharply with device size. To study this effect, power MOSFETs w ith different layout
strategies were designed, fabricated, and tested. The effects o f layout parasitics on RF
performance were modeled using both lumped element models and distributed
transmission line models. The RF characteristics o f the power devices were accurately
predicted.
The effects o f self-heating on SOS power MOSFETs were also
investigated. Self-heating was found to play only a minor role in SOS technology.
Finally, an RF PA was demonstrated using SOS MOSFETs. The 1GHz class13 amplifier was designed using NMOS devices and measure to have 8dB gain. At
ldB gain compression, the PA has 21 dBm output power and a power added efficiency
o f 27%.
The performance can be further enhanced through device optimization.
Although class-B, the amplifier has good linearity, meeting IS-95 linearity
specifications for CDMA signals up to an output power o f 20dBm.
xxv
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1 Introduction
1.1 Motivation
Recent years have seen an explosive growth in wireless communications and
the use o f portable handheld electronic devices. Historically, the performance and
speed required by wireless communications systems operating at 1.9GHz or higher has
been the realm o f compound m -V semiconductor devices such at MESFETs, HBTs,
HEMTs, and PHEMTs. These devices, although faster and often w ith lower noise
figures, have lower integration densities than silicon CMOS circuits due to limits on
scaling and wafer size. They also typically use more power due to higher tum-on
voltages and higher quiescent currents or require a negative voltage to operate which
increases system complexity.
This had led circuit designers to be faced with an engineering tradeoff. Do
circuit designers use a technology that can more easily meet the communication
system requirements o f linearity and noise at the design frequency? Or do they use a
technology that can more easily meet the application needs o f low cost and low
power?
This dilemma has led many device, fabrication, and design engineers to seek
out new technologies as well as to increase the performance o f current technologies.
Improved silicon MOSFETs hold the promise o f being able to provide low power,
high-speed, and high integration density for most if not all o f the components for
wireless communications. If a single technology, such as silicon based MOSFETs,
1
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2
can provide all o f the components for a system (including both active devices and low
loss passive elements), it is possible to fabricate the entire system on a single chip.
Having fewer components to put together would make manufacturing cheaper and
products more compact. At the same time, most signals would stay on-chip, negating
the need for many off-chip buffers.
This would reduce power consumption, and
possibly increase the overall system performance.
Studies on scaled MOSFETs have shown the inherent speed that is possible
with CMOS based technology [1]. There have also been many studies showing the
ability o f circuit designers to use CMOS technology to design analog circuit blocks for
wireless applications [2, 3, 4]. Silicon-on-insulator (SOI) and silicon-on-sapphire
(SOS) technologies have been getting increased attention for their advantages in deep
sub-micron scaling advantages and lower capacitances [5, 6, 7]. SOS technology not
only has the advantages o f the high packing density and low power common to silicon
MOSFET technologies, it also has the advantage of lower capacitances, lower loss
passive elements, and improved device isolation.
Silicon-on-sapphire technology was first proposed by Manasevit and Simpson
in 1964 [8]. Instead o f using a sliced silicon ingot as wafer starting material, they
proposed depositing a thin silicon film on an insulating sapphire substrate. The idea
was proposed to improve device fabrication and design.
Although SOS provides
many benefits, its main application was in space due to radiation hardness [9] and poor
material quality. In the late 1970’s a silicon film improvement process was developed
by Lau and co-workers, producing device quality materials, consisting o f an
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3
implantation and double solid-phase epitaxial regrowth [10, 11]. The result is today is
silicon film o f high quality o f 1000A and thinner can be deposited on sapphire
substrates [12, 13].
SOS devices with power gain up to 60GHz have been
demonstrated [14] and SOS circuits for wireless communications operating at 2.4GHz
[15].
The future role o f SOS in the microwave regime w ill be strongly influenced by
dimensional scaling. Particularly for power and high dynamic range applications, it
will also be strongly influenced by the drop in voltage handling capability that
accompanies scaling. Although this is tolerable for digital applications, in microwave
circuits the low voltage-handling capability limits dynamic range, and makes it
particularly difficult to provide power amplification. In order to develop significant
power levels, it is necessary to generate very large current levels. This causes the
required devices to be very wide, and leads to strong parasitic elements that degrade
the microwave gain. The use o f high current and low voltage also results in the need
to match low output impedance levels to 50 ohms, which is difficult to accomplish
while maintaining efficiency and bandwidth. The central issues o f this thesis are the
performance o f scaled SOS circuits and the design and characterization o f large gate
width devices for use in power amplifiers.
1.2 CMOS Scaling
The silicon MOSFET has had an unprecedented rapid evolution since its
inception, following Moore’s law o f exponentially shrinking geometry.
Today’s
powerful desktop computers, laptop and palm computers, digital television, DVD
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4
players, and many other products would not be possible without the benefits o f CMOS
transistor scaling to sub-micron dimensions.
Even though commercial MOSFET
feature sizes have now shrunk to 0.13 pm, the performance o f silicon MOSFETs can
still be greatly increased through further scaling o f the gate length, gate oxide
thickness, and the doping concentrations.
The scaling o f the MOSFET gate length is key to developing the next
generation technology and for improving MOSFET performance.
A basic
understanding o f this can be attained from the gradual channel approximation, even
though this model will not hold true for very short gate length transistors. In the
gradual channel approximation, a MOSFET’s transconductance (gm) is given by
equations 1-1 where W and L are the transistor width and length respectively, p is the
channel mobility, Q is the gate capacitance per unit area, Vd is the applied drain
voltage, and vsat is the saturation velocity o f the carriers in the channel.
Linear Region
Saturation Region
(1- 1)
One benchmark for the speed o f a transistor is its cutoff frequency,^- This is
defined as the frequency where the current gain drops to zero. F t o f the a MOSFET
can be approximated by
Sm
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(1-2)
5
In the approximation that Cgd is small, Cm is given by the Cgs, then equations 11 and 1-2 can be combined to give
uV
ft =—
2 tjL
f _
Li near Region
Vth)
2 nL f
Saturation Region
(1-3)
Equations 1-3 show ^ o f long channel devices (only valid for gradual channel
approximation) would improve by a factor o f k2. This does not hold true for short
channel devices. Short channel FETs are limited by velocity saturation. The transit
time o f carrier through the channel is not a function o f applied bias under the limit of
velocity saturation. In this case gm an d ^ are given by equations 1-4.
g m =WC, vsat
Saturation Region
f ( =-^£2L
2 tcL
Saturation Region
(1-4)
From equations 1-4 it is easily seen that the gate length, L, is the only
parameter in processing or device design that can increase^ for short channel devices.
In the saturation region, f varies inversely with gate length, making great speed
improvements possible through the reduction o f the gate length. As the device is
scaled down by a factor k, f has been shown to increase by a factor o f k while _/Vnax
increases by a factor tJ k 2/( k +1) [16].
As the MOSFET gate length is scaled, other device parameters undergo scaling
as well. In one possible MOSFET scaling strategy, the gate length is scaled down by a
factor k, the gate oxide thickness, gate width, gate length, and doping junction depths
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6
are also scaled down by k . The doping concentration is increased by a factor o f k , and
all voltages are reduced by a factor o f k . Thus, as the gate length o f the MOSFET is
scaled down, not only does the speed o f the device increase greatly, it is also possible
to greatly reduce the applied voltages, making scaled devices faster while using less
power. This is a very important result not only for high-speed applications, but also
for low power applications.
CMOS transistor scaling has lead to an unprecedented rapid improvement in
the speed o f MOSFET technologies and shows no sign o f decay until the year 2012
[17] when the technology is expected to approach fundamental limits o f quantum
mechanics. CMOS technologies will continue to evolve, becoming faster, smaller,
and using less power. This trend will not only carry CMOS technologies into the new
millennium, but also help CMOS to continue to meet the technological challenges o f
new applications.
1.3 SOS versus Bulk Silicon
A cross-section showing the main features o f bulk silicon (here depicted as a
single n-well process) and SOS MOSFETs is shown in Figure 1-1.
The main
technological difference is that bulk silicon devices are fabricated on the top surface o f
a thick conductive silicon wafer while SOS devices are fabricated on a thin film o f
silicon that has been deposited on an insulating sapphire wafer. This difference leads
to many advantages for SOS devices. The most obvious advantages are depicted in
Figure 1-1. Figure 1-1A shows the latch-up model for a single n-well bulk silicon
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7
process. Care must be taking in choosing the doping levels and geometries o f the
device in order to keep the current gain o f the parasitic bipolar transistors below 1 so
that latch-up cannot occur. In the SOS device shown in Figure 1-1C, latch-up cannot
occur. Since the devices are isolated by having them on separate islands o f active
silicon, there is no current path between the devices, and as such, latch-up cannot
occur. This dramatically improved device isolation is very easy to achieve in SOS
technology.
The simple device isolation in SOS also makes for a more compact
design since devices can be placed closer together without worry o f latch-up or
coupling. In bulk silicon technology channel stop implants, trench isolation, and many
other steps are needed to prevent both surface currents and substrate currents between
devices. Even with all these complex processing steps, there is always at least a small
coupling between devices in bulk silicon.
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8
Trench Isolation
Drain
p-Type Silicon
(A)
Trench Isolation
Drain
Drain
p-Type Silicon
Source
Drain
Drain
Source
Sapphire Substrate
(Q
Figure 1-1. Cross-sections of NMOS and PMOS transistors on
bulk silicon and SOS showing (A) latch-up model for bulk silicon,
(B) parasitic capacitances for bulk silicon, (C) thin film silicon-onsapphire.
Another fundamental advantage o f SOS technology over bulk silicon is the
reduction in device capacitance. As shown in Figure 1-1B, a bulk silicon device has
many parasitic capacitances to the n-well and to the p-substrate. In addition to the
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9
parasitic capacitance shown is the capacitance from the metal interconnects to the
substrate. The largest benefit for the device itself is the reduction in the drain and
source capacitance to the body. Because the drain and source areas are usually heavily
doped, the junction capacitance can be large. In a typical 1pm CMOS process, this
will amount to a capacitance o f 0.2-0.35fF/um2, depending on the doping levels. This
capacitance is eliminated in SOS by eliminating the conductive substrate.
The
dynamic power dissipated by a CMOS inverter is given by Po^/CVdd . The reduction
in device capacitance and interconnect capacitance will therefore lead to a lower
power dissipation with the same supply voltage and frequency o f operation.
In addition to leading to higher speed and lower power digital circuits, the
absence o f a conductive substrate is also beneficial to analog circuits. Most analog
circuits require some passive elements for matching networks, inductive loading, DC
blocks, ect. hi bulk silicon, the inductors and capacitors are capacitively coupled to a
lossy silicon substrate. This leads to loss in the passive elements, lowering the quality
factor (Q) o f the elements. It has been shown that SOS technology provides lower
loss and higher self-resonant frequencies in passive element when compared to bulk
silicon or other SOI technologies [18].
This allows for lower loss in the passive
elements and the possibility o f higher operating frequencies than in bulk silicon.
The nature o f the thin film transistor is to confine the cross-section from two
dimensions to one dimension. It requires great efforts to achieve this same result for
deep sub-micron gate lengths in bulk silicon.
In deep sub-micron bulk silicon
fabrication it is important to pay careful attention to the junction depths, metal or
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10
silicide depths (to avoid spiking that will short to the contact to the substrate), and the
doping profile (often via halo or super-halo implants). M ost o f the benefits o f these
specialized processes used in bulk silicon come for free from the thin-fihn silicon on
sapphire technology. This makes fabrication o f deep sub-micron MOSFETs in SOS
technology easier than in bulk silicon.
One o f the important design parameters for fabrication o f sub-micron
MOSFETs is the threshold voltage rolloff. For longer gate length MOSFETs, the
threshold voltage is given by the equation
lr
_ ^
Qox , '-tff* , q N gX d max
+ --—-------ox
^ox
th = <DMS —p — + 2<Pf
«
(1 -5 )
where <X>ms is the gate to semiconductor workfunction difference, Na is the
doping in the channel, Op is the fermi energy level o f the semiconductor with doping
Na, C0x is the gate oxide capacitance, and Xdmax is the maximum depletion depth given
by
14s - 0 17
— ——— . The last term in equation 1-4 is simply the potential derived from the
V 9N a
depletion charge underneath the gate. However, as shown in Figure 1-2A, not all o f
the charge under the gate can be controlled by the gate voltage. Only the charge Qd’
is controlled by the gate, the rest o f the charge is due to the depletion regions around
the drain and source implants. As the channel is made shorter, a larger percentage o f
the charge under the gate is not controlled by the gate voltage.
When this effect
becomes large enough, the threshold voltage begins to rolloff with decreasing gate
length. An SOS MOSFET is shown in Figure 1-2B. Because o f the thin-film silicon,
the charge Qd’ scales better with gate length, mitigating the Vth roll-off [19,20].
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11
Source
- W 'Y
Drain
i ..- B a s s
Source | \ / j Drain
Silicon substrate
Silicon substrate
(A)
Source \
Q d’
Drain
/ | Drain
Sapphire substrate
Sapphire substrate
(B)
Figure 1-2. Depletion charge for long and short channel
MOSFETs in (A) bulk silicon and (B) SOS technology.
Because o f the increased control over the depletion charge, SOS devices also
have increased control over the potential at the silicon gate oxide interface known as
the surface potential. This improved control over the surface potential leads to an
improved subthreshold slope [21]. In one study, the subthreshold slope improved
from 108mV/decade for thick-film and bulk silicon MOSFETs to a near ideal
62mV/decade for thin-film MOSFETs [22]. The improved subthreshold slope means
the threshold voltage can be reduced while maintaining low off-state leakage currents.
The scaling o f the threshold voltage is very important in order to allow for the scaling
o f the supply voltage and therefore reduced power operation.
A benefit unique to the SOS technology comes from the difference in thermal
expansion coefficients o f silicon and sapphire.
The silicon film is deposited on a
sapphire wafer at high temperature. As the silicon and sapphire cool, their lattice
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12
constants change differently due to the slight difference in their thermal expansion
coefficients.
This leaves the silicon film under compressive strain at room
temperature. Although the thin film SOS has high electron mobility, the strain reduces
the mobility slightly from the value o f bulk silicon electron mobility [23]. At the same
time, however, the compressive strain splits the degeneracy o f the heavy and light hole
valence bands, making the light hole band slightly more favorable. This leads to an
improvement in the hole mobility in SOS over the hole mobility in bulk silicon [24].
This effect is similar to the effects seen in silicon germanium layers on silicon [25].
This results in faster and more balanced complementary device system than other
CMOS technologies.
One o f the drawbacks o f SOS technology, like other SOI technologies, is the
“kink effect”. It is a byproduct o f the device either not having a body contact, or
having a body contact with high series resistance. When the electric field becomes
large enough, it results in extra electron-hole pairs being generated by impact
ionization. In a bulk silicon device, carriers generated by impact ionization in the
channel will result in substrate or body current.
In SOS devices without a body
contact, these charges are not conducted away and build up in the device below the
channel as depicted in Figure 1-3.
This results in a back bias, which lowers the
threshold voltage o f the device, increasing output current. This effect can be mitigated
if the silicon film in SOS technology is made very thin, A simulation showing the
effects this has on the transistors output current is shown in Figure 1-4. If the silicon
film is thin enough to have a depletion region that extends all the way to the back
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13
interface with the sapphire at threshold, it is called a fully depleted (FD) device. This
condition occurs for silicon films o f approximately 1200A, depending on doping
levels. An example o f the FD device without the kink effect is shown in Figure 1-5.
Body
Source
G ate
i
n* Polv
1
Drain
gEiSgggf
mm
£
3
'/t
mmsm
p-type Silicon Substrate
(A)
n Polv
Sapphire Substrate
(B)
Figure 1-3. Impact ionization in channel region in (A) bulk silicon
results in substrate currents while in (B) SOS results in charge
build-up underneath channel, lower the threshold voltage.
0.20
0.16
< 0.12
■3 0.08
0.04
0.00
0
0.5
V ds (V)
1
1.5
Figure 1-4. Simulated DC curve showing kink effect of partially
depleted device.
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0
0.5
1
1.5
2
2 .5
3
Vds (V)
Figure 1-5. Measured data from NMOS 0.5pm x 120pm device.
Vgs is varied from 0V to 3.5V.
All o f these advantages have been used to produce record breaking device and
circuit results in the SOS technology. Optically defined SOS MOSFETs have been
reported with /^=25GHz and j/?nax=66GHz for NMOS transistors and jr=T4GHz and
yinax=41GHz for PMOS transistors [14]. This technology was used to produce a low
noise amplifier (LNA) with lOdB gain and 2.8dB noise figure at 2.4GHz [26], a mixer
with input referred third order intercept point (DP3) o f 5dBm and conversion loss o f
5dB operating at 2.4GHz [15], and a transmit-receive (TR) switch with 0.6-0.7dB
insertion loss and 20dB isolation in the l-5GHz band [7], Commercial products are
now available from Peregrine Semiconductor, including a fully integrated frequency
synthesizer with excellent phase noise characteristics [27].
X-ray lithography has
been used with SOI technology to produce NMOS transistors with 70nm gate length,
150GHz f , and a 9.5ps gate delay ring oscillator (the first sub-lOps CMOS ring
oscillator at room temperature) [28]. An SOS NMOS device w ith 0.1pm gate lengths
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15
has been demonstrated with fi= \05GHz and/max=50GHz [7]. Silicon-germanium pMODFETs with gate lengths o f 0.1pm on a sapphire substrate have been
demonstrated with ^t=49GHz and /rnax=95GHz. [7].
These results show that SOS
technology is capable o f satisfying general circuit needs in the RF regime and will
continue to operate and higher and higher frequencies with improvements in the
materials and devices.
1.4 Large Periphery MOSFETs
Record breaking high frequency results are invariably achieved with minimum
size transistors. While MOSFETs in digital circuits generally have gate widths o f a
few microns or less, there are many analog and mixed signal applications that require
substantially larger gate widths. The gate widths used in analog and mixed signal
applications can range from the smallest gate widths up to 8mm o f gate width.
One application for such large periphery devices would be for very accurate
analog to digital converters. If 10 to 12 bits o f accuracy are required, all measures
must be taken to reduce the system noise. One o f the sources o f noise is the kT/C
noise associated with the gate-to-source capacitor o f the MOSFET. This is inversely
proportional to the size o f the capacitor, and can therefore be reduced by using a very
large gate width MOSFET.
Another application for very large gate width MOSFETs is for use in a power
amplifier. Communication systems must be able to radiate a considerable amount o f
power. Depending on the application, the power amplifier will have to provide up to
lOmW to 1 Watt o f power. Most cell phone power amplifiers provide a maxim um o f
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16
1 W att output power. Because o f the low power density o f silicon MOSFETs (as will
be discussed in chapter 6), this results in gate widths o f 8mm or larger to achieve the
necessary maximum output power, depending on the device design.
Unfortunately, the large periphery MOSFETs used in power amplifiers and
other applications do not measure up to the performance o f their minimum geometry
counterparts. Two useful figures o f merit for transistors is the cutoff frequency,/^ and
the m axim um frequency o f oscillation, 7 ^ . -Ft is the frequency where the current gain
(H 2 1 ) drops to unity whiles/max is the frequency where the power gain drops to unity. If
the device has voltage gain, Tinax can be larger than f . Digital circuits are generally
limited by how quickly electrons can be moved to charge or discharge a capacitive
load. Analog circuits are generally limited by how much power is delivered to a
capacitive or a resistive load. Thus f t is a more important figure o f merit for digital
circuits while /max is a more important figure o f merit for analog circuits.
NMOS transistors fabricated on SOS with 0.35jjm effective gate lengths and
metal T-gate structures have shown excellent RF performance. The transistor were
fabricated at SPAWAR Systems Center (SSC), San Diego. The design and testing
was performed at UCSD. Transistors in this technology with lOOpm gate width have
7t=19GHz and7max=39GHz. However, as shown in Figure 1-6 and Figure 1-7, as the
gate width is increased, f t and Tmax can drop dramatically.
As the gate width is
increased to 4.4mm, f and Tmax both drop to about 8GHz. This greatly limits the
useable bandwidth of the transistors and the available gain o f the transistors at wireless
communication frequencies o f 900MHZ to 2.4GHz. Although it was widely believed
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
that the reduction in performance is due to layout parasitics, the effects were not
understood.
20
18
16
14
12
a
- • —Waffle
- • —Standard
Spaceship
10
8
6
4
2
0
0
1000
2000
3000
4000
5000
Gate Width (urn)
Figure 1-6. Cutoff frequency,/;, versus gate width for different
layout strategies.
45
40
35
30
—• —Waffle
—• —Standard
Spaceship
25
<2 20
15
10
0
1000
2000
3000
4000
5000
Gate Width (um)
Figure 1-7. Maximum oscillation frequency.
versus gate width
for different layout strategies.
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18
1.5 Scope o f Dissertation
SOS has a well-developed digital and analog process.
SOS also has many
benefits such as improved device isolation, easier device scaling, and lower loss
passive elements that make it a very attractive alternative for future high-speed digital,
analog and mixed signal applications. It remains to be seen, however, how much the
performance can be enhanced b y device scaling, or i f the reduction in breakdown
voltage with device scaling will place too tight o f restrictions on the circuit design. In
addition, an explanation for the poor RF performance o f large gate width power
devices is needed.
A better understanding o f the causes o f the RF performance
degradation are needed to assess the possibility o f using SOS power devices in RF
power amplifiers. These issues are all addressed in this thesis.
Chapter 2 provides a study o f the scaling impact on digital circuits using a
0.1pm scaled bulk CMOS technology. A frequency divider circuit was fabricated in
this technology with record breaking performance, operating up to clock frequencies
o f 26.5GHz. The design and analysis o f this circuit provides a basis for estimating the
performance o f SOS.
It is shown that a comparable SOS circuit in a 0.1pm
technology can be expected to operate up to a clock frequency o f 30-32GHz, breaking
the barrier for silicon based MOSFETs in the milli-meter wave regime.
Chapters 3 through 5 provide an in-depth investigation o f the effects o f scaling
up the width o f SOS transistors on their microwave performance.
Chapter 3 will
present three different layout strategies for large gate width MOSFETs that were
fabricated and studied. These layout strategies were designed in an effort to mitigate
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19
the RF performance degradation with increasing gate width and to better understand
the causes o f the RF performance degradation. The RF performance o f these different
layout strategies will also be presented here.
In chapter 4, a investigation o f the effects o f self-heating on the SOS devices
will be presented. Self-heating is a well known problem for other silicon-on-insulator
technologies, and was investigated as a possible source o f the RF degradation o f
power devices. Although there are some self-heating effects, the self-heating was
found not to significantly degrade the RF performance o f the power MOSFETs. In
chapter 5, another source o f RF degradation will be explored. Chapter 5 deals with the
effects o f layout parasitics in the power MOSFETs. A new theory to describe the
layout parasitics was developed. It is found that most o f the performance degradation
comes from the effects o f the layout parasitics.
Next in chapter 6, a demonstration power amplifier using SOS MOSFETs will
be presented. The amplifier is being operated in class B. At 1GHz the amplifier has a
gain o f 8dB. At ldB gain compression the amplifier has an output power o f 21 dBm
(126mW), power added efficiency (PAE) o f 27%, and a drain efficiency o f 34%. The
amplifier is linear enough to meet the strict IS-95 linearity requirements up to an
output power o f 20dBm. The study o f this amplifier pinpoints the difficult tradeoffs in
the use o f large periphery SOS devices.
Finally, chapter 7 presents a summary o f the work presented in this thesis and
suggestions for future improvements to the SOS technology.
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20
1.6
References
1.
Y. Mii, S. Rishton, Y. Taur, D. Kern, T. Lii, K. Lee, K.A. Jenkins, D. Quinlan,
T. Brown Jr., D. Danner, F. Sewell, M. Polcari, “Experimental high
performance sub-0, lp m channel nMOSFET's”, IEEE Electron Device Letters,
vol.15, no.l, pp. 28-30, Jan. 1994.
2.
M. Steyaert, M. Borremans, J. Janssens, B. De Muer, N. Itoh, J. Craninckx, J.
Crols, E. Morifuji, H.S. Momose, W. Sansen, “A single-chip CMOS
transceiver front-end for DCS-1800 wireless communications”, Analog
Integrated Circuits and Signal Processing, vol.24, no.2, pp. 83-99, July 2000.
3.
Kwok-Kei Kan, Dongsheng Ma, Kin-Chung Mak, H.C. Luong, “Design theory
and performance o f 1-GHz CMOS downconversion and upconversion mixers”,
Analog Integrated Circuits and Signal Processing, vol.24, no.2, pp. 101-111,
July 2000.
4.
Q. Huang, “CMOS RF design-the low power dimension”, Proceedings o f the
IEEE 2000 Custom Integrated Circuits Conference pp. 161-166, May 2000.
5.
C. L. Chen, R.H. Mathews, J.A. Bums, P.W. Wyatt, D.-R. Yost, C.K. Chen,
M. Fritze, J.M. Knecht, V. Suntharalingam, A. Soares, C.L. Keast, “Highfrequency characterization o f sub-0.25pm frilly depleted silicon-on-insulator
MOSTFETs”, IEEE Electron Device Letters, vol. 21, no. 10, pp. 497-499,
October 2000.
6.
J.P. Colinge, “Thin-film SOI technology: the solution to many submicron
CMOS problems”, IEEE International Electron Devices Meeting, pp. 817-820,
1989.
7.
I. Lagnado, P.R. de la Houssaye, W.B. Dubbelday, S J . Koester, R. Hammond,
J.O. Chu, J.A. Ott, P.M. Mooney, L. Perraud, K.A. Jenkins, “Silicon-onsapphire for RF Si systems 2000”, Topical M eetings on Silicon Monolithic
Integrated Circuits in RF Systems Digest, pp.79-82, April 2000.
8.
H.M. Manasevit, W.I. Simpson, “Single-crystal silicon on a sapphire
substrate”, Journal o f Applied /physics, vol. 35, pp. 1349-1351, 1964.
9.
J.G. Rollins, J. Choma, W.A. Kolasinski, “Single-event upset in SOS
integrated circuits”, IEEE Transactions on Nuclear Science, vol. NS-34, no. 6,
December 1987.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
21
10.
S.S. Lau, S. Matteson, J.W. Mayer, P. Revesz, J. Gyulai, J. Roth, T.W.
Sigmon, T. Cass, “Improvement o f crystalline quality o f expitaxial Si layers by
ion-implantation techniques”, A pplied Physics Letters, vol. 34,1979.
11.
T. Yoshii, S. Taguchi, T. Inoue, H. Tengo, “Improvement o f SOS device
performance by solid-phase epitaxy”, Japanese Journal o f Applied Physics,
1982, vol. 21, pp. 175-176.
12.
G. A. Garcia, R.E. Reedy, M.L. Burgener, “High-quality CMOS in thing
(lOOnm) silicon on sapphire”, IE EE Electron D evice Letters, vol. 9, no. 1, pp.
32-34, January 1988.
13.
G.A. Garcia, R.E Reedy, “Electron mobility within lOOnm o f the Si/Sapphire
interface in double-solid-phase epitaxially regrown SOS”, IEEE Electron
Device Letters, vol. 221, no. 10, p. 537, 1986.
14.
R.A. Johnson, C.E. Chang, P.R. de la Houssaye, G.A. Garcia, I. Lagnado, P.M.
Asbeck, “Microwave characteristics o f high/max low noise thin film silicon-onsapphire MOSFETs”, IEEE International SO I Conference, October 1995.
15.
R.A. Johnson, P.R. de la Houssaye, C.E. Chang, P-.F. Chen; M.E. Wood, G.A.
Garcia, I. Lagnado, P.M. Asbeck, “Advanced thin-film silicon-on-sapphire
technology: microwave circuit applications”, IEEE Transactions on Electron
Devices, vol.45, no.5, pp. 1047-1054, May 1998.
16.
E. Morifuji, C.E. Biber, W. Bachtold, T. Ohguro, T. Yoshitomi, H. Kimijima,
T. Morimoto, H.S. Momose, Y. Kattsumata, H. Iwai, “RF noise study of small
gate width Si-MOSFETs up to 8 GHz application for low power
consumption”, Extended Abstract SSDM, pp. 80-81, September 1998.
17.
T.H. Ning, “CMOS in the new millennium”, IEEE Custom Integrated Circuits
Conference, pp. 49-56, 2000.
18.
R.A. Johnson, C.E. Chang, M.E. Wood, G.A. Garcia, I. Lagnado, P.M.
Asbeck, “Comparison of microwave inductors fabricated on silicon-onsapphire and bulk silicon”, IEEE M icrowave and Guided Wave Letters, vol. 6,
no. 9, September 1996.
19.
J.P. Colinge, “Thin-film SOI devices: A perspective”, M icroelectronic
Engineering, vol. 8, pp. 127-147, December 1988.
20.
K.K. Young, “Short-channel effect in fully depleted SOI MOSFETs”, IEEE
Transactions on Electron D evices, vol. 36, no. 2, pp. 399-402, February 1989.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
22
21.
J.-P. Colinge, “Subthreshold slope o f thin-film SOI MOSFET”s”, IEEE
Electron D evice Letters, vol. 7, no. 4, pp. 244-246, April 1986.
22.
J.-P. Colinge, “Subthreshold slope o f thin-film SOI MOSFET’s”, IEEE
Electron D evice Letters, vol. 7, no. 4, pp.244-246, April 1986.
23.
G.A. Garcia, R.E. Reedy, “Electron mobility within lOOnm o f the Si/Sapphire
interface in double-solid-phase epitaxially regrown TFSOS”, Electronics
Letters, vol. 22, no. 10, p. 537, 1986.
24.
M. Roser, S.P. Clayton, P.R. de la Houssaye, G.A. Garcia, “High-mobility
fully-depleted thin-film SOS MOSFETs”, 1992 Device Research Conference
Proceedings, June 1992.
25.
P.M. Garone, V Venkataraman, J.C. Sturm, “Hole mobility enhancement in
MOS-gated GexSil-x/Si heterostructure inversion layers”, IEEE Electron
Device Letters, vol. 13, no. 1, January 1992.
26.
R.A. Johnson, C.E. Chang, P.R. de la Houssaye, M.E. Wood, G.A. Garcia,
P.M. Asbeck, I. Lagnado, “A 2.4GHz silicon-on-sapphire CMOS low noise
amplifier”, IEEE Microwave and Guided Wave Letters, vol. 7, no. 10, October
1997.
27.
R. Reedy, J. Cable, D. Kelly, M. Stuber, F. Wright, G. Wu, “UTSi CMOS: A
complete RF SOI solution”, Analog Integrated Circuits and Signal Processing,
vol.25, no.2, pp.171-179, November 2000.
28.
C. Wann,F. Assaderaghi, L. Shi, K. Chan, S. Cohen, H. Hovel, K. Jenkins, Y.
Lee, D. Sadana, R. Viswanathan, S. Wind, Y. Taur, “High-performance 0.07(im CMOS with 9.5-ps gate delay and 150GHz
IEEE Electron Device
Letters, vol. 18, no. 12, pp. 625-627, December 1997.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
2 High Frequency Digital CMOS
2.1 Introduction
This chapter discusses the potential o f high-speed digital CMOS circuits on
SOS and shows that dramatic increases in circuit speed can be expected. Clock rates
higher by x5 to x8 than those in use today can be expected with scaled CMOS on
SOS.
This will permit digital functions in realms that correspond to microwave
circuits today. With the increased demand for high volume RJF circuits and systems,
increasing attention is being placed on silicon MOSFET based technologies. These
technologies leverage the MOSFETs advantages o f high volume, high-density, low
power, and low cost circuits.
However, in order to meet future communication
systems requirements, advances in MOSFET technology will be required.
RF
communications systems are now being designed with an increased amount of digital
logic for digital signal processing (DSP), an application ideally suited for CMOS
technologies. In addition to the normal signal coding done by the DSP, future systems
will most likely use the DSP for real-time predistortion o f signals to meeting
increasing system linearity requirements. Other system components, however, have
more rigorous demands on the device, requiring increased performance of CMOS
devices before integration on a single chip can be achieved.
SOI and SOS technologies have the benefits o f improved scalability, improved
device isolation, improved subthreshold slope, more resistant to latch up, increased
packing density, and increased circuit speed, as mentioned in section 1.3. A common
23
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24
benchmarking tool for high-speed technologies is a frequency divider. This not only
provides an example o f the circuit speeds that can be attained by the technology, but
also is a component o f a phased locked loop, a key part o f many communication
systems. The digital frequency divider within the phase locked loop must operate at a
clock rate o f the transmission signal. In order to demonstrate the inherent speed of
scaled silicon MOSFET technology, a high-speed digital frequency divider was
designed and fabricated in bulk silicon, SOI, and SOS at IBM. Unfortunately, the SOI
and SOS circuits have not yet been successfully fabricated. However, from the results
o f the bulk silicon frequency divider it is possible to infer the results the SOS circuit
would have had. The frequency dividers resulting from this work achieved world
record performance for any MOS technology. It can be inferred that an SOS version
o f the circuit would have performed even better, as will be shown in section 2.4.
First, advantages from scaling MOSFETs and the technology used to fabricate
the frequency divider will be briefly discussed.
Next, the circuit design o f the
frequency divider will be presented. Finally, the results o f the high-speed frequency
divider will be presented and discussed.
2.2 Scaled CMOS Technology
Device and circuit fabrication was done at IBM T.J. Watson Research Center
as part o f a SPAWAR Systems Center, San Diego sponsored research program to
demonstrate the capabilities o f scaled CMOS and CMOS on SOS. The fabrication
process was a standard digital CMOS process with a minimum drawn gate length of
0.15pm , giving a 0.1pm effective gate length. The devices were made in a single n-
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25
well process, employing a 1-2 Ohm-cm p-type substrate and two levels o f
metallization. The gate oxide was 30A thick.
The devices have excellent RF
performance, as shown in Figure 2-1.
— ■— 10 x (D.15um x10um)
—o— 5 x(0.15um x 2 0 um)
100-
908070-
£
CD
X
«3
■czo
(D
6050 4030 2010-
0.0
0.5
1.0
1.5
2.0
VG (volts)
Figure 2-1. F t and F m.r of NMOS device. (Data courtesy of Keith
Jenkins at IBM T.J. Watson Research Center)
Wafers fabricated at IBM were measured at UCSD. The DC characteristics o f
the NMOS and PMOS devices are shown in Figure 2-2 and Figure 2-3 respectively.
A t a drain to source bias o f 0.6 volts and a gate to source bias o f 0.8 volts, a 0.1pm x
20pm NMOS device has a dc transconductance o f 500 mS/mm. A corresponding
PMOS device has a DC transconductance of 250 mS/mm at a drain to source bias o f 0.6 volts and a gate to source bias o f -0.8 volts. These values are very good relative
to state-of-the-art.
For comparison, BS1M3 models o f TSM C 0.25pm MOSFETs
available through MOSIS predict maximum transconductances o f 310mS/mm and
165mS/mm for NMOS and PMOS device respectively. The 0.1pm IBM devices have
a breakdown voltage o f over 3 volts. The NMOS devices have an f t o f up to 100GHz,
as shown in Figure 2-1. The PMOS devices are estimated to have a maximum A o f
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26
about 55 GHz.
As with most high-speed devices, these devices suffer from low
breakdown. However this problem can be overcome with careful circuit design.
8
^ = 0 . 1 to l.IV , Step 0.25V
Vp =0 to IV , Step 0.25V
6
<
£
2(O
4
«
2
200
0
0 .4
0.8
1.2
0 .4
Vds (Volts)
0.8
1.2
V gs (Volts)
Figure 2-2. DC characteristics o f 0.1x20pm NMOS device.
V,=-0.1 to-1.1V,Step -025V
o
E
200 -
V ^= 0 to -IV , Step -0.25V
-1 .2
-0 .8
-0 .4
-
1.2
V d s (V olts)
-0 .8
-0 .4
V gs (V olts)
Figure 2-3. DC Characteristics of 0.1x20pm PMOS device.
2.3 Frequency Divider Circuit Design
Circuits were designed and layed out at UCSD in order to demonstrate the
potential o f the technology. A frequency divider was chosen as the most appropriate
vehicle to illustrate the high-speed circuit potential. Since the process had no resistor
layer, diode-connected devices were used as active loads.
In order to achieve the
highest possible clock speed, an all NMOS design in source coupled FET logic
(SCFL) was used. The use o f SCFL made it possible to make a fully balanced design.
The layout was made as symmetrical as possible.
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27
The circuit design is similar to that o f a clocked oscillator employing two logic
stages (one o f which is inverting). The general circuit operation is depicted in Figure
2-4. In Figure 2-4A, the clock is positive, turning off the left half o f the circuit (the
shaded area o f the diagram). If the outputs o f transistors A ’ and B ’ are assumed to
start low and high respectively, this drives the circuit output and transistor B input low
while driving transistor A input high. In the next clock phase, Figure 2-4B, the right
half o f the circuit is turn off. Since the inputs o f transistors A and B were driven high
and low respectively, the outputs are now low and high respectively. This drives the
inputs o f transistors A ’ (low) and B ’ (high) while the circuit output remains low.
When the clock becomes high again, Figure 2-4C, the inputs o f transistors A’ and B ’
are still low and high respectively. This changes the outputs transistors A ’ (high) and
B ’(low), switching the circuit output. In the final diagram, Figure 2-4D, the left half
o f the circuit is off. Transistors A and B will drive the inputs o f transistors A ’ and B ’
low, such that the next clock cycle will be identical to Figure 2-4A.
For every two
full clock cycles, the circuit output goes through one cycle. This results in a 2:1
frequency divider with the clock as the circuit input.
A schematic o f the circuit is shown in Figure 2-5. The logic stages, in addition
to a main differential pair (the reading pair), contain a cross-connected transistor pair
(the latching pair) driven by the same phase o f the clock. When the reading pair o f the
logic stage begins to change state, the latching pair boosts the current to speed up the
output voltage swing. The latching pair provides positive feedback to increase the
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28
gain o f the stage. Since the latching pair does not maintain the output logic level with
the clock transistor off, this circuit is a dynamic divider.
VsT
Vs2*
VS3
(A)
vsr
VsZVss
(B)
!D—A
Vs2Vss
(C)
vsr
V s2-
Vss
(D)
Figure 2-4. Operation o f 2:1 frequency divider circuit.
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29
Out
Out
I_____
cue
cue
Vss
Figure 2-5. Circuit schematic o f frequency divider circuit.
Latching stage enclosed with dashed boxes.
The size o f the circuit was limited by the size o f the probe pads. The circuit
was placed as close to the output pads as possible (to reduce the loading on the output
buffer) with coplanar lines connecting the clock pads to the circuit input.
A die
photograph is shown in Figure 2-6. Although the size o f the circuit is 830pm x
780pm , the flip-flop takes up only 97pm x 66pm o f space while the current sources
take up 80pm x 79pm. The output buffer has dimensions 110pm x 90pm.
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30
Figure 2- 6. Die Photograph of frequency divider circuit.
Simulations indicate that the rise and fall times o f the logic stage vary roughly
inversely with the ratio o f WL to WR. Figure 2-7 illustrates the decrease in rise time
o f a clocked latch driving a large capacitive load as the WL to W R ratio is increased.
For increasing values o f WLAVR, power dissipation increases. The width o f the nMOSFETs used in the reading pair was 24pm (WR) and that o f the latching transistors
was 9pm (WL). This gives a WLAVR value of 0.375, which provides a boost in speed
with only a moderate increase in power.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
31
'
ffl
cn
220
3
2.15
'
2.10
•g
2.05
WL7WR=0
WL/WR=0.375
WL/WR=0.9
WL/WR=1.2
zoo
3.0
3.5
4.0
4.5
Time (nS)
Figure 2-7. Rise time o f output voltage for different WL to WR
ratios with a large capacitive load.
The circuit design shares many features with the dynamic HLO-FF [1]
frequency divider.
The HLO-FF makes use o f stages which contain reading and
latching pairs o f different width.
However, in HLO-FF dividers the reading and
latching transistor pairs are driven with different phases o f the clock, and in the limit
as WL/WR approaches 1, the circuit becomes a conventional static divider. This is
not the case in the present design.
The outputs o f SCFL circuits are referenced to Vdd- To reduce potential effects
o f line bounce on Vdd, Vdd was made to be ground, and all other voltages are negative.
A negative bias was applied to the p-substrate in order to prevent leakage currents.
The top rail o f the current source is connected to a pad rather than ground, so that the
current through the flip-flop can be adjusted. To be able to adjust the output buffer
independently o f the flip-flop, the bottom rail o f the output buffer has its own Vss pad
separate from the rest o f the circuit. Voltages Vsi and V S2 in Figure 2-5 are generated
on chip with a cascode current source.
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32
2.4 Measurement Results and Analysis
Tests were performed on wafer. High-speed signal-ground-signal probes were
used for the clock input and the divide by two output. Power probes with bypass
capacitors close to the probe tip were used to provide DC biasing. A DC bias voltage
was provided as reference to both inputs. One o f the inputs was also fed with the
clock input while the other input was AC terminated off-chip with 50Q to ground.
The output signal was measured differentially with an external 180° hybrid. —lOdB
couplers were used on the input and output to plot the input waveform and measure
the output spectrum respectively.
An HP54120 50GHz oscilloscope was used to
measure the waveforms, while an HP8565E spectrum analyzer was used to measure
the output spectrum. A schematic o f the test setup is shown in Figure 2-8.
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33
HP83752B Synthesized
Sweeper
oscilloscope
Frequency=(clock frequency)/2
10MHz reference out
RF out
Channel 1 I Channel 2
HP8340A Synthesized
Sweeper
Frequency==clock frequency
10MHz reference in
RF out
-lOdB
2:1 frequency
divider
Hybrid
Combiner
-10dB
HP8S65e spectrum
analyzer
RF in
10MHz reference in
T
Figure 2-8. Test setup for frequency divider.
The input sensitivity versus input frequency is shown in Figure 2-9. For most
o f the bandwidth, the divider needs a single ended input power o f about OdBm to
operate. This is within ±4dB o f the input power needed by other reported dynamic
frequency dividers that do not have an input buffer to amplify the clock signal [1, 2,
3]. Many frequency dividers have a null in input power versus frequency where the
divider self-oscillates. Although this dynamic divider does not self-oscillate, the dip
in required input power shows it to be close to oscillating at 26GHz. Figure 2-10
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34
shows DC power consumed by the flip-flop plus current sources versus frequency and
the DC power consumed by the output buffer versus frequency.
For input clock
frequencies up to 20GHz, the flip-flop and current sources use less than 26mW o f DC
power. This power is substantially lower than that used in many other high-speed
frequency dividers. At the maximum frequency o f 26.5GHz, the flip-flop uses 90mW
o f DC power. Figure 2-11 shows the input clock waveform at 26.5GHz and the divide
by two output waveform. Although the maximum clock frequency is much slower
than clock speeds up to 80GHz achieved with compound semiconductor HBTs and
HEMTs or with SiGe HBTs [2, 3, 4, 5, 6], it is a record clock frequency for silicon
MOSFETs. It is also important to note the higher power consumption o f the HBT and
HEMT technologies.
The logic core o f the HBT and HEMT frequency dividers
typical uses 500-1000mW o f power at the highest clock frequency.
The power
consumption o f the MOSFET frequency divider is only 90mW at the highest clock
frequency, considerably less power than its HBT and HEMT counterparts.
10
Q- -15
-20
-25
5
10
15
20
Frequency (GHz)
25
Figure 2-9. Minimum single-ended input power required by
circuit.
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35
450
_ 375
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1
1!
i
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1 300
9 225
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15
25
20
Frequency (GHz)
Figure 2-10. DC power consumed by output buffer (top) and by
logic core plus current sources (bottom)
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V
- 0 .0 2 -
-0.03 20.25
20.30
20.35
Time (nS)
20.40
Figure 2-11. Input (top) and output (bottom) waveforms with
clock of 26.5GHz.
Measurements o f the frequency range and output power agree well withi circuit
simulations.
The simulations show correct operation o f the circuit from 6G H z to
25GHz. The simulated output power is within ldB o f the measured output power.
The relatively low measured output power can be attributed to the very simple output
buffer design used. The output buffer was designed primarily to buffer the divider
from the large pad capacitance and provides attenuation rather than voltag<e gain.
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36
Simulations indicate that the on-chip differential voltage swing in the divider core was
250mV for operation at 25GHz (and up to 600mV at 20GHz).
2.5 Estimated Performance o f SOS MOSFET Circuits
Although this is the fastest known digital MOSFET frequency divider, the SOS
version o f the circuit would have been faster. The speed o f the SOS version can be
estimated by either an examination o f the node capacitance o f logic core o f the
frequency divider or by spice circuit simulations using the SOS device models.
To analyze the node capacitance, the interconnect capacitance to bulk,
interconnect capacitance between parallel lines, the transistors’ input capacitance, and
the transistors’ output capacitance were estimated.
The capacitance to bulk and
capacitance between parallel lines were calculated as described by Bama to take the
fringing capacitance into account [7].
A comparison between the estimated
capacitances o f bulk silicon and SOS is shown in Figure 2-12. In bulk silicon, the
interconnect capacitance is dominated by the capacitance to bulk, hi SOS circuits, the
interconnect capacitance is dominated by fringing between parallel lines. With narrow
interconnect lines placed close together, the two technologies have almost the same
amount o f interconnect capacitance. The main advantage o f SOS is the reduced drain
and source capacitance. This gives about a 25% lower node capacitance for SOS over
bulk silicon. It can be estimated that the maximum clock rate is roughly linearly
proportional to the node capacitance. So the SOS circuit would have operated 25%
faster than the bulk silicon circuit, up to a clock frequency o f 33GHz.
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37
B Interconnects
glGate Capacitance
B Drain-Bulk &
Source-Bulk
Bulk
SO S
Figure 2-12. Estimated node capacitance in frequency divider flipflop.
Spice models estimating the expected performance o f the SOS devices were
also made.
The frequency divider was simulated with the SOS models.
The
interconnect parasitics were left the same as for bulk silicon, based on the estimates
that the interconnect loading should be about the same for the two technologies.
Using the SOS models, the circuit operates up to a clock frequency o f 31.5GHz, 26%
faster than the circuit simulates with the bulk silicon MOSFET models. It is therefore
expected that the SOS frequency divider should have operated up to clock frequencies
o f 30-33GHz, breaking the barrier in the mm-wave regime.
2.6 Conclusions for Chapter 2
A bulk silicon divide-by-two dynamic frequency divider with maximum clock
speed o f 26.5GHz has been achieved. The dynamic divider operates from 6.5GHz to
26.5GHz. This is the fastest frequency divider in CMOS technology reported to date
This demonstrates the ability o f circuits based on scaled CMOS technology to achieve
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38
clock speeds over 20GHz. It has also been shown that a mm-wave circuit utilizing
SOS MOSFETs is possible.
As technology continues to evolve, further scaling o f the SOS MOSFETs can
provide even greater speeds. Ultra high-speed digital circuits in SOS can be used to
meet the demands o f current and future applications into the mm-wave regime.
2.7
References
1.
K. Murata, T. Otsuji, E. Sano, M. Ohhata, M. Togashi, M. Suzuki. “A novel
high-speed latching operation flip-flop (HLO-FF) circuit and its application to
a 19-Gb/s decision circuit using a 0.2pm GaAs MESFET”, Journal o f SolidState Circuits, Oct. 1995, vol. 30, no. 10, pp. 1101-1108.
2.
B. Tang, J. Notthoff, A. Gutierrez-Aitken, E. Kaneshiro, P. Chin, A. Oki, “InP
DHBT 68GHz frequency divider”, GaAs IC Symposium, October 1999, pp.
193-196.
3.
K. Murata, Y. Yamane, “74 GHz dynamic frequency divider using
IhAIAs/InGaAs/InP HEMTs”, Electronics Letters, vol. 35, no. 23, pp. 20242025.
4.
H. Nakajima, E. Sano, M. Ida, S. Yamahata, “80GHz 4:1 frequency divider IC
using non-self-aligned InP/InGaAs heterostructure bipolar transistors”,
Electronics Letters, January 2000, vol. 36, no. 1, pp. 34-35.
5.
M. Wurzer, T.F. Meister, H. Knapp, K. Aufinger, R. Schreiter, S. Boguth, L.
Treitinger, “53GHz static frequency divider in a Si/SiGe bipolar technology”,
LEEE International Solid-State Circuits Conference, February 2000, pp. 206207.
6.
K. Washio, e. Ohue, K. Oda, R. Hayami, M. Tanabe, H. Shimamoto, t. Harada,
M. Kondo, “82GHz dynamic frequency divider in 5.5ps ECL SiGe HBTs”,
IEEE International Solid-State Circuits Conference, February 2000, pp. 210211.
7.
A. Bama, VHSIC: Very High Speed Integrated Circuits Technologies and
Tradeoffs, 1st Edition, Chapter 1, John Wiley and Sons, New York, 1981.
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39
2.8 Acknowledgements
Some o f the material in this chapter is as it appears in "A 26.5 GHz Silicon
MOSFET 2:1 Dynamic Frequency Divider", IEEE M icrowave and Guided Wave
Letters, Oct. 2000, vol. 10, pp. 421-423. I would like to acknowledge the co-authors
L. Shi, K. Jenkins, P.R. de la Houssaye, Y. Taur, P.M. Asbeck, I. Lagnado. I was the
prim ary investigator and primary author for this publication.
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3 Largefet Device Design and Characteristics
3.1 Introduction
As transistor gate lengths are scaled down, the breakdown voltage o f the
transistors drop. This creates a large problem for power applications. If the voltage
must remain low, the only way to achieve high power output is to scale up the output
current. This leads to MOSFETs with very large gate widths. However, as the gate
width is scaled up to increase power, the microwave gain o f the transistor drops. The
growing wireless communications industry not only requires high power amplifiers (in
the range o f lOmW to 1W), but also high power added efficiency for extended battery
fife. Power added efficiency is degraded by low gain in amplifiers. It is therefore
important to make large periphery transistors that not only provided adequate output
power, but also provide the best possible microwave power gain. This is equivalent to
achieving the highest possible
H i g h i s also a requirement for more advanced,
higher frequency circuits and systems.
It is believed that the layout parasitics o f the device strongly influence the
behavior o i f t and
as gate width is scaled up, although the effects are not well
understood. This chapter discusses the major design issues faced when d esigning a
large periphery device, different layout strategies that were designed and fabricated in
order to improve the high frequency response o f the MOSFETs, and the results from
these different designs.
40
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41
3.2 Large Device Design Considerations
Even, though a large periphery transistor is effectively only a single transistor,
there are m any design issues to consider. The interconnects, as well as the individual
device fingers, have a major impact on the performance o f large transistors. Given the
equivalent small circuit model o f a MOSFET shown in Figure 3-1, it can be shown
that
'
2 k {C ^ + Cgd)
(3-1)
(3-2)
Equation 3-1 is for the case when Rg=Rs=Rd=0. Equations 3-2 and 3-2 do not
hold for the complex case o f a large transistor, but they do demonstrate the important
device characteristics for high frequency operation. For high/i, the transconductance,
gm, must be maximized while the gate to source capacitance, Cgs, is minimized. With
a high f , high/max can be achieved by reducing the gate resistance, Rg, and reducing
the gate to drain feedback capacitance, Cgd.
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42
<m
Figure 3-1. Small signal model of a MOSFET.
In trying to m in im ize these parameters, the origin o f the problem o f designing
a large periphery transistor can be seen. For a single finger device, minimizing the
geometry o f the finger invariably attains the highest RF performance. However, by
using the minimum gate width, an prohibitively large number o f gate fingers will be
needed to attain the desired effective gate width.
This will require an excessive
amount o f interconnects to wire all o f the individual gate fingers. With a metal T-gate,
the RF performance o f SOS MOSFETs remains high, even for gate widths o f 50pm or
larger.
For a 50pm wide gate finger the gate resistance is roughly 200Q for a
polysilicon gate compared with about 2C1 for metal T-gate. It is therefore possible to
make wider gate fingers in this process than standard silicon MOSFET processes.
This will cause the transistor area to become very large and will lead to larger
distances between the active device and the bond pads. The self-inductance o f a wire
can be approximated with the rule o f thumb o f InH/mm length. For reasonable wire
geometries, this is usually within 10% to 15% o f the self-inductance calculated with
the equations outlined by Greenhouse [1]. This means if the distance from the active
area to a source pad increases by 100pm, the source inductance will increase by
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43
O.lnH. At 2GHz this will lead to an impedance o f 1.25Q, and 6.28Q at 10GHz. This
source degeneration leads to a decrease in the transconductance given by
S ’m = , J 7m —
l + Z s&m
(3‘3)
where gm is the transistors intrinsic transconductance, g’m is the transistors extrinsic or
measured transconductance, and Zs is the source impedance. The drop in f t and
however, is subtle and is not conveyed by equation 3-3.
On top o f the problems o f additional inductance and resistance, the increased
area o f a large transistor will m ost likely cause power combining problems,
hi
realistic large transistor layouts, there will be some device fingers that are closer to the
input and output pads, and others that are farther away. This will cause a relative
phase difference between the signals arriving at the output pad, as shown in Figure
3-2. Signals that are out o f phase will not combine to produce that maximum power.
Some o f the power will be lost in destructive power combining. The power lost due to
destructive power combining o f two sine waves is illustrated in Figure 3-3. From
Figure 3-3, it can be seen the phase difference should be kept less than 15 degrees to
avoid significant power loss. Assuming the wavelength is determined by the dielectric
constant o f the interlevel dielectric material (in chapter 5 this will be shown to be an
inadequate estimate), then with SiC>2 as the interlevel dielectric material the maximum
path difference can not exceed roughly 630pm at 10GHz. As the frequency increases,
the phase difference between two fixed paths will increase, exacerbating the problem
as the frequency o f operation increases.
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44
Drain
I do
CO
CO
Idoe
-jeo(Ti+T2)
CO
CO
CO
V.
Gate
Figure 3-2. Simplified schematic of transistor layout showing delay
that can cause destructive power combining.
0
m
T3
CD
T3
-
0.1
-
0.2
-0.3
CD
O
)
CU
-0.4
T3
CD
5o
CL
J_____
-0.5
-
0.6
-0.7
0
10
20
30
40
P h a se difference (d egrees)
Figure 3-3. Power lost from combining two sine waves that are out
o f phase.
In addition to increased parasitics and destructive power combining, a
transistor that uses too large an area many have stability problems. If the length o f the
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45
gate, drain, or source interconnects becomes on the order o f a wavelength at a
frequency where the transistor has high gain, the structure may oscillate under all
matching conditions. The long interconnects combined with a transistors inherent
gain and feedback may lead to instability.
Without special care taken to damp
oscillations between opposite ends o f the transistor structure, the transistor may
become unusable. However in the studies presented in this thesis, the devices were
not large enough in area for this to be a concern.
There are also many technology dependent variables that must be considered
relating to how the transistor interconnects will be fabricated. It is import to know
what type o f metal will be used and how thick the metal will be, as well as the
resistance associated with vias and contacts.
The type o f metal being used is
important for issues o f electromigration and allowed current densities.
This is
particularly important in large transistors, where peak currents o f over 1 amp are
routine. The type o f metal and its thickness will help determine the minimum width
required to carrier the expected current levels.
The type o f metal will also determine how much o f a problem the skin-effect
will be. At high frequencies, most o f the current will be carried only by a thin section
o f the metal’s surface, or skin. Aluminum metalization is used in silicon processing.
This has a greater skin effect than the gold metalization used in TTT-V processing. This
causes the effective cross-section to decrease, and the resistance and loss to increase
with increasing frequency. So an interconnect that provided a low resistance at low
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46
frequency may be inadequate at microwave frequencies if the skin-effect has been
ignored.
M any o f the problems ju st described can be greatly reduced if the technology
has a backside via process available to the designer. Backside vias etch through the
substrate and connect the front side to a backside ground plane. This can be done
anywhere on the chip, providing an excellent source ground wherever it is needed,
even in the middle o f the chip. Unfortunately, the chemical and mechanical stability
o f the sapphire substrates makes this incredibly difficult to accomplish with SOS. It is
very difficult to etch sapphire under any circumstances, and for SOS it m ust be done
without any damage to the active silicon film on the sapphire substrate.
In addition to these problems is the problem o f device self-heating. Because o f
the large amounts o f power dissipated by large transistors, they can heat up
considerably, degrading device performance. It is important to note that as the area
used by a transistor decreases, to minimize interconnect parasitics and power
combining problems, the self-heating will tend to increase. This topic will be covered
in detail in chapter 4.
3.3 Device Design
As discussed in the previous section, the interconnects can effect the device
performance through addition o f parasitic capacitance, resistance and inductance. The
style o f layout and the design o f the individual gate finger, or unit cell, greatly effects
the overall size o f the transistor and therefore the amount o f parasitics. Although the
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47
parasitics can not be altogether eliminated, there are tradeoffs that can be made in the
design o f a large transistor.
Three types o f layouts were designed, fabricated, and tested in an effort to
improve and better understand RF performance o f the large periphery devices. The
three different styles o f layouts all have tradeoffs in parasitic.
The first was the
standard layout used for a benchmark. This layout tries to minimize the interconnect
capacitance. The second layout style was a waffle layout. The waffle layout has the
advantage o f a very compact design. The last layout style that was fabricated and
tested is called the spaceship layout. This layout was made to reduce source parasitics
and give a more compact layout than the standard layout. All o f the layouts and
results presented in this chapter are for devices with an effective gate length o f
0.35|xm (0.5pm drawn) and an aluminum metal T-gate.
3.3.1
Standard Layout
The first layout style made is referred to here as the standard layout. This is
the layout style that was used in a previous study o f device performance and is
included here as a means o f comparison. The layout is sometimes referred to as a fish­
bone style layout. As shown in Figure 3-4, the main drain bus runs down the middle
o f the layout with connections coming outwards. The layouts o f this style where made
to minimize the parasitic overlap capacitance o f the interconnect lines.
Due to the reduction in interconnect crossovers, the standard layouts are not
very compact.
However, due to the insulating substrate in SOS technology, the
increased area does not translate into increased capacitance to the substrate.
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The
48
individual gate fingers all have gate widths o f 50pm. MOSFETs o f this style were
designed and fabricated with effective gate widths o f 600pm, 2400pm, and 4400pm.
These transistors together with their probe pads take up areas o f 250pm x 275pm,
600pm x 450pm, and 600pm x 750pm respectively.
Drain
H lillllillll
o
Figure 3-4. Standard layout. Left: diagram of interconnect
strategy. Right: Die photograph o f standard device with 4400pm
effective gate width.
Although the larger area o f this layout style does not incur extra capacitance
from the substrate, the larger area can cause problems with power combining. As
discussed in section 3.2, it is important to keep the phase difference below 15 degrees.
This effect will be described in more detail in chapter 5.
3.3.2
Waffle Layout
The waffle layout strategy gets its name from the square waffle like pattern
made up by the polysilicon gates, as shown in Figure 3-5. The gate fingers can only
be connected to the gate input at the edges o f the square pattern. This is due to the fact
that the interior o f the square pattern is used to connect to all the drain and source
diffusion regions, leaving no room for a polysilicon contact. Each alternate square is
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49
either a drain or a source region. While the gates are connected from the exterior o f
the square, the drain and source connections must be made with diagonal lines coming
out from the center o f the active silicon region.
Due to the compact nature o f this layout, the waffle style MOSFETs are much
more compact than the standard layouts.
This results in a reduction o f phase
difference from different gate fingers, and therefore a reduction in the destructive
power combining. In addition to reducing the phase delay, the more compact layout
should result in lower parasitic inductance and resistance in the interconnects.
However, at the same time, the reduced size causes an increase in the capacitance and
mutual inductance between interconnect lines.
The waffle layout also has many
parallel, closely spaced, drain and source lines, which can lead to a significant mutual
inductance, possibly canceling out the benefits o f the lower inductance due to shorter
interconnects.
All waffle style MOSFETs were designed with a unit gate width o f 20pm per
side o f each source and drain square. Waffle style MOSFETs with effective gate
widths o f 240pm, 620pm, 2130pm, 4160pm, and 4320pm. The transistors plus probe
pads take up an area o f 250pm x 375pm, 250pm x 375pm, 400pm x 375pm, 450pm x
400pm, 375pm x 525pm respectively. The 4320pm waffle transistor only uses 44%
o f the area o f the 4400pm wide standard layout.
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50
Figure 3-5. W affle Layout Left: diagram of interconnect
strategy. Right: die photograph o f waffle device with 4320pm
effective gate width.
The waffle layout also has a unique property when examining the gate
resistance, which is important for high frequency power gain. Even though the gate
can only be contacted at the outer edge o f the waffle structure, the gate resistance does
not increase as the size o f the square is increased. This is due to the multiplicity o f
paths to get to any point along the array o f gate fingers. If the waffle remains square,
the resistance will remain a constant.
It is important to note, however, that as the effective gate width o f the structure
increases, there comes a point when the square geometry o f the waffle can no longer
be maintained. This is due to current density limitations in the drain and source lines.
Eventually, the square structure must give way to a more rectangular structure so that
each drain and source lines are not connected to more transistors than they can handle.
The 4320pm wide waffle MOSFET shown in Figure 3-5 breaks the current density
rules for the source and drain lines. The 4120pm wide waffle MOSFET is m uch taller
and narrower, to avoid the current density problem.
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51
3.3.3
Spaceship Layout
The third layout strategy that was fabricated is referred to as the spaceship
layout. This style o f layout derived its name from the resulting layout o f the 2400pm
size device shown in Figure 3-6. The overall structure is similar to that o f the standard
layout. However, the source connections where made directly over the top o f the
active silicon area.
Doing this allowed the source connections to be very wide,
reducing the source inductance and resistance. Although this leads to increased gatesource and drain-source capacitance, it avoids increasing the feedback capacitance
between the drain and gate interconnects. This layout style is also more compact than
the standard layout, reducing power combining problems due to differing phase delays
o f the different gate fingers.
The spaceship layout is a compromise between the
standard and waffle layouts. It has reduced source parasitics and reduced area from
the standard layout. But it is not as compact as the waffle layout, leading to lower
interconnect capacitance and lower mutual inducatances.
The individual gate fingers have a width o f 50pm, the same as the standard
layouts.
The total effective gate widths o f the spaceship transistors are 2400pm,
3600pm, and 3900pm. The total area used by these transistors plus their probe pads is
575pm x 425pm, 575pm x 525pm, 575pm x 525pm respectively. The 3900pm wide
spaceship layout uses only 67% o f the area o f the standard 4400pm wide transistor.
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52
D rain ^
S Q H ceJ ^ ^ H c
•Q:
Gate
Figure 3-6. Spaceship layout. Left: Diagram of interconnect
strategy. Right: Die photograph o f spaceship device with 2400pm
effective gate width.
As can be seen in Figure 3-6, the 2400pm spaceship layout is made from four
active silicon regions (each highlighted by a horizontal source connection). In going
from 2400pm to 3600pm, two more o f these active regions were added, as can be seen
in the left half o f Figure 3-7. In the 2400pm and 3600pm wide spaceship transistors,
the gate feeding structure connects first to the gates closest to the drain bus,
connecting last to the gates farthest from the drain bus. This has the effect o f creating
a large phase difference between the first and last gate finger.
In the right half Figure 3-7 a die photograph o f a 3900pm spaceship transistor
is shown. In the 3900pm wide transistor, the gate feeds first to the fingers farthest
from the drain bus. Although this increases the length o f the gate line, increasing
resistance and inductance, it will lead to a decrease in the phase difference from the
different gate fingers because the output power is traveling in the same direction as the
input power. The 3900pm transistor also has extra source metal that crosses over the
drain and gate interconnects. This extra source metal provides a shorter path to the
ground pad, reducing the source parasitics at the expense o f higher gate-source and
higher drain-source capacitance.
Not shown is a second version o f the 3900pm
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53
spaceship transistor which has approximately twice the width o f metal crossing over
the drain and gate interconnects to the source probe pads.
Figure 3-7. Left: 3600pm spaceship transistor with gate feeding
from the middle. Right: 3900pm spaceship transistor with gate
feeding from the sides.
3.4 RF Measurements
3.4.1
Measurement approach
Measurements were carried out on wafer using high-speed ground-signal-
ground probes. Special custom bias tee’s were used to provide a DC bias. The bias
tee’s are capable o f handling 2 amps o f DC current with only 0.15Q series resistance,
and have an RF bandwidth o f 20GHz. Small signal parameters were measured using
an HP8510 network analyzer.
Even with the low series resistance, however, special care must be taken to
ensure the voltage drop in the cables, bias tee’s and probes do not effect the
measurements. In order to ensure correct biasing o f the transistors, a DC needle probe
was placed on the probe pad to measure the actual pad voltage. The power supplies
were then adjusted to give the proper biasing on the transistors and the needle probes
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54
were removed before high frequency data was taken. The NMOS devices typically
had maximum^/t at a bias o f about 2 volts on both the drain and the gate. The PMOS
devices had a higher threshold voltage and the maximum yi was typically achieved
with a bias o f about —2.5 volts on both the gate and the drain.
3.4.2
Results
The devices were characterized for speed by using the small signal data to
measure th e /t andj^ax o f the devices. The results for the NMOS and PMOS devices
are shown in Figure 3-8 and Figure 3-9 respectively. From the graphs o i f t andfm x
versus gate width, it can easily be seen that the different layout strategies did not have
the desired effect o f mitigating the rolloff o f RF performance.
The 100pm wide
NMOS device has an/max o f approximately 40GHz, while the 4.4mm devices have an
/max o f approximately 8GHz. The 240pm waffle PMOS device has an/max o f 17GHz
compared to 26GHz for the 240pm waffle NMOS. However, the 4320pm waffle
layout hasy^nax o f 8Ghz for the NMOS device and 6GHz for the PMOS device. As the
device gate width increases, the f and
becomes more dependent on the layout
characteristics than the device itself
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55
20
45
1 5 -------->
30 • 12
25 • -A
O
|
10
S p » c« » h tp
0
1000
2000
3000
4000
lb
20
15
0
5000
1000
G a te W idth (u m )
2000
3000
4000
5000
G a te W idth (urn)
Figure 3-8. F t and F max versus gate width for NMOS devices.
Measured with Vds=Vgs=2.0 Volts.
20
12
18
10
14
oX
ox
u.
- a —S p a c a a h ip
12
10
8
6
4
2
0
0
1000
2 000
3000
G a te W idth (um )
4000
5000
0
1000
2000
3000
4000
5000
G a te W idth (um )
Figure 3-9. F t and F max versus gate width for PMOS devices.
Measured with Vds=Vgs=-2.5 Volts.
Although the rolloff o f /max was not changed much by the different layout
strategies, the f
rolloff wad mitigated some by the spaceship style layout.
In
particular, by looking at the variations o f the 3600pm and 3900pm wide NMOS
spaceship transistors, a rise in ft can easily been seen. The differences in these layouts
are the reduction in phase delay between the gate fingers and the addition o f extra
source metal. In addition, there are two 3900pm NMOS spaceship style devices. The
3900pm device with the larger amount o f extra source metal is the one with the higher
ft <*nd/max-
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56
Although the different styles o f layouts have pros and cons in term o f reduced
interconnect capacitance or reduced self inductance, the overall performance o f the
different styles did not vary much. The largest deviations from the general trend came
from connecting the gate lines o f the spaceship devices to reduce phase delay and by
adding more source metal at the expense o f overlap capacitance. The difference in
phase delay will be explored in more detail in chapter 5.
3.5 Conclusions for Chapter 3
Three different styles o f layouts were proposed, fabricated, and tested in an
effort to mitigate the rolloff o f ^
with increasing gate width and to gain a
better understanding o f how the layouts effect the RF performance.. The only layout
that mitigated the rolloff o f ^ was the spaceship layout that also tried to m in im iz e
phase delay and further reduce the source parasitics. The behavior of/max, however, is
more complicated and needs to be studies further.
The improvement in f and
is very important for the design o f power
transistors with high gain. An analytical study o f the behavior o f ft and^/max will be
presented in chapter 5.
3.6 References
1
H. M. Greenhouse, “Design o f Planar Rectangular Microelectronic Inductors”,
IEEE Transactions on Parts, Hybrids, and Packaging, vol. 10, no. 2, June
1974, pp. 101-109.
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57
3.7 Acknowledgements
Some o f the material in this chapter is as it appears in "Prospects o f CMOS
Power Amplifiers on Thin Film SOS for Wireless Applications," F irst Annual UCSD
Conference on Wireless Communications, San Diego, CA, March 1998. I would like
to also acknowledge the co-authors o f this publication R.A. Johnson, P.F. Chen, B.
Xavier, P.R. de la Houssaye, P.M. Asbeck, I. Lagnado.
I was also the primary
investigator and primary author o f this paper.
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4 Thermal M odeling o f CMOS on Sapphire
4.1 Introduction
Self-heating is a possible source o f performance degradation in large periphery
transistors. Self-heating is a known problem for SOI devices [I, 2]. The thin buried
oxide layer in SOI acts as a thermal insulator, causing the devices to heat up much
more than similar devices in bulk silicon. SOS devices do not have a buried oxide
layer, however, the sapphire substrate has only about one-third the thermal
conductivity o f bulk silicon. This chapter discusses the self-heating effects o f SOS
MOSFET’s and the possible impact this will have on RF performance.
hi addition to trying to explain the drop in RF performance, it is important to
understand the issues of thermal management for circuit applications. It is important
to know if the thermal dissipation is a major impediment to potential circuit designs
and to know what impact the thermal dissipation may have on other neighboring
components. For system-on-a-chip solutions, it is important to understand if the high
power circuitry will cause too much self-heating for the other modules on the chip.
This chapter will first briefly describe the effects self-heating has on a
MOSFET and the possible signs o f self-heating in measured SOS devices. Next a
comparison o f the thermal resistance o f SOI and SOS will be presented. Then results
from thermal resistance simulations and thermal resistance measurements in SOS
MOSFETs will be discussed. Next device measurements at various temperatures will
be presented to show the temperature dependence o f SOS MOSFETs is the same as
58
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59
the temperature dependence o f bulk silicon MOSFETs. Finally, the impact o f thermal
effects on DC and RF characteristics o f the SOS MOSFETs will be discussed.
4.2 Effects o f Self-Heating
With poor thermal management o f a device, self-heating can have detrimental
effects on a device’s DC and RF characteristics.
Self-heating can cause the DC
current density (Amps/mm o f gate width) to drop dramatically, while degrading the
RF performance. Figure 4-1 shows a simulation o f the DC characteristics o f an SOS
MOSFET with and without self-heating effects.
At high current and high drain
voltage, the power being dissipated by the device is causing it to heat up, resulting in a
noticeable drop in the DC current density at a fixed Vgs- This leads to a decrease in
the output conductance o f the device. If the self-heating is severe enough, it will cause
the current to drop with increasing drain voltage, giving a negative output resistance.
A quick examination o f the DC output conductance is a quick yet effective method of
testing for self-heating problems. Figure 4-2 illustrates the effect temperature has on^t
o f a silicon MOSFET.
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60
120
100
-
80 - -
Without Self-Heating
<
E 60
■ With Self-Heating
40 20
-
0
3
2
1
Vds (Volts)
Figure 4-1. Simulated MOSFET I-V curves with and without selfheating (thermal resistance is 300W/K).
£
13 -
E
12-
O
20
40
60
80
Temperature (Celsius)
Figure 4-2. Simulated F t versus temperature for silicon MOSFET.
To understand self-heating effects on the DC and AC characteristics o f a
MOSFET, the two most important temperature dependent parameters are the carrier
mobility and the saturation velocity o f carriers in the semiconductor. In short channel
devices, the electric fields are very high, causing carriers to quickly reach the
saturation velocity. In saturation, the drain current for a short channel MOSFET can
be approximated by
ID sat = W g C Q{Vg — Vth \>sat
(4 -1 )
where Wg is the gate width, C0 is the gate capacitance in farads per unit area, Vg is the
applied gate bias, Vth is the threshold voltage, and vsat is the saturation velocity. From
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61
equation 4-1 it is easily seen that the saturation drain current for a short gate length
MOSFET does not depend on the mobility. It only depends on saturation velocity.
The saturation velocity o f carriers is limited by optical phonon scattering.
The
saturation velocity o f electrons in silicon is given as a function o f temperature by the
equation [3]
For temperatures close to room temperature, this can be approximated by the equation
n -0.701
ref
It can be shown th a t^ is inversely related to the transit time o f carriers through
the channel o f a MOSFET. For saturated short channel MOSFETs, the transit time
will be proportional to the saturation velocity. It is therefore easy to combine the
temperature dependence o f the saturation velocity with the transit time across the
channel to predict the temperature dependence o f f t.
In the linear region, the electric fields in the channel are not strong enough to
saturate the carrier velocities. Under this case, current transport is dependent on the
carrier mobility, not the saturation velocity.
The carrier mobility is limited by
scattering with acoustic phonons. In theory, the low field mobility should decrease
with temperature as ~(T)'3/2, however the measured dependence on temperature
deviates from this due to other scattering mechanisms such as impurity scattering.
The carrier mobility is much more sensitive to temperature than the saturation
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62
velocity. The mobility has been found to vary as T
and T '
for n- and p-type
sihcon respectively [4]. This is a much stronger dependence than the T*0'701 for the
saturation velocity. Li the linear region, a MOSFET’s transconductance and drain
current are linearly proportional to the channel mobility. These leads to much stronger
temperature dependence for long channel devices than for short channel devices, as
the electric field is reduced in long channel devices.
Thus high performance
microwave MOSFETs usually retain their performance better with temperature than
slower long channel devices.
A secondary effect that tends to cancel some o f the drop in DC current is the
change in threshold voltage. As the temperature o f the device increases, the fermi
level in the channel changes. It is well known that the fermi level tends toward the
middle o f the bandgap as temperature increases. This has the effect o f reducing the
flatband voltage and causes a decrease in the threshold voltage. As will be shown in
section 4.6, the change in threshold voltage is slight, only about lOmV for a
temperature rise o f 30°C.
4.3 Evidence o f Self-Heating in SOS
It is important to examine the data taken from SOS MOSFETs to see if there is
evidence o f self-heating. As the gate width is scaled up, more power being dissipated
by the device in a relatively small area. Because o f the thermal interaction o f the gate
fingers, the thermal resistance does not scale linearly with gate width.
So larger
transistors have a slightly thermal resistance per unit gate width. If the bias conditions
are held constant, larger transistors will heat up more. As the transistor heats up, the
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63
current density will drop. This leads to a very simple test to for self-heating, simply
comparing the DC current densities (in mA/pm) o f different size devices.
I f the
devices do not exhibit any self-heating effects, the current density should not change
for different size devices. The current density for the transistors is shown in Figure
4-3, Figure 4-4, and Figure 4-5 for a fixed Vgs=2V.
0.25
0.20
E
— 100um unit cell
-»-600um Standard
-»-2400um Standard
-*-4400um Standard
0.15
e
g
3
o
0.10
k_
CO
Q
0.05
0.00
0
2
1
3
Vds (Vgs=2)
Figure 4-3. Current density comparison for 100pm, 600pm,
2400pm, and 4400pm NMOS standard layout transistors (data
corrected for series resistance in measurement setup).
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64
— 100um unit cell
-» -2 4 0 u m Waffle
-* -6 2 0 u m Waffle
-•-4 1 6 0 u m Waffle
-» -4 3 2 0 u m Waffle
E 0.15
O 0.10
0.05 -
0
1
2
3
Vds (Vgs=2)
Figure 4-4. Current density comparison for 240pm, 620pm,
4160pm and 4320pm NMOS waffle layout transistors (data
corrected for series resistance in measurement setup).
— 100um unit cell
E 0.15
-*-2400um Spaceship
-»-3600um Spaceship
O 0.10
-*-3900um Spaceship
-*~3900um Spaceship
(extra source meta)
0
1
2
3
V ds(V gs=2)
Figure 4-5. Current density comparison for 2400pm, 3600pm, and
3900pm NMOS spaceship layout transistor (data corrected for
series resistance in measurement setup).
These measurements show that the current density is dropping as the gate
width is increased. The results suggest that there is a measurable self-heating effect.
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65
However, the comparison o f characteristics must be examined carefully since other
effects can influence the results. B y examination o f the current for VdS< l V, it can be
seen that the 100pm unit cell transistor has less drain and source resistance than the
other structures. This is an artifact o f the layout. The 100pm unit cell transistor has a
much wider source connection, and the pads are closer to the device. For increasing
gate width, the current density remains almost constant for Vds<lV, and decreases
with increasing gate width for Vds>lV.
The measurements must be performed very carefully. Even though the bias
tee’s, cables, and probes only added about 0.7Q series resistance, this small amount o f
extra series resistance in the setup can completely alter the results. This is illustrated
in the difference between Figure 4-6 and Figure 4-7. Figure 4-6 shows the drain
current o f the NMOS standard layout device in mA/(pm gate width). It appears from
this figure that the drain current density drops from 0.022mA/pm to 0.007mA/pm
from the 100pm device to the 4400pm device. Because o f the low bias o f VdS=0.05V,
this difference can not possibly be due to self-heating. The 4400pm transistor is only
dissipating about 1.5mW o f power. This is not enough power dissipation to cause any
measurable difference in current density.
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66
0.025
0.02
— 100um unit cell
-»-600um Standard
-*-2400um Standard
-*-4400um Standard
(
£
0
0.5
1
1.5
2
2.5
3
V gs (Vds=0.05V)
Figure 4-6. Normalized drain current for standard NMOS layouts
of 100 pm, 600pm, 2400pm and 4400pm. No correction made for
voltage drop in measurement setup.
However, if a kelvin connection is used to measure the voltage on the device
probe pads, the voltage drop in setup can be eliminated. These results are shown in
Figure 4-7. During the long measurement sequence to correct for the resistance in the
setup, it is possible for the probe contact resistance to vary.
Due to the contact
resistance variation, the data collected to correct for the setup resistance is not as
smooth. After correction for the measurement setup resistance, the current density
only drops from 0.024mA/pm to 0.017mA/pm. This remaining difference in current
density can be can be explained by process variations and by the fact that the drain and
source resistance do not scale ideally with gate width.
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67
0.025
0.02
— 100um unit cell
-*-600um Standard
-*-2400um Standard
-*-4400um Standard
E. 0.015
O
c
0 .0 1 -
0.005
0
1
2
3
V gs (Vds=0.05V)
Figure 4-7. Normalized drain current for standard NMOS layouts
o f 100pm, 600(J.m, 2400pm and 4400pm. Voltages corrected for
voltage drop in measurement setup.
4.4 Comparison of SOI and SOS Thermal Resistance
It has been shown [1, 2] that SOI has significant self-heating problems. A
typical fully-depleted SOI layer structure and a fully depleted SOS structure are shown
in Figure 4-8. The materials have thermal conductivities o f 1.5 W cm"1 K‘l, 0.448 W
cm"1 K~l, and 0.014 W cm '1 K '1 for silicon, sapphire and Si02 respectively. If the
structures are cubic in shape (as in Figure 4-8) and if heat is added uniformly in the
silicon layer, then heat will flow evenly through the substrate to the heatsink. This is
the case for a one-dimensional problem. In this simple case o f heat flow in onedimension, the thermal resistance can easily be calculated.
The results o f a one­
dimensional thermal resistance o f SOI and SOS are shown in Figure 4-9. For this
simple case, SOS would have higher thermal resistance than SOI for substrate
thicknesses greater than 20pm.
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68
2pm SiO;
1000A Si
Silicon substrate
sapphire substrate
Heat Sink (300K)
Figure 4-8. Representative layer structures used for SOI and SOS
MOSFETs. Top oxide layer is representative of interlevel
dielectrics or passivation.
S'
250
^<D
200
O
c
2
jn
w
£
co
E
u.
as
■C
h-
150
100
50
0
25
50
75
100
Substrate T hickness (um)
Figure 4-9. SOI and SOS thermal resistance assuming uniform
power dissipation in cube with cross-section of 1cm2.
However, contrary to this fact, it is known that SOS MOSFETs generally do
not exhibit characteristics o f self-heating [5]. The discrepancy is due to the fact that
an MOSFET is generating heat in the channel region, not the entire plane o f active
device silicon. W hen heat is being generated in a small area, the thermal resistance is
dominated by the thermal impedance o f the material in immediately contact with the
hot region (the spreading resistance component). Even though the buried oxide layer
is only 0.4pm thick, this thin layer dominates the thermal resistance o f an SOI device
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69
on a 500pm thick silicon substrate. SOS MOSFETs are in contact with a material,
sapphire, which has a thermal conductivity 32 times greater than Si02Using very simple two-dimensional approximations, it can easily be shown a
single gate finger SOS MOSFET has significantly lower thermal resistance than a
similar structure in SOL It has been shown that heat added to a surface o f a material
will propagate through the material spreading at an angle o f 45° as it travels to the heat
sink at the backside [6]. Calculations were done for a 0.35pm x 25pm gate finger on a
silicon island that extends 5pm on either side o f the channel for the source and drain
regions. I f the spreading o f the heat in the active silicon layer is correctly accounted
for [7], accurate calculations can easily be made for the thermal resistance o f the
structure. Results based on this simple approximation o f heat spreading at an angle o f
45° is compared with more accurate Silvaco thermal simulations (discussed below) in
Figure 4-10.
3000
? 2500 2000
SOI: Calculated
■ SOI: Simulated
—— SOS: Calculated
A SOS: Simulated
-
1500 ra 1 0 0 0 -
0.01
0.1
1
10
100
1000
Substrate Thickness (um)
Figure 4-10. Comparison o f simple calculation and simulation of
SOI and SOS thermal resistance for a 0.35pm x 25pm MOSFET.
The results shown in Figure 4-10 consider the buried oxide layer in SOI to be
part o f the substrate.
It can easily be seen that the thermal resistance increases
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70
dramatically to a depth o f 0.4pm at the buried oxide silicon substrate interface. Then
the thermal resistance only increases from 2550 K/W to 2800 K/W as 500pm of
silicon substrate are added to the 0.4pm thick buried oxide.
This shows that the
material immediately below the device determines the thermal resistance, even if it is
a very thin layer.
Because o f this, SOS devices have significantly lower thermal
resistance than SOI devices.
Figure 4-10 shows that the thermal resistance o f an SOS MOSFET is much
smaller than the thermal resistance o f an SOI MOSFET. As the sapphire substrate
thickness is increased from 100pm to 500pm, the thermal resistance only increases
from 1270W/K to 1300W/K.
This has two very important practical implications.
First, simulations can be greatly reduced by simulating a thinner substrate than is
actually used. This will give very accurate results with decreased simulation time.
Secondly, if one wants to reduce the thermal resistance by thinning the substrate, a
sapphire substrate would have to be thinned to less than 100pm to achieve a
measurable difference. Although sapphire substrates can be thinned, it is difficult to
make the substrate very thin without resulting in microcracks that can destroy device
performance.
It should also be noted that the critical thickness where the thermal
resistance remains almost constant with increasing substrate thickness depends on the
geometries o f the device structures.
These quick calculations ignore the effect o f phonon scattering at surface
boundaries. It has been shown that the thermal conductivity at room temperature o f a
silicon film can be reduced by nearly 40% from the bulk silicon value as the film
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71
thickness is decreased to 0.42pm [8].
Th>e effects o f phonon scattering at the
interfaces has been ignored in calculations due to the increased complexity o f the
calculations.
As will be shown in the nerxt section, predictions for large SOS
MOSFETs are not significantly affected by ignoring the phonon scattering.
4.5 Thermal Resistance of SOS
It has been shown in previous sections that the thermal resistance o f SOS
MOSFETs is much smaller than that o f SOI MEOSFETs. However, it is still important
to investigate exactly how much self-heating occurs in large gate width SOS
MOSFETs and what effect this has on device jperformance. In order to determine the
thermal resistance o f SOS devices, some device structures were simulated using
Silvaco’s three-dimensional thermal simulaitor.
The thermal simulations were
confirmed by measuring the device temperature while under DC bias.
4.5.1
Simulation
SOS MOSFET structures were simulated in order to approximate the devices’
thermal resistance. The simulator’s input file defines the structure, material thermal
properties, and the amount o f power being dissipated in specific regions o f the
structure.
Power was assumed to be uniform ly distributed in the channel o f the
device. A cross-section of the SOS structure used in simulation is shown in Figure
4-8.
As shown in the previous section, the substrates do not need to be the full
thickness to achieve accurate simulation results. If the three-dimensional volume o f
the simulation is too large, the simulation w ill begin to loose accuracy as the mesh
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72
points become too sparse. W ith this in mind, a substrate thickness of220pm was used
for the following simulations. A top view o f representative simulated structures is
shown in Figure 4-11.
These structures mimic the standard style layouts.
Interconnects and heat transfer from the device side o f the wafer to air do not
measurably affect the thermal results and were ignored for the simulation [7].
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73
Silicon Island
450pm
200pm250pm 300pm
Opm 200pm
(a)
Silicon Islands
450pm250pm -
—
20um
200pm —
Opm
Opm
T
T
T
T
200pm
250pm
270pm
320pm
-%
520pm
(b)
Figure 4-11. Top view of simulated device structures. All gates are
0.35pm x 50um. (a) 100pm gate width device, (b) 600pm gate
width.
The bottom o f the substrate was defined to be 300K. Areas o f sibcon equal to
the effective gate length and width o f the transistor, 0.35pm x 50pm, were used as the
source o f power dissipated by the device. Thermal simulations were done to estimate
the thermal resistance o f the 100pm, 600pm, and 2400pm standard layouts. Larger
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74
transistors could not be simulated due to a limitation on the number o f nodes within
Silvaco. The power was defined by assuming a drain current o f 0.2mA/(pm gate
width) at VdS=2V. Thermal conductivites o f 1.5 Wcm_1K '1, 0.448 W cm-1 K '1, and
0.014W cm''K'1 were used for the silicon layer, the sapphire substrate, and SiC> 2 are
respectively.
Figure 4-12 shows the simulated thermal resistance. The 100pm device has a
thermal resistance o f 500K/W, compared to 167K/W and 71K/W for the 600pm and
2400pm device respectively. If N gate fingers could be placed infinitely far apart
from each other, each o f the fingers would act independently, and the overall thermal
resistance would be 1/N times the thermal resistance o f a single finger. Based on this
ideal scaling law, and using the results for the 100pm device as a reference point, an
ideal thermal resistance can be calculated for the larger devices. This idealize thermal
resistance is shown in Figure 4-12. The difference between the simulated value and
the ideal value is due to the thermal interaction between the gate fingers. The thermal
resistance o f a large device can therefore be greatly reduced by increasing the
separation between the gate fingers. However, as discussed in chapter 3, if the device
is made too large it is possible for the increased size o f the device to degrade its RF
performance.
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75
1000
Simulation
(D
o
c:
- - - - - - Ideal
CD
C/3
'to
CD
CH
_
100
CD
E
u.
CD
10
0
500
1000
1500
2000
2500
G ate width (um)
Figure 4-12. Simulated thermal resistance for 100pm, 600fim, and
2400pm standard layout. Compared with ideal scaling of thermal
resistance from the 100pm device.
Silvaco’s thermal simulations show that at a bias o f Vds=2V and
Ids=0.2mA/(jjm gate width), the 100pm device will heat up by 20K while the 2400pm
device will heat up by 68K. This results in a temperature difference o f only 48K
between the two devices. This is not nearly enough self-heating to account for a drop
o f roughly 40% i n f t. Such a large drop in
would require a temperature rise on the
order of 140K. Therefore, if the simulations are correct, self-heating is not the correct
explanation for the degradation in RF performance.
4.5.2
Measurement o f Thermal Resistance
Some approximations had to be made in order to simulate the device
structures.
Most importantly, the phonon scattering at material interfaces and the
effect o f device doping levels on thermal conductivities were both ignored. Either o f
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76
these effects can alter the simulation results. To confirm the results from simulation,
the thermal resistance was measured experimentally using a liquid crystal technique.
The liquid crystal method o f measuring self-heating makes use o f the
temperature sensitivity o f birefringent nematic liquid crystals [9]. The liquid crystal
has a specified transition temperature where it changes from an ordered to a random
state. In the ordered state, the liquid crystal can affect the polarization o f light as it
passes through the liquid. Above the transition temperature, the liquid crystal is in a
random state and can not effect the polarization o f light. The spatial resolution o f this
method is limited by the optical resolution o f the microscope and is generally about
2pm resolution. Using this technique, the temperature rise at the surface o f the device
can be directly measured.
This technique has been shown to be very useful for
measuring the self-heating o f semiconductor devices [10, 11].
The setup for the measurement is shown in Figure 4-13. The cross-polarized
lenses are inserted into the optical path o f the microscope, effectively blocking all
light. The sample is placed on top o f a thermal chuck, so the substrate temperature
can be adjusted. A film o f liquid crystal is put on top o f the device. When the liquid
crystal is in its ordered state, the polarized light passing through it will have its
polarization changed. If the polarization is changed by the liquid crystal, the light can
now pass through the second polarizing lens.
With a DC bias on the device, the thermal plate underneath is heated up until
the hot regions o f the device start to turn black. This is the point at which the liquid
crystal reaches its phase transition temperature.
The self-heating o f the device is
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77
simply the difference between the known transition temperature o f the liquid crystal
and the chuck temperature. Knowing the DC power dissipation o f the device, the
thermal resistance can easily be determined.
Liquid
Crystal
Wafer
Figure 4-13. Liquid crystal measurement setup with cross­
polarized lenses and thermal plate.
Devices o f various gate widths and layout styles where measured. The results
are shown in Figure 4-14. The results o f the large devices agree fairly well with the
simulated thermal resistance. The measured value for the 100pm wide device is much
higher than the simulated value. This is believed to be due to neglecting the effect o f
the phonon scattering in the silicon layer.
Not only does the phonon scattering
increase the thermal resistance at the boundary, but it also decreases the thermal
conductivity o f the silicon layer, reducing the heat spreading in the active layer [8].
As the gate width increases, the metal interconnects must become wider to carry the
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78
larger currents. As the metal interconnects become large, their effect can not be
ignored (as was done in simulations).
The increased heat spreading via the
interconnects will result in lower thermal resistance. This effect is believed to be
responsible for the drop in measured thermal resistance with increasing gate width.
As can be seen in Figure 4-14, the effect o f increased thermal resistance in the thin
silicon film and increased heat spreading from the interconnects tends to cancel for the
2400pm device.
900
—• —Measured Standard Layout
800
■ Measured Spaceship Layout
a
Measured Waffle Layout
~ o ~ Simulated Standard Layout
® 400
300
£
200
100
0
1000
2000
3000
Gate Width (urn)
4000
5000
Figure 4-14. Measured and simulated thermal resistance.
Simulation shown with open symbols, measurements with filled
symbols.
Measuring the temperature o f the hot chuck directly under the wafer was the
largest source o f error in the measurement. The temperature could only be determined
within about 1.5K. This resulted in about a 7% uncertainty in the measurement o f the
thermal resistance.
The measured thermal resistance o f the 100pm and 2400pm
devices are 837K/W and 76K/W respectively.
With a bias o f Vds=2V and
Ids=0.2mA/(pm gate width), this gives a temperature difference o f 39.5K between the
two devices. This is close to the predicted temperature difference o f 48K. However, a
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79
temperature difference o f only 39.5K can not account for the drop in RF performance.
As noted in the previous section, the temperature difference would have to increase to
roughly 140K before one could account for the drop in RF performance, assuming
self-heating is the only determ ining factor.
4.6 Temperature Dependence o f SOS MOSFETs
Agreement has been shown between theory, simulation, and measurement o f
self-heating o f SOS MOSFETs. However, it is important to note that SOS is different
from bulk silicon. The thin silicon layer on the sapphire substrate is under strain. This
strain is large enough to effect the mobility o f the electrons and holes. The level o f
strain will change with changing temperature, due to the fact that silicon and sapphire
have different thermal expansion coefficients. It is therefore important at this point to
verify that SOS MOSFETs have the same temperature characteristics as bulk silicon
MOSFETs.
To verify the temperature dependence o f SOS MOSFETs, a 0.35pm x 100pm
NMOS SOS device was measured at various temperatures from -40°C to +100°C.
First the threshold voltage was measured versus temperature as shown in Figure 4-15.
The threshold voltage was measured with a drain to source voltage o f 0.1V.
As
expected, there is only a small variation o f the threshold voltage with temperature.
The threshold voltage varies by only 51mV, or a 9% drop, over a temperature range o f
140°C.
Due to the small variation, the threshold voltage between measured
temperature points is simply interpolated.
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80
0.58 i
>
■ Vth (Measured)
— Vth (Interpolated)
0.57 -
0
o> 0.56 -
CO
I
0.55 -
1
0.54-
jg 0.53 K 0.52 0.51
-50
-25
0
25
50
75
100
T em perature (C)
Figure 4-15. Measured and interpolated threshold voltage versus
temperature for 0.35pm x 100pm NMOS SOS device.
Next the saturation current was measured over the same range o f temperatures.
The simple model given by equations 4.1 and 4.2 and the interpolated threshold
voltage is compared to the measured saturation current in Figure 4-16. Unlike the
threshold voltage, the saturation current has a significant drop o f 23% over the 140°C
temperature range. The simple o f model given by equations 4.1 and 4.2 was used to
predict the saturation current. A slight modification had to be made to account for
changes in the gate-to-source capacitance due to the change of the fermi-level with
changing temperature. A very good agreement is attained between measurement and
theory.
Therefore the saturation velocity follows the classical temperature
dependence.
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81
E 25
20
■ Measurement
— Model
15
10
5
-50
-25
0
25
50
Temperature (C)
75
100
Figure 4-16. Measured and predicted saturation current versus
temperature for 0.35pm x 100pm NMOS SOS device.
Next the f
o f the device was measured at various temperatures. As the
temperature is increased from -40°C to 100°C the ^ o f the transistors dropped from
11.5GHz to 9.8GHz. This drop in ft was modeled by combining the equation fo vft
Sm
J t ~ 2 * C in ’
r
the temperature dependence o f the gate-to-source capacitance, and gm (the derivative
o f equation 4.1 with respect to the gate voltage). Figure 4-17 shows the agreement
between the measured and modeled f . It is easily seen that the standard bulk silicon
MOSFET equations correctly predict the temperature dependence of the SOS
MOSFETs.
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82
13
12
£
11
■ Measurement
Model
O
10
g --------- 1------ ----- ----------- ----------------8 -I-------- i------ 1--------- -------- -------- 1--------50 -25
0
25
50
75
100
Temperature (C)
Figure 4-17. Measured and predicted f t versus temperature for
0.35pm x 100pm NMOS SOS device.
4.7
SOS Device Characteristics
Simple first order models o f bulk silicon MOSFET temperature dependence
also accurately predict the DC and AC performance o f SOS MOSFETs versus
temperature. Based on this and the measurements o f device temperature, it can be
asserted that self-heating can not be causing the dramatic drop in RF performance
described in chapter 3. However, as shown in Figure 4-3, Figure 4-4, and Figure 4-5,
self-heating is having some measurable effect on device performance.
4.7.1 DC Measurements
As shown in Figure 4-3, Figure 4-4, and Figure 4-5, the current density in the
SOS MOSFETs drops as the gate width increases. This is a sign that the devices are
heating up. A simple method was devised to see i f the loss in current density could be
regained if the self-heating effects could be eliminated. Using a circuit simulator, the
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83
temperature o f the transistor was predicted based on the thermal resistance and power
dissipated by the device. The temperature o f the simulation was then corrected for this
temperature rise. This was done on a point-by-point basis for the family o f curves,
since each point has a different dissipated power, and therefore a different temperature
rise. The results o f the corrected current densities are shown in Figure 4-18, Figure
4-19, and Figure 4-20 for the standard, waffle, and spaceship style layouts
respectively. Comparing these results with the original data shown in Figure 4-3,
Figure 4-4, and Figure 4-5, it can be seen that the current densities have become more
constant with gate width. There is still some variation which can be attributed to
process variations, the drain and source resistance not scaling ideally, and most
importantly the simple method used to subtract the self-heating effects.
0.25
E 0.15
— 100um Unit Cell
-•-Standard 600um
O 0.10
-*• Standard 2400um
-•-Standard 4400um
0.05
0
1
2
Vds (Vgs=2)
3
Figure 4-18. DC current density of standard layout NMOS SOS
device after correction for self-heating.
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84
— 100um Unit Cell
e_o.i5
-•-Waffle 240um
-•-Waffle 620um
o 0.10
-“-Waffle 4160um
-•-Waffle 4320um
0.05
0.00
0
2
1
3
Vds (Vgs=2)
Figure 4-19. DC current density o f waffle layout NMOS SOS
device after correction for self-heating.
0.20
— 100um Unit Cell
-“-Spaceship 2400um
-•-Spaceship 3600um
O 0.10
c
-•-Spaceship 3900um
-•-Spaceship 3900um
(extra source meta)
0.05
0.00
0
2
1
3
Vds(Vgs=2)
Figure 4-20. DC current density o f waffle layout NMOS SOS
device after correction for self-heating.
The thermal resistances used in the circuit simulator to correct for self-heating
are compared with the measured values in Figure 4-21. Although there are some
discrepancies between the measured thermal resistance and the thermal resistance used
in the circuit simulator, overall the two techniques are in fair agreement.
So the
measured thermal resistance does indeed account for most o f the drop in the DC
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85
current density.
Without the self-heating, the current density should scale almost
ideally with increasing gate width.
1000.0
:
800.0 ° Measured Standard
*■ Measured Spaceship
a Measured Waffle
• Fit Standard
■ Fit Waffle
* Fit Spaceship
— Trend
600.0 -
±
ro 400.0
E
ID
H■C
200.0
...
\
'
\
O I
_4
!
|
—^
—■
7 ^ ^ .
*
7TT
0.0
1000
2000
3000
4000
5000
Gate Width (um)
Figure 4-21. Comparison of measured thermal resistance (open
symbols) and thermal resistance used to correct for self-heating
effects (solid symbols).
4.7.2
AC Measurements
AC measurements can also be done to characterize a device without the effects
o f self-heating. From the small signal s-parameters, the output conductance, or slope
o f the DC curve, can be determined. If the slope & ds
dV,ds
as a function o f Yds is
gs
known, and it is known that Ids(Vds=0)=0A, then the slope can be integrated to create
the DC curve without self-heating effects.
This has been referred to as the AC
conductance technique [12]. This method o f producing the DC curves without the
effects of self-heating was carried out for the 100pm unit cell, 240pm waffle, 600pm
standard, and 620pm waffle NMOS devices. The DC curves directly measured from
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86
the devices are shown in Figure 4-22 while the results from the AC conductance
technique are shown in Figure 4-23.
0.2
c
— 100um Unit Cell
♦ W a ffle 240um
♦ Standard 600um
♦ W a ffle 620um
0.1
0.05
0
0.5
1
2
1.5
Vds (Vgs=2V)
2.5
3
Figure 4-22. DC current density for SOS NMOS devices.
Measurement not corrected for resistance in setup.
0.25
0.2
E.0.15
— 100um Unit Cell
♦ W a ffle 240um
♦ S ta n d a rd 600um
♦ W a ffle 620um
0.05
0
0.5
1
2
1.5
Vds (Vgs=2V)
2.5
3
Figure 4-23. DC current density for SOS NMOS devices derived
from the AC conductance technique.
The agreement o f the current densities attained via the AC conductance
technique is very good. However, it should be noted that not all o f the increase in
current density between the DC measurements and AC conductance measurements is
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87
due to correcting for self-heating. The probe pad voltages were not measured for these
DC curves, so the resistance in the measurement setup was not taken into account.
W hen performing the AC conductance technique, the calibration o f the network
analyzer will take out all resistance up to the probe tips. So in addition to correcting
for self-heating, the AC conductance technique can also be used to correct for small
amounts resistance in the measurement setup.
It is also possible to remove thermal effects by keeping the device junction
temperature constant. Knowing the thermal resistance and power dissipation, it is
possible to change the temperature o f the wafer chuck such that all devices are
measured at the same temperature. This was done in order to m easure^ and^rrax to see
how much o f the drop i n ^ and/nax would remain without self-heating effects. The
wafer chuck temperature was adjusted such that all devices were measured with a bias
o f VdS=2V and Vgs=2V with all devices having a temperature o f 100°C. The results
are shown in Figure 4-24.
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88
35
30
'
n
'
2
-
xCD
20
Fmax
—
**
,1 15 10
—
5 —
0
1000
2000
3000
4000
5000
Gate Width
Figure 4-24. F t and F max measured at a constant device
temperature of 100°C for standard layout NMOS transistors.
F t and Fmax start slightly lower for the lOOpm device, however, ft and /rax
continue to drop drastically with increasing gate width. Since all the transistors are at
the same temperature, the drop can not possibly be due to self-heating. The drop in
performance must therefore be caused by the layout parasitics and phase delay
described in chapter 3.
4.8 Conclusions for Chapter 4
Although there is some self-heating associated with SOS MOSFETs, the self­
heating is not enough to significantly degrade the DC or AC performance for the
MOSFETs as in the case o f SOI MOSFETs. The thermal resistance for SOS devices
is high enough that self-heating effects should be considered when designing high
power transistors. However, the performance o f SOS devices can easily be predicted
based on simple models developed for bulk silicon device.
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89
Since the drop in j t and^rnax can not be attributed to self-heating, it must be due
to the layout parasitics. This will be further investigated in the following chapter.
4.9
References
1.
K.E. Goodson, M.I. Flik, “Effect o f microscale thermal conduction o f the
packing limit o f silicon-on-insulator electronic devices”, IEEE Transactions on
Components, Hybrids, and Manufacturing Technology, vol. 15, October 1992,
pp. 715-722.
2.
Z. Chai, M. Berger, “The self-heating effect and its influence on the electrical
properties o f SOI MOSFET’s” Proceedings o f the IEEE SO I Conference,
1992, pp. 78-79.
3.
S.M. Sze, Physics o f Semiconductor devices, 2nd Edition, Wiley, New York, p.
46.
4.
S.M. Sze, Physics o f Semiconductor devices, 2nd Edition, Wiley, New York, p.
29.
5.
D.K. Sadana, Y-J. Mii, H J. Hovel, J.Y-C. Sun, Y. Taur, C. Demic, K. Chan, S.
Cohen, “Fully depleted 0.25pm nMOSFETs on SOS, SIMOX and BSOI
substrates”, Proceedings o f IEEE International SO I Conference, October 1994,
pp 6-7.
.
L.H. Holway Jr., M.G. Adlerstein. “Approximate formulas for the thermal
resistance o f IMP ATT diodes compared with computer calculations”. IEEE
Transactions on Electron Devices, Feb. 1977, pp. 156-159.
7.
K.E. Goodson, M.I. Flik, L.T. Su, D.A. Antoniadis.
“Prediction and
measurement o f temperature fields in silicon-on-insulator electronic circuits”.
Transactions o f the ASME, Journal o f Heat Transfer. Vol. 117, August 1995,
pp. 574-581.
.
M. Asheghi, M.N. Touzelbaev, K.E. Goodson, Y.K. Leung, S.S. Wong.
‘Temperature-dependent thermal conductivity o f single-crystal silicon layers
in SOI substrates”, Transactions o f the ASME, Journal o f Heat Transfer. Vol.
120, February 1998, pp. 30-36.
9.
J.P. Van Meter, “Chemistry o f liquid crystals,” Eastman Organic Chemical
Bull., vol. 45, no. 1,1973.
6
8
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90
10.
D J . Channin, “Liquid-crystal technique for observing integrated circuit
operation,” IEEE Transactions on Electron Devices, October 1974, pp. 650652.
11.
K.J. Negus, R.W. Franklin, M.M. Yovanovich, “Thermal modeling and
experimental techniques for microwave bipolar devices”, IEEE Transactions
on Components, Hybrids, and Manufacturing Technology, vol. 12, No. 4,
December 1989, pp. 680-689.
12.
R.H. Tu, C. Wann, J.C. King, P.K. Ko, C. Hu, “An AC conductance technique
for measuring self-heating in SOI M OSFET’s”, IEEE Electron Device Letters,
vol. 16, no. 2, February 1995, pp. 67-69.
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5 Large FET Analysis
5.1 Introduction
The drop in RF performance o f large SOS MOSFETs with increasing gate
width is not due to self-heating, as shown in chapter 4. Another possible cause is the
interconnect parasitics o f the large periphery transistors. The layout parasitics come
from paralleling many small transistors to make a large periphery transistor. This
chapter will examine the effects o f the layout parasitics on the RF performance of
MOSFETs.
It is important to understand the effects o f parasitics in order to be able to
combat the associated problems and design devices with improved RF performance
for use in microwave circuits. It is also important to be able to correctly model the
performance o f the MOSFETs so that circuit designers can accurately simulate their
circuits, cutting down the number o f design iterations.
This chapter will first discuss some basic theory o f the extraction of/max. Fm^
is extracted from either the combination o f maximum available gain and maximum
stable gain (MAG/MSG) curve or from the unilateral gain. The extracted value o f f max
is invariant to addition o f loss-less lumped elements (inductance, capacitance, or
delay) at the input or output o f a transistor. This demonstrates the necessity o f a more
complex model o f parasitics than adding equivalent lumped elements at the input and
output.
An effort to use composite lumped element models to predict the RF
performance will be presented.
Next a model where the parasitics elements are
91
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92
distributed elements rather than lumped elements will be presented followed by a
discussion and implications o f the distributed model.
5.2 Determination of F mar
Fjxax. is defined as the frequency where the power gain drops to unity. For
microwave transistors, this is obtained by measuring the s-parameters versus
frequency, computing the maximum stable gain / maximum available gain
(MAG/MSG) or the unilateral gain from these parameters, and plotting the values in
dB versus the log o f the frequency. For well-behaved devices, the maximum stable
gain drops lOdB/decade while the maximum available gain and the unilateral gain
drop 20dB/decade. An example is shown in Figure 5-1 for a 120pm SOS MOSFET
without a metal T-gate.
For this device, /max is 28GHz, as extracted from either
MAG/MSG or from the unilateral gain.
Extraction from either MAG/MSG or
unilateral gain was found in simulation and experiment to give the same result. The
unilateral gain curve in Figure 5-1 is not a straight line due to polysilicon depletion in
the device fabricated by Peregrine. The polysilicon depletion in the Peregrine devices
will be discussed in section 5.4.1.
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93
30
25
20
—
m
"O
•— •MAG/MSG
Unilateral Gain
]=f 15 —
CD
C3
10
- —
Fmax=28GHz
0.1
1
10
100
Frequency (GHz)
Figure 5-1. MAG/MSG and unilateral gain versus frequency for
0.5fj.m x 120pm SOS MOFET (fabricated by Peregrine).
The unilateral gain, also knows as Mason’s gain, is not affected by lossless
elements added to the input and output ports. The unilateral gain is derived from the
equation
u
____________ ( f e l —Z 12l)2______________
4 Re(Zxj ) * Re(Z 2 2 ) - Re(Z21)'* R e f a 2 ) *
(5-1)
If a capacitor or inductor is added in series with port one o f the device under
test, it will change the imaginary part o f Z l l , which does not alter the value o f
equation 5-1. Similarly, a series inductor or capacitor on port two only changes the
imaginary p art o f Z22, and does not affect the value o f equation 5-1. Similar results
can be derived, for shunt elements. Any lossless element can therefore be tuned out by
adding the correct series or shunt lossless elements. Therefore, the unilateral gain is
not affected b y the shunt capacitance or series inductance o f the probe pads.
If shunt or series resistors are added to the circuit, f ^ x will degrade. Under
these circumstances, MAG/MSG and unilateral gain will continue to have the classical
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94
slope. The effects o f the layout parasitics can not be accounted for by simply adding a
lumped resistor, inductor, and capacitor to the input and output ports. In order to
correctly account for the layout parasitics, a model m ust take into account the fact that
the parasitics are distributed throughout the transistor, and not just at the ports.
5.3 Composite Model
A composite model assumes small finite elements o f the overall structure can
be modeled as ideal lumped elements. These lumped elements are then connected to
build up the full structure being modeled. This technique is powerful since it can be
applied to any configuration or layout. An accurate simulation o f any layout can be
made as long as accurate models for the individual elements can be derived, and
enough characteristics o f the layout can be modeled. However, for a complex layout,
modeling all the different layout interactions can be very difficult.
First a brief
summary o f the device technology used for the composite modeling will be presented,
followed b y a discussion o f the detailed composite model, and finally a simplified
model for predicting the behavior o f H21 (current gain) andjt5.3.1
Device Technology
The devices for testing the composite model were fabricated by SPAWAR
Systems Center (SSC) San Diego. A cross-section o f a standard device is shown in
Figure 5-2. The main features are a 1000A silicon film thickness (for fully depleted
devices), 0.35pm effective gate length,
1 2 0
A gate oxide, silicided drain and source,
and a m etal T-gate to reduce the gate resistance. This technology has been used to
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95
demonstrate NMOS devices with./=20GHz and/nax^fiOGHz [1], The short effective
gate length is responsible for the high/t while the metal T-gate allows for high fm x by
reducing the gate resistance. Most o f the large MOSFETs were designed with, unit
gate widths o f 50pm. The unit cell transistor for most o f the large MOSFETs was two
0.5pm x 50pm gate fingers w ith/=19G H z and/nax=39GHz.
Aluminum metal Tgate to reduce gate
1 2 0 A thick
gate oxide
Silicon film
thickness
1000A
Sapphire Substrate
Figure 5-2. Cross-section o f device fabricated at SSC San Diego.
Device has metal T-gate to reduce gate resistance and 0.35pm
effective gate length.
5.3.2
Detailed Modeling
AgilentEEsof s Libra software was used to make the composite model and
simulate the microwave characteristics of the large periphery MOSFETs. A single
0.5pm x 100pm (two 50pm wide fingers) NMOS transistor was represented by a spice
level 3 model based on DC and RF measurements. The model was fit to accurately
predict the s-parameters at a bias around VdS=2V and Vgs=2V, the point of maximum
f t. This same bias was used in subsequent simulations using this level 3 model. An
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96
example o f the composite models is shown in Figure 5-3 while the corresponding
layout is shown in Figure 5-4.
The series resistance o f interconnects was estimated based on the known sheet
resistance and the geometries o f the interconnects.
The inductance o f the
interconnects was taken to be the self-inductance o f the lines only, based on equations
by Greenhouse [2].
Following standard practice for estimation o f parasitics, the
mutual inductances were ignored due to the complexity in accurately calculating the
values.
Capacitance between parallel interconnects was also ignored due to the
complexity o f the field lines in a complex layout.
However, overlap capacitance
between metal layers was calculated based on the area o f overlap and thickness o f the
interlevel dielectric. These lumped element values for parasitic resistance, inductance
and capacitance were assumed to be constant with frequency. The results o f the model
did not noticeably change when compared to results using a microstrip element to
correctly model the frequency dependence o f the resistance and self-inductance.
The interconnects were broken down into sections or 50pm long o f less, most
o f the sections being considerably shorter than 50um. Assuming the wavelength o f
the signal is determined by the dielectric constant o f the medium around the
interconnects, this translates into a maximum length o f about 3 degrees for a 25GHz
signal. This is short enough to model the sections o f interconnect as discrete lumped
elements.
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97
I T
3E
D rain
U T
JX
JX.
JX .
JX.
3r
1I
Figure 5-3. Composite model of 3900pm wide spaceship layout.
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98
D r a in '
Figure 5-4. Layout o f 3900pm spaceship device.
Results o f the simulated yj andyinax based on the composite models are shown
in Figure 5-5. The symbols show the predicted performance based on the composite
model simulations in Libra. The solid line shows the measured performance. The
detailed composite model predicts a significant portion o f the drop 'm ft a n d y ^ .. It
has error o f predicting^ o f 25% and 10% for the 2400pm and 3900pm wide spaceship
layouts respectively. The error in predicting the drop my^ax is 35% and 17% for the
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99
2400pm and 3900pm wide spaceship layouts respectively. The 100pm transistor was
used to model the unit cell transistor, s o ^ andyinax agree by virtue o f the modeling.
"" L e g e n d
F t : S p a c e s h ip
F m a x : S p a c e s h ip
■
F t: L ib r a M o d e l
|
♦
F m a x : L ib r a M o d e l
G a t e W i d t h ( in n )
Figure 5-5. Simulated and measured^ a n d /max versus gate width
for the spaceship style layouts.
Based on the thermal resistance o f the devices and the power dissipated by the
device, the 2400pm wide spaceship transistor is expected to heat up by at most 75°C.
Based on data from section 4.6, this will lead to a drop iny^ o f about 9%. This will
cause the expected f t o f the 2400pm device to be reduced from 16GHz to 14.5GHz,
reducing the error from 25% to 17%. The 3900pm device is expected to heat up by
approximately 100°C, leading to a drop in y[ o f
1 1
%.
This reduces the f o f the
3900pm device from 15GHz to 13.4GHz, reducing the error from 10% to 1.5%.
Although the composite model does not precisely predict the drop in ft and /max,
when combined with self-heating effects, does provide a means o f predicting the
degree to which the RF performance drops and means to compare layouts before
fabrications.
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100
5.3.3
Simplified Lumped Element M odel
Although the detailed composite model predicts the behavior o f the transistors
fairly well, it takes a considerable amount o f time to calculate and extract all o f the
parasitic elements for the model. It is therefore desirable to find a simplified model
that can predict some o f the RF performance quickly. W ith this in mind, a very simple
method was developed to predict the behavior o f ft.
Simulation o f the current gain, h n versus frequency, showed that the slope o f
the line should have been very close to the theoretically predicted slope o f
20dB/decade. Experimentally it is found that at low frequencies, frzi has the correct
slope, but the slope increases with increasing frequency. This results in a OdB current
gain at about 10GHz for a measured 2400/sm device. However, as shown in Figure
5-6, f extracted from low frequency measurements would result in jr=16GHz. This
roll-off o f current gain with increasing frequency could not be explained with a simple
lumped resistor, capacitors and/or inductor at the input or output o f the transistor.
25
Measured H21
Theoretical H21
5 —
10
Frequency (GHz)
Figure 5-6. Measured H21 (current gain) and theoretical
prediction. Slope of measured H21 increases with increasing
frequency, resulting in lower f .
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101
Almost all o f the drop m f t for the large devices can be attributed to this same
type o f roll-off o f current gain with increasing frequency. For the small gate width
devices, the measured transit time from source to drain was about 1.5ps while for large
devices the transit time was about 7-9ps. This extra delay is associated with the extra
time for the signal to get though the long interconnects on the gate, drain and source.
The simplest model to describe this effect is to put in a short length o f transmission
line between the device terminals and the input and output ports. A simple small
signal model o f the MOSFET output used for the following analysis is shown in
Figure 5-7.
lout
Figure 5-7. Model of transistor output with transmission line on
drain.
In an ideal case, H21 is measured with the device output shorted, so that none
o f the device output current is used up in the output resistor. In the ideal case, the
output current iout has the same magnitude as the current generated b y the
transconductance, is. With a transmission line on the output, some o f the output
current m ay now be consumed in the device’s output resistance, Ro, depending on the
output resistance, the transmission line characteristics, and the operating frequency.
Solving for i,-n and iout shown in Figure 5-7 in terms o f the forward and reverse
going waves in the transmission line yields the relation
r
°Ut
“
2exp ( j 0 )
zexpV**)
r _______ £________
l+cxp(2//3?)
m exp(-j/3l)+cxp( j/3l)
lm
cos(/3f)
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(5-2)
102
The current going into the current source, is, has components from both the
output resistor and the transmission line. The current into the transmission line is then
given by the equation
m
(5-3)
s R0 +Z0j\zx{pi) •
Combining equations 5-2 and 5-3 and solving for iout in terms o f is yields
1
I nut
(5-4)
It
cos(/S?) +j^-sm(/3l)
Ko
For small delays expected from the layouts, the product pi will be small, and 54 can be simplified to
1
W ® 1*.
i
1
-
2
Za , v
2
W
1
(5-5)
-
Equation 5-5 shows how the current gain can be modified by the transmission
line on the drain. If Z 0 is larger than Ro, then the current gain will be reduced by the
delay in the transmission line. For large MOSFETs, Ro is small, making it more likely
for Z0 to be larger than Ro. For low frequency, the product pi can be approximated as
zero, leading iout to equal is, resulting in the same current gain as the transistor without
a transmission line on the output.
The product pi will increase with frequency,
resulting in a roll-off of H 2 1 with increasing frequency, as observed in measurements.
Using only a short transmission line on the drain and ideally connected FETs
to build a 2400fan effective gate width, the model was simulated in Libra and
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103
compared to measured data, shown in Figure 5-8. The simulations show very good
agreement with the measured values with a delay o f 3ps and a transmission line
characteristic impedance o f 35 Ohms on the drain.
25
—A—Measured H21
Theoretical H21
20
S
15
£!
10
10
Frequency (GHz)
Figure 5-8. Measured and modeled H 21 for a 2400pm wide device.
As the gate width o f the transistor is scaled up, the measured delay in the
transistor increases from about 1.5-2ps to 7-9ps. A delay o f 3ps is reasonable based
on RF measurements and based on the physical size o f the transistor. If one assumes
the wavelength o f the RF signal is determined by the Si0
2
interlevel dielectric
(er=3.9), then the 3ps delay would correspond to a physical length o f about 450pm.
This is the same distance as the gate to drain probe pad o f the 2400pm standard
layout. So the delay is in agreement with the physical size o f the transistor.
Although this simple model can be used to explain the roll-off o f H 2 1 and the
drop in /t, it can not explain the drop in/max. As discussed in section 5.2, lossless
lumped elements added at the transistor input or output can be tuned out, and therefore
do not effect the maximum available gain or the/max o f the transistor.
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104
5.3.4
Discussion
The simplified lumped element model using a transmission line on the drain
has a solid physical basis and predicts the roll-off in current gain very well. However,
the simplified modeled does not predict any drop in power gain measured as either
MAG/MSG or unilateral gain. In the detailed composite model, the interaction o f all
the parasitic elements (resistors, inductors, and capacitors) is needed to predict the
drop in /t and^max.. While the detailed model predicts the drop m f t and
a closer
examination o f the RF characteristics shows some deficiencies o f the composite
model.
The model for the 2400(j.m spaceship style FET was adjusted to better predict
the measured drop in f t and /max. Figure 5-9 shows the measured and modeled H21
versus frequency for this device. Exactingjt from the model in the frequency range o f
l - 8 GHz provides a value that is close to the measured value. However, at 8 GHz10GHz there appears to be a resonance as H21 suddenly increases, pushing out the
frequency with unity gain.
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105
- e — H 21 M o d e l
—
H2 1 M e a s u r e d
30
m 20
10
Frequency (GHz)
Figure 5-9. Measured (solid) and modeled (open) H21 for 2400pm
spaceship style FET.
Figure 5-10 shows the modeled and measured power gain (MAG/MSG and
unilateral gain) versus frequency. Although these curves are much better behaved
than the current gain versus frequency, they do lead to an error in the gain o f 2dB3dB. In the region o f conditional stability (< 6 GHz), the model follows the classical
result o f lOdB/decade for MAG/MSG.
However, in the region o f unconditional
stability (> 6 Ghz), the model deviates sharply from the classical (and measured) result
o f 20dB/decade for MAG/MSG. The modeled unilateral gain curve is fairly well
behaved, only showing a slightly sharper than expected roll-off as the gain approaches
OdB.
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106
M o d e l M A G /M S G
M o d e l U n ila t e r a l G a in
M e a s u r e d M A G /M S G
M e a s u r e d U n ila t e r a l G a in
30
GO
T3
-
CO
O
w
©
*o
C
L
20
10
Frequency (GHz)
Figure 5-10. Measured (solid) and modeled (open) power gain
(MAG/MSG and unilateral gain) for 2400pm spaceship style FET.
Figure 5-11 and Figure 5-12 show the s-parameter fit in the range o f 0.5GHz to
25GHz. The model does not accurately predict SI 1, S22, and the phase o f S21. SI 1
and S22 o f are particular interest, as these are used in designing the matching structure
for the transistor. With incorrect s-parameters, it would be very difficult to design a
circuit with the proper performance.
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107
s n m
Figure 5-11. Measured (lines) and modeled (symbols) s-parameters
for 2400pm spaceship style FET from 0.5GHz to 25GHz.
90.
135
45
S 21
180
225
315
270
Figure 5-12. Measured (lines) and modeled (symbols) s-parameters
for 2400pm spaceship style FET from 0.5GHz to 25GHz.
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108
The detailed composite model and the simplified model predict some o f the RF
characteristics o f the large periphery MOSFETs. However, there is still a lot o f room
for improvement in the model.
Better predictions o f s-parameters are needed for
circuit design and well-behaved H21 and MAG/MSG curves are desired.
5.4 Distributed Model
Increasing the accuracy o f the detailed composite model can make the
composite model prohibitively complex for an arbitrary layout.
The electric and
magnetic field lines between all o f the interconnects will be nearly impossible to
accurately determine in a complex layout.
Taking into account capacitance from
parallel metal lines and mutual inductance between the metal lines increases the
complexity o f the model and the difficulty in calculating the values o f the lumped
capacitances and inductances.
A more extensive model that takes into account mutual inductance and
capacitance is needed. However, due to the complexity o f the electric and magnetic
field lines, this can not be applied to arbitrary layouts. It has been shown that a
distributed transmission line model o f a FET can provide good agreement in
predicting the s-parameters o f a device to very high frequencies [3,4]. Many such
studies predict the behavior o f a single gate finger and most ignore distributed effects
o f the source lead, since a backside via to ground for the source is assumed. For this
work, a three-coupled transmission line model is used, modeling the distributed
parasitics on the gate, drain and source leads. This model can accurately account for
mutual capacitance and inductance, but only in limited types o f layouts. First the
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109
device technology use to verify this model will be briefly discussed, followed by the
mathematical setup and solution o f the coupled transmission line problem. Next a
comparison o f the distributed model versus measured data will be shown, followed by
a discussion o f some o f the model implications.
5.4.1
Device Technology
Unlike the devices used for the composite modeling, the devices for the
distributed model were fabricated by Peregrine Semiconductor through MOSIS
(supported by SSC San Diego). The Peregrine devices have a minimum gate length o f
0.5pm and do not have a metal T-gate. This leads to a low er^ and Anax o f 14GHz and
27GHz respectively. A cross-section o f the device is shown in Figure 5-13.
Dual polysilicon
process\
A thick
gate oxide
1 0 0
Silicon film
thickness
1 2 0 0 A
Sapphire S ubstrate
Figure 5-13. Cross-section of device fabricated at Peregrine
Semiconductor used to verify the distributed model.
The Peregrine devices were fabricated in a dual polysilicon process, meaning
that the NMOS devices have an n+ doped polysilicon gate while the PMOS devices
have a p+ doped polysilicon gate. This can lead to some complications. In order to
attain differing polysilicon doping types, the polysilicon is usually doped by the
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110
source/drain implants. However, the doping concentration can not achieve the same
levels as when the polysilicon is degenerately doped dining deposition.
This, in
addition to a thin gate oxide, can lead to polysilicon depletion [5]. I f the gate oxide is
thin, the inversion charge can have a significant effect on the electric potential o f the
polysilicon gate. If at the same time the polysilicon gate is not degenerately doped, a
depletion region can form in the polysilicon at the gate oxide interface.
This effect changes the small signal model from the traditional small signal
model shown in Figure 5-14 to the small signal model shown in Figure 5-15. At low
frequencies, the polysilicon depletion has the effect o f increasing the gate resistance,
decreasing microwave gain. A t high frequencies, the depletion capacitor acts like a
short, resulting in lower gate resistance and higher microwave gain. This change from
lower to higher gain occurs between 1GHz and 3GHz for these devices, as shown by
the unilateral gain in Figure 5-1.
out
Figure 5-14. Traditional small signal model of MOSFET.
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I ll
Cdep
Figure 5-15. Small signal model of MOSFET with polysilicon
depletion.
5.4.2
Problem Setup and Solution
hi the distributed model, the interconnect parasitics, as well as the FET
admittances, are regarded as continuous functions o f position along a one-dimensional
line. Voltages and currents can be calculated as continuous functions o f position using
transmission line equations. One section of the distributed circuit model is shown in
Figure 5-16. The gate, drain, and source feeding structures all have a series resistance
and inductance. Additionally, there are mutual inductances between the three lines,
and capacitances between the three lines.
The box labeled “Y” in Figure 5-16
represents the y-parameters o f the continuous FET. The continuous FET is the active
device small-signal model with no layout parasitics.
It is assumed there is no
inductance or capacitance coupling from one segment o f the transmission line to the
next.
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112
Cgd
Ld
Mgd
Mds
Rc
Rd
\SSSj-----vfljui— kQfifi/— w<Lg
Mgd
\SHSb
—
M gs
i
Rg
\9S9/ —
r
Ls
Mds
M gs
Rs
-\59Sj-----\959j— vfififi/— va—
r
V
C gs
c
Cds
Figure 5-16. One section o f distributed model. Y-box represents
the small-signal y-parameters o f the active device.
Equations describing the changes in voltage and current along the three
transmission lines can be easily derived.
Explicit source dependence can be
eliminated with the use o f KirchofPs current law, Is(x)+Id(x)+Ig(x)=0, and the
expression o f the gate and drain voltages with respect to the source voltage.
A
detailed solution o f the equations is shown in appendix A. The transmission line
equations can be expressed as:
d 2Vgs(x)
dx2
= aVgs(x ) + pvds[x )
d 2Vds(x)
= SVgs(x) + yVds(x) ■
dx2
(5-6)
where a , (3, 8 , and y depend on the interconnect inductance, resistance, and
inductive and capacitive coupling.
The boundary conditions assume that the gate input is at the position x=0 and
the drain is at the position x=L, as shown in Figure 5-17.
The definition o f the
positive direction o f the gate and drain current is to facilitate the solution o f the small
signal parameters, which take positive currents going into the device.
Using the
boundary conditions specified in Figure 5-17 and an eigenvalue solution to decouple
the equations 5-6, the coupled transmission line problem can be readily solved.
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Figure 5-17. Boundary conditions: source terminals grounded,
Vgs(x=0)=Vg, Vds(x=L)=Vd, Ig(x=0)=Ig, Ig(x=L)=0, ld(x=0)=0,
Id(x=L)=Id.
The equations most easily lead to a solution o f the z-parameters. Once the zparameters are obtained, transformations can easily be made to obtain s-parameters, hparameters, or y-parameters. The z-parameter solution is given by the equations (a
detailed solution is shown in appendix A):
g d P + M d s P ~ M gs[r-
Zps
“«))
r l-a
^ - { M g d p - M d sp + M g s ( r | - a ) )
r+Tarth(r+L )
jco M g d 8 + M g S§
^
r 2 —r+
zgs
ja
jc o { M g d P -M d s P
---------
Zg{.
[ A fg d S + M g s S
r+ Sinh{r+ L)
r_ S in h (r_ L )
I
r_Tanh{r_L)
VM
r+ - a _________
r+Sinh{r+ L)
r- - r - —
________
^ g d s + M g ss+ ,vrds {r+ ~ a ]j r+ - y ~ ^ - { M g d s
r+ Tanh(r+L )
^ 2
g s s + M d s (r-
-«))
~d______________________
r_Tanh(r_L)
a + Y±4(pc-r)2 +*P8
where
a = Y ll-{ Z g + Z s ) - Y 2 l- Z s - a > 2 ■Cgd ■{M d s-M g d - 3 Mgs) +
2 & > 2 -Cgs-M gs + j { —2co-M gs- T il —a>Y2l-{Mds —M gd —Mgs) -fcoCgd ■{Zg + 2Zs) + coCgs ■{Zg + Zs)}
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(5-7)
114
P = -Y 2 2 - Zs + Y12 -(Zg + Zs) + co2 - Cgd •(M d s -M g d - 3Mgs) +
CD2 ■Cds ■(Mds —M gd —Mgs) + j{-a>Y22-(M ds —M gd —Mgs) —
2eoYY2 -Mgs —coCgd - (Z g —2Zs) —coCds - Zs}
y = 722 •(Zd - Zs) + Y12 -Zs - co2 • (Mfe - Mgd + Mgs) +
j{coYll ■(Mgd —Mds —Mgs) + coCgd - (Zd —2Zs) —coCds • (Zd —Zs)}
5 = 711 •Zs) + 721 •(Zd - Zs) + co1 • Cgd •(Mds - M g d + Mgs) +
at2C gs-(M ds—M gd + Mgs) + y {<a711• (Mgd —M d s—Mgs) —
coCgd •(Z f —2Zs) -+-coCgs • Zs)}
5.4.3
M odel Verification
To verify equations 5-7 derived from the distributed model, transistors were
designed that could be easily modeled by a coupled transmission line. The RF signals
follow a linear path from input to output, as depicted in Figure 5-18. Except where the
active device area connects to the interconnects, this layout style avoids comers and
bends, minimizing the coupling between different sections o f the layout as assumed in
the problem setup in section 5.4.2.
G ate
Figure 5-18. Linear layout style used for model verification.
MOSFET’s with a linear layout design and with gate widths o f 432pm,
864pm, 1296pm, and 2160pm were designed. The transistors take up an area o f
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115
400pm x 300pm, 400pm x 375pm, 400pm x 450pm, 400pm x 600pm respectively.
The transistors o f different gate widths have the same basic structure. To increase the
gate width, more gate fingers are added in parallel, increasing the length o f the
interconnect transmission lines as shown in Figure 5-19.
2160pm
1296pm
432pm
Figure 5-19. Layouts for the 432pm, 1296pm, and 2160pm devices.
Interconnects go in a straight line so as to be modeled by a
transmission line. Only difference in layouts is length of
interconnect transmission line.
Unlike the devices already presented in this thesis, the Peregrine process does
not have a metal T-Gate, resulting in a lower ^max for all device sizes. In addition, the
minimum gate length was 0.5pm, leading to a slightly lower f for all device sizes,
although this is partially counteracted by a higher channel mobility. The peregrine
devices also have a lower threshold voltage, 0.35V compared with 0.55V-0.65V for
devices fabricated at SSC San Diego. The measured f t for a 120pm width NMOS
device in this technology was 14GHz while^nax was 28GHz with a DC bias o f Vds=2V
and Vgs=1.4V.
The RF data usually has some noise in the data set. This noise increased for
large gate width devices due to the difficulty in maintaining a good RF probe contact
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116
under high current bias. This did not create any difficulty in extracting^ and /max, or
for optimizing a small-signal model for a single device. However, the noise in the RF
measurements complicated the ability to accurately optimize the model parameters
simultaneously for multiple gate widths. To reduce this problem, a lower current
density was used when measuring the devices for the distributed model.
The
m easured^ and^nax presented in the section may therefore not be the maximum if the
bias conditions are changed. But the distributed nature o f the model can still be
verified.
The lower current density also reduces problems o f self-heating, such that
devices o f different gate widths can be approximated as being at the same temperature.
The devices were biased with VdS=2V, Vgs=1.4V and a current density o f
approximately 0.15mA/(pm gate width). The voltage at the probe pads was measured
before RF measurements were taken to properly account for series resistance in the
measurement setup. The temperatures o f the devices are estimated to be within 25°C
o f each other.
The polysilicon depletion made it difficult to make an accurate small signal
model o f a small gate width device over the entire frequency range o f 0.5GHz to
26.5GHz. To overcome this obstacle, a FET with gate width o f 120pm was used to
determine the y-parameters o f a FET without effects from parasitics. The distributed
capacitances Cgd, Cgs, and Cds in Figure 5-16 are included in the capacitances o f the
unit FET model, and are therefore set to zero. The distributed inductances, Lg, Ld,
and Ls were calculated by [2] to be 0.0798pH/pm, 0.220pH/pm, and 0.101pH/pm
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117
respectively. Due to the fact that the layout has four parallel gate feeds, the calculated
gate inductance is one fourth o f the inductance o f each individual gate line. The
calculated source inductance is one half o f the inductance for each line since there are
two source connections. The DC resistances were estimated from the known sheet
resistance to be Rg=0.01 Ohm/pm, Rd=4.81e-4 Ohm/pm, and Rs=2.56e-4 Ohm/pm.
During optimization o f the model, the resistances were allowed to increase with
frequency, but this was a very minor effect (increasing from the DC value by 4% at
25GHz). Because o f the layout symmetry, Mgd was set to equal Mgs. The values o f
Mgs, Mgd, and the frequency dependence o f the interconnect resistance were obtained
from parameter optimization.
As is shown in Figure 5-20 and Figure 5-21, the measured y-parameters show
a resonance that decreases in frequency as the FETs are scaled up and the transmission
lines made longer. The frequency o f modeled resonance could be adjusted by tuning
the parasitic series inductance and the mutual inductance o f the interconnect lines.
The magnitude o f the resonance could be adjust by tuning the parasitic resistance of
the interconnects.
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118
0.80
•
*
—
—
0.60
Model:
Model:
Meas:
Meas:
RealY11
Imaginary Y11
RealY11
Imaginary Y11
0.40
0.00
-
0.20
-0.40
0
5
10
Frequency (GHz)
15
20
Figure 5-20. Measured (symbols) and modeled (lines) Y l l of
1296pm wide NFET.
0.70
*
*
—
—
0.60
0.50
0.40
Model:
Model:
Meas:
Meas:
RealY11
Imaginary Y11
RealY11
Imaginary Y11
0.30
0.20
0.10
0.00
-
0.10
-
0.20
-0.30
0
5
10
15
20
Frequency (GHz)
Figure 5-21. M easured (symbols) and modeled (lines) Y l l of
2160pm wide NFET.
The equations were programmed into E E sof s Libra simulator for comparison
to the measured data and for optimization. The mutual inductances in Libra were
calculated from the coupling coefficient, k, and the inductances o f the two coupled
lines given by M yy =
^JLxLy . The coupling coefficients were primarily used to
fit the resonances in the y-parameters, however, values between 0.2 and 0.7 were
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119
considered to be reasonable. The frequency dependence o f the metal resistance was
taken as R = R ^ C o s h fR s e •Frequency) after [3]. After op tim ization, the model was
found to be in excellent agreement with the measured data. The optimized values are
shown in Table 5-1. Most o f the optimized values are close to the initially estimated
values. However, the initially estimated source inductance is much larger while the
estimated gate inductance is smaller than the detailed optimization would indicate.
These values could be affected by pad deembeding for the measured used to derive the
behavior o f the unit cell FET or from deembeding o f the large FET data. The coupling
between the gate and drain lines and the gate and source lines is strong with a coupling
coefficient o f 0.636. A large coupling is expected since these lines are only separated
by 2 pm.
The model for all gate widths used the same values o f the parasitics. The only
parameter that was changed was the length o f the transmission line. The model is in
excellent agreement with the measured data. The s-parameters for the 432pm, 864pm,
1296pm, and 2160pm devices are shown in Figure 5-22 through Figure 5-29.
Table 5-1. Calculated and optimized values o f parasitics.
Ls
Ld
Lg
Rs
Rd
Rg
Rse
kgd=kgs
kds
Calculated
0.101 pH/pm
0.220 pH/pm
0.0798 pH/pm
2.56e-4 Ohm/pm
4.81e-4 Ohm/pm
0.01 Ohm/pm
—
—
—
Optimized
0.00355 pH/pm
0.355 pH/pm
0.328 pH/pm
2.14e-4 Ohm/pm
1.31e-5 Ohm/pm
0.0147 Ohm/pm
0.0116 1/GHz
0.636
0.376
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120
1
3
*
Figure 5-22. Measured (symbols) and modeled (lines) S l l , S12,
and S22 of 432}im gate width NFET from 06GHz to 25GHz.
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121
90
4 .5
45
135
3 .5
2 .5
7 S 21 /
S
1 .5
180
315
225
270
Figure 5-23. Measured (symbols) and modeled (line) S21 of 432fim
gate width NFET from 06GHz to 25GHz.
90
O
06-
0®"
o1
-'
^
Figure 5-24. Measured (symbols) and modeled (lines) S l l , S12,
and S22 of 864|am gate width NFET from 06GHz to 25GHz.
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122
90
45
135
*/
S21
180
315
225
270
Figure 5-25. Measured (symbols) and modeled (line) S21 o f 864fj.m
gate width NFET from 06GHz to 25GHz.
Figure 5-26. Measured (symbols) and modeled (lines) S l l , S12,
and S22 of 1296{xm gate width NFET from 06GHz to 25GHz.
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123
90
45
135
S 21
180
315
225
270
Figure 5-27. Measured (symbols) and modeled (line) S21 of
1296{j.m gate width NFET from 06GHz to 25GHz.
Figure 5-28. Measured (symbols) and modeled (lines) S l l , S12,
and S22 of 2160fj.m gate width NFET from 06GHz to 25GHz.
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124
45
135
S21 \
180
315
225
270
Figure 5-29. Measured (symbols) and modeled (line) S21 of
2160jj.m gate width NFET from 06GHz to 25GHz.
With, accurate models o f the s-parameters, the current gain and power gain can
be predicted. Figure 5-30 and Figure 5-31 show the predicted current and power gain
respectively versus frequency. The model correctly predicts the roll-off behavior of
the current gain versus frequency for the large transistors. The model also correctly
predicts the drop in RF power gain with increasing gate width. It can be seen from
Figure 5-32 that the model shows while ft remains nearly unchanged for a broad range
o f gate widths J^nax drops for all gate widths.
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25
•
▼
■
►
20
•10
i
Wg=432um
Wg=864um
Wg=1296um
Wg=2160um
10
Frequency (GHz)
Figure 5-30. Measured (symbols) and modeled (lines) current gain
0921) versus frequency.
•
T
■
►
25
20
ffi
Wg=432um
Wg=864um
Wg=1296um
Wg=2160um
15
•10
10
1
Frequency (GHz)
Figure 5-31. Measured (symbols) and modeled (lines) unilateral
gain.
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126
a►
*t
\
•
'
Ft
Fm ax
\
m
v
•
•
G a te W id th (u m )
Figure 5-32. Measured (symbols) and modeled (lines) f t a n d /maI
versus gate width.
Using the distributed model, the RF behavior o f MOSFETs up to a gate width
o f 2160pm was accurately modeled based on measurements o f a
1 2 0
pm wide
MOSFET. I f all the distributed parasitics and line coupling are included in the model,
very accurate predictions o f device behavior can be attained.
5.5
Analysis o f Transmission Line Model
The coupled transmission line models predicts the behavior o f the transistors
very accurately. It can therefore be used to gain some insight and understanding about
the transistors. First, the wave propagation along the coupled transmission lines was
examined, then FET structures based on this model were simulated.
5.5.1 Wave Propagation
The propagating electric field can be described by the wave
, where
y = a + j'P , a is the attenuation constant, and p is the phase constant. The group
velocity can be derived by taking the inverse o f the derivative o f P with respect to
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127
frequency. In the solution to the distributed differential equations, y is given by the
two possible eigenvalues, labeled r+ in equations 5-6.
These two eigenvalues
describe the velocity and attenuation o f the two propagation modes supported by the
distributed transmission lines.
hi the limiting case o f there being no source parasitics, no inductive or
capacitive coupling between the gate and drain lines, and the FET is described only by
Cgs, Cds, and gm, the transmission line reduces to that shown in Figure 5-33. In this
limiting case, the gate is. coupled to the drain through the transconductance parameter
gm. The drain line, however, is decoupled from the gate transmission line. A solution
o f the eigenvectors shows there are two modes supported by the transm ission line.
One mode where the signal propagates solely on the drain interconnect, and one mode
where the signal is shared between the gate and drain interconnects.
Ld
Rd
Figure 5-33. Simplified transmission line model.
Similarly, the two modes o f the full distributed model describe the distribution
o f voltage between the gate and drain transmission lines. However, the gate and drain
lines
are
now
coupled
by
mutual
inductance,
coupling
capacitance,
the
transconductance gm, and feedback elements such as Cgd and Rs. This means a signal
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128
launched onto the drain transmission line will not be able to propagate solely on the
drain line, but will instead be coupled to the gate line. A signal launched on the gate
line will immediately be coupled to the drain line through the transconductance as well
as the coupling parasitics and feedback elements. The relative magnitude o f gate and
drain voltages for the two supported modes o f propagation are shown in Figure 5-34.
Mode 1 is for signals launched on the gate line and thus shared between the gate and
drain lines. Mode 2 has voltage primarily on the drain with increasing voltage on the
gate as the coupling becomes stronger at higher frequencies.
Mode 1
Mode 2
1.2
1.2
0 .8
2
— Gate Voltage
— Drain Voltage
0.6
S’ 0 .4> 0 . 2 -----
0
>
5
10
15
Frequency (GHZ)
20
"
25
0.2
-
00
5
10
15
20
Frequency (GHz)
25
Figure 5-34. Voltage distribution on gate and drain line for two
modes of full distributed transmission line model.
Figure 5-35 shows the attenuation per centimeter o f the two modes versus
frequency. The large attenuation is expected on the scale o f centimeters, as the widths
o f the interconnect lines are narrow, leading to large resistivities for long lengths (eg
4.8 Ohms for a 1cm long drain line and 100 Ohms for a 1cm long gate line). The
lengths o f the actual interconnects are on the order o f hundreds o f microns only, so the
predicted attenuation is not unreasonable for the actual experiment. This predicted
attenuation can be compared to the actual drop in measured power gain.
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The
129
attenuation o f modes 1 and 2 was normalized for 300jmi length, the difference in the
transmission line length o f the 432pm transistor and the 2160pm transistor. This is
compared in Figure 5-36 to the measured drop in unilateral gain between these same
two transistors. The attenuation o f mode 1 matches the drop in power gain almost
exactly over the frequency range o f 3GHz to 18GHz. Based on the distribution o f
voltages in Figure 5-34, mode 1 should be the primary propagation mode.
The output current and power gain are affected not only b y the attenuation o f
signals along the transmission lines, but also by constructive and destructive
interference effects. The interference effects are associated with the different phases
o f the signals along the gate and drain lines, as well as by the reflections at the ends o f
the gate and drain lines.
400
350
300 S
-S2 250
CD
*o
§
200
CO
150
100
-
50 -
0
5
10
Frequency (GHz)
15
20
Figure 5-35. Attenuation constant, a, versus frequency for the two
propagation modes.
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130
12
I 10
ID
O
5
Q
=
CD
8
Measured Gain Drop
• Mode 1 Attenuation
•Mode 2 Attenuation
6
CD
'c
SCO 4
3c
<
D
%
2
0
0
5
10
15
20
25
Frequency (GHz)
Figure 5-36. Attenuation for mode 1 and 2 for a 300pm long
transmission line compared to the difference in power gain
between the 432pm and 2160pm transistors.
Figure 5-37 and Figure 5-38 show the group velocity and phase velocity o f the
two propagation modes. Based on interconnect length and effective dielectric constant
o f the material around the interconnect, a group velocity o f one third to one half o f the
free space velocity is expected. However, mode 1 only has a group velocity on the
order o f one tenth the speed o f light. This gives an effective dielectric constant of
about 100 for the transmission line, far greater than is possible. This shows that the
propagation velocity along the interconnect lines is dependent more on the capacitive
loading by the active device than the physical parameters o f the dielectric media.
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131
0.2
cl
-Mode 1
-Mode 2
0 .1
0.05
0
5
10
Frequency (GHz)
15
20
Figure 5-37. Group velocity of two propagation modes relative to
free space velocity (c).
0.16
0.14
0.12
CL.
>
&
0.1
-Mode 1
- Mode 2
O 0.08
>
8ro 0.06
sz.
a.
0.04
0.02
0
5
10
Frequency (GHz)
15
20
Figure 5-38. Phase velocity of two propagation modes relative to
free space velocity (c).
The dependence on the capacitive loading by the active device helps to explain
why the low frequency characteristics tend to drop quickly. The gate interconnect has
extra capacitance from Cgs and Cgtj. However, Cgd is multiplied by the MOSFET’s
gain due to the Miller effect.
Therefore the capacitive loading decreases with
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132
frequency, as the gain drops. When Cgd is no longer a dominant factor, the curve tends
to level off.
For silicon-on-sapphire MOSFETs, Cgs+Cgd is generally 4-10 times larger than
Cds, without taking the Miller effect into account. Due to the higher capacitance, the
signal on the gate transmission line will travel much slower than the signal on the
drain transmission line. This will lead to de-phasing o f the signals, causing destructive
power com b ining. Since the group velocity is much smaller than expected from the
material dielectric constants, the destructive power com b ining will have a measurable
effect over shorter distances than expected on the basis o f the wavelength in the
dielectric material.
Mathematica was used to solve for the real part o f the gate and drain voltages
as a function o f position. First the z-parameters were calculated as described above.
This was used to solve for H21, the current gain. The output current was assumed to
be one h alf o f the input current times H21. This would correspond to the FET having
a conjugate output match such that half o f the current goes to the output load and half
through the device output resistance.
More importantly, this corresponds to not
having any reflections on the input or output o f the transmission lines. The only
unknown parameter was then the input current.
This is an independent variable,
depending on the power o f the input signal. The gate input current was chosen to
correspond to a —20dBm signal into a 50 Ohm load. The solutions to the gate and
drain voltage waveforms o f the 2160pm transistor under these conditions are shown in
Figure 5-39 and Figure 5-40 respectively.
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133
Small Signal Gate V oltage
0.0020
0.0015
° Frequency=5 GHz
x Frequency=9.8 GHz
° Frequency=13 GHz
0.0010
0.0005
0 .0 0 0 0
0
1 0 0
200
300
400
Position (n.m)
Figure 5-39. Gate voltage as a function o f position along coupled
transmission lines for 2160pm transistor.
Small Signal Drain Voltage
0.0020
0.0015
a Frequency=5 GHZ
x Frequency=9.8 GHz
° Frequency=13 GHz
0.0010
0.0005
0.0000
0
100
200
300
400
Position (pm)
Figure 5-40. Drain voltage as a function of position along coupled
transmission lines for 2160pm transistor.
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134
The right end o f the gate line in Figure 5-39 and the left end o f the drain line in
Figure 5-40 have open circuit boundary conditions. Reflections from the open-circuit
end o f the transmission lines cause rises in the voltage at the end o f the line. At high
frequencies, the gate voltage waveform is attenuated more along the gate transmission
line.
If the gate signal decays along the line, the gate fingers at the end o f the
transmission line will not be excited as much as the first gate fingers. The drain
voltage waveform has a shorter wavelength than the gate waveform, meaning the drain
waveform has a higher propagation velocity. This is expected, since the drain line has
lower capacitance than the gate line.
The resistance, inductance, capacitance, and coupling are all important in
predicting the behavior o f the large transistors. The resistance provides for some o f
the drop in RF performance, but a significant part o f the degradation comes from delay
along the transmission lines resulting in destructive power combining.
5.5.2
Simulated structures
The model also provided a means to simulate the RF performance o f some
FET structures without fabrication. Two structures are presented here, both are based
on the three coupled transmission line model developed in this chapter. However,
instead o f using the mathematical equations, a lumped element model was used. The
transmission lines were broken up into 3.75(im long segments to approximate the
distributed nature o f the transmission lines, which has nearly the same behavior as the
distributed mathematical solution.
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135
5.5.2.1 Gate and Drain on Same Side
The devices that were fabricated and tested had the gate and drain probe pads
on opposite sides o f the layout. This helped to facilitate the use o f high-speed groundsignal-ground probes. In simulation, the situation with two connections put on the
same side o f the transistor can be considered. This changes the boundary condition
from those shown in Figure 5-17 to the boundary conditions shown in Figure 5-41.
X =0
X =L
Figure 5-41. Gate and drain connection on same side rather than
opposite sides.
The change in probe location increases the phase difference between the
closest gate fingers and the farthest gate fingers. The farthest gate fingers have a delay
associated with the signal propagating down the gate line a distance L, through the
FET, then back along the drain line a distance L while the closest gate fingers only
have a delay through the FET. This should increase the RF gain degradation, as the
dephasing will be increased. The 432pm and 2160pm devices were compared with
the connections on the same side and the connections on the opposite side. The power
gain (MAG/MSG) is shown in Figure 5-42. The open symbols are for the simulations
with the gate and drain connected on opposite sides (similar to the measured devices).
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136
25
432um S a m e S ide
-■— 2160um S a m e S ide
-e— 432um O pposite S ide
■a— 2160um O pposite Side
15
m
"O
CD
CO
2
CD
<
2
1
Frequency (GHz)
10
Figure 5-42. Power gain for 432pm and 2160 pm transistors with
gate and drain connections on same side and on opposite side.
For the 432(jm device, there is very little difference, as expected. The short
transmission line o f the small device will not significantly affect the phase o f the
signal. There is a slight drop in power gain at high frequencies. However, Figure
5-42 shows an unexpected result for the 2160pm device. Connecting the gate and
drain on the same side (solid squares) increases the destructive power combining
noticeably, causing a drop in the gain at 2GHz.
However, at 8 GHz, the gain rises
back above the simulated structure with the gate and drop connected on the opposite
sides. As shown by the waveforms in Figure 5-39 and Figure 5-40, as the frequency
increases, the signal penetrates less along the gate transmission line.
At high
frequencies, the gate fingers closer to the gate input have higher signal strength than
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137
the gate fingers farthest from the gate input.
Therefore, at high frequencies the
average signal path from gate to drain is much shorter with the gate and drain on the
same side than with the gate and drain on opposite sides. The shorter signal path
reduces the resistive loss o f the interconnects, giving rise to a higher gain at high
frequencies.
5.5.2.2 M ultiple Probe Pads
For many applications, it is possible to design large transistors with many input
and output points. Transistors designed for wirebonding are usually designed in this
manner, to have parallel wirebonds. An example o f this type o f layout is shown in
Figure 5-43. The transmission line for this type o f layout horizontal, with intermittent
connection points to the gate input and drain output. The lumped element model was
used to simulate this type o f structure with four connections to the gate and the drain.
The gain versus frequency is shown in Figure 5-44 for the 432pm and 2160pm
devices as fabricated and for the 2160pm device with four probe pads.
DRAIN
DRAIN
DRAIN
DRAIN
Figure 5-43. Example of large transistor layout with many probe
pads.
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138
25
-*— 432um O n e P ad
-«— 2160um O n e Pad
■e— 2160um F our Pads
20
m
"O
CD
CO
5
CD
<
2
1
10
Frequency (GHz)
Figure 5-44. Power gain (MAG/MSG) for 432|xm and 2160p.m
transistors connected as fabricated and with many four probe
pads.
It can be seen that with this type o f connection, much o f the power gain can be
recovered. This type o f layout also has the advantage that the pad parasitics and
bondwire parasitics scale better with gate width than for a device with a single probe
pad. However, it should be noted the simulation with four probe pads had an ideal
power splitting and combining. In a real implementation, there will resistive loss in
the feeding structure that was not accounted for. Furthermore, if the bondwires do not
have the exact same length, there may also be phase differences introduced into the
feeding structure, resulting in lower gain.
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139
5.6 Conclusions for Chapter 5
The effects o f layout parasitics can be very accurately modeled by the use o f a
coupled transmission line model. The effects that degrade the microwave gain o f the
transistors are the resistive loss in the interconnects, the phase delay between the
different gate fingers, and the stronger attenuation o f the gate signal at high
frequencies. The resistive loss o f the lines is very easy to account for based on the
sheet resistance o f the interconnects. The distributed inductance and capacitance is
important in determining the phase delay, which causing a drop in gain due to
destructive power combining. Due to the loading o f the transmission line by the active
device capacitances, the group velocity is smaller than expected.
This makes it
possible for the destructive power combining to be an important factor at lower than
expected frequencies.
The attenuation along the gate transmission line at high
frequencies is important for layouts with long segments o f active transistor area. The
gate fingers farthest from the gate input provide little addition to the signal at high
frequencies. This is believed to be the cause o f the roll-off off t with frequency for the
large devices.
In theory most o f the RF performance o f the large periphery transistors can be
regained through layouts with many input and output probe pads. Under this type o f
design, all o f the gate fingers are within a short distance o f the probe pads. This helps
to mitigate the phase delay between different fingers and the problem o f the
attenuation o f the input signal at high frequencies.
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140
The optimum type o f layout design depends on the application. For operating
frequencies lower about 2GHz, layouts in SOS technology can be made as compact as
possible without severely degrading the current and power gain. For higher operating
frequencies careful consideration must be made about the layout style. I f possible for
the application, a layout with many bondpads would provide the best performance.
5.7
References
1.
R.A. Johnson, C.E. Chang, P.R. de la Houssaye, G.A. Garcia, I. Lagnado, P.M.
Asbeck, “Microwave characteristics o f high/max low noise thin film silicon-onsapphire MOSFETs”, IEEE International SO I Conference, October 1995.
2
H.M. Greenhouse, “Design o f Planar Rectangular Microelectronic Inductors”,
IEEE Transactions on Parts, Hybrids, and Packaging, vol. 10, no. 2, June
1974, pp. 101-109.
3.
S.J. Nash, A. Platzker, W. Struble, “Distributed Small Signal Model for MultiFingered GaAs PHEMT/MESFET Devices”, IEEE M icrowave and M illimeterWave M onolithic Symp. Digest, pp. 219-222, 1996.
4.
S. Masuda, T. Hilrose, Y. Watanabe, “An Accurate Distributed Small Signal
FET Model for Millimeter-Wave Applications”, IEEE M TT-S D igest, pp. 157160, 1999.
5.
C.Y. Wong, J.Y.-C. Sim, Y. Taur, C.S. Oh, R. Angelucci, B. Davari, “Doping
o f n+ and p+ polysilicon in a dual-gate CMOS process”, IEEE D igest o f the
International Electron Devices Meeting, pp. 238-241, 1988.
5.8
Acknowledgements
Some o f the material in this chapter is as it appears in "Layout Parasitic Effects
on Microwave Characteristics o f Large Periphery Transistors", IEEE Topical
Workshop on Power Amplifiers fo r Wireless Communications, San Diego, CA, Sept.
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141
2000. I would like to acknowledge the co-authors P. R. de la Houssaye, P. M. Asbeck,
and I. Lagnado. I was the prim ary investigator and primary author for this publication.
Some o f the material in this chapter also appears in "Prospects o f CMOS
Power Amplifiers on Thin Film SOS for Wireless Applications," F irst Annual UCSD
Conference on Wireless Communications, San Diego, CA, March 1998. I would like
to also acknowledge the co-authors o f this publication R.A. Johnson, P.F. Chen, B.
Xavier, P.R. de la Houssaye, P.M. Asbeck, I. Lagnado.
I was also the primary
investigator and primary author o f this paper.
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6 Power Amplifier
6.1 Introduction
Standard short gate length MOSFETs have a relatively low breakdown voltage.
In order for these devices to output high power, the gate width must be scaled up to
provide a large current.
According to the results o f chapters 3-5, large periphery
transistors can be fabricated, and only have minor effects from self-heating.
Furthermore, although the f t and
o f the transistors drops with increasing gate
width, reducing the distance between the gate fingers and the probe pads can minimize
this effect. The gain at frequencies used in current wireless communication systems
(<2GHz) does not drop severely with gate width. The large transistors still have
adequate gain at these frequencies for use in communication circuits. Building and
testing a power amplifier with these devices helps to test the predictions that the self­
heating will not be too detrimental and that the gain at 1GHz will not be severely
degraded by the layout parasitics.
Using SOS technology for power amplifiers has many possible benefits. One
benefit comes from the superior device isolation o f the insulating sapphire substrate.
In bulk CMOS, single-ended circuits tend to have higher substrate coupling than fully
balanced circuits; however, in SOS technology, the substrate coupling should be easy
to overcome. This will allow for the integration o f the power amplifier with other
analog and digital circuits.
SOS technology is well suited for both scaled CMOS
digital circuits (as shown in chapter 2 ) and for high performance analog circuits (as
142
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143
discussed at the end o f section 1.3). I f a high performance SOS power amplifier could
be demonstrated, all transceiver components could be fabricated in a single
technology,
possibly
leading
to
a
system-on-a-chip
solution
for
wireless
communications.
In this chapter, first the effects o f CMOS scaling on power amplifiers will be
discussed followed by an introduction to class A and class B amplifier operation.
Next the design and implementation o f the SOS amplifier w ill be discussed. This
includes a brief discussion o f bias circuitry, techniques used to stabilize the amplifier,
and choice o f load line for the amplifier.
Then the experimental results o f the
amplifier will be presented. This includes data corresponding to simple sine wave
inputs as well as results from code division multiple access (CDMA) modulated input.
Finally the results will be compared with simple calculations, simulations, and results
from other technologies.
6.2 Effects of Scaling on Power Amplifiers
In section 1.2, many o f the benefits o f device scaling were discussed. The
benefits include increased^ and^nax which lead to increased current and power gain,
reduced operating voltage which leads to lower power dissipation in digital circuits,
and increased integration density which leads to smaller die size and reduced cost.
The increased speed o f scaled MOSFETs was demonstrated in chapter 2 with the
fastest MOSFET frequency divider. Although scaled CMOS circuits are advantageous
for low power digital and analog receiver and transmitter components [ 1 , 2 ], there are
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144
great difficulties in using scaled CMOS for power applications due to the reduced
breakdown voltage.
The critical device parameters for a power amplifier are the gain o f the device,
the on state resistance (Ron), and the breakdown voltage. A low on-resistance makes it
possible to have a low knee voltage and high efficiency (as will be discussed in the
next section). High breakdown voltages allow the device to have large voltage signals
to provide high output power and high efficiency. Figure 6-1 shows the measured onresistance and breakdown voltage for SOS NMOS devices fabricated at SPAWAR
using a 1000A thick silicon film with 100pm gate width. The breakdown voltage
(corresponding to the voltage Vds where the current begins to sharply rise) was
measured with Vgs=0V. The on-resistance improves approximately linearly with gate
length scaling. However, the breakdown voltage drops rapidly as the gate length
becomes less than 1 pm.
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145
10
8
_ s£?=
6
o
"O
jt:
ca
4
CQ
£
■<o0
>
2
0
0
1
2
3
4
5
Drawn Gate Length (um)
Figure 6-1. On resistance drain-source breakdown voltage versus
drawn gate length for SPA WAR SOS NMOS devices.
The breakdown voltage is not the only consideration for maximum voltage
ratings.
For short gate length devices, it is also important to consider hot-carrier
degradation. High electric fields present in short channel devices can lead to electrons
in the channel having enough energy to be injected into the gate oxide, damaging the
gate oxide, degrading the device characteristics and reducing the device lifetime [3,4],
To avoid this detrimental effect and provide a long circuit lifetime, the DC bias
voltage is usually taken to be only one-half to one-third o f the breakdown voltage.
The lower voltages necessary for a scaled MOSFET technology make it impossible to
attain high output powers through large voltage swings. Therefore, high power must
be attained through high current swings. This alleviates pressure on device breakdown
and lifetime, but brings new challenges to the circuit design.
In order to increase the output current, large periphery devices must be used.
As shown in previous chapters, the larger the device, the lower the microwave gain.
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146
Lower gain will degrade the overall system performance (although at frequencies
lower than about 2GHz, the gain may not be severely degraded). The high current and
large periphery also make output matching very difficult. In general, most circuits are
matched from the device load impedance to a 50 Ohm reference. With high currents
and low voltage swing, the 50 Ohm reference must be transformed to a small load
impedance at the device.
A 1 Ohm to 50 Ohm transformation is about the practical limit o f impedance
matching. Even at this level there are many difficulties. As the transformation ratio
increases, the Q o f the matching circuit increases and the bandwidth o f the circuit
decreases. With an impedance transformation ratio o f 50:1, the bandwidth is already
narrow enough to put tight restrictions on manufacturing tolerances. In addition, it is
difficult to implement a high transformation ratio matching circuit while keeping the
loss in the matching circuit to a minimum. Even small losses in the output matching
circuit have a large effect on amplifier efficiency.
Even though scaled MOSFETs have higher speed, deep-submicron MOSFETs
are not suitable for power amplifiers.
The low breakdown voltage decreases
efficiency and output impedance to unacceptable levels.
6.3 Class A and B Amplifier Operation
In a class A amplifier, the transistor is biased half way between the minimum
and maximum voltage and current swings.
A simple load line analysis is shown
superimposed on measured device data in the left half o f Figure 6-2. The load line
shows the transistor output voltage and current assuming an ideal resistive load. The
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147
resistive load is equal to the slope o f the load line. It should be noted in an actual
implementation the load line should not extend into the device’s linear region. In the
linear region the transconductance depends on the drain voltage, causing distortion o f
the output signal. A constant transconductance will be assumed along the entire load
line for this section.
1.4
^
0.8
S••
~ 1.5 ■—V
0.4------- ^
02.
0
1
2
3
Time
Figure 6-2. Left: Load line of class A amplifier. Right: Ideal
voltage and current waveforms of class A amplifier at full power
and half power.
The right half o f Figure 6-2 shows the ideal output current and voltage
waveforms for class A operation. The figure contains the waveforms for both the
maximum output power and half o f the m axim um output power. Because the bias
point is independent o f the output power, it can be seen that the average, or DC, power
o f a class A amplifier remains constant. This gives the class A amplifier a relatively
low drain efficiency (RF output power / DC input power) at low input powers.
While the efficiency is low, the linearity o f the class A amplifier is very good.
In realizable FETs, the transconductance can be made fairly constant as long as the
load line does not approach the maximum drain current or maximum drain voltage o f
the load lines shown in Figure 6-2. This is equivalent to having a slightly lower
maximum output power in order to maintain high linearity.
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148
The maximum output power from a class A amplifier is given by
n
_
* RFMax
Max ~ Vknee y^Max
g
(6 - 1 )
The drain efficiency is giving by
PRF
( 6 -2 )
PDC
Equations 6-1 and 6-2 can be combined with the DC power consumption o f the
amplifier. Li the case where the knee voltage goes to zero, the drain efficiency is
limited to a maximum o f 50% for class A amplifiers.
Class B amplifiers have an input Vgs bias such that the transistor is off with no
RF input signal. As the RF input signal rises, the transistor is turned on, producing an
output current. The load line and waveform o f the class B amplifier are shown in
Figure 6-3. As can be seen from the waveforms, the average, or DC, drain current
changes with output power. However, the output current waveform is only a half sine
wave. By fourier transform, it can be shown that the output waveform now has a DC
component, a component from the fundamental frequency, and even harmonics o f the
fundamental frequency. The even harmonics are usually shorted out so they do not
provide any current to the load, and the device voltage is purely sinusoidal.
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149
e
—
—
—
—
5
Current
Votage
Current (half power)
Votaoe (half power)
Figure 6-3. Left: Load line of class B amplifier. Right: Ideal
voltage and current waveforms of class B amplifier at full power
and half power.
Due to the fact that the class B amplifier changes the DC power depending on
the RF input power, class B amplifiers can attain much higher efficiency than class A.
However, a class B amplifier can not avoid the part o f the load line with low gate
voltages, and therefore can not avoid nonlinearities in the transconductance as the FET
turns on and off. This effect together with the inherent generation o f harmonics give
the class B amplifier a lower linearity than the class A amplifier.
In general, the
higher the efficiency, the lower the linearity. Class C, D, E, F, and S amplifiers are
inherently nonlinear, but have much higher maximum efficiencies than class A or
class B.
The maximum output power o f a tuned class B amplifier with a short for even
harmonics is unchanged from the class A amplifier is given by equation 6-1.
However, the output current is zero for half o f the wave, reducing the current gain by a
factor o f 2, or 6 dB reduction in gain from a class A amplifier. The DC power is given
by
(6-3)
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150
Equations 6-1, 6-2 and 6-3 can be combined, giving a maximum o f ti/4, or
78.5% when the knee voltage is zero. The maximum efficiencies o f 50% and 78.5%
for class A and B respectively can only be attained with a zero knee voltage. Figure
6-4 shows the predicted efficiency for class A and B based on load line analysis
presented in Figure 6-2 and Figure 6-3 assuming a maximum tolerable Vds o f 3V. Due
to the high knee voltage, the maximum efficiency has been reduced to 25% and 39%
for class A and B respectively. Due to the low maximum voltage used in these load
line analyses, the load resistance was only 2.3 Ohms, for a device with gate width of
4.012mm. The corresponding maximum output power for this load line is 23.4dBm
(217mW). This power is higher than can actually be achieved because as the load line
enters into the linear region, the transconductance and gain drop.
The load line
analysis assumes the gain remains constant in the linear region.
40%
Class A
-o- Class B
CD
k_
Q
0
0.25
0.5
0.75
Power / Maximum Power
Figure 6-4. Efficiency o f class A and B based on load line analysis
of device data shown in Figure 6-2 and Figure 6-3.
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151
This load line analysis helps to highlight the dependence o f the maximum
power and efficiency on device characteristics o f breakdown and on-resistance. It
should also be noted that power amplifier output matching is not done solely based on
the transistor’s small signal output impedance.
Instead, power amplifier output
matching is based on an analysis o f maximum output power and power efficiency on a
large signal basis.
6.4 Design and Implementation
As a demonstration, a 1GHz NMOS SOS power amplifier was designed and
implemented. The devices were fabricated at Peregrine Semiconductor (technology
described in section 5.4.1) with support from SSC San Diego. The device has a gate
length o f 0.5pm, gate width o f 4012pm, a breakdown voltage o f 4V, and a maximum
Vdd rating o f 3.6V. The on-resistance for the devices used in the power amplifier, as
shown by Figure 6-5, is approximately 2.70hm-mm.
1.80hm-mm o f the on-
resistance corresponds to the source and drain contact resistance, and the remainder is
the channel resistance at maximum gate bias. The devices, designed and tested at
UCSD, use a layout strategy o f having many input and output bondpads to keep
devices close to the probe pads, as described in section 5.5.2.2.
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152
5 —
y = 2 .4 7 x + 1.79
®3
0.5
0
1
1.5
2
1/(Vg-Vth) (1/V)
Figure 6-5. Extraction o f on-resistance for SOS power amplifier
device fabricated at Peregrine Semiconductor (Lg=0.5pm,
Wg=4012|xm).
The power amplifier was implemented as a hybrid circuit, using a packaged
NMOS transistor, surface mount inductors, resistors, and capacitors, and microstrip
transmission lines. Details about the model o f the circuit board material to describe
the transmission lines are given in appendix B. A circuit schematic o f the amplifier is
shown in Figure
6
-6 , showing both unintentional (parasitic) elements as well as
intentional circuit elements (for input and output impedance matching and
stabilization). The values o f the elements used in the power amplifier are given in
Table 6.1. Inductors L4 and L5 are via inductance o f the circuit board and have been
estimated to be 0.75nH. Inductors L I, L2, and L3 are the bondwire inductances, and
have been estimated based on the length of the bondwires and number o f parallel
bondwires. Transmission lines T1 and T2 take into account the length o f line in the
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153
package between the bondwires and the package output, and have different physical
parameters than the other transmission lines. Transmission lines T5 and T 6 along with
capacitors C3 and C4 and via inductance L4 and L5 form quarter wave shorts for DC
biasing, as described in appendix B.
These quarter wavelength lines also help to
provide a short circuit for even harmonics.
R1
L6
\88Ur
Drain
Voltage
C5
T7
T8
R4
j-vfflfc— IH
*
1.4
C3
T5
RF
Input
T6
C2
T9
T10
C1
T3
L3
T1
T2
T4
LI
L2
T12
R2
Til
I_____
Packaged NMOS Device
Figure 6-6. Circuit schematic of NMOS power amplifier.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
154
Table 6.1. Circuit element values used In power amplifier
R1
R2
R3
R4
Cl
C2
C3
C4
C5=C6
LI
L2
L3
L4
L5
L6
L7
T1=T2
T3
T4
T5=T6
T7
T8
T9
T10
T il
T12
10 Ohms
100 Ohms
10 Ohms
24 KOhms
15 pF
10 pF
40 pF
40 pF
3 capacitors in parallel: 10 pF, 22 nF, 2 uF
0.65 nH
0.2 nH
0.1 nH
0.75 nH
0.75 nH
22 nH
22 nH
Package bondwire landing
W idth = 120mil, Length = 300mil
W idth = 120mil, Length(to T12)= 1lOmil,
Length(to C2/R2)=300mil
W idth = 25mil, Length = 1730mil (quarter
wavelength short for 1GHz)
W idth = 25mil, Length = 300mil
W idth = 25mil, Length = 450mil
W idth = 120mil, Length = 390mil
W idth = 120mil, Length = 2,250mil
Zo~50 Ohms, Length = l,250mil
Zo~50 Ohms, Length = l,450mil
Since the DC biasing o f the gate o f a MOSFET does not draw any current,
resistors in series can be used along the gate bias line to help avoid oscillation.
Resistor R3 helps to provide some loss in DC bias line, dampening possible
oscillations.
Resistor R 4 is very large, effectively blocking RF and possible low
frequencies oscillations from proceeding up the bias line. Using a large resistor value
for R3 caused low frequency oscillations at high input power.
This type o f
termination on the gate line was necessary in order to prevent oscillations.
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155
W ith large drain currents, series resistors can not be used without severely
cutting down the amplifier efficiency. To avoid low frequency oscillations, a 40pF
capacitor was used for the end o f the shorted quarter wavelength bias line. At 1GHz
this capacitor has an impedance o f 40hm s. Although this does not provide an ideal
short at 1GHz, the capacitor is small enough to provide a sizable impedance at lower
frequencies. To avoid oscillation, it is important to keep low frequencies from having
a low loss path to ground at the transistor output, which would lead to reflections back
to the transistor causing oscillations. Inductor L7 in parallel with resistor R1 provides
a low resistance path for DC current while higher frequencies (72MHz and higher)
have a smaller impedance through resistor R l. Thus most low frequencies have a
lossy path to ground, dampening oscillations on the drain bias line. Isolation between
the circuit and power supply was achieved by using a ferrite core to create a large
inductance (estimated at > lpH ) and large bypass capacitors to ground on the circuit
board.
Even with these carefully designed bias lines, oscillations were still present
with a large input RF signal. Under certain conditions, the amplifier would oscillate
between 70MHz and 400MHz. In order to reduce the gain at frequencies below 1GHz
and make the amplifier more stable, capacitors C l and C l and resistor R2 were added.
Capacitors C l and C2 are relatively small, providing a high impedance to lower
frequencies. The parallel combination o f C2 and R2 was designed to help attenuate
the lower frequencies. While low frequencies will pass through R2, high frequencies
such as the design frequency o f 1GHz will pass through C2.
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156
The hybrid amplifier was implemented using an FR-4 circuit board connected
to an aluminum block. The aluminum block provides both mechanical stability and a
ground for both the circuit board and the transistors. Good ground contact must be
maintained between the circuit board and the aluminum block to avoid oscillations.
Tuning o f the input and output match was done with open circuit microstrip
stubs on the input and output RF line. First the output was matched based on load line
analysis, then the input was matched through s-parameter measurement o f the input
reflection coefficient. The transistor characteristics were shown earlier in Figure 6-2
and Figure 6-3. Figure 6-7 shows the maximum output power and drain efficiency
based on DC device measurements, an assumed breakdown o f 3.5V, and assuming the
load line must stay out o f the linear region. For maximum output power, a load
resistance o f 0.75Ohms is required. For maximum drain efficiency, an output load
resistance o f 60hm s is required.
Based on this analysis, the amplifier was designed with a gate bias o f 0.25V
and drain bias o f 2V. The target output power was at least lOOmW (20dBm), so the
desired output match was chosen to be 1-2 Ohms, closer to the match for maximum
output power. According to this simple analysis, a lOhm output match should give a
maximum output power o f 22dBm and a drain efficiency o f 31.3%. Matching such
low impedances are sensitive to the exact microstrip positions and lengths, so a
separate circuit board was fabricated with just the output h alf o f the amplifier (as
shown in the last section o f appendix B). In this way, the impedance presented to the
device could be checked. A picture o f the finished amplifier is shown in Figure 6 -8 .
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
25.00
45.00%
20.00
40.00%
15.00
35.00%
10.00
30.00%
5.00
25.00%
0.00
0.00
2.00
4.00
6.00
RIoad (Ohms)
8.00
20 .00 %
10.00
Figure 6-7. Maximum output power and drain efficiency based on
load line analysis.
Figure 6-8. Photograph of NMOS power amplifier. Total board
size is 4 inches by 6 inches and is mounted on an aluminum block.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Drain E fficiency
Maximum
Output Power (dB m )
157
158
6.5 Experimental Results
After the circuit was built and tuned, the s-parameters were measured to
determine input and output reflection and gain versus frequency. Figure 6-9 shows the
input match, SI 1, versus frequency. At the DC gate bias voltage o f 0.25V, the match
appears to be relatively poor, with a reflection o f —9.5dB at 1GHz. However, as the
transistor self biases with increasing RF input power, the average gate voltage
increases. Figure 6-9 shows that S l l drops to less than —15dB for higher gate biases.
Thus for the average signal, the input match is fairly good.
-15
-20
-25
0
500
1500
Frequency (MHz)
1000
2000
2500
Figure 6-9. Input match of SOS power amplifier with Vd=2V.
I f the output match is done to give a m in im um S 22, the transistor would be
matched for maximum gain, and have relatively low m ax im u m output power and
efficiency. The output match for a power amplifier is determined by the load line, and
therefore the S22 is poor. At the DC gate bias o f 0.25V, S22 is only —2.5dB. S22
improves at higher gate biases, dropping to —5dB at a gate bias o f IV as shown in
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159
Figure 6-10. Although this matching is necessary to achieve the desired output power,
it results in a poor reflection on the output. Normally an S22 o f less than —lOdB is
desired to achieve high gain and withstand large voltage standing wave ratios
(VSWR).
■o
,
s r - io CM
-15
-20
0
500
1500
Frequency (MHz)
1000
2000
2500
Figure 6-10. Power amplifier output match with Vd=2V.
Figure 6-11 shows the gain, S21, o f the amplifier versus frequency. At higher
gate biases, the amplifier has 10-1 ldB o f gain between 500MHz and 1GHz. The gain
at 1GHz is 3.3dB lower at the DC bias level o f 0.25V than at a gate bias o f 0.5V. The
lower gate bias required for class B operation leads to a lower gain than is achievable
with a class A amplifier. In order to increase the stability o f the amplifier, capacitors
and resistors were added to decrease the low frequency gain. However, the gain still
increases to about 15dB at 300MHz.
At 300MHz the amplifier is still close to
oscillation, but with a 50Ohm load, is stable.
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160
20
15
C
■Q
o
-Vg=0.25V
-Vg=0.5V
-Vg=1V
-5 -10
0
500
1000
1500
Frequency (MHz)
2000
2500
Figure 6-11. Power amplifier gain versus frequency with Vd=2V.
The rest o f the amplifier characteristics were measured using signal generators
and power meters as described by Figure 6-12. For the two-tone test, the single signal
generator was replaced by two signal generators connected through a power combiner
and two isolators. The —20dB power couplers help to measure the available input
power and the delivered output power without having to measure losses in the
isolators, power combiners, or cables.
Power
Meter
Gate
bias
Drain.
bias
-20dB
Signal
Generator
Power
Meter
-20dB
SOS PA
HP8565e
Spectrum
Analyzer
Figure 6-12. Power amplifier measurement setup.
Figure 6-13 shows the amplifiers gain and output power as a function o f input
power. The gain expansion right before the gain compression is characteristic of
many power amplifiers and is likely due to increasing transconductance with
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161
increasing signal level on the gate input. The gain at low input powers is 7.9dB. At
an input power o f 14.6dBm, the gain drops by ldB to give an output power o f 21.5dB.
The highest input power measured for this power sweep was an input power o f
19.3dBm, which corresponds to a gain o f 4.9dB (3dB lower than the maximum) and
an output power o f 24.2dBm. The ldB gain compression occurs with an output power
o f 21.5dBm, above the target o f 20cLBm.
25
- -1 5
6
-5
r 4-- -15
---25
-35
-40
-30
-20
-10
0
10
20
Input Power (dBm)
Figure 6-13. Gain and output power versus input power.
Another important characteristic is the efficiency o f the amplifier. Figure 6-14
shows the amplifiers output power and drain efficiency versus input power. The drain
efficiency is simply the RF output power divided by the DC power consumption. At
the ldB compression point (input power o f 14.6dBm), the amplifier has a drain
efficiency o f 35% and an output power o f 21.5dBm.
According to the load line
analysis shown in Figure 6-7, a 1.5 Ohm load will give a maximum output power o f
21.6dBm and a drain efficiency o f 33.1%. Although it is difficult to measure the exact
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162
load impedance presented to the packaged device, it is expected to be l-20hm s. The
load line analysis is in very good agreement with the performance at the ldB
compression point. The highest measured drain efficiency was 47% at the point were
the gain had dropped by 3dB.
30
50%
2 0
--
10
-
-- 40%
m
T 30%
-
-10
o
-2 0
m
20% -f
--
10
%
-30 -40
0
-40
-30
-20
-10
0
10
%
20
Input Power (dBm)
Figure 6-14. Output power and drain efficiency versus input
power.
Wireless system requirements, especially for handheld applications, must take
the power added efficiency (PAE) into consideration. The power added efficiency
takes into account the amount o f input RF power needed to drive the amplifier. If an
amplifier has high gain, the PAE is close to the drain efficiency. However, in this
case, the gain is below 8 dB, so the PAE is measurably lower than the drain efficiency.
p
The PAE is calculated from the equation PAE = RFout
p
Rfjn_
pjg^-g g_i 5 shows
PDC
the PAE versus input power. At the ldB compression point, the PAE is only 28%,
and reaches a maximum o f 32% for high input power.
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163
30
35%
2 0
30%
UJ
E
m
,u
i
0
25%
2 0
%
<
CL
>
oc
o
eUJ
£Q_
3
-io
o
-20
■o
<
10%
§O
-30
5%
15%
-40
0
-40
-30
-2 0
-1 0
0
10
T3
CD
T3
Q_
%
20
Input Power (dBm)
Figure 6-15. Output power and power added efficiency versus
input power.
Some o f today’s digital modulation schemes have tight requirements on power
amplifier linearity. The first test o f linearity was a standard two-tone test. Two sine
waves (fi and f 2 ) separated by 1MHz were used as the input signal. The nonlinearities
o f the device cause an interaction between these two signals which generates a new
signal, the third order intermodulation product, which appears at frequencies 2 fi-f2 and
2f2 -f,. Since the intermodulation products are in the frequency band o f interest, they
can not be filtered out. Instead they must be minimized by keeping the amplifier as
linear as possible.
Figure 6-16 shows the results o f the two-tone measurement. The extraction of
the third order intercept point (EP3) is done in the region where the intermodulation
product has a slope o f three. This gives an output referred IP3 (OIP3) o f 17dBm.
Although this is not very good it is characteristic o f class B or AB amplifiers. Over a
very wide range o f powers, the intermodulation power IM3 is more than 30dB below
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164
the fundamental power. The circuit is, therefore, expected to be linear enough for use
in wireless co m m unication circuits.
20
10
0
-•-Fundamental
m
■a
•10
Intermodulation
Product
■30
-40
-15
-10
-5
0
5
10
15
Fundamental Input Power (dBm)
20
Figure 6-16. Two tone linearity measurement. Fundamental and
third order intermodulation power versus fundamental input
power.
The amplifier was tested with a code division multiple access (CDMA)
modulated digital signal. The IS-95 specifications for CDMA signals require power
amplifiers to be very linear. The signal channel is 1.2MHz wide. Instead o f creating a
signal frequency next to two input tones, nonlinearities in a CDMA system will
generate a spectrum o f signals next to the channel o f interest.
This is known as
spectral regrowth. A very linear CDMA output is shown in Figure 6-17 with an
output power o f —10.4dBm. As the output power is increased, the spectral regrowth
causes the noise floor to increase next to the channel o f interest, as shown in Figure
6-18 with an output power o f 19.7dBm. This spectral regrowth is too close to the
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165
signal o f interest to be filtered out, causing problems for the adjacent communication
channel.
-20
- 3 0 ------40 03
-50
3 -60
-70
-80
-90
997
998
999
1000
1001
1002
1003
Frequency (MHz)
Figure 6-17. CDMA output signal from SOS NMOS power
amplifier. Output power is —10.4dBm.
o -—
m
-10
<D
§
-20
•3
-30 -
*o
Q.
O
-
-40 -50
997
998
999
1000
1001
1002
1003
Frequency (MHz)
Figure 6-18. CDMA output signal from SOS NMOS power
amplifier showing spectral regrowth. Output power is 19.7dBm.
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166
The IS-95 specification for power in the adjacent channel is specified as a ratio
o f power in the 1.2MHz wide channel to the power in a 30kHz band at an 885kHz
offset from the center o f the channel. . This ratio is known as the adjacent channel
power ratio (ACPR). The ACPR ratio is effectively equivalent to specifying that the
power in a 30kHz band at an 885kHz offset must be at least 26dB lower than the
power in a 30kHz band in the center o f the channel. The SOS amplifier meets the IS95 specification for ACPR up to an output power o f 20dBm, as shown in Figure 6-19.
-1 0
-15 _
O
CD
S
-20
Power at 885kHz Offset
- - IS-95 Specification
-
-25 -
N
- -30 in
co
co
_co
-35 -
a:
o_ -40 o
-45 -50
-55
-10
•5
0
5
10
Output Power (dBm)
15
20
25
Figure 6-19. Measured ACPR. SOS amplifier meets the IS-95
specification up to an output power o f 20dBm.
Figure 6-20 shows the output power and PAE versus CDMA input power. At
an output power o f 20dBm, the maximum power meeting the linearity specifications,
the amplifier has a PAE o f 28.2%. The amplifier achieves a maximum PAE o f 31.3%
at an output power o f 23dBm.
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167
20
E
m
-o
10
- —
CL
Q.
3
o
0
0
-1 0
-20
10
0
-1 0
%
20
CDMA Input Power (dBm)
Figure 6-20. Output power and PAE versus CDMA input power.
6.6 Discussion
The measured output power and drain efficiency at the ldB compression point
were 21.5dBm and 35% respectively. Assuming the load line could not go into the
linear region, a simple load line analysis shows that a 1.250hm load will give a
m ayim nm output power o f 21.8dBm and a drain efficiency o f 31.3%. This is in good
agreement with measured results.
The amplifier was also simulated in Agilent-EEsoPs ADS simulator.
As
shown in chapter 5, the gain of a large periphery transistor at 1GHz is not severely
degraded from the gain o f a small transistor.
Therefore, the large signal model
(BSIM3v3) for a small gate width device provided by Peregrine Semiconductor was
ideally scaled up to 4.012mm of gate width and used in the ADS simulations.
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168
Although no layout parasitics were included, the parasitics o f the package, bondwires,
and circuit board were included in the simulation.
Figure 6-21, Figure 6-22, and Figure 6-23 compare the measured results with
the ADS simulations without layout parasitics for the gain, drain efficiency, and PAE
respectively. The simulated gain at low input power is 0.73dB higher. This m ay be
due to small differences between the measured and simulated reflection coefficients or
some inaccuracies o f the circuit board model. The low input powers, the amplifier
draws very little DC power, thus self-heating can not be the cause o f the lower gain at
low input powers. The simulated drain efficiency and PAE are in excellent agreement
up to input powers o f 12dBm (corresponding to an output power o f 19dBm for the
measured amplifier). The difference between measured and simulated drain efficiency
and PAE versus input power is offset by the difference in measured and simulated
gain versus input power. The drain efficiency and PAE at the ldB compression points
are in very good agreement. Table 6.2 shows a summary o f the measured results,
results from ADS simulations, and results calculated from load line analysis.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
25
15
E
CD
•P.
5
CD
L_
<D
s
o
OL
3CL
•5
CO
O
-15
-2 5
-35
-4 0
-30
-20
-10
20
10
0
Input Power (dBm)
Figure 6-21. Simulated (lines) and measured (symbols) gain and
output power versus input power.
60%
50%
g.
c
8
cz
40% -
3o%-
E
Q
20% -
10 %
-
0%
-40
-30
-20
-10
0
10
20
Input Power (dBm)
Figure 6-22. Simulated (line) and measured (symbols) drain
efficiency versus input power.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
170
40%
UJ
2:
30 % -
jG
O
m
■IDo
T3
■a
20%
<
§
o
10 %
CL
0%
-40
-30
-20
-10
0
10
20
Input Power (dBm)
Figure 6-23. Simulated (line) and measured (symbols) PAE versus
input power.
Table 6-2. Comparison o f measured and simulated performance.
Gain
Pout (ldB compression)
Drain Efficiency (ldB
compression)
PAE (ldB compression)
Drain Efficiency with 19.25dBm
input power
Measured
Simulated
(1.25 Ohm
load)
7.88dB
21.5dBm
35.0%
.6 dB
21.2dBm
35.0%
27.8%
47.0%
28.8%
50.4%
8
Load Line
Analysis
(1.25 Ohm
load)
—
21.8dBm
31.4%
—
—
Table 6-3 compares the results achieved with the SOS power amplifier
presented here to results attained in other technologies. All other amplifiers shown in
the table have higher PAE. However, class D and E amplifiers sacrifice linearity in
order to achieve high efficiency. Some o f the amplifiers were designed for GSM or
other standards, which have greatly reduced linearity requirements than CDMA
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171
systems. The italicized entries with an asterisk identify the power amplifiers that meet
CDMA or the more stringent W-CDMA linearity requirements.
Table 6-3. Comparison of different technologies for power
amplifiers.
denotes amplifiers for linear modulation schemes
such as CDMA and W-CDMA.
Frequency
(MHz)
830
885
Pout
(dBm)
30
15
PAE
(% )
42
60.5
D
B
2 0
1730
1980
1900
8200
1950
900
30.4
30
23.5
39.9
27
23
45
41
35
44
42
49
AB
E
AB
AB
AB
E
3.5-4
1000
20
28.2
B
Breakdown
(V)
Technology
0.8pm CMOS T51
*0.8pm CMOS
(complementary pushpull)[6]
0.35pm CMOS \7]
0.35pm CMOS f81
*0.35pm CMOS [91
0.5pm GaNHEMT|T01
*InGaP/GaAs H B T f l l J
SOI LDMOS (0.35pm
channel, 3.85pm drift)
[1 2 ]
*This work 0.5pm SOS
NM OS
—
—
—
60-70
14
Class
The push-pull amplifier [6 ] takes advantage o f harmonic cancellation to
achieve high linearity and high efficiency. Most push-pull amplifiers use narrowband
baluns or transformers instead o f complementary devices, since most technologies
lack a good p-type device.
By using complementary devices, an amplifier can
theoretically achieve high efficiency and high linearity without sacrificing bandwidth.
However, as mentioned in section 1.3, SOS technologies have the advantage o f having
higher hole mobility, resulting in higher performance PMOS devices than other
technologies.
complementary
With a higher performance PMOS device and more balanced
devices,
SOS
should
provide
superior
performance
complementary push-pull amplifier.
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in
a
172
The 8.2GHz GaN HEMT amplifier [10] used devices with an on-resistance o f
30hm -mm . This is 67% higher than the on-resistance o f the SOS devices. However,
because the breakdown voltage was so large, 60-70V, a high efficiency could still be
attained. Due to the large breakdown field o f GaN, this material is being studied for
power amplifier applications.
Although GaN is an excellent material for power
amplifiers, it has not yet achieved cost, yield, or integration levels suitable to compete
with CMOS or GaAs commercial applications at lower frequencies and output powers.
It is also w orth noting that while the SOS power amplifier has a power density o f only
31.4mW/mm, the GaN amplifier has a power density o f 9.1 W/mm for small devices,
and 4.9W /mm for large devices (2mm gate width). The low power density o f the SOS
amplifier is primarily due to the low breakdown voltage. Devices with an asymmetric
doping, having a lightly doped region on the drain side (LDD region), have higher
breakdown voltage. A device has been demonstrated in SOS to improve the device
breakdown voltage to 13V [13]. This would greatly improve the efficiency and power
density o f SOS MOSFET amplifiers. It would also make load line matching much
easier.
One o f the bulk CMOS amplifiers reported in Table 6.3 was biased as a class
AB and characterized for CDMA [9].
The amplifier meets the stringent linearity
requirements up to an output power o f 23.5dBm with a PAE o f 35% at 1900MHz.
The output pow er and maximum efficiency are higher than those for the SOS power
amplifier at a higher frequency, but the performance advantage is not overwhelming.
With improvements in microwave gain (through better output matching), on-
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173
resistance, or breakdown voltage, it would be possible for the SOS amplifier to
achieve similar or better results.
The performance o f the SOS NMOS amplifier presented in this chapter is
lower than those published in the literature. However, it has been demonstrated that
SOS technology can be used for power amplifiers for wireless com m unications.
Furthermore, improvements in the breakdown voltage o f the devices, as shown in [13]
will greatly improve the efficiency and power density o f SOS devices.
6.7 Conclusions for Chapter 6
An SOS power amplifier was demonstrated at a frequency o f 1GHz. The
amplifier’s efficiency and output power are not better than published works, due to the
low breakdown voltage and higher on-resistance o f the SOS CMOS devices. The
amplifier’s characteristics would greatly improved if the breakdown voltage were
increased by an LDD region.
Simulations using ADS are in good agreement with measured results. As
predicted in chapter 5, due to the operating frequency o f 1GHz, m ost o f the effects of
the layout parasitic could be ignored for rough simulations.
In order to refine the
simulations and attain a more accurate prediction o f the gain and PAE, a more detailed
model would be needed. A detailed model would also be needed if the operating
frequency o f the circuit were above 2GHz, or if the bandwidth o f the circuit was large.
The amplifier did not show signs o f poor performance due to self-heating
effects.
The ADS simulations did not take into account self-heating, but yet the
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174
predictions o f the simulations were in good agreement- As shown in chapter 4, the
thermal resistance o f the sapphire substrate is not a problem for power applications.
6.8
References
1.
Q. Huang, F. Piazza, P. Orsatti, T. Ohguro, “The impact o f scaling down to
deep submicron on CMOS RF circuits”, IEEE Journal o f Solid-State Circuits,
vol. 33, no. 7, pp. 1023-1036, July 1998.
2.
P. Orsatti, F. Piazza, Q. Huang, “A 20-mA-receive, 55-mA-transmit, single­
chip GSM transceiver in 0.25pm CMOS”, IEEE Journal o f Solid-State
Circuits, vol. 34, no. 12, pp. 1869-1880, December 1999.
3.
S.P. Sinha, F.L. Duan, D.E. Ioannou, W.C. Jenkins, H.L. Hughes, ‘Tim e
dependence power laws o f hot carrier degradation in SOI MOSFETS”, 1996
IEEE International SO I Conference Proceedings, pp. 18-19, 1996.
4.
S.H. Renn, E. Rauly, J.-L. Pelloie, F. Balestra, “Hot-carrier effects and. lifetime
prediction in off-state operation of deep submicron SOI N-MOSFETs”, IEEE
Transactions on Electron Devices, vol.45, no.5, pp.1140-1146, M ay 1998.
5.
D. Su, W. McFarland, “A 2.5V, 1-W monolithic CMOS RF power amplifier”,
IEEE 1997 Custom Integrated Circuits Conference, pp. 189-192, 1997.
.
M. Yokoyama, T. Saito, Y. Tachibana, A. Morimoto, K. Masu, K. Tsubouchi,
“A high-efficiency CMOS class-B push-pull power amplifier for codedivision-multiple-access cellular system”, Japanese Journal o f Applied
Physics, Part 1, vol. 39, no. 4B, pp. 2463-2467, April, 2000.
7.
C. Fallesen, P. Asbeck, “A 1W 0.35pm CMOS power amplifier for GSM-1800
with 45% PAE”, 2001 IEEE International Solid-State Circuits Conference,
February 2001.
.
K.-C. Tsai, P.R. Gray, “A 1.9GHz 1-W CMOS class-E power amplifier for
wireless communications”, IEEE Journal o f Solid-State Circuits, vol. 34, no. 7,
pp. 962-970, July, 1999.
9.
A. Giry, J-M. Fournier, M. Pons, “A 1.9GHz low voltage CMOS power
amplifier for medium power RF applications”, 2000 IEEE Radio Frequency
Integrated Circuits Symposium, pp. 121-124, 2000.
6
8
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175
10.
Y.-F. Wu, D. Kapolnek, J. Ibbetson, N.-Q. Zhang, P. Parikh, B.P. Keller, U.K.
Mishra, “High Al-content AlGaN/GaN HEMTs on SiC substrates with very
high power performance”, IEEE 1999 International Electron Devices Meeting,
pp. 925-927,1999.
11.
T. Iwai, K. Kobayashi, Y. Nakasha, T. Miyashita, S. Ohara, K. Joshin, “42%
high efficiency two-stage HBT power amplifier MMIC for W-CDMA cellular
phone system”, 2000 IEEE International M icrowave Symposium, pp. 869-872,
June 2000.
12.
M. Kumar, Y. Tan, J. Sin, L. Shi, J. Lau, “A 900MHz SOI fully-integrated RF
power amplifier for wireless transceivers”, 2000 IE EE International SolidState Circuits Conference, pp. 382-383, 2000.
13.
R.A. Johnson, S.D. Kasa, P.R. de la Houssaye, G.A. Garcia, I. Lagnado, and
P.M. Asbeck, "Novel polysilicon sidewall gate silicon-on-sapphire MOSFET
for power amplifier applications," 1997 IEEE International SO I Conference,
Fish Camp, California, Oct. 1997.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
7 Conclusions and Future Work
7.1 Summary o f Dissertation
Wireless circuit applications are moving toward integration o f all the
transceiver components on a signal chip.
This gives advantages o f reduced
manufacturing costs, reduced power consumption, and higher system performance.
The main roadblock to a complete system-on-a-chip implementation for SOS
technology is the power amplifier. The low breakdown voltage o f CMOS and SOS
technologies makes implementation o f the power amplifier difficult due to the large
periphery transistors that are needed and due to the low impedance load line necessary
to deliver high power.
In order to demonstrate the inherent speed o f scaled CMOS technology for use
in high-speed digital applications, a 2 to 1 digital frequency divider was designed and
tested using a 0.1pm scaled CMOS technology. The frequency divider operated up to
a clock frequency o f 26.5GHz, the fastest digital CMOS circuit reported to date in the
literature. The same circuit fabricated in SOS was estimated to have operated with
clock frequencies in excess o f 30GHz, which would break the barrier for MOSFET
technologies in the millimeter wave regime.
The 0.1pm scaled CMOS devices would not be suited for power applications
due to excessively low breakdown voltages. However, even 0.35-0.5pm gate length
CMOS devices have relatively low breakdown voltages without a lightly doped drain
176
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177
(LDD). In order to attain high output power, it is therefore necessary to scale the gate
width o f the device to provide high current.
The microwave performance o f the large periphery transistors is degraded by
the layout parasitics. Different layout strategies were implemented and tested in an
effort to improve the microwave performance and better understand the effects o f the
layout parasitics. Neglecting the coupling between the interconnects, lumped circuit
elements were used to describe the series resistance, inductance, and crossover
capacitance o f the interconnects.
These lumped element circuit models predicted
much o f the microwave behavior o f the large transistors. To more accurately predict
the microwave characteristics o f the large transistors, a distributed model taking into
account series and shunt parasitics as well as inductive and capacitive coupling
between the lines was developed. This model was shown to very accurately predict
the characteristics o f transistors from a gate width o f 120pm to 2.16mm up to 26GHz.
A layout with many inputs and outputs reduces the mean distance between the active
area o f the device and the input and output points. This type o f layout was shown to
overcome many o f the performance problems o f large periphery transistors.
The lower thermal conductivity o f the sapphire substrate compared to bulk
silicon initially suggested that self-heating may play a m ajor roll in high power SOS
transistors. The thermal resistance o f SOS MOSFETs was studied as a function of the
layout style and gate width o f the transistor. From both thermal simulations and
thermal measurements, it was determined the thermal resistance o f the large devices
was not high enough to cause significant performance degradation.
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178
Finally, a hybrid 1GHz power amplifier was demonstrated using SOS
technology.
transistor.
The amplifier was implemented using a 0.5pm x 4.012mm NMOS
It was shown that simulations could be easily done with reasonable
accuracy at this frequency without modeling the effects o f the layout parasitics, which
affect the microwave performance at higher frequencies. The amplifier, operated in
class B, provides linear output signal and meets CDMA linearity requirements up to
an output power o f 20dBm (100mW). This is an adequate power level for many shortrange wireless applications. The drain efficiency at 20dBm output power was only
31%, while the PAE was only 25%. This does not compare favorably with other
technologies. However, both the maximum output power and the efficiency can be
greatly improved through improvement o f the breakdown voltage.
7.2 Future Work
Although the large transistor small signal behavior has been accurately
modeled and a 1GHz SOS power amplifier has been demonstrated, more work must
still be completed before SOS power amplifiers can become commonplace.
The poor efficiency o f the amplifier highlights areas for improvement for
power applications.
The most important improvement needed is the increase in
breakdown voltage through use o f an LDD region..
This will allow for higher
efficiency, higher power density, higher output load impedance, and longer life o f the
power amplifier. If the on-resistance and threshold voltage remain the same, a simple
load line analysis shows a device with 7V breakdown biased at 3.5V with a 5 Ohm
load line will have a maximum output power o f 25dBm (320mW) and a drain
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179
efficiency o f 50%. I f the gate width is increased to 9mm, the output power would
increase to 28.6ldBm (725mW) with an efficiency o f 53.8%. This would meet the
maximum output power requirements specified for CDMA systems. Alternatively, if
the breakdown voltage could be increased to 10V and the bias voltage increased to 5V,
a 4mm wide device with a 5 Ohm output load line would give 28.63dBm (730mW)
maximum output power with a drain efficiency o f 55.1%. This is a large improvement
over the prediction of 21.6dBm with 33% drain efficiency for the current devices.
As mentioned in section 1.3, thin film FETs such as SOS MOSFETs suffer
from a kink effect. This causes a lower breakdown voltage in SOS MOSFETs than in
bulk silicon MOSFETs. However, the carrier multiplication needed to cause the kink
effect has a time constant associated with it. On an RF time scale, it m ay be possible
to apply higher biases on the device without causing breakdown. Therefore, slightly
higher power and efficiency may be able to be squeezed out o f the device performance
without detrimental effects to the device. This effect remains to be studied.
Before SOS power amplifiers can be used in commercial products, a deeper
investigation o f device lifetime and hot-carrier injection must be undertaken.
Although many low power digital circuits have been demonstrated in SOS, low power
circuits do not place as much stress on the device as a power amplifier. It is therefore
important to understand how the devices degrade under high power RF excitation.
W ith a higher breakdown voltage and better understanding o f the breakdown
mechanisms, a 1 Watt power amplifier should be demonstrated at 1.9GHz.
The
amplifier should take advantage o f the good complementary devices offered by the
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180
SOS technology. This will make it possible to have a broadband, high power, high
efficiency, SOS amplifier with high linearity. After the successful demonstration o f a
1 Watt SOS power amplifier, studies need to be undertaken to integrate the amplifier
into a system-on-a-chip solution for wireless communications. To achieve the highest
efficiency, the common practice o f using off-chip output matching components should
still be used.
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A. Distributed Calculation of Large FET Small Signal
Param eters
A 1 Introduction
This appendix describes in detail the mathematical method used to solve for
the distributed large FET behavior. Mathematica was used to solve the equations. At
the end o f this appendix are the model parameters used to fit the data given in chapter
5. This type o f analysis has been used to model the small signal behavior o f PHEMTs
and MESFETs up to frequencies of 100GHz if skin effect is taken into account [1, 2].
The work in this thesis is different from [1, 2] in that the transmission line is not taken
to be along the gate finger, but rather along the gate, drain, and source interconnect
lines.
A.2 Definition of V ariables
Because o f the large number o f parameters in the equations, it is necessary to
start with the definition o f all the parameters for reference. The parameters to be used
in the equations are defined in Table A -l.
181
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182
Table A -l. Description of variables and parameters used in
distributed solution.
Parameter
Rg
Rd
Rs
Lg
Ld
Ls
Cgd
Cds
Cgs
Y l l , Y12,
Y21, Y22
Mgs
Mgd
Mds
CO
Description
Distributed resistance on gate feed
Distributed resistance on drain feed
Distributed resistance on source feed
Distributed inductance on gate feed
Distributed inductance on drain feed
Distributed inductance on source feed
Distributed capacitance between gate and
drain feeds
Distributed capacitance between drain and
source feeds
Distributed capactiance between gate and
source feeds
Distributed y-parameters o f a unit cell
MOSFET without effects o f parasitics
Mutual inductance between gate and source
feeds
Mutual inductance between gate and drain
feeds
Mutual inductance between drain and source
feeds
Angular frequency
Units
Q/length
Q/length
Q/length
H/length
H/length
H/length
F/length
F/length
F/length
1/(Q
length)
H/length
H/length
H/length
Radians/s
In addition, three simple equations are used to make the setup o f the initial
equations simpler:
Zg = Rg + joiLg
Zd =Rd + jo)Ld
Zs —Rs + jcoLs
(A.I.)
The resistance o f the lines (Rg, Rd and Rs) are taken to be frequency
dependent, given by
R g = Rgo ■Cosh(Rse ■f )
R d = Rdo • Cosh{Rse ■f )
Rs = Rso • Cosh(Rse •f )
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(A.2.)
183
where Rg0, Rdo, and Rs0 are the DC resistances o f the gate, drain, and source feeding
structures resectively. Rse is a factor that determines the frequency that the skin effect
begins to become noticable.
A.3 C oupled T ransm ission Line A nalysis
In this analysis, the coupled transmission lines are the passive feeding
structures. It is assumed the active area o f the device acts as a traditional small signal
FET, as described by the circuit in Figure A -l. A circuit diagram o f the transmission
line modeling is shown in Figure A-2.
The transmission lines are made o f up the distributed self-inductance,
resistance, and capacitance.
The lines are coupled through mutual inductances,
capacitance between the lines, and the y-parameters o f a traditional small signal FET
without interconnect parasitics (depicted in the figure with a box labeled Y).
itit
Figure A -l. Small signal model of FET without effects from
interconnects.
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184
7
Ld
Mgd Mds Rd
® — iQvft— m — va——
Lg
®
Ls
Mad
Ld
Mgd Mds Rd
• --------------------iQQffi— tCWi——iCffl— Vh-----1 j
Mgs Rg
M l— W — V A Mds
>■.....
Mgs
-visa— vffl—
Rs
Lg
-« — — f — j-----------------------®
I
\
ij \ M
7T
L -r1
Mgd
--------- «
Ls
'
Mds
Mgs
Rg
T
— f f i r — VA---- • — — .
*
Mgs
Rs
i\ i \ l[7i
>-4-*
\ • \ —•-----------® ® —l®—VA--- * ^• \
Cgs
Cds
Cgs
•—
Cds
Figure A-2 Two units o f the distributed model. The box labeled Y
is the active FET model without any parasitics.
This model has considerable generality. However, one implicit assumption is
that the mutual inductive coupling between the different lines can be described in
terms o f currents and voltages at a particular position along the line. This would not
necessarily be the case if there were loops in the current paths. Layouts that have
bends to reduce the area, such as in the standard, waffle and spaceship layouts
presented in chapter 3, may have inductive and capacitive coupling between different
positions along the transmission line. From the layout presented in chapter 3, the
waffle layout is expected to have the largest coupling between different positions due
to complex signal path. Layout were the signal propagates in a linear fashion from the
input to the output can be represented very well by the model presented here.
The input signal is normally specified as an applied voltage at one end o f the
transmission line. The voltage at the opposite end o f the transm ission line is not
known, but the current must drop to zero when the transmission line ends in an open
circuit. This makes it easier to specify the boundary conditions in terms o f currents.
With the boundary conditions specified in terms o f current rather than voltage, it is
easiest to solve for the z-parameters. The s-, h-, or y-parameters can then eaisly be
obtained through simple transformations.
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185
The z-parameter definition is for positive current going into the device under
test. For this reason, postive current flow is defined for the three couple lines for gate
and source current traveling towards the right, and for drain current traveling toards
the left. Now equations can be easily dirived to describe the changes in voltage and
current along the circuit shown in Figure A-2.
Voltage drops as current travels
through the resistance and inductive elements as describe by the following equations
vg'(x) = -Z g ■ig(x) +- jco ■{Mgd ■id(x) - Mgs ■w(x)]
vd'(x) = Zd ■id(x) + jco -{—Mgd •ig(x) —Mds •is(x)]
vs'(x) = —Zs ■is(x) + jco ■{Mds ■id(x) —Mgs • ig-(x)]
(A.3.)
Current is exchanged between the coupled lines as the signal propagates. This
is expressed by the equations:
ig'(x) = -vg s(x) - Y l l —vds(x) - Y l l —jco-Cgd ■[ygs(x) - v<&(x)] —jco ■vgs(x) • Cgs
id ’(x) = vds{pc) • Y22 + vgs(x) •Y l l —jco •Cgd •[vgs(x) —vds(xj\ + jco ■vds(x) • Cds
is(x) = -ig (x ) - id(pc)
(A.4.)
The third equation line in equations A.4 is simply KirchofFs current law. To
simplify the equations, this relationship will later be used to eliminate the explicit
source current dependence. Equation A.3 can be express in terms o f a differential
voltage along the gate and drain lines with respect to the voltage along the source lines
given by
ygs'(x) = —Zg • ig(x) + Zs ■is{x) + jco ■{Mgd •id(x) —Mds •id(x) + Mgs •ig(x) —Mgs ■£s(x)]
vds '(x ) = Zd -id(x) + Zs ■is(x) + jco •{—Mgd •ig(x) + Mgs •ig{x) —Mds •id (x) —Mds •£s(x)]
(A.5.)
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186
Taking the derivative o f equations A.5 yields an equation that is dependent on
the derivatives o f the currents, assuming the parasitic elements are constant with
position. With use o f K irchoffs law to eliminate the explicit dependence on is and
substituting equation A.4 into the derivative o f equation A.5 we obtain
vgs”(x) = a ■vg.s-(x) +
- vds(x)
vds”(x) = 5 • vgs(x ) + y • vds(x)
where
a = 71 1 •(Zg + Zs) - 721 -Zs - a) 2 •Cgd ■(Mds - M gd - 3Mgs) +
'la?' -Cgs-M gs + j { —2a>■M g s• T11—a>Y2 1 • (Mds —M gd —Mgs) +
coCgd - (Zg + 2Zs) + coCgs • (Zg + Zs)}
p = -7 2 2 • Zs + 712 • (Zg + Zs) + a>2 ■Cgd - (Mds -M g d -3 M g s ) +
aP • Cds • (M ds—M gd —Mgs) + j{-a>Y22 ■(M d s—Mgd —Mgs) —
2a>Y\2 •Mgs —coCgd •(Zg —2Zs) —coCds ■Zs}
y = 7 2 2 • (Z d -Z s ) + Y\2-Z s —go1 ■Cgd - (M d s-M g d +M gs) +
j{a>YYl • (Mgd - Mds - Mgs) + aC gd ■(Zd - 2Zs) - eaCds - (Zd - Zs)}
S = 711 •Zs) + 721 - ( Z d - Z s ) + co2 ■Cgd •(M d s-M g d + Mgs) +
co2 Cgs • (M ds—M gd + Mgs) + j{coY\ 1 *(M gd —M ds —Mgs) —
coCgd •(Zd —2Zs) + coCgs • Zs)}
By substituting the equations for a , (3, y, and 5 to obtain the differential
equation given by equation A.6, most o f the complex behavior o f the distributed
system can be abstracted in order to derive a mathematical solution to the differential
equations.
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187
Next the boundary conditions m ust be specified.
Figure A-3 shows a
simpbfied view o f the systems with the boundary conditions noted. W hen solving for
Z n , the boundary conditions are given by
Ig (x = 0 ) = I g
Ig (x = L) = 0
Id (x = 0) = 0
Id (x = L ) = 0
Fgs(x = 0) = Vgs
Vds(x = L) = Vds
(A.7.)
Id
.
V d*
Id
V q*
J
r
0
1
X
X*■L
Figure A-3. Simplified view of transmission line structure with
specified boundary conditions.
The equations in A.6 are solved with the boundary conditions in A.7 using an
eigenvalue solution. The column eigenvectors make up a transformation matrix P that
transforms the couple equations into a vector space where the equations for Vgs(x) and
Vds(x) are independent. A solution o f the form Aere is assumed, where A is a constant
and r is an eigenvalue. The eigenvalues are given by
{ \2
c x + y ± J ( a - r ) 2 +4/3S
(r± Y = ------VV n -------- —
(A. 8.)
W hen the square root o f both sides o f equation A. 8 are plugged into the form
o f the solution, Aere, both a forward and reverse traveling waves are formed. The
equations for Vgs(x) and VdS(x) can then be independently solved, then transformed
back into our original coordinate system. These solutions can then be used to solve
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188
for Z n . Z2 1 , Z 1 2 , and Z 2 2 by substituting the appropriate boundary conditions into
equations A.7. The final z-parameter solutions are given by
r—- tz - j^ M g d P + M d s P - M g s (r l - « ) ) r l
Z„ =
r+Tanh(r+L')
r*~rl
Zg S
Z 21
=
1- ja
z 22
=
=
r2
_ - r +2
r l-r l
JW
gs
3 ~
r+
-g
r_Sinh(r_L)
r—~r+
ZdP
r—Tanh(r^L)
.
M gd P~M dsP
M g d 8+M gsS
Z \2
g d P~M dsP+M gs (r? -a ])
g
1- joo_
Zd .
r+~r
(
M gd P Mgsfi
IfZ
¥Mgs
r+Sinh(r+L)
■Mds
r_Sinh(r_L)
jco M gd S+M gsS
Zd
-a
r+Sinh(r+L)
■Mds
r_
- - Y - ^ - { m gdS+M gs8 + M d s {r l-a § r+ - y - J ^ M g d S + M g s ^ + M ^ ir i-a jj
**d
ZdJ
r+Tanh(r+ L)
r—Tanh(r_L,)
(A-9.)
A.4 P aram eter Values
The values used in equations A.9 to fit the model to the measured data are
given in Table A-2. The y-parameters were derived from the measured data o f a
120pm device. It was assumed that the 120pm device was small enough to estimate
this as not having any distributed parasitic elements. The mutual inductances were
calculated from the coupling coefficient, k, and the inductances o f the two coupled
lines given by
^ L x Ly .
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189
Table A-2. Values used in fitting the equations to measured data.
Parameter
Rg
Rd
Rs
Rse
Lg
Ld
Ls
kgs
kgd
kds
Optimized Value
0.0147 Ohm/pm
1.31e-5 Ohm/pm
2.14e-4 Ohm/pm
0.0116 1/GHz
0.328 pH/pm
0.355 pH/pm
0.00355 pH/pm
0.636
0.636
0.376
A.5 R eferences
1.
S .J. Nash, A. Platzker, W. Struble, “Distributed Small Signal Model for MultiFingered GaAs PHEMT/MESFET Devices”, IEEE Microwave and MillimeterWave Monolithic Symp. Digest, pp. 219-222,1996.
2.
S. Masuda, T. Hilrose, Y. Watanabe, “An Accurate Distributed Small Signal
FET Model for Millimeter-Wave Applications”, IEEE MTT-S Digest, pp. 157160, 1999
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
B. Circuit Board Characterization
B.1 Introduction
The electrical characteristics o f the circuit board material and the SMA
launchers must be modeled before making any hybrid circuits. Accurate models are
needed in order to be able to design microstrip matching or filter elements and to
design 50Q connections. It is also important to characterize specific structures such as
a quarter wavelength shorted stub for later use. Via inductance through the board can
significantly change the length o f microstrip needed in order for the structure to appear
as a shorted quarter wavelength line. In order to have confidence in the fabricated
microstrip structures, many structures were designed and tested before proceeding to
building the actual circuit.
B.2 Circuit B oard C haracteristics
The first goal was to model the necessary substrate parameters for a microstrip
simulation in A gilentEEsofs ADS software. The circuit boards used in this study
were obtained from Evenstar. The boards are FR4 with copper cladding on both sides.
In addition to the copper cladding, a gold flash has been applied to the top side. The
gold flash should enable chips to be wirebonded directly to the circuit board without a
package, however, this ability was not tested.
The first structures produced were simply straight microstrip lines. Lines with
lengths o f 2inches and 4inches were fabricated in addition to lines o f lOOmil width
190
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and 240mil width. W hen these structures were measured, it was found that the SMAto-microstrip launcher had 0.2nH series inductance. Therefore a model o f the SMA
launcher had to be made before proceeding to characterize the circuit board material
itself. A physical transmission line element was used in ADS in series with a 0.2nH
inductor. The parameters used in the physical transmission line model are shown in
Table B -l.
Table B -l. Physical transmission line parameters to model SMA
launcher.
Physical Length
Characteristic Impedance
Effective Dielectric Constant
Attenuation
Dielectric Loss (tanS)
304 Mils
50Q
2.1
0.02dB
0.0202
After modeling the SMA launcher, a structure to cancel out the extra series
inductance could be designed. Extra capacitance (a wider strip o f microstrip line) was
needed to cancel out the series inductance. I f the microstrip line is too wide, it will be
shorted out by the SMA launcher at the edge o f the circuit board. In order to cancel
out the inductance, a single piece o f transmission line would have been too wide,
resulting in a short. To avoid this problem, a three stage matching network was used.
The matching structure is shown in Figure B - l.
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192
SMA
launcher
connects here
50Q Line
140 x 30 mils
240 x 30 mils
80 * 50 “ “ k
Figure B -l. SMA launcher matching structure.
In order to model the circuit board material separately from effects of the SMA
launchers, microstrip lines with open-circuit stubs were fabricated. These structures
will exhibit a resonance, the frequency and bandwidth o f which is determined entirely
by the circuit board material.
In this way, any variations in the launcher
characteristics can be eliminated while modeling the circuit board characteristics.
Measured data comparing the characteristics o f the through line with no stubs to the
microstrip lines with open-circuit stubs is shown in Figure B-2 and Figure B-3. As
can be seen from the Figure B-2 and Figure B-3, the lines with the open-circuit stubs
have completely different characteristics than a through line o f the same conductor
width. In this way, an accurate model of the circuit board material can be extracted
independent o f the connector characteristics.
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193
♦ S i n g le Stub
♦ Double Stub
— Through
-50
0
2
4
6
8
10
Frequency (GHz)
Figure B-2. S l l of 50Q microstrip line with no stubs, with single
open-circuit stub, and with two open-circuit stubs.
o
•5
-10
♦ Single Stub
♦ Double Stub
— Through
CD
T3
-15
-20
-25
-30
0
2
4
6
8
10
Frequency (GHz)
Figure B-3. S21 of 50Q microstrip line with no stubs, with single
open-circuit stub, and with two open-circuit stubs.
Using this data, a microstrip model was made in ADS. The model accurately
predicts the behavior o f the circuit board structures up to about 7GHz. For a 1GHz
circuit, this means the performance o f the microstrip lines and connectors will be
accurately predicted well past the fourth harmonic. This was deemed to be acceptable
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194
for this application. The substrate parameters used in the microstrip model are shown
in Table B-2.
Table B-2. Parameters used in ADS microstrip substrate
definition.
Substrate Height
Relative Dielectric Constant
Permeability
Conductor Conductivity
Conductor Thickness
Dielectric Loss (tanS)
Surface Roughness
60 Mils
4.25
1
5.8e6
0.5 Mils
0.0012
0
It was determined that a 120 mil wide microstrip line provides a relatively
good 50Q transmission line. The measured reflection and transmission o f a 120 mil
line w ith SM A launchers is shown in Figure B-2 and Figure B-3. The 120 m il wide
line provides an SI 1 o f roughly —30dB up to a frequency o f about 6GHz.
B.3 B ias Circuitry
Besides the connectors and 50Q transmission lines, the other m ain structure o f
importance is the quarter wavelength line for DC biasing. It is a well-known fact that
a quarter wavelength shorted line appears to be an open-circuit at the input. This is
due to the fact that the only difference between an open-circuit and a short-circuit is a
180° phase shift. As the signal travels a quarter wavelength down the line and reflects
back a quarter wavelength, the signal shifts by 180°, making a short-circuit appear as
an open-circuit and visa versa.
If the quarter wavelength line is not directly shorted, but rather AC shorted
with a capacitor to ground, the line can be used to provide a DC bias. This is due to
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
195
the fact that at the input to the AC shorted line, the design frequency will see an opencircuit, thus being unaffected by the AC shorted line. In a practical implementation,
the AC signal goes to ground through a capacitor and via to the ground plane. This
means the length o f the transmission line must be adjusted so that any phase shift
through the capacitor and via to ground will still result in a total phase shift o f 90°
between the line input and ground. Rather than making an extensive modeling effort
o f the via inductance and the capacitor characteristics, it is much easier to make a
series o f lines o f slightly different length. From this data, the correct microstrip length
to make a short-circuited quarter wavelength line can be determined.
All structures make use o f the connector matching structure shown in Figure
B -l.
The necessary length o f transmission line was estimated and two different
lengths used as shown in Figure B-4. The structure has a 120 mil wide line (50Q)
from port 1 to port 2. A narrow 25 mil wide line branches off. This line is made
narrow so it will be high impedance even to frequencies where it does not look like a
quarter wavelength. The impedance o f the line is approximately 100Q. Because o f
the length o f a quarter wavelength line at 1GHz (initial calculation o f 1680 mils long),
the line had to follow a serpentine path. A 35 mil gap is at the end o f the line for a
surface mount capacitor.
The grounded pad at the end has 4 parallel vias to the
backside to reduce the via inductance.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
196
120 x 780 mils
iL
25 mils wide
1580, 1680, &
1780 Mils long
35 mil gap
Pad with
4 vias to
ground
Figure B-4. Structures used for determining length of line for a
shorted quarter wavelength line.
The characteristics are compared with the characteristics o f a 50Q through line
in Figure B-5 and Figure B-6. As desired, when the length o f the line is a quarter
wavelength, both the reflection and transmission are similar to that o f a straight 50Q
microstrip line. The initial calculation showed the quarter wavelength line should be
1680 mils long. Three lines were then fabricated and tested with lengths o f 1580 mils,
1680 mils, and 1780 mils. By measuring three lengths a very accurate length for the
quarter wavelength line can be extracted.
The measured s-parameters are shown in Figure B-5 and Figure B-6. From the
sharp dips in the S21 frequency response, it is easy to extract the frequency where the
short circuit stub appears to be a short circuit at the 50Q thru line. This corresponds to
the stub being half a wavelength long. The frequency where S21 has a minimum is
plotted versus stub length in Figure B-7. From Figure B-7, it can be seen that a 1730
mil long short circuit stub is a half wavelength at 2GHz, and therefore will be a quarter
wavelength at 1GHz. Both the 1680 mil and 1780 mil line are close to being correct.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
197
Figure B-5 and Figure B-6 show that at 1GHz these stubs have a sim ilar frequency
response as the 50Q thru line. Therefore a 25 mils by 1730 m il stub can be used for
the bias circuitry in the power amplifier while having m inim al effect on the RF
response o f the amplifier. A photograph o f the test circuit board with the quarter
wavelength bias lines and 50Q through line is shown in Figure B-8.
-10
-o -1 580 Mils
-o -1 680 Mils
-* -1 780 Mils
— Thru line
-30
-40 -
-50
0
1
2
3
4
5
Frequency (GHz)
Figure B-5. S l l of two q u a rte r w avelength test structures
com pared to 50Q through line.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
0
-4
~
-®-1580 Mils
-a-1680 Mils
—•1780 Mils
— Thru line
-8
CM
w _12
-16
-20
0
1
3
2
4
5
Frequency (GHz)
Figure B-6. S21 of two quarter wavelength test structures
compared to 50Q through line.
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X
CD
2.3
©
to
g
to
2.2
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CC
S'
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Z
J
cr
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u_
2.1
-
c
E
c
S
1.9
1550
1600
1650
1700
1750
1800
Length o f short circuit stub (Mils)
Figure B-7. Minimum in S21 frequency response corresponds to
half wavelength. 1730 mils is estimated to be the correct length for
1GHz quarter wavelength.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
199
Figure B-8. Photograph o f test circuit board with quarter
wavelength bias lines and 50Q through structure.
B.4 O utput Circuit for PA
A circuit board consisting o f the output half o f the power amplifier was made
in order to verify the models o f the circuit board material and the surface mount
devices. This structure was also used to test the output matching circuit. A schematic
is shown in Figure B-9 and a picture o f the board is shown in Figure B-10. The board
is the same as the output half o f the PA presented in chapter 6, except without the
toroid and wire connecting to the DC power supply.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
D ra in
V o lta g e
"II—vMUr-^
C4
L5
C2
T IP
r
T6
RF
In p u t
HI
'—
RF
O u tp u t
'
"
T4
R2
Figure B-9. Schematic of PA output circuit without matching
elements.
Figure B-10. Photograph of board used to test output matching
and verify board and surface mount models.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
201
The modeled and measured S l l and S21 are shown in Figure B - ll and Figure
B-12. The data shown is without any stubs for output tuning. Overall the agreement
between the model and data is very good.
180 T
135 * *
90
-10
45
-30
-90 '
-135
-40
0
500
-180 ±
1000
1500
2000
2500
0
3000
500
Frequency (MHz)
1500
2000
Frequency (MHz)
1000
2500
3000
2500
3000
Figure B - ll. Modeled and measured S l l for output half of PA
circuit.
180
135
90
CO
X -10 •
— Model
— Measured
8a>
<o
45
o '
-90
-1 5 -
-135
-20
0
-180
500
1000
1500
Frequency (MHz)
2000
2500
3000
0
500
1500
2000
Frequency (MHz)
1000
Figure B-12. Modeled and measured S21 for output half of PA
circuit.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
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