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Reconfigurable and micromachined microwave structures

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RECONFIGURABLE AND MICROMACHINED MICROWAVE STRUCTURES
by
Michael James Hill
Copyright © Michael James Hill 2001
A Dissertation Submitted to the Faculty o f the
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
In partial Fulfillment o f the Requirements
For the Degree of
DOCTOR OF PHILOSOPHY
In the Graduate College
THE UNIVERSITY OF ARIZONA
2 00 1
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UMI Number: 3010204
Copyright 2001 by
Hill, Michael Jam es
All rights reserved.
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THE UNIVERSITY OF ARIZONA
GRADUATE COLLEGE
As members of the Final Examination Committee, we certify that we have
read the dissertation prepared by Michael J. Hill_______________________
entitled
Reconfigiirahlp and Mi rrnmanhinod M i c m w a v p Shniftnrw________
and recommend that it be accepted as fulfilling the dissertation
requirement for the Degree of
Doctor o f Philosophy
Dan
Dat<
Date
Date
Date
Final approval and acceptance of this dissertation is contingent upon
the candidate's submission of the final copy of the dissertation to the
Graduate College.
I hereby certify that I have read this dissertation prepared under my
direction and recommend that it be accepted as fulfilling the dissertation
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STATEMENT BY AUTHOR
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advanced degree at The University o f Arizona and is deposited in the University Library
to be made available to borrowers under rules o f the Library.
B rief Quotations from this dissertation are allowable without special permission,
provided that accurate acknowledgement o f source is made. Requests for permission for
extended quotation from or reproduction o f this manuscript in whole or in part may be
granted by the copyright holder.
SIGNED:
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4
Table
of
C ontents
L is t
of
F i g u r e s ................................................................................................................................................6
L is t
of
T a b l e s .................................................................................................................................................. 8
A b s t r a c t -------------------------------------------------------------
9
1 I n t r o d u c t i o n ..............................................................................................................................................11
2 T ools
and
T e c h n i q u e s ..........................................................................................................................18
2.1 Simulation to o ls ......................................................................................................18
2.1.1
Crystal Simulations with TRIX 3D.................................................................. 22
2.1.2 Frequency Resolution and The Pade Approximation.....................................24
2.1.3
Cavity Simulations With H F S S ........................................................................27
2.1.4 HFSS Frequency Sweeps...................................................................................28
2.1.5 HFSS Ports.......................................................................................................... 30
2.2 M easurement T echniques ....................................................................................... 31
2.2.1
Free Space EBG Crystal M easurements..........................................................32
2.2.2 Coaxial measurements....................................................................................... 33
2.2.3
On Wafer M easurements...................................................................................34
3 P E G C r y s t a l .............................................................................................................................................. 3 7
3.1 B ackground .............................................................................................................. 37
3.2 Experimental Crystal D esign ............................................................................. 39
3.2.1
Defects................................................................................................................ 40
3.2.2 Simulated and Measured R esults..................................................................... 43
3.2.3
Improved D efect................................................................................................ 49
3.2.4 Pade Simulation Enhancements........................................................................52
3.3 C onclusions from the EBG crystal experiments .......................................... 53
4 T h e P l a n a r E B G C a v i t y R e s o n a t o r .........................................................................................5 5
4.1 T he M icrostrip Coupled Cavity R esonator .....................................................55
4.2 EBG S ide Walls........................................................................................................ 57
4.3 F abrication ............................................................................................................... 61
4.4 Simulation and M easurement ............................................................................. 62
4.4.1
Resonator Q ........................................................................................................64
4.5 Summary of results from the EBG resonator ................................................67
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5
T a b le o f C o n te n ts - Continued.
5 A R e c o n f ig u r a b l e E B G
5.1
5.2
5.3
5.4
c a v i t y r e s o n a t o r .......................................................................... 6 9
Reconfigurable resonator walls ......................................................................69
Resu lts .......................................................................................................................72
Continuing D evelopment ......................................................................................76
Conclusions .............................................................................................................. 78
6 M ic r o s t r ip C o u p l e d C a v i t y D i p l e x e r
6.1
6.2
6.3
6.4
6.5
6.6
on
D u r o id ® ........................................................ 80
Overview ................................................................................................................... 80
Cavity D esign ........................................................................................................... 81
D iplexer D esign ........................................................................................................83
Fabrication ............................................................................................................... 87
Measurements ..........................................................................................................89
Conclusions .............................................................................................................. 91
7 A S il ic o n M ic r o m a c h i n e d D i p l e x e r ......................................................................................... 9 2
7.1
7.2
7.3
7.4
P rogression to Silicon ...........................................................................................92
Silicon D esign and F abrication ..........................................................................92
Results ...................................................................................................................... 97
Conclusions ............................................................................................................ 103
8 C o n c l u s i o n s .............................................................................................................................................. 104
A p p e n d i x A . M i c r o s t a t i o n L e g o C o d e ......................................................................................107
A p p e n d i x B . P a d e A p p r o x im a t io n
in
M a t h e m a t ic a ..........................................................125
A p p e n d i x C . P C B B o a r d F a b r i c a t i o n ........................................................................................ 127
A p p e n d i x D . P l a t e d T h r u - H o l e F a b r i c a t i o n .......................................................................133
A p p e n d i x E . S il i c o n M i c r o m a c h i n i n g
and
L it h o g r a p h y T e c h n i q u e s ............... 137
A p p e n d i x F . H F S S S e t u p I s s u e s ....................................................................................................... 144
R e f e r e n c e s .................................................................................................................................................... 146
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6
L is t
of
F ig u r e s
Figure 2.1. Typical crystal simulation pulse shape............................................................... 23
Figure 2.2. Pulse spectra..........................................................................................................23
Figure 2.3. Simulation and interpolated simulation.............................................................. 27
Figure 2.4. Microstrip ports..................................................................................................... 31
Figure 2.5. Crystal measurement setup.................................................................................. 33
Figure 2.6. CPW to microstrip transition (all dimensions are in microns)........................ 35
Figure 2.7. CPW to microstrip transition data....................................................................... 36
Figure 3.1. Experimental crystal fixture.................................................................................38
Figure 3.2. Close-up o f experimental test fixture..................................................................40
Figure 3.3. Typical defect structures...................................................................................... 42
Figure 3.4. Electronically switchable defect element...........................................................42
Figure 3.5. Crystal transition region....................................................................................... 43
Figure 3.6. Measured crystal transmission, polarization parallel to the defect rod.......... 45
Figure 3.7. Measured crystal transmission, polarization perpendicular to the defect rod.
............................................................................................................................................. 46
Figure 3.8. Simulated crystal transmission, polarization parallel to the defect rod..........47
Figure 3.9. Simulated crystal transmission, polarization perpendicular to the defect rod.
..............................................................................................................................................48
Figure 3.10. Initial and improved defects.............................................................................. 49
Figure 3.11. Simulated insertion loss with the original and improved defects..................51
Figure 3.12. Measured insertion loss o f the improved defect.............................................. 51
Figure 3.13. Application o f the Pade approximation to simulation data........................... 53
Figure 4.1. A microstrip coupled cavity resonator................................................................ 55
Figure 4.2. The microstrip coupled EBG cavity resonator...................................................58
Figure 4.3. EBG Cavity board masks..................................................................................... 61
Figure 4.4. Fields in the EBG cavity...................................................................................... 63
Figure 4.5. EBG Cavity simulated and measured results..................................................... 63
Figure 4.6. Low coupling Q measurement.............................................................................65
Figure 4.7. Q As a function o f printed circuit board thickness............................................67
Figure 5.1. Reconfigurable cavity side wall.......................................................................... 70
Figure 5.2. Switchable via elem en t....................................................................................... 71
Figure 5.3. Cavity fields with switchable elements turned o ff ........................................... 71
Figure 5.4. Simulated results from the reconfigurable EBG resonator.............................. 73
Figure 5.5. Measured results from the reconfigurable EBG resonator............................... 74
Figure 5.6. Switchable element ‘cap’..................................................................................... 75
Figure 5.7. Simulated switch-off response.............................................................................76
Figure 6.1. Simulated cavity response....................................................................................83
Figure 6.2. Diplexer topology..................................................................................................84
Figure 6.3. Duroid diplexer measurement fixture................................................................. 87
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7
L i s t o f F ig u r e s - Continued.
Figure 6.4. Measured and simulated data............................................................................... 89
Figure 6.5. Input match & isolation........................................................................................ 90
Figure 7.1. Diplexer wafer stack..............................................................................................94
Figure 7.2. Anisotropic cavity etch......................................................................................... 94
Figure 7.3. Cavity and feed wafers..........................................................................................96
Figure 7.4. Close up o f the top feed wafer.............................................................................96
Figure 7.5. Cavity Q measurement..........................................................................................98
Figure 7.6. Receive channel data........................................................................................... 100
Figure 7.7. Transmit channel data..........................................................................................100
Figure 7.8. Simulation o f the over-etched diplexer cavities............................................... 101
Figure 7.9. Isolation d a ta........................................................................................................102
Figure 7.10. Summary o f measured data.............................................................................. 102
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8
L is t
TABLE 2-1.
TABLE 3-1.
TABLE 4-1.
TABLE 4-2.
TABLE 5-1.
TABLE 5-2.
TABLE 6-1.
TABLE 6-2.
TABLE 7-1.
of
Tables
Fast sweep simulation sizes..............................................................................30
Crystal dimensions............................................................................................ 40
EBG Cavity filter dimensions..........................................................................60
EBG Cavity resonator results...........................................................................64
Design Parameters............................................................................................ 72
Simulated and measured results.......................................................................73
Diplexer dimensions..........................................................................................88
Measured and simulated values....................................................................... 90
Summary o f the silicon diplexer results........................................................101
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9
A bstract
Recent expansion o f the wireless
infrastructure has led to a dramatic increase in
the use o f consumer wireless devices.
This trend is driving the development o f
reconfigurable, high performance and
inexpensive microwave components.
One
technology that promises to help meetsome o f these demands involves the use o f
periodic structures, also known as electromagnetic band gap (EBG) structures. The use
o f these EBG structures coupled with micromachining fabrication techniques provides
the possibility o f producing inexpensive, small and reconfigurable filters that can be used
for many microwave applications. With this technology, an electronically reconfigurable
EBG crystal has been developed that demonstrates contrast ratios o f more than 30 dB
between configuration states. This device has led to the development o f a microstrip
coupled EBG resonator, and then a reconfigurable microstrip coupled EBG resonator.
Quality factors on the order o f 400 have been demonstrated for these inexpensive and
easy to integrate high performance microwave resonators.
The first step towards the use o f these EBG resonators in a microwave diplexer
has been completed.
A high performance single pole microwave diplexer has been
designed, fabricated and tested using Duroid® circuit board material from Rogers
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10
Corporation- This diplexer exhibits channel bandwidths o f less than 3 % , and was used as
a test structure for subsequent construction on silicon. Using silicon micromachining
techniques the diplexer has been fabricated using silicon wafers. This silicon diplexer
has shown improved performance over the Duroid® device in channel bandwidth
(<1.6%), insertion loss (<1.5 dB), and channel-to-channel isolation (>26dB).
The
development o f each o f these devices, including the simulated and measured results are
be presented along with a discussion o f the development path towards a reconfigurable
EBG diplexer on silicon.
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11
1 In t r o d u c t io n
Recent advances in technology have allowed circuits and electronic devices to
shrink dramatically. With this size reduction comes reduced cost, mass produced devices
that exhibit functionality unheard o f several years ago. Devices like cellular phones,
once considered to be luxury items, are now seen by many as necessities and, because o f
the cost reduction associated with mass production, are so inexpensive they are often
given away with service contracts. This trend has produced consumers that place ever
increasing demands on electronic devices. It is no longer acceptable to have a cellular
phone that is only a phone.
Consumers want a device that is a phone, an internet
connection and a personal data assistant. The device must also operate for days on a
single battery charge.
The microelectronics industry has produced ultra-high speed microprocessors that
operate on very low voltages and powers.
These processors have provided today’s
electronic devices with the computing power required for many o f the tasks consumers
demand. Typically, these systems are limited in both functionality and battery life by the
wireless link used to connect the devices to the base station. Interference, link length,
increased traffic, and the need for higher data rates place a lower limit on the
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12
transmission power required for a functional device.
Additionally, newer digital
transm ission schemes, that are being used to maximize the bandwidth usage, requdre very
high performance RF and microwave components. These components must bae stable
over temperature and time, small, and inexpensive to manufacture. These are in sd d itio n
to the requirement for efficient power usage.
Because o f the speed o f development o f wireless devices, design cycles arre rapid
and often require components that can be used in several systems. A dditionally, local
regulatory requirements often require these high tech devices to operate oveir vastly
differing frequency regimes. Often this leads to redundant components in the w ireless
link portion o f the circuitry. It has historically been very difficult to produce devLces that
exhibit high performance behavior and can operate in multiple frequency ranges.
An
ever-present industry goal is the single chip transceiver —a fully functional transm itter
and receiver requiring no external parts. Although this may not materialize for som etim e,
the message is clear.
Devices are needed that can be electronically reconfigured to
operate in different frequency ranges. Moreover, at the same time they must not sacrifice
performance for reconfigurablility.
Although the most visible need for high performance reconfigurable devices is the
consumer wireless market, other not so visible applications share these requirem ents (e.g.
satellite communication systems). Most, if not all, of the consumer wireless devices have
a receiving base-station that connects the wireless device to the wired infrastructure.
With more demand, the number o f required base stations is on the rise. O ften , these
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13
base-stations share many o f the RF requirements o f the mobile devices in terms o f
performance. Applications such as satellite phones with world-wide service require even
more from the base station electronics, particularly with respect to size and weight. The
list o f applications is enormous and continues to grow: automotive radar, remote sensing,
and electronic countermeasures to name a few.
To meet these requirements research has focused on promising technologies, as
well as enhancing existing ones.
Two areas o f research that have received attention
recently are the use o f micromachining techniques to produce micro-electromechanical
system (MEMS) microwave devices, and photonic bandgap (EBG) structures adapted to
the microwave regime.
MEMS devices allow the opportunity to produce very small
microwave structures that were once considered ‘unshrinkable’.
A n example is the
microwave MEMS switch. Low loss, high isolation microwave frequency switches have
historically required large, waveguide style components.
Integrated devices suffered
from high loss and low isolation that made them unusable for many circuits. Using
MEMS technology, electrically actuated mechanical microwave switches have been
constructed that exhibit both low loss and high isolation [1]. Additionally, because the
construction methods used to produce these devices are based on semiconductor
fabrication techniques, the devices are well suited to mass production. Other devices
such as the micromachined cavity resonator have produced planar, easy to integrate
circuits with exceptional performance characteristics [2].
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14
Like MEMS devices, photonic bandgap structures were originally developed for
applications outside of the microwave regime. Photonic bandgap structures have been
used for some time in the optical community and have resulted in high performance
optical devices, including ultra-low dispersion PBG optical fibers [3]. These bandgap
devices, which consist o f a periodic arrangement o f metallic or dielectric elements that
alter the allowed modes o f electromagnetic propagation, have been adapted to microwave
frequencies [4]. With this technology high quality factor microwave filters have been
demonstrated [4].
The combination o f MEMS fabrication technology with photonic bandgap
structures adapted to the microwave regime (electromagnetic bandgap or EBG) promises
to provide new, high performance reconfigurable devices.
It is the investigation and
development o f devices utilizing these technologies that is the focus of this dissertation.
Specifically, this dissertation will discuss the development o f several new types o f
microwave devices. These devices include an electronically switched defect EBG crystal
that demonstrates the feasibility o f electronically reconfiguring EBG devices, a novel
high-Q planar reconfigurable EBG resonator that can be easily implemented using
standard processes, and a high performance, compact, narrow band micromachined
silicon diplexer.
Each o f these devices is a step along the path towards a useful
reconfigurable high performance silicon diplexer, and knowledge gained in the
development o f each device was useful to the design o f subsequent devices. For this
reason, after discussing simulation and measurement techniques used throughout, this
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15
dissertation will discuss the development o f each device as it builds on previous
experience.
First the development o f a prototype metallic EBG crystal will be discussed. This
device, unlike previous EBG crystals, utilizes p-i-n diodes as defects in the crystal
structure. This allows electronic switching o f the defects in the crystal and thus allows
electronic control of the passband behavior o f the crystal. Although this prototype device
has limited use, it demonstrates the feasibility o f electronically controlled defects in EBG
crystals.
Using the knowledge gained from the EBG controlled defect crystal, a more
useful EBG structure was developed. This structure, a microstrip coupled EBG resonator
(MCER) provides several important features: a high-Q response, easy integration with
planar circuits, and fabrication using standard processes. Following successful testing of
the MCER, the defect concept o f the EBG crystal was implemented in the MCER
structure. By placing controllable elements in the bandgap structure o f the MCER, a
reconfigurable resonator was developed.
In addition to the features o f the original
MCER, this resonator has the added benefit o f reconfigurability.
Planar micromachined cavity resonators have been shown to provide high-Q
responses[2]. Because o f similarities with the MCER, circuits constructed with these
cavity resonators are a natural starting point for the development o f M CER filters and
devices.
To this end, a single-pole diplexer that utilizes fully conducting side wall
(FCSW) micromachined cavity resonators was developed.
Initially constructed on
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16
Duroid®, the operation o f the diplexer was verified before micromachining techniques
were used to construct the microwave circuit on a silicon wafer.
The microwave circuits and the simulation and experimental techniques
developed for this dissertation are essential steps toward a long-term goal o f developing a
micromachined reconfigurable EBG diplexer on silicon. This diplexer will utilize all of
the techniques discussed in this dissertation and will demonstrate the applicability o f this
technology to the development o f advanced microwave components. Although the work
presented here has proven the usefulness o f these technologies, it has only scratched the
surface in terms o f the types o f devices that could be created with these technologies and
o f the impact these technologies will have on future microwave devices.
In order to discuss each o f these components in depth, it is first necessary to
discuss some o f the design tools and measurement techniques used to develop these
devices. In many cases, there is overlap in the design and measurement tools used for
each device. This is expected as many o f the tools and techniques are common to several
microwave engineering application areas.
customization for each particular circuit.
Often these techniques require some
This is the case with many o f the devices
developed in this dissertation. The next chapter will address these issues and will focus
on the tools and measurement techniques used in creating these microwave circuits.
Then, in chapter 3, the development o f the controlled defect EBG crystal will be
discussed.
Experimental results will be presented that conclusively demonstrate the
ability to create controlled defects in EBG crystals. Chapter 4 will introduce the EBG
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17
microstrip coupled resonator, a useful and easy to fabricate microwave device based on
the EBG concept.
In Chapter 5, this device is implemented in a reconfigurable
configuration using techniques learned from the initial controlled defect EBG crystal,
thus providing a complete reconfigurable resonator that can be used as a building block
for future designs.
With this stage complete, we will then step back and focus on a
component that could utilize this type of resonator —a frequency selective single-pole
diplexer.
The initial diplexer, a fixed FCSW cavity based diplexer fabricated with Duroid®
will be presented in chapter 6. Chapter 7 then addresses the conversion o f this diplexer to
a silicon based implementation. Finally chapter 8 will focus on possible future directions
for this research including the implementation of EBG cavities in place of the FCSW
cavities in the silicon diplexer. Ultimately this work will lead to the use o f reconfigurable
EBG cavities in the silicon diplexer, thus providing an integrated solution for some o f the
multi-band design problems.
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18
2 Tools
2 .1
S im u l a t io n
and
T e c h n iq u e s
tools
The complicated two and three-dimensional structures used in many o f today’s
microwave circuits do not lend themselves to simple analysis methods. Because o f this,
many types o f simulation tools have been developed and are used for simulating and
analyzing complicated microwave structures.
Some of these tools, like Agilent's
Advanced Design System (ADS), use lumped element models to simulate common
microwave structures. Typically these tools can only be used for pre-modeled elements
in a design (like a microstrip bend) that are not coupling significantly to other devices.
This is a serious limitation for the design o f new structures.
To circumvent this problem, other more complete numerical methods have been
developed for modeling electromagnetic interactions with full three-dimensional
structures. Two popular simulation techniques used today are the finite difference time
domain (FDTD) method, and the finite element method (FEM) [5]. Each technique has
its own advantages and disadvantages. Typically, FDTD simulation involves discretizing
the problem to be simulated into blocks o f uniform size. A time-domain simulation is
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19
executed on this discretized space, and Fourier transforms are used to extract frequency
domain data from the time domain simulation results. The FEM method also involves
discretizing the problem to be simulated; however, the discretization does not have to use
uniform shapes. This allows objects without convenient common-multiple dimensions to
be simulated. Unlike the FDTD method in which frequency data can be extracted from a
single simulation, the FEM simulator must solve the problem at every frequency o f
interest. Additionally, because the discretization is dense at high field locations, objects
with many edges and comers typically result in a large number o f mesh objects (usually
tetrahedra).
Two simulation tools were used to simulate structures in this dissertation. One
tool, TRDC 3D, developed at the University o f Arizona by D. Witter and R.W.
Ziolkowski [6], is based on the FDTD method. This tool was used for the simulations o f
the electromagnetic bandgap crystal. Because the geometry o f the crystal was easy to
discretize into uniform blocks, it was ideally suited for simulation with the FDTD
method. Additionally, it was desirable to simulate the actual crystal structure, not simply
one unit cell o f the crystal that would result in a simulation o f an infinitely large crystal.
If a method such as the FEM were used to model a finite crystal whose size was as large
as the one presented here, it would have resulted in a simulation requiring an extremely
large mesh and would not have been solvable on today’s personal workstations.
The other tool used for the electromagnetic simulations o f the microwave
structures developed in this dissertation was Ansoft's High Frequency Structure
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20
Simulator (HFSS) version 7. The HFSS simulator uses the FEM method and was used to
simulate the FCSW microstrip coupled resonators, the diplexers, and the EBG resonators.
Because o f HFSS’s ability to accurately mesh irregularly shaped objects, it is very useful
for intermediate designs where dimensions may change drastically in each design
iteration. HFSS also has optimization features that can help speed the design process for
devices that have not yet been fully characterized. Unfortunately, these advantages can
also be disadvantages in that the simulations may be larger than necessary for a given
problem, and in many cases could be much larger than they would be using other
methods such as the FDTD method.
Often, structures with repetitive features can be modeled easily using FDTD
methods because they can be easily discretized into uniform blocks. Although the EBG
resonators contain repetitive EBG structures that might lend themselves to FDTD
analysis, the use o f cylindrical vias (which can be fabricated more easily than rectangular
vias) would have made the simulation o f these structures difficult with FDTD. In order
to properly model the curves o f the cylinders and annular rings used in the microwave
circuits, a small grid size would have been necessary. This would have resulted in a very
large simulation given the size differences between the vias and the overall structure.
Additionally, at the onset there was not a good choice for a common-multiple grid size.
Future simulations could be performed on these structures using the FDTD method if the
object dimensions were such that they could be accurately divided into a reasonable
num ber o f uniform blocks.
In this situation the FDTD analysis may prove to be
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21
significantly faster than other methods. One additional difficulty that would have been
encountered i f the TRIX 3D simulator were used involves the setup o f the problem.
Currently the TRIX simulator does not have a user interface that allows for easy
modifications o f the simulation structures. Although this is not an inherent problem with
the FDTD method, it does impact the ease in which microwave circuits can be simulated
with the TRJX 3D tool. In fact, it was found while simulating the crystal structures that it
was very difficult to verify the proper entry o f the simulation structure.
The visual
display routines available with TRIX 3D that are used for viewing the entered structures
were not mature enough to use to ensure the models were entered properly. This is
particularly true with objects like the crystal which have many parts with features that
have both small and large dimensions when compared to the problem space (for example,
the crystal bar element cross section is small compared to the bar length).
To circumvent this problem, a custom application was programmed using
Microstation Modeler’s macro language.
Microstation Modeler is a commercially
available 3D drafting package that has full three dimensional visualization capabilities. It
also allows for custom adaptation through the use o f a fully functional macro language.
The software o f Appendix A was implemented on Microstation Modeler version 5.05.
The software allows the geometry definition files used to enter structures into the
TRIX 3D simulator to be read and interpreted by Microstation Modeler. This allows for
visual verification o f structures entered into the TRIX 3D software.
Additionally, it
allows for the verification o f structure dimensions, in both cell units and actual physical
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22
distances. Although this code has significant capabilities, it is still primitive and still
lacks features that would be desired for structures other than EBG crystals.
Further
development o f this software could enable structures to be drawn in the Microstation
environment and then exported to TRIX 3D for rapid creation o f the resulting FDTD
simulation data files.
2.1.1
C r y s t a l S im u l a t io n s
w it h
TR IX 3D
TRIX 3D simulations o f the crystal structure were performed on a 500 M Hz DEC
Alpha computer with 1GB of RAM. This computer allowed crystal simulations to be
performed at a rate o f approximately 93 minutes per time step using a simulation space o f
163 x 163 x 70 (—7720 resolution). Typical crystal simulations were 5000 time steps,
resulting in a 54-hour runtime. The input signal for these simulations typically consisted
o f a 20 GHz sinusoid, windowed with a 1 cycle rise and fall time, with no CW duration
(see figure 2.1). By taking the Fourier transform o f this waveform, the spectra o f the
signal can be found; it is shown in figure 2.2. It is important that the pulse be designed to
cover the frequency range of interest. In this case, the pulse spectrum has a peak at
20 GHz and covers the 2 —38 GHz range, which completely encompasses the range o f
interest for the crystal.
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23
Typical pulse shape
1.0
at
T3
S
0.5
Q.
E
■o
re
0.0
at
N
re
zo
-0.5
-
1.0
20
0
60
40
100
80
Time (ps)
Figure 2.1. Typical crystal simulation pulse shape
Normalized Magnitude
Pulse Spectrum
1
0.8
0.6
0.4
0.2
0
0
10
20
30
40
50
Frequency (GHz)
Figure 2.2. Pulse spectra.
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60
70
24
2.1.2
F r e q u e n c y R e s o l u t io n
and
T h e P a d e A p p r o x im a t io n
FDTD simulations produce a time sequence o f discrete time steps as output. This
output is typically transformed to the frequency domain using a Fourier transform. Using
5000 time steps in the unpadded Fourier transform provides a frequency resolution o f
approximately 129 MHz. Although this is sufficient to demonstrate rough trends in the
response, more frequency resolution was desired. One method to increase this resolution
involves increasing the number o f time steps. In order to achieve a 64 MHz resolution,
10000 time steps would be required, and this would result in a 108-hour simulation —an
unacceptably long time period.
Another method to achieve the desired increase in the frequency resolution, called
the Pade method, involves fitting the existing Fourier transformed TRIX 3D output data,
P(oa), to a function o f the form [7]:
(1)
where,
(2)
M
(3)
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25
The approximation can then be implemented by solving for the coefficient vectors a and
p using the output data samples from the Fourier transformed TRIX 3D output time
series, P(a>). Equation (1) can then be rewritten at discrete frequency points as:
P(a>J) - D u (a)J) = Q „ ( a > j ) ,
y = 0 ,...,5-1
(4)
where S is the number o f FFT data points to be used in the curve fitting. Allowing Po to
be equal to 1, (4) takes the form:
P { o ) j ) •Y f i p ' j ~ Y a , a ) j = - P i f i t j ) ,
i= l
7 = 0 ,...,5 -1
(5)
;'= 0
Because the a and p coefficients are multiplied by large powers o f <n for large numbers
o f FFT data points, the dynamic range required for accurate processing of this data is
very large.
When applying this technique, it is important to verify that the required
dynamic range has not exceeded that o f the computer’s internal representation o f floating
point numbers. An easy way to check for adequate computing dynamic range is to verify
that the original FFT data points (both real and imaginary components) can be accurately
recovered using the approximation. If the frequency points o f an actual FFT sample are
entered into the approximation, and if the values returned from the approximation do not
closely match the original complex FFT data, it is likely that the dynamic range o f the
computer’s floating point numbers has been exceeded. This check should be performed
at each o f the original FFT data points.
This Pade method was implemented using Wolfram's mathematics processing
software, Mathematica®. It was found that using the default representation for floating
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26
point numbers did not yield enough numeric precision for accurate recovery o f the
original FFT data points.
Fortunately, Mathematica allows for arbitrary precision
arithmetic. Using this feature the accuracy o f the computation was increased to insure
that the procedure was implemented accurately.
The Mathematica code used to
implement this procedure can be found in Appendix B.
To test the implemented procedure, a resonant cavity was simulated using the
TREX 3D code. The dimensions o f the simulated cavity were 8mm x 17.5mm x 9mm.
The FFT output data from this simulation is shown in figure 2.3 along with the Pade
approximation data. From this plot the enhancement o f the resonance peaks can be seen
clearly.
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27
Interpolated R e so n a n c e s
-40
-60
-80
-100
-120
— Data
— Pade Approximation
-140
15
20
25
30
35
Frequency (GHz)
Figure 2.3. Simulation and interpolated simulation
In applying this Pade technique to the simulated crystal data it was found that the
method did not improve the correlation with measured data. Nonetheless, it did yield
additional detail not seen in the original simulations. This will be discussed in more
depth in Chapter 3.
2.1.3
C a v i t y S im u l a t io n s W
it h
HFSS
Ansoft’s High Frequency Structure Simulator (HFSS) version 7 was used to
simulate many o f the cavity structures developed for this dissertation. Although this is a
commercially available software package, it has many pitfalls that one must work
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28
through before being able to efficiently simulate a given structure.
HFSS uses an
adaptive meshing technique to automatically enhance the mesh discretization o f the
structure to be simulated [8]. This adaptive technique starts by forming an initial mesh
with mesh vertices placed at the vertices o f the simulation object. The problem is then
solved at a single frequency. Next, HFSS enhances the existing mesh by adding more
tetrahedra to the mesh in regions that have the largest impact on the results (near vertices,
interfaces etc.). The problem is again solved and the solution is compared to the previous
solution. If the solutions match to within a degree o f error specified by the user, the
simulation is complete. If the solutions differ by more than the specified error, the mesh
is enhanced further; and the process is repeated until the two most recent simulations
agree to within the specified error. Typically, the allowable error between simulations is
specified in terms o f a ‘m ax im u m delta S .’ This is the maximum change in any
S-parameter (absolute, not dB) between the two most recent simulations. It is possible to
specify different error allowances for each S-parameter in the S-matrix. This can be
helpful in large simulations where convergence is problematic for an S-parameter that is
o f little interest.
2 .1 .4
H FSS Fr eq uen cy Sw e eps
Once HFSS has converged to an acceptable level at the meshing frequency, sweep
simulations are then performed. Two types o f sweeps are offered: a discrete sweep and a
fast sweep. The discrete sweep solves the simulation at each frequency specified in the
sweep using the mesh previously found. This method provides the most accurate result at
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29
the expense o f long simulation times. Because the problem is solved at each data point,
sweeps with large numbers o f points can become excessively long. To circumvent this
issue, the fast sweep option can be used. The fast sweep uses the adaptive Lanczos-Pade
sweep (ALPS) to extrapolate the field solution across the desired sweep range from a
single adaptive solution [8].
The main advantage o f this is speed.
The fast sweep
typically increases the simulation speed for sweeps with a large number o f points.
Several simulations were run on cavity structures using both the discrete and ALPS
sweep methods. For all structures tested, the ALPS fast sweep accurately reproduced the
data from the slower discrete sweeps. After verifying the reliability o f the fast sweep for
the types of structures being simulated for this dissertation, the fast sweep was used
almost exclusively.
Although the ALPS fast sweep typically results in a significant time savings for
frequency sweep simulations, the method requires significantly more computing
resources than single point and discrete sweep solutions.
On large problems (large
number o f tetrahedra), this can result in the inability o f HFSS to complete the sweep. We
have found that HFSS can typically solve discrete sweeps with meshes 1.5 to 2 times
larger than it would be able to complete using a fast sweep. Therefore, on some large
problems it is necessary to utilize the discrete sweep to enable the problem to be
simulated. TABLE 2-1 summarizes rough estimates o f maximum problem size for some
examples of computing resources, and may be helpful to gauge solvability for
simulations.
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30
n
Processor
„
Frequency
n
J
_
RAM
Approximate maximum number
,, , . . _ _ .
of tetrahedra for fast sweep
Pentium HI
450 MHz
384 MB
20,000
Pentium HI
550 MHz
768 MB
28,000
Dual Pentium III
550 MHz
1 GB
45,000
TABLE 2-1. Fast sweep simulation sizes.
2 .1 .5
HFSS P o r t s
In order to provide a signal source for simulations using microstrip lines, an HFSS
port is defined in the simulation setup. The design of this port is important for accurate
simulation results. An HFSS port consists o f a 2-D simulation object that lies against the
background o f a simulation. The HFSS solver uses the 2-D cross-section in a simulation
separate from the rest o f the problem to determine the allowable modes, impedances and
propagation constants o f the imaginary 3-D transmission line created by extruding the
2-D cross-section to infinity. The results o f the overall problem are usually reported in
terms o f an S-parameter matrix with port impedances normalized to the port impedance
calculated from the 2-D port extrusion. It is very important to take this into account
when examining the simulation results. For example, if the 2-D extrusion yielded a line
impedance o f 75Q, all S-parameters reported would be normalized to a 75Q system and
would not reflect the results obtained by measurement with a standard 50Q network
analyzer test set. For this reason, a renormalization routine is included with HFSS and
should be used to renormalize the port impedances to the desired value.
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31
Most o f the structures discussed here utilize a microstrip feed o f one configuration
or another. Typically the port object should be defined to encompass the ground plane
and the microstrip line, and the majority of the fringing fields o f the microstrip line. This
is usually straightforward, and the simulation edge can often be used in place o f a specific
port object when defining the port. In other situations like the EBG resonator, a specific
port object is required to properly define the port. In this case the port encompasses the
microstrip ground plane but not the dielectric or the ground plane for the cavity below the
microstrip feed board (see Figure 2.4).
I------------------------------------------------- 1
S pecial MBG reson ator port
Typical microstip port
Figure 2.4. Microstrip ports.
2 .2
M e a s u r e m e n t T e c h n iq u e s
In order to make measurements of the structures developed, several techniques
were used along with a high frequency network analyzer. Because o f the EBG crystal
design, measurements on this device had to be made in a free space setting.
Other
microwave circuits, like the EBG resonator, were measured using coaxial-to-microstrip
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32
connectors that allowed these circuits to be connected directly to the network analyzer’s
test port cables. Although this technique was convenient for the Duroid® microstrip
circuits, it was not useful for the silicon microstrip circuits presented here. To measure
these circuits, an on-wafer probing technique was used.
2.2.1
F r e e S p a c e EBG C r y s t a l M e a s u r e m e n t s
The measurements o f the EBG crystal were performed using two X-band horn
antennas connected to an HP8720C network analyzer. The hom configuration is shown
in figure 2.5. A metal adapter was fabricated to connect the transmit hom to the crystal
face. This adapter was sealed to both the hom and the crystal face with copper tape. This
prevented signals emitted by the transmitting hom from reaching the receiving hom
without propagating through the crystal structure. The inside o f the adapter was lined
with absorbing material to prevent unwanted resonances in the launch structure. The
adapter was also designed to allow the crystal to be rotated in 90° increments, allowing
polarization effects to be evaluated.
In order to normalize the measured data, a thru measurement was made using the
setup without the crystal. This data was then used as a baseline for other measurements.
Although the method does not provide calibrated field data, it is very useful to examine
the changes in crystal tra n sm ission resulting from different crystal or crystal defect
configurations. All crystal measurements were made in this fashion.
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33
Horn-crystal
adapter
MBG
Crystal
Receive
hom
Transmit
hom
Figure 2.5. Crystal measurement setup.
2 .2 .2
C o a x ia l
m easu rem ents
Circuits constructed on Duroid® were placed on aluminum or brass test fixtures.
These fixtures were fabricated to support Southwest Microwave SM A connectors. These
connectors can be used mode free up to 27 GHz. Clamps and, when possible, plastic
screws were used to secure the boards to the test fixture to prevent ground connection
problems.
Both the HP8720C and the HP8510 network analyzers were used in the
coaxial measurements. In all cases the network analyzer was calibrated using SOLT
calibration standards [9].
Calibration using these standards place the measurement
reference plane at the end o f the network analyzer’s test port cables. In some cases it was
necessary to remove the line loss incurred on the test fixture that was not part o f the
device under test (DUT). This loss was removed by measuring a ‘thru’ section o f the
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34
transmission line, computing the loss per unit length, and then subtracting the
extrapolated loss from the DUT data.
2 .2 .3
O n W afer M easu rem ents
In order to accurately measure devices fabricated on silicon wafers, a wafer probe
station and coplanar wafer probes were used. PicoProbe 150pm pitch GSG probes were
attached to the network analyzer with measurement grade coaxial cables. Calibrations
were performed using on-wafer thru-reflect-line (TRL) standards and NIST’s Multical
software [10]. By using on-wafer TRL standards for calibration, the reference plane for
the measurement is located on the wafer half way through the ‘thru’ standard.
This
allows test port cable and probe effects or probe-to-line discontinuities, as well as extra,
undesired, on-wafer transmission lines to be effectively removed from the measurement.
Because the silicon devices developed for this dissertation utilize microstrip
feeds, a coplanar to microstrip transition was needed to allow the coplanar probes to
connect to the microwave circuit. This transition is an altered version o f one the used in
[11]; it is shown in figure 2.6. Unlike the transition used in [11], this transition does not
use vias to short the landing pad to ground. For the frequency range o f interest, the top
ground plane of the landing pad provides enough capacitive coupling to the bottom
ground plane to eliminate the need for the shorting vias.
To verify proper operation of
this transition, two transition circuits were fabricated on a silicon wafer.
One circuit
consisted o f two transitions connected with a 200pm long microstrip line. The other
circuit replaced the 200pm line with a 1cm long line.
By measuring both o f these
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35
microwave circuits, the microstrip line loss can be separated from the transition loss. It
was found that each transition resulted in an additional 0.26 dB insertion loss. The data
from these measurements are shown in figure 2.7. Although this transition introduces
some loss, the effect o f this loss in the measurements is removed through the TRL onwafer calibration, as the effects o f the transition are lumped into the effects o f the probe /
cable combination.
985
ii
50
-H h -
120
-H k -
100
O
03
280
CM
CM
270
385
i r
Figure 2.6. CPW to microstrip transition (all dimensions are in microns).
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36
M easured Transition Data
o
-10
-20
-30
-40
—
S11,
S21,
S11,
• S21,
200pm
200pm
1cm
1cm
-50
16
18
22
Frequency (GHz)
20
Figure 2.7. CPW to microstrip transition data.
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24
26
37
3
3 .1
PBG C r y s t a l
Background
Photonic bandgap structures have been fabricated for optical applications for
some time [12]. Often, to ease fabrication these optical structures have been scaled to
centimeter sizes for use in the microwave regime [4]. Typically these structures consist
o f periodic stacks o f dielectric or metallic cylindrical rods or rectangular bars (figure 3.1).
The transmission behavior o f these structures is commonly altered through the addition o f
defects in the crystal structure. Often these defects are simply split or missing rods in the
crystal structure. Utilizing these defects, high - Q passband responses have been shown
both experimentally and through simulations [13].
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^^^^/..//::+$.//:D
Figure 3.1. Experimental crystal fixture.
For many applications fixed filter responses are acceptable; however, with
increased interest in multi-band wireless devices, the need for electronically reconfigurable high quality factor filters is on the rise. Electromagnetic bandgap structures
have the possibility o f drastically improving the filters used in reconfigurable devices.
Because the properties of the filter response can be altered by modifying the defect in an
EBG crystal, electronically controllable filters can be designed by utilizing switching
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39
elements in the crystal defects [14]. W ith this goal in mind, an experimental EBG crystal
was designed.
3 .2
E x p e r im e n t a l C r y s t a l D e s i g n
In order to allow the testing o f a broad range o f crystal structures, an adjustable
test fixture was designed.
This fixture consisted o f two brass frame sections with
accurately machined reference holes placed along the perimeter o f the frame. Alignment
pins were used to support the rod elements in the crystal. These pins were placed through
holes in the ends o f the crystal rods and through the alignment holes in the fram e (see
figure 3.2). This arrangement allowed the rods to be accurately placed and maintained in
the crystal structure, and allowed for a mechanically robust crystal. Additionally, by
leaving out elements during assembly, the periodicity of the crystal could be easily
modified (for example, only every other bar is installed). For ease o f construction, offthe-shelf brass bars (obtained from a hobby shop) were used to construct the crystal
elements.
Although the use o f off-the-shelf parts limited the accuracy o f the cross
sectional dimensions o f the bar, it significantly reduced the cost and time required to
construct the fixture.
Using the finite difference time domain simulations discussed in section 2.1, the
dimensions o f the crystal frame were chosen. The rod sizes were also chosen using this
method; however, the rod sizes were limited to those readily available at the local hobby
shop. These dimensions are summarized in TABLE 3-1.
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40
AlignmenfrPin
Frame
Figure 3.2. Close-up o f experimental test fixture.
3 .2 .1
D efects
Typically, defects in electromagnetic bandgap structures consist o f missing or
broken rods (see figure 3.3). To create the missing rod defect, rods are simply left out
Parameter
Value
Rod to Rod Spacing
12.7 mm
Rod Cross-Section
2.38mm x 2.38 mm
Layers
12 (rods)
Overall Size
~14cm square by 2.7cm
= 1 1 x 1 1 x 1 2 rods
TABLE 3-1. Crystal dimensions.
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41
during the assembly o f the crystal. To create the broken rod defect, a section of an
existing rod must be removed. This presents a problem with respect to maintaining the
two separate rod sections accurately in the crystal structure because only one end o f each
rod section is mechanically attached to the frame. Although the missing rod defect is
easy to fabricate, it does not lend itself to the insertion o f a switchable device; therefore,
the broken rod defect was used. To circumvent the structural problem associated with the
broken rod defect, a low dielectric plastic support was placed in the center o f the square
metallic rod for support. This arrangement makes it possible to insert a p-i-n diode in the
gap o f the gap defect rod. By adding a switching diode in the middle o f the crystal rod,
the broken rod defect can be approximated when the diode is off. When a bias current
flows through the p-i-n diode, the gap in the rod is effectively closed, approximating the
fully conducting rod case. Although this seems like a straightforward task, biasing the
diode can be difficult in a metallic crystal. Without careful design, the conducting rods
surrounding the defect rod allow a DC conduction path around the p-i-n diode, thereby
preventing its biasing.
To circumvent this problem, the defect structure o f figure 3.4 was designed. This
defect rod utilized a hollow brass square rod with a cylindric plastic center for support.
The outer metal o f the rod was removed to allow insertion o f a printed circuit board
containing the p-i-n diode. Additionally, a small gap at each end o f the rod was added to
prevent the bias current from shorting to the crystal frame. Finally, the rod was coated
with non-conducting enamel to keep it DC isolated from the other rods o f the crystal.
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42
Figure 3.3. Typical defect structures.
p -i-n Diode on PCB
Support
Plastic Support
Alignment Pin
Bias Leads
Figure 3.4. Electronically switchable defect element.
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43
3 .2 .2
S im u la te d a n d M e a su r e d R e s u l t s
Using 5 o f the defect elements shown in figure 3.4 placed into layer 7 o f the
crystal structure and using the measurement methods described in section 2.2, the
controllable defect crystal was tested. Because o f measurement issues, and because the
edge o f the crystal bandgap region provides the most rapid variations in the transmission
behavior, the leading edge o f the bandgap (see figure 3.5) was selected as the frequency
band o f interest. The crystal transmission was tested with the diodes switched on (no­
defect case) by applying a bias current to the p-i-n diode in the defect. Bias currents in
the range of 10- 40 mA were tested, and it was found that the transmission behavior was
m
■o
to
-20
8
s
aJ
£
-40
Leading edge of the
transition region
CD
Z
-60
-80
5
10
15
20
Frequency (GHz)
Figure 3.5. Crystal transition region.
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25
30
44
not strongly dependent on the level o f bias current used for the diodes-on case. A bias
current o f 30mA was selected for the remaining measurements. The results o f these
measurements are shown in figure 3.6. They demonstrate a 7dB change in insertion loss
between the diodes-on and diodes-off cases when the input electric field polarization is
parallel to the defect element. When the input field is perpendicularly polarized with
respect to the defect, there is very little contrast between the diodes-on and diodes-off
cases (see figure 3.7). This result is expected as the defect in the defect element acts to
disrupt currents primarily in the direction o f the element.
Although the quantitative
agreement between these data and the simulated data (figure 3.8 and figure 3.9) is poor,
qualitatively the simulations predict the trend with some accuracy.
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45
Crystal Defect Measurements
Insertion Loss (dB)
-10
-20
-30
-40
-50
Diodes On
Diodes Off
-60
10
11
12
13
Frequency (GHz)
Figure 3.6. Measured crystal transmission, polarization parallel to the defect rod.
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14
46
Crystal Defect Measurements
Insertion Loss (dB)
-10
-20
-30
-40
Diodes On
Diodes Off
-50
-60
10
11
12
13
Frequency (GHz)
Figure 3.7. Measured crystal transmission, polarization perpendicular to the defect rod.
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14
47
Crystal Defect Simulations
-20
Insertion Loss (dB)
-10
--3 0
-20
-40
-50
12.75
-30
13.00
-40
-50
— Diodes On
— Diodes Off
-60
10
11
12
13
Frequency (GHz)
Figure 3.8. Simulated crystal transmission, polarization parallel to the defect rod.
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48
Crystal Defect Simulations
Insertion Loss (dB)
-10
-20
-30
-40
-50
- Diodes On
- Diodes Off
-60
10
11
12
13
Frequency (GHz)
Figure 3.9. Simulated crystal transmission, polarization perpendicular to the defect rod.
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49
3 .2 .3
Im proved D e f e c t
During the assembly o f the defect crystal, it was found that the defect elements
were very fragile and would often break, mainly due to inadequate diode support. Any
flexture o f the diode rod placed stress on the thin diode leads, pulling them from the
diode package. The initial defect design also yielded a defect that was centered over the
rods in the previous and succeeding layers.
Additional simulations indicated that
relocating the defect in the crystal would improve performance. Therefore, rather than
centering the defect, which placed the defect above a rod in the crystal, an improved
Initial d e fe c t
Figure 3.10. Initial and improved defects.
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50
defect rod was designed which placed the defect over one o f the gaps in the previous
layer o f the crystal (see figure 3.10).
Other improvements made to the defect rod
included additional side support to prevent diode damage during assembly, and an
additional series p-i-n diode. This diode was added to effectively widen the diodes-off
defect gap. Using this new defect arrangement, the crystal parameters were re-measured.
The simulated results for the parallel polarization are shown in figure 3.11 along with the
simulated results from the original defect for comparison. These simulations indicate a
significant increase in contrast between the two diode states. This improvement can also
be seen in the measured results o f figure 3.12.
From the measured data, a 30.2 dB
contrast change is shown between the diodes-on and diodes-off cases.
As with the
original defect, the simulations and measurements show some qualitative agreement and
were useful in predicting design trends; but quantitatively the agreement is poor. With
more precise fabrication techniques the quantitative agreement between simulation and
measurement could be improved; however, without a comprehensive model for the diode
switch, the
agreement between simulation and measurement will be
limited.
Additionally, modeling the effects o f the circuit board and diode would significantly
increase the size o f the FDTD mesh, and would therefore result in a significant increase
in simulation times.
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51
-10
-10
-20
-20
/ I‘/ y
-30
'vA
^ «
-40
14
13
GHz
No Defect
Original Defect
Improved Defect
-40
-50
18
Frequency (GHz)
Figure 3.11. Simulated insertion loss with the original and improved defects.
-1 0
CQ
XJ
D iodes Off
D iodes On
-20
-1 0
-20
-30
-40
-50
CM
CO
-40
-50
12.1
GHz
12
14
13
Frequency (GHz)
Figure 3.12. Measured insertion loss o f the improved defect
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52
3.2.4
P ade S imulation E nhancements
In order to try to provide a better correlation between the simulated and measured
results for the controlled defect EBG crystal, the m ethod outlined in section 2.1.2 to
increase frequency resolution o f the FDTD simulation data was used.
This post
processing method, the Pade approximation, was applied to the improved defect FDTD
simulation data. The results are shown in figure 3.13 as a comparison between the
original and approximated data sets. Although this method did add detail not previously
visible in the simulated results, it did not quantitatively improve the correlation between
the measured and simulated data. The Pade approximation can be used to accurately add
detail to simulated data only if the original simulation data contains enough points to
recreate the dominant poles and zeros o f the frequency response in the frequency regime
o f interest. It is believed that more than 5000 data points are required to meet this criteria
for the crystal structure. Because the approximated data indicates the passive device
generates power around 14 GHz, it is clear that there is not enough information in the
simulation data to accurately enhance the data with this method. The small number o f
samples coupled with the fact that the crystal structure contains parasitic effects that are
not possible to simulate accurately (bar dimension variation for example), ultimately
limited the correlation o f the measured and simulated data. The Pade approximation, like
all fitting and modeling techniques, can be o f limited use when details exist in the
physical device that are not present in the model.
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53
10
m
XJ
-10
C
CO
O
o
_j
o
■g -20
CO
c
-30
Pade Approximation
Simulation Data
10
11
13
12
14
15
16
Frequency (GHz)
Figure 3.13. Application o f the Pad£ approximation to simulation data.
3.3
C o n c l u s io n s
fro m th e
EBG
c r y s t a l e x p e r im e n t s
These experiments have shown that electrically controlled defects can be created
in electromagnetic bandgap crystals. On-to-off contrast ratios of more than 30dB were
demonstrated for a stopband filter with the improved defect design. It was shown that
defect placement has a significant impact on the depth o f the stop band. Additionally, it
was found that the crystal assembly and reliability is aided significantly by sturdy defect
elements.
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54
Although the EBG crystal suffers from a large insertion loss at the controlled
defect frequency, it demonstrates the possibility of utilizing electronically controlled
defects for more useful reconfigurable filters.
Additionally, for m ost practical
applications, structures must be compatible with integration into more complex
environments. In its current configuration the controlled defect crystal can not be easily
coupled with planar microwave circuits.
In the following chapter this issue will be
addressed and the knowledge gained from the EBG crystal will be used to develop a
resonator based on an EBG structure that can be easily coupled to other microwave
circuits.
This resonator has many desirable features and is the basis for the
reconfigurable resonator that will be presented in Chapter 5.
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55
4 T h e P l a n a r E B G C a v it y R e s o n a t o r
4 .1
T h e M ic r o s t r e p C o u p l e d C a v it y R e s o n a t o r
Microstrip coupled resonators have been used to create high-Q passband
responses [2].
These resonators utilize a conducting rectangular cavity coupled to
microstrip input and output transmission lines via magnetic coupling slots in the top
cavity wall (see figure 4.1). Typically these slots are placed one quarter o f the cavity
length from the edge o f the cavity. To provide efficient coupling it is important that an
Magnetic Coupling
/
Slots
SP
Microstrip
F eed lin e
co
Cavity
SL
Cav'ty Length
Figure 4.1. A microstrip coupled cavity resonator.
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56
electric short circuit exist at the center o f the coupling slot.
Typically this is
accomplished by extending the feed transmission line X/4 beyond the coupling slot
center. This open circuited transmission line then reflects a short circuit to the slot. T he
slot width (SW) and slot length (SL) control the amount o f coupling to the cavity, and
can be selected as described in [2]. Depending on the conductivity o f the cavity w alls
and the cavity dimensions, the Q ’s o f these cavities can range from 200 to 1000 or m ore.
Most often these cavity resonators are operated in the TEioi mode in which a one h a lf­
wavelength standing wave exists in the width and length dimensions. For this mode, th e
resonant frequency can be described by [15]:
(6)
7E101
where c is the speed o f light, and L and W are the cavity length and width, respectively.
Because the cavity is air filled (sr=1), all cavity losses occur as metal losses. Therefore
the cavity quality factor, Q , is equal to the Q due to metal losses, Q c , and can b e
computed from:
where W , L and H are the cavity width, length and height, respectively, 77 is the w ave
impedance, k is the wave number, and the effective resistance,
7E101
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(8)
57
Although a cavity resonator designed in this manner can be a very useful device,
it can be difficult to fabricate. In order to achieve vertical side walls and square cavity
comers, precision machining o f the cavity structure is necessary. This machining can be
time consuming and expensive; and when complete, the cavity must then be attached to
the feed circuit in some manner. Because o f fabrication requirements, the cavity lid can
not be part o f the cavity. Usually the ground plane o f the feed wafer is used as the cavity
lid; therefore, a gap may exist at the cavity —cavity-lid junction. Added resistance or
gaps at this edge can lead to leakage and degradation o f the cavity Qc4 .2
EBG
S id e W a l l s
The construction issues associated with the fully conducting side wall (FCSW)
cavity have been addressed by the introduction o f an electromagnetic band gap structure.
This structure consists of an array of conducting posts that define the side walls o f the
cavity. Rather than containing the cavity fields by a solid metal wall, the EBG structure
was created with a stop band at the operating frequency o f the resonator, and was used to
confine the fields to the cavity region (see figure 4.2). This provided several advantages
over the FCSW cavity. First, it allowed the cavity to be constructed in a low loss circuit
board material. This eliminated the m ach in in g required for cavity construction in the
FCSW resonator, and replaced it with standard circuit board fabrication techniques.
Secondly, by replacing the FCSW cavity with a circuit board EBG cavity, the problems
associated with the closure o f the cavity lid were eliminated.
With the EBG cavity
resonator, the top and bottom o f the cavity were created using the metalization on the
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58
circuit board material, forming a gap-less cavity. Although there was still an interface
between the top and bottom boards, this interface was no longer part o f the cavity.
Therefore, a gap at this interface would not impact the cavity Q. In addition to these
advantages, by replacing an air filled metal cavity with the EBG circuit board cavity, the
dielectric constant o f the circuit board material was used to reduce the size o f the
resonant structure.
Microstnp
Feedline
A
f J
Microstrip lines —^
Microstrip feed board
Cavity
Plated
Vias
MBG Cavity
Walls
Figure 4.2. The microstrip coupled EBG cavity resonator.
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Metal
i
59
The FCSW cavity was used as a model for the EBG cavity by using the
centerlines o f the vias to define the effective location o f the cavity edge. This allowed
equation (6 ) to be used to design the EBG cavity. With the addition o f the dielectric
constant o f the circuit board material, s r, equation ( 6 ) becomes [15]:
/n n "'
1l ( l )
2^
* {w )
Equation (7) is stillused in the computation o f the quality
'
(9>
factor o f the resonator;
however, to account for dielectric losses as well as metal losses, the following equation is
used:
— = —
Q
Qc
+ —
( 10 )
Qo
where, if tan(5) is the loss tangent o f the dielectric, then,
1
= tan(<5)
Qo
With this method, a resonant EBG cavity was designed with a 10.5 GHz
resonante frequency. To provide proper operation o f the EBG sidewalls in this resonator,
the spacing and size o f the vias used to define the cavity was selected to provide a stop­
band in the EBG at the operating frequency o f the resonator. This was achieved by
limiting the gap between the posts to no more than 'AX at the highest operating frequency
o f interest; however, by reducing the gap size further, the overall size o f the structure was
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60
reduced. The spacing was also adjusted so a whole number o f posts would be used to
define the cavity. A square lattice was chosen for the resonator EBG because simulations
indicated that this would provide the best confinement for a given number o f EBG rows.
Simulations also indicated that 2 rows o f posts would be adequate to limit losses due to
leakage. TABLE 4-1 summarizes the design dimensions for this resonator.
Width
11.34 mm
S
1.29 mm
Length
18.90 mm
Via Diameter
0.79 mm
SP
5.12 mm
Via Spacing
1.89 mm
SW
3.48 mm
EBG Rows
2
SL
0.34 mm
TABLE 4-1. EBG Cavity filter dimensions.
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61
4 .3
F a b r ic a t io n
Standard printed circuit board fabrication technology was used to construct the
EBG cavity resonator. After simulating and optimizing the structure using HFSS, the
design was imported into Adobe Illustrator® for mask generation. To provide accurate
drill locations for the construction o f the EBG posts, undersized holes were printed on the
mask (see figure 4.3). When etched on the circuit, these holes provided pilot drill holes
and enabled easy and accurate drilling using a milling machine. Duroid® 5880 circuit
board material (er=2.2, tan(8)=0.0009) was used for the cavity board, and Duroid® 6010
(er=10.8, tan(8)=0.0024) was used for the top feed circuit board. Both boards were
0.031” thick. Other board materials could have been used with appropriate adjustment o f
the transmission lines and structures. After printing and etching the circuit board using
the procedure in Appendix C, the EBG post holes were drilled. Then, using the copper________________________________________ I
_ l ____________________________________ I
Microwave Bandgap Cavity Fitter
V1.0 4/24/2000
>
ffi
o
o
The University of Arizona
Department of Electrical and Computer Engineering
Top Board Top
The University of Ar rona
Department of Electrical and Computer Engineering
Bottom Board Top
Figure 4.3. EBG Cavity board masks.
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62
through-hole via fabrication method outlined in Appendix D, the posts o f the EBG were
created. The circuit was then trimmed to fit the test fixture, and the boards were mounted
to the fixture. Alignment between the top and bottom boards was achieved through the
use o f alignment holes drilled in both boards. A pin placed through these holes ensured
accurate alignment between the boards.
4 .4
S im u l a t io n
and
M
ea surem ent
Ansoft's HFSS was used for the simulations and optimizations o f the cavity
resonator.
Using this tool both S-parameter data and field plots were generated.
Examination of the cavity fields demonstrate the containment provided by the EBG walls
(see figure 4.4). The simulated S-parameter data are presented in figure 4.5; they show
good agreement between simulation and measurement, with the exception o f the roll-off
in the measurement above 11 GHz. It is believed that the main source o f discrepancies
between the simulated and measured responses is related to assembly issues, and could be
eliminated through professional board fabrication. In this configuration the resonator
provided a 1.33% bandwidth with 2.17dB o f insertion loss. TABLE 4-2 summarizes
these results.
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63
Figure 4.4. Fields in the EBG cavity.
Sim ulated
-10
-20
S11
30
-4 0
-1 0
-20
-5 0
10
1 0 .5
10
Frequency (GHz)
Figure 4.5. EBG Cavity simulated and measured results.
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12
64
Simulated
Measured
Difference
10.51 GHz
10.67 GHz
1.5%
Bandwidth
1.65%
1.33%
0.3%
Insertion Loss
1.82 dB
2.17 dB
0.35 dB
TABLE 4-2. EBG Cavity resonator results.
4.4.1
R esonator Q
In order to measure the unloaded quality factor o f the EBG resonator, another
circuit wasfabricated.
In this circuit the couplingslots o f the original resonator were
replaced with much smaller
slots.
This reduced the microstrip-cavity coupling and
allowed for accurate extraction o f the circuit’s Q.
Because o f the sensitivity of the
extracted Q value, it is important that the coupling for the resonator be designed to
provide approximately 20 dB o f insertion loss. Using this low-coupling circuit (see
figure 4.6), the unloaded Q was determined to be 293 using [2]:
_ SRESONANT
.r
LOADED ~
n n
V1 l )
bfldB
p 2.(rfg)1
QEXTERNAL ~
^
— = ---Q QLOADED
' QLOADED
C ^)
(13)
QEXTERNAL
where, Q loaded is the cavity Q with the loading effects o f the microstrip line.
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65
Using a similar low-coupling cavity in an HFSS simulation resulted in a simulated
Q=300.
This provided very good agreement between simulation and measurement.
However, it was determined that extraction o f Q values using HFSS simulations can be
very sensitive to the discretization mesh used.
For accurate results the convergence
criteria used for the simulations must provide an extremely dense mesh.
Using the
FCSW cavity equations (7) and (10) to predict the Q o f the EBG resonator yields Q=518.
After much investigation it was found that the Q’s predicted by HFSS converged to the
values given by (7) and (10) if the discretization mesh was sufficiently dense. This left a
very large discrepancy between the measured and expected Q for the resonator.
-20
-
m
•o
CM
co
-40 -
-50 -
-60
8
9
10
11
Frequency (GHz)
Figure 4.6. Low coupling Q measurement
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12
66
During the plating o f the vias that make up the EBG posts, a conductive ink is
used as a seed layer for the copper plating process (see Appendix D for detailed
information on the plating process). The ink manufacturer specifies that a 31 mil via
coated with ink (not plated) will result in a via with a 2 ohm resistance. Assuming a
31 mil thick board, the conductivity o f the ink was calculated to be approximately
T10 4S/m. Although it is difficult to gauge the thickness of the ink layer, it was at least
25pm. At 10.5 GHz this results in a layer of very lossy material that is a skin depth or
more thick.
Simulations with HFSS confirmed that the introduction of lossy post
material would result in Q values drastically lower than expected. The losses from these
vias were found to be the source of the discrepancy between measured and simulated Q
values. The reconfigurable resonators discussed in the next chapter address this problem
by creating the EBG posts with a process that does not utilize the lossy, Q reducing ink.
In addition to improvements in the manufacturing processes, a careful
examination o f equation (7) reveals another method o f increasing the Q of the resonator.
For a fixed width and length cavity, metal losses can be reduced by increasing the height
o f the cavity. As the metal losses are decreased, the corresponding Qc increases and
results in an increase in the overall dielectric loaded cavity Q. When the dielectric losses
are accounted for through equation ( 10 ), a plot o f the various loss mechanisms and the
resulting Q values can be created. Figure 4.7 demonstrates the effect of cavity board
thickness on overall cavity Q. Increases in overall Q through an enhanced Qc is limited
by the dielectric loss o f the board material. Figure 4.7 also indicates that for thin boards
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67
Unloaded Q and its components Qc and QD
2000
Metal Limited
1500
Current design
500
Dielectric Limited
0
0.0
0.5
1.0
1.5
2.0
2 .5
3.0
3.5
Board Thickness — Cavity Height (man)
Figure 4.7. Q As a function o f printed circuit board thLckness.
the losses are dominated by metal conductivity loss, and th at for thick boards the
dielectric losses are the limiting factor. This fact allows the Q o f the resonator to be
selected, within reason, by the choice o f board thickness.
4.5
Sum m ary
o f resu lts fr o m t h e
EBG r e s o n a t o r
A reduced size, planar electromagnetic band gap microstrip coupled resonator has
been designed, simulated and tested. Using this resonator as a single pole filter resulted
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68
in a 10.67 GHz passband filter with a 1.33% bandwidth and less than 2.2dB insertion
loss. The topology o f this structure provides microwave circuit designers with a means to
create planar, high Q filters using fabrication techniques currently available at any
commercial board house. Additionally, the cavity filter can be utilized in microstrip
circuits without modification. Through the use o f the closed form rectangular cavity
resonance equation, the physical parameters o f the filter can be computed easily and
directly. Final op tim iz a tio n s can be performed using commercially available simulation
tools. The flexibility o f this design is further enhanced through the availability o f circuit
board materials. Dielectric constants and board thicknesses can be chosen to alter the
filter properties or to facilitate integration with other system components. This design
also allows for the construction o f reconfigurable filters by electronically or mechanically
“turning o ff’ rows o f posts enclosing the resonant cavity. The next chapter will focus on
this capability and will discuss the design and development o f a reconfigurable microstrip
coupled EBG resonator.
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69
5 A R e c o n f ig u r a b l e
5 .1
R e c o n f ig u r a b l e
EBG
c a v it y r e s o n a t o r
r eso n a to r w alls
The cavity resonator discussed in chapter 4 consists of a cavity defined by plated
thru-hole vias. In order to provide reconfigurablility, special switchable post elements
have been introduced at two o f the cavity side walls. By turning these posts ‘on’ the
effective width o f the cavity is reduced, thereby increasing the resonant frequency o f the
circuit (see figure 5.1). In the circuit presented here one row on each side o f the cavity
was created with switchable elements, but more than one row could be ‘switched’ and
would allow the operation o f more than 2 resonant frequencies.
The switchable and static elements used in the EBG walls o f the cavity were
constructed using conductive vias.
To eliminate the extra losses caused by the
conductive ink used in the prototyping thru-hole via process, each via was created with a
solid 0.031” brass rod soldered to the top and bottom ground planes. The switchable
elements were created by printing am annular ring gap at the top o f these vias. This ring
was used to disconnect the top o f the via from the ground plane closing the top o f the
cavity structure (see figure 5.2). By removing the current path connecting the via post to
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70
the top o f the cavity, the blocking effect o f the post is essentially removed. Figure 5.3
shows the fields in the cavity with the two switchable rows turned off.
Although the
posts in the off state do perturb the fields slightly, the resonant frequency can be
approximated by equation (9) with the cavity width defined without th e switchable
elements, as in figure 5.1. Fine tuning can then be performed using simulations. In order
to turn the controllable elements on and off, the annular ring gap was closed
mechanically by clamping a metal ground plane across the gap. This all-owed currents
from the post to flow to the top ground plane, effectively blocking fiedd penetration
beyond the post.
Cy C; C*' C/
S w itch -o n c a s e
S w itc h -o ff c a s e
Figure 5.1. Reconfigurable cavity side wall.
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71
A n n u la r R ing G ap
M etalized Via
Figure 5 2 . Switchable via element.
Figure 5.3. Cavity fields with switchable elements turned off.
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72
5 .2
R esu lts
Using the photolitographic techniques outlined in appendix C, the reconfigurable
resonator cavity was fabricated using Duroid® 5880 (er=2.2, tan(8)=0.0009), and the
microstrip feed lines were fabricated on Duroid® 6010 (er=10.8 tan(5)=0.0024).
Simulations were run for both the switch ‘on’ and ‘o f f cases. For the switch ‘o f f case,
the annular ring structure was simulated using octagons rather than circular elements. To
demonstrate the reconfigurability and to allow for an accurate Q measurement, the
coupling slots for the resonator were reduced in size to allow for an insertion loss o f
appoximately 20dB.
The relevant design parameters, selected as described in the
previous chapter, are shown in TABLE 5-1 (refer to figure 4.2). The simulated response
for both the switch ‘on’ and switch ‘o ff cases are shown in figure 5.4.
The
corresponding measured results are shown in figure 5.5. Using the techniques described
in section 4.4.1, the numerical results shown in TABLE 5-2 were extracted.
SP
5.26 mm
Cavity Length
sw
2.30 mm
Cavity W idth
SL
0.14 mm
Via Diameter
0.79 mm
Via Spacing
1.89 mm
18.9 mm
(Switch On)
11.34 mm
(Switch Off)
15.12 mm
TABLE 5-1. Design Parameters
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73
S im u la te d Low C oupling D ata
x.
Switch-On i
Sw itch-O ff
-10
S21 (dB)
-20
-30
-40
-50
-60
8.0
8.4
8.8
j
10.4
10.6
10.8
Frequency (GHz)
Figure 5.4. Simulated results from the reconfigurable EBG resonator.
Switch State
Resonant Frequency
Unloaded Q
On-simulated
10.67 GHz
445
On-measured
10.60 GHz
448
Off-simulated
8.36 GHz
260
Off-measured
8.63 GHz
274
TABLE 5-2. Simulated and measured results.
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11.0
74
M e a s u r e d Low Coupling Data
xj
Switch-On :
Switch-Off
-1 0
-20
CM
-30
CO
-40
-50
-60
8. 0
8.4
8. 8
10.4
1 0 .6
10.8
11.0
F r e q u e n c y (GHz)
Figure 5.5. Measured results from the reconfigurable EBG resonator.
The results o f TABLE 5-2 demonstrate both the ability to reconfigure the resonant
frequency o f the device and the Q’s achievable with this planar structure. Because this
resonator is similar in structure to the one discussed in chapter 4, the effect o f the cavity
height on the Q follows a similar trend as described in figure 4.7.
This allows the
adjustment o f the cavity Q by selection o f the cavity board thickness. Equations (7) and
(10) can be used to accurately predict the cavity Q for the switch-on case; however, the
results for the switch-off case are not well predicted by these equations. As show n in
TABLE 5-2 the switch off case exhibits a significantly lower Q than the switch-on case.
This phenomena was investigated using the HFSS simulator, and it was found that the
open annular rings used in the switch element significantly disrupt the currents flowing
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75
Figure 5.6. Switchable element ‘cap’.
on the cavity lid, resulting in an energy loss. To circumvent this problem, the structure o f
figure 5.6 was designed. This ‘cap’ covers the annular ring and provides a path over the
gap for the currents flowing on the cavity lid. Although the switch still eliminates the
post-to-lid current path in the ‘o f f state as desired, the cap improves the ‘o ff state cavity
Q by reducing the disruption o f the cavity lid currents caused by the open annular rings.
Simulations were run to test this concept. The results o f these simulations (shown
in figure 5.7) indicate that adding the ‘cap’ to the switching elements o f the
reconfigurable EBG cavity resonator results in an increase o f the off-state unloaded Q to
approximately 406. This is much closer to the ideal closed cavity response in both the
quality factor and the resonant frequency.
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76
The cap of figure 5.6 has not yet been fabricated for test. Construction o f this
type o f structure will require a printed circuit board bridge fabrication technique to be
implemented.
-15
-20
-25
-30
CD
T3
-35
CNJ
CO
-40
-45
-50
-55 l—
8.00
8.25
8.50
8.75
9.00
Frequency (GHz)
Figure 5.7. Simulated switch-off response.
5 .3
C o n t in u i n g D e v e l o p m e n t
In its current configuration the reconfigurable EBG cavity resonator must be
reconfigured mechanically and in its ‘ofP state it exhibits a lower than desired Q. By
fabricating the ‘cap’ structure discussed above, the ‘off* state Q can be improved
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77
significantly. This ‘cap’ structure appears similar in topology to many o f the MEMS
switches in the literature [16], and it is believed that both the cap and switch could be
implemented using a single micromachined switch structure.
This switch would be
designed to allow the cavity lid currents to flow freely over the switchable element in the
‘o f f state, and would allow for the shorting o f the element to the cavity lid to provide the
switch ‘on’ state.
Construction could be implemented on silicon to allow silicon
micromachining techniques to be utilized for fabrication.
substrate poses a few design challenges.
Introduction o f a silicon
First, an ultra high resistivity silicon wafer
would be required in order to keep the dielectric losses to a minimum. Additionally,
construction o f the cylindrical vias in a silicon substrate would require advanced
micromachining techniques such as laser micromachining [17] coupled with a high
aspect ratio metal deposition technique to metalize the vias. Although these issues will
present challenges, the construction on silicon would be advantageous. The dielectric
constant of silicon is approximately 11.7 [15] and would thus provide a significant
reduction in cavity size for a given resonant frequency (as described by equation (9)).
Other construction possibilities include fabrication on substrates such as quartz which
could provide some of the benefits o f silicon while maintaining ultra low dielectric
losses.
Conversion o f the mechanical switching utilized here to electronic switching
could be implemented without the introduction o f a silicon substrate. The mechanical
switching action utilized on the Duroid® resonators could be implemented with p-i-n
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78
diodes or other active switching devices. Introduction o f a semiconductor device with
current control capability, such as a MOSFET, could provide both electronic switching as
well as intermediate switching states. These intermediate states could be designed to
provide an adjustable Q by introducing an adjustable loss mechanism to the microwave
circuit. Additionally, by individually switching posts that define the cavity wall rather
than switching a complete row o f the wall, a multitude o f resonant structures could be
formed through an electronic reconfiguration.
5 .4
C o n c l u s io n s
A reconfigurable, planar resonator has been designed, fabricated and tested.
Because the resonator utilizes planar construction and microstrip feeds, it is easy to
integrate with other planar circuits.
Additionally, the resonator is compatible with
standard printed circuit board processing techniques. This coupled with the ability to
reconfigure the resonant frequency makes the circuit well suited for use in massproduced, cost sensitive microwave devices.
Future work will enhance the current design by using thicker substrates to
produce resonators with Q ’s above 500. Implementation o f electronic switching elements
through the use o f MEMS or semiconductor devices will allow electronic control o f the
resonant behavior o f the cavity structure.
With these resonators, electronically
reconfigurable controlled ripple filters can be implemented through the use o f multiple
reconfigurable resonators. Other useful reconfigurable devices, such as reconfigurable
diplexers will eventually be developed. Towards this end, and as part o f the ground work
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79
for developing a reconfigurable EBG diplexer, a microstrip coupled cavity diplexer was
developed. This diplexer is the focus o f the next chapter.
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80
6 M ic r o s t r ip C o u p l e d C a v it y D i p l e x e r o n
D u r o id ®
6 .1
O v e r v ie w
Microwave and millimeter wave (mm-wave) components have traditionally been
built with waveguide technology. This technology offers low-loss and high quality factor
circuits. However, because o f the physical size and construction materials used,
waveguide components are often large, heavy and expensive. Additionally, waveguide
components often require waveguide-to-microstrip transitions that are both expensive an d
lossy, and that complicate the integration with monolithic microwave circuits.
For
commercial systems, where high yield, increased component density and low cost are
fundamental requirements, the drawbacks o f waveguide components can often prohibit
their use.
One o f the major limiting waveguide components o f microwave / m m-wave
wireless communication systems is the transmit / receive diplexer that is used to provide
low-insertion loss and high channel-to-channel isolation. Realization o f the diplexer w ith
planar resonators and filters is generally avoided due to the low quality factor and higher
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81
losses caused by the presence o f the substrate material. With the recent developments in
microwave micromachining, however, it is now possible to make planar cavity resonators
that offer high-Q and narrow bandwidth responses. Because of the planar nature o f these
devices, they are easy to integrate with other passive and active components.
Using microstrip coupled cavity resonators fabricated in an aluminum test fixture,
a transmit / receive single-pole diplexer has been created.
This diplexer was
implemented in this fashion as a test circuit for the corresponding construction on a
silicon wafer using silicon micromaching techniques. The long-term objective o f this
effort is to eventually fabricate a multi-pole diplexer on silicon with the reconfigurable
EBG resonators discussed in the previous chapter.
6.2 Cavity D esign
The diplexer developed in this dissertation is designed around two microstrip
coupled FCSW cavities. Because o f recent interest in the use o f K-band (18-26.5 GHz)
for point to point communications and wireless LANs [18], the operating frequencies,
19 GHz, for transmission and 21 GHz, for reception, were selected for the diplexer
design. Using the air filled cavity resonance equation (6) of chapter 4, the width and
length for two rectangular TEioi resonant cavities were found to be: W=8.01mm,
L=17.5mm and W=8.85mm, L= 15.83mm for the transmit and receive cavities,
respectively. For each of these cavities, the unloaded Q at resonance is governed by the
metal loss in the cavity. This loss, and therefore the Q o f the cavity, is a function o f the
cavity height. It is described by equation (7) o f chapter 4. In this case, a height o f
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82
0.93mm was chosen; this choice allows the design to be easily converted to a silicon
device utilizing a 1 mm thick substrate. This height provides theoretical unloaded Q’s of
approximately 1321 and 1366 for the transmit and receive cavities, respectively.
Using the cavity filter design strategies discussed in chapter 4 and in [2], the
transmit and receive single-pole filters o f the diplexer were designed independently. The
microstrip feed structure was designed for use on 31 mil thick Duroid® 6010 which has a
relative dielectric constant o f 10.8.
This was chosen because it would facilitate the
conversion to silicon (£r= 11.7) which will be discussed in the next chapter. Because this
substrate supports the input and output feed lines to the cavities, it has very little impact
on the operation o f the air-filled cavity. In order to use a top substrate with a different
dielectric constant, one has to readjust the widths o f the input and output microstrip lines
to provide a matched 50 Q line impedance. The other filter dimensions would remain
largely unchanged. Because o f physical layout limitations, this fact can be useful and
will be discussed in more detail later in this chapter.
Following the rough design o f the cavity dimensions, the cavity structures were
modeled in HFSS. This allowed the cavity performance to be simulated and optimized.
A scripting language provided in HFSS allows the user to vary the structure parameters,
such as the input and output stub lengths; simulate; and store the simulation results
without further user intervention. Because the runtime o f each cavity simulation can be
long, this scripting capability made parameter sweeps and optimizations significantly
more efficient. Using this method, the initial cavity parameters were adjusted to improve
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83
the performance o f each cavity. The simulated response (S21) o f each cavity is shown in
figure 6.1.
These results show a 1.3% bandwidth and 0.26 dB o f insertion loss for the
19 GHz transmit cavity. The 21 GHz receive cavity yielded 1.3% bandwidth and a 0.27
dB insertion loss.
S21
0
-10
-20
CD
-30
-40
-50
19 g h z Channel
2lGHz channel
I
12.5
I
15
17.5
I . . . . I .. II . I . . . . 1______
20
22.5
25
27.5 30
GHz
Figure 6.1. Simulated cavity response.
6.3 Diplexer Design
With the cavity simulations completed, the two cavities were combined into one
HFSS simulation, along with a ‘T’ feed network (see figure 6.2). For proper diplexer
operation, it was important that the lengths o f the transmission lines from the T junction
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84
to each cavity be adjusted to provide an open circuit at the T junction at the resonant
frequency o f the other cavity. Specifically, the length o f the transmission line from the
T-junction to the receive cavity (LI) should be adjusted to present an open circuit at the
T-junction at the resonant frequency o f the transmit cavity (F2).
Similarly, at the
resonant frequency of the receive cavity (FI), the length o f the input line to the transmit
cavity (L2) should be adjusted to provide an open circuit at the T-junction. Neglecting
open-end and cavity loading effects, one would ideally set LI and L2 to be:
Xr
Lx = ~ 2y ~
where J-Grcs1 and
XG
and L 2 = - ^ ~
(14).
( are the guided wavelengths in the Duroid® substrate at the
R e c e iv e
FI j
zz
V 4 l|
.......
Xnput
LI
L2
V4 I
F2 !
T r a n s m it
Figure 6 2 . Diplexer topology.
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85
resonant frequencies o f the transmit and receive cavities, respectively. However, this is
not always possible. Because the physical length of the half wavelength stubs depends
on the relative dielectric constant o f the substrate, it is possible that with high Sr
substrates (which equate to physically short lengths, W 2 ), the cavities beneath the
microstrip will collide ( d o f figure 6.2 will approach 0). When designing the cavity to
achieve low insertion loss, it is important that the coupling slots be located approximately
V* o f the
cavity length from the cavity edge. Because magnetic coupling slots are used, it
is also important to provide an electric short circuit at the center o f the coupling slots.
This is achieved by placing a W Xo stub beyond the center o f the coupling slot [2]. For
physically realizable designs, these two constraints result in an upper limit on the
dielectric constant o f the microstrip substrate.
It can be shown that for physically realizable designs, both cavity resonators must
satisfy:
(15)
'Cavity I
where:
se is the effective dielectric constant o f the microstrip lines,
c
is the speed o f light,
Lcavityi
f resi
is the length o f the first cavity,
and fres 2 are the resonant frequencies o f the first and second cavities
respectively, and
A mm is
the minimum manufacturable distance between the two cavities.
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86
One solution to this problem is to allow LI and L2 to be larger than Xg /2 . Any
length n-Xq/2 will reflect as an open circuit at the T-Junction and should allow proper
operation of the junction. However, for «>1, LI and L2 will reflect open circuits to the
T-junction at frequencies other than the resonant frequency o f the cavity resonators.
Ripples in the response o f the diplexer will result in this case. These ripples can be
severe, and as n gets large, can begin to overlap the cavity resonance, resulting in very
poor performance.
In this design it was found that the cavities would overlap if LI and L2 were set to
Xg i /2
and Xoi/2, respectively, and that setting LI and L2 to Xg i and T^gi (n—2),
respectively, provided an acceptable balance between a non-physical solution (cavity
overlap) and performance. These lengths were then optimized in HFSS to account for
parasitics and open-end effects.
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87
6 .4
F a b ric a tio n
The cavity diplexer was fabricated using standard circuit board processing
techniques on 31 mil thick Duroid® 6010 (8r= 10.8). This circuit board was mounted on
top o f an aluminum support fixture. The cavities for the two filters were machined into
the fixture. The support fixture also provided mounting for SMA coaxial launches that
connected the microstrip circuit to the network analyzer test cables. This fixture is shown
in figure 6.3. The design dimensions for the cavities are shown in TABLE 6-1.
For proper performance o f the diplexer, it was important to maintain the proper
location o f the coupling slots with respect to the cavity walls. In order to accurately align
the aluminum fixture to the circuit board, small holes were machined in the aluminum
fixture containing the cavities. A matched set o f holes was drilled in the Duroid circuit
Figure 6.3. Duroid diplexer measurement fixture.
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88
board using a printed pattern on the board to automatically center the drill bit. The two
pieces were then aligned with a gauge pin and clamped together.
To ensure good
diplexer performance and to minimize losses, 12 screws and a clamp were used to secure
the circuit board to the fixture.
Dimension (refer to figure 4 .1 )
Cavity 1
Cavity 2
18.99GHz
20.99GHz
Cavity Length
17.50mm
15.83mm
Cavity Width
8.85mm
8.01mm
Cavity Height
0.93mm
0.93mm
Top Substrate Thickness
0.635mm
0.635mm
Top Substrate sr
10.8
10.8
Microstrip width
0.56mm
0.56mm
S
0.96mm
0.87mm
SP
4.40mm
3.98mm
SW
3.48mm
3.15mm
SL
0.34mm
0.31mm
fr e s
TABLE 6-1. Diplexer dimensions.
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89
6.5
M e a s u re m e n ts
The assembled diplexer was characterized using an HP8510 network analyzer.
The network analyzer was calibrated using SOLT standards and the S-parameters for the
diplexer were measured. Because the diplexer is a three port device, a 50 Q termination
was used to terminate the third port o f each two port measurement. Additionally, a thru
section o f line was measured to allow both the fixture and line loss o f the diplexer to be
de-embedded. Both the simulated and measured data are shown in figure 6.4 and figure
6.5.
At the channel centers, the diplexer exhibits an insertion loss o f 2.38 dB and
2.89 dB for the transmit and receive channels respectively. The measured isolation was
Meas Channel #1
Meas Channel #2
Sim Channel #1
Sim Channel #2
-10
V.
-20
S
-30
-40
-50
16
18
20
GHz
22
Figure 6.4. Measured and simulated data.
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24
26
90
o
-1 0
-20
* ./
'j
-30
Meas S 1 1
Sim S 1 1
Meas Iso
-40
Sim Iso
16
18
20
22
24
26
GHz
Figure 6.5. Input match & isolation.
better than 24 dB at all frequencies measured. Channel bandwidth measurements show
2.39% and 1.8% bandwidth for the transmit and receive channels, respectively.
A
comparison of the measured and simulated data is shown in TABLE 6-2.
The most significant discrepancy between the measured and simulated data shown
in TABLE 6-2 is in the channel bandwidth data. It is believed that manufacturing and
Measured
Simulated
Ave A
Transmit
Receive
Transmit
Receive
Bandwidth
2.39%
1.80%
1.25%
1.27%
66%
Center Frequency
18.78 GHz
20.73 GHz
19.06 GHz
20.96 GHz
1.3%
Insertion loss
2.38 dB
2.89 dB
1.24 dB
1.43 dB
1.3 dB
TABLE 6-2. Measured and simulated values.
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91
assembly issues such as surface roughness and contact resistance between the a lu m in u m
cavity and the circuit board ground plane reduce the Q o f the resonant cavities, resulting
in wider than expected bandwidths. Improved fabrication could reduce this discrepancy.
Improvements to the process could include a more robust method for attaching the
feedwafer to the cavity fixture.
6 .6
C o n c l u s io n s
Microstrip coupled resonant cavity diplexers can exhibit good performance if
properly designed. Because these diplexers are easy to integrate with microstrip based
circuits, they are well suited for wireless design. A novel Duroid® based single-pole
diplexer has been demonstrated which can pave the way for both fixed and
reconfigurable multi-pole high performance planar diplexers. The simulations o f this
diplexer agree well with the measured results. An improved method o f sealing the feed
board to the cavity fixture is needed.
This problem will be addressed in the silicon
diplexer design discussed in the next chapter.
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92
7 A Si l i c o n M i c r o
7 .1
m a c h in e d
D ip l e x e r
P r o g r e s s io n t o S ilic o n
Silicon processing using silicon micromachining techniques has been used to
develop a number of microwave devices including MEMS RF switches [16] and phase
shifters [19]. Using these techniques it is possible to create three dimensional silicon
features on a silicon wafer. These techniques provide construction methods for miniature
microwave devices that have been historically limited to waveguide scale components.
Additionally, they allow planar features like microstrip lines to be fabricated on silicon.
Through standard photolithography and micromachining techniques, the Duroid® based
diplexer designed in chapter 6 was converted to a silicon design to yield a device with
both reduced size and enhanced performance.
7 .2
S i l i c o n D e s ig n a n d F a b r i c a t i o n
Unlike the Duroid® diplexer design o f chapter 6, the silicon diplexer was
constructed using a stack o f three silicon wafers. The top wafer served as a substrate for
the microstrip feed lines.
In order to minimize microstrip loss, a high resistivity
(p>1000 Q-cm) 400 pm thick silicon wafer was used. The design also included CPW-to-
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93
microstrip transitions to allow for on-wafer probing and measurement of" the operating
characteristics o f the diplexer (as described in chapter 2.2.3). These transitions are not
part o f the diplexer and, thus, do not have to be included in a microstrip-based microwave
system realization. The second and third wafers were low resistivity (p<100£Tcm) 1 mm
thick wafers with a <l-0-0> crystal orientation. These wafers were usedL to define the
resonant cavities and do not support internal fields; therefore, the resistivity o f these
wafers is not critical. The cavities were micromachined in the second ’wafer through
chemical wet etch with tetramethylammonium hydroxide (TMAH)[20]. T h e third wafer
was used to seal the bottom o f the etched cavity (see figure 7.1). The T M A H wet etch
provided an anisotropic etch; and when used on < 1 -0 -0 silicon, resulted im a cavity with
sloped (54.74 degrees) side-walls (see figure 2.7). This presented a problem with respect
to the resonant frequency described by equation (6). The sloping side-walls can perturb
the resonant frequency significantly. If the cavities were designed, however, to maintain
a volume similar to the ideal vertical wall case, then the resonant frequencies can be well
approximated by equation (6). Further optimizations can then be perform ed using threedimensional modeling tools such as HFSS.
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Figure 7.1. Diplexer wafer stack.
54.74
<100> Silicon W afer
' j ‘V
• ' l '1 r ' \ f =
Cavity
Figure 7.2. Anisotropic cavity etch.
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95
In a manner similar to the methods used for the Duroid® diplexer, HFSS was
used to optimize the cavity resonators, feed stubs, and the T-junction. The diplexer was
then fabricated using the micromachining and photolithographic techniques described in
Appendix E. Because the coupling slots were required in the cavity lid, metalized circuit
features were required on both the top and bottom o f the top feed wafer. The coupling
slot features on the bottom o f the top wafer were produced through a lift-off process.
They were aligned to the features on the top o f the wafer through the use o f an MJB-3
mask aligner with infrared capability. This mask aligner was also used to print the cavity
openings on the second wafer. These openings were then replicated in a thick oxide layer
(—0.7 micron) on the cavity wafer. The patterned oxide layer was then used as a mask for
the TMAH etch process. When the TMAH etch process was complete, a bottom wafer
was attached to the cavity wafer with conductive epoxy.
This assembly was then
metalized with gold to a thickness o f approximately 3 microns. Finally, the cavity wafer
was bonded to the feed wafer with conductive epoxy.
The alignment o f these two
structures was performed using an infrared wafer aligner and bonder. A photo o f the
fabricated silicon wafers is shown in figure 7.3. The overall diplexer size is 37 mm x
10.3 mm x 2.5 mm.
In order to measure the quality factor o f the sloped wall cavity
resonators, a separate single cavity with narrow coupling slots was also fabricated on the
same wafer. This test cavity was similar to the high frequency cavity o f the diplexer; it
was created with a 8.85mm wide x 15.83mm long mask opening. Calibration standards
were also fabricated on the top wafer (see figure 7.4).
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96
Figure 7.3. Cavity and feed wafers.
Figure 7.4. Close up o f the top feed wafer.
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97
7 .3
R esu lts
The fabricated diplexer was measured using an HP8510 network analyzer and a
Cascade Microtech probe station with 150pm pitch Picoprobe coplanar wafer probes.
Since the network analyzer can only measure a two-port circuit, the third port o f the
diplexer was always terminated with a 3.5-mm broadband load connected to the probe
station’s third coplanar probe. De-embedding o f the CPW-to-microstrip transitions was
performed using on-wafer thru-reflect-line standards and NIST’s Multical software [10].
The reference planes for the 2-port measurements were located 5.78 mm away from the
CPW-to-microstrip transition.
For insertion loss measurements the diplexer input
reference plane was located right at the T-junction, while the diplexer output reference
planes were located at the center o f the output coupling slots. For the channel-to-channel
isolation measurement the reference planes were located at the centers of the input and
output coupling slots. These reference planes were selected because they encompass
only the diplexer components. They do not include the extra feed transmission line
lengths included in the test circuit that would not be necessary in a real application.
The quality factor, Q , of the resonator was first obtained by measuring the
scattering parameters o f the single Q test cavity (see figure 7.5). To allow for accurate
measurement o f the unloaded Q o f the cavity, Q u , the resonator coupling slots were
designed to provide approximately 20 dB o f insertion loss at the resonant frequency of
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98
the cavity. The Q u was then extracted using the method described in section 4.4.1.
Using this method and the measured data o f figure 7.5 (^ = 2 0 .4 5 GHz, Af3-dB=26 MHz,
S2iR.es—18.6dB) the loaded cavity Q, Q i, was found to be 786.
This resulted in an
external Q, Q& o f 6689 and a n unloaded Q, Qu, o f 890.
-10
-20
^0
-50
-60
20.0
20.2
20.4
20.6
20.8
21.0
Frequency (GHz)
Figure 7.5. Cavity Q measurement
Figure 7.6 and figure 7.7 show the simulated and measured results from the
micromachined diplexer for the receive and transmit channels, respectively. A summary
o f these data is shown in TABLE 7-1. This table indicates that there is a 2.3% shift
between the simulated and measured center channel frequencies o f the diplexer. It was
found that the fabricated cavities were slightly larger than the ones designed.
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99
Measurement o f the cavity sizes after etching indicated a 4.35% increase in the volume o f
both cavities (length / width increase varied from 100 to 400 jam). When this volume
increase is taken into account the agreement between measured and simulated results is
improved (resonant frequencies differ by 0.8% and 0.4% for the transmit and receive
channels, respectively). This is demonstrated by simulations o f the diplexer using the
larger, over-etched cavities (see figure 7.8).
In order to avoid this size increase, a
compensation in the mask design can be implemented based on the TMAH solution and
etch time used. TABLE 7-1 also indicates slightly larger insertion loss for both channels.
These discrepancies are mainly due to the T-junction. The T-junction was optimized for
the nominal cavity dimensions and is therefore non-optimal when used with the overetched (off-frequency) cavities.
These discrepancies could by reduced if the correct
cavity dimensions were fabricated using mask size compensation.
Additionally,
simulations were performed using perfect electric conductor transmission lines.
This
leads to an underestimate o f the circuit losses. Finally, the silver epoxy bonding used to
bond the wafers may contribute to conductor losses at the cavity —cavity lid junction.
Improved bonding techniques could be used to further reduce losses at this junction.
Figure 7.9 shows the simulated and measured results for the cannel-to-channel
isolation. Measurements were taken by terminating the common port (input port o f the
diplexer) with a 50 Q broadband load. The measured isolation is better than 26 dB across
the measured range and agrees well with simulation results. The measured performance
o f the diplexer is summarized in figure 7.10.
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100
o
-10
-20
-30
-40
-50
Measured
Simulated
Measured
Simulated
-60
S11
S11
S21
S21
-70
17
19
21
23
Frequency (GHz)
Figure 7.6. Receive channel data.
0
-10
-20
-30
-40
Measured
Simulated
Simulated
Measured
-50
S11
S11
S31
S31
-60
17
19
21
F req u en cy (GHz)
Figure 7.7. Transmit channel data.
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23
101
o
-10
X
-20
-30
-40
-50
Simulated
M easured
M easured
Simulated
-60
S31
S31
S21
S21
-70
17
23
21
19
F req u en cy (GHz)
Figure 7.8. Simulation o f the over-etched diplexer cavities.
TABLE 7-1. Summary o f the silicon diplexer results.
Simulation
Measurement
Transmit
Channel
Receive
Channel
Transmit
Channel
Receive
Channel
Center Frequency
19.08 GHz
20.94 GHz
18.64 GHz
20.47 GHz
Bandwidth
1.33 %
0.96 %
1.11 %
1.53 %
Insertion Loss
0.6 dB
0.4 dB
1.4 dB
1.0 dB
Isolation
> 2 7 dB
> 26 dB
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102
0
— Measured Isolation
— Simulated Isolation
-2 0
m
T3
-40
-6 0
-80
17
21
19
23
F requency (GHz)
Figure 7.9. Isolation data.
Hv/T
/V
\
/ V/ VN\
\
/ VA
N 4*4$
—
—
-10
i
------ - —
Ch 1
—
—
— Ch 2
'
►
\
>
> s
V
m
____
-20
-30
-40
-50
:
p r . t f t y '#
:
-60
17
18
19
20
Frequency (GHz)
21
Figure 7.10. Summary o f measured data.
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22
23
103
7 .4
C o n c lu s io n s
A silicon-based planar micromachined single-pole cavity diplexer hias been
designed, fabricated and tested. The diplexer exhibited very small insertion lo ss (1.4 dB
and 1.0 dB for the transmit and receive channels respectively), in conjunction with
narrow bandwidth (1.11% and 1.53% for the transmit and receive channels, respectively)
and good channel-to-channel isolation (greater than 26 dB) over the entire m easurem ent
band.
In addition, simulated results using Ansoft’s HFSS agreed w-ell with
measurements. Simple integrated circuit fabrication on common silicon wafers offers the
possibility o f low cost small size / w eight mass produced and easy to integrate diplexers
for a multitude o f applications. This design is a first step towards both a m o re useful
multi-pole micromachined diplexer and an EBG cavity based diplexer. W ith co-mpletion
o f these enhanced diplexers, work on a reconfigurable EBG cavity based dip lex er will be
possible.
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104
8 C o n c l u s io n s
The growth o f the wireless infrastructure has resulted in enormous consumer
demand for more capable, portable and inexpensive wireless devices. High performance
wireless
links for these devices require sophisticated microwave components.
Additionally, because o f local regulatory requirements as well as the desire for individual
devices to perform multiple functions, these systems must operate over multiple
frequency bands. This requirement adds significantly to the cost and complexity o f the
wireless link circuitry. As these trends continue, microwave components that operate
over vastly differing frequency bands will be necessary. These devices will have to be
easy to integrate with existing components, and will have to be low cost.
To develop microwave components that meet these requirements, several new
microwave devices have been designed, constructed and tested. Each o f these devices is
a step towards useful microwave components that are inexpensive, easy to integrate, high
performance, and reconfigurable for operation at different frequency bands. The devices
that have been demonstrated include an electromagnetic band gap free-space
reconfigurable filter. This device was developed to prove that electronically controlled
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105
defects could be used in EBG crystals to electronically reconfigure their transmission
behavior. Using this device, contrast ratios between switching states o f more than 30 dB
were shown. Information learned from this crystal led to the development o f a planar
EBG cavity resonator. This resonator exhibits many desirable properties including an
easy to integrate microstrip compatible topology, inexpensive construction, and quality
factors exceeding 400. Unlike traditional microstrip resonators that have quality factors
around 150 or less, the quality factors o f this EBG resonator can be pushed beyond 600
through the use o f thicker substrate materials. Additionally, the device topology allows
for the inclusion o f reconfigurable elements to the EBG structure. This addition allows
the resonant frequency o f the device to be reconfigured. Resonator frequency shifts o f
more than 20% have been shown.
With the successful development o f a planar, reconfigurable EBG resonator,
significant progress towards a reconfigurable microwave diplexer was made. To this end,
a high performance single-pole diplexer was designed, fabricated and tested.
This
diplexer was implemented on both Duroid® and silicon. The Duroid® device was used
as a test circuit for an improved performance silicon microwave diplexer. This silicon
diplexer demonstrated channel bandwidths less than 1.6%, insertion losses less than
1.5 dB, and channel-to-channel isolation better than 26dB.
This diplexer also
demonstrates significantly narrower channel bandwidths when compared to other, more
difficult to fabricate membrane-based high performance diplexers (1.3% - 1.6% vs. 5%6.5%)[21].
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106
The next step in the development process towards a reconfigurable EBG diplexer
would be the development o f a fixed EBG diplexer. This diplexer would use the fixed
EBG cavity resonators in place o f the fully conducting side wall cavities used in the
Duroid® and silicon diplexers.
This device would then be further enhanced by the
implementation o f multi-pole filters utilizing multiple EBG cavity resonators.
These
multi-pole filters will allow the passband properties of the diplexer, such as passband
ripple, to be chosen during the design stage.
Finally, by replacing the EBG cavity
resonators with reconfigurable EBG cavities, a reconfigurable diplexer can be
constructed. This high performance diplexer will be easy to integrate with other planar
circuits, will be inexpensive to manufacture, and will be reconfigurable allowing for
operation over varying frequency regimes. Future reconfigurable resonators can make
use of multiple switching states to provide more than two configurable states, further
enhancing the usefulness o f this novel device.
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107
A p p e n d i x A . M ic r o s t a t io n L e g o C o d e
This appendix contains code written in Microstation Basic Macro Language. The
software allows TRIX 3D LEGO files to be imported into Microsation for 3D
visualization. The code utilizes Microstation object ‘tags’ to store LEGO file data about
each object (name, color, material etc.).
Once the LEGO file has been imported,
measurements o f the objects described by the LEGO file can be made. The code allows
measurements to be made in both LEGO ‘cell’ units and in meters.
These features
simplify the verification o f the LEGO file input data. The following code should be
implemented with version 05.05.02.23 or later o f Microstation Modeler.
Microstation Macro code to read TRIX 3D input lego files
For visual verification of simulation structures.
Also allows for measurement of objects in cells or
physical dimensions. With proper setup of tags in Microstation
the lego file object names and properties are loaded into tags
associated with the objects.
The user can view these tags to
determine what displayed objects are called in the lego file, and
to determine what properties those objects have.
Modifications
to more gracefully handle extra space at the end of the lego
files is needed, as well as to handle objects that would be used
in non-crystal type simulations.
Like most of my code, it is really poorly commented (if at all) .
Type MyPoint
x as double
y as double
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108
z as double
end type
Type CubeType
Name as string
Type as string
Material as string
Priority as string
Filled as string
StartCord as MyPoint
StopCord as MyPoint
StartTxt as string
StopTxt as string
Orientation as string
end type
Type ProbeType
Name as string
FieldQty as string
PositionCord as Mypoint
PositionTxt as string
StartCord as Mypoint
StopCord as Mypoint
StartTxt as string
StopTxt as string
end type
Type LineSourceType
Name as string
Direction as string
Type as string
Amplitude as string
Phase as string
StartCord as Mypoint
StartTxt as string
StopCord as Mypoint
StopTxt as string
Frequency as string
Envelope as string
end type
Type MaterialType
Name as string
Type as string
Color as string
Epsilon as string
Mu as string
Sigma as string
SigmaStar as string
ColorNum as integer
end type
function getnocomments(filenum as integer) as string
dim temptext as string
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109
line input #filenum, temptext
while left$(temptext,1)="#"
line input ffilenum,temptext
wend
getnocomments=temptext
end function
function drawline(pointl as mypoint, point2 as mypoint) as string
dim p as MbePoint
MbeSendCommand "PLACE LINE CONSTRAINED n
MbeSendCommand "IGEN CONSTRAIN LENGTH LOCK "
MbeSendCommand "IGEN CONSTRAIN LENGTH UNLOCK "
MbeSendCommand "IGEN CONSTRAIN ANGLE UNLOCK "
p.x = pointl.x
p.y = pointl.y
p.z = pointl.z
MbeSendDataPoint p, 1%
p.x = point2.x
p.y = point2.y
p.z = point2.z
MbeSendDataPoint p, 1%
MbeSendReset
drawline="done"
end function
Function GetColorNum(cstring as string,mats() as materialtype)
dim nummats as integer
dim counter as integer
dim tempcolor as integer
nummats=ubound(mats)
tempcolor=9
for counter = 1 to nummats
if ucase? (cstring) =ucase$ (mats (counter) .name) then
tempcolor=mats(counter) .colornum
end if
next counter
GetColorNum=tempcolor
end function
as integer
Function GetPriorityNum(PriorityNames() as string,cstring as string) as integer
Dim counter as integer
dim tempmatch as integer
tempmatch=0
for counter= 1 to ubound(PriorityNames)
if ucase$ (PriorityNames (counter) )=ucase$ (cstring) then
tempmatch=counter
end if
next counter
GetPriorityNum=tempmatch
end function
Sub Main
Dim PriorityNames() as string
Dim status as long
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110
Dim
Dim
Dim
Dim
dim
dim
dim
dim
dim
dim
dim
dim
dim
dim
dim
dim
dim
dim
dim
dim
dim
dim
dim
dim
dim
dim
dim
dim
button as long
text$ as String
filename? as String
finish as String
cubelist () as CubeType
materiallist() as MaterialType
probelist () as ProbeType
linesrclist() as linesourcetype
numbercubes as integer
numbermat as integer
numberprobes as integer
numberlinesrc as integer
counter as integer
point as MbePoint
maxspace as Mypoint
junk as string
origin as Mypoint
temppoint as Mypoint
temppoint2 as Mypoint
numpriorities as integer
deltaxyz as MyPoint
c hoices(1 to 2) as string
temptextS as string
triadlen as double
triadorg as double
arrow as double
singlepiece as integer
retvalue as integer
'much confusion about this origin & the grid
origin.x=0
origin.y=0
origin.z=0
numbercubes=0
numbermat=0
numpriorities=0
numberlinesrc=0
suggest$
filters
directoryS
titleS
filenames
=
=
=
=
=
" '*
" *. *,All files [*.*]"
"c:\winnt\profiles\hillm\desktop\"
"Choosea Lego
File to Open"
""
status = MbeFileOpen (filenames, suggests, filters, directoryS, titleS)
If status <> MBE_Success Then
exit sub
End If
Open filenames for input as #1
finish="false"
while finish=”false"
textS=getnocomments(1)
if LeftS (texts, 10) ="BasicSimul" then finish="true"
Wend
text$=getnocomments(1)
text$=wordS(texts,2,6)
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I ll
maxspace.x=val(word?(text?,1))
maxspace.y=val(word?(text?,2))
maxspace.z=val(word?(text?,3))
text?=getnocomments(1)
text?=Word?(Text?,2,16)
deltaxyz.x#=val(word?(text?,1,2))
deltaxyz.y#=val(word?(text?,3,4))
deltaxyz.z#=val(word?(text?,5, 6) )
choices(1)= ”Cells"
choices(2)="meters"
counter=MbeSelectBox("Select Units”,choices,"Units”)
if counter=l then
deltaxyz.x=l
deltaxyz.y=l
deltaxyz.z=l
end if
'this allows for assembly one primitive at a time, or all at once
choices(1)="Piece at a time”
choices(2)="A11 at once”
counter=MbeSelectBox ("Assemble:”,choices)
singlepiece=0
if counter=l then singlepiece=l
maxspace.x=maxspace.x*deltaxyz.x
maxspace.y=maxspace.y*deltaxyz.y
maxspace.z=maxspace.z*deltaxyz.z
MbeSendCommand "ACTIVE COLOR 40"
MbeSendCommand "ACTIVE STYLE 2"
MbeSendCommand "ACTIVE LEVEL 63”
temppoint=origin
temppoint.x=maxspace.x
junk=drawline (origin, temppoint)
temppoint=origin
temppoint.y=maxspace.y
junk=drawline (origin, temppoint)
temppoint=origin
temppoint.z=maxspace.z
junk=drawline (origin, temppoint)
temppo int=maxspace
temppoint.x=0
junk=drawline (maxspace, temppoint)
temppoint=maxspace
temppoint.y=0
junk=drawline (maxspace, temppoint)
temppoint=maxspace
temppoint.z=0
junk=drawline (maxspace, temppoint)
temppoint.x=maxspace.x
temppoint.y=0
temppoint.z=0
temppoint2.x=maxspace.x
temppoint2.y=0
temppoint2.z=maxspace.z
junk=drawline (temppoint, temppoint2)
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112
temppoint2.x=maxspace.x
temppoint2.y=maxspace.y
temppoint2.z=0
junk=drawline (temppoint, temppoint2)
temppoint.x=0
temppoint.y=maxspace.y
temppoint.z=maxspace.z
temppoint2.x=0
temppoint2.y=0
temppoint2.z=maxspace.z
junk=drawline (temppoint, temppoint2)
temppoint2.x=0
temppoint2.y=maxspace.y
temppoint2.z=0
junk=drawline (temppoint, temppoint2)
temppoint.x=0
temppoint.y=0
temppoint.z=maxspace.z
temppoint2.x=maxspace.x
temppoint2.y=0
temppoint2.z=maxspace.z
junk=drawline (temppoint, temppoint2)
temppoint.x=0
temppoint.y=maxspace.y
temppoint.z=0
temppoint2.x=maxspace.x
temppoint2.y=maxspace.y
temppoint2.z=0
junk=drawline (temppoint, temppoint2)
MbeSendCommand "ACTIVE STYLE 0"
MbeSendCommand "ACTIVE LEVEL 1”
finish="false"
while finish="false"
text$=getnocomments(1)
if Left$(text$,10)="Priorities” then finish="true"
Wend
text$=getnocomments(1)
while lefts(texts,1)<>"0"
numpriorities=numpriorities+l
redim preserve PriorityNames(numpriorities)
PriorityNames(numpriorities)=Word$(texts,1)
text$=getnocomments(1)
wend
finish="false"
while finish="false"
line input #1, texts
if Lefts(textS,9)="Materials" then finish="true"
Wend
text$=getnocomments(1)
while lefts(texts,4)="Name”
numbermat=numbermat+l
redim preserve materiallist(numbermat)
materiallist (numbermat) .Name = wordS (texts, 2, 6)
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113
materiallist (numbermat)
materiallist (numbermat)
materiallist (numbermat)
materiallist (numbermat)
materiallist (numbermat)
materiallist (numbermat)
text$=getnocomments(1)
text$=getnocomments(1)
-Type=word? (getnocomments (1), 2, 6)
-Color=word$ (getnocomments (1) ,2, 6)
-Epsilon=word$ (getnocomments (1) ,2,6)
-Mu=word$ (getnocomments (1) ,2, 6)
.Sigma=word$ (getnocomments (1) ,2,6)
.SigmaStar=word$ (getnocomments (1) ,2, 6)
wend
for counter=l to numbermat
if ucase$ (materiallist (counter) .Color) ="WHITE" then
materiallist(counter).ColorNum=0
elseif ucase?(materiallist (counter)-Color)="BLUE" then
materiallist(counter)-ColorNum=l
elseif ucase?(materiallist(counter)-Color)="GREEN" then
materiallist(counter)-ColorNum=2
elseif ucase$ (materiallist (counter) .Color) ='*RED" then
materiallist(counter).ColorNum=3
elseif ucase$(materiallist (counter)-Color)= ”YELLOW" then
materiallist(counter).ColorNum=4
elseif ucase?(materiallist(counter)-Color)="GOLD" then
materiallist(counter)-ColorNum=4
elseif ucase?(materiallist (counter).Color)="PORPLE" then
materiallist(counter)-ColorNum=5
elseif ucase?(materiallist (counter)-Color)="ORANGE" then
materiallist(counter)-ColorNum=6
elseif ucase?(materiallist (counter).Color)="LIGHTBLUE" then
materiallist(counter).ColorNum=7
else
materiallist(counter)-ColorNum=6
end if
next counter
numbermat=numbermat +1
'add pec, pmc and vaccuum, which are always
predefined
redim preserve materiallist(numbermat+2)
materiallist(numbermat)-Name = "PEC"
materiallist(numbermat)-Type="ISOTROPIC"
materiallist(numbermat).Color="GOLD"
materiallist(numbermat)-ColorNum=4
numbermat=numbermat+1
materiallist (numbermat)-Name = "VACCUOM"
materiallist(numbermat).Type="ISOTROPIC"
materiallist(numbermat).Color="GREY"
materiallist(numbermat)-ColorNum=80
numbermat=numbermat+1
materiallist (numbermat)-Name = "PMC"
materiallist(numbermat).Type="ISOTROPIC"
materiallist(numbermat).Color="GREY"
materiallist(numbermat).ColorNum=80
'now find the start of the primitives section of the lego file
finish= "false"
while finish="false"
line input #1, text?
if Left?(text$,10)="Primitives" then finish="true"
Wend
text$=getnocomments(1)
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114
while left?(text?,4)="Name"
numbercubes=numbercubes+l
redim preserve cubelist (numbercubes)
cubelist(numbercubes).Name = word$(text$,2,6)
cubelist (numbercubes) .Type=word$ (getnocomments (1) ,2, 6)
'cube,
plane etc
cubelist (numbercubes) .Material=word$ (getnocomments (1) ,2, 6)
cubelist (numbercubes) .Priority=word$ (getnocomments (1) ,2, 6)
text?=getnocomments(1)
text?=word?(text?,2, 6)
cubelist (numbercubes) .StartTxt=text$
'get
start point info & substract one to convert
cubelist (numbercubes) .startcord.x=val (word? (text?, 1) )-1
'blocks
to coords
cubelist (numbercubes) .startcord.y=val (word$ (text$,2))-1
cubelist (numbercubes) .startcord. z=val (word? (text?,3))-1
if left$ (ucase? (cubelist (numbercubes) .Type) ,4) ="CUBE" then
'it
is a cube, and has fill next
text$=getnocomments(1)
text?=word?(text$,2,6)
cubelist(numbercubes).StopTxt=text$
cubelist (numbercubes) .stopcord.x=val(word? (text?, 1) )
cubelist (numbercubes) .stopcord.y=val (word? (text?,2) )
cubelist (numbercubes) .stopcord. z=val (word$ (textS, 3) )
cubelist (numbercubes) .filled=word$ (getnocomments (1) ,2, 6)
elseif left? (ucase? (cubelist (numbercubes) .Type), 4) ="PLAN" then 'it
is a plane (no thickness) and has
text?=getnocomments(1)
text?=word?(text?,2,6)
cubelist(numbercubes).StopTxt=text$
cubelist (numbercubes) .stopcord.x=val(word? (text?,l) )
cubelist (numbercubes) .stopcord.y=val (word? (text$,2) )
cubelist (numbercubes) .stopcord. z=val (word? (text$,3) )
cubelist (numbercubes) .orientation=word? (getnocomments (1) ,2, 6)
if left$ (ucase? (cubelist (numbercubes) .orientation), 1) =''X" then
'make plane a little thick (less than 1 grid)
cubelist (numbercubes) .stopcord.x=cubelist (numbercubes) .stopcord.x+0.2*deltaxyz.
x
Elseif left? (ucase? (cubelist (numbercubes) .orientation) ,1) =''Y”
then
cubelist (numbercubes) .stopcord.y=cubelist (numbercubes) .stopcord.y+0.2*deltaxyz.
y
elseif left$ (ucase? (cubelist (numbercubes) .orientation) ,1)="Z"
then
cubelist (numbercubes) .stopcord. z=cubelist (numbercubes) .stopcord. z+0,2*deltaxyz.
z
end if
end if
text$=getnocomments(1)
text$=getnocomments(1)
wend
'fit all views to max space box.
MbeSendCommand "FIT VIEW EXTENDED 2"
MbeSendCommand "FIT VIEW EXTENDED 1"
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115
MbeSendCommand "FIT VIEW EXTENDED 3"
MbeSendCommand "FIT VIEW EXTENDED 4"
for counter= 1 to numbercubes
'set assembly to a piece at a time, if desired
if singlepiece=l then
retvalue=MbeMessageBox("Place Next Piece:
"+cubelist(counter)-Name,MBE_OKCancelBox)
if retvalue=MBE_BUTTON_CANCEL then
singlepiece=0
end if
end if
MbeSendCommand "ACTIVE LEVEL " +
str$ (GetPriorityNum(PriorityNames, cubelist (counter) .priority) )
MbeSendCommand "ACTIVE COLOR " +
Str$ (GetColorNum(cubelist (counter) .material,materiallist) )
MbeSendCommand "PLACE SLAB ICON "
MbeSetAppVariable "3DTOOLS”, "ms3DToolSettings.type", 2&
MbeSetAppVariable "3DTOOLS", "ms 3 DToolSettings. block. axisMode", 0&
MbeSetAppVariable "3DT00LS",
"ms3 DToolSettings.block.length.locked", 0 &
MbeSetAppVariable "3DTOOLS”, "ms3DToolSettings.block.width.locked",
05
MbeSetAppVariable "3DT00LS",
"ms3DToolSettings.block.height.locked", 0£
point.x = cubelist(counter).startcord.x*deltaxyz.x
point.y = cubelist(counter).startcord.y*deltaxyz.y
point.z = cubelist(counter).startcord.z*deltaxyz.z
MbeSendDataPoint point, 0%
point.x = cubelist(counter).stopcord.x*deltaxyz.x
point.y = cubelist(counter).startcord.y*deltaxyz.y
point.z = cubelist(counter).startcord.z*deltaxyz.z
MbeSendDataPoint point, 0%
point.x = cubelist(counter).stopcord.x*deltaxyz.x
point.y = cubelist(counter),stopcord.y*deltaxyz.y
point.z = cubelist(counter).startcord.z*deltaxyz.z
MbeSendDataPoint point, 0%
point.x = cubelist(counter).stopcord.x*deltaxyz.x
point.y = cubelist(counter).stopcord.y*deltaxyz.y
point.z = cubelist(counter).stopcord.z*deltaxyz.z
MbeSendDataPoint point, 0%
MbeSendCommand "Attach Tags "
MbeSendKeyin "TAGJOURNAL ATTACH SET lego"
'MbeSendKeyin "TAGJOURNAL ATTACH SET lego"
'MbeSendKeyin "TAGJOURNAL ATTACH SET lego"
point.x = (cubelist(counter).startcord.x)*deltaxyz.x
point.y = (cubelist(counter).startcord.y)*deltaxyz.y
point.z = (cubelist(counter).startcord.z)*deltaxyz.z
MbeSendDataPoint point, 0%
MbeSendDataPoint point, 0%
MbeSendKeyin "TAGJOURNAL ATTACH TAG name"
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116
MbeSendKeyin "TAGJOURNAL
MbeSendKeyin "TAGJOURNAL
MbeSendKeyin "TAGJOURNAL
MbeSendKeyin "TAGJOURNAL
cubelist(counter).Material
MbeSendKeyin "TAGJOURNAL
cubelist(counter).Material
MbeSendKeyin "TAGJOURNAL
MbeSendKeyin "TAGJOURNAL
MbeSendKeyin "TAGJOURNAL
MbeSendKeyin "TAGJOURNAL
MbeSendKeyin "TAGJOURNAL
cubelist(counter).priority
MbeSendKeyin "TAGJOURNAL
cubelist(counter).priority
MbeSendKeyin "TAGJOURNAL
MbeSendKeyin "TAGJOURNAL
cubelist(counter).starttxt
MbeSendKeyin "TAGJOURNAL
cubelist(counter).starttxt
MbeSendKeyin "TAGJOURNAL
MbeSendKeyin "TAGJOURNAL
MbeSendKeyin "TAGJOURNAL
ATTACH VALUE " + cubelist(counter).Name
ATTACH VALUE ” + cubelist(counter).Name
ATTACH TAG material"
ATTACH VALUE " +
ATTACH VALUE " +
ATTACH TAG filled"
ATTACH VALUE " + cubelist(counter) .filled
ATTACH VALUE ” + cubelist(counter) .filled
ATTACH TAG priority"
ATTACH VALUE " +ATTACH VALUE " +
ATTACH TAG start"
ATTACH VALUE " +ATTACH VALUE " +
ATTACH TAG stop"
ATTACH VALUE " + cubelist(counter) .stoptxt
ATTACH VALUE " + cubelist (counter) .stoptxt
MbeSendCommand "MBEl CLOSEMODAL OK"
MbeSendDataPoint point,0%
next counter
finish= "false"
while finish="false"
line input #1, text?
text$=ucase$(Left$(text$,11))
if text$="FIELDPROBES" or text?="LINESOURCES" then finish=*'true"
Wend
if text$="LINESOURCES" then
' process line source elements
text?=getnocomments(1)
numprobes=0
MbeSendCommand "ACTIVE COLOR 62"
MbeSendCommand "ACTIVE LEVEL 62"
'source / probe level
while ucase?(left?(text?,4))=”NAME"
numberlinesrc=numberlinesrc+l
redim preserve linesrclist(numberlinesrc)
linesrclist(numberlinesrc).name=Word?(text?,2,6)
linesrclist(numberlinesrc).direction=Word$(getnocomments(1),2,6)
linesrclist (numberlinesrc) .type=Word? (getnocomments (1) ,2, 6)
linesrclist (numberlinesrc) .amplitude=Word? (getnocomments (1) ,2, 6)
linesrclist (numberlinesrc) .phase=Word? (getnocomments (1) ,2,6)
text?=getnocomments(1)
text?=word?(text?, 2,6)
linesrclist(numberlinesrc).starttxt=text?
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117
linesrclist (numberlinesrc) .startcord.x=val(word$ (text?, 1)) *deltaxyz.x
linesrclist (numberlinesrc) .startcord. y=val(word? (text$, 2) )*deltaxyz. y
linesrclist (numberlinesrc) .startcord.z=val(word? (text?, 3) )‘deltaxyz.z
text$=getnoconanents(1)
text?=Word?(text?,2,6)
linesrclist (numberlinesrc) .stoptxt=text$
linesrclist (numberlinesrc) .stopcord.x=(val (word? (text?, 1))) *deltaxyz.x
linesrclist (numberlinesrc) .stopcord.y=(val (word? (text?, 2)) ) *deltaxyz.y
linesrclist (numberlinesrc) .stopcord. z= (val (word? (text?, 3) )) ‘deltaxyz.z
linesrclist (numberlinesrc) .frequency=Word? (getnocomments (1) ,2,6)
linesrclist (numberlinesrc) .envelope=Word? (getnocomments (1) ,2, 6)
'add offset to place cylinder in middle of cell
if ucase? (linesrclist (numberlinesrc) .direction) = ”X" then
linesrclist (numberlinesrc) .startcord. y=linesrclist (numberlinesrc) .startcord. y0.5 *deltaxyz.y
linesrclist (numberlinesrc) .startcord. z=linesrclist (numberlinesrc) .startcord. z0.5 *deltaxyz.z
linesrclist (numberlinesrc) .stopcord. y=linesrclist (numberlinesrc) .stopcord. y0.5*deltaxyz.y
linesrclist (numberlinesrc) .stopcord. z=linesrclist (numberlinesrc) .stopcord. z0.5‘deltaxyz.z
elseif ucase? (linesrclist (numberlinesrc) .direction) ="Y" then
linesrclist (numberlinesrc) .startcord.x=linesrclist (numberlinesrc) .startcord. x0.5‘deltaxyz.x
linesrclist (numberlinesrc) .startcord. z=linesrclist (numberlinesrc) .startcord. z0.5‘deltaxyz.z
linesrclist (numberlinesrc) .stopcord.x=linesrclist (numberlinesrc) .stopcord.x0.5‘deltaxyz.x
linesrclist (numberlinesrc) .stopcord. z=linesrclist (numberlinesrc) .stopcord. z0.5‘deltaxyz.z
elseif ucase? (linesrclist (numberlinesrc) .direction) ="Z" then
linesrclist (numberlinesrc) .startcord. x=linesrelist (numberlinesrc) .startcord. x0.5‘deltaxyz.x
linesrclist (numberlinesrc) .startcord. y=linesrclist (numberlinesrc) .startcord. y0.5‘deltaxyz.y
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118
linesrclist (numberlinesrc) .stopcord.x=linesrclist (numberlinesrc) .stopcord.x0.5*deltaxyz.x
linesrclist(numberlinesrc).stopcord.y=linesrclist(numberlinesrc).stopcord.y0.5*deltaxyz.y
end if
MbeSendCommand "PLACE CYLINDER ICON "
MbeSetAppVariable "3DTOOLS",
"ms3DToolSettings.cylinder.radius.locked", -1&
MbeSetScaledAppVar "3DT00LS",
"ms3DToolSettings.cylinder.radius.value", l*deltaxyz.x
point.x = linesrclist (numberlinesrc) .startcord.x
point.y = linesrclist (numberlinesrc)-startcord.y
point.z = linesrclist(numberlinesrc).startcord.z
MbeSendDataPoint point
point.x = linesrclist (numberlinesrc) .stopcord.x
point.y = linesrclist (numberlinesrc) .stopcord.y
point, z = linesrclist (numberlinesrc) .stopcord. z
MbeSendDataPoint point
MbeSendCommand "Attach Tags "
MbeSendKeyin "TAGJOURNAL ATTACH SET linesrc"
MbeSendKeyin "TAGJOURNAL ATTACH SET linesrc"
MbeSendKeyin "TAGJOURNAL ATTACH SET linesrc"
point.x = linesrclist (numberlinesrc) .startcord.x
point.y = linesrclist (numberlinesrc) .startcord.y
point, z = linesrclist (numberlinesrc) .startcord. z
MbeSendDataPoint point
MbeSendDataPoint point
MbeSendKeyin "TAGJOURNAL
MbeSendKeyin "TAGJOURNAL
linesrclist (numberlinesrc) .name
MbeSendKeyin "TAGJOURNAL
linesrclist(numberlinesrc).name
MbeSendKeyin "TAGJOURNAL
MbeSendKeyin "TAGJOURNAL
linesrclist (numberlinesrc) .type
MbeSendKeyin "TAGJOURNAL
linesrclist(numberlinesrc).type
MbeSendKeyin "TAGJOURNAL
MbeSendKeyin "TAGJOURNAL
linesrclist(numberlinesrc).amplitude
MbeSendKeyin "TAGJOURNAL
linesrclist(numberlinesrc).amplitude
MbeSendKeyin "TAGJOURNAL
MbeSendKeyin "TAGJOURNAL
linesrclist(numberlinesrc).phase
MbeSendKeyin "TAGJOURNAL
linesrclist(numberlinesrc).phase
MbeSendKeyin "TAGJOURNAL
MbeSendKeyin "TAGJOURNAL
linesrclist(numberlinesrc).starttxt
MbeSendKeyin "TAGJOURNAL
linesrclist(numberlinesrc).starttxt
ATTACH TAG name"
ATTACH VALUE " +
ATTACH VALUE " +
ATTACH TAG type"
ATTACH VALUE " +
ATTACH VALUE " +
ATTACH TAG amplitude"
ATTACH VALUE " +
ATTACH VALUE " +
ATTACH TAG phase”
ATTACH VALUE " +
ATTACH VALUE " +
ATTACH TAG start"
ATTACH VALUE " +
ATTACH VALUE " +
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
119
MbeSendKeyin "TAGJOURNAL ATTACH
MbeSendKeyin "TAGJOURNAL ATTACH
linesrclist(numberlinesrc).stoptxt
MbeSendKeyin "TAGJOURNAL ATTACH
linesrclist(numberlinesrc).stoptxt
MbeSendKeyin "TAGJOURNAL ATTACH
MbeSendKeyin "TAGJOURNAL ATTACH
linesrclist(numberlinesrc).frequency
MbeSendKeyin "TAGJOURNAL ATTACH
linesrclist(numberlinesrc).frequency
MbeSendKeyin "TAGJOURNAL ATTACH
MbeSendKeyin "TAGJOURNAL ATTACH
linesrclist(numberlinesrc).envelope
MbeSendKeyin "TAGJOURNAL ATTACH
linesrclist(numberlinesrc).envelope
MbeSendCommand "MBE1 CLOSEMODAL
MbeSendDataPoint point
TAG stop”
VALUE " +
VALUE " +
TAG frequency"
VALUE " +
VALUE " +
TAG envelope"
VALUE " +
VALUE " +
OK"
finish="false"
while finish="false"
'continue until 0 is reached
line input #1, text?
text?=ucase?(Left?(text?, 11))
if text?="0" then finish="true"
Wend
line input #1, text?
wend
end if 'end if linesources section
if text?<>"FIELDPROBES" then
finish= "false"
while finish="false”
line input #1, text?
text?=ucase?(Left?(text?, 11))
if text?="FIELDPROBES" then finish="true"
probe section
Wend
end if
'find the field
'process field probes
text?=getnocomments(1)
numprobes=0
MbeSendCommand "ACTIVE COLOR 31"
MbeSendCommand "ACTIVE LEVEL 62"
while ucase?(left?(text?,8))="FILENAME"
numprobes=numprobes+l
redim preserve probelist(numprobes)
probelist(numprobes).name=Word?(text?,2,6)
probelist(numprobes).fieldqty=Word?(getnocomments(1),2, 6)
text?=getnocomments(1)
if ucase?(word?(text?,1))="POSITION" then
text?=word?(text?,2,6)
probelist(numprobes).positiontxt=text?
probelist(numprobes).positioncord.x=val(word?(text?,1))*deltaxyz.x
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
probelist (numprobes) .positioncord. y=val (word$ (text$, 2) )*deltaxyz. y
probelist (numprobes) .positioncord. z=val (word$ (text$, 3) )‘deltaxyz. z
MbeSendCommand "ACTIVE COLOR 31"
MbeSendCommand "ACTIVE LEVEL 62"
MbeSendCommand "PLACE SPHERE ICON "
MbeSetAppVariable "3DTOOLS",
”ms3DToolSettings.parametricSolid”, 0&
MbeSetAppVariable "3DTOOLS",
"ms3DToolSettings.sphere.radius.locked” , -1&
MbeSetScaledAppVar "3DTOOLS",
"ms3DToolSettings .sphere, radius .value”, l*deltaxyz .x
point.x = probelist (numprobes) .positioncord.x
point.y = probelist (numprobes) .positioncord.y
point, z = probelist (numprobes) .positioncord. z
MbeSendDataPoint point, 2%
point.x = probelist (numprobes) .positioncord.x*2
point.y = probelist (numprobes) .positioncord. y*2
point, z = probelist (numprobes) .positioncord. z*2
MbeSendDataPoint point, 2%
MbeSendCommand "Attach Tags "
MbeSendKeyin "TAGJOURNAL ATTACH SET probe"
MbeSendKeyin "TAGJOURNAL ATTACH SET probe"
MbeSendKeyin "TAGJOURNAL ATTACH SET probe"
point.x = probelist (numprobes) .positioncord.x
point.y = probelist (numprobes) .positioncord. y
point, z = probelist (numprobes) .positioncord. z
MbeSendDataPoint point
MbeSendDataPoint point
MbeSendKeyin "TAGJOURNAL ATTACH TAG filename"
MbeSendKeyin "TAGJOURNAL ATTACH VALUE ” +
probelist(numprobes).name
MbeSendKeyin "TAGJOURNAL ATTACH VALUE ” +
probelist(numprobes).name
MbeSendKeyin "TAGJOURNAL ATTACH TAG fieldqty"
MbeSendKeyin "TAGJOURNAL ATTACH VALUE " +
probelist(numprobes).fieldqty
MbeSendKeyin "TAGJOURNAL ATTACH VALUE " +
probelist(numprobes).fieldqty
MbeSendKeyin "TAGJOURNAL ATTACH TAG position"
MbeSendKeyin "TAGJOURNAL ATTACH VALUE " +
probelist(numprobes).positiontxt
MbeSendKeyin "TAGJOURNAL ATTACH VALUE " +
probelist(numprobes).positiontxt
MbeSendCommand "MBE1 CLOSEMODAL OK"
MbeSendDataPoint point
elseif ucase$(word?(texts,1))="START" then
text?=word?(text?,2,6)
probelist (numprobes) .starttxt=text?
probelist (numprobes) .startcord.x=val (word? (text?, 1) ) ‘deltaxyz
probelist (numprobes) .startcord.y=val (word? (text?, 2) )‘deltaxyz
probelist (numprobes) .startcord.z=val (word? (text?, 3) )‘deltaxyz
text?=getnocomments(1)
text?=Word?(text?,2,6)
probelist (numprobes) .stoptxt=text?
probelist (numprobes) .stopcord.x= (val (word? (text?, 1) ) )‘deltaxyz.x
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
121
probelist (numprobes) .stopcord.y=(val (word? (text?,2) ) ) *deltaxyz.y
probelist (numprobes) .stopcord.z=(val (word? (text?,3) ) ) *deltaxyz.z
•add offset to place cylinder in middle of cell
if right? (ucase? (probelist (numprobes) .fieldqty) ,1) = ”X" then
probelist (numprobes) .startcord.y=probelist (numprobes) .startcord.y0.5*deltaxyz.y
probelist (numprobes) .startcord. z=probelist (numprobes) .startcord. z0.5 *deltaxyz.z
probelist (numprobes) .stopcord.y=probelist (numprobes) .stopcord. y—0. 5*deltaxyz. y
probelist(numprobes).stopcord. z=probelist(numprobes) .stopcord.z-0.5*deltaxyz. z
elseif right?(ucase?(probelist(numprobes).fieldqty),1)="Y" then
probelist (numprobes) .startcord.x=probelist (numprobes) .startcord.x0.5 *deltaxyz.x
probelist (numprobes) .startcord. z=probelist (numprobes) .startcord. z0.5*deltaxyz.z
probelist (numprobes) .stopcord.x=probelist (numprobes) .stopcord.x-0 .5*deltaxyz.x
probelist (numprobes) .stopcord. z=probelist (numprobes) .stopcord. z-0.5*deltaxyz.z
elseif right? (ucase? (probelist (numprobes) .fieldqty) ,1) ="Z" then
probelist (numprobes) .startcord.x=probelist (numprobes) .startcord.x0.5 *deltaxyz.x
probelist (numprobes) .startcord. y=probelist (numprobes) .startcord.y—
0.5*deltaxyz.y
probelist (numprobes) .stopcord.x=probelist (numprobes) .stopcord.x-0.5*deltaxyz .x
probelist (numprobes) .stopcord.y=probelist (numberlinesrc) .stopcord. y0.5*deltaxyz.y
end if
MbeSendCommand "PLACE CYLINDER ICON "
MbeSetAppVariable "3DTOOLS",
"ms3DToolSettings.cylinder, radius.locked", -1&
MbeSetScaledAppVar "3DTOOLS”,
"ms3DToolSettings.cylinder, radius .value", l*deltaxyz .x
point.x = probelist(numprobes).startcord. x
point.y = probelist(numprobes).startcord.y
point.z = probelist (numprobes) .startcord. z
MbeSendDataPoint point
point.x = probelist(numprobes).stopcord. x
point.y = probelist(numprobes) .stopcord.y
point.z = probelist(numprobes).stopcord. z
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
122
MbeSendDataPoint point
point.x = probelist(numprobes).startcord.x
point.y = probelist(numprobes).startcord.y
point.z = probelist(numprobes).startcord.z
MbeSendTentPoint point
MbeSendDataPoint point
MbeSendDataPoint point
MbeSendCommand "Attach Tags "
MbeSendKeyin "TAGJOURNAL ATTACH SET probe"
MbeSendKeyin "TAGJOURNAL ATTACH SET probe"
MbeSendKeyin "TAGJOURNAL ATTACH SET probe"
MbeSendDataPoint point
MbeSendDataPoint point
MbeSendKeyin "TAGJOURNAL ATTACH
MbeSendKeyin "TAGJOURNAL ATTACH
probelist (numprobes).name
MbeSendKeyin "TAGJOURNAL ATTACH
probelist(numprobes).name
MbeSendKeyin "TAGJOURNAL ATTACH
MbeSendKeyin "TAGJOURNAL ATTACH
probelist (numprobes).fieldqty
MbeSendKeyin "TAGJOURNAL ATTACH
probelist(numprobes).fieldqty
MbeSendKeyin "TAGJOURNAL ATTACH
MbeSendKeyin "TAGJOURNAL ATTACH
probelist (numprobes) .starttxt
MbeSendKeyin "TAGJOURNAL ATTACH
probelist (numprobes).starttxt
MbeSendKeyin "TAGJOURNAL ATTACH
MbeSendKeyin "TAGJOURNAL ATTACH
probelist (numprobes).stoptxt
MbeSendKeyin "TAGJOURNAL ATTACH
probelist (numprobes).stoptxt
MbeSendCommand "MBE1 CLOSEMODAL
MbeSendDataPoint point
TAG filename"
VALUE " +•
VALUE " +
TAG fieldqty"
VALUE " +
VALUE " +
TAG start"
VALUE " +
VALUE " +
TAG stop"
VALUE " +
VALUE " +
OK"
end if
text$=getnocomments(1)
text$=getnocornments (1)
wend
close #1
'draw axes marks
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
123
MbeSendCommand "ACTIVE COLOR 2"
MbeSendCommand "ACTIVE LEVEL 63"
triadorg=-0.20* (maxspace.x+itaxspace.y)/2
triadlen=0.25* (Maxspace.x+maxspace.y+maxspace.z)/3
arrow=0.10*triadlen
MbeSendCommand "PLACE LINE CONSTRAINED "
point.x = triadorg
point.y = triadorg
point.z = 0
MbeSendDataPoint point, 1%
point.x = triadlen
point.y = triadorg
point.z = 0
MbeSendDataPoint point, 1%
point.x=triadlen-arrow
point.y=triadorg-0.5*arrow
point.z=0
MbeSendDataPoint point, 1%
point. y=triadorg+0.5*arrow
MbeSendDataPoint point, 1%
point.x=triadlen
point.y=triadorg
MbeSendDataPoint point, 1%
MbeSendReset
MbeSendCommand "PLACE DIALOGTEXT ICON "
MbeSendAppMessage "TEXTEDIT", "FirstLine X"
MbeSetScaledAppVar "", "tcb->chheight", 1.8*arrow
MbeSetScaledAppVar "", "tcb->chwidth", 1.8*arrow
point.x = 1.2*triadlen
point.y = triadorg
point.z = 0
MbeSendDataPoint point, 1%
MbeSendCommand "PLACE LINE CONSTRAINED "
point.x = triadorg
point.y = triadorg
point.z = 0
MbeSendDataPoint point, 1%
point.x = triadorg
point.y = triadlen
point.z = 0
MbeSendDataPoint point, 1%
point.x=triadorg+0.5*arrow
point.y=triadlen-arrow
point.z=0
MbeSendDataPoint point, 1%
point.x=triadorg-0.5*arrow
MbeSendDataPoint point, 1%
point.x=triadorg
point.y=triadlen
MbeSendDataPoint point, 1%
MbeSendReset
MbeSendCommand "PLACE DIALOGTEXT ICON "
MbeSendAppMessage "TEXTEDIT", "FirstLine Y"
MbeSetScaledAppVar "", "tcb->chheight", 1.8*arrow
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
124
MbeSetScaledAppVar "", "tcb->chwidth", 1.8*arrow
point, y = 1. 2* triadlen.
point.x = triadorg
point.z = 0
MbeSendDataPoint point, 1%
MbeSendCommand "PLACE LINE CONSTRAINED ”
point.x = triadorg
point.y = triadorg
point.z = 0
MbeSendDataPoint point, 1%
point.x = triadorg
point.y = triadorg
point.z = triadlen
MbeSendDataPoint point, 1%
MbeSendDataPoint point, 1%
point.x=triadorg+0.5*arrow
point.z=triadlen-arrow
point.y=triadorg
MbeSendDataPoint point, 1%
point.x=triadorg-0.5*arrow
MbeSendDataPoint point, 1%
point.x=triadorg
point.z=triadlen
MbeSendDataPoint point, 1%
MbeSendReset
MbeSendConnnand "PLACE DIALOGTEXT ICON ”
MbeSendAppMessage "TEXTEDIT", "FirstLine Z"
MbeSetScaledAppVar
"tcb->chheight", 1.8*arrow
MbeSetScaledAppVar
”tcb->chwidth", 1.8*arrow
point.z = 1.2*triadlen
point.y = triadorg
point.x = triadorg
MbeSendDataPoint point, 3%
MbeSendReset
MbeSendCommand "MBE1 CLOSEMODAL OK"
MbeSendReset
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
125
A p p e n d ix B. P a d e A p p r o x i m a t i o n in M a t h e m a t i c a
This appendix contains code written for Wolfram’s mathematics processing
package Mathematica®. The code implements two functions. One function is used to
determine the Pade approximation coefficients given a data set containing frequency —
complex data pairs. The other function uses these coefficients to interpolate the complex
data at a desired frequency (presumably a frequency point not in the original data series).
The code should be implemented using Mathematica version 4.0 or later.
Define function to create Pade coefficients
Useage: CreatePade Coefls [MaxFrequency.Data Set]
W here MaxFrequency is approximately the highest frequency data point to be used in generating coefls.
DataSet consists of {{Frequency_l, Data(conqilex)_l},{F2,D2}I...1{Fn,Dn}}
Returns: {List of A Coefis,List of B Coefls .Number of FFT paints used,{Freq Scaling Info}}
Define function to interpolate data using generated Pade coefficients
Useage: PadeInterp[Frequency,CoeflList]
W here Frequency is the frequency of interest
CoeflList is the list returned from the Create Pade Coefls function
Returns: {Frequency,Data(canq>]ex)}
H e e d s [" L in e a r A lg e b r a ' M a tr i ^ M a n i p u l a t i o n '" ] ;
Note: all data used in the interpolation function should have accuracy set with
SetAccruacy[number, 128] .
This includes frequency input data. Otherwise the matrix inversion will be
performed with machine precision numbers, which are often not accurate enough
for proper inversion.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
126
CniteradeCsBUi[Knll«urie^_, DataSet_] : - Block[( ),
E ln lla d a [ f r e ^ , I n t J
rm
Block[{mJ, For [ a - 1, d n t | i | | l | < f r a t ,
p h ^ n .> J T » ^
(i,d (e tM )];
I];
Data2TT • S e t t e e «JLa e j [DataSet, 1 2 1 ] :
MrnJreg » n i T a t a p i t f r e t , BataZER]I2, 11:
HiaFre* - DataZITTIl, 11;
M K i O S R l o l i t i - Fladladex[Kajrre?, D iU O R K ll;
It[Ewrt[lalirtOinPiiiit»]t M il lOgTTPoiata - M eiOSRIalita *1]
t h m C a e t a * (MwrOSinaliti-1);
FrcqScaleiPata - Table [(GetScaledFreq[PataaFTla, l | ] , t a t i 3 n | a w 2]), (a, 1, HwtierflfFFTPolals>] :
WKatrix . Table [FresScalnSatalK, 21 »FrpqSr«l«ia>afllf, H7, {K, n , KufeertJfFFTPaiatx}, ( r , 1 , KvaCoef* / 2}];
U t a t x l x » Table [-FrcQScaletBatafM, l l 7"1, ( X , 1, M e i O t l l l P o l i t a ) , (P, 1, 1 * X m C o e tM / Z>]:
IppeatKoaa pBMatrlx, Witatrix]:
Zero - Table[{l), (P, 1, ■ ■ b e iO R T Iiiiiti)];
OaeZero - Table[XI[P .. • , 1,
I],
(2, t, R^irrOgTTPolata)];
U S fa trlx a 4 p a d C o lm [ ( 0 n Z e r o ) , lppeadRn*v{Zero, lppexRmaDSMatrix, W ta trix ]]] ;
RHSMatrlx-Table[(If[s» ■, 1, FreqScaleAatafg, 21]), ( ; , I , l a t e r O R n o l i t t ) ] ;
SolvedCoefta • L iieirS aln[U tatatxix, D EX ttrix];
BetaCoeffs - Table [SolvedCoeffaM, ( ( , 2, 1 * B T n e le /2)1:
UpfcaCoeff* • Table[SolvedCoeffslgf, ( 9, 2 +lhuCoefe/2, Ktm C o e tm * I}];
Ret«ra[(llphaCoetf>, BetaCoeffa, RatfierOlRTPaiats, (KaxDataFrea, atLxFreq))]:
Padelaterp [Fre«aeacr_, Coet*_] :« Block[{ },
KaxFrapfz . Coef«I«,
If;
KiaFreq - Coefa H , 21:
UpbaCoeffa - Coefa(lB;
BetaCoeffs - Coefa|21;
( 2 » r - Qtaxfre^iz - MlaTregl) _
CetScale«greg[x_] :«
KaxTretfd ♦ XUfre«
£•«££•]
IatexpData[Fxeq_] :
ta>9Tfa[B«t»Co«tf»]
UpkaCoeffafa, H .F req * 1
GetIaterpDataPoiat[Freq_] : » IxterpData[GetScale«*‘reqlTre«J];
Return [GetlaterpDataPoiat [Freqaeacp] ]:
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
BetaCoeffsBC, 11 •P ie t1 ;
127
A p p e n d ix C .
PCB B o a r d F a b r i c a t i o n
This appendix contains processing instructions for the fabrication o f printed
circuit boards.
Various substrate materials can be processed using these methods
(Duroids, Epoxy resin ‘FR-4’ type, TMM materials etc.). Many o f the steps in these
procedures require practice and careful execution in order to produce good results. W ith
the exception o f board cutting, drilling and soldering, all steps should be performed in the
clean room wet bench area.
Single Sided Board (see process steps below):
• P re p a re B oard
• P erfo rm Photolithography - If a metal ground plane on the back side of the board is
required, cover the back o f the board with plastic tape. This will prevent the etch solution
from reaching the copper on the back o f the board. Be sure that the tape coverage is
complete or the etch solution will bleed under the tape and etch the board. Also be
careful not to scratch or touch the front o f the board while applying the tape - you could
easily scratch the photoresist and ruin your board. I f you do not want the metal on the
back-side o f the board, move on to the etch step.
• E tch copper
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
128
• Strip the photoresist.
Double Sided Board:
• Prepare the board.
• Perform photolithography on the front side - Carefully apply tape to the back-side of
the board (just as in the single sided, ground-backed case) to protect the copper on the
back side o f your board.
• Etch the board.
• Rinse and dry the board. Remove the tape from the back.
• Perform photolithography on the back-side of the board - A hole drilled in the
board can be used to align the front and back masks to the board. First print the front
side, drill the alignment hole(s), then pattern the back-side using the hole(s) (and patterns
on your mask) to align the masks visually.
• Place tape on the front of the board to prevent etching of the front surface.
• Etch the board
• Rinse, dry and remove the tape. It is important that all the tape glue be removed
before placing the board into the stripper. If there is any tape ‘glue’ left, the stripper will
discolor your board.
• Strip the photoresist.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
129
Processes:
Board Preperation
1. Trim the board material to a reasonable size —approximately Vi inch larger
than the circuit to be printed. If the substrate is soft (e.g. Duroid®), this can be
done easily on a paper cutter.
2. Wipe the substrate clean before entering the clean room.
3. After entering the clean room, be sure to remove the plastic protective sheet
from each side o f the substrate (if it exists).
4. Dust off the substrate with the nitrogen gun. I f necessary, the board can be
cleaned with IPA or acetone. Some substrates may be damaged by acetone, but
most are not if they are cleaned quickly.
Try not to touch the surface o f the board after you have cleaned it —handle it by the edges
only.
Photolithography
1. Attach the board to the spinner. If the board is small and not bent, the vacuum
chuck may be strong enough to hold the board. Otherwise it may be necessary to
tape the board to the chuck. This can be done by removing the chuck from the
spinner axle and taping the board to the chuck. Try to center the chuck on the
board as much as possible. The tape should only be on the back side of the board
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
130
- do not let it go around the edge to the front o f the board. The chuck should be
smaller than the board and should not stick out beyond the edges o f your board.
2. Set the spinner to about 2500 rpm. The spin time should be about 30 seconds.
Using a pipette, apply the photoresist (AZ1915, a positive resist — dark mask
locations result in metal left on the board) to the board as soon as you start the
spinner. This should be done quickly and smoothly. When the spinner stops,
check to see if the coating looks uniform. If not, remove the photoresist with
acetone (spin on the acetone with the spinner running), and reapply photoresist.
3. After coating the substrate, place it on the hotplate for 1 m inute at 110°C. It
helps to elevate the board slightly by using two or four glass slides for supports.
The slides should be placed near the edges o f the board so that only the edges of
the board touch the slides and so that the board itself does not touch the hotplate.
4. Remove the board from the hotplate and let it cool for a minute. Place the
board on a piece o f glass (there should be some in the clean room ~5 inches
square or so). It is a good idea to tape one comer o f the board to the glass. Place
the mask on the board, EMULSION SIDE DOWN. The emulsion side of the
mask is the 'dull' side. Look carefully at a dark portion o f the m ask - one side will
be glossy and the other side will be slightly dull.
Center your design on the
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
131
circuit board. To maintain alignment, it is a good idea to tape the mask to the
glass. Make sure the tape is not placed over the circuit board, i.e. you would like
the glass —board —mask ‘stack’ to be as smooth as possible (which is why the
board should be taped very carefully).
5. Take the stack to the exposure box. Place the stack mask-side down on the
glass. Close the lid and turn on the vacuum pump. After 10 or 15 seconds turn on
the timer. Use an external clock (the timer has poor resolution) to expose the
stack for 1 minute.
6. Remove the stack from the exposure box. Carefully remove the mask, tape,
and glass. Place the exposed board in AZ300 developer for 30 seconds, rocking
the container continuously to circulate the developer. After developing, quickly
place the board in a beaker o f water for 30-40 seconds to stop the development
process. The circuit pattern should be clearly visible. Be careful when handling
the board — it is very easy to scratch the photoresist. Dry the board with the
nitrogen gun.
Copper Etching
1. Pour approximately V* inch o f copper etch solution into a flat plastic etch pan.
Add about 100ml o f hot water —the solution etches faster if it is warm. Place the
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
132
board to be etched into the solution.
Be careful when doing this - if the
photoresist gets scratched, your board may be ruined. It will take 10-25 minutes
to etch the board. Occasionally stirring the solution by rocking the pan or by
‘swishing’ the board accelerates the process. If desired, the solution can be kept
warm by setting a beaker o f hot water in the pan. This allows the solution to be
warmed without further dilution.
2. When etching is complete, the board should be rinsed for several minutes in
the sink or cascade rinser.
Photoresist Stripping
1. Place about V* inch o f photoresist stripper (PR2000) in a pyrex container large
enough for your board. Heat the solution on the hotplate until it reaches about
80°C. If the stripper begins to ‘smoke’, you should turn down the hotplate (the
temperature is not critical, but you do not want the stripper to boil off). Place the
board in the hot stripper for about 1 minute. Remove the board and rinse it for
several minutes.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
133
A p p e n d ix D . P l a t e d T h r u -H o l e F a b r ic a t io n
This appendix contains instructions for producing plated vias in printed circuit
boards. Almost any board material can be used, provided that a method for drilling the
vias can be found (e.g. ceramic materials can be used if an appropriate drilling m ethod is
found). To achieve good results, these processing steps require some practice. For this
reason test vias should be fabricated on a spare board before the procedure is used on an
actual circuit.
C o p p er P lating
Copper plated vias can be created with the copper plating bubbler set-up. First
the vias must be drilled. Vias as small as 15 or 20 mils can be made, but larger (31 mil)
vias are easier. For proper plating, all surfaces to be plated must be conductive and
electrically connected to a power supply. Because o f this requirement, it may be easier
(depending on the circuit layout) to plate holes before performing the lithography to
create the circuit traces. This does present an additional alignment step to properly align
the vias to the circuit mask. Conductive ink is used to coat the sidewalls o f the vias. This
provides a conductive surface that is electrically connected to the front and back side
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
134
copper surfaces. This electrically conductive “seed layer” is required for the surface to
plate properly.
The first step in the process is to drill the via holes in the circuit board. Carefully
de-burr the drilled holes. This can be done with fine sandpaper. In the clean room, set
the oven to 100°C and let it heat up. Clean the board carefully (use both acetone and
isopropyl alcohol (IPA)). Scrubbing the board with an abrasive pad and DI water may
help.
It is important to have a clean board before plating.
Make sure all debris is
removed from the drilled holes. Shake the bottle o f conductive ink for several minutes.
Using a pipette, place a small amount of ink on one side o f the board. Use the rubber
squeegee to push ink into the holes. Make sure that the holes are completely filled with
ink.
With the squeege try to quickly wipe the ink residue o ff the board (ink should
remain in the holes). Then quickly blow the ink out o f the holes using the nitrogen gun.
Hold the board up to the light to check to see if the ink is gone from all o f the holes (this
is a messy process). All holes should be clear. Try to keep the board as clean as possible
- the main surface should not be covered with ink. Ink can be removed by carefully
wiping the ink away with an acetone coated cotton swab. W hen finished, check again
that all holes are clear. This whole process must be done quickly because ideally, you
would like the ink that remains on the sides o f the holes to be wet. Next, place the board
in the oven at 100°C for 30 minutes to cure the ink.
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135
While the ink is curing, set up the plating beaker. Rinse the plating beaker with
DI water. Add the mixed plating solution to the beaker. Attach the output from the air
pump to the vertical tube on the plating tank. Plug in the power supply, and attach the
positive lead from the power supply to the two copper plates on the top o f the tank. The
negative lead will need to be attached to your board. This can be done either with an
alligator clip or by soldering a small wire to the board so that the lead is connected to the
wire (this works best - the soldering can be done after you drill the holes).
If your board is mostly copper and is in the 2 inch by 2 inch size range, the plating
current should be around 1 Amp (plating current should be approximately 10 —20 amps
per square foot o f plated area for good adhesion). The web page listed below provides a
calculation for accurate plating thickness. Set the current limit to this value, and set the
voltage to 0.2V.
After the ink has cured, the board must be carefully cleaned. Any area on the
surface of the board with ink remaining will have poor adhesion when plated. So you
must lightly scrub the ink away from the main areas o f the circuit board. Be careful not
to remove the ink from the edge o f the holes. This takes some practice. When finished,
rinse the board in DI water, and then dip the board for 10 to 15 seconds in 35% sulfuric
acid. Attach the board to the board holder. Attach the negative power supply lead to
your board (or the wire you have soldered to the board). Turn on the output o f the power
supply. Turn on the air pump. Lower the board into the tank, making sure the board is
completely covered with solution. Ramp up the voltage on the power supply until the
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136
current limit is met. Typical plating time is about 35 minutes for a double sided 2” x 2”
board plated with !4 to 1 mil o f copper (see the web page listed below for an accurate
current vs. area vs. time calculation). When the plating is complete, remove the board
and rinse in DI water for several minutes.
Return the plating solution to the container for re-use. Rinse and dry the plating
tank and parts.
The plating process is based upon the “Think and Tinker Copper Electroplating
Process,” see http://www.thinktink.com for very detailed plating instructions, including
an analysis o f the chemistry and a formulation o f the plating solutions.
Over time the conductive ink tends to dry out in the bottle. It can be diluted by
mixing it with Butyl Cellosolve Acetate (a solvent).
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137
A p p e n d ix E . S il ic o n M ic r o m a c h in in g
and
L it h o g r a p h y T e c h n iq u e s
Standard Procedures:
Wafer Cleaning
1. Soak the wafer in isopropyl alcohol (IPA) for 2 minutes, followed by 2
minutes in acetone.
2. Dry with N 2.
3. Dehydrate bake on the hot plate for 1 minute at 130°C.
Patterning —Lift off process (dark mask locations result in metal on wafer)
1. Spin Hexamethyldisilazane (HMDS) on the wafer for 30s at 4.5k rpm.
2. Spin AZ5214 photoresist on the wafer for 30s @ 4.5k rpm.
3. Bake on the hot plate at 110°C for 2 minutes.
4. Expose with the MJB3 for 3.5s.
5. Post bake on the hot plate at 130°C for 1 minute.
6. Flood expose w ith the MJB3 (no mask) for 72s.
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138
7. Develop in AZ300 for 27 to 35 seconds. After 27 seconds visually monitor
the development, adding 2 or 3 seconds at a time.
8. Rinse with water.
9. Post bake on the hot plate at 110°C for 1 minute.
10. Using the E-Beam Evaporator, evaporate 500A Ti, followed by 2kA Au and
500A Ti.
11. Perform the lift-off by placing the wafer in 80°C photoresist stripper
(PRS2000). Use the acetone squirt bottle to rinse off any stray fragments o f
metal. Time ranges from 30 minutes to 12 hours.
12. Rinse for several minutes in the cascade rinser.
13. Dry w ithN 2-
Patterning —Plating features (clear mask locations result in metal on wafer)
1. Use a metalized wafer containing 500A of Ti, 2000A Au, followed by 500A
Ti.
2. Spin HMDS on the wafer for 30s at 3k rpm.
3. Spin PR1827 photoresist on the wafer for 30s at 3k rpm.
4. Bake on the hot plate at 105°C for 1 minute.
5. Expose with the MJB3 for 20s.
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139
6. Develop with MF351 developer mix (1 part MF351 to* 5 parts water) for
approximately 38s. Visually monitor the development, a d d in g more time if
necessary (in 2 to 3 second increments).
7. Rinse with water and dry with N 2.
8. Verify finished thickness with the Alpha Step (thickness sfciould be ~ 3 jJ .n i).
9. Gold plate (see procedure) to a thickness o f approximately 3 pm.
10. Clean the wafer with acetone to remove the photoresist.
11. Remove Ti seed layer by dipping in HF:H20 1:5 forr approximately 30
seconds. Visually monitor the etch, adding time if necessary (in 5 second
increments).
12. Remove the Au seed layer by placing the wafer in
gold etch solution
(Transene Company’s TFA Gold Etch Solution) for approxim ately 1 minute.
Visually monitor the etch, adding time if necessary (in 5 se c o n d increments).
13. Remove the bottom Ti seed layer by placing the wafer in HF:H20 1:5 for
approximately 30 seconds.
Visually monitor the e tc h , adding time if
necessary (in 5 second increments).
14. Rinse the wafer for at least 4 minutes in cascade rinser.
Gold Plating
1. Assemble the plating tank.
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140
2. Pour in the re-usable gold plating solution (Orotemp 24 loz. Au/gal from
Technic Inc., contains cyanide, very toxic —no not mix with any acid or acid
residue).
3. Add the stir-bar to tank. Insert the temperature probe into the tank and plug it
into the hot plate.
4. Set the stirrer to 250rpm and the probe target temperature to 55°C.
5. Connect the leads to the power supply (off) with the positive lead to the
resistor and the negative lead to the sample.
6. Wait for the solution to reach 55°C.
7. Insert the sample.
8. Set the power supply current to the desired current level (plating rate is
O.lpm/min at 2mA / cm2). Turn on the power supply output and make sure
voltage is set high enough to achieve the desired current.
9. When the plating is finished, remove the sample and rinse it for at least 4
minutes in the cascade rinser. Dry with N 2.
10. Check the plating height with the Alpha Step and repeat the plating if
necessary.
11. If the plating thickness is acceptable, strip the photoresist with acetone.
12. Return the plating solution to bottle and clean the glassware and tank parts
carefully.
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141
Oxide Etch
1. Pattern the Au using photolithography (Au will be used as an etch mask)
2. Remove the oxide from the mask openings —use a mixture o f BOE 6:1 H 2 0
for approximately 1 minute (depending on the oxide thickness). The etch rate
is about 950A per minute. A plastic pipette can be used to place the BOE
mixture only on the mask openings. This will reduce the risk o f opening the
oxide barrier on the edges o f the wafer.
The oxide etch can be visually
monitored — when the oxide has been completely removed the wafer will
become hydrophobic and the liquid will no longer wet to the surface.
3. Rinse the wafer for at least 4 minutes in cascade rinser and then dry the wafer
withN2.
Cavity / Silicon Etch
1. Pattern and etch the oxide (see procedure above).
2. Mix TMAH (25%) solution with water (1 part 25% TMAH to 2 parts water).
3. Place the mixture on hot plate with the temperature probe attached.
4. Set the probe target temperature to 90°C.
5. Etch the native oxide to remove any oxide growth - use a solution of BOE 6:1
H20 for 1-2 seconds. Check to see if the wafer is hydrophobic to verify that
all the oxide has been removed.
6. Insert the sample and cover the beaker w ith several layers o f aluminum foil.
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142
7. The silicon etch rate is approximately 100pm / 3 hours.
8. Add water to the TMAH solution as necessary to keep the liquid level
constant.
9. Rinse the wafer in the cascade rinser when the etching is com plete.
Micromachined cavity diplexer fabrication:
1. Clean a high resistivity silicon wafer.
2. Use the E-Beam Evaporator to evaporate 500A Ti, 2kA Au follow ed by 500A
Ti on the surface o f the wafer.
3. Create the top feed circuit using photolithography and g o ld plating (see the
procedures above).
4. Using the lift-off procedure above, pattern the coupling slots on the back side
o f the top feed wafer. Use the MJB3 IR mask alignment capability to align
the coupling slot mask to the features on the top o f the wafer.
5. Remove the Ti from the bottom of the wafer by dipping it in HF:DI 1:5 for
several seconds.
6. Rinse the wafer thoroughly in the cascade rinser.
7. Use the gold plating procedure to increase the gold thickness on the back o f
the top wafer to approximately 3 pm.
8. Clean a low resistivity, oxidized silicon wafer for the middle -cavity wafer.
9. Using the lift-off procedure, pattern the cavity openings.
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143
10. Etch the cavities using the silicon etching procedure.
11. Using conductive epoxy, bond a third wafer to the bottom o f the cavity wafer
to create the bottom o f the cavity.
12. Use the E-Beam Evaporator to evaporate 500A Ti followed by 2kA A u on the
cavity assembly. This will coat the walls and the bottom o f the cavity with
metal.
13. Use the gold plating procedure to plate a layer o f gold approximately 3pm
thick on the cavity assembly.
14. Using conductive epoxy, bond the top feed wafer to the cavity wafer.
A
camera assisted wafer to wafer bonder / aligner can be used to align the two
pieces (available in the Steward Observatory clean room).
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144
A p p e n d ix
F. HFSS S e t u p I s s u e s
Ansoft’s HFSS Version 7 has several default options that hinder its performance
on computers with good resources. For good performance it is important that fresh
installs o f HFSS be configured to use all o f the computer resources available. Without the
addition of several key configuration settings, simulations performed will be severely
limited in size and simulation speed will be slowed. The following options should be
adjusted appropriately to get good performance from a newly installed HFSS package.
System RAM:
By default HFSS assumes a computer only has 128MB o f RAM. To get HFSS to
utilize more memory, a file should be created in the Ansoft/CONFIG directory. This file,
‘Prefs.ini’ should contain the command option:
DIRECTJSOLVER MemLimitSoft X
where X is the amount o f RAM (in kB) that is available to the solver. On a system with
1GB o f RAM this might be 900000 kilo bytes (allowing 100000 kilo bytes for operating
system overhead etc.) Note: X should be specified in kilo bytes without any unit postfix.
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145
The file should also contain the command option:
DIRECTJSOLVER MemLimitHard X
where X is the maximum amount o f RAM the solver can use before exiting. On a system
with 1GB o f RAM this might be 980000 kilo bytes (allowing for minimal OS overhead).
HFSS uses physical RAM until it reaches the MemLimitSoft limit, at which time it
begins to use an efficient internal swapping method to allow for much larger memory
requirements. If the problem exceeds this swapping capability and has to use more RAM
HFSS will exit when the limit, MemLimitHard, is reached (to prevent a never ending
simulation). If the value MemLimitHard or MemLimitSoft is set too high, Microsoft
Windows will begin to swap memory using the operating system swapping methods.
This will result in simulations that will probably never finish because the Windows
swapping routine is not efficient with HFSS.
Multiple Processors
By default HFSS will only use one processor. I f a dual processor machine is
used, a dual processor license must be purchased for that copy of HFSS (—$100 extra
with the educational discount). The Windows kernel m ust also be installed with multiple
processor support.
Finally, there must be a command option in the ‘Prefs.ini’ file
described above. This option should read:
DIRECTSOLVER NofProcessors X
where X is the number o f processors available.
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146
References
[1] D. Peroulis, S. Pacheco, K. Sarabandi and L.P.B. Katehi, "MEMS Devices for High
Isolation Switching and Tunable Filtering," IEEE MTT-S International Microwave
Symposium Digest, 2000, pp. 1217-1220.
[2] J. Papapolymerou, J.C. Cheng, J. East and L.P.B. Katehi, "A Micromachined High-Q
X-Band Resonator," IEEE Microwave and Guided Wave Letters, Vol. 7, No. 6, pp. 168170, June 1997.
[3] P.J. Bennett, T.M. Monro and D.J. Richardson, "Toward practical holey fiber
technology: fabrication, splicing, modeling, and characterization," Optics Letters, Vol.
24, No. 17, pp. 1203-1205, September 1999.
[4] E. Ozbay et. al., "Defect Structures in Metallic photonic crystals", Applied Physics
Letters, 64,1994.
[5] A.F.
Peterson,
E le c tro m a g n e tic s,
S.L.
Ray
and
R.
Mittra,
C o m p u ta tio n a l
New York: IEEE Press, 1997.
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M e th o d s
fo r
147
[6] D. C. Wittwer, "Extension o f FDTD absorbing boundary condition methods to lossy
dielectrics for the modeling o f microwave devices," Ph.D. Dissertation, The University o f
Arizona, 1998.
[7] S. Dey and R. Mittra, "Efficient Computation o f Resonant Frequencies and Quality
Factors o f Cavities via a Combination o f the Finite-Difference Time-Domain Techniques
and the Pade Approximation," IEEE Microwave and Guided Wave Letters, Vol. 8,
No. 12, pp. 415-417, December 1998.
[8] HFSS On-line user manual, Ansoft Corporation.
[9] HP8720C Network Analyzer Operating Manual, Hewlett-Packard Company, 1991.
[10] R.B. Marks and D.F. Williams, M u ltic a l v l .0 0 , NIST, Boulder, CO, Aug. 1995.
[11] J. Papapolymerou, "MMIC Passive and Active Structures," Ph.D. Dissertation, The
University of Michigan, 1999.
[12]J.D. Joannopoulos, R.D. Meade, and J.N. Winn, P h o to n ic C r y s ta ls : M o ld in g th e
F lo w o f L ig h t ,
Princeton, Princeton University Press, 1995.
[13] E. Ozbay et al., "Defect structures in a layer-by-layer photonic band-gap crystal,"
Physical Review B. May, 1995.
[14]R.W . Ziolkowsi and M. Tanaka, "FDTD analysis o f PBG waveguide power splitters
and switches for integrated optics applications," Integrated Photonics Research, OSA
Technical Digest, 1999.
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148
[15] D.M. Pozar, M ic r o w a v e E n g in e e rin g , 2nd edition, John Wiley & Sons Inc., 1998.
[16] E.R. Brown, "RF-MEMS Switches for Reconfigurable Integrated Circuits," IEEE
Microwave Theory and Techniques, Vol. 46, No. 11, pp. 1868-1880, November, 1998.
[17] C.K. Walker, A Hungerford, G. Narayanan, C. Groppi, T.M. Bloomstein, S.T.
Palmacci, M.B. Stem, J.E. Curtin, "Laser micromachining o f silicon: A new technique
for fabricating high quality terahertz waveguide components," International Symposium
on Space Terahertz Technology, Cambridge, MA, pp. 358-376, March. 1997
[18] A. Hyun, H. Kim, J. Park, J. Kim, J. Lee, N. Kim, B. Kim, and U. Hong, “K-Band
Hair-pin Resonator Oscillators,” IEEE MTT-S International Microwave Symposium
Digest, 1999, pp. 725-728.
[19] J.S. Hayden and G.M Rebeiz, “One and two-bit low-loss cascadable MEMS
distributed X-Band phase shifters,” IEEE MTT-S International Microwave Symposium
Digest, June 2000, pp. 161-164.
[20] O. Tabata, R. Asahi, H. Funabashi, K. Shimaoka and S. Sugiyama, “Anisotropic
etching o f silicon in TMAH solutions,” Sensors and Actuators A, vol 34, pp. 51-57, 1992.
[21] A.R. Brown and G.M. Rebeiz, “A high performance integrated K-Band diplexer,”
IEEE Trans, on Microwave Theory and Techniques, vol. 47, No. 8, August 1999, pp.
1477-1481.
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