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A computer controlled microwave spectrometer

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This thesis, having been approved by the
,
special Faculty Committee is accepted
by the Graduate School of the
,
University of Wyoming
in partial fulfillment of the requirements
_
for the degrjee^f---ML%M£.°L-§Sii£i\£p________
'
Dean of the Graduate School
D afe~B&Y£mbex--i7_»„i2.70
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
A COMPUTER CONTROLLED
MICROWAVE SPECTROMETER
by
James Robert Jones
A Thesis
Submitted to the Department
o f Physics and the Graduate School
o f the U n ive rsity o f Wyoming in P a rtia l
F u lfillm e n t o f Requirements fo r the Degree of
Master o f Science
LIB R A R Y
UNIVERSE'/ 0 ? WYOMING
L A K A iV ilE
U n ive rsity o f Wyoming
Laramie, Wyoming
November, 1970
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U M I N u m b e r: E P 1 6 3 8 6
IN F O R M A T IO N T O U S E R S
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In the unlikely e ven t that the author did not send a com plete m anuscript
and there are missing pages, th ese will be noted. Also, if unauthorized
copyright m aterial had to be rem oved, a note will indicate the deletion.
®
UMI
U M I M icroform E P 1 6 3 8 6
Copyright 2 0 0 7 by P roQ uest Inform ation and Learning C o m pany.
All rights reserved. This m icroform edition is protected against
unauthorized copying u nder Title 17, United S tates C ode.
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A nn Arbor, Ml 4 8 1 0 6 -1 3 4 6
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ii
ACKNOWLEDGEMENTS
The author wishes to express his g ra titu d e to the fo llo w in g :
Dr. Edgar A. Rinehart, thesis d ire c to r, fo r his help, understand­
in g , and tr u s t ;
Dr. Derek J. Prowse, Physics Department Chairman,
fo r providing to me the opportunity o f graduate work a t the Univer­
s it y o f Wyoming and fo r m aintaining a personal in te re s t in my progress;
the National Aeronautics and Space A d m inistration, which funded the
p ro je c t fo r which th is work was done and which provided my fin a n c ia l
support during my graduate study.
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DEDICATION
To Bonnie
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iv
TABLE OF CONTENTS
Page
I.
In tro d u ctio n
......................
1
A) C o n tro llin g Purpose.............................
1
B) Equipment A vailable & In te rfa ce Requirements
II.
.......
D escription o f Equipment ................
5
A)
5
MRR Spectrometer ...........................
B) PDP8/I
1)
.................................
Computer D escription
.............
2)
H
11
b) Processor Registers
IP
Input/O utput System
a) I/O In s tru c tio n s
C)
H
a) Basic C o n fig u ra tio n ................................................
................
c) In s tru c tio n s and D ata............................................
III.
?
..................................
13
15
....................................................
15
b) I/O Bus .....................................................................
17
3)
Logic Elements ..............................................................
15
4)
Device Addressing and IOP Pulses ............................
5)
Data to and from AC .....................................................
2^
6)
SKIP and INTERRUPT ........................................
27
General In te rfa ce D e s c rip tio n ............................................
8400B—PDP8/I In te rfa ce
07
u '
.............
32
A) Hardware and Nomenclature ..................................................
32
1)
DECModules and Wire-Wrap Boards .............................
R eproduced with permission of the copyright owner. Further reproduction prohibited without permission.
32
V
Page
B)
2)
Equipment Location .......................................................
32
3)
Drawing Conventions and A bb re viation s.....................
36
PDP8/I I/O Additions
1)
................... ........................................
10 Channel ADC Input M u ltip le xe r ........................
39
a)
Description .................................................
39
b)
In s tru c tio n Set and Programming
39
c)
Logic Operation
......................
............................
2)
MPXR - A/D OP-AMP:
3)
1 0 -B it Analog to D ig ita l Converter
4)
Description
AO
..............................
a)
Description
b)
In s tru c tio n Set andProgramming
c)
Logic Operation
......................
..........................................................
6)
45
48
AO
........................
48
.....................................................
49
1 2 -B it, 0 to 10V D ig ita l to Analog Converter
D/A-l
5)
39
52
a)
D escription
..................
52
b)
In s tru c tio n Set
.....................................................
52
c)
Logic Operation
.....................................
52
1 2 -B it, 0 to -10V DAC (D/A-2) and 1 0 -B it,
0 to -10V DAC ( D/A-3)
55
a)
D escription
55
b)
In s tru c tio n Set
c)
Logic Operation andConnections
d)
F ilt e r — OP-AMP Operation
....................................
...............................................
..........................
56
...............................
60
I/O Bus Transfer Register M735
a)
D escription
56
..........................................................
R eproduced with permission of the copyright owner. Further reproduction prohibited without permission.
61
6.1
vi
Page
b)
7)
In s tru c tio n Set
................................................
61
D ig ita l Counter Reader/Translator . . ....................
63
a)
D escription
63
b)
In s tru c tio n Set
and Programming ....................
66
c)
Logic Operation
and Connections
66
i)
........................................................
Cable Connections
i i ) Logic Operations
8)
9)
..................
..........
68
........* ..................
68
P lo tte r Control
.....................
79
a)
D escription
.........
79
b)
In s tru c tio n Set and Programming
c)
Logic Operation
..........
Surplus Paper Tape Reader
a)
Description
..................
8?
............
84
..........................................................
b) In s tru c tio n Set
and Programming
c)
and Cable Connections
Logic Operation
10) Motor Control
80
...................
84
84
.........
86
.............................................................
83
a)
Description
.......................
b)
In s tru c tio n Set and Programming
c)
Logic Operation
83
...................
............
84
85
11) Stepper Motor Subcontrol fo r MRS Pressure
Gauge
............................................................................
a)
D escription
.........................................................
b)
In s tru c tio n Set and Programming
c)
Logic Operation
d)
D escription o f StepperMotor C onfiguration..
100
100
...................
^82
................................................
*83
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- n8
v ii
Page
e)
MKS Gauge DC Output A m p lifie r and
F ilt e r
12)
IV
......................................
In d ic a to r Lamps and PanelSwitches
Additions and M odifications
A)
117
......................
120
................ . ................................
128
P h o to e le ctric Paper Tape Reader
...................................
128
1)
M otivation
.............................
128
2)
Description
..................................................
128
3)
In s tru c tio n Set and Programming
4)
Logic Operation
5)
System M odifications
...........
B) P lo tte r Flag M o dification
V A Test Program
Selected References
...........................
.................................................
.....................................
129
130
132
13^
.................................................... * .....................
..................................
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^
viii
LIST OF TABLES
TABLE
I.
II.
III.
IV.
V.
.
Page
Abridged MPXR 4047/43 S pe cifica tion s
Binary Codes
.................
41
.............................................................
64
...............
70
...................
89
Counter Cable and Adapter Connections
Reader Transport Cable Connections
U Frame - Switch Cable - 32 Pin Connector
Connections
..............................................................
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122
LIST OF FIGURES
Figure
Page
2.0
Block Diagram o f Spectrometer..................
6
2.1
Simple Logic G ates...............................
21
2.2
Logic Elements.................................................................
23
2.3
Device S e le c tio n ......................... . ................................
25
2.4
Data Transfer to AC................................................
2.5
SKIP and INTERRUPT....................................................
2.6
8400B-Interface-PDP8/I C o n fig u ra tio n ...............
3.0-A.B
Module Locations ...........................................................
34-5
3.1
10 Channel Analog Input M u ltip le xe r fo r ADC......
42
3.2
W993 MPXR Module Printed C irc u it Board
26
.
28
29
Connections.....................
3.3
44
MPXR Operational A m p lifie r & D/A-2 Operational
A m p lifie r Schematics.............................................
46
3.4
Burr Brown Powered Rack Panel.............................
47
3.5
Analog to D ig ita l Converter - 0 to 10V, 1 0 -B it..
3.6
D ig ita l to Analog Converter D /A -l:
1 2 -B it,
0 to 10V ....................................
3.7
D ig ita l to Analog Converters — D/A-2:
0 to -10V & D/A-3:
50
53
1 2 -B its,
1 0 -B its, 0 to -10V ................
57
3.8
Input Gates and Cabling fo r D/A-2 and D/A-3
....
58
3.9
Burr Brown Powered Rack — Rear Hat Channel
....
59
3.10
I/O Bus Transfer Register ...........................................
62
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X
Figure
Page
3.11
Reader/Translator Accumulator Loading Scheme..
67
3.12
Reader/Translator Cable Connection .....................
69
3.13
Frequency Marker Cable Connector M o dification .
71
3.14
Reader/Translator Input A m p lifie r Board
Schematic
3.15
..................................................................
...................... ............. .
Binary Code T ra nslato r
3.16-A,B,C,D Counter Reader/Translator
73
.....................................
3.17
BNC Connector S trip
3.18
P lo tte r Control
3.19
Paper Tape Reader 90VDC Power Supply and
81
....................................................
83
3.20
Paper Tape O rienta tio n and AC Loading Scheme
3.21-A.B
Surplus Paper Tape Reader Logic
3.22-A,B,C
Motor Control
3.23-A,B
Stepper Motor Subcontrol
3.24
Subcontrol Timing
3.25
Stepper Coils and V e rify Switches
3.26
-7VDC In d ic a to r Lamp Supply & +28VDC
..
..................
......................
Stepper Coil Supply
74-7
................................................
......................................................
Solenoid D river
72
85
87
90-1
96-8
........................................
......................................... . ......... ..
............. ..
...............................................
104-5
106
110
112
3.27
Function Switch M odifications
..............................
113
3.28
Stepper Cable Connections
....................................
114
3.29
D riv e r:
Stepper Coil Drivers
...........................
115
3.30
D rive r:
Wiper Select & Schmidt T r ig g e r s .. . . . . .
116
3.31
Schmidt T rigger Printed C irc u it Board
........
118
3.32
MKS Gauge DC Output A m p lifie r -F ilte r
..................
HO
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xi
Figure
Page
3.33
In d ic a to r Panel:
Lamps and Sw itches
3.34-A.B
In d ic a to r Lamp Drivers & Cable Connections^. . . .
3.35
Pov/er In d ica tio n Logic
3.36
W976 AMP-3 Printed C irc u it Board
......................
126
3.37
W976 AMP-2 Printed C irc u it Board
.......................
127
^•1
High Speed Paper Tape Reader Logic
...........
131
4.2
P lo tte r Flag M o dification
.................................... .
135
5.1
FOCAL Program
..........................................
123-4
125
...........................................
P lo t o f Absorption Line Data
5.3
121
..................................
P rin to u t o f Absorption Line Data
...........................
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137
138
139
I
In tro d u ctio n
A)
C o n tro llin g Purpose
In the Microwave Spectroscopy Laboratory o f the U n ive rsity o f
Wyoming Physics Department, a Molecular Rotational Resonance (MRR)
Spectrometer is maintained and operated.
This instrument provides a
microwave absorption spectrum corresponding to the ro ta tio n a l energy
levels o f a sample o f some molecule which possesses an e le c tr ic dipole
moment and which is in the gaseous s ta te .
The recording o f the absorp­
tio n versus frequency spectrum provided by the Spectrometer indicates
d ir e c tly the frequency, lin e w id th , and in te n s ity
lin e resolved.
o f each absorption
From these parameters much inform ation can be d ete r­
mined about the sample molecule:
re la xatio n ra te s ,
bond lengths and angles, molecular
concentration in a mixed sample, e le c tr ic dipole
moment s tre n g th , e tc .
The spectra o f the more complex molecules are very ric h in lin e s
and the processing o f the contained inform ation becomes both time
consuming and subject to human e rro r.
Moreover, in ap plicatio ns in ­
volving the analysis o f a large number o f samples fo r even the c o l­
le c tio n o f a small number o f measurements per sample, manual opera­
tio n o f the spectrometer fo r such data a c q u is itio n becomes very
in e f f ic ie n t in terms o f time spent in managing the operation and in
errors introduced w hile manually recording data.
Now an automated
system fo r c o n tro llin g spectrometer functions and fo r receiving and
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processing spectral data would elim inate these undesirable e ffe c ts .
I f , in a d d itio n , th is automated system were programmable, the
system would possess the necessary f l e x i b i l i t y to control the spectro­
meter in various specialized s itu a tio n s .
A programmable system would
allow : quick survey spectra o f a ll or p art o f the spectrometer f r e ­
quency range, high re s o lu tio n spectra, determination o f re la tiv e con­
centrations o f various compounds in a m ixture, time averaging o f weak
spectral lin e s , precise frequency determination o f spectral lin e s ,
cataloging o f spectra, search fo r a sp e cifie d lin e or group o f lin e s ,
e tc.
Operation o f the MRR Spectrometer a t the U n ive rsity o f Wyoming
has indicated th a t the above advantages would be both desirable and
expedient.
Thus i t was decided to automate the spectrometer, and a
small d ig ita l computer was purchased to become the heart o f the con­
t r o llin g system.
B)
Equipment A vailable and In te rfa ce Requirements
The Spectrometer is a RE05-8400B Microwave Spectrometer which
was purchased in the summer o f 1967 from Hewlett Packard w ith funds
from NASA Grant MGR 51-001-020.
The instrument operates in the R-band
(26.5 to 40 GHz), w ith a backward wave o s c illa to r microwave source and
a Stark Modulation detection system.
The computer is a PDP8/I d ig ita l
computer purchased from D ig ita l Equipment Corporation in the spring
o f 1969, also w ith funds from the above mentioned G ra n t.1
This paper is concerned w ith the d e ta ils o f the in te rfa c e betv/een the PDP8/I and the 8400B a t the time o f w r itin g .
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
There are several requirements th a t the in te rfa c e must s a tis fy :
a)
The in te rfa c e must provide the PDP8/I w ith control o f 8400B
functions s u ffic ie n t to s ig n ific a n tly reduce the operator
tasks required.
b)
A ll spectral inform ation from 8400B can be tra n sfe rre d to
PDP8/I a t any time
c)
The type o f inform ation handled by the PDP8/I (binary num­
bers) must be made compatible v/ith the inform ation form
handled by the RE05 (analog voltage le v e ls )
d)
The e rrors introduced by the in te rfa c e must be in s ig n ific a n t.
The in te rfa c e described in th is paper has been b u ilt and is now
operating.
I t provides programmed control o f the 8400B operating fr e ­
quency via the PDP8/I, enables the PDP8/I to receive spectral informa­
tio n from the 8400B, and allows the PDP8/I to m onitor gas sample
pressure w ith in the 8400B absorption c e lls .
The e n tire in te rfa c e is under complete control o f the PDP8/I,
each in te rfa c e fu n ctio n being associated w ith a unique machine lan­
guage Input/O utput in s tru c tio n .
Some sections o f the in te rfa c e are
capable o f sig n a lin g the PDP8/I fo r service requests.,
The in te rfa c e was designed to allow independent programmed con­
t r o l o f each fu n c tio n ; a given RE05 operating scheme is effected by
combining and re la tin g these functions in a software program such th a t
the desired scheme w ill be followed by the PDP8/I.
In the sections fo llo w in g , a fu n ctio n al d escriptio n o f the
spectrometer is f i r s t given fo r the purpose o f in d ic a tin g the type o f
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equipment which must be c o n tro lle d , and the form the c o n tro llin g in ­
form ation must assume, as w ell as in d ic a tin g the form o f the informa­
tio n outputted by the 8400B.
A general d e scription o f the PDP8/I is
then given, followed by a de ta ile d de scriptio n o f the Input/O utput
f a c i li t i e s o f the machine, d escriptions which are
necessary fo r an
understanding o f the p a rtic u la r functions o f the in te rfa c e as well as
fo r an understanding o f the d e ta ils o f in te rfa c e operation.
With th is
background in fo rm a tio n , a general in te rfa c e de scription is then given,
followed by d e ta ile d descriptions o f each section o f in te rfa c e .
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5
II
D escription o f Equipment
A)
MRR Spectrometer
The Hewlett Packard Model 8400B Molecular Rotational Resonance
(MRR) Spectrometer2 is an assembly o f e le c tro n ic and vacuum handling
equipment which can be divided in to seven major operational d ivisio n s
fo r purposes o f d e s c rip tio n .
These d iv is io n s are:
1)
A vacuum and gas sampling system.
2)
An absorption c e ll in which the gas sample being analyzed is
subjected to microwave ra d ia tio n .
3)
A microwave source o f va ria ble frequency and constant power
output.
4)
An in d ic a to r o f the microwave source frequency
5)
A Stark modulation system
6)
A system fo r detection o f microwave power absorbed by the
gas sample in the absorption c e ll
7)
An in d ic a to r o f the power absorbed at a given fre q u e n c y
These d iv is io n s are elaborated on below.
A generalized block diagram
o f the spectrometer is shown in f ig 2.0.
The vacuum system consists o f a sample intake manifold eouipoca
w ith vacuum control valves; a mechanical forepump, a molecular sieve,
and ion pump
fo r producing high vacuum; vacuum lin e s connection the
intake m anifold to the absorption c e ll in te r io r .
An MKS Instrum ents.
Inc. Baratron Pressure Gauge is used to provide in d ic a tio n o f the
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MICROWAVE
ATTENUATOR
ATTENUATOR
ATTENUATOR
PHASE
SHIFTER
PIN
MODULATOR
FREQUENCY
COUNTER
MODULATOR &
DRIVER
SYNCHRONOUS
STARK CELLS
SPECTROMETER B L O C K
DIA G RAM - FI GURE
2.0
7
pressure w ith in the absorption c e ll by comparing th is pressure w ith a
reference, usually a high vacuum.
The absorption c e ll consists o f a s ix -fo o t length o f waveguide,
the in t e r io r o f which can be evacuated.
One end allows microwaves to
e n te r, w hile the other end is terminated w ith a microwave detection
device.
Contained w ith in the c e ll and running down it s length is an
electrode insulated from the c e ll w a lls , to which a square wave poten­
t i a l is applied during spectrometer operation so th a t Stark E ffe c t
detection techniques can be employed.
The absorption c e ll is connect­
ed to the vacuum and gas sampling system so th a t gas samples a t low
pressures can be introduced in to the c e ll.
The microwave source is an HP 8690A Backward Wave O s c illa to r
(BWO) operating in the R-band range o f 26.5 to 40 GHz.
is continuously
va ria ble over th is frequency range.
containing a therm istor
The BWO output
A feedback loop
microwave power monitor samples the output
power and holds i t constant over the R-band frequency range.
The BWO
is frequency s ta b iliz e d by phase locking i t to the 100th harmonic o f
an HP 8466A Reference O s c illa to r, a stable va ria ble o s c illa to r opera­
tin g in the range 24 to 40 MHz.
o f an HP 8709A Synchronizer.
The phase lock is achieved by means
Part o f the BWO output is mixed w ith
harmonics o f the 8466 reference o s c illa to r and presented to the input
o f the 8709.
The la t t e r v / ill accept only a 20?-Hz d ifferen ce frequency
input and an in te rn a lly generated 20MHz s ig n a l.
to s ta b iliz e the BWO.
This output is used
When out o f lo c k , the synchronizer w ill gener­
ate search s ig n a ls , which when applied to the BWO, cause
the la t t e r
to sweep over a frequency range u n til recaptured by the 8709.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
The
synchronizer also outputs a phase e rro r signal to the reference o s c il­
la to r servo motors, enabling the la t t e r to track the BWO in c e rta in
modes o f operation:
such a mode is employed when a va ria ble DC voltage
level is applied to the BWO FI! in pu t - - the BWO frequency w ill vary
w ith voltage applied, and the reference o s c illa to r w ill tra c k .
Now the 8466 reference o s c illa to r can be frequency c o n tro lle d
by the a p p lica tio n o f a voltage level at a frequency-tuning varicap
w ith in the u n it.
This feature allow s, in some modes o f operation, the
8466 to be frequency s ta b iliz e d by s e ttin g up a phase lock between i t
and the 8708A Synchronizer which contains a very stable cry s ta l o s c il­
la to r .
The output o f the 8466 is sampled by the 8708, and the la t t e r
provides co rre ctio n a l signals to the 8466.
The 8708 in turn has a
frequency-controllable FM in p u t, allow ing the BWO frequency to be
c o n tro lle d over small frequency ranges with high s t a b ilit y through the
8708A synchronizer.
The microwave frequency output o f the BWO is indicated on an HP
H21-5246L D ig ita l Counter connected to the 8466A reference o s c illa to r
through a H06-5252A Pre-Scalar.
The la t t e r divides the reference
o s c illa to r output by 100 and the re s u ltin g frequency is counted by
the counter.
The counter values are o ffs e t by 20flHz to compensate fo r
the 8466 harmonic lock 20MHz above the BWO frequency.
The counter
w ill in d ica te the BWO output in MHz., assuming the BWO is phase locked
to the 100th harmonic o f the reference o s c illa to r .
Stark modulation techniques are used to detect power absorption
by a gas sample contained w ith in the absorption c e ll.
Stark modula­
tio n lim its the spectrometer in use to the study o f only those mole­
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
cules possessing an e le c tr ic dipole moment.
The method is advantage­
ous in th a t the noise re je c tio n th a t can be realized is high, enabling
the detection o f extremely weak absorptions.
The 33.333KHz square wave Stark modulation signal is generated
by the HP 8428B Modulator Control which d is trib u te s th is signal to the
detection system and to the HP 8421B Stark Modulator.
This la t t e r
instrument power-am plifies the modulation signal and applies i t to
the Stark electrode w ith in the absorption c e ll.
The square wave modu­
la tio n signal is applied to the c e ll such th a t the lower base o f the
square wave is a t ground p o te n tia l.
The base-to~peak height o f the
square wave is continuously variable at the 8428 modulator control over
a 2000V range.
Thus the qas w ith in the absorption c e ll
is subjected
to an e le c tr ic f ie ld a lte rn a te ly switched on and o f f a t a 33.333Khz
ra te .
I f the gas is polar in nature, the applied e le c tr ic f ie ld in te r ­
acts w ith the e le c tr ic dipole moments o f the gas molecules in a manner
described by the Stark E ffe ct such th a t the molecules' ro ta tio n a l
energy le ve ls are s h ifte d from the n o -fie ld values.
This is equival­
e n tly a s h if t o f the microwave absorption frequencies away from no­
f ie ld values when an e le c tr ic f ie ld is applied.
This Stark modulation technique allows a phase-sensitive means o f
detection to be employed.
The detector operates e s s e n tia lly as follow s
Assume the BWO is slow ly sweeping a frequency range at a rate such th a t
the 33.333 KHz modulation wavelength is much sm aller than some swept
absorption lin e bandwidth.
The detector operates by comparing the
strength o f the microwave signal passed through the gas sample w ith and
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
10
w ithout the Stark f ie ld applied.
I t is th is d iffe re n ce signal which is
detected and converted to a DC voltage level proportional to the power
d iffe re n ce detected.
Mow a t some frequency at which the gas sample has
no ro ta tio n a l absorption lin e in both the on and o f f fie ld con dition s,
I
or has a lin e th a t does not s h if t w ith f ie ld (molecule w ithout e le c tr ic
dipole moment)
no power d iffe re nce is detected.
As the BWO sweeps
through some absorption band fo r which the Stark e ffe c t is present, a
d iffe re n ce is detected.
Mow as the BWO sweeps on past the lin e , i t
eventually encounters the same absorption lin e as s h ifte d when the
e le c tr ic fie ld is on.
The power d iffe re nce is detected in th is case
a lso , but due to the phase se n sitive detection means, the diffe re n ce
detected is given a magnitude s ig n ifica n ce opposite th a t given to the
detected n o -fie ld lin e .
Thus i f the no-signal DC output level o f the
detector is adjusted to 0V, and the n o -fie ld lin e s show as p o s itiv e
excursions, then the a p p lie d -fie ld lin e s w ill be indicated as neaative
excursions.
A c ry s ta l detector is used to demodulate the Stark-modulated
microwave energy passing through the absorption c e ll.
The re s u ltin g
amplitude-modulated 33.333KHz signal is am plified by the HP 8426D
P re a m p lifie r.
I t is passed on to the 8420A Synchronous Detector where
i t is compared w ith the 33.333KHz reference supplied by the 8428B
Modulator Control discussed above.
The comparison y ie ld s a b ip o la r DC
output s ig n a l.
This output is displayed on the 7127A S trip Chart Recorder, on
an o scillo sco p e , or on a meter located on the Synchronous Detector.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
B)
PDP8/I
1)
Computer Description
^a)
Basic C onfiguration
The D ig ita l Equipment Corporation's Programmed Data Processor 8/1
(PDP8/I)3*5*6 consists o f a d ig it a l inform ation processor, random
access magnetic core memory, in p u t/o u tp u t bus system, power supply, and
control panel mounted in the lower h a lf o f a s ix -fo o t high cabinet in
which can be mounted standard 19 inch rack mounted assemblies.
Sup­
p lie d w ith the cabinet assembly is a 33 ASP. teletype w ith hardware fo r
in te rfa c in g i t as an I/O device o f the PDP8/I.
The PDP8/I processor and memory u nits taken together comprise a
processing u n it w ith a storage capacity o f 4096 fixe d -le n a th words o f
12 b its each, and a memory cycle time o f 1.5 p sec.
The u n it perforins
two's complement a rith m e tic on 12 b it signed binary numbers.
Eight
in s tru c tio n s provide stored program control of processor operations:
s ix single-address memory reference in s tru c tio n s , one microproqrammable
re g iste r-op e ra tio n s in s tru c tio n , and one Input/Output control in s tru c ­
tio n .
This basic co n fig u ra tio n
has been extended in the PDP8/I system
e x is tin g in the Microwave Spectroscopy Lab through the purchase o f sev­
eral DEC options:
The KE8/I Extended A rithm etic Element (EAE) option
extends the number o f microprogrammable operations performed by the
re g iste r-o p e ra tio n s in s tru c tio n to include those of binary m u lt ip li­
c a tio n , d iv is io n , and some flo a tin g -p o in t fu n ctio n s; the VC8/I-B
Oscilloscope Display consists o f D ig ita l to Analog Converters (DAC)
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
connected to the I/O bus and c o n tro lle d by the I/O in s tru c tio n , enabling
the PDP8/I to control the beam p o sitio n and in te n s ity on an o s c illo ­
scope tube face; the KA8/I-B P o sitive I/O Bus option enables devices
employing p o s itiv e TTL or DTL lo g ic levels to be connected d ir e c tly to
the I/O bus w ithout p rio r lo g ic level conversion; the KW8/I-D Line
Frequency Clock is an I/O device which, under program c o n tro l, w ill
count down and provide in d ic a tio n o f elapsed re a l-tim e in te rv a ls .
b)
Processor Registers
The PDP8/I contains several re g iste rs which are used fo r tempo­
ra ry storage o f inform ation during in s tru c tio n execution.
te rs relavent
1)
to the
Those re g is­
problem o f in te rfa c in g are these:
The Accumulator (AC) Register is a 12 b it re g is te r in which
a ll a rith m e tic and lo g ic a l operations are performed.
The AC is the
im plied operand in the memory reference in s tru c tio n s TAD, AND, DCA
(described below); a ll in p u t/o u tp u t inform ation between the processor
and the I/O Bus moves through th is re g is te r.
The contents o f the AC
can be complemented, ro ta te d , incremented, tested fo r various Droperties
by means o f the OPR in s tru c tio n (see below).
2)
The Link is a o n e -b it re g is te r which is used as a carry and
borrow re g is te r w ith the AC during a rith m e tic operations and as the
le ftm o st AC p o s itio n during rotate-AC operations.
3)
The Memory
B uffer (MB) Register tem porarily holdsanyin fo r ­
mation passing between the various re g iste rs and the memory.
Other re g iste rs are the In s tru c tio n Register which holds the
current 3 - b it in s tru c tio n operation code, the Memory Address Register
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
13
which contains the current memory address to or from v/hich inform ation
is to be tra n s fe rre d , the Program Counter (PC) which contains the
address o f the next in s tru c tio n to be executed, and the Switch Register
which re fle c ts the status o f the twelve control panel switches,
c)
In s tru c tio n s and Data
A ll 4096 memory locations are addressable, thus the contents o f
any lo c a tio n can be operated on in the AC as a word o f data.
In s tru c ­
tio n words and Data words are both 12 b its in length.
For convenience, the set o f unsigned 12 b it binary integers w ill
be w ritte n in fo u r - d ig it octal representation.
Thus the binary range
000,000,000,000 to 111,111,111,111, which is 0000 to 4095 decimal,
becomes 0000 to 7777 o c ta l.
I t w ill be understood th a t in s tru c tio n
codes, data words, and memory addresses w ill be in octal reDresentatio n unless otherwise stated.
When re fe rrin g to a b i t p o sitio n in the AC, MB, or in a memory
lo c a tio n , a "bit-num ber" w ill be given, the leftm ost b i t o f the word
being b i t 0, the rightm ost b i t being b it 11 (bit-numbers are decim al).
The Input/O utput Transfer (IOT) in s tru c tio n con tro ls the actual
tra n s fe r o f inform ation between the AC and the I/O Bus and w ill be
discussed separately below.
In order to in dica te how the PDP8/I can
process received inform ation in to usable form and provide control in ­
form ation to various I/O devices, the other seven in s tru c tio n s w ill be
lis te d below along w ith b r ie f d e scrip tio n s.
code take
The in s tru c tio n ODeration
the f i r s t three binary d ig its ( f i r s t octal d ig it ) o f the
in s tru c tio n v/ord.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
AND (0000):
In th is memory reference in s tru c tio n , the contents o f the
sp e cifie d memory lo ca tio n are lo g ic a lly ANDed on a b it- b y b i t basis w ith the contents o f the AC.
in the AC.
TAD (1000):
The re s u lt is put
Example:
memory lo ca tio n contents:
0703
AC:
3345
re s u lt (in AC):
0301
This memory reference in s tru c tio n performs two's comple­
ment a rith m e tic w ith the contents o f a memory lo ca tio n and
the AC by adding the contents together and placing the
re s u lt in the AC.
The Link re g is te r is used to in d ica te
carry outs (o ve rflo w ).
In two's complement a rith m e tic ,
b i t 0 o f a data word is the sign o f th a t number:
negative, 0 i f p o s itiv e .
1 if
A negative number can be obtained
from a p o s itiv e number by forming the two's complement o f'
the la t t e r , one o f the functions o f the OPR in s tru c tio n .
The TAD in s tru c tio n is used to load a word o f data in to
the AC a fte r the AC has been cleared.
ISZ (2000):
Increment the contents o f the specified memory lo ca tio n
by one.
I f the value o f the re s u lt is zero, increment the
PC by cne (skip the next in s tru c tio n ).
Otherwise no more
action is taken (execute the next in s tru c tio n ).
in s tru c tio n is used in forming program loops.
This
I t does
not d is tu rb the contents o f AC.
DCA (3000):
Deposit the contents o f AC in to the memory loca tio n
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15
s p e c ifie d , wiping out the previous contents o f th a t
memory lo ca tio n and clea rin g the AC.
JMS (4000):
Deposit the contents o f the PC in to the address sp ecifie d
by the in s tru c tio n , put the sp ecifie d address in to the PC
and increment the PC by one (re s u ltin g in a program jump
to the specified address plus one).
This in s tru c tio n
jumps to a sp e cifie d subroutine, simultaneously provid­
ing the subroutine w ith return linkage inform ation.
JMP (5000):
Place the address sp ecified in to the PC (re s u ltin g in a
program jump to the address s p e c ifie d ).
OPR (7000):
This in s tru c tio n does not reference the memory, but only
the AC.
There are two groups o f elementary operations
performed by th is in s tru c tio n .
Operations o f the f i r s t
group act on the AC and a lte r it s contents by ro ta tio n ,
complementing, incrementing, and clearing fu n ctio n s.
Group two in s tru c tio n s p rim a rily consist o f te s t opera­
tions which cause the PDP8/I to skip the next sequential
in s tru c tio n i f the te s t is tru e , otherwise there is no
skip .
2)
Input/O utput System
a)
TheInput/O utput
I/O In s tru c tio n s
Transfer (IOT) in s tru c tio n provides the pro­
grammer w ith control over
the devices connected to the I/O Bus.
It
provides device s e le c tio n , issues various commands to the selected
device to tra n s fe r in fo rm ation , and tests the status o f the selected
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
device.
Two IOT in s tru c tio n s con trol the In te rru p t Function.
When
th is computer fu n ctio n is enabled, I/O devices are able to request
service by in te rru p tin g programs being executed by the PDP8/I.
The
IOT in s tru c tio n is :
IOT (6000):
I n it ia t e a 4.25 y sec. I/O cycle.
B its 3-8 (second and
th ir d octal d ig its ) o f the in s tru c tio n comprise the de­
vice code (the address o f the device on the I/O Bus), and
b its 9-11 ( la s t octal d ig it ) define the function to be
performed by the addressed device.
The function b its 9-11 control access of three tim ing (IOP)
pulses to the selected device.
B it 11 controls pulse I0P1 a t time t l ,
b it 10 controls I0P2 a t la te r time t2 , and b it 9 controls I0P4 a t s t i l l
la te r time t4 , where t l , t2 , t4 are contained w ith in the 4.25 y sec
I/O cycle.
Each pulse is about 500nsec long and the time between the
end o f one pulse and the beginning o f another is about 300 nsec.
A "1" in a fu n ctio n b i t p o sitio n allows the corresponding IOP pulse to
be generated and be a va ila ble to the addressed device.
At the end o f
each pulse, the AC re g is te r w ill accept any inform ation placed on it s
input lin e s from the I/O Bus.
The actual functions co n tro lle d by
the IOP pulse depend on the I/O device addressed.
In general these
pulses w i l l :
a)
cause inform ation to be transferred from the AC to the I/O
device addressed
b)
cause inform ation to be transferred from the I/O device
addressed to the AC
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17
c)
in it ia t e
an I/O fu nction o f the selected device
d)
te s t the status or some condition o f the addressed device.
The actual e ffe c ts o f the IOT in s tru c tio n are determined by the way
the I/O device is connected to the I/O Bus, and by the nature o f the
I/O device i t s e l f .
b) I/O Bus
The I/O Bus consists o f a group o f lin e s connecting the PDP8/I
processor to various I/O devices, the la t t e r being connected in a
" p a r a lle l" fashion to the lin e s . Inform ation is transm itted
over a
ty p ic a l lin e in the form o f two voltage levels — nominally
+3 v o lts
(re fe rre d to as "lo g ic a l one" or "hig h") and 0 vo lts ("lo g ic a l zero"
o r "lo w ").
M u ltip le b its o f binary inform ation are transm itted in
p a ra lle l (a t one time) over a group o f lin e s rather than s e r ia lly over
one lin e .
Thus each lin e e ffe c tiv e ly ca rrie s only one b it o f informa­
tio n during a single given inform ation tra n s fe r cycle.
The fo llo w in g
is a l i s t o f the I/O Bus lin e groups and a d escription o f each:
a) BAC 0-11:
These 12 lin e s made available to any device the
current contents o f the AC.
A "1" in an AC p o sitio n pro­
duces a high condition on the corresponding BAC lin e .
b)
BMB 3-8 (1 ):
These s ix lin e s r e fle c t the contents o f MB b its
3-8
c)
BMB 3-8 (0 ):
These s ix lin e s are the same as (b) except th a t
the signal levels have been inverted fo r each b i t p o s itio n .
d) BMB 9-11:
9-11.
These three lin e s re fle c t the contents o f MB b its
During an I/O cycle , the IOT in s tru c tio n is contained
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18
in the MB.
Thus the device code appears on BMB 3-8 and the
fu n ctio n b its appear on BMB 9-11.
e)
AC 0-11:
These lin e s comprise the AC input bus.
biased high and are connected to the AC in p u t.
They are
I f a lin e
is forced low by an I/O device during an IOP pulse tim e, at
the completion o f th a t pulse a "1" w ill be ORed in to th a t
AC b i t p o s itio n .
f)
I0P1, I0P2, I0P4:
Pulses v / ill appear on these lin e s as
described above depending on the contents o f BMB 9-11
during an IOT in s tru c tio n
g) AC CLEAR:
execution cycle.
This lin e is biased high.
Forcing i t low u n til
the
end o f an IOP pulse w ill cause the AC to be cleared to 0000.
h)
SKIP:
This lin e is biased high.
Forcing i t low u n til the
end o f an IOP pulse w ill cause the in s tru c tio n fo llo w in g the
current IOT in s tru c tio n to be skipped upon completion o f the
I/O cycle.
i)
INTERRUPTREQUEST:
This lin e is normally biased high.
If
the PDP8/I is in the In te rru p t Mode and is executing some
program in s tru c tio n , then fo rcin g th is lin e low w ill cause an
automatic "JMS to Location 0000" to be executed by the PDP8/I
a fte r the current in s tru c tio n is completed, also causing the
PDP8/I to be taken out o f the In te rru p t Mode. I f the PDP8/I
was not o r ig in a lly in the In te rru p t Mode, thestatus o f
INTERRUPT REQUEST lin e is
j)
INITIALIZE:
the
ignored.
A pulse appears on th is lin e when PDP8/I power
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19
is turned on or when the START key on the control panel is
depressed.
k)
BTS 3:
This lin e ca rrie s a tim ing pulse occurring a t the
beginning o f various computer cycles, in p a rtic u la r a t the
beginning o f an IOT execution cycle.
The pulse ends 300nsec
before I0P1 would s ta r t.
3)
Logic Elements
In order to process or to operate w ith the signal le ve ls and pulses
o f the I/O Bus, special c ir c u itr y is required.
Since any lin e has only
two stable s ta te s , any processing c ir c u itr y need have only two stable
sta te s .
Other requirements are:
low noise s u s c e p tib ility ; DC coup­
lin g , since a signal level must sometimes be held fo r long or inde­
f i n i t e periods o f tim e; s im p lic ity in design, since in most cases o f
in te rfa c e design, many id e n tic a l c ir c u it elements are required to
process m u lti- b it inform ation groups.
This s im p lic ity im plies th a t
signal output le ve ls be compatible w ith signal input le v e ls , as ex­
ternal level converters add to design com plexity.
Also required is
fa s t c ir c u it response tim e, since a qiven signal may move through many
c ir c u it elements in series before i t is in the form to be used.
In th is in te rfa c in g a p p lic a tio n , p o s itiv e -le v e l T ra n sisto rT ra n sisto r Logic (TTL) cu rre n t-sin kin g c ir c u it elements were used:
Their lo g ic levels are compatible w ith those o f the I/O Bus, they
f u l f i l l the other requirements lis te d above, they are inexpensive, and
they are convenient to use.
The elements are available in Integrated
C irc u it form or they may be constructed from d iscrete components.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
20
Groups o f TTL elements are commercially a v a ila b le , premounted on p r in t­
ed c ir c u it boards w ith power connections made, in p u t/o u tp u t leads being
brought to connector pins a t the ends o f the cards.
These cards were
used in the present in te rfa c e whenever p o s s ib le .1*
In the processing o f tw o-state ( d ig ita l) lin e s o f inform ation,
the signals are usually combined according to the laws o f switching
(Boolean) algebra.
In considering a given c ir c u it element, one is more
concerned about the way signal levels are combined by the element to
give an output ra th e r than in the tra n s ie n t response o f the element or
other c h a ra c te ris tic s .
Thus, instead o f representing the element on a
switching c ir c u it diagram as an actual e le c tro n ic c ir c u it schematic, i t
is represented by a symbol which s ig n ifie s the signal combining func­
tio n o f the element.
Figure 2.1 gives the names, equations, symbols,
and tru th tables fo r some o f the switching functions.
A and B are the
signals applied to the inputs o f the elements represented by the sym­
b o ls, and C is the re s u ltin g output.
lo g ic a l 0 (0V).
The l i t t l e
Levels are lo g ic a l 1 (+ 3V) and
c irc le s on some o f the symbol leads corres­
pond to the bars above the le tte rs or le t t e r groups in the correspon­
ding equations and s ig n ify inversion (or complementation) as indicated
in the case (2) tru th ta b le .
The lo g ic elements most commonly a v a il­
able and r e la tiv e ly inexpensive in TTL form are the MAND gates (4 ),
INVERTERS (2 ), and NOR gates (5 ).
Gates are a vailable w ith more than
two in p u ts , or combinations o f 2-input gates th a t perform the same
function can be w ired.
Any desired function can be constructed ex­
c lu s iv e ly o f 2 -in p u t MAND oates or NOR gates, assuming propaoation
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
AND
A - B =C
A
B
(1 )
A
B
c
0 0
0
A
0 1
1 0
1 1
0
0
1
(2 )
I NV ERT
OR
A =B
A + B =C
z
NAND
a
B i
>
A
C
A
B
C
0
1
1
0 0
0 1
0
1
1 0
1 1
1
0
aT b = C
A
A- B = C ( =A + B )
B
A
B
(4)
A
B
C
0 0
0 1
1 0
1
1
1
1 1
0
B
1
NOR
A + B' =C
C
A
(7)
A
B
C
0 0
0 1
1 0
1 1
1
B
(5)
A ♦ B =C ( = A- B )
A
T > c
O
A
0
0
B
1
0 0
0 1
1 0
1 1
0
C
0
0
0
(6)
A
B
c
0 0
0 1
1 0
1
1 1
0
1
1
(8 )
A B
C
0 0
0 1
1 0
0
1
1
1
A • B = C (= A+ B)
A —C
B -C
1
SIMPLE
LOGIC
GATES
1
FIGURE
2.1
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
22
delays are w ith in any lim ita tio n reeuired.
Other lo g ic elements w ith
special symbols and appearing in th is paper are discussed below.
The D-TYPE FLIP-FLOP (Figure 2 .2 , case (1)) is a b i-s ta b le c i r ­
c u it used as a storage device.
mentary (A = F ).
The outDuts A and B are always comple­
When B = 1 (A = 0) the f lip - f lo p is said to be " s e t" ,
when B = 0 (A = 1 ), the f lip - f lo p is "re s e t".
normally high.
The R and S inputs are
The f li p - f lo p can be reset by making R low.
goes high again, the f l i p - f lo p remains re set.
w ill set the f l ip - f l o p .
When R
S im ila rly , a low a t S
I f the f l ip - f lo p happens to be in the set
sta te and a set pulse is given, no action occurs (and s im ila rly fo r
the reset s ta te ).
R and S inputs should not be low at the same time.
Another way to switch the f l ip - f lo p is by means o f the C and D in p u ts.
A step from 0 to 1 a t the C (clock) input causes the f l ip - f lo p to
switch according to the le vel o f the D (data) in p u t.
A 1 a t the D input
w ill cause the f li p - f l o p to be s e t; a 0 causes the f lip - f lo p to be re­
se t.
The only time data a t the D input can a ffe c t the f lip - f lo p state
is a t the in s ta n t v/hen the above-mentioned p o s itiv e tra n s itio n occurs
a t the C in p u t.
Case (2) o f Figure 2.2 is a SCHMIDT TRIGGER.
This device gives a
low output when the voltage at input A is below some predetermined le v e l.
When the voltage rise s above th is le v e l, output B goes high.
Case (3) is a SINGLE SHOT MULTIVIBRATOR.
A tra n s itio n from 0
to 1 a t input A causes the normally low output B to go high fo r a pre­
determined amount o f time and then go low, regardless o f the state o f
A during the time B is high or a t the time B goes low.
Usually some
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23
(1)
D-TYPE
FLIP-FLOP
A
B
0
1
-G R
S
C
D
(2 )
SCHMIDT
TRIGGER
(3)
SINGLE
SHOT
(4)
TIME
DELAY
r
\
LOGIC
B
ELEMENTS
FIGURE
2. 2
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
24
recovery time is required a fte r B qoes low before a p o s itiv e tra n s itio n
can again be applied a t A.
Case (4) indicates a DELAY element.
Any step tra n s itio n appear­
ing a t A is delayed a fix e d amount o f time before appearing a t B.
4)
Device Addressing and IOP Pulses
Figure 2.3 indicates how devices connected to the I/O Bus are
selected by an IOT in s tru c tio n .
When the IOT in s tru c tio n is being exe­
cuted, i t is located in the MB re g is te r - - pu ttin g the device code on
lin e s BMB 3-8 and the fun ctio n b its on lin e s BMB 9-11.
In order to
illu s t r a t e device s e le c tio n , assume the IOT in s tru c tio n
being executed
is 6576.
In Figure 2 .3 , the lower 6 -in p u t HAND gate w ill have low out­
put (a t B) only i f 57 appears on lin e s BMB 3-8.
low.
Thus fo r 6576, B is
This p a r t ia lly enables the three connected 2 -in p u t MAND gates,
allowing them to pass any generated IOP Dulses to points F, G, and H.
Since the function b its are 110 (6576), I0P2 appears a t G and I0P4
appears a t H.
No IOP pulses appear at C, D, and E since those gates
were not enabled by a low at A.
5)
Data to and from AC
An illu s t r a t io n w ill serve to show how data is tra n sfe rred from
an I/O device to the AC.
Assume th a t the devices 54 and 57 o f Figure
2,3 are devices needing to tra n s fe r inform ation to the AC.
Refer to
1
Figure 2 .4 , where a ty p ic a l AC innut bus lin e (AC 5) is shown.
lin e is biased high.
The
I f th is lin e is high at the end o f an IOP Dulse,
the contents o f AC b it p o sitio n 5 w ill remain unchanged.
I f th is lin e
is forced low by the end o f an IOP pulse, AC p o sitio n 5 w ill be forced
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
25
(
J
if) O
O
UJ
U_
0
I
in o
o
BMB
LINES
o
o
T—
o
o
m
o
DEVICE
SELECTION
t
F I G URE
2.3
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
♦3 V
26
A
b
— d
A
<
h<
Q
in
UJ
u
>
u
Q
DATA
TRANSFER
FIGURE
TO AC
2.4
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
27
to 1.
I f the AC is cleared before tra n s fe r takes place, a ll low AC bus
lin e s w ill force l ' s in those AC p o s itio n s ;
main O's.
other positions w ill re­
Assuming device 57 uses an I0P4 to put inform ation in to the
AC, then 6576 w ill cause the AC 5 bus lin e to go to the same le vel as
DATA Y a t I0P4 time.
DATA X has no e ffe c t since device 54 was not
selected.
Data bus lin e s from the AC (BAC 0-11) are wired to inputs o f gates
o f any devices re q u irin g such data. An IOP pulse o f the selected de­
vice is used to gate the inform ation where needed.
6)
SKIP and INTERRUPT
Figure 2.5 illu s tr a te s w irin g o f the SKIP and INTERRUPT bus lin e s .
These lin e s are biased high lik e the AC bus lin e s , and a ll devices
re q u irin g SKIP and INTERRUPT functions are wired to the lin e s in a
s im ila r manner.
In Figure 2 .5 , as long as the STATUS f l ip - f lo p o f
device 57 is re s e t, no action occurs.
I f some condition should cause
the f li p - f lo p to s e t, the INTERRUPT lin e goes low w ith the re s u ltin g
action previously described.
enabled.
Now i f STATUS is s e t, gate A is p a r tia lly
I f a 6571 is executed, the SKIP lin e is pulled low durina
I0P1 time and a skip occurs a fte r the IOT cycle.
I f STATUS were reset
and a 6571 executed, no subsequent skip would occur since SKIP remains
high.
C)
General In te rfa ce Description
The 8400B-INTERFACE-PDP8/I Configuration is shown in Figure 2.6.
In te rfa ce power supplies are not shown on th is diagram;
also not
shown are RE05 devices not d ir e c tly connected to the in te rfa c e .
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
In te r-
STATUS
28
NTERRUPT
URE
2.5
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
I/O BUS C O N T R O L K A 8 / I - B P O S IT IV E
I/O BUS
U
<
u
<
D IG IT A L
E Q U IP M E N T
C O R PO R ATIO N
P D P -8 /I-D
D IG ITA L
C O M P U TE R
E/VV 4K M EM O R Y
EXTENDED
A R IT H M E T IC
D EC K E 8 /I
H E W LE T T - PACKARD
M OLECULAR
R O T A T IO N A L
RESONANCE
M IC R O W A V E
SPECTROM ETER
RE 0 3 - 8 4 0 0 8
3 0 ,3 1 ,3 2 2 ,3 2 4
P LO TTE R
HP 75S 0C
PLO TTER
CONTROL
0 5 .0 6 ,0 7
O S C IL L O ­
S C O PE
TEK 5 0 3
OSCILLOSCOPE
D IS P L A Y
DEC V C 8 / I- B
M O TO R
C O N TR O L
3 2 1 ,3 3
S TEPPER
M OTOR
B ALANCE
STEPPER
MOTOR
SUBCONTROL
54
10 B IT
10 C H A N N E L
ANALOG IN PU T
M U L T IP L E X E R
D /A - 3
10 B IT
I/O BUS
TRANSFER
REGISTER
D /A -1
12 B IT
L O W -P A S S
F IL T E R
16,17
0-0
SURPLUS
PAPER TAPE
READER
0 3 ,0 4
3 3 ASR E /W
PAPER TAPE
MKS TYPE 7 7 H - 3
PRESSURE HEAD
C O N N E C TE D TO
STARK C E L L S
SYNCHRONOUS
DETEC TOR
8420A
CLOCK
DEC K W 6 /IO
TEM PORARY
D E V IC E
MKS
BARATRON
TY P E 7 7
PRESSURE
M E TE R
SYNCHRONIZER
8703 A
SW EEP
O S C IL L A T O R
H 8 1 -S S S 0 A
E L E C T R O N IC
C OUNTER
H 6 2 -5 2 4 6 L -0 2 .
0 3 .0 6
R E 0 3 -IN T E R F A C E - PO P 8/1
C O U NTER
READER/
TRANSLATOR
C O N F IG U R A T IO N
F IG U R E
2 .6
I\3
30
face devices are connected to the I/O Bus as in d ica te d , w ith device
codes indicated in the upper le ft-h a n d corners o f the relavent boxes.
Some device codes are shared by several devices — the th ir d d ig it
indicated in such codes indicates the function b its which must be pre­
sent in the IOT in s tru c tio n in order to operate the device.
Although
a ll in te rfa c e devices w ill be discussed in d e ta il la te r , a b r ie f de­
s c rip tio n o f how some operate w ith respect to the RE05 w ill be given
here.
The 8400B frequency control is obtained through the use o f D/A-1
and D/A-2.
These D ig ita l to Analog Converters convert binary numbers
(received from the PDP8/I) to voltage le v e ls .
The D/A-1 output is f i l ­
tered o f high frequency noise and then connected to the 8708A FM in p u t,
thus providing fin e frequency control o f the BWO.
The D/A-2 output is
filt e r e d and converted to an output range o f 0 to 17.5V.
I t is con­
nected to the BWO FM in p u t, thus providing PDPO/I-controlled coverage
o f the e n tire BUO range o f 26.5 to 40 GHz.
The Counter Reader/Translator can read the frequency o f the BWO
as indicated on the 5246L E le ctro n ic Counter at any time.
The A/D (Analog to D ig ita l) Converter, upon command, w ill convert
a voltage le ve l appearing at it s input to a binary number which is made
available to the PDP8/I.
range 0 to 10V.
The A/D w ill accept an input signal in the
Since most signals from the 840QB w ill be b i-n o la r, an
operational a m p lifie r before the A/D input enables signals in the ranqe
-10V to 10V to be applied.
Preceeding the operational a m p lifie r is a
10 channel input expander.
The output o f the 8420A Synchronous Detector
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
is connected to one o f these inputs to provide the PDP8/I w ith absorp­
tio n lin e data.
Not shown on Figure 2.6 is a block o f ten unassigned operational
a m p lifie rs (w ith v a ria b le attenuation co ntro ls) which have been mount­
ed on the 8400B cabinet and which are used to a lte r the amplitudes o f
various signals to ranges near the -10V to 10V range accepted by the
Input M u ltip le x e r.
This is done w ith the 8420A output signal (with
range ± IV ).
The MKS Baratron Pressure Gauge is a d ire c t pressure read-out
A.C. bridge c ir c u it .
I t is balanced by means o f stepper motors, the
n u ll- e rr o r voltage being read by the A/D.
In the balanced p o sitio n o f
the gauge, the positions o f the stepper motors in d ica te the pressure to
the PDP8/I.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
32
III.
RE05 - PDP3/I In terface
A)
Hardware and Nomenclature
V)
DEC Modules and Wire-Urap Boards
Wherever possible lo g ic gates mounted on DEC supplied printed
c ir c u it modules are employed in the in te rfa c e .1* The modules plug in to
19-inch rack mountable v/ire-wrap connector boards.
The modules are sold
w ith w arranty, and are easy to replace i f one should become d e fe ctive .
The wire-wrap term inals f a c ilit a t e simple co rrectio n o f connection mis­
takes.
Later d e le tio n s , a d d itio n s, or m odifications can be made e a s ily
on wire-wrap boards.
Some DEC modules commonly used in th is in te rfa c e
are:
M103 - Device S elector:
Contains a prewired device se lection c ir c u it
„
and two 2 -in p u t NAND gates.
M ill - In v e rte r:
Contains sixteen in v e rte rs .
Ml 12 - NOR Gate:
Contains ten 2 -in p u t NOR gates.
Ml13 - NAND Gate:
Contains ten 2 -in p u t MAND gates.
M206 - F lip -F lo p :
Contains s ix D-tyoe f lip - f lo p s .
M623 - Bus D rive r:
Contains twelve gates o f the type shown in
Figure 2 .1 , case (8 ).
When specialized c ir c u it r y had to be used, i t was generally constructed
on etched c ir c u it cards and plugged in to the v/ire-wrap boards along
w ith the DEC modules.
2)
Equipment Location
The PDP8/I processor / power supply occupies the lower h a lf o f
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
33
i t s cabinet.
Mounted immediately above the PDP8/I Control Panel is the
BNC Connector S tr ip .
Above th is on the fro n t panel is located the Burr-
Brown Rack assembly.
Immediately above the Rack is an In d ic a to r Panel
(yellow) upon which is mounted a row o f lamps, a row o f switches, and
a row o f BMC connectors.
Above the In d ic a to r Panel is a blank gray
metal panel, then one blank panel o f black p la s tic .
Above these is
located the Soroban Paper Tape Reader Transport.
The "L Frame" wire-wrap board is located behind the yellow in d i­
cator panel;
the "U Frame" board is behind the blank gray panel; the
"S Frame" board is mounted on the right-hand side of the cabinet, level
w ith the Paper Tape Transport.
The + 5V Inte rfa ce Power Supply is mounted on p art o f the S Frame.
The ± 15V In te rfa ce Power Supply and the -7V In d ica to r Lamp Power Supply
are mounted on the upper p a rt o f the rear o f the PDP8/I cabinet.
The
+ 28V Stepper Motor Power Supply is mounted on a separate chassis near
the MKS Pressure Gauge.
Stepper Motors are mounted on the face o f the MKS Gauge.
The Oscilloscope and X-Y Recorder are bench models.
Figure 3.0-A is a w irin g -s id e view o f the module locations fo r
the U and L Frames.
Figure 3.0-8 is a s im ila r drawing fo r the S Frame.
Note th a t each Frame is divided in to numbered p osition s going
across ( 1 to 32 on U and L, 1 to 12 on S) and in to tv/o v e rtic a l sec­
tio n s (A and B).
p o s itio n .
Tv/o sing le-w idth DEC modules w ill f i t in to one numbered
A module lo ca tio n is referenced by s ta tin g the frame (U, L,
or S ), the p o s itio n number (1 to 32 or 1 to 12), and the row (A o r B).
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
LAM PS & O/ASW ITC H ­ 2 ,3
ES
STE P PE R M O TO R C O N TR O L
A
u
FRAM E
B
10
11
12
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
z>
O
A
L
FRAM E
B
C ABLES
ANALOG INPUT M U L T IP L E X E R
&
A /0 CO NVERTER
D /A - 1
I/O
C O U NTER
BUFF] P L O T T E R
ER
R E A D E R / TRANSLATOR ;
CONTROL
M OTOR CONTROL
M ODULE
F IG .
LO C A TIO N S
3.0-A
CO
35
STEPPER
MO T O R
CONTROL
SURPL US P A P E R
READER
TA P E
n
i
2
a.
<
A
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CO
a:
o
in
O
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CM
CM
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it;
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■sr
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CO
cn
CM
O
CD
o
CM
2
-5
8
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co
2
2
co
in
SC
10
11
12
CM
CM
S FRAME
MODULE
LOCATI ONS
F I GURE
3.0- B
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
3G
Thus there is an Ml03 a t L6B.
Double-width modules are referenced w ith -
out the rov/ being s p e c ifie d , since both are used.
Thus there is an A801
a t L12.
3)
Drawing Conventions and Abbreviations
On a sin g le -w id th DEC module, there are 36 connection points —
18 on a side.
On a wire-wrap board s lo t p o s itio n , there are 36 cor­
responding wire-wrap term inals.
The connections and term inals are num­
bered consecutively be le tte rs (A, B, C, D, E, F, H, J , K, L, M, N, P,
R, S, T, U, V) and numbers (1 , 2 ), the le tte rs re fe rrin g to one o f 18
connections on a sid e , and the number re fe rrin g to the side o f the board
(1 is the component s id e ).
Thus the output o f a MAND gate on the module
M103 a t L6B is pin number K1.
This pin can be referred to as L6BK1.
The two inputs to the same MAND gate are a t L6BH1 and L6BJ1.
Double-width modules have twice as many pin connections but use up
two s lo ts .
Thus the method o f re fe rrin g to th e ir pin connections is the
same as above.
The lo c a tio n o f pin K1 on the lower h a lf o f the A301
module a t L I2 is simply L12BK1.
In the drawings o f Section I I I - 8 , the
pin numbers o f lo g ic element inputs and outputs are located near the
leads close to the symbol referenced.
Module locations are placed near the group o f symbols located on
th a t module.
When the group appearing on a drawing represents the ma­
j o r i t y o f lo g ic elements a t a board lo c a tio n , the module type is indicated
immediately above it s lo ca tio n coordinates.
Lines connecting an in te rfa c e device to the I/O Bus have the Bus
connections s ig n ifie d by Bus Line names appearing at one end o f these
lin e s .
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
37
Pin lo ca tio n coordinates appearing at the end o f a lin e re fe r to
the pin number on another drawing to which th a t lin e is connected.
The
word or phrase accompanying the coordinates in dica te the drawing on which
the connection is made.
A lin e term inating in an arrowhead accompanied by a le t t e r o f the
alphabet on a m u lti sheet drawing s ig n ifie s a connection to another
s im ila rly le tte re d lin e on another page o f the drawing.
The arrows
p o in t in the d ire c tio n o f "lo g ic flow " (from input to o u tp u t).
The fo llo w in g is a l i s t o f abbreviations used in the drawings and
te x t o f Section I I I - B .
I/O
Input/Output
MPXR
M u ltip le x e r
BCD
Binary-coded decimal
ADC
Analog to d ig ita l converter
DAC
D ig ita l to analog converter
MHz
Megahertz
GHz
Gigahertz
V
Volts (when a s u ffix to
DEC
D ig ita l Equipment Corporation
HP
Hewlett Packard
OP /VIP
Operational a m p lifie r
LSB
Least s ig n ific a n t b it
uSEC
Microsecond
INT
In te rru p t
CRT
Counter Reader/Translator
a number)
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
EN
Enable
P/C
P lo t complete
SPTR
Surplus Paper Tape Reader
SS
Single shot m u ltiv ib ra to r
ST
Schmidt trig g e r
CNT
Count
U/D
Up/Down
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
B)
PDP 8/1 I/O ADDITIONS
39
1) 10-channel ADC Input M u ltip le xe r
a)D escription
The Input M u ltip le x e r functions as a program co n tro lle d analog
input expander fo r the Analog to D ig ita l Converter. The heart o f the
device is a Burr-Brown Model 4047/43 m u ltip le xe r module.7 I t consists o f
ten analog in p u t channels, ten d ig ita l input channels, and a sing le ana­
log output channel. Any one o f the ten analog inputs can be switched to
the output channel by applying a lo g ic a l "1" to the corresponding d ig i­
ta l in p u t. The channel w ill remain connected u n til the d ig ita l signal
1s removed. Each in p u t channel w ill accept an analog signal o f range
±10V and i f selected w ill present the signal a t the output w ith u n ity
gain.
Channel se le ctio n is achieved by connecting the m u ltip le x e r to
the I/O BUS as an output device w ith code 54. Then, a ce rta in 10T
in s tru c tio n w ill cause the la s t fo u r binary b its in the AC to be tra n s­
ferred to a b u ffe r re g is te r in the m u ltip le x e r in te rfa c e . Assuming
these binary d ig its form a BCD number in the range 0 to 9, th is number
is then decoded, ra is in g one o f the ten m u ltip le x e r d ig it a l inputs to
lo g ic a l ” 1 ".
The MPXR module is mounted on an etched c ir c u it board and is
located along w ith it s associated in te rfa ce lo g ic in the L frame.
b )In s tru c tio n Set and Programming
Two IOT in s tru c tio n s provide control o f the m u ltip le xe r in te r ­
face:
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
6541 (ADCC)-
CLEAR ADC MPXR CHANNEL NUMBER TO 0
^
This in s tru c tio n clears the in te rfa c e b u ffe r re g is te r
to 0, thus connecting analog channel #0 to the analog
output.
6542 (ADSC)-
SET MPXR CHANNEL NUMBER TO BCD VALUE IN AC 8-11
This in s tru c tio n loads the in te rfa ce b u ffe r w ith the
contents o f AC 8-11. I f the contents form a BCD value in
the range 0-9, the correspondingly numbered analog
channel w ill be switched to the output channel.
In programming, consideration must be given to the s e ttlin g time
o f the m u ltip le x e r module when switching from channel to channel occurs.
Refer to Table ( I ) fo r a p a rtia l l i s t o f MPXR 4047/43 Specs.
c)Logic Operation
Refer to Figure 3.1. Module M103 responds to a device code o f 54
and supplies I0P1 and I0P2 pulses to the in te rfa c e . Four f lip - f lo p s
o f module M206 a t L7A form a 4 b i t b u ffe r storage re g is te r which
supplies the Ml61 decoder module. The la t t e r decodes a BCD number appear­
ing a t it s fo u r input lin e s by ra is in g the selected one out o f ten
output lin e s to lo g ic a l "1 ". These outputs are connected to the corres­
ponding d ig ita l inputs o f the MPXR module. Thus the BCD number held in
the b u ffe r re g is te r causes the correspondingly numbered analog channel
to be connected to the analog output.
A 6541 in s tru c tio n causes an inverted I0P1 pulse to appear at the
reset inputs o f the re g is te r f lip - f lo p s , thus causing a BCD 0 to be
entered. •
*
A 6542 in s tru c tio n generates an I0P2 pulse which strobes informa-
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
41
TABLE ( I )
ABRIDGED MPXR 4047/43 SPECIFICATIONS7
MINIMUM
“
STATIC ACCURACY
Gain
TYPICAL
MAXIMUM
1.00
UNITS
V/V
Gain E rror
-0.01
%
Gain D r if t (output)
-
20
yV/V/°C
-
15
V
o f 10V
INPUT CHARACTERISTICS
Analog Inputs
Signal Level
Impedance to
i 10
Sig. Com.
10
10
n
OUTPUT CHARACTERISTICS
Voltage
^10
Rated Current
-
Impedance
V
2
ma
0.1
.25
Si
Noise (d -c to lOhHz)
1
mVrms
Voltage O ffset (A djust
D r if t :
to zero)
1
mV
vs temperature
vs supply
t
20
100
v>V/°C
pV/%
,
-
.01
%
DYNAMIC RESPONSE
(a t b u ffe r output w ith IKn
source resistance in each
analog channel)
Crosstalk (20 Vpp 1kHz
microwave applied to
9 o f f channels)
S e ttlin g Tima (+ and 10 VDC applied to
a lte rn a te channels
and channels switched
se q u e n tially)
to 0.01% o f 10V
to 0.1 % o f 10V
10
5
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
o f 10V
y sec
y sec
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
AF2
0
AH2
1
AK2
BF2
BO 2
BP2
AT2
2 -A U iL
AM2
AR2
AS2
3
4 Q.D
Z
MPXR
L IO
5o
£
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6 z<
■R32.
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O6
7
BR2
BV2
A N A LO G
O UTPUT
AV2
BH2
7
J }J Z .
a
9
RL2
AN2
n o PIN 8
TO PIN 9
• R2
P2
H2
L2
M O D U LE 3 ON
BURR B RO W N
P O W E R E D RACK
M2
(1)
4 (0 )
E2
9 (1 )
F2
6 (1 )
H2
7 (0 )
J2
8 (0 )
K2
J2
D2
E2
U1
V2
U2
V1
L1
r-t
S1
V2
K2
02
N2
M 161
LB A
M 103
L7B
3d)
F2
M 206
L7 A
*-0^
H1
L2
BACO
M2
SAC 9
N1
PI
S2
T2
BAC fO
BAC 11
IOP2
10 C H A N N E L
IO P4
ANA LO G
M U L T IP L E X E R
POR
F IG U R E
IN P U T
ADC
3.1
ro
tio n from BAC lin e s 8-11 in to the re g is te r.
The MPXR c ir c u it board connections are shown in Figure 3.2.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
44
- 1 5 V D C 22
NC
20
<BT2
23
BURR-BROWN
24
10 CHANNEL
25
<BM2
26
■< B L 2
27
<BJ2
BD2
28
<BH 2
BF 2
29
<BE2
BV 2
A N A L O G I NPUT
BR 2
MULTIPLEXER
BP2
4047/43
30
AR 2
32
\ B B2
AM 2
33
<AV2
34
- < A U2
35
<AT2
36
A S2
AH 2 >
BAL
37
BAL
AN. OUT 3 8
BAL
39
AD2 >
AN. NODE
40
AC 2 >
COM
R
15 VDC
NC
R: 2 K T R I M P O T
MO UNT E D ON DEC
DO U B L E W I D T H BOARD
W 9 9 3 MPXR
MODULE
PRI NTED CI RC U I T BOARD
CONNECTIONS
FI GURE 3.2
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2) MPXR—
A/D OP-AMP:
Description
Several signals from the RE-8400B spectrometer which need to be
monitored by the PDP 8/1 are b ip o la r in nature. Since the A/D converter
interfaced to the PDP 8/1 can sample only unipolar signals o f 0 to 10 V
range, i t is necessary to s h if t the voltage level o f these signals so
th a t they may be monitored. A Burr-Brown 1556/15 operational ampli­
f i e r was selected to perform th is fu n ctio n (Figure 3 .3 ). The in p u t o f the
operational a m p lifie r is connected to the analog output o f the MPXR. The
a m p lifie r takes the input s ig n a l, halves i t , subtracts fiv e v o lts , and
in v e rts the re s u lt. Thus a voltage on a selected input channel o f the
MPXR in a range -10 to 10V w ill give a 10 to OV range at the a m p lifie r,
output, where OV input corresponds to 5V a m p lifie r output. The -5V
s h if t p o te n tia l is provided by a voltage d iv id e r in the c ir c u it . This
voltage p o in t is tapped, decoupled, and connected to MPXR analog in p u t #1.
The OP AMP and associated c ir c u it r y are contained in module #3
o f the Burr-Brown Powered Rack (Figure 3.4) and employ the model
506/16 ±15 VDC power supply on the rack.
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Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
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MPXR O P -A M P
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M OUNTED IN B U R R -B R O W N
M O U N TE D IN B U R R -B R O W N
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M ODULE
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4
(L O W )
TRIM POT
(L O W )
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TO M P X R
INPUT 1
(L 1 0 A H 2 )
TRIMPOT
LO W -P A S S
F IL T E R
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B U R R -B R O W N
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TRIMPOT
FR O M M PXR
OUTPUT
(L10A N 2)
(H IG H )
BURR-BROWN
1 59 6 *19
TO A /D
IN PU T
(L 1 2 B V 2 )
2 .2 K
-2 6 V
OUTPUT
3>-
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M PXR O P E R A T IO N A L A M P L IF IE R
&
D /A - 2 O P E R A T IO N A L A M P L IF IE R
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R E S IS T A N C E
1
V A L U E S IN O H M S
C A P A C IT A N C E
S C H E M A T IC S
V A LU ES IN M F D
F IG U R E
3 .3
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3) 1 0 -B it Analog to D ig ita l Converter
m
a)D escription
The A/D converter consists o f a DEC A801 A/D converter module
and associated in te rfa c e lo g ic . The converter accepts an input analog
signal in the range 0 to 10V and upon command w ill convert the signal
amplitude to a binary number in the range 0 to 7774g in a lin e a r
manner. When conversion is complete (in about 10y sec.) an "A/D done
pulse" is issued by the converter module, in d ic a tin g th a t the 10 b it
binary value is a va ila b le in it s b u ffe r re g is te r. Accuracy o f conversion
is 0.1% f u l l scale ± %LSB.
The in p u t o f the A/D converter is connected to the output o f the
MPXR-A/D OP AMP and is thus the la s t stage o f a m u lti-in p u t ADC system.
The A/D converter is an input device (Code 53) on the I/O BUS.
Inte rfa ce lo g ic consists o f bus d rive rs which put output inform ation
on the AC bus upon program command, and a fla g f lip - f lo p which is set by
the A/D done pulse and reset by the read A/D in s tru c tio n . This fla g when
set can cause program in te rru p t i f the in te rru p t f a c i l i t y is on, and w ill
cause a skip upon execution o^ the SKIP ON A/D FLAG in s tru c tio n .
The converter and associated in te rfa ce lo g ic are located on the L
frame.
b )In s tru c tio n Set and Programming
The A/D converter is co n tro lle d by three in s tru c tio n s :
6351 (ADSF)-
SKIP ON ADC FLAG
Skip the in s tru c tio n fo llo w in g 6531 i f ADC fla g is se t.
Otherwise, execute the fo llo w in g in s tru c tio n . A set ADC
fla g indicates th a t A/D conversion is complete.
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6532 (ADCV)-
START ADC SEQUENCE
49
Execution o f th is in s tru c tio n resets the ADC fla g and
issues the A/D s ta r t pulse to the converter. About 10y
sec. la te r the converter w ill fin is h and issue a A/D
done pulse which sets the ADC fla g .
6534 (ADRB)-
OR ftDTBUFFFK' INTO AC 0-9 CLEAR FLAG
The ADC fla g is cleared, and the complement o f the 10 b it
ADC b u ffe r is lo g ic a lly ORed w ith the contents o f Ac 0-9.
AC 10-11 are not a ffe cted .
Normally the AC must be cleared before issuing a 6534 in s tru c tio n .
Then fo r ananalog signal
being applied to a selected MPXR input channel,
the ADRB in s tru c tio n would place the fo llo w in g octal values in the AC
fo r the indicated analog le v e ls :
-10V = 0000
- 5V « 1774
OV - 3774
5V = 5774
10V = 7774
On the yellow in d ic a to r panel, switch #1 UP enables the ADC Skip
and In te rru p t fu n c tio n s , and lamp #6 indicated when the ADC fla g set i f
switch #1 is up.
c)Logic Operation
Refer to Figure 3.5. Module M103 passes I0P1, I0P2, I0P4 pulses
when selected by device code 53. The fla g f lip - f lo p a t L7A is set
by an A/D done pulse from the A801 converter module, and is reset by
e ith e r an I0P2 or I0P4 pulse. When panel switch #1 is up, the input
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CONVERTER
B IT
DIGITAL
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Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
TO
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ANALOG
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51
a t U22BA1 in h igh, allow ing the f l ip - f lo p to control the s k ip , in te rru p t
and lamp d riv e r fu n ctio n s. Switch #1 down disables these fu n ctio n s. A
6532 in s tru c tio n in it ia t e s the conversion sequence fo r the A801. The
I0P1 pulse is wired fo r the skip fu n c tio n , the I0P4 gates the comple­
ment o f the A801 output onto the AC bus.
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4) 12 B it , Oto 10V D ig ita l to Analog Converter D/A-l
52
a)D escription
The d ig ita l
to
range 0 to 7777g
to
analog converter converts a 12
b i t binary numbero f
an analog voltage in the range 0 to 1OV. A change
o f 1 in the binary in p u t value produces a 0.0025 v o lt change in the
output. A binary 0 corresponds to 0 v o lts output; an input value 7777g
yie ld s 9.9975 v o lts output. Accuracy is ±0.015% f u l l scale at 25° C.
S e ttlin g time is 50y sec. fo r maximum output change.
The purpose
of
th is DAC is to provide ameans fo r PDP 8/1 to
produce high re s o lu tio n microwave frequency control over small frequency
ranges. This can be re alized when the DAC output is connected to the
8708A synchronizer FM in p u t. The synchronizer can be adjusted to pro­
vide a 3MHz change to a 40MHz change in microwave output fo r a 10 v o lt
DAC output change.
The DAC is an output device (Code 551) on the 1/0 bus. The
device consists o f a DEC A613 DAC module, an A704 reference power
supply, an external 12 b i t input b u ffe r consisting o f 12 f lip - f lo p s on
two M206 modules. A sin g le in s tru c tio n controls the DAC.
b )In s tru c tio n Set
6551 (DALI)-
LOAD AC INTO D/A-l BUFFER
The contents o f the AC are loaded in to the inp ut b u ffe r
o f the DAC. The analog output w ill s e ttle w ith in 50p
sec. o f in s tru c tio n execution.
c)Logic Operation
Refer to Figure 3.6. Module M103 a t L18B responds to device
code 55. In s tru c tio n 6551 y ie ld s a t I0P1 pulse at the clock inputs o f the
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CONVERTER
ANALOG
TO
DIGITAL
o u-
o o
Z -i
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12 b i t f l i p - f lo p b u ffe r. This pulse strobes in the inform ation on lin e s
BAC 0-11. The "1" outputs on the f lip - f lo p s drive the DAC binary input
lin e s . An A704 voltage reference module supplies -10 v o lts reference
to the DAC.
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55
5) 12 B it , 0 to -10V DAC (D/A-2) and 10 B it, 0 to -10V DAC (D/A-3)
a)D escription
The two DAC's are id e n tic a l except in re solu tio n and accuracy.
The 10 b it DAC is accurate to ±0.1% f u l l scale
± h
LSB plus reference
supply e rro rs . The 12 b i t DAC has accuracy o f ±0.05% f u l l scale
± h
LSB
plus reference supply e rro rs . The 10 b i t DAC converts, upon command, a
binary value in range 0 to 7774g located at AC 0-9 to an analog voltage
le ve l in the range 0 to -10V. The 12 b i t DAC converts a binary value
in range 0
to 7777g in AC 0-11 to an analog voltage level in
0 to -10V.
S e ttlin g times are less than 50y sec.
the range
The .purpose o f the 12 b i t DAC is to provide PDP 8/1 c o n tro lle d coarse
frequency tuning o f the H81-8690A microwave source. This is achieved by
converting the signal output o f the DAC to 0 to +17.5V, f ilt e r in g out
noise, and connecting th is output to the FM input on the 8690A. The
PDP 8/1 can then vary the microwave frequency over the f u l l range o f
26.5 to 40GHz.
As o f y e t, the 10 b i t DAC has no s p e c ific assignment.
Both DAC's are b u ilt by Computer Products o f Fort Lauderdale,
F lo rid a . The binary inputs are compatible w ith the TTL lo g ic used by
the PDP 8/1. They are constructed on PC boards and are mounted together
in a small shielded case located on the rear o f the Burr-Brown Powered
Rack. They employ the Burr-Brown Rack ±15V power supply fo r both reference
and power.
The tv/o DAC's are connected to the I/O bus as output devices
(code 552 fo r 12 b i t DAC and 554 fo r 10 b i t DAC). Each DAC is co n tro lle d
by one in s tru c tio n . The in te rfa c e lo g ic consists o f the M103 module at
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
5F
L18B which is shared w ith the 12 b it 0 to 10V.DAC; an Ml01 module a t
U23A which gates the AC data to the DAC's during a 55 code I/O in s tru c tio n
o n ly; some in v e rte rs on a shared M ill module at U23B.
b )In s tru c tio n Set
One in s tru c tio n operates the 12 b i t 0 to -10V DAC (D/A-2):
6552 (DAL2)-
LOAD AC INTO D/A-2 BUFFER
The contents o f the AC are loaded in to the DAC b u ffe r when
the I0P2 pulse is generated.
S im ila rly one in s tru c tio n operates the 10 b i t 0 to -10V DAC (D/A-3).
6554 (DAL3)-
LOAD AC 0-9 INTO D/A-3 BUFFER
The contents o f AC locations 0-9 are loaded in to the DAC
b u ffe r when the I0P4 pulse is generated.
c)Logic Operation and Connections
Refer to Figure 3.7. The two DAC's are mounted together in a
shielded box. Binary input pins and power supply pins are tie d together.
Raising e ith e r strobe lin e to lo g ic a l 1 w ill allow binary in p u t levels
to enter the in p u t b u ffe r o f the selected DAC. Dropping the strobe to "0"
w ill cause the corresponding b u ffe r to hold the data presented to i t at
the time the strobe drops. The output o f the 10 b i t DAC is connected to
a fro n t panel ja c k , the output o f the 12 b i t converter goes to a low
pass f i l t e r and then on th an OP AMP (Figure 3.3) fo r conversion to
0 to +17.5V output. Other lin e s are brought out and connected to two
term inal s trip s mounted a t the rear o f the Burr-Brown rack (Figure 3 .9 ),
and labeled as indicated in Figure 3.7 and Figure 3.8.
Referring to Figure 3.8, a cable leads from the term inal s trip s
to unused wire wrap pins a t U32A.
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60
The M103 a t L18B (Figure 3.6) enables the Ml01 in p ut gates when
device code 55 is presented. Since the input gates w ill in v e rt the signals
from the AC bus, in v e rte rs are placed behind the gates before signals
are put on the cable to the DAC's. These in ve rte rs are located on boards
a t U23B, L18B, and U25A. The I0P2 pulse output from the M103 is connected
to the 12 b i t DAC strobe, w hile the I0P4 pulse output is connected to the
10 b it DAC strobe.
d )F i1te r - OP AMP Operation
The output o f the D/A-2 is f ilt e r e d by a low-pass f i l t e r mounted
on the rear o f the Burr-Brown Rack (Figure 3 .9 ). The signal is then
passed to the input o f an OP AMP c ir c u it (Figure 3.3) located in module
#4 o f the Burr-Brown Rack. The OP AMP is powered by a Burr-Brown type
505 ±26VDC power supply mounted on the rear o f the rack. This supply is
activated when PDP 8/1 power is turned on. The OP AMP in v e rts , am plifies
and f i l t e r s the in p u t signal such th a t the output is in the range 0 to
+17.5V. The output is a va ila b le a t a BMC connection on the module #4
face. Removing th is faceplate enables one to reach two trim p o ts: the
upper being zero adjust and the lower being gain control fo r the OP
AMP c ir c u it .
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
6) I/O Bus Transfer Register M735
a)D escription
The M735 Bus Transfer Register is a DEC module incorporating
in te rfa c e c ir c u it r y designed to provide easy connection o f external
d ig it a lly c o n tro lle d devices to the PDP 8/1 I/O bus. I t consists o f
device se le ctio n c ir c u it r y , fun ctio n operation c ir c u it r y , a data output
b u ffe r re g is te r, and a data input gate/bus d riv e r.
The M735 is treated as an I/O device on the I/O bus and is
assigned device code 15. I t is located a t L19.
b )In s tru c tio n Set: Refer to Figure 3.10. The in s tru c tio n set is
dependent o f the type external device connected to the module:
6151-
Inverted I0P1 pulse a t pins BR1 used fo r skip fu n ctio n
6152-
Inverted I0P2 pulse a t BP1 used fo r AC cle a r
6153-
toad output b u ffe r re g is te r,
6154-
OR input data in to AC
6155-
Load output b u ffe r re g is te r,
6156-
6152, then 6154
6157-
6153, then 6154
then 6152
then 6154
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
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7) D ig ita l Counter Reader/Translator
63
a)D escription
The purpose o f the Reader/Translator (CRT) is to enable the PDP
8/1 to read the microwave frequency value from the HP H21-5246 L d ig i­
ta l counter.
The counter w ill display the 8 most s ig n ific a n t d ig its o f a count
on a NIXIE tube d is p la y . Each tube is driven by a fo u r-lin e binary
coded decimal counter. The output le ve l o f each counter are a va ila ble
a t the rear o f the instrum ent as a 4221 weighted binary code. The deci­
mal d ig its and th e ir corresponding 4221 codes are lis te d in Table I I .
In general, the decimal d ig its encoded th is way would be unusable by a
computer program re q u irin g the value o f the counter output. A much more
convenient code is the fa m ilia r 8421 weighted binary code (see Table I I ) .
Code conversion could be e ffected e ith e r by softv/are ro utin e or by a
hardware decoder. The la t t e r was chosen in order to save both computer
time and storage space.
The outputs at the 5246-L are not compatible w ith TTL lo g ic , since
they are high impedence, w ith a lo g ic a l 1= +18V and a lo g ic a l 0= -8V.
Thus the in te rfa c in g c ir c u itr y must include converter a m p lifie rs to
y ie ld compatible lo g ic le v e ls .
The 8 s ig n ific a n t decimal d ig its o f counter readout y ie ld 32 to ta l
lin e s o f corresponding binary output at the rear o f the counter.
Since the AC can accept only 12 binary b its o f inform ation per I/O
in s tru c tio n , i t is necessary th a t the counter value be read in several
sections.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
64
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Since the values o f the decimal counters are changing during the
count cycle , they cannot give a co rre ct frequency count during th a t
period.
The counter issues a +13V to OV high impedence step signal on
a separate lin e when the counter has completed a count cycle, in d ic a tin g
th a t the counter can be read.
The re a d e r/tra n s la to r was therefore constructed to :
1) Sense the read pulse from the 5246-L and provide th is inform ation
to the PDP 8/1 by means o f the skip and in te rru p t fu n ctio n s.
2) Convert the 5246-L output signals to
TTL compatible levels
3) Divide the counter output lin e s in to
three groups, each o f which
can be read in by an I/O in s tru c tio n .
4) Translate each d ig it from 4221 code to 8421 code as i t is being
tra n sfe rre d from 5246-L to AC.
The re a d e r/tra n s la to r is connected to the I/O bus as an input de­
vice w ith code 14.
Signal leve l conversion is achieved w ith 32 simple
tra n s is to r in v e rtin g a m p lifie rs mounted on four PC boards.
Gating lo g ic
steers e ith e r the two le a s t s ig n ific a n t, three middle s ig n ific a n t, or
three most s ig n ific a n t decimal d ig its o f inform ation to the AC.
Before
reading the AC, the d ig ita l inform ation is translated from 4221 code to
8421 code by three id e n tic a l tra n s la tio n lo g ic networks,
one fo r each
decimal d ig it o f fo u r binary lin e s .
The 5246-L counter indicates the frequency o f the 8690A microwave
source, which is e ith e r o f f o r operating in the reaion 26.5 to 40 GHz.
Thus the most s ig n ific a n t d ig it o f the counter w ill always have value
0 ,2 ,3 , or 4.
Referring to Table I I i t is seen th a t the 4-weighted
binary d ig it fo r these values is 0.
Thus th is inform ation b i t does not
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
66
have to be tra n sfe rre d (since it s value is always known) and the le vel
converter a m p lifie r thus freed is used to convert the read pulse to
TTL lo g ic le v e ls . This pulse w ill a c tiva te the skip and in te rru p t
functions o f the PDP 8/1. I t occurs a fte r each 5246-L count cycle . The
skip and in te rru p t functions are manually armed by ra is in g panel switch
#3. In d ic a to r lamp #7 indicates the presence o f the read pulse i f switch
#3 is up.
Logic fo r the re a d e r/tra n s la to r is located on the L frame.
b )In s tru c tio n Set and Programming
The reader tra n s la to r is co n tro lle d w ith four in s tru c tio n s :
6144 (CRTS)-
SKIP ON CRT FLAG
This in s tru c tio n w ill cause a skip during the time the
5246-L count complete pulse is a c tiv e , in d ic a tin g the
counter can be read.
6145 (CRTL)-
CLEAR AC AND LOAD 2 LOW ORDER BCD DIGITS INTO AC 0-7
The two low order 8421 coded d ig its are loaded in to
AC as indicated in Figure 3.11. 0 is loaded in to AC 8-11.
6146
(CRTM)- CLEAR AC AND LOAD 3 MIDDLE ORDER BCD DIGITS INTO AC 0-11
AC is loaded as indicated in Figure 3.11.
6147 (CRTH)- CLEAR AC AND LOAD 3 HIGH ORDER BCD DIGITS INTO AC 0-11
AC is loaded as indicated in Figure 3.11.
As presently w ired, the count-complete pulse drives the skip
and in te rru p t lin e s d ir e c tly , w ith ou t being buffered by a fla g f lip - f lo p .
Thus the in te rru p t signal cannot be turned o f f , and i f the PDP 8/1 is in
the in te rru p t mode, in te rru p ta b le in s tru c tio n s w on't be executed fo r the
30 m illiseconds during which the count complete pulse is a c tiv e .
c)Logic Operation and Connections
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
I
1 |2 I 3
4 i 5 |6 i 7
o
101
104
107
' 2 ! 1
00
8*4
103
106
ro
O
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Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Reader/ T ra n s la to r Accumulator Loading Scheme
8 i 9 110 1 11
0
102
105
8 14 1 2 1 1
FIG U R E
3.11
AC POSITION
6145
6146
6147
POSITION BCD
i ) Cable Connections
68
The CRT-5246L lin k is e ffected by means o f a 32 conductor cable,
connected a t the PDP 8/1 to wire wrap term inals on the L frame correspond­
ing to the le ve l a m p lifie r in p u ts, and terminated a t the other end w ith
a 32 contact connector. A 32 to 50 contact adapter completes connection
to the 5246L as indicated in Figure 3.12, Pin connections fo r the cable
and adapter are shown in Table I I I . When PDP 8/1 connection is not e ffe c t­
ed, the 5246L binary outputs d rive the 8429A Frequency Marker on the 7127A
S trip Chart Recorder. The cable from the 8429A was terminated w ith a
32 pin connector wired as shown in Figure 3.13. This cable plugs in to
the adapter as shown in Figure 3.12 when the PDP 8/1 is not hooked up to
the 5246L.
ii) L o g ic Operation
Input lo g ic le ve ls from the 5246L are f i r s t converted to TTL
lo g ic le v e ls by 32 in v e rtin g a m p lifie rs mounted on 4 sin g le -w idth DEC
PC boards. C irc u its and pin connections -For a ty p ic a l in v e rtin g ampli­
f i e r board are shown in Figure 3.14.
The code tra n s la to r c ir c u it operates on the complement o f the 4221
BCD code to give the complement o f the 8421 code (Table
I I ) . The 4221
code in p u t is comlemented by the in v e rtin g a m p lifie rs , and tra n s la to r
output complement 8421 code is recomplemented upon passing through the AC
bus d riv e rs , so th a t 8421 code appears in the AC. Translator lo g ic d ia ­
grams and equations are shown in Figure 3.15.
Figure 3.16 shows the complete CRT lo g ic . Three duplicate tra n s la to r
c ir c u its OR 8421 BCD d ig its in to AC 0-3, 4-7, and 8-11 by means o f the
M623 bus d riv e r card a t L25A.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
R e a d e r/ T r a n s la to r Cable C o n n e c t io n
32 PIN CONN.
TO PDP 8 /!
READ/
32 PIN CONN.
TRANSLATE
INTERFACE
HP5246L
5 0 PIN CONN.
ELECTRONIC
COUNTER
5 0 PIN
32 PIN CONN.
CONN..
TO HP 8 42 9 A
FREQUENCY
MARKER
MIN. BNC
FIG U R E 3.12
TABLE I I I
Decimal
D ig it
Group
Order
Decimal
Di gi t
Signi ficance
10
L
70
Pin
Number:
5246-L
50 Pin
Connector
Binary
Weight
Transferred
to
Accumulator
P osition
4
2
2
1
0
1
2
3
20
19
4
3
29
28
4
3
4
2
2
1
4
5
6
7
18
17
2
1
27
26
2
1
4
2
2
1
0
1
2
3
26
25
10
9
35
34
10
9
4
2
2
1
4
5
6
7
24
23
8
7
33
32
8
7
4
2
2
1
8
9
10
11
22
21
6
5
31
30
6
5
32
48
40
16
15
Pin
umber:
2 Pin
nnector
0
W
10c
10
H
I
D
D
10
L
E
10
_______ PRINT COMMAND
7
H
2
2
1
2
1
3
31
16
15
6
10
4
2
2
1
4
5
6
7
30
29
14
13
39
38
14
13
5
4
2
2
1
8
9
10
11
28
27
12
11
37
36
12
11
10
I
G
H
10
GND
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
50
4 6(to 8NC)
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
F re q u e n c y M a r k e r Cable C o n n e c t o r M o d ific a tio n
32
PIN C O N N E C T O R
a —O
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CASE
32 0
BLU
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YEL
ORG
RED
BLK
VL T
CABLE
TO H P 8 4 2 9 A
FREQUENCY
F IG U R E
3 .1 3
MARKER
M IN .
B NC
Reader / Translator
Input Amplifier
Board
S chem atic
77
CM
CM
CM
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3 .1 6 - C
FIGURE
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78
Connected to the inputs o f each tra n s la to r c ir c u it are the outputs
o f an Ml69 gating module, one fo r each tra n s la to r. In ve rtin g a m p lifie r
outputs fo r 3 4221 coded BCD d ig its appear a t the AND gate inputs o f
each Ml69. Three control lin e s are connected to the remaining AND gate
inputs in such a manner th a t when any one control lin e is lo g ic a l 1
and the other two are lo g ic a l 0, one o f three groups o f d ig its (low ,
m iddle, or high order) w ill be selected and steered to the tra n s la to r
c ir c u it s . A c ir c u it consisting o f two flip - flo p s and two NOR gates de­
codes the device in s tru c tio n s e t, insuring th a t the M169 control lin e s
are a ll low fo r the skip in s tru c tio n , and th a t only one lin e is high fo r
each tra n s fe r in s tru c tio n .
The AC is cleared on 164X, where X= (1 ,2 ,3 ,5 ,6 ,7 ). When
X -
(1 ,2 ,3 )
no tra n s fe r in to AC takes place, since I0P4 enables the bus d riv e r gates.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
8) P lo tte r Control
79
a)D escription
The P lo tte r Control in te rfa c e provides sk ip , in te rru p t and p lo tte r
enable functions fo r a HP 7590C-01 X-Y recorder8when the recorder is
driven by the PDP 8/1 OSCILLOSCOPE DISPLAY outputs.
The X-Y recorder is a bench-top model w ith e le c tro s ta tic paper
hold-down. W riting area is 10 x 15 inches. The ZERO p oin t may be set
anywhere on the w ritin g area; d e fle c tio n o f the recording pen o r
character p rin te r in the X or Y d ire c tio n is proportional to the voltage
applied at the X or Y inputs re sp e ctive ly.
The p lo tte r is enabled by applying -3V to the ENABLE BIAS in p u t.
When th is in p u t is 0V, the p lo tte r is disabled, allow ing an oscilloscope
to be used fo r d isp la y purposes w ith the p lo tte r connected to the o s c ill­
oscope d isp la y w ith power on.
When connected to the PDP 8 /1 , the p lo tte r is normally operated in
the mute mode. An external SEEK pulse (from PDP) in itia te s a p lo t c y c le -causing the p lo tte r to move the pen to the p o sitio n indicated by the X
and Y voltage le v e ls , f i x the pen a t th a t p o in t, and issue a p lo t com­
p lete pulse to the external control device. In the mute mode, the p lo tte r
can e ith e r draw continuous lin e s from p o in t to p o in t, or p r in t a p o in t
or character a t each p lo ttin g p o s itio n . In the m ute-line mode, the f i r s t
SEEK pulse causes the p lo tte r to move the pen to the desired p o s itio n , and
the pen to drop to the paper ju s t before the PLOT COMPLETE pulse is
given. The pen then remains on the paper fo r a ll succeeding SEEK pulses.
The pen is raised by d isa b lin g the p lo tte r (removing enable b ia s ).
In the m ute-point mode, the pen or character p r in te r remains raised
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
8°
except fo r a b r ie f time immediately a fte r the pen has been fix e d a t a
p lo ttin g p o sitio n and ju s t before the PLOT COMPLETE pulse is issued.
When connected to the PDP 8 /1 , the p lo tte r X and Y axis inputs
are driven by the OSCILLOSCOPE DISPLAY X and Y axis outputs, and the
SEEK pulse is supplied by the OSCILLOSCOPE DISPLAY Z axis output . The
DISPLAY OUTPUTS are a t BMC connectors mounted on a metal s t r ip (Figure
3.17) immediately below the BURR BROWN RACK on the PDP 8/1 fro n t panel.
The ENABLE BIAS output and PLOT COMPLETE pulse input are also located on
th is s t r ip .
The p lo tte r control has been assigned a device code 50. The skip
and in te rru p t functions are manually enabled by ra is in g panel switch #4.
In d ic a to r lamp #9 on indicates the PLOT COMPLETE fla g is on i f switch
#4 is up. Lamp #8 on indicates th a t -3 v o lts enable bias in being applied
to the p lo tte r .
b )In s tru c tio n Set and Programming
Three in s tru c tio n s are associated w ith the p lo tte r c o n tro l:
6501 (PLSF)-
SKIP ON PLOTTER FLAG
In s tru c tio n causes skip i f PLOTTER FLAG has been turned
on by a PLOT COMPLETE pulse.
6502 (PLD)-
DISABLE PLOTTER
In s tru c tio n removes enable bias from p lo tte r .
6504 (PLCE)-
CLEAR FLAG, ENABLE PLOTTER
P lo tte r fla g f lip - f lo p is re se t, -3V enable bias is applied
to p lo tte r*
The OSCILLOSCOPE DISPLAY in s tru c tio n s 3are used to run the p lo tte r .
The SEEK pulse is supplied w ith an INTENSIFY in s tru c tio n (DIX, DIY, DXS
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
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82
or DYS). The brightness re g is te r (BR) must have been set previously to
e ith e r MEDIUM (6076) or MAXIMUM (6077) brightness so th a t the SEEK pulse
w ill be o f s u ffic ie n t magnitude to be detected by the p lo tte r.
c)Logic Operation
An M103 a t L27B selects the device code 50. The ENABLE BIAS f l i p flo p (Figure 3.18) is reset when PDP 8/1 power comes up. A resistance v o lt­
age d iv id e r mounted on a PC card at U27B supplies 0 vo lts to the ENABLE
BIAS output. When the ENABLE BIAS f l ip - f lo p is se t, i t drives a gate
which grounds p a rt o f the voltage d iv id e r, causing -3 v o lts to appear at
the ENABLE BIAS output.
The PLOT COMPLETE fla g f lip - f lo p is set d ir e c tly by the PLOT COM­
PLETE pulse.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
3.18
FIGURE
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U S 1A M 8
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9) Surplus Paper Tape Reader
a)D escription
84
The Surplus Paper Tape Reader (SPTR) consists o f a Soroban paper
tape tra n sp o rt9and in te rfa c in g hardware. The control in s tru c tio n s are
e ffe c tiv e ly the same as those which operate the 33 ASR paper tape reader.
The tra n sp o rt can perform 15 read operations per second; paper tape
hole sensing is mechanical. The tra n sp o rt can read e ith e r one e ig h tchannel paper tape, or two such tapes sim ultaneously. Thus hardware
was implemented to read e ith e r e ig h t channels o f one tape in to AC 4-11
or s ix channels each o f two tapes in to AC 0-11.
The tra n sp o rt consists o f supply and takeup spools, read heads,
d riv in g motor to run read mechanics and rewind fu n c tio n , read-rewind
sw itch, motor power sw itch, rewind solenoid, and read cycle solenoid.
A 90V power supply and solenoid d riv e r (fig u re 3.19) was b u ilt and mounted
on the tra n sp o rt frame to power the rewind solenoid, and to a c tiv a te the
read solenoid when a TTL lo g ic signal is applied to the d riv e r in p u t.
Most o f the in te rfa c in g lo g ic is contained on the S frame.
The SPTR is treated as an I/O device on the I/O bus. I t has
device codes 15 and 17. The motor d rive power switch also powers the
solenoid power supply. Raising panel switch #2 enables the SPTR -Hag
and in te rru p t fu n ctio n s. In d ic a to r lamp #14 is on when the SPTR fla g is
on i f switch #2 is up.
b )In s tru c tio n Set and Programming
Six in s tru c tio n s control operation o f the SPTR:
6161 (TRS1) -
SKIP ON SPTR FLAG
A skip occurs i f the SPTR FLAG is on, in d ic a tin g a
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
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SURPLUS PAPER T A P E R EA D E R
TRANSPORT
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character has been read in to the reader b u ffe r and is
ready to be tran sfe rred to the AC.
6162 (TRC1) -
CLEAR SPTR FLAG, CLEAR AC
6164 (TRR1) -
READ
BUFFER INTO AC 4-11, LOAD CURRENT
TAPE CHARACTER INTO BUFFER, ADVANCE SPTR TO NEXT CHAR­
ACTER POSITION, SET FLAG
The e ig h t b i t code presently in the read b u ffe r is OR'ed
in to AC 4-11 (Figure 3 .20), and the reader solenoid allows
the read mechanics to sense the holes in the paper tape
character p o sitio n then located a t the read head. The 8
b i t code sensed is read in to the reader b u ffe r, the paper
tape is advanced one character p o s itio n , the mechanics
h a lt and the fla g is set.
6171 (TRS2)-
SKIP ON SPTR FLAG
Equivalent to 6161
6172 (TRC2)
CLEAR SPTR FLAG, CLEAR AC
Equivalent to 6162
6174 (TRR2)-
READ
BUFFER INTO AC 0-11, LOAD CURRENT TAPE CHARACTER
INTO BUFFER, ADVANCE SPTR TO NEXT CHARACTER POSITION,
SET FLAG.
S im ila r to 6164 except th a t two tapes are being read,
channels 1 to 6 o f the tape nearest tra nspo rt being OR'ed
in to AC 6-11; channels 1 to 6 o f the tape fa r from trans­
p o rt being OR'ed in to AC 0-5 (Figure 3.20).
c)Logic Operation and Cable Connections
Figure 3.20 shows the o rie n ta tio n o f the tapes passing over the
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Paper Tape O r ie n ta t io n and AC Loading Scheme
TRANSPORT
G U ID E E D G E
—
TAPE
D IR E C T IO N
TAPE 1
AC
INST.
6 16 4
6174
P O S IT IO N
...... j_
..... ,.j
8 7
14 13 12 11 10 9
(0)
(0)
(0 )
(0 )
T A P E P O S IT IO N F R O M
W H IC H
6
6
5
5
4
4
IN F O R M A T IO N
3
3
2
2
1
1
TRANSFERRED
O 10
O
12
TAPE 2
O 13
O
14
O
16
co
F IG U R E
3 .2 0
88
tra n s p o rt read head. The symbol "S" re fe rs to the paper tape sprocket
hole channel. The fig u re also shows where the inform ation from each tape
is placed in the AC during the read in s tru c tio n s 6164 or 6174. The
symbol "0" indicates th a t a "0" is OR'ed in to the indicated AC p o sitio n
during the 6164 in s tru c tio n . A hole punched in the tape in a channel
p o s itio n is read in to the AC as a lo g ic a l 1; a non-punch reads as a
lo g ic a l 0.
The tra n sp o rt read head consists o f a group of 16 switch assemblies
one per channel. During the mechanical read cycle, switch contacts fo r a
channel remain open i f no hole is sensed, and closure to a common ground
is made i f a hole is sensed. Thus one side o f a ll switch contacts are
grounded and the other sides are brought out to a 37 pin connector.
When
the aboveswitches are in hole sensing p o sitio n during
read cycle , a READER COMMON CONTACT is grounded, in d ic a tin g th a t
the
in fo r ­
mation tra n s fe r can take place. This contact output also appears at the
37 pin connector.
A cable leads from the connector to two K581 modules on the S
frame where each contact is F ilte re d and flo a te d a t +5 v o lts . A K581
f i l t e r output is lo g ic a l 1 when it s corresponding contact is open, and
lo g ic a l 0
when th a t contact is closed. Table IV lis t s the cable
ions from
tra n sp o rt to K581 modules.
connect
The M103 module a t S8B (Figure 3.21) selects device codes 16 and
17. The MODE f li p - f l o p is set on a 6164 and is reset on 6174. When th is
f l i p - f lo p is s e t, inputs to reader b u ffe r f lip - f lo p s 0-3 are ^orced
zeros, and tape channel outputs 7 and 8 are steered to b u ffe r inputs
5 and 4. When the f l i p - f lo p is re se t, b u ffe r inputs 0-3 are enabled to
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
89
TABLE IV
TAPE T R A N S P O R T _______
Tape
Hole P osition
Connector
Pin Number
1
1
2
2
3
K581_____________ ____
Location
S12B
Input Term
Number
Output
Pin Number
I
D2
"
2
F2
3
”
3
J2
4
4
"
4
L2
5
5
“
6
N2
6
6
"
7
R2
7
7
1
D2
8
8
"
2
F2
9
9
"
3
J2
10
10
”
4
L2
11
11
"
6
N2
12
12
"
7
R2
13
13
"
8
T2
14
14
"
9
V2
5
C2 (GND)
8
T2
S12A
20,21,33,17
reader
conuion
32
S12B
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Ia C 1 1
IaCIO
AC 9
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INPUTS
O
POSITION
TAPE
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! AC 3
IA C 4
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AC 6
Ia C 7
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Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
9?
accept tape channel outputs 14-11, and tape channel 9 and 10 are steered
to b u ffe r inputs 5 and 4.
In a read in s tru c tio n (6164 o r 6174), the I0P4 pulse switches the
MODE f l i p - f lo p as described above, strobes the contents o f the reader
b u ffe r onto the AC bus, and sets the SOLENOID f lip - f lo p . This f lip - f lo p
then a ctiva te s the read solenoid by applying a +3 v o lt signal to the
solenoid d riv e r (Figure 3.19). This in itia t e s the mechanical read
cycle. When a ll read head contacts are in hole sensing p o s itio n , the
reader mechanics causes the READER COMMON contacts to close momentarily.
This closure is detected by the M501 Schmidt T rigger module which trig g e rs
the One Shot Delay module
M302 and simultaneously strobes tape
channel inform ation in to the reader b u ffe r, and resets the SOLENOID
f l i p - f lo p .
As the mechanical read cycle progresses, the READER COMMON contacts
open, causing the M501 Schmidt Trigger to recover. The read head contacts
return to t h e ir non-sensing p o s itio n s , the paper tape is advanced one
character p o s itio n , and the read cycle mechanically ends.
The M302 One Shot Delay has been adjusted to recover immediately
a fte r the end o f the read cycle. When i t recovers, i t sets the FLAG f l i p flo p .
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
TO) Motor Control
93
a)D escription
The Motor Control (MC) in te rfa c e lo g ic allows motors to be run as
sp e cifie d by the PDP 8/1. The Motor Control i t s e l f is designed to d ir ­
e c tly control the operation o f ordinary ro ta ry DC or AC motors. I t is
used along w ith the STEPPER MOTOR SUBCONTROL to control operation o f
LEDEX stepper motors.
The Control can operate only one o f ten connected motors at a tim e,
i t being selected by programmed in s tru c tio n . A START MOTOR in s tru c tio n
sends an ENABLE signal to the selected motor, causing th a t motor to begin
operation. A 12 b i t counter can be loaded
by programmed in s tru c tio n , the
count representing the number o f motor re volutions to be executed,
the sign o f the number in d ic a tin g the motor ro ta tio n d ire c tio n . Signal
le ve ls in d ic a tin g the number sign are ava ilab le to the motor drive
c ir c u its . Pulses generated by some means ^rom the ro ta tin g motor sha^t
are used to count down the counter to zero. When zero-count occurs, or
when the STOP MOTOR in s tru c tio n is executed, the enable signal to the
selected motor is removed and the MC fla g is set. The current value o f
the counter can be read at any time by the PDP 8/1.
The Motor Control cannot d rive motors d ir e c tly ; i t only supplies
control signal le ve ls to motor d rive c ir c u it r y . A scheme must e x is t
fo r return o f pulses associated w ith ro to r operation. The leading edoe
o f these pulses is used to increment or decrement the counter value.
The Motor Control is connected to the I/O bus as an I/O device
w ith codes 30, 31, 32. A ll lo g ic modules are located on the L *rame.
Indicator, lamp #11 is on i f the MOTOR ENABLE f lip - ^ lo p is on. Raising
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
panel switch #5 enables the MC fla g skip and in te rru p t fu n ctio n s.
94
In d ic a to r lamp #10 is on when the MC fla g is on i f switch #5 is up.
b )In s tru c tio n Set and Programming
6307 (MCL)-
RESET AND LOAD MC COUNTER, SUBTRACT 1 IF POSITIVE VALUE,
CLEAR MC FLAG
The in s tru c tio n loads a 12 b i t signed binary number
from the AC, decrements i t by 1 i f p o s itiv e , and clears
the AC. The carry in or out o f the high order counter
p o s itio n is used to disable a motor and set the MC fla g .
This occurs in passing from OOOOg to 7777g when decre­
menting o r in passing from 7777g to OOOOg v/hen increment­
ing .Thus in order th a t a number or it s two's complement
negative form always represent the number o f revolutions
to be made, the p o s itiv e value is decremented by one upon
loading i t . The sign o f the number at the time o f loading
determines whether pulses received from the driven motor
w i ll increment or decrement the counter. P ositive numbers
loaded cause increments. 0 should not be loaded in to the
counter.
6311 (MCSF)-
SKIP ON MC FLAG
A skip occurs i f the MC fla g is ON, in d ic a tin g th a t
a selected motor has stopped, due to e ith e r a count down
to 0 o r a 6314 in s tru c tio n .
6312 (MCCF)«
CLEAR MC FLAG,.START MOTOR
The MC FLAG is cleared, and an enable signal is sent to
the selected motor.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
6314 (MCSM)-
STOP MOTOR, SET MC FLAG
95
The MC fla g is set and the enable signal is removed from
the selected motor.
6322 (MCR)-
OR MC COUNTERINTO AC 0-11
The current contents o f the MC COUNTER are OR'ed w ith
the contents o f AC 0-11.
6324 (MCSN)-
SET MOTOR NUMBER TO BCD VALUE IN AC 8-11
The BCD value in the range 0 -9, representing the motor
to be selected, is loaded in to the MOTOR NUMBER REGISTER
from AC 8-11.
A fte r the MOTOR COUNTERhas counted to zero and the MC fla g is s e t,
the counter is
s t i l l capable o f receiving pulses and w ill continue to count
in the same d ire c tio n as before. This is useful i f i t is desired to
determine the number o f overshoot revolutions o f a motor. Pulse inputs
o f a ll motors are OR'ed together before being presented to the counter.
No pulses are in h ib ite d , even from non-selected motors.
c)Logic Operation
Refer to Figure 3.22. Two M211 s ix - b it binary up/down counters are
connected to form a 12 b i t counter. The M211 enable (EN) inputs must be
high when counting, and must be low 100 nsec. before the up-down (U/D)
inputs are changed. A high U/D lin e causes the counter to increment, a
low U/D lin e causes i t to decrement. A p o s itiv e tra n s itio n a t the count
(CNT) in p u t causes a single count, the CARRY output y ie ld s a p o s itiv e
tra n s itio n whenever a carry or borrow occurs. Thus the 6307 in s tru c tio n
works as fo llo w s :
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
CONTROL
96
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99
The M103 a t L28B responds to code 30. The I0P1 pulse resets the M211
f lip - f lo p s , and the COUNT ENABLE f lip - f lo p is set—causing the M211 EM
lin e s to go low. The t r a ilin g edge o f the I0P1 pulse resets the U/D
f li p - f l o p to DOWN. The I0P2 pulse gates data in to the counter f lip - f lo p s
from the AC. I f the number is negative (le ft-m o s t b it= 1) the U/D
f li p - f l o p is set UP. The t r a ilin g edge o f the I0P2 pulse resets the
COUNT ENABLE
f l i p - f l o p , causing the M211 lin e s to go high, allow ing the
counter to accept count pulses. The I0P4 pulse resets the MC FLAG f l i p flo p . I f the number in the counter is p o s itiv e (U/D f lip - f lo p reset)
the I0P4 pulse is gated to the CNT in p u t o f the r ig h t side M211, causing
a decrement o f 1.
Code 31 is selected by the M103 at L29B. The I0P1 pulse operates
the MC fla g skip fu n c tio n ; the I0P2 pulse sets the MOTOR ENABLE f l i p flo p and resets the MC FLAG f l i p - f l o p ; the I0P4 pulse resets the MOTOR
ENABLE f l i p - f l o p and sets the MC FLAG f lip - f lo p .
The M141 a t L32A OR's together p o s itiv e inputs from motor shafts and
places these pulses on the r ig h t side M211 CNT lin e .
The Ml03 a t L30B selects code 32. The I0P4 pulse is used to strobe
the contents o f AC 8-11 in to a 4 binary d ig it b u ffe r re g is te r. The output
o f th is b u ffe r drives the in p u t o f an Ml61 Decimal Decoder module. For
a BCD d ig it in p u t in the range 0 to 9 the b u ffe r selects one o f ten
pairs o f output lin e s o f the Ml61. An output p a ir consists o f an output
lin e and it s complement. The output lin e s are low unless the enable gate
is driven by the MOTOR CONTROL f l i p - f l o p , in which case the selected
output lin e goes high. These output lin e s are used by motor d rive
c ir c u it r y to s ta r t motor ro ta tio n .
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
11) Stepper Motor Subcontrol fo r MKS Pressure Gauge
100
a)D escription
The Stepper Motor Subcontrol in te rfa ce consists o f lo g ic which
augments the Motor Control to the extent necessary to control the func­
tio n in g o f b i-d ire c tio n a l stepping motors,^ and o f motor d rive and
completed-step sensing c ir c u it r y . The fiv e stepper motors thus fa r
connected are used to control the se ttin g s o f fo u r m u lti-p o s itio n
switches and one potentiometer on the fro n t panel o f an MKS Baratron
Pressure Gauge.
A b i-d ire c tio n a l stepper motor can ro ta te in e ith e r d ire c tio n ,
w ith a separate d rive c o il fo r each d ire c tio n . R eferring to the
d ire c tio n s as UP and DOWN, the motor is stepped e ith e r up or down once
fo r each current pulse at the corresponding drive c o il. In order to
cause a motor to step, a current pulse in the order o f 50 m illiseconds
length is required, followed by a no-current recovery time o f about 400
m illise co n d s. Using the Motor Control to se le ct the desired stepper
motor, ro ta tio n d ire c tio n , and step count, the Subcontrol w ill provide
pulses w ith the necessary tim ing requirements to the selected stepper
d rive c o il.
The sh a ft o f each stepper motor is f it t e d w ith a wafer-switch
assembly w ith contacts corresponding to each neutral p o sitio n o f the
motor s h a ft. These contacts provide signals to the Subcontrol which
in d ic a te th a t a step has been completed or th a t a p o sitio n o f maximum
allowable ro ta tio n has been reached. These signals inform the subcontrol
th a t:
a) a step has been completed w ith in allowable ro ta tio n rang
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
101
b) a step to the maximum allowable upward p o sitio n has
occured (c a lle d MAX p o s itio n ).
c) a step to the maximum allowable downward p o sitio n
has occured (c a lle d HOME p o s itio n ).
In a ll three cases the Subcontrol provides the Motor Control
counter w ith a count pulse, thus changing the step count by one. In
case (a ), i f another step UP past the MAX p o sitio n is attempted, the
MALFUNCTION fla g is s e t, in h ib itin g any current pulses to the stepper
motor. In case ( c ) , a step DOWN to HOME causes the HOME f lip - f lo p to
be s e t. An attempt to step DOWN from HOME causes the MALFUNCTION fla g
to be set and current pulses are in h ib ite d as in case (a ). The MAL­
FUNCTION fla g can cause an in te rru p t or a s k ip , and must be reset by a
programed in s tru c tio n .
This Subcontrol w ill generate a s trin g o f drive pulses as long
as the MOTOR ENABLE f l i p - f lo p o f the Motor Control is set and no
m alfunction condition e x is ts . I f a curre nt pulse is generated by the
Subcontrol and no step-complete signal is received w ith in a c e rta in fixe d
time set by the SINGLE SHOT MULTIVIBRATOR w ith the Subcontrol, the MAL­
FUNCTION fla g is set.
A programmed RESET command can be given which w ill cause the Sub­
control to step DOWN a selected stepper motor to it s HOME p o s itio n ,
causing a RESET COMPLETE fla g w ith in te rru p t and skip c a p a b ilitie s to
be se t.
In s tru c tio n s are availab le to cle a r the MALFUNCTION and RESET
COMPLETE fla g s , or to skip on these same fla g s .
The Stepper Subcontrol is connected to the I/O bus as an in te r -
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
102
ruptable device, and in d ir e c tly through the Motor C ontrol.
addressed with device codes 32 and 33.
I t is
Subcontrol lo g ic is located on
the U frame; the two-section cable-connected K644 c o il d riv e r modules
are located on the U and S frames.
Raising panel switch #6 enables the
skip and in te rru p t functions o f the MALFUNCTION fla g ; in d ic a to r lamp #12
is on i f the MALFUNCTION fla g is set and switch #6 is up.
Raising
panel switch #7 enables the RESET COMPLETE fla g skip and in te rru p t
fu n ctio n s; in d ic a to r lamp #13 is on i f the RESET COMPLETE fla g is on
and switch #7 is up.
b)
6321 ( STC)-
In s tru c tio n Set and Programming
CLEAR AC AND RESET MALFUNCTION, RESET COMPLETE FLAGS.. .
The accumulator is cleared; the MALFUNCTION and RESETCOMPLETE flags are reset.
In Subcontrol operation, the
MALFUNCTION fla g being set causes the MC fla g to set and
the MOTOR ENABLE f lip - f lo p to reset.
The states o f the
MC and MOTOR ENABLE f lip - f lo p s w ill not be changed by
any in s tru c tio n u n til a fte r an STC in s tru c tio n is
executed.
6331 (STSM)-
SKIP ON MALFUNCTION FLAG
A skip occurs i f the MALFUNCTION fla g is on, in d ic a tin g
the fa ilu r e o f a step to occur or an attempt to step
out o f maximum allowable range o f ro ta tio n .
6332 (STSR)-
SKIP ON RESET-COMPLETE FLAG
A skip occurs when a selected stepper motor has reached
i t s HOME p o sitio n as a re s u lt o f a previously executed
STR command (below).
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
6334 (STR)-
RESET STEPPER MOTOR
103
The Subcontrol causes the selected motor to be stepped
DOWN to it s HOME p o s itio n . The motor w ill be stepped
DOWN regardless o f the contents o f the MC counter or the
status o f the MOTOR ENABLE f lip - f lo p . A MALFUNCTION
condition w ill in h ib it fu rth e r d rive pulses.
Execution o f STR w ith the selected motor in HOME p o sitio n merely
causes the RESET COMPLETE fla g to be set.
Execution o f an STC sometime a fte r an STR and before the selected
motor has reached HOME aborts and n u llif ie s the STR in s tru c tio n and
may cause a MALFUNCTION co n d itio n ,
c)Logic Operation
R eferring to Figure 3.23-A, the lo g ic elements enclosed in the
dotted box w i ll produce pulses when enabled by a high condition a t (V).
Figure 3.24 is a tim ing diagram in d ic a tin g the action a fte r p o in t V is
raised a t time T=0. Time in te rv a l t l is the recovery time o f the M302
Single Shot M u ltiv ib ra to r, t2 is the delay time of the element a t U27B.
Pulses w ill be produced a t output U27AF2 u n til V is made low. I f V is
low a t time T=b, another cycle a t U27AF2 w ill not occur i f t3 < t2 .
I f V is low a t T=a, the current cycle o f duration t l w ill be completed
a t U27AF2.
Figure 3.23-B indicates th a t V can be made high in two ways,
namely, a set MC MOTOR ENABLE flip - ^ lo p along w ith a reset MALFUNCTION
f l i p - f l o p , or a set RESET f lip - f lo p along w ith reset HOME and MAL­
FUNCTION f lip - f lo p s . The RESET f lip - f lo p is set by an STR (6334)
in s tru c tio n .
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
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Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
105
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Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
106
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SUBCONTROL
TIMING
FIGURE
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
3.24
The STEP COMPLETE f lip - f lo p serves to lim it the amount o f time
107
current is applied to the stepper c o il and to provide abnormal condition
in d ic a tio n . This f l i p - f l o p is set when U27AK2 is low and is reset when
the selected stepper motor has advanced one p o s itio n . Current is
applied to the selected stepper c o il during the time both STEP COMPLETE
is set and U27AF2 is high. This fun ctio n appears a t the PULSE output
on Figure 3.23-A, and normally is ju s t the time STEP COMPLETE is s e t,
as shown in Figure 3.24. t4 is the time required fo r the stepper to
advance one p o sitio n w ith power applied. At the end o f t4 , d riv e r
power is removed, and the time remaining th a t U27AF2 is high ( t l - t 4 ) is
made long enough to allow the motor s u ffic ie n t recovery time.
I f STEP COMPLETE has not been reset by the time U27AF2 goes low,
in d ic a tin g th a t the selected motor has not stepped, an abnormal condi­
tio n e x is ts . Thus the condition o f the STEP COMPLETE f lip - f lo p is
strobed in to the MALFUNCTION f lip - f lo p each time U27AF2 goes low.
I f the STEP COMPLETE f l i p - f lo p is s t i l l set at th is tim e, the MAL­
FUNCTION f lip - f l o p is s e t, which causes (Figure 3.24) V to go low and no
more d rive pulses to be generated, and which resets the MOTOR ENABLE f l i p flo p .
The STEP COMPLETE f l ip - f lo p is reset by a selected stepper as
fo llo w s : The extreme p o sitio n contacts on the selected stepper are
connected to the MAX and HOME inputs in Figure 3.23-A. A ll in te r ­
mediate contacts are connected together and then to the MID in p u t.
The contacts are flo a te d high by connecting them to a high impedence
lo g ic a l 1 source. The common contact o f the selected stepper wafer
switch is grounded. The wafer switch works w ith a break-before-make
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
108
a ctio n . Thus before a step occurs one input (MAX, HOME or MID) is low
and the other two are high, producing a high condition at the STEP
COMPLETE clock in p u t. As a step is executed, the wafer switch breaks
contact and a ll three inputs are high, causing a low clock
in p u t. As
the step is completed, some input is grounded, causing the
STEP
COMPLETE clock in p u t to go high, strobing in a lo g ic a l 0, thus re se ttin g
the f lip - f lo p .
In order to prevent damage re s u ltin g from the Motor Control
being a ccid e n tly programmed to step a motor beyond it s maximum permissable range, the Subcontrol detects such attempts and in h ib its f u r ­
th e r motor operation. As shown in Figure 3.23-A, a high condition
e x is ts at U26BK2 only i f the MC U/D f l ip - f lo p is UP and the stepper is
in MAX p o sitio n o r i f the MC U/D f lip - f lo p is DOWN and the
stepper is in
HOME p o s itio n . This high condition w ill prevent any pulses
generated from
reaching the PULSE outputs. I f the M302 does produce a pulse, the lack
o f d riv in g pulse w ill allow the stepper to remain s ta tio n a ry , prevent­
ing the reset o f STEP COMPLETE, and re s u ltin g in the s e ttin g o f the
MALFUNCTION f lip - f l o p when U27AF2 goes low.
Stepping in to the HOME p o sitio n causes the HOME f lip - f lo p to se t.
I f an STR (6334) had been given the set RESET f lip - f lo p (Figure 3.23-B)
along w ith a set HOME f lip - f lo p combine to give a RESET COMPLETE fla g
which causes in te rr u p t, skip and po in t (V) to go low.
In Figure 3.23-A, the output o f STEP COMPLETE is combined w ith the
M302 output to y ie ld a p o s itiv e tra n s itio n a t the COUNT output a t the end
o f time in te rv a l t4 in Figure 3.24. This tra n s itio n causes the MC counter
to change by one.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
109
When an STR (6334) in s tru c tio n is executed, the I0P4 pulse sets
the MC U/D f li p - f l o p to DOWN and disables the MC counter,
d)D escription o f Stepper Motor Configuration
The Subcontrol is used to d rive fiv e LEDEX stepper motors
mounted on the f r o r t panel o f the MKS BARATRON PRESSURE GAUGE.10
The MKS gauge consists o f an AC bridge w ith a pressure dependent
capacitance in the c ir c u it . When the bridge is balanced by means o f
three ro ta ry decade switches and a potentiometer mounted on the
fro n t panel, a d ire c t pressure readout corresponding to the switch and
pot p o sitio n is obtained. The gauge is equipped w ith a meter which
indicates the n u ll- e rr o r voltage, a b ip o la r DC n u ll- e rr o r voltage
output ja c k , a meter range switch which varies the s e n s itiv ity o f the
n u ll- e rr o r voltaqe detecting c ir c u its , and a n ull-ope ra te sw itch, which
makes the n u ll- e rr o r voltage e ith e r no n -lin e a r ( n u ll) or lin e a r (operate)
w ith respect to pressure on the sensing capacitance.
The stepper switches enable the PDP 8/1 computer to balance
the MKS gauge under program c o n tro l. The high s ig n ifica n ce decade
switch is l e f t alone. The middle s ig n ific a n t p o sitio n decade switch
(MSP) is connected to motor M2 (see Figure 3.25), and the le a st
s ig n ific a n t p o sitio n decade switch (LSP) is connected to motor M3.
The b id ire c tio n a l stepper switches move in 30° steps, so they can
c o rre c tly p o sitio n the decade switches which have ten p ositions
separated by 30°. The most counterclockwise positions o f the MSP and
LSP switches are wired as the HOME positions while the most clockwise
p ositions are wired MAX.
Motor M4 is connected to the potentiometer (POT) by means o f a
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series o f gears which enable M4 to step POT through 300°+ o f tra ve l
in steps o f 3°. L e ttin g an almost completely CCW p o sitio n o f the POT
to be referenced 0G, HOME is wired as -3 °, MAX is wired as 300°.
CCW stepping o f the motor (UP) causes clockwise ro ta tio n o f the POT.
HOME and MAX contacts are wired through S2 and S3, as shown in
Figure 3.25. Since M4 completes several revolutions in 100 steps, it s
corresponding wafer switch must be wired to ignore HOME and MAX
p ositions u n til the POT is near the extreme points o f it s tra v e l, thus
S2 and S3 are cam operated m icroswitches, the cams being driven by the
ro ta tio n o f the POT. Switch S2 enables the MAX contact fo r POT
positions greater than 282°, w hile switch S3 enables the HOME contact
fo r POT positions less than 15°.
Motor M0 is a u n id ire c tio n a l stepper used to switch between the
n u ll and operate functions o f the MKS gauge FUNCTION sw itch. When the
stepper c o il 28VDC power supply (Figure 3.26) is turned on, the
FUNCTION (S206) switch is disables (Figure 3.27) by a relay which
shunts the n u ll and operate functions to the deck-2 wafer switch
(NULL) o f Motor
M0. Deck-1 o f M0 is wired so th a t the n u ll function
corresponds to HOME. The 20 ohm re s is to r and switch SI in Figure 3.25
merely modify the d riv in g pulse o f
M0.
The leads o f Figure 3.25 are connected to a term inal s tr ip
shown in Figure 3.28. A cable leads to three terminal s t r ip K782
modules in the PDP 8 /1 , as shown in Figure 3.29 and Figure 3.30.
When a stepper motor is selected through the Motor Control
in s tru c tio n MCSN (6324), it s K644 c o il d rive rs are p a r tia lly enabled
(Figure 3 .29), and i t s wafer switch wiper is enabled by grounding i t
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
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SUPPLY
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113
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A3
A2 .
O***'
A1 „
FUNCTION
SWITCH
( S2 0 6 ) —OF M K S
GAUGE
B2.
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C2
C1
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D2
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MODIFICATION:
LEACH RELAY
MS 25271-D1
M O U N T E D ON MKS
GAUGE CHASIS
AND C O N N E C T E D
AS S HOWN
DECK 2 OF
NULL-OPR
STEPPER
SWITCH
^TO 2 8 V D C
1
STEPPER
P O W E R SUPPLY
s
FUNCTION
SWITCH
M O D I F I C AT IONS
S 2 0 6 DISAB LED WHEN STEPPER
P O W E R S U P P L Y IS O N . M K S
F U N C T I O N IS " N U L L ” W H E N
NULLOP R S W I T C H IS IN H O M E P O S I T I O N ,
F U N C T I O N IS " O P E R A T E "
OTHERWISE .
FIGURE
3.27
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
C O N N E C T IO N S
K
E
^ce
CABLE
inun.
STEPPER
iflOto
fy-JVI
£o>e
S=ZZ
M
0= 2 «
2
« i o *S*'
O u
i "
ui<
KZ (u
»P sj
o5 *
Ul<
ftZ
U sz
M
* |o
O uj
*5
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K 2.L2
115
r;
r \
n
n
1n
£D
0* CVi
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
3 .3 0
FIGURE
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
117
(Figure 3.30) by means o f M623 gates. Then as seen in Figure 3.29,
the condition o f the MC U/D f l ip - f lo p is used to steer Subcontrol drive
pulses to e ith e r the m otor's UP or DOWN c o il d riv e r.
Signals re turning from the selected wafer switch are conditioned
(Figure 3.25) by smoothing w ith ca pa citors, and converting them to
step functions through the use o f Schmidt trig g e rs (Figure 3.30).
The Schmidt trig g e rs o f Figure 3.30 and the
Delay a t U27B o f Figure
3.23-A are constructed on an etched c ir c u it
board as shown in Figure
3.31
e)MKS Gauge DC Output A m p lifie r and F ilt e r
In order th a t the PDP 8/1 be able to balance the MKS gauge
through the Motor Control and Subcontrol, an in d ic a tio n o f the gauge
n u ll- e r r o r voltage must be provided. This is done by am plifying and
f il t e r in g the e rro r voltage by means o f the c ir c u it o f Figure 3.32.
The c ir c u it is mounted in the BURR BROWN RACK module #5 as shown in
Figure 3.4. The a m p lifie r output is brought
out to a panel ja c k ,
where connection can be made to an A/D MPXR channel in p u t.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
MOUNTED
SINGLE
ON
W IDTH
F1
DEC
118
BOARD
H1
J1
.
S1
A2
14
MC 9 7 0 9 P
ST
ST
ST
ST
10
2 .4 K
2.4 K
A /V v 3.9 K
V2
M1
U2
\/
<V1
24a
1 7 8 0 -a
SCHMIDT
TRIGGER
PRINTED
CIRCUIT
FIGURE
3.31
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
BOARD
♦ 15V
119
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
120
12) In d ic a to r Lamps and Panel Switches
The in d ic a to r panel holds tw enty-four in d ic a to r lamps and tw enty-four
switches wired to two connectors as shown in Figure 3.33. Two cables with
the mate connectors lead from the U Frame. Table
V
l is t s the 32 pin
connector w irin g . Figure 3.34 shows the cable connections and in d ic a to r
lamp d rive rs associated w ith the 24 pin connector.
Figure 3.35 shows the connections providing in d ic a tio n o f the
presence o f +90V power fo r the paper tape solenoid; +28V power fo r the
stepper motor c o ils ; +15V and -15V L and U Frame power fo r the p lo tte r
c o n tro l, W993 m u ltip le x e r, A801 D/A, A704 reference supply, and A613
A/D; +5V power fo r lo g ic elements on the U,L, and S Frames. -7V in d ica ­
to r lamp
p o w e r
(Figure 3.26) is indicated as a re s u lt o f the ground at
U31AS1 in Figure 3.34-B.
The in v e rte rs a t S7A in Figure 3.35 are special level converters
providing an
output acceptable to the M050 Lamp D rivers. The in v e rte r
c ir c u its are shown in Figure 3.36. Level converters were also con­
structed fo r +15V and -15V in te rfa c e power in d ic a tio n . The elements
a t U21B in Figure 3.35 are constructed on an etched c ir c u it board as
shown in Figure 3.37.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
23
O
o
o
lO
o
o
23
24
2 4 P IN C O N N E C TO R
32
24
23
22
P IN C O N N E C T O R
27
20
29
23
R E S IS T O R S : 4 7 K O H M S . 1/2 W
CONNECTO RS
C A M P S : C H IC A G O M IN IA T U R E
C M 2 2 -2 -0 1 -2 7
REAR O F IN D IC A T O R
24
M O U N T E D ON
PA NEL
S W IT C H E S : A L C O S W IT C H
M C T -1 1 0 0
IN D IC A T O R PA N EL:
L A M P S AND S W IT C H E S
F IG U R E
3 .3 3
12?
TABLE V
U FRAME - SWITCH CABLE - 32 PIN CONNECTOR CONNECTIONS
Switch
Number
Connector
Number
Pin P osition
a t U30
1
24
AA1
2
23
AB1
3
22
AC1
4
21
ADI
5
20
AE1
6
19
AF1
7
18
AH1
8
17
AJ1
9
16
AK1
10
15
AL1
11
14
AMI
12
13
AN1
13
12
API
14
11
AR1
15
10
AS1
16
9
AU1
17
8
AVI
18
7
BA1
19
6
BB1
20
5
BC1
21
4
BD1
22
3
BE1
23
2
BF1
24
1
BH1
29
GND
31
+5V
27
-7V
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
123
M050
U21A
U31A
U23BB1
D2
U21BK2
E2
U 21BM2
F2
L3AH2
H2
L3AK2
J2
U 22BC1
K2
U 22BF1
L2
L24AV1
M2
U22BK1
N2
U 22BK2
P2
P1
L 24AM1
R2
R1
U 22BN1
S2
B1
H1
D1
M1
<8
1 / 2 O F 2 4 PI N
C ON N EC TO R TO
I N D I C A T O R PANEL
INDICATOR
CABLE
LAMP
DRIVERS
CONNECTIONS
FIGURE
3. 3 4 - A
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
&
124
M050
U 22 A
U31A
U22BN2
D2
U22BF2
E2
(0 )
F2
F1
H2
H1
U31B
A1
K2
<1 8
L2
M2
B1
M1
<20
N2
P2
D1
P1
<22
R2
S2
<24
I
1/ 2 O F 2 4 P I N
CONNECTOR
TO
INDIC ATO R PANEL
INDICATOR
CABLE
LAMP
DRIVERS
CONNECTIONS
FIGURE
3. 3 4 - B
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
&
♦90VDC
PAPER TAPE
P O W E R SUPPLY
REWIND
SURPLUS
PAPER TAPE
READER
REWIND SOLE NOI D
GND
>
S7A
V2
P1
S7BK2
+90 V
PAPER TAPE
POWER
L3AK2
-o
U 21A J 2
‘
CABLE
DRIVERLAMP 5
S7A
T2.
M1
S7BH2
L3AH2
♦28V
STEPPER
POWER
U21AH2
a-----
©-
DRIVER
LAMP 4
CABLE
U 21 B
H2
U21AE2
U27BA1
♦ 15 V
INTERFACE
POWER
DRI V E R LAMP 2
U21 B
U27BC1
P2
M2
U21AF2
-15 V
INTERFACE
POWER
DRIVERLAMP 3
U23B
U24BV1
A V , S\ B 1
U21AD2
♦5 V
INTERFACE
POWER
DRIVERLAMP 1
POWER
IN DICATION
FIGURE
LOGIC
3.35
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
1P6
P1
A2
33 K
2
AA/V
t L 10 M F D
T * 20VDC
2 N4400
3. 9 K
M1
V
22 K
V vV
12 K
2
A /W
10 K
A /W
10MFD
20VDC
ro
2N 4 4 0 0
3. 9 K
M O U N T E D ON DE C
S I N G L E WIDTH BOARD
T1 /
W976
A M P -3
PRINTED
CIRCUIT
FIGURE
BOARD
3.36
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
127
V2 >
r r
2 2 M F D , 15 VDC
U 2 > --------------------------------------------------T2
3 9 M F D , 2 0 VDC
K2
S2
H2
\/
10 K
V v V
2N4400
3.9K
A 2
10 K
1N251
M2
3.9K
P2
M O U N T E D ON DEC
sin g le
W I D T H BOARD
W976
AM P-2
PRINTED
CIRCUIT
GURE
BOARD
3.37
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
128
IV.
M odifications and Additions
A)
P hotoelectric Paper Tape Reader
V)
M otivation
The only permanent record inputs possessed by the PDP8/I are the
33ASR paper tape reader and the Soroban paper tape reader.
They input
characters from a sin g le paper tape at rates o f 10 and 15 characters
per second, re s p e c tiv e ly , both using mechanical methods o f hole
sensing.
Now the programming approach used in computer control o f the
spectrometer is to b u ild various spectrometer operation schemes in a
conversational programming language s im ila r to BASIC or a simple FORTRAN,
called FOCAL.
Function commands in th is language c a ll up machine language
subroutines which are s p e c ia lly w ritte n to service and control each
spectrometer in te rfa c e fu n c tio n .
Data obtained by th is method is then
immediately able to be processed by fu rth e r FOCAL programming.
The loading o f the various programs necessary fo r creating machine
language subroutines, such as tane e d ito rs and assemblers, requires
much tim e, as does the loading o f the FOCAL system i t s e l f .
Debugging
the patched system is somewhat d e stru ctive and may require several
reloadings, o f the FOCAL system per programming change.
For these
reasons a t le a s t, i t was decided to replace the Soroban tape reader
w ith a fa s te r model:
2)
the Dataterm, Inc. P hotoelectric Paper Tape Reader.
Description
The p h o to e le c tric tape reader assembly consists o f stepper motor
d rive w ith d riv in g c ir c u it r y , p h o to e le ctric tape hole sensors w ith amo-
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
129
l i f i e r s and Schmidt trig g e r outputs, and tim ing control c ir c u itr y .
Tape channel outputs are TTL compatible; the "advance one tape char­
acter" order consists o f a 0 to +3V step on a lin e from the external
control device.
The tape reader control c ir c u itr y provides a 0 to +3V
step when the tape character has been c o rre c tly positioned over the
photo-sensing diodes a t the read s ta tio n .
The tape reader w ill oper­
ate a t a maximum asynchronous speed o f 300 char./sec.
deck is equipped to handle fa n -fo ld tape.
The tra n sp o rt
The only panel control is
a power switch which actuates the lig h t source and the power supplies
fo r the motor d riv e , p h o to e le ctric a m p lifie r, and control c ir c u it r y .
The tape reader is inte rfa ced as an input device on the I/O Bus
w ith device code 10.
fla g is on.
In d ic a to r lamp #14 is on when the tape reader
Panel switch #2 on advances tape through the reader at
a 400 ch a r./se c. ra te .
No reading takes place i f th is switch is on:
i t is meant to provide convenient po sitio n in g o f leader tape during
loading, and to run out t r a ilin g tape a fte r a load operation is complete.
3)
In s tru c tio n Set and Programming
Three in s tru c tio n s control operation o f the High Speed Tape
Reader:
6011 (RSF) - SKIP ON READER FLAG
A skip occurs i f the READER FLAG is on, in d ic a tin g th a t
a read operation has been completed and th a t the character
is properly positioned fo r reading in to the AC.
6012 ( RRB) - OR CHARACTER INTO AC AMD CLEAR FLAG
The READER FLAG is cleared and the character positioned
over the read s ta tio n is lo g ic a lly ORed w ith the contents
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
130
o f AC 4-11, the tape channel inform ation going to AC
positions as indicated in Fig. 3.20 fo r the 6164 in s tru c ­
tio n .
6014 (RFC) - CLEAR FLAG AMD FETCH NEXT CHARACTER
The READER FLAG is cleared and an "advance one tape
character" order is issued to the reader tra n sp o rt motor
d riv e .
When the next character has been properly positioned
over the read s ta tio n , the READER FLAG is set.
The in s tru c tio n codes and the operations they control are id e n ti­
cal to those fo r the High Speed Perforated Tape Reader Type PR8/I option
a vailable from DEC.
The Dataterm reader was interfaced as a s u b s titu te
fo r th is DEC o p tio n , and thus software c o n tro llin g operation o f the PR8/I
w ill control the Dataterm reader w ithout a lte ra tio n .
4)
Logic Operation
In te rfa ce control lo g ic fo r the Dataterm reader is shown in
Fig. 4 .1 .
A ty p ic a l tape channel output provides a TTL compatible
lo g ic a l 1 i f a hole is sensed, and a lo g ic a l 0 fo r no hole sensed a t
the read s ta tio n .
A p o s itiv e pulse o f duration 20 ysec. to 1 msec.
(STEP SIGNAL) is required from the in te rfa c e lo g ic in order to cause
the tra n sp o rt motor d rive to advance the paper tape one character
p o s itio n .
The tra n sp o rt e le ctro n ics supplies the in te rfa c e w ith a
signal (SPROCKET STROBE) which is lo g ic a l 1 i f and only i f a tape
character is c o rre c tly positioned over the read s ta tio n .
drops to lo g ic a l 0 during tape advance.
The signal
The p o s itiv e step tra n s itio n
o f th is signal is used to ind icate th a t a tape advance operation has
been completed.
A ll signal connections are available a t the tra nspo rt
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
131
Oo>
i5
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
132
through a 25 pin connector.
Proper pin connections are noted fo r the
appropriate in te rfa c e leads in Fig. 4.1.
The purpose o f the M302 Single Shot M u ltiv ib ra to r at U27A is to
provide the STEP SIGNAL o f proper length to the tra n sp o rt motor d rive .
The fla g f li p - f l o p indicates a "tape has advanced one character p o s iti
condition when in the 0 s ta te .
enabled by the 0 state fla g .
The skip and in te rru p t functions are
The fla g is cle ar when in the 1 state
and indicates th a t no character is necessarily ready to be read in to
AC.
The fla g is set to the 0 state by the SPROCKET STROBE leading
edge from the tape tra n s p o rt; i t is set to the 1 sta te by the 6012 or
6014 in s tru c tio n s , or by the INITIALIZE oulse generated by the PDP3/I
when the PROGRAM START panel switch is depressed.
Panel switch #2
on holds the STEP SIGNAL lin e high, causing the tape tra n sp o rt to
advance tape continuously at a 400 ch ar./se c. rate out o f control o f
the in te rfa c e lo g ic .
This switch should not be turned on when the
reader is reading tape under program c o n tro l.
No flag-enable switch
has been provided, since the tra n sp o rt is meant to be a d ire c t sub­
s t it u t e fo r the DEC PR 8/1 option.
5)
System M odifications
The Dataterm tape reader replaces the SPTR and associated in te r ­
face lo g ic .
Thus the SPTR in s tru c tio n s described in section III-B -9
are in a c tiv e , and a ll SPTR lo g ic on the S-Frame has been removed.
Enable Switch #2 and Lamp #14 o f Fig. 3.12-B have been reassigned as
shown in Fig. 4.1 and as described in section IV-A-2.
The power
in d ic a to r fo r the solenoid power supply, Lamp #5 in Fig. 3.35, is
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
133
in a c tiv e .
The SPTR tra n sp ort and solenoid power supply have been
removed from the cabinet, the Dataterm transport occupying the vacated
spot on the PDP8/I cabinet.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
134
B)
P lo tte r Flag M odification
I t was found during the w ritin g o f p lo tte r control software
th a t programming would be s im p lifie d i f the PLOT COMPLETE fla g could
be assumed to be cle a r whenever PDP8/I in s tru c tio n execution is
in it ia t e d .
Thus the P lo tte r Control lo g ic o f Fig. 3.18 was modified by
is o la tin g point L24AF2 and in s e rtin g the extra lo g ic gates as shown
in Fig. 4 .2.
As a r e s u lt, the PDP8/I generated INITIALIZE pulse
w ill cle a r the PLOT COMPLETE fla g .
P lo tte r Control in s tru c tio n s
are not affected by the m o d ifica tio n .
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
135
I NIT_______
L24AK2
L27BK1
L24AU2
L27BF1
&
&
s r>
V2
A1
B1
PLOTTER
L24AF2
FLAG
M ODIFICATIO N
FIGURE
4.2
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
136
V. A Test Program
In order to v e r ify th a t the various in te rfa ce devices could be
made to work together in a ty p ic a l experimental s itu a tio n in volving
a computer c o n tro lle d spectrometer through the use o f simple control
functions in a conversational level programming language, several
such function routines were w ritte n fo r the FOCAL language.
These
in te rfa c e device service ro u tin e s, when c a lle d , cause the proper
inform ation tra n s fe r to occur or the proper operation to be executed.
The functions and th e ir purposes are:
1) FADC(n)
- Read output o f Synchronous Detector
2) FNEW( )
- Read BWO operating frequency from D ig ita l Counter.
3) FC0M(m,n)
- Set operating frequency of BWO
4) FX(0,X,Y)
- P lo t p oint ( X, Y) on P lo tte r
5) FX(1,T)
- Delay fu rth e r program execution fo r specified
A simple FOCAL program v/as w ritte n using these fu n ctio n s.
time.
The
program (Figure 5.1) causes the spectrometer to sweep over a small
frequency range in which an absorption lin e is assumed to be located.
The program reads the detector output values a t in te rv a ls durinci the
sweep, sto ring th is data, p lo ttin g i t out on the X-Y p lo tte r (Figure
5 .2 ), and p rin tin g i t out on the 33ASR (Figure 5 .3 ).
A fte r c o lle c tin g
a specified number o f points w ith in a specified sweep range, the pro­
gram f i t s a s tra ig h t lin e to each side o f the lin e swept by means o f
a le a s t squares process; the in te rs e c tio n o f the two s tra ig h t lin e s
is taken to be the frequency o f the lin e peak:
the BWO operating
frequency o f th is point is found and printed out and is indicated as
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
w
O F O C A L * 1 9 69
01.10
01.03
01.30
S D=FCOM< 1 * 0 > 5 S D = F X ( 0 * 0 * 0 )
A
T j X I j X2 5 S C=< X 2 - X 1 >/ N, * S
F A=0 j N-1;DO 5
V=Xl5
S K=-
02.08 S
02.10 I
02.12 S
02. 1 A D
02.16 S
0 2. 1 8 D
02.23 S
02.22 T
02«24 T
32.2 6 S
02'. 2 8 S
02.33 T
02.31 F
0*32 0
K = K+l
<Y<K>-Y<K+t)) 2 .0 8 *2 .0 8 5
A = Y <K > j S L = 0 5 S H = K - 2
3
Ml =M5 S B 1=85 S R 1 - R 5 S L = K + 2 5 S
3
N1J = CQ-B1 ) / ( M l - M )
! * ?MU? 5 T "
” ?A?* !
?R1?J T "
" ?R?*!
V = N U * DO 5 . 1
D = F\ >FWO
!*D
0 = 1 * 5 3 * 1 3 3 3 5 3 A= FXC 3 * V / 4* D )
03.08
03.0 4
03.3 6
03.33
33.10
03.12
N 1 =.H - L + 1 5 S XI =0 5 3 Y1 =3
J=L*K5 D 3 .1 2
X I = X 1 / M 15 S Y 1 = Y 1 / N 1 5 S 8 = 3 5 S 8 1 = 0 5 5 S
I = L * H 5 DO 4
M= 3 / S 15 S 3 = Y 1 - M A X 15 S ~ = 3 / F S 0 7 ( S 1 * 5 2 ) 5
X I = X 1 + X C J ) 5 S Y 1 = Y 1 + Y C J ) 55
5
F
3
F
8
S
K=N-1
04.08
S S= 5 + ( X ( I ) - X ! ) * ( Y ( I ) - Y ! )
04.0 4
S S 1 = S 1 + ( X CI ) - X 1 ) t 2
34.0 6 3 S 2 = S 2 + ( Y C I ) - Y l >t ? j R
05.13
05.23
05.33
05.40
S D=FCOMC1 * V ) 5 S D = F X ( 1 * T )
5 YC A ) = FAOO C3 ) * 1 3 5 3D= r X <0 * V / 4*
3 X ( A ) = V 5 S V=V+G
I ! * X < A ) * Y ( A ) 5 R ZTURN
FOCAL
CY < A ) ) * 2
PROGRAM
F I G U R E 5.1
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission
3 4 2 3 6 .5 0 MHz
34237. 4 4 MHz
(D/A = 2 5 5 0 )
(D/A: 3 6 0 0 )
CALC. FREQ.
=3 4 2 3 6 . 9 5 M H z
(D/A = 3 0 5 5 )
PLOT
OF
LINE
DATA
FIGURE
ABSORPTION
5.2
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
139
♦GO
:2 1
■:300
:2550
S3 6 0 0
= 9559.0000=
= 2600.0990=
= 2650. 3009 = .
= 2 7 0 0 . 0 3 90=
= 2750.0000=
—
2899.0090=
= 2859.0099=
= 2993 * 0390 =
= 2953.3300=
= 3900.9 33 9=
= 30 5 0 . 0 3 9 0 =
= 3100.0330=
= 3153.0009=
= 3290 * 0390 =
= 3259.0309=
= 3 3 0 9 . 0939=
= 3350.0303=
= 3409.0009=
= 3453.3932=
3500.9000=
= 3550.9003=
N!J=
R 1=
=
3955.6000
0.9931
1.9141
2.2266
2.5781
2.3516
3.9859
3.4189
3.6328
3.9258
4.9234
4.1797
4.1797
4.1797
4.023 4
3.7891
3.5547
3 . 3 59 4
2.92 97
2 . 6 9 53
2.3823
2.1289
1.9141
A=
R=-
.
4.179 7
3.9973
4236.9533*
PRINTOUT
LINE
OF
ABSORPTION
DATA
FIGURE
5.3
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
140
a v e rtic a l lin e on the p lo tte r output.
The program, although employing a somewhat inadequate method
fo r fin d in g a lin e peak frequency, does in dica te th a t programming
control over the spectrometer can be r e la tiv e ly simple - the datataking ro utine o f the program o f Figure 5.1 consists o f the group 1
and group 5 in s tru c tio n lin e s .
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
141
SELECTED REFERENCES
1)
U n ive rsity o f Wyoming Department o f Physics: Status Report on NASA
Grant NGR 51-001-020 fo r the Period 1 January 1967 to 1 January
1969, Submitted by Edgar A. Rinehart.
2)
Prelim inary Operating and Service Manual: Model 8400 C Molecular
Rotational Resonance Spectrometer. Hewlett-Packard.
3)
PDP 8/1 Maintainance Manual. Volume I , I I . D ig ita l Equipment Cor­
p o ra tio n , Maynard, Massachusetts, 1968.
4)
Logic Handbook.
1968.
5)
Small Computer Handbook. D ig ita l Equipment Corporation, Maynard,
Massachusetts," T'968.
6)
Users Handbook. D ig ita l Equipment Corporation, Maynard, Massa­
chusetts’, 1968.
7)
In s tru c tio n Manual: Model 4047/43 10 Channel Analog M u ltip le x e r.
b urr Brown Research’ Corporati on,"Tucson ."'"Arizona",' 19’68.
8)
7590C/7590CR Automatic P lo ttin o System: Operating and Service Manual.
Hewlett-Packard/Moseley D iv is io n , Pasadena, C a lifo rn ia , 1965.
D iq ita l Equipment CorDoration, Maynard Massachusetts,
9) Adjustment Procedure fo r Model FR-310M and FR-350M Readers.
Engineering, In c ., Melbourne, F lo rid a .
Soroban
18) Operating In s tru c tio n s : MRS Baratron Typ£ 77 Pressure Meter Using
lype 77H Pressure HeacT, Type 77M"^XR In d ic a to r. MRS"'Instruments^
In c . ."ThTrTiligTon, Massachusetts.
11) Gordy, W., W. Smith, R. Trambarulo. Microwave Spectroscopy.
York: Dover P u b lica tio n s, In c ., 1953.
12) Townes, C. H. and A. L. Schawlow.
McGraw-Hill, 1955.
Microwave Spectroscopy.
New
New York:
13) W ollrab, James E. Rotational Spectra and Molecular S tructu re .
York: Academic Press, 1W7T
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
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