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Active and passive RF and microwave frequency multipliers

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Active and Passive RF and Microwave
Frequency Multipliers
By
DONALD GONZELAS THOMAS, JR.
B.S. (Howard University) 1987
M.S. (University o f California, Davis) 1993
DISSERTATION
Submitted in partial satisfaction o f the requirements for the degree of
DOCTOR OF PHILOSOPHY
in
Electrical and Computer Engineering
in the
OFFICE OF GRADUATE STUDIES
of the
UNIVERSITY OF CALIFORNIA
DAVIS
Approved:
Committee in Charge
1998
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Abstract
RF and microwave frequency multipliers form an extremely important class of
devices which are utilized in a broad range o f modem electronic systems. These
components are frequently employed in such diverse applications as commercial wireless
communication systems, microwave transmitters and receivers, and military systems.
Frequency multipliers are catogorized according to their nonlinear mechanism for
producing harmonics: i) passive and ii) active. This research encompasses an in-depth
study o f frequency multipliers within each of the fundamental classes mentioned above
delineating the theory, operation, and properties o f frequency multipliers. Contributions
to the advancement o f frequency multiplier technology are presented in this study along
with contributions applicable to other nonlinear circuits such as mixers. A number of
analyses and studies are performed for optimizing the performance of frequency
multipliers. Other areas addressed in this reasearch include the development of accurate
nonlinear circuit models, a review of existing design techniques along with improved
design techniques delieanted in this work, pertinent nonlinear properties of the devices
used in multiplier development, and fundamental performance descriptions.
ii
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Acknowledgements
The author gratefully acknowledges Professor G. R. Branner for his many
contributions to this work and Dr. Giovonnae Anderson for her mentoring and support.
In addition, overwhelming gratitude is expressed to my parents for their encouragement
and guidance, my friends A. Bryant, I. Dennis, D. Hamilton, D. Ligon, I. Turner, and R.
Turner for support and encouragement, and all my other friends who are too numerous to
name for understanding the concept “Friendship is Essential to the Soul”. Lastly, but
certainly not least, I would like to thank my Creator for making this possible.
Dedication
This dissertation is dedicated to the memory of my grandparents: Mr. and Mrs.
Douglas Lay and Mr. and Mrs. Robert E. Thomas.
iii
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C o n tents
Chapter 1 Introduction and Background
1
1.1
Introduction
1
1.2
Description of Research
3
Chapter 2 Applications
2.1
6
Applications
2.1.1 Communication systems
2.1.2 Cellular applications
Chapter 3 Passive Frequency Multipliers
6
6
9
13
3.1
Introduction
13
3.2
Background and Theory
3.2.1 Diode model
3.2.2 Non-linear mechanism
3.2.3 Voltage-capacitance and
charge-capacitance characteristics
3.2.4 Power considerations
3.2.5 Optimization o f efficiency
3.2.6 Idlers
13
15
18
26
32
35
39
3.3
Analysis Techniques
42
3.4
Pertinent Properties of Passive Multipliers
43
3.5
Classical Realizations
45
3.6
Passive Multiplier Design Techniques
3.6.1 Existing design techniques
3.6.2 State-of-the-art
54
54
60
Chapter 4 Active Frequency Multipliers
67
4.1
Introduction
67
4.2
Fundamental Performance Descriptions
70
iv
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4.3
Pertinent Properties o f the Active Device
75
4.3.1 Nonlinear modeling
75
4.3.2 Quantification o f nonlinearities
145
4.3.3 Nonlinearities valuable for frequency multiplication
166
4.3.4 Quantification o f detrimental parasitics
173
4.3.5 Optimum bias selection referencing harmonicterminations 175
4.4
Analysis Technique and Software
4.4.1 Frequency-domain technique (Power Series Analysis)
4.4.2 Volterra series analysis
4.4.3 Harmonic balance
196
196
197
200
4.5
Active Multiplier Design Techniques
4.5.1 Existing design techniques
4.5.2 Unified design technique
4.5.2.1 Illustration of Unified Design Technique
4.5.2.2 Experimental Results
4.5.2.3 Summary of Results
4.5.3 Reflector philosophy
4.5.3.1 Reflector Networks
4.5.3.2 Consideration o f Reflection Phase Angle
4.5.3.3 Effect o f Reflection Phase Angle
on Conversion Gain
4.5.3.4 Narrow band Doubler Design
4.5.3.5 Medium Band and Wide Band Doubler Designs
4.5.3.6 Alternate Design Topology
206
206
215
217
222
228
239
239
244
Chapter 5 Conclusion
5.1
5.2
248
252
257
259
275
Summary
Future Work
275
277
Appendix A. Block Diagram of FET IV Curve Measurement
280
Appendix B. Sample Sensitivity Data File o f Computer
Optimization Program
282
Appendix C. Sample Computer Optimization Subroutine
Sample Input Data File of Optimization Program
Sample Output Data File of Optimization Program
296
327
328
Appendix D. Sample Test Program Files
369
V
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Appendix E. M anufacture Data Sheet of Devices Used in this Study
373
Appendix F. Sample Test Data from Devices Used in this Study
391
Appendix G. Listing of Publications
397
vi
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Chapter 1
Introduction and Background
1.1
Introduction
Frequency multipliers are harmonic generators which produce various frequency
multiples o f an input (fundamental) frequency and are often employed in RF and
microwave systems. High-frequency signals are generated from lower-frequency signals
by harmonic multiplication, as demonstrated in the simple analysis shown below in
Figure 1.1.1. The circuit designer seeks to maximize the power delivered to the output
load at the N* harmonic.
fn
fo u t ~ N fn
Figure 1.1.1 Simple Harmonic Multiplier
The capability to optimize the performance o f the multiplier can improve the
overall performance o f the specific system. This enhanced performance leads to this
optimization becoming a crucial component in the development o f the system. Multiplier
performance is dependent upon the nonlinear device producing the required frequency
harmonics and the design technique employed. The most important design
considerations in frequency multipliers are conversion gain, harmonic suppression,
output power, efficiency, dc bias requirements, and bandwidth. Frequency multipliers
1
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exhibiting high conversion gain, good harmonic suppression, wide bandwidth, and high
efficiency are achieved from optimum designs. As will be discussed, many authors give
various, contradictory means of optimizing the performance of frequency multipliers.
One o f the dominant operating parameters o f a frequency multiplier is its
conversion gain or conversion loss. The conversion gain is the ratio o f the output power
at the desired harmonic frequency to the input power at the fundamental frequency. It
has been demonstrated that various parameters affecting the conversion gain include the
bias level, input power, harmonic terminations, and the nonlinear device producing the
frequency harmonics [1-7]. Techniques which m axim ize the conversion gain are
necessary for the development of frequency multipliers.
The greatest contributions to frequency multiplier technology addressed in this
research will occur with the active multipliers. With the advent o f new active devices,
such as HEMT’s, PHEMT’s, and HBT’s, new multiplier designs incorporating these
devices are desired. This has led to the emergence of new research area where little
information has been reported in the literature. This research work addresses some of
these areas. Some areas considered are the development o f accurate nonlinear circuit
models, identifying pertient properties of the transistor, optimizing multiplier designs,
and improving some o f the existing design techniques. As previously mentioned, the
greatest contribution to frequency multiplier technology occurs with active multipliers.
2
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1.2
Description of research
A thorough and concise discussion of active and passive frequency multipliers is
presented in this work. Presently, in perusal o f the literature, an in-depth study on active
and passive frequency multipliers presented as a collection in one volume is nonexistent.
In this regard, this research work presents the first in-depth study of active and passive
multipliers presented in one collection. Chapter 2 discusses practical applications of
frequency multipliers, demonstrates the significance of multipliers, and highlights
advantages associated with their use. Passive multipliers are discussed in Chapter 3 in
which background and reporting material from the literature are presented. The
background and theory of operation of passive multipliers are discussed delineating
general operation. In addition, several sections discussing analysis techniques of passive
multipliers, pertinent properties, classical realizations, and passive multiplier design
techniques are provided. The discussion of active multipliers is relegated to Chapter 4.
In this chapter, the pertinent properties of the active device including nonlinear modeling
and quantification of nonlinearities valuable for frequency multiplication are presented.
A summary o f existing nonlinear models is presented proceeded with a discussion on the
development o f accurate nonlinear models used in this research work. Original
contributions are presented in the development of these nonlinear models in efforts to
improve the accuracy of the models as shown in section 4.3.1. One o f the primary
objectives of this research is to develop a systematic procedure for the design o f active
multipliers. Thus, a summary of active multiplier design techniques is delineated in
Chapter 4 beginning with existing techniques and concluding with new, original design
techniques developed by the author, as shown in section 4.5. Chapter 5 concludes with a
3
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summary of the outcome of the research efforts undertaken and suggestions for future,
ongoing efforts.
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References
[ 1]
M. Gupta et al., “Performance and design o f microwave FET harmonic
generators,” IEEE Transactions on Microwave Theory and Techniques, Vol.
MTT-29, No. 3, pp. 261-263, 1983.
[2]
Y. lyama et al., “Second harmonic reflector type high-gain FET frequency
doubler operating in K-band,” IEEE MTT-S International Symposium Digest, pp.
1291-1294, 1989.
[3]
R. Stancliff, “Balanced dual gate GaAs FET frequency doublers,” IEEE MTT-S
International Symposium Digest, pp. 143-145,1981.
[4]
R. Gilmore, “Concepts in the design of frequency multipliers,” Microwave
Journal, pp. 129-139, March 1987.
[5]
C. Rauscher, “High-frequency doubler operation o f GaAs field-effect transistors,”
IEEE Transactions on Microwave Theory and Techniques, Vol. MTT-31, No. 6,
pp. 462-473, 1983.
[6]
E. Camargo and F. Correra, “A high gain GaAs MESFET frequency quadrupler,”
IEEE MTT-S International Symposium Digest, pp. 177-180, 1987.
[7]
M. Borg and G. R. Branner, “Novel MIC bipolar frequency doublers having high
gain, wide bandwidth and good spectral performance,” IEEE Transactions on
Microwave Theory and Techniques, Vol. 39, No. 12, pp. 1936-1946, December
1991.
5
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Chapter 2
Applications of Frequency Multipliers
2.1
Applications
The extension of system operating frequencies into higher frequency bands has
led to considerable interest in generating RF power at lower frequencies and using a
nonlinear device to achieve RF power at a higher harmonic frequency. Harmonic
generators provide a convenient source of signals at higher frequencies, where direct
generation from an oscillator is difficult or inconvenient. The frequency multiplier
produces an output signal at a harmonic frequency multiple o f the fundamental input
frequency and eliminates the requirement for a high frequency oscillator. The ability to
design frequency multipliers generating the higher harmonic frequency has made
frequency multipliers important circuits in RF and microwave components and, thus, they
find a wide range of use in the electronics arena. Potential uses include radar systems,
communications systems, subscriber radio systems, and low-phase-noise EW
applications.
2.1.1
Communication Systems
As an illustration demonstrating the convenience of a frequency multiplier,
consider a communication system requiring a 15 GHz local oscillator source as shown
below in Figure 2.1.1.
6
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Mixer
RF
Outpu
LO
15 GHz
Figure 2.1.1 Configuration without Frequency Multiplier
The configuration shows a 15 GHz source driving the LO chain of the mixer.
Alternately, the 15 GHz source can be replaced with a 5 GHz local oscillator and
frequency tripler to obtain the required 15 GHz signal. Advantages in using the 5 GHz
source over the 15 GHz source lie in the cost associated with the two sources. Usually,
high frequency components are more expensive than lower frequency devices.
Additionally, the 5 GHz source could possibly pose less of a design challenge than the 15
GHz source. With this change in the configuration, the final circuit can be represented by
Figure 2.1.2 which employs the frequency multiplier.
Mixer
RF
Outpu
LO
15 GHz
Frequency
Tripler
5 GHz
Figure 2.1.2 Configuration with Frequency Multiplier
7
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As an additional exercise demonstrating the advantage in cost reduction
associated with typical, high frequency multipliers, consider the scenario where a 10 GHz
oscillator is required to provide power to the LO port of a mixer similar to Figure 2.1.1.
A 10 GHz oscillator meeting the required specification is a Hewlett-Packard oscillator
(part number VTO-8950) with a price of $174. An alternate topology uses a frequency
quadrupler fed with a 2.5 GHz oscillator. A frequency quadrupler designed with a
Fujitsu FHX35LG HEMT device using microstrip topology along with all associated bias
components gives a total cost o f $5.50. A 2.5 GHz oscillator provided by HewlettPackard (part number VTO-8200) costs $88 and, therefore, the cost of the 2.5 GHz
oscillator and quadrupler gives a total cost of $93.50. Hence, this indicates that there is a
cost savings of $80.50 (or 46%) utilizing the topology which includes a quadrupler and a
lower frequency ocsillator. For high volume applications, this is an enormous cost
reduction.
Frequency multiplier applications have been extended to Monolithic Microwave
Integrated Circuit (MMIC) receivers in communication systems [1-4]. One such
application is shown in Figure 2.1.3 [2]. In this configuration, two doublers are used in
series to supply the LO chain o f the mixer. Using these doublers in the topology allows a
6.5 GHz VCO to be implemented. The 6.5 GHz signal is feed into the two frequency
doubler circuits which produce an output signal at 26 GHz. Without the use o f the two
doubler circuits in the block diagram, a 26 GHz VCO would have been required.
8
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LNA
Outpu
RF Input
26 GHz
Amplifier
Frequency
Divider
6.5 GHz
VCO
X2
13/26 GHz
Doubler
X2
DC
Control
PLL Controller
Figure 2.1.3 Block Diagram of 26 GHz MMIC Receiver Model
2.1.2
Cellular Applications
Wireless applications operating in the 900-2500 MHz frequency range frequently
use frequency multipliers in their design topologies. The systems include synthesizers,
transmitters, receivers, and transceivers [5]. A transmitter topology demonstrating the
use o f frequency multipliers is shown below in Figure 2.1.4. The modulated signal of
450 MHz is multiplied by the doubler to produce a signal o f 900 Mhz for transmission.
Again, as demonstrated in the preceding section, the cost advantage o f using a frequency
multiplier along with a lower frequency voltage-controlled oscillator for high volume
applications make the topology shown in Figure 2.1.4 attractive.
9
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VCO
Frequency
Doubler
Baseband
Input
Filter
Power
Amplifier
Bandpass
Filter
PLL
Figure 2.1.4 Direct VCO Modulator Transmitter
The receiver topology using a frequency doubler is shown in Figure 2.1.5. The
doubler is placed in the LO chain of the downconverter. The downconverter produces an
IF which is signal-processed to obtain the desired information from the signal.
Mixer
Filter
Amplifier
RF
Demodulator
LO
Frequency
Doubler
Figure 2.1.5 Receiver Employing Frequency Multiplier
10
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A/D
Converter
As a final example, a block diagram of a transceiver employing the use of a
frequency doubler is shown in Figure 2.1.6 [5]. This topology uses a single LO source.
The doubler is used in the LO chain o f the receiver and used to produce the transmitting
frequency in the transmitter.
Demod
Filter
LNA
Image
Filter
LNA
Frequency
Doubler
Filter
vco
Amplifier
1— Filter
PLL
Figure 2.1.6 Transceiver Employing Frequency Multiplier
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References
[1]
J. Lester et al., “High performance HEMT MMIC'c for low cost EHF satcom
terminals,” IEEE Microwave and Millimeter-Wave Circuits Symposium, pp. 11
116, 1992.
[2]
P. Staecker, “mm-Wave transmitters using power frequency multipliers.”
Microwave Journal, pp. 175-181, Februaryl988.
[3]
A. Chu et al., “Monolithic analog phase shifters and frequency multipliers for
mm-wave phased array applications,” Microwave Journal, pp. 105-119,
December 1986.
[4]
R. Mott, “High-performance frequency doublers for the COMSTAR beacon.”
COMSAT Technical Review, Vol. 7, No. 2, pp. 556-577, Fall 1977.
[5]
Personal conversation with Andy Dao.
12
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Chapter 3
Passive Frequency Multipliers
3.1
Introduction
As previously mentioned, frequency multipliers are harmonic generators which
produce frequency multiples of an input (fundamental) frequency. At radio and
microwave frequencies, frequency multipliers typically employ a nonlinear device to
generate the desired harmonic spectrum. The choice o f this nonlinear device divides
multipliers into two categories: passive multipliers and active multipliers. In the case of
the active multipliers, the nonlinear device includes any o f the devices in the transistor
classes (BJT, FET, MESFET, etc) as will be discussed in the following chapter. This
chapter will discuss the development of passive multipliers. This discussion will include
the basic theory and operation o f passive multipliers, various devices which are typically
used in the development o f passive multipliers along with various advantages and
disadvantages, the nonlinear mechanism responsible for harmonic production, power
considerations, optimization o f efficiency, realizations, and design topologies.
3.2
Background and Theory
As mentioned, frequency multipliers at radio frequencies typically require a
nonlinear element to produce the desired harmonic spectrum. For passive multipliers,
this requirement is fulfilled by the exploitation o f the nonlinear characteristics of
nonlinear resistors, nonlinear inductors, or nonlinear capacitors. The excitation of these
devices by an input fundamental frequency produces an output spectrum possessing the
desired harmonic output o f interest. Typical nonlinear devices providing the
13
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aforementioned properties in the development o f passive frequency multipliers include
rectifying metal-semiconductor junctions with their nonlinear current-voltage
characteristics, reverse-biased metal-semiconductor or pn-junctions with their nonlinear
capacitance, and nonlinear transmission lines having distributed nonlinear capacitance
[!]•
As mentioned, harmonic generation is produced in a passive frequency multiplier
whenever a sinusoidal input signal drives a nonlinear impedance. A variable resistance,
inductance, or capacitance whose magnitude varies instantaneously with the applied
voltage or current characterizes this nonlinear impedance. Semiconductor diodes have
been reported throughout the literature as an efficient means of providing the necessary
nonlinear characteristics for passive multiplier design [1-31]. The diodes have various
characteristics which produces, as expected, various performances.
Varactor diodes are commonly used by microwave designers in the development
of passive multipliers with great success [2-5], The varactor diode is a variable-reactance
element where the diode junction capacitance changes nonlinearly as a function o f the
applied voltage, as will be discussed in the following section. Varactors are classified
into two major categories: 1) junction varactors which are widely used at microwave
frequencies and 2) Schottky diode devices typically used for millimeter wavelength
applications. In a derivation by Manley and Rowe [34], which will be discussed later,
and mentioned by other authors [7, 35, 39], a nonlinear capacitance (reactance) harmonic
generator such as that developed with a junction varactor, can theoretically generate
harmonics with efficiencies ( rj=Pou/P tn) approaching 100 percent. On the other hand,
passive frequency multipliers utilizing passive nonlinear resistors for harmonic
14
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generation have at most an efficiency of I/N2 where N is the order of the harmonic as
shown by Page [36] and commonly referenced by other authors [3-4, 7], Therefore, in
the case o f a frequency doubler, theoretically, the highest efficiency achievable is 25
percent (\N=2).
The step recovery diode is also used in passive frequency multiplier design for
lower frequencies (< 30 GHz) [5]. The step recovery diode is another variable-reactance
element which is a variation o f the varactor diode. Archer states that the step recovery
diode is a pn-junction diode explicitly designed to enhance the charge storage capacitance
associated with minority carrier injection during forward conduction and that the chargestorage capacitance supplies the nonlinearity necessary for harmonic generation. Based
on the available literature, step recovery diodes are not as popular in comparison with the
varactor diodes in the design of passive frequency multipliers. Therefore, the ensuing
discussions will not focus on step recovery diodes.
3.2.1
Diode Model
As will be mentioned in the following chapter, one o f the most important tools of
microwave circuit designers is the availability of device circuit models which allows the
performance o f the device to be predicted before and after embedding with external
networks. Since a diode model is essential in the understanding and development of
passive frequency multipliers utilizing these devices as the source o f nonlinearity, the
following discussion will be devoted to the circuit model o f the diode.
An equivalent circuit model for the varactor model is shown below in Figure
3.2.1. This simple circuit model contains a frequency dependent series resistance (Rs), a
15
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voltage dependent nonlinear conductance (g(v)) in parallel with the voltage dependent
junction nonlinear capacitance C/v) where v is the voltage over the junction[5, 26].
VW
C,(v)
Figure 3.2.1 Varactor Diode Circuit Model
The nonlinear conductance, which can produce resistive multiplication, is defined as:
[26]
8i
S(y) = ^
av
g
(3.2.1)
(3.2.2)
= Isa,
sot (eXP (~ “ ) ~ 1)
rjkT
where /* ,, is the diode saturation current, q is the electron charge, 7 is the ideality factor
of the diode, k is the Boltzman constant, and T is the diode temperature. The nonlinear
16
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capacitance (C, (v)), which is responsible for supplying the nonlinear reactance, is
defined as [26]:
C ,(v) =
CJO
(3.2.3)
where CJOis the zero bias junction capacitance, fo, is the built-in voltage potential, and y
is related to the doping profile in the epitaxial layer. Raianen states that typical values o f
these parameters for a varactor diode with radius o f 1-5 pm is: the zero-bias junction
capacitance (CJO) ranges from 3-20 fF, the series resistance (Rs) ranges from 5-20 ohms,
the built-in potential ($*,-) ranges from 0.6-1.0 volt, and /ranges from 0.4-0.5. The series
resistance (Rs) arises from the undepleted materials in the diode and the contact
resistance. [2]
As shown in this model, suitable nonlinear elements exist for harmonic
generation; namely the nonlinear resistor (l/g(v)) and the nonlinear capacitance (C/vj).
As previously mentioned and will be discussed in a following section, harmonic
generation due to the nonlinear reactance produced by Cj (v) is, theoretically, more
effective because it is possible to convert all o f the available power applied to a lossless
nonlinear reactive element to output power at any higher harmonic frequency. An ideal
resistive multiplier utilizing the nonlinear resistor (l/g(v)) theoretically has a maximum
efficiency o f only 1/N2 where N is the harmonic frequency.
17
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3.2.2
Non-linear mechanism
As previously mentioned, high-frequency signals can be generated from lower-
frequency signals by harmonic multiplication. Frequency multipliers provide and
efficient means o f exploiting the nonlinear characteristics of various devices to provide
the desired harmonic multiplication. The circuit designer of frequency multipliers seeks
to accentuate the device nonlinearity in a particular manner such that exciting the
nonlinear device by a sinusoidal input signal at a fundamental frequency produces an
output spectrum at harmonic frequencies o f the input fundamental which, obviously,
includes the desired harmonic of interest. This section will identify and discuss the
general nonlinear mechanisms responsible for harmonic production in passive frequency
multipliers.
It was noted in the previous section that nonlinear resistors, nonlinear capacitors,
and nonlinear inductors could be exploited for their nonlinear characteristics. Typical
nonlinear devices providing these nonlinear characteristics essential for harmonic
production include rectifying metal-semiconductor junctions with the nonlinear currentvoltage characteristics, reverse-biased metal-semiconductor or pn-junctions with their
nonlinear capacitance, and nonlinear transmission lines having distributed nonlinear
capacitance [1]. As a simple example demonstrating harmonic generation, consider a
nonlinear device whose nonlinear transfer function can be represented as a polynomial of
the form:
Vm, = a y m + a2(Viny
(3.2.4)
18
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where a / and a2 are constants. Applying a sinusoidal input ( Vm = cos a x ) into equation
3.2.4 gives:
Vaut = a, cosatf + a ,(co scot)3
= a, cosax + a ,( —cos3atf + -cosatf)
‘ 4
4
= (a,H
3a,
a,
-)cosatf + — cos3atf
4
4
__
(3.2.:>)
Equation 3.2.5 shows that an output harmonic is generated at the fundamental frequency
(a)) and the third harmonic frequency (3 a;). Therefore, for the specific application o f a
frequency tripler, this nonlinear device as represented by the transfer function given in
equation 3.2.4, theoretically provides the nonlinear characteristics for the design o f a
frequency tripler.
Throughout the literature, researchers and designers have developed passive
multipliers typically with nonlinear diodes. For this reason, the ensuing discussion
focuses on the nonlinear mechanism associated with semiconductor diodes which are
used throughout the microwave industry. Although the discussion is specific to diodes,
the concepts presented are applicable to other studies as well.
As mentioned, semiconductor diodes have been reported throughout the literature
as an efficient means o f harmonic production. In an attempt to demonstrate the nonlinear
mechanism o f the diode, consider an abrupt pn-junction diode shown below in Figure
3.2.2 excited by an applied voltage (Va) [37]:
19
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-x d -
p-region
n-region
Figure 3.2.2 PN-Junction Diode Structure
Muller [37] shows that:
2s , ..
1
1
X a = X p + X n = — (.& -K X— + — )
Q
N.. N .
X„ =
2e(<!>-Va)
(3.2.6)
(3.2.7)
« w .o + % , >
1
2
X. =
2s($ - Vca)
(3.2.8)
20
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where
Xp = the depletion region extending into the p-type semiconductor
Xn = the depletion region extending into the n-type semiconductor
X(( = the total depletion region
<p = built-in potential
Va = applied voltage
Na, Nrf = semiconductor dopant concentrations
By charge neutrality
(3.2.9)
Q = q NJX n =q NaX p
(3.2.10)
dQ = qN ddXn = qNad X p
(3.2.11)
dQ _ dQ d X p
dVa d X p dVa
(3.2.12)
£
= qN
qeNgNd
2
(3.2.13)
1
(3.2.14)
C jo
(3.2.15)
21
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(3.2.16)
where
From this analysis, equation 3.2.15 shows that the magnitude o f the junction capacitance
varies nonlinearly as a function o f applied voltage (V J which is essential for generating
frequency harmonics when a sinusoidal voltage is applied to Va. Using the binomial
series expansion on equation 3.2.15 yields:
= C JO 1+ — ( — ) + —(— )2 - —
(3.2.17)
= a 0 + a xVa + a 2V; + a 3Vj +■
(3.2.18)
2 </>
)3
16 <f>
8 <p
(3.2.19)
1=0
where
a
0
=
C
a,1 =
“
«3=-
jo
/ 2 <p
5 C Jo
7 ,16^r
^3
22
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From equations 3.2.12 and 3.2.18
dQ(Va) = C]{Va)dVu
(3.2.20)
Q ( K ) = jc ,( v jd v ,
(3.2.21)
=
f ( a0 + a , K + a 2r J + - ) J V „
=
2
3
+ 7 a , r : +•
4
(3.2.22)
(3.2.23)
(3.2.24)
=2> ;c
(=0
where
«o =«o
2
«2 = - « 2
Demonstrating the effect o f applying a sinusoidal signal across the pn-junction, the
current across the diode can be calculated from:
/(') =
dQ '
dt ,
(3.2.25)
23
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and inserting equation 3.2.23 into equation 3.2.25 with the pn-junction excited by the
sinusoidal signal Va=cosojt gives:
Q
=
a
S
.
+
- c c >
X
V
;
+
+ ■ ■ ■
c
c
= C (cosox) + —^-cos2 rut + —^-cos3 (ot + ••4<j>
8<f>~
(3.2.26)
= ^ +(C'"+ § ^ )cos‘“ +<^ )“ s2‘*
+ (-^ )c o s3 n * + -
(3.2.27)
32 <p~
and inserting equation 3.2.27 and differentiating gives:
/< o= f
dt
3C
2fflC„
= -w (C yo + ■ ^ r ) sin or —(—^ —) sin 2<ar
3coC
■(— f)sin 3 u tf + -
(3.2.28)
32 q>~
As shown by equation 3.2.28, this example illustrates the various frequency harmonics
produced by the pn-j unction when excited by a sinusoidal source and demonstrates the
nonlinear mechanism by which the semiconductor diode produces harmonic generation.
24
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It is this variable capacitance which has led semiconductor diodes, varactors. etc. to be
vital components aiding microwave engineers in nonlinear circuit development.
25
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3.2.3
Voltage-capacitance and charge-capacitance characteristics
As previously stated, harmonic generators utilizing the nonlinear capacitance
characteristics o f varactors are often employed throughout the microwave industry by
researchers and designers. The voltage and charge-capacitance characteristics of the
varactor diode are important in analyzing and studying the behavior characteristics of
diodes. This section will discuss the relationship between the voltage and the capacitance
and the charge and the capacitance since they are often utilized in studying the
performance and the design o f passive frequency multipliers.
Referring to the diode example in the preceding section along with equations
3.2.12 and 3.2.15 which are restated below in equation 3.2.29 [6]:
C ( v ) = — = ---- ^ ----J
dv (
/V
where
(3.2.29)
v = the voltage across the junction in the absence o f any applied bias
<f>= built-in potential
Cj0 = zero bias junction capacitance
m = index number (1/2 for abrupt junctions and 1/3 for linearly graded
junctions
Scanlan states that the minimum capacitance (Cm,„) occurs at the reverse breakdown
voltage (v=-Vr) such that the junction capacitor at this bias is shown as:
26
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c„„=cJ(-r„)=
cjo
(3.2.30)
Letting Vo=Vr+0 and rewriting equation 3.2.30 gives
cJO=cmm[i+ R
/(p
=c.
1+
V .- * '
(3.2.31)
and inserting equation 3.2.31 in equation 3.2.29 gives
CA
1+
V .-*
C » =
=c„
(3.2.32)
From equation 3.2.29
dQ = Cj (v)dv
(3.2.33)
27
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and inserting equation 3.2.32
Q(v)= \ C t {y)dv
(3.2.34)
l-m
where k is the constant o f integration. When v=<f>, the voltage across the junction is zero
and the charge is zero which indicates that k=0 as well. This allows equation 3.2.34 to be
rewritten as equation 3.2.35 where the charge is represented as a function of the voltage
(3.2.35)
The depletion-region (Xp, X„) and the electric field across pn-junctions increase as
the reverse bias increases [37]. Intuitively, there are physical limitations to these
increases as governed by the structure of the junction and the dopant concentrations. As
the reverse bias increases, eventually a voltage is encountered where the barrier to current
flow is broken and current flow increases substantially. The voltage at which this occurs
is defined as the breakdown voltage iy--V R). At the breakdown voltage (v = -VR),
equation 3.2.35 shows
(3.2.36)
l-m
28
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and recalling that VQ= VR+Ogives
Now, dividing equation 3.2.35 by equation 3.2.37 gives
cl-m
Q (v )_
C rornFo
l-m
y—
V
V
r o
(3.2.38)
J
This expression relates the charge across the junction in terms o f breakdown
characteristics (Vr, Qr) and the minimum capacitance (Cmm).
Often throughout the literature, the capacitance is used in defining the elastance
S(v) where [6-7]
s W = 7C(v)
7 1 an d S " » = 7Cm
^tn-
(3-2J9>
This allows equation 3.2.32 to be rewritten in terms o f the elastance as shown below in
equations 3.2.40 and 3.2.41 where the elastance is written as a function o f voltage.
29
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Referring back to equation 3.2.38, the charge (Q(v)) is expressed as function of v.
Alternately, equation 3.2.38 can be rearranged to give the voltage as a function of the
charge. This is expressed as:
(
Q
'| X -
=K - t - v 0
' Q_)X"
IQ r )
(3.2.42)
and therefore,
1- f Q _ Y ~
<Qr j
= v_ 1- ( O Y
<Qr >
where
y =
(3.2.43)
l-m
30
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Equations 3.2.29 - 3.2.43 show the various mathematical expressions for the
characteristics between the voltage, charge, capacitance, and elastance o f pn-junction
semiconductor diodes. Researchers and designers often use these expressions, amongst
others, in analyzing diodes and implementing diodes into multiplier designs.
31
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3.2.4
Power considerations
A discussion on power flow into and out of the nonlinear device is very useful in
understanding the behavior of passive nonlinear devices and their usefulness in designing
passive frequency multipliers as it can be used to predict optimum power and conversion
gain efficiency. This section will discuss the power flow at the various harmonics and
their relation to the performance of frequency multiplier designs, which leads to a
fundamental understanding o f the limitations imposed by diodes.
Manley and Rowe [34] have provided a general relation which is commonly used
throughout the microwave industry discussing the power flow o f a particular class of
nonlinear elements. Manley and Rowe derive general power relations which govern
single-valued nonlinear elements such as nonlinear inductors and capacitors. Their final
derivations, independent o f input power, give two independent equations characterizing
the power content at various harmonics
Manley and Rowe perform their derivation on an ideal nonlinear capacitor but
state that a similar analysis can be performed on a nonlinear inductor. They began their
analysis by evaluating the voltage across the nonlinear capacitor which is defined as
some arbitrary function o f the charge. Then, they write an equation for the charge across
the capacitor represented in a Fourier series. From the charge, they are able to calculate
the current in Fourier series notation. Next, the voltage across the nonlinear capacitor is
given in a Fourier series from which the Fourier coefficients for the voltage are calculated
using orthogonality. After further substitutions and integrations, they conclude with the
following equations:
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
(3.2.44)
(3.2.45)
where m and n are integers representing various harmonics and Pmn is the average power
flowing into the nonlinear reactances at the frequencies mfi and nfi. These equations are
significant in that they indicate that for an ideal, lossless capacitance (with Rs = 0 in
Figure 3.2.1), the sum o f all inward power flow at the different frequencies must be zero.
This indicates, theoretically, that when exciting the nonlinear capacitor at a fundamental
frequency, the output power at the desired harmonic has the same magnitude of the input
power level o f the fundamental. This is achieved provided that all power at the
undesirable harmonics has been reactively terminated which insures that no power is
dissipated at these undesirable harmonics.
As an example demonstrating this procedure, consider exciting a nonlinear
capacitor at the fundamental frequency/ / (m=l, n=0). Then, equation 3.2.44 gives
(3.2.46)
or
00
(3.2.47)
33
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or in general, the sum of all powers flowing at the various harmonic frequencies must be
zero. Equations 3.2.47 indicate that the input power (Pio) at the fundamental is the sum
of the output powers at all harmonics combined. Therefore, this indicates that if external
embedding circuitry to which the nonlinear capacitor is connected is developed such that
the power at all undesirable harmonics are reactively terminated, power delivered to the
load at the desired harmonic can, theoretically, produce conversion efficiencies of 100
percent [5]. Practical diodes, however, exhibit nonzero series resistance (Rs * 0) which
indicates, therefore, that practical conversion efficiencies are less than 100 percent.
34
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3.2.5
Optimization of efficiency
As in the design o f any component, achieving optimum efficiency is an essential goal of
the designer. In the case of passive multipliers, proper techniques should be employed in efforts
to maximize the conversion efficiency o f the multiplier and maximize the power delivered to the
load at the desired harmonic.
The Manley-Rowe equations given in the preceding section indicate that, theoretically, an
ideal nonlinear capacitor can achieve 100 percent conversion efficiency. In practical
applications, nonlinear capacitors (varactors) are not ideal components and, thus, have some loss
associated with them. Therefore, as a general example, the varactor utilized in passive multiplier
design should exhibit low series resistance (Rs) at the frequency and power level of operation [6,
26]. Other requirements necessitate implementing input impedance matching on the input of the
nonlinear device to ensure that the input power is efficiently coupled to the diode. Similarly,
output impedance matching at the desired harmonic of interest should be implemented such that
power generated in the nonlinear device at the output harmonic is efficiently transferred to the
external output load. Significant real power should exist in the diode at the fundamental and the
output harmonic o f interest and low-loss resonators should be utilized as idler circuits [1, 34-35,
38-39], At this juncture, idler circuits have not been discussed but will be discussed in a
following section.
Archer [5] notes that an equivalent-circuit model o f a varactor diode embedded in
external circuitry can be utilized to predict and optimize the performance of a passive multiplier.
Archer shows the equivalent circuit for a varactor multiplier showing the connection between the
varactor and the embedding network as shown below in Figure 3.2.3. In Figure 3.2.3, the
embedding network models the impedance presented to the diode at the fundamental frequency
35
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and other harmonics. The two networks (embedding and equivalent diode circuit model) are
optimized to obtain maximum power transfer between the embedding network and the reactance
o f the diode at the input fundamental frequency and the output harmonics. This optimization can
be performed manually using the mathematical equations governing the response of the networks
or through an optimization routine provided by a commercial circuit simulator.
Diode Circuit Model
E g ( fo )
Embedding Network
Figure 3.2.3 Equivalent Network Model o f Passive Frequency Multiplier
The conversion efficiency is dependent upon the large-signal diode currents and voltages
which are determined by the impedances presented to the diode at the fundamental and higher
harmonic frequencies [5-6]. Simulations can be performed to optimize the conversion efficiency
utilizing the impedances presented to the diode in conjunction with the diode circuit model.
36
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The steady-state large-signal voltage and current coefficients are shown as [5]:
(3.2.49)
k
(3.2.50)
k
w h ere/is the fundamental frequency. The predicted performance and thus, optimization of
efficiency, is determined after solving equations 3.2.49 and 3.2.50 with regards to the boundary
conditions. The boundary conditions are imposed by the diode and the embedding network (the
embedding impedance Ze (f) ). Solutions to equations 3.2.49 and 3.2.50 subject to the boundary
conditions to obtain the nonlinear large-signal behavior of specific multipliers (such as doublers,
triplers, etc.) using idealized models have been calculated and presented by various authors [2-6,
8-31]. Authors present data representing the efficiency, power handling, input and load
resistances, and Pma/Pm, for example, versus frequency for various multipliers. Using plots such
as these, theoretical optimization can be achieved for specific multiplier types utilizing data such
as this.
In summary, it is important to optimize the performance o f frequency multipliers. Chang
states general guidelines for achieving this:
a)
good impedance match on the input and output of the nonlinear device over the frequency
range o f interest, and terminate all idler circuits reactively with low loss
37
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b)
at frequencies other than the fundamental, desired harmonic of interest, and idler
harmonics, the nonlinear device should be mismatched to the embedding circuitry to minimize
power loss
c)
the input and output networks should be isolated physically and electrically
38
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3.2.6
Idlers
An important concept in the fundamental development of passive frequency multipliers,
as briefly alluded to in prior sections, is idler currents and idler circuits. Idler currents are
currents flowing at frequencies other than the input fundamental frequency and output harmonic
frequency which are required for a particular class of passive multipliers [38]. This section will
discuss the property of idlers and demonstrate the requirement of them for particular multiplier
designs.
In section 3.2.3, a discussion was presented demonstrating the voltage and charge
relations o f nonlinear varactors. Referring to equations 3.2.42, it is observed that there is a
square law characteristic exhibited by the diode where the voltage is proportional to the square o f
the charge for an abrupt junction diode (m = 1/2) [35]. Consider the condition in which the
charge across the junction of an abrupt junction diode is represented as a sinusoidal at the
fundamental frequency (a)=2xf):
(3.2.51)
Q(')=Qo +Q\ cos cot
where Qa is the dc biasing component
Inserting equation 3.2.51 into equation 3.2.42 and using the trigonometric identities give:
(3.2.52)
39
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Q„ +Qi cos cot \-
K
Ql
(
2\
Q l+ % -
(3.2.53)
'O'.Q.Q '
Ql
2\
cosox — K Q i cos 2cot
.2Q l)
(3.2.54)
From equation 3.2.54, it is observed that the voltage produced by this charge across the abrupt
junction diode has a dc component, a component at the fundamental frequency, a component at
the second harmonic frequency, but no component at any harmonic greater than 2, which is
required for frequency triplers, quadruplers, etc. The component at the second harmonic
frequency indicates that this suitable for a frequency doubler, however. This example indicates
that except for the case o f the doubler, if currents flow only at the input and output frequencies, it
is impossible to generate harmonics greater than 2 with an abrupt junction varactor. This is an
expected result due to the square law behavior o f the varactor. Thus, in order to achieve output
harmonics for n>2, it is necessary for intermediate currents (idler currents) to flow in the varactor
at specific harmonic frequencies.
The abrupt junction varactor can be thought of as providing a mechanism for frequency
doubling (due to the square law relationship previously mentioned) and for frequency mixing
when idler currents are utilized [7], In the case of mixing, currents flowing at specific harmonic
frequencies are mixed with the fundamental frequency and with each other (if more than one is
introduced) to produce additional currents at various harmonics. Therefore, introducing an idler
current into an abrupt junction varactor at the second harmonic causes the second harmonic to
mix with the fundamental frequency to produce an output at the third harmonic. This additional
idler produces the component necessary for a successful frequency tripler design.
40
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Introducing additional currents into an abrupt junction varactor provides a means for the
device to generate higher harmonics. This extends the use o f abrupt junction varactors to. not
only frequency doubler design, but higher order designs as well.
41
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33
Analysis Techniques
Passive frequency multipliers are nonlinear circuits requiring solutions from
large-signal circuit analysis. As previously stated in preceding sections, the efficiency of
passive multipliers utilizing diodes is affected by the diode parameters, embedding
impedance (Ze(nfa)) at the fundamental and harmonic frequencies, input power level (Pm),
and bias voltage. Various techniques are utilized by researchers and designers for
analyzing and optimizing nonlinear circuits and specifically, passive multipliers. In some
simple cases analytic, closed-form solutions may be obtained for optimizing the
efficiency, however, for most cases the most convenient analysis method is through
numerical analysis. Some of these techniques include the power series analysis, Volterra
series analysis, and harmonic balance techniques where time-domain current and voltage
solutions are sought which satisfy the diode boundary conditions and frequency-domain
solutions are sought which satisfy the external circuit equations. Using these analysis
techniques along with an accurate equivalent circuit model of the passive nonlinear
device, the predicted performance o f the device embedded in external circuitry can be
obtained.
Since the analysis techniques for passive and active frequency multipliers are
similar, the author refers further discussion on this topic to section 4.4 where a detailed
discussion is presented on the analysis techniques mentioned above. Even though
Chapter 4 deals with active frequency multipliers and section 4.4 is tailored around active
nonlinear devices, the analysis techniques are applicable for passive nonlinear devices as
well.
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3.4
Pertinent properties of passive devices
The RF performance of passive multipliers is governed by, among other things,
the pertinent properties of the nonlinear device. These properties can be divided into two
categories [31]: i) those affecting the efficiency of the multiplier and ii) those affecting
the power handling capability of the multiplier. Tolmunen notes that the efficiency of the
nonlinear diode is mostly affected by the cut-off frequency, which will be defined below,
the strength of the nonlinearity, and the type o f multiplication (resistive or reactive, as
discussed in section 3.2). The power handling capability is affected by the device area,
the extent of the nonlinearity, and the breakdown voltage which was previously identified
in section 3.2.3.
Focusing on varactor frequency multipliers, for efficient varactor operation it is
necessary, as expected, for the reactance o f the junction capacitance of the varactor to be
much larger than the device series resistance (Rs in Figure 3.2.1) [5]. Therefore, this
necessitates an upper frequency limit (cut-off frequency) on the usefulness of a given
varactor [6]. The dynamic cut-off frequency is defined as [31 ]:
fed =
(3.4.1)
2nR
where Cmi„ and Cmax are the minimum and maximum capacitance of the varactor and Rs is
the diode series resistance. Therefore, for optimum performance, the cut-off frequency
should be greater than the particular frequency o f application.
43
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A sharp nonlinearity in the C-V response of the varactor results in efficient
harmonic generation. In retrospect, it is the nonlinearity o f the device which is
responsible for harmonic generation. The advantages o f a sharp or steep nonlinearity
depend on the extent of the voltage swing across the diode generated by the input power.
Varactors have high input impedance, thus, enabling large voltage swings to be generated
across the device. A diode with high nonlinearity, even at low input power levels,
produces significant voltage swings, and, therefore, is capable of achieving optimum
performance. Typically, the optimum conditions occur in applications where the
nonlinearity extends over voltages comparable to the voltage swing o f the input power
signal.
Tolmunen states that the power handling capability is proportional to the average
capacitance o f the device area. As in the case of other high power devices, diodes with
large surface areas are able to handle larger input power levels and, consequently,
produce larger voltage swings. In practical diode applications, however, this may result
in matching problems because matching the diode over a broad voltage range is quite
challenging and, thus, trade-offs have to be made. As will be shown in the design
techniques in a later section, another approach commonly used to improve the power
handling capability is to stack devices in series or parallel. This configuration increases
the total area o f the diode thus allowing it to sustain larger voltage swings. Large device
arrays are useful in high power applications.
44
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3.5
Classical realizations
The previous sections highlighted some of the basic properties of passive
multipliers and the fundamental characteristics of nonlinear components which are
utilized extensively in passive multiplier development. As mentioned, the nonlinear
component is embedded in external circuitry to accentuate the desired harmonic. As
demonstrated throughout the literature, various topologies exist for realizing passive
multipliers demonstrating the interaction between the embedding circuitry and the
nonlinear device. This section will highlight some o f the classical realizations utilized
extensively by microwave designers and researchers.
Scanlan and Leeson have presented some simple, classical realizations for passive
multipliers, as shown in Figure 3.5.1 and Figure 3.5.2 [6, 8]. Scanlan identifies the
passive multiplier topology shown in Figure 3.5.las a series model where the varactor
diode is series-mounted with the embedding network. The input and output networks Ft
and Fs , respectively, represent ideal filters at the fundamental frequency and the Nlh
harmonic which permit voltages to exist at the fundamental frequency and the Nth
harmonic, respectively. In other words, Ft acts to short-circuit all frequencies other than
the fundamental frequency and Fx acts to short-circuit all frequencies other than the
harmonic frequency o f interest. Although more sophisticated filters may be required,
parallel LC networks can be synthesized for Ft and Fx at their respective frequencies as
shown by equation 3.5.2.
• • 'T ic
(3'5'2)
45
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Figure 3.5.2. on the other hand, is the shunt diode topology for passive frequency
multiplier design using a nonlinear diode. Again, the input o f output networks. F/ and
F,v, respectively, represent ideal filters at the fundamental frequency and the N,h harmonic
which permit currents to flow at the fundamental frequency and the N*h harmonic,
respectively. This indicates that F/ acts to open-circuit all frequencies other than the
fundamental frequency and Fv acts to open-circuit all frequencies other than the
harmonic frequency of interest. Similarly, F/ and Fv can be synthesized as series LC
networks resonant at the fundamental frequency and the output harmonic frequency of
interest.
Figure 3.5.1 Series-mounted Diode Passive Diode Frequency Multiplier
46
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S2.
Figure 3.5.2 Series-mounted Diode Passive Diode Frequency Multiplier
Faber [1] has discussed the realizations presented by Scanlan with an emphasis
placed on achieving optimum efficiency of the multiplier. Block diagrams of the
realizations (series-mounted and shunt-mounted) shown by Faber are given below in
Figure 3.5.3and Figure 3.5.4.
Z d ou t
Z d in
Input Filtering
and
Matching
Network
-‘Out
Output Filtering
and
Matching
Network
Figure 3.53 Block Diagram of Series-mounted Diode Frequency Multiplier
47
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Zdin
Input Filtering
and
Matching
Network
2 dtUiut
sz .
Output Filtering
and
Matching
Network
Figure 3.5.4 Block Diagram of Shunt-mounted Diode Frequency Multiplier
Recall from section 3.2.4 that the Manley-Rowe power equations imply that it is
theoretically possible to deliver all input power at the fundamental frequency to the
output load at the desired harmonic of interest thereby achieving 100 percent efficiency.
Achieving optimum efficiency requires that power should not be dissipated at any o f the
undesired harmonics either in the input network or the output network. This indicates
that, with regards to Figure 3.5.3, that
M Z * ,( / ) } s O
(3.5.1)
R e{Z *(n /)}= 0
(3.5.2)
48
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when the input and output networks contribute to the device reactance compensation. If
the conditions represented by equations 3.5.1 and 3.5.2 are met. power is not dissipated at
the fundamental frequency in the output network and power is not dissipated at any o f the
harmonic frequencies in the input network, respectively.
Similarly, for Figure 3.5.4, the following conditions are sought:
(3.5.3)
(3.5.4)
Apart from the realizations previously mentioned, several variations of these
topologies have been utilized as well. At RF and microwave frequencies several diodes
connected in series or parallel have been utilized to handle cases where there was
insufficient power, voltage, or current handling capability of a single device or from
inconvenient single-device impedance levels. Connecting m diodes in series (stacking)
produces a breakdown voltage which is m times as high and m diodes in parallel provide
m times higher current [1], Therefore, topologies such as those shown in Figure 3.5.5
and Figure 3.5.6 are commonly encountered.
49
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T
s
ii
ii
ii
ZL
Figure 3.5.5 Series Connected Diode Multiplier Topology
Figure 3.5.6 Parallel Connected Diode Multiplier Topology
The circuit complexity of passive multipliers can be increased even further.
These include topologies shown in Figures 3.5.7 -3.5.10[1, 5-6, 19]. The anti-parallel
topology of Figure 3.5.7 produces currents containing components at the fundamental
frequency and higher odd-order harmonics. This can substantially simplify the design of
input and output filters in the development o f odd-order multipliers. Figure 3.5.8 shows
the anti-series topology utilizing a transformer between the input signal and the diode
circuit. The transformer provides a 180-degree phase shift between the input signal
voltages feeding the two diodes. Therefore, the current components cancel in the load
50
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producing no voltage across the load at the fundamental frequency. In contrast to the
anti-parallel topology, the anti-series topology provides even-order harmonics and.
therefore, leads to less stringent requirements on the input and output filters. Figure 3.5.9
utilizes a transformer in the anti-parallel series topology as well. Faber notes that the
odd-order components are in phase so, therefore, when the odd-order components flow
through the transformer primary winding, they do not excite the load mesh. The evenorder components, on the other hand, are o f opposite phase so they cancel in the input
signal source branch but excite current in the load mesh. This action causes the antiparallel series topology to produce even-order harmonic multiplication. Finally, Figure
3.5.10 shows a bridge frequency multiplier. Similarly to frill-wave rectifiers, bridge
rectifiers can be used to produce even-order harmonic multiplication.
Figure 3.5.7 Anti-parallel Diode Pairs
51
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Figure 3.5.8 Anti-series Diode Pair
Figure 3.5.9 Anti-parallel Series Connected Diodes
52
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Figure 3.5.10 Bridge Frequency Multiplier
53
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3.6
Passive Multiplier Design Techniques
3.6.1
Exiting design techniques
Numerous design techniques exist for the design of passive multipliers utilizing
various topologies, many o f which are presented in the previous section. This section
presents, in perusal of the available literature, various existing design techniques and, in
some cases, details the performance of such designs.
A fundamental topological representation for realization o f passive
RF/Microwave multiplier circuits is shown in Figure 3.6.1 where networks N/ and iV? are
on the input and output of the nonlinear device, respectively. As mentioned in a previous
section, multiplier performance is governed by embedding circuitry, networks Ni and N2,
and the pertinent properties of the nonlinear device. Various authors have used various
networks in the synthesis o f networks Ni and JV? o f Figure 3.6.1. Traditional synthesis o f
networks Nj and V? have included short-circuited and open-circuited stubs at the
fundamental frequency and various harmonics [4, 13-14], impedance matching and filter
networks [3, 15-18], and waveguides and filters [2, 20-22, 25-30].
Passive
Nonlinear
Device
Figure 3.6.1 Passive Frequency Multiplier Realization
54
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Referring to Figure 3.6.1, in the synthesis of A'/ and A'?, several authors have
utilized short-circuited and open-circuited stubs for low frequency and high frequency
applications. Gavan [4] uses microstrip stubs in the development o f a 1250 - 2500 MHz
step recovery diode frequency doubler. Gavan synthesizes Ni with a XJS stub (at 2f0) on
the input network to provide a short circuit for the second harmonic signal and
synthesizes Af? with a XJ4 microstrip stub (at f 0) which provides a short-circuit to ground
for the fundamental frequency. Using this design technique, Gavan achieves conversion
gain efficiency o f 75 % and does not present any data on harmonic suppression. Chen
[13-14] performs a 47 - 94 GHz Schottky barrier varactor diode frequency doubler
design utilizing MMIC technology. Chen uses a XJ2 short-circuited stub (at 2fa) on the
input network to create an RF short at 94 GHz and a XJ4 short-circuited stub (at f a) on
the output to create an RF short at the fundamental frequency. This high frequency
MMIC design provided a maximum conversion efficiency o f 25 % (6 dB conversion
loss).
Several authors have developed passive frequency multipliers utilizing impedance
matching networks and filters in the input and output networks [3, 15-18]. The
impedance matching networks are employed to match the input and output impedances of
the nonlinear device while the filters are used to attenuate specific harmonics. Gavan [3]
designs a 1250 - 2500 MHz varactor frequency doubler utilizing the shunt varactor
topology shown in Figure 3.5.4 along with a low-pass filter in the input network and a
two-section coupled band pass filter at 2500 MHz in the output network. This design
technique utilized by Gavan yields a maximum conversion gain efficiency o f 71 percent.
Chang [18] develops a varactor 46-92 GHz frequency doubler utilizing a topology similar
55
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to that shown in Figure 3.5.4. Input and output networks are synthesized with filters and
additional matching networks to achieve optimum power transfer at the source and load.
Chang’s design achieves a conversion loss o f 8 - 9 dB over a 500 MHz bandwidth.
Furthermore, some authors have chosen to utilize a balanced topology for the
design o f frequency multipliers [19-22]. A block diagram o f a balanced design topology
is shown below in Figure 3.6.2. In typical balanced circuits, a 180-degree phase
difference in the input signals feeding the nonlinear device produces fundamental signals
and other odd harmonic signals with opposite phase. By destructive interference, the
fundamental and other odd harmonics cancel giving good harmonic suppression while the
second harmonic signals, on the other hand, interfere constructively, thereby, enhancing
the output signal at the second harmonic. This design technique will be revisited in
Chapter 4 in the discussion o f active frequency multipliers.
Phase
Shifter/
Power
Splitter
Passive
Nonlinear
Device
Combiner
Passive
Nonlinear
Device
Figure 3.6.2 Block Diagram o f Typical Passive Balanced Frequency Multiplier
56
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Bitzer [19] utilizes a balanced topology similar to that shown in Figure 3.5.9 and
presented again in Figure 3.6.3 below to design a broadband Schottky barrier diode
frequency doubler. In this structure, the input signal is fed antiphase to the diodes in
order to switch on one diode patch every half-cycle. The rectified output signal is
coupled to the load via a balun. As mentioned previously, the fundamental signals and
other odd harmonic signals from the diodes have opposite phase and, therefore, by
destructive interference, cancel giving good harmonic suppression. The second harmonic
signals interfere constructively, thereby, enhancing the output signal at the second
harmonic. Bitzer’s data shows that from 6 - 1 8 GHz, the conversion loss is 9.5 dB ± 1
dB and harmonic suppression > 15 dBc.
Figure 3 .6 3 Anti-parallel Balanced Diode Configuration
57
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Archer [22] develops a balanced varactor diode 85 - 116 GHz frequency doubler
similar to the typical topology shown in Figure 3.6.2. Archer uses a waveguide Tj unction as a power divider on the input to fed two varactor diodes. On the output, a
matched waveguide hybrid T-junction combines the power on the output port. Using this
design topology, a maximum conversion efficiency o f 16.5 percent was achieved.
Unfortunately, Archer does not present any data on harmonic suppression.
At high frequency applications, waveguide circuitry provides an efficient means
o f realizing frequency multipliers [2]. Waveguides provide low loss, posses desirable
high pass filter characteristics, and provide a good thermal path for dissipated power.
Energy is typically coupled/decoupled from the input and output of the waveguide
through a low-pass filter. Various authors have utilized waveguide circuitry in high
frequency multiplier designs [2,20-22,25-30]. Raisanen [26] notes that for frequencies
from 100 to about 500 GHz, for example, the highest efficiencies and highest output
powers have been achieved with waveguide multipliers. Archer [28] has developed a
varactor frequency doubler at 260 GHz utilizing waveguides and filters. The input
network consists o f a low-pass filter and a waveguide. The low-pass filter is a sevensection design which passes the fundamental signal while attenuating higher order
harmonics. The output network consists of a XJ4 impedance transformer and a
waveguide. Using this design technique, Archer achieves a conversion gain efficiency of
20 % for narrow-band applications (5 % bandwidth) and conversion efficiencies o f 10 %
for wider band applications (8 % bandwidth). Mott [25] performs a varactor frequency
doubler design at a lower frequency (1 9 -3 8 GHz) utilizing waveguides as well. Mott
has synthesized the input network with a waveguide, a XJ4 impedance transformer, and a
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low-pass filter and notes that the characteristic impedance o f the filter is synthesized such
that it equals the real part o f the diode input impedance. The output network consists of
an output waveguide impedance transformer synthesized to present the optimum load
impedance to the output o f the diode. Mott achieves a conversion efficiency o f 60 %
(conversion loss of 2.2 dB) over a 1 dB output bandwidth o f 640 MHz.
At higher frequency ranges, frequency multipliers are capable o f achieving high
conversion efficiency at low input powers, but the output power tends to saturate at rather
low power levels [20]. The use of series arrays o f diodes provides an attractive approach
to overcoming this shortfall. Cascading multiple-diode junctions increases the beak
down voltage and provides greater power handling capability [10]. A series array o f n
identical diodes can handle rf times the amount of power as a single diode [20]. For
these reasons, various authors have utilized series and parallel sacked diodes in passive
design as shown in Figures 3.5.5 and 3.5.6 to improve the power handling capability of
passive frequency multipliers [2, 10, 19-20,23-24]. Chu [23] develops an 1 8 -3 6 GHz
stacked diode frequency doubler utilizing 2 series diodes. The input and output matching
circuits consist of XJ4 impedance transformer sections with open-circuited stubs resonant
at the input and output frequencies. This design technique produced a maximum output
power o f 150 mW with a conversion efficiency of 24 % and a peak conversion efficiency
of 35 % with 95 mW of output power.
59
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3.6.2
State-of-the-art
In passive frequency multiplier development, as well as other technologies,
researchers and designers are constantly pushing the leading edge o f technology in
attempts to achieve better performance. In passive frequency multipliers, designers
desire, among other things, greater power handling capability and greater conversion gain
efficiency. This section will highlight state-of-the-art developments in passive frequency
designs.
In perusal o f the available literature, it appears that the leading edge o f technology
in passive frequency designs is not focused so much on developing new design
topologies but rather new methods o f fabricating new semiconductor diodes, particularly
for millimeter and sub-millimeter wavelength applications [14, 26,29, 31]. It has been
demonstrated that the performance o f passive frequency multipliers is highly dependent
on the pertinent properties of the nonlinear device. Therefore, it is reasonable to expect
that one o f the areas in improving the performance of passive frequency multipliers
would begin with the nonlinear device.
Over the years, the GaAs Schottky varactor diode has served as one of the most
important nonlinear elements for frequency multipliers [26,31]. Consequently, over the
past few years growing interest in novel, new diodes have brought to light new structures
which have been developed showing excellent theoretical performances comparable or
better than the conventional Schottky varactor. In comparison to the Schottky varactor,
these new diodes have potential advantages in their characteristics such as a stronger
nonlinearity or a special-symmetry, which make them very attractive for millimeter and
sub-millimeter wave frequency multiplication. Stronger nonlinearities allow more
60
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efficient higher-order harmonic generation with smaller input signal levels [26]. These
novel diodes include single barrier varactors (SBV) or quantum barrier varactors (QB V),
barrier-intrinsic-n" diodes (BIN), and high electron mobility varactors (HEMV).
The quantum well diode (QWD) has been studied since 1970 [31]. The QWD is a
heterojunction diode in which a thin undoped layer between two thin barriers form the
quantum well. Its high speed and negative differential resistance makes it attractive for
millimeter-wave oscillators. Due to its symmetric structure, the highly nonlinear anti­
symmetric / - V curves and symmetric C -V characteristics result in odd-harmonic
generation. Therefore, as expected, quantum well diodes have been utilized in tripler
designs, with some designs going up to 200 GHz. Raisanen notes that the resulting
output powers are promising from these tripler designs, but the output powers are lower
than those achieved from the best Schottky multipliers. Replacing the quantum well with
a single thicker barrier, produces a quantum barrier varactor (QBV) or a single barrier
varactor (SBV) where the nonlinear current is suppressed but the nonlinear C-V
characteristic remains. Due to the symmetric C- V characteristc, this diode is also
attractive for tripler and quintupler design. SBV triplers have been developed up to 280
GHz producing output powers o f 2.5 mW [26].
The barrier-intrinsic-n+ (BIN) diode has been proposed as an improved diode for
harmonic generation [31]. Unlike quantum well diodes or single barrier varactors which
consist o f a heterostructure and two ohmic contacts as terminals, the BIN diode is
essentially a Schottky varactor with an unique doping profile that yields a sharper C-V
characteristic than the Schottky varactor. The BIN diode consists o f a Schottky contact, a
61
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barrier layer, and an intrinsic layer. Tulmunen notes that connecting two BIN diodes
back-to-back produces a symmetric C-V characteristic.
A high electron mobility varactor (HEMV) is a modification o f the planar
Schottky varactor where a heterostructure is used. The electrons in this device have
higher mobility, as in high electron mobility transistors (HEMT) which are modeled and
used in active multiplier designs in Chapter 4, thus making it attractive for high
frequency applications. In a varactor, this structure produces a strongly nonlinear
capacitance, but, however, with a high undesirable parasitic capacitance associated with
its structure.
Tolmunen [31] has designed several multipliers utilizing the above mentioned
novel devices at 200 GHz. The conclusions from his study reveal that the sharp C-V
characteristic of the BIN diodes improves the performance at low input powers (< 10
mW) and is the most effective of all the devices. The single barrier varactor yields
excellent theoretical performance but is less efficient due to its high resistive losses but
does, however, provide the best performance at high input power levels.
As researchers and designers continue to push the envelope of technology for
higher performance devices, these novel devices will be utilized extensively. These
diodes have attributes and benefits which make them attractive in specific applications
particularly at sub-millimeter and millimeter frequencies.
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References
[1]
M. Faber, Microwave and Millimeter-Wave Diode Frequency Multipliers''
Artech House, 1995.
[2]
D. Peterson, “The varactor power frequency multiplier a device for quietly
extending the frequency range of microwave power sources,” Microwave Journal,
pp. 135-146, May 1990.
[3]
J. Gavan and A. Peled, “Low-power passive frequency doublers o f high efficiency
using varactor diodes,” International Journal o f Electronics, Vol. 68, No. 6, pp.
1011-1019, 1990.
[4]
J. Gavan and A. Peled, “Highly efficient passive frequency doublers in the L and
S bands implemented by step recovery diodes,” International Journal o f
Electronics, Vol. 63, No. 3, pp. 401-408, 1987.
[5]
J. Archer and R. Batchelor, “Multipliers and parametric devices,” in Handbook o f
Microwave and Optical Components Microwave Solid-state Components, K.
Chang, Ed., Vol. 2, pp. 142-191.
[6]
J. Scanlan, “Analysis of varactor harmonic generators,” in Advances in
Microwaves, L. Young, Ed., New York: Academic Press, Vol. 2, pp. 165-236,
1967.
[7]
H. Watson, Microwave Semiconductor Devices and Their Circuit Applications.
New York: McGraw-Hill, Chapter 8,1969.
[8]
D. Leeson and S. Weinreb, “Frequency multiplication with nonlinear capacitors-a circuit
analysis,” Proc. o f the IRE, pp. 2076-2084, December 1959.
[9]
D. Roulston and A. Boothroyd, “A large-signal analysis and design approach for
frequency multipliers using varactor diodes,” IEEE Trans, on Circuit Theory, pp. 194205, June 1965.
[10]
P. Staecker, “mm-Wave transmitters using power frequency multipliers,”
Microwave Journal, pp. 175-181, February 1988.
[11]
P. Jounet and M. Fourrier, “20-40 GHz broadband frequency doubler with
gallium arsenide varactor,” Rev. Sci. Instrum., 49(1), pp. 124-125, January 1978.
[12]
S. Nilsen et al., “Single barrier varactors for submillimeter wave power
generation,” IEEE Transactions on Microwave Theory and Technique, Vol. 41,
No. 4, pp. 572-579, April 1993.
63
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[13]
S. Chen et al., “Rigorous design of a 94 GHz MMIC doubler,” IEEE Microwave
and Millimeter-Wave Monolithic Circuits Symposium, pp. 89-92, 1993.
[14]
S. Chen et al., “A high-performance 94 GHz MMIC doubler,” IEEE Microwave
and Guided Wave Letters, Vol. 3, No. 6, pp. 167-169, June 1993.
[15]
J. Archer, “A novel quasi-optical frequency multiplier deign for millimeter and
submillimeter wavelengths, ” IEEE Transactions on Microwave Theory and
Technique, Vol. 32, No. 4, pp. 421-426, April 1984.
[16]
T. Takada et al., “Hybrid integrated frequency doublers and triplers to 300 to 450
GHz,” IEEE Transactions on Microwave Theory and Technique, Vol. MTT-28.
No. 9, pp. 966-973, September 1980.
[17]
R. Hess, “Low-power MIC diode doubler,” MSN & CT, pp. 58-67, December
1987.
[18]
K. Chang et al., “W-band (75-110 GHz) microstrip components,” IEEE
Transactions on Microwave Theory and Technique, Vol. MTT-33, No. 12, pp.
1375-1380, December 1985.
[19]
R. Bitzer, “Planar broadband MIC balanced frequency doublers,” IEEE
Microwave Theory and Techniques Symposium, pp. 273-276, 1991.
[20]
B. Rizzi et al., “A high-power millimeter-wave frequency doubler using a planar
diode array,” IEEE Microwave and Guided Wave Letters, Vol. 3, No. 6, pp. 188190, June 1993.
[21]
N. Erickson, “High efficiency submillimeter frequency multipliers,” IEEE
Microwave Theory and Techniques Symposium, pp. 1301-1304, 1990.
[22]
J. Archer, High-output, single- and dual-diode, millimeter-wave frequency
doublers,” IEEE Transactions on Microwave Theory and Technique, Vol. MTT33, No. 6, pp. 533-538, June 1985.
[23]
A. Chu, “Monolithic analog phase shifters and frequency multipliers for mmwave phased array application,” Microwave Journal, pp. 105-119, December
1986.
[24]
J. Cushman et al., “High power epitaxially-stacked varactor diode multipliers:
performance and application at W-band,” IEEE Microwave Theory and
Techniques Symposium, pp. 923-926, 1990.
64
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[25]
R. Mott, “High performance frequency doublers for the COMSTAR beacon."
Comsat Technical Review. Vol. 7, No. 2, pp. 555-576, Fall 1977.
[26]
A. Raisanen, “Frequency multipliers for millimeter and submillimeter
wavelengths,” Proceedings o f the IEEE, Vol. 80, No. 11, pp. 1842-1852,
November 1992.
[27]
P. Staecker and R. Chick, “ 10 to 40 GHz doubler-doubler chain for satcom
applications,” Microwave Journal, pp. 87-108, December 1985.
[28]
J. Archer, “Millimeter wavelength frequency multipliers,” IEEE Transactions on
Microwave Theory and Technique, Vol. MTT-29, No. 6, pp. 552-557, June 1981.
[29]
D. Choudhury et al., “A 200 GHz tripler using a single barrier varactor,” IEEE
Transactions on Microwave Theory and Technique, Vol. MTT-41, No. 4, pp. 595599, April 1993.
[30]
J. Archer, “An efficient 200-290 GHz frequency tripler incorporating a novel
stripline stucture,” IEEE Transactions on Microwave Theory and Technique, Vol.
MTT-32, No. 4, pp. 416-420, April 1984.
[31]
T. Tolmunen, “Theoretical performance of novel multipliers at millimeter and
submillimeter wavelengths,” International Journal o f Infrared and Millimeter
Waves, Vol. 12, No. 10, pp. 1111-1133, 1991.
[32]
E. Carman, “V-band and W-band broadband, monolithic distributed frequency
multipliers,” IEEE Microwave Theory and Techniques Symposium, pp. 819-822,
1992.
[33]
R. Pantell, “General power relationships for positive and negative nonlinear
resistive elements,” Proceedings o f the IRE, pp. 1910-1913, December 1958.
[34]
J. Manley and H. Rowe, “Some general properties of nonlinear elements- Part I.
General energy relations,” Proceedings o f the IRE, pp. 904-913, July 1956.
[35]
P. Penfield and R. Rafuse, Varactor Applications, Cambridge, Ma.: MIT Press,
1962.
[36]
C. Page, “Frequency conversion with positive nonlinear resistors, ” J. Res. Nat.
Bur. Std., Vol. 56, pp. 179-182, April 1956.
[37]
R. Muller and T. Kamins, Device Electronics for Integrated Circuits, Second
Edition, New York: John Wiley & Sons, 1986.
[38]
B. Diamond, “Idler circuits in varactor frequency multipliers,” IEEE Trans.
Circuit Theory, pp. 35-44, March 1963.
65
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[39]
S. Maas, Nonlinear Microwave Circuits, Norwood, Massachusetts: Artech House.
Inc., 1988.
66
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Chapter 4
Active Frequency Multipliers
4.1
Introduction
Another class of frequency multipliers encompasses those which are designed and
constructed utilizing active nonlinear devices. As previously discussed multipliers require
a nonlinear element for harmonic production. Active frequency multipliers, as
demonstrated in the block diagram below in Figure 4.1.1, utilize the nonlinear
characteristics o f an active element to produce an output spectrum rich in harmonics
when excited by a sinusoidal source. Typically, the active element consists o f any of the
transistor classes which include BJT, HBT, FET, MESFET, HEMT, PHEMT, etc. Active
multipliers offer various advantages over passive multipliers. As an example which will
be discussed in the following section, one o f the performance descriptions of the
frequency multiplier where active multipliers has a distinct advantage over passive
multipliers is in the conversion gain. Active multipliers are capable o f producing
conversion gains greater than 0 dB whereas passive multipliers are not capable of
achieving this performance. This chapter will also discuss the development of active
frequency multiplier technology including the fundamental performance descriptions,
pertinent properties o f the active device which include modeling and quantification o f the
nonlinear properties, analysis techniques used in the simulation o f nonlinear microwave
circuits, and design techniques of active frequency multipliers.
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R<
■Wrf
©
Input
Network
Active
Nonlinear
Device
Output
Network
-Rl
Figure 4.1.1 Block Diagram of Active Frequency Multiplier
In perusal of the available literature numerous authors have presented various
discussions on active frequency multipliers which are referenced throughout this chapter.
In the development of active frequency multipliers, one o f the primary concerns is the
capability to accurately predict the linear and nonlinear performance o f the active device
before embedding the device into other networks, which is typical in the development
and design o f frequency multipliers. Several authors [1-39] have presented details and
techniques for modeling the active devices. Each author delineates the various
advantages and disadvantage of their study. In section 4.3.1, techniques for modeling
HEMT’s and PHEMT’s are presented as they are used to investigate and study the
nonlinear characteristics of the devices and are also employed in developing and
designing frequency multipliers which are shown in the later sections o f the chapter.
The performance characteristics o f active frequency multipliers are governed by,
amongst other things, the characteristics o f the active device utilized in the design and the
design technique employed in the development stage. Numerous design techniques have
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been employed in the realization of active frequency multipliers as shown throughout the
literature. Several authors [44-87] have shown various advantages and disadvantages of
their designs. Other authors have combined their research efforts to discuss design
techniques along with modeling simultaneously. Presenting measured and modeled data
simultaneously strengthens the study and the results. Similar to this approach, section 4.5
details the design techniques utilized in this dissertation along with accompanying
modeled data to strengthen the study and conclusions.
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4.2
F u ndam ental P erform ance Descriptions
As discussed previously, frequency multipliers are nonlinear circuits that convert
signals at an input fundamental frequency (f0) into signals at a harmonic frequency
multiple o f the input frequency (nf0). Several performance descriptions and parameters
demonstrate the effectiveness o f frequency multipliers at frequency conversion. The
objective o f this section is to identify and discuss the prominent fundamental
performance descriptions o f active frequency multipliers.
Active frequency multipliers utilize the nonlinear characteristics possessed by any
o f the several transistor classes such as BJT, FET, etc. Exciting the nonlinear device by a
fundamental frequency provides an output spectrum rich in frequency harmonics. One of
the main advantages o f active multipliers is their capability of producing positive
conversion gains (conversion gains greater than 0 dB). The conversion gain o f a
frequency multiplier is defined as the ratio of the harmonic output power expressed for a
particular harmonic delivered to the load to the fundamental input power. Maximizing
the conversion gain is crucial in the development and design of frequency multipliers. In
the specific case of frequency doublers, an input signal at the fundamental frequency (f0)
is converted into a signal at the second harmonic (2 f,). Mathematically, the conversion
gain can be expressed as [40]:
Conversion Gain =
(4.2.1)
PJJo)
Or
Conversion Gain{dB) = Poul2/o(dBm) - Pin/o(dBm)
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(4.2.2)
Frequency doublers, which will be presented in section 4.5, have been designed and
developed in this dissertation exhibiting conversion gains approaching 9 dB. Alternately,
the conversion gain can be expressed as a percentage [41]. This percentage is defined as
the ratio of the input power at the fundamental to the output power delivered to the load
at the desired harmonic. Using the example for the frequency doubler, this can be
represented as:
tj
(%) =
Pm(f0)
x
i
oo%
(4.2.3)
Pout(2 fo )
Similarly, as in the consideration o f RF amplifiers, the effectiveness o f the
conversion of DC power into AC power is also a meaningful parameter in discussing
frequency multipliers. In the case o f frequency doublers, the consideration is focused on
the effectiveness o f converting DC power into ac power at the second harmonic. A
general expression for the DC-to-RF efficiency can be represented as [41 ]:
DC - to - R F (%) = ^ Pout(h^ monic) ^jx j 00o/o
(4.2.4)
From this equation, it is observed that optimum DC-to-RF efficiency performance is
achieved when maximum RF power is produced from a minimum quantity o f DC power.
For the class of frequency multipliers presented in section 4.5, DC-to-RF efficiencies of
up to 24% have been obtained.
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The transfer o f power between the fundamental frequency at the generator to the
desired harmonic at the load is dependent, amongst other things, upon the return loss or
VSWR o f the input port and the output port o f the multiplier circuitry. The return loss is
a measure of the impedance match of each o f the ports (input and output) of the
frequency multiplier to the source impedance and the load impedance. For the case of the
frequency doubler, it is desired that maximum power is transfened from the RF source
into the multiplier at the fundamental frequency and that maximum power is transferred
from the multiplier to the load at the second harmonic frequency. Mismatches between
the impedance of the generator and input impedance o f the multiplier will cause some of
the RF power to be reflected back into the generator which reduces the efficiency of the
multiplier. Likewise, mismatches between the output impedance o f the multiplier and the
load impedance produce similar effects. Therefore, good impedance matches are desired
for optimum multiplier designs at the appropriate harmonics. Computer simulations are
performed for HEMT frequency doublers in section 4.3.5 (Tables 4.11 and 4.12)
delineating the advantages o f good impedance matching. In these simulations significant
improvements in the conversion gain are achieved in the cases where the input and output
ports are impedance matched.
As previously discussed, frequency multipliers are harmonic generators which
produce an output harmonic (nfa) when excited by a fundamental frequency if0). In the
generation of the desired harmonic of interest other undesirable harmonics are generated
as well. As an example, in the case of a frequency doubler, the desired output harmonic
is 2f0 but other undesired harmonics at fo, 3fo, 4fa., etc. are generated as well. The ability
o f the multiplier to suppress the undesired harmonics is another key performance
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description o f the multiplier. This capability of the frequency multiplier is defined as
harmonic suppression. Harmonic suppression is defined mathematically as:
Suppression(nfo]{dBc) = Po(nfo){dBm)- Po{ni/o](dBm)
(4.2.5)
where nfo is the desired frequency harmonic and mfo represents the undesired harmonics.
In the case of the frequency doubler, n=2 and m=l, 3, 4, etc. which indicates that the
desired harmonic is 2fa and harmonic suppression is calculated for the fundamental
frequency (f0), third harmonic frequency (3fa), etc.
An application of frequency multipliers previously discussed in section 2.1 is use
in communication systems in receivers and transmitters. A performance description of
receivers in communication systems and, therefore, frequency multipliers used in
receivers, is indicated by its dynamic range. Dynamic range is the range o f input or
output power levels where signals can be processed with high quality without signal
distortion. At low power levels, the dynamic range is limited by the sensitivity to the
noise floor or the minimum detectable signal as governed by the noise floor. At higher
powers, the dynamic range is limited by the acceptable level of signal distortion or, in
general, by the power level where small-signal gain has been compressed by 1 dB
[42,43],
Using these definitions for dynamic range, optimum dynamic range for frequency
multipliers is achieved when the power range between the noise floor and signal
distortion is maximized and involves tradeoffs between the input signal drive level, tne
noise floor level, and the output signal distortion.
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Another important performance description o f frequency multipliers is the
operational bandwidth. Bandwidth is defined as the frequency band where specific
performance specifications are met and. typically, this performance description is
identified by the conversion gain. Specifying a -3 dB bandwidth indicates the frequency
band where the conversion gain decreases by 3 dB from its peak. Optimizing multiplier
bandwidth is an important task to the designer. Typically, tradeoffs have to be made in
the performance o f the devices to achieve high bandwidths. As an example, higher
conversion gains are achieved for narrow bandwidth designs and usually wide bandwidth
designs are accomplished at the expense of the conversion gain as the conversion gain is
reduced. A reason for this is due to impedance matching. As mention previously,
impedance matching at the input and output o f the multiplier improves the performance
o f the multiplier. Over a wide band o f frequencies, it is difficult to achieve a good
impedance match over the entire band. Subsequently, the conversion gain is reduced
over the band to compensate for the extended bandwidth. Over narrow frequency bands
impedance matching is less of a challenge and, thus, readily provides opportunities for
optimum conversion gains.
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43
P ertinent P roperties o f the Active Device
43.1
4.3.1.1
Nonlinear modeling
Introduction
The existence of accurate device models are crucial to circuit designers and
researchers. The ability of the designer to accurately predict the performance of a device
and circuit verifies the design process, strengthens the overall design, and provides
valuable information on the operation of the device. This information provides insight on
the contributions of the intrinsic parameters on the operation o f the device.
Performance predictions o f the device are obtained from mathematical
expressions describing the operation o f the device. Typically, computer simulations are
used for these computations. After the development of the device model, external
circuitry can be added to the device and, with confidence, predictable results can be
obtained. This capability enhances the success of the designer considerably.
Device models are typically categorized by their application. Device models used
to predict linear, low-power applications usually through the use o f S-parameters are
categorized as small-signal or linear models. Models used for the prediction of non­
linear applications, frequency harmonics, or high-power applications are classified as
large-signal or non-linear models.
4.3.1.2
Classification o f device models
As previously mentioned, models are developed and categorized according to
their application and depending upon the particular application, a specific model is
employed. As an example, a circuit designer interested in linear, small-signal designs
could use the simpler, small-signal model without the requirement of developing the
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large-signal model. Typically for small-signal models. S-parameters are measured at
various bias points and, if required, at various frequencies. From the S-parameter data,
the intrinsic elements o f the device are extracted and combined with the extrinsic
parasitic elements to form the complete, equivalent circuit model [1], Alternately,
through the use of an optimization technique, the mathematical expressions describing
the operation o f the device model can be fitted to the measured data such that the
mathematical expressions agree with and accurately predict the measured data.
Typically, non-linear models present additional challenges to their development
than the linear models. Non-linear models are required to predict the linear and non­
linear performance o f the device. This non-linear prediction includes the ac performance
of the various frequency harmonics. The development of the non-linear model begins
with dc parameters (drain-to-source current (/<&), transconductance (gm), and output
conductance (gds))- Using the mathematical expressions for these parameters, the
measured data is used to determine all the parameters included in the mathematical
expression. Once the dc model parameters are determined and accurately predict the dc
performance o f the devices, the ac performance o f the device is considered. This can be
achieved by measuring the output power of the device versus the input power for various
bias points at the fundamental and higher harmonic frequencies. Using the intrinsic ac
parameters of the device model, the measured data is fitted with the modeled data by
tuning the ac parameters governing the model. The ac parameters are typically the
intrinsic capacitors, which are typically nonlinear functions o f applied bias voltage, and
inductors of the device along with the parasitic elements o f the device and packaging.
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This process will be revisited in much greater detail in the development of a PHEMT
transistor non-linear model in section 4.3.1.3.4.
4.3.1.3
Development o f precision models
4.3.1.3.1
Application o f models
As previously mentioned, the main focus of this research work is on the
development of active frequency multipliers. Frequency multipliers are non-linear
devices requiring accurate modeling capability for the fundamental and higher harmonic
frequencies. These requirements dictate the necessity o f an accurate non-linear transistor
model. The present research undertaken employs the use o f HEMT (Fujitsu FHX35LG)
and PHEMT (HP/Avantek ATF-36163) transistors requiring accurate HEMT and
PHEMT non-linear models. The frequency multipliers developed in this research project
are frequency doublers and thus, the highest frequency harmonic, which will be modeled,
is the third harmonic frequency.
4.3.1.3.2
Existing FET models
Various authors [1-12] have developed and discussed several empirical non-linear
FET models. Differences in these models reside in the way that the drain-to-source
current and the intrinsic capacitors are modeled [2]. These differences account for their
varying degrees o f accuracy observed among the models. Measuring the performance o f
the transistor and fitting this data to mathematical equations as previously mentioned
provides a mean for developing empirical models. Embedded in the mathematical
equations are various parameters, which can be varied to alter the resulting solution of the
77
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mathematical equations. Optimization techniques are commonly employed and.
consequently, provide great accuracy between the measured and modeled (mathematical
equations) results. This area will be discussed in greater detail in the following sections.
Physical models have been developed to predict device behavior from the solidstate physics o f the device. Some of these process parameters include doping levels,
sheet resitivity, die size. etc. The development o f accurate physical models for GaAs
transistors for use in circuit simulators is not wide spread due to the complexity and
difficulty in developing these models. For great accuracy, these models require solutions
to the 3-dimensional Poisson’s and transport equations. Solutions to these equations are
not trivial. Additionally, defects in the semiconductor structure, surface effects, and
trapping states are not well modeled for use in circuit simulators.
A general non-linear FET model is shown below in Figure 4.3.1. In this model,
the non-linear parameters include [2]:
Dgs = gate-to-source diode
Dgd = gate-to-drain diode
Cgs = gate-to-source capacitance
Cgd = gate-to-drain capacitance
Cds= drain-to-source capacitance
Ids= drain-to-source current
Rds = output resistance
gm = transconductance (not shown in model but is represented by the equation:
gm = 5Ids/SVgs )
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Gate
• — J11
Drain
Source
Figure 43.1 Non-Linear Device Equivalent Circuit Model
The drain-to-source current of a FET transistor is dependent on Vgs and V& as
shown by the equivalent circuit model in Figure 4.3.1. The drain-to-source current o f the
transistor exhibits nonlinear characteristics. As a demonstration o f these nonlinear effects,
Figure 4.3.2 shows typical measured I-V curves o f a FET transistor. In this figure V* is
increased in steps starting at the pinch-off voltage (Vp=Vgsx -0 .5 volts) leading to a
complete family o f curves. A requirement o f the nonlinear model is the ability to
accurately predict the family o f curves shown in Figure 4.3.2.
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0.025 Vgs=0 v
Saturation
Region
Vgs=M). I v
OhmiC^
Region
Vgs=-0.2 v
Vgs=-0.3 v
Region
'd s(sat)
Vgs=-0.4 v
Vgs=-0.5 v
0
0.5
1.5
2
25
3
Vds (V)
Figure
Typical I-V Curves of FET Transistor
The operation of the FET is characterized by examining the regions o f the I-V
curves as demonstrated in Figure 4.3.2 [3]. The principal regions shown are the cutoff,
saturation, and ohmic (linear) regions. In the ohmic region, a small
value is applied to
the FET and the device behaves as a linear voltage-variable resistor. In Figure 4.3.2 this
linear resistor region is approximated by the dashed curve ( Vds(sat)) where in the ideal
case, this is where the /«*-P* curves become flat. Long and Butner [3] note that a square
law drain-to-source current expression incorporating the gate-to-source voltage fits the
measured I-V characteristics o f the FET quite well in the ohmic region as demonstrated
by equation 4.3.1a below.
(4.3.1a)
*
+
delineated by dashed curve
for this device,
< 0 2 volts
80
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where fi will be discussed below
As V& is increased beyond
as shown in Figure 4.3.2, and enters the saturation
region, the drain current flattens and theoretically remains relatively constant with further
increases in V&. The saturation factor
as shown below in equation 4.3.1b
empirically accounts for the increase of the drain current as V& increases in the actual
measured device response.
(4.3.1b)
where X will be discussed below
A hyperbolic tangent function provides an empirical means for representing the drain-tosource current at the knee of the I-V characteristics (where V^Vais{ial^). As V& increases
above Vds(sa) the hyperbolic tangent function approaches unity when the argument
becomes large. These topics will be revisited in the following sections.
a)
Curtice circuit model
Curtice [4,5] presents an analytical model for the GaAs MESFET for use in
circuit simulation programs. The model developed by Curtice, however, has limitations
as will be discussed below. This general model consists of Ids, Cgs, Cgd, C*, and Dgs in
the dc analysis but Curtice uses Ids and Cgs as the only non-linear elements contributing
to the nonlinear effect neglecting the gate-to-drain capacitance (Cge/) and the gate-to-drain
81
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diode ( D gd ) in the nonlinear analysis. The drain-to-source current (Id s) is given by Curtice
as:
I*
+
(4.3.1c)
where J3, Vto, A and a are model parameters which will be described below. A basis for
the development of the expressions in this equation for the various regions (linear and
saturation regions) of operation was mentioned in the preceding section. In equation
4.3.1c, the device parameter P represents the transconductance parameter with units of
amperes per square volts and for GaAs FETs scales directly with the channel width of the
FET [3]. Typical values for /? are from 1CT6 to 2 x 10° A /V 2. Vp (V,J is the pinch-off
voltage and represents the gate-to-source voltage where the FET begins to become active.
The FET is off when operated with V * < V p (V t0). Typical values for Vp range from -2.0
to -0.5 V for depletion mode and 0.1 to 0.3 V for enhancement mode devices. A
represents the channel-length modulation parameter and has units of V 1. The factor
(l + AV *) in equations 4.3.1b and 4.3.1c is used to empirically model the slope o f the
increasing drain current in the saturation region as the drain-to-source voltage increases.
Typical values for A are between 0.01 to 0.2 V~l for most MESFETs with gate lengths in
the 0.8 to 2.5-micrometer range [3]. The saturation voltage parameter,
or,
affects the
slope of the drain current in the linear region and the saturation voltage
as observed
in Figure 4.3.2. The saturation voltage parameter improves the empirical modeling of the
drain-to-source current at the transition between the linear and saturation regions [3].
82
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A drawback o f the Curtice model lies in the square-law approximation used in the
drain-to-source current expression. This square-law approximation is valid for small Vgs~
Vto values. As larger values o f Vgs-Vto are encountered the accuracy of the drain-to-source
current expression decreases [2]. Long and Burner [3*] demonstrate that the fit between
typical measured and modeled /<&values using this model can be in error by as much as
300 m V o iV js 'vn the linear region using this square-law approximation. Another
drawback o f this model (Curtice) lies in the modeling of the intrinsic capacitors, Cgs and
Cgd. The expressions for these values are given as:
(4.3.2)
C
(
=
- C
'-gdo 11
\
(4.3.3)
where Vbi = built-in voltage potential
Vapp = intrinsic gate-to-source or gate-to-drain voltage
Cgso = zero-bias gate-to-source capacitance
Cgdo = zero-bias gate-to-drain capacitance
Golio states that these simple junction capacitance expressions fail to predict accurate
capacitance values for low drain-to-source voltages.
Reference 3, pages 89-96.
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In the development of the Curtice model, the derivatives o f the drain current
dl
dl
( — —,——) have been neglected. In order to accurately model /<&, these derivatives
dV„ d V j
should be considered. As will be seen in models presented in later sections, greater
success in predicting the dc performance of the nonlinear models is achieved when the
derivatives of the drain current are taken into consideration.
b)
Kacprzak-Materka circuit model
Kacprzak and Materka [6,7] developed a non-linear model to accurately predict
the current-voltage characteristic using a modified hyperbolic tangent function different
from that used by Curtice. They have introduced a global equation for the pinch-off
voltage (Vp) which models Vp as a function of the drain-to-source voltage (V&). This
pinch-off equation is represented as:
V '- V '.+ i V *
(4.3.4)
where Vpo = pinch-off potential of ideal square-law transistor
y
= empirical constant
Using this modification the drain-to-source current is represented as:
I< h
~
1
I d ss
.
E- tanh
v, j
lK
aK
84
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(4.3.5)
where /<&, is the saturation current at zero gate-to-source voltage. This model uses the
same gate-to-source and gate-to-drain capacitor expressions as the Curtice model and
therefore poses similar limitations. In the complete nonlinear development o f this model,
the gate-to-drain capacitance (Cgd) is neglected in the non-linear analysis.
c)
Statz-Raytheon circuit model
The Statz(Raytheon) model was developed to improve on the limitations o f some
o f the previous models [8]. As mentioned, one o f the limitations of the Curtice model is
that it is primarily valid for small VwrVp values and for larger values the accuracy
decreases [2]. Long and Butner state that improvements can be obtained by modifying
the saturation current level to reflect velocity-saturation effects. In an attempt to correct
this, the Statz model modifies the original square-law equation o f the drain-to-source
current expression in equation (4.3.1c) to improve the accuracy by adding a Vgs term in
the denominator (l +^(Vgs - Vp))- The authors of the Statz model indicate that the
hyperbolic tangent function in the drain-to-source current expression consumes large
amounts o f computer time. To overcome this, they have chosen to express the hyperbolic
function as a truncated series that allows the complete drain-to-source current equation to
be written as:
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'
aV ^3
1- 1 -
(4.3.6)
o •*•-» *)
for 0<V(js <3/a, and
p(v„-vaf .
,
U = -^-F— ^ 0 +
(4.3.7)
)
for Vfc > 3/a
where the parameters Vp, (3, and X are the same as those in the Curtice model. The
parameter b (in units o f V 1) is the doping tail extending parameter modeling the
velocity-saturation effects of the transistor [3]. The magnitude o f b is varied to
reflect the velocity-saturation effects of transistors. The junction capacitance
expression used in the Curtice model does not accurately predict the capacitance
for low drain-to-source voltages. The Statz model provides capacitance
expressions modeling all drain-to-source voltage regions correcting the limitations
of the capacitance expressions of the Curtice model [2]. The Statz capacitance
equations are given as [2]:
((
)
\
(4.3.8)
l b ...
'
f
z
\
)
86
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(r
1
(4.3.9)
C „K > K X
\v
where
r n i x = 0.5
6
0.2
=
1
K, = - 1 +
a:
3
(4.3.10)
(4.3.11)
- l 1+
2
2
1-
K
- O
(4.3.12)
87
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(4.3.13)
K
r .+ V n + iK - r n ,) 1 *
2
^
(4.3.14)
(4.3.15)
where
and Vgd are intrinsic device voltages, the adjustable model parameters
are Cgso and CgdQ, and a is determined by considerations o f equations 4.3.6 and
4.3.7.
In most circuit simulators, the bias dependent equivalent circuit parameters
describing the I-V curves and other device characteristics (such as gm, g , etc.) are
produced by the circuit simulator by one o f two basic methods: a) curve-fit methods,
representing the models represented and discussed thus far where the device
characteristics are computed from analytical expressions, and b) table-based models. [9],
d)
Table-based circuit models
The objective of table-based models is to accurately predict the performance of
transistors by interpolating the device characteristics from a table of measurements [9],
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As an example, in a curve-fit model, the drain-to-source current is computed from the
analytical /<&equation but in a table-based model the drain-to-source current is
interpolated from a table o f measurements where the drain-to-source current has been
measured at a considerable number of bias voltages. An advantage of the table-based
model is that the small-signal S-parameters are accurately predicted at any bias because
the equivalent circuit parameters can be interpolated at any bias point. In the case o f
some curve-fit models, accuracy can be lost due to the fitted drain-to-source currents not
predicting the corresponding transconductances or output resistances well at some bias
conditions.
Another major concern of curve-fit models is whether the analytical expressions
accurately predict higher order derivatives of capacitances and conductances with respect
to the gate and drain voltage that is required for intermodulation distortion and harmonic
predictions. In principle, this issue is alleviated with table-based models because a
sufficiently large number o f data is used in establishing the data look-up table. In
practice, however, the table-based model can experience limitations if a suffice amount of
data points are not taken in establishing the data table.
A disadvantage o f table-based models is that they require that the device
characteristics be supplied to the circuit simulator in a look-up table and for improved
accuracy, a sufficiently large number o f data points are needed. This requirement
increases the amount o f memory and disc space needed for accurate implementation of
this model. Anholt states that this can be a significant problem in designing for yield
where device data is required for hundreds o f different devices [9]. Another disadvantage
o f this model occurs when noise resides in the measured data. Anholt notes that noise in
89
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the measured data causes the interpolated results to posses wild variations in the circuit
parameter quantities and in the derivatives between the data points.
Table-based device models have shown great success in circuit simulators and
have been used throughout the microwave community. The Root model is a table-based
model that is embedded into the HP-EEsof commercial simulator (Microwave Design
System (MDS)) [9,13-15]. Hewlett-Packard’s Libra circuit simulator uses a B-Spline
model which is also a table-based circuit model.
Several authors have developed other FET models recently [16-18]. Shirakawa
[16] has developed a small-signal HEMT model using S-parameters to analytically
determine the intrinsic parameters o f the equivalent small-signal circuit model with great
success. Morton [17] has developed a physical HEMT model capable o f predicting DC,
small-signal, and large-signal performance. This model relates manufacturing process
variations to the electrical performance o f devices. Tanimoto [18] has developed an
analytical nonlinear model based on the Curtice model. The author states that average
errors of 2.6% for dc current and S-parameter errors o f less than 20% for the linear region
and 10% for the saturated region has been achieved.
90
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4.3.1.3.3
HEMT Modeling
As previously mentioned an accurate non-linear model for the Fujitsu FHX35LG
HEMT transistor is required for the frequency multiplier analysis. Determining that a
non-linear model o f this device resides in the device library of the Libra simulation
package presents a convenient solution to this requirement. The manufacturer developed
this model and, thus, ideally, no additional modeling had to be undertaken for this device.
This solution simplifies the designer’s task considerably but does possess one significant
drawback. The modeling software of this transistor does not allow the user to physically
alter the modeling equations in any form. The designer does not have the flexibility of
tweaking any o f the equations, if required, for the model to be used in any
nonconventional means such as studying the nonlinear contributions o f the intrinsic
parameters independently.
Typical measured DC results for the Fujitsu FHX35LG HEMT transistor are
shown below in Figures 4.3.3 - 4.3.8. The DC data was obtained using the HP 4155A
Semiconductor Parameter Analyzer utilizing the block diagram shown in Figure A. 1 in
Appendix A. Due to possible oscillations, careful attention has to be given to the
termination ports of the bias tees used in the measurements. As shown in the previous
mentioned block diagram, fifty ohm terminations are required in the test setup and using
this setup, a family o f curves representing the drain current versus the drain-to-source and
gate-to-source voltages are generated as shown in Figures 4.3.3 and 4.3.4.
91
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o
0.5
1
1.5
2
2.5
3
Vds (V)
Figure 4 3 3 Typical Measured Drain Current of HEMT Transistor versus Drain-toSource Voltage
35 V ds=3 V
V d s-2 .4 V
V d s-2 V
V d s-1 V
10
-
0.6
-0.5
-0.4
-0.3
-
0.2
-
0.1
-
0
Vgs (V)
Figure 43.4 Typical Measured Drain Current of HEMT Transistor versus Gate-toSource Voltage
Reproduced with permission o f the copyright owner. Further reproduction prohibited without permission.
80
70
60
50
-------------V g s-0 V
<
------------ Vgs—-0.2 V
E 40
E 30
..................V gs=-0.4 V
------------ Vgs=-0 6 V
20
10
0
0
0.5
2
1.5
2.5
3
Vds (V)
Figure 4 3 .5 Typical Measured Transconductance of HEMT Transistor versus
Drain-to-Source Voltage
80
£<
_E
E
at
V d s -3 V
V d s-2 V
V ds-1 V
-
0.6
-0.5
-0.4
-0.3
-
0.2
-
0.1
0
Vgs (V)
Figure 43.6 Typical Measured Transconductance of HEMT Transistor versus Gateto-Source Voltage
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80
70 60
-
Vgs~Ov
gd (m S)
50
40
30
20
0
0
0.5
2
1.5
2.5
3
Vds (v)
Figure 43.7 Typical Meaured Output Conductance of HEMT Transistor versus
Drain-to-Source Voltage
20
V d s-0.6v
Vds* 3 v
-
0.6
-0.5
-0.4
-0.3
-
0.2
-
0.1
0
Vgs(v)
Figure 43.8 Typical Measured Output Conductance o f HEMT Transistor versus
Gate-to-Source Voltage
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As previously mentioned the nonlinear model for the FHX35LG HEMT transistor
resides in the device library o f the Libra simulator. As an initial analysis, the measured
dc performance of the HEMT is evaluated against the results of this model. Figures 4.3.9
- 4.3.11 show the drain current, transconductance, and output conductance versus drainto-source voltage for the transistor with measured and modeled data presented. These
figures demonstrate wide discrepancies between the measured and simulated data. Figure
4.3.8 shows that difference between measured and simulated drain current is on the order
o f 30% for higher gate-to-source voltages and up to 50% for lower gate-to-source
voltages. The error between the measured and simulated transconductance is on the order
of 25% for higher gate-to-source voltages and up to 40% for lower gate-to-source
voltages while the output conductance shows discrepancies on the order o f 25%.
50
. . . . . - V gs= 0 v (M easured)
-------------- V gs=0 v (Sim ulated)
- - •O- - -V g s—02 v (M easured)
O
V gs=-0.2 v (Sim ulated)
-V gs = -0 4 v (M easured)
A ------V gs= -0 4 v (Sim ulated)
- - -X- - -V gs =-0 6 v (M easured)
X ------V gs=-0 6 v (S im ulated)
FT0.5
1
1.5
2.5
Vds (v)
Figure 4.3.9 Measured and Modeled Drain Current of HEMT Transistor versus
Drain-to-Source Voltage Using Model Residing in Device Library
95
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90 80
<
70
------------- V gs=0 v (M easured)
60
. . . . . -V g s= 0 v (Sim ulated)
— A— Vgs=M).2 v (M easured)
50
* - -A- - ~Vgs=-0.2 v (S im ulated)
E.
40
E
at
X
V gs=-0 4 v (M easured)
- - -X- - -Vgs=M).4 v (S im ulated)
30
20
. -X '
10
0
0
0.5
2
1.5
3
2.5
Vds (v)
Figure 43.10 Measured and Modeled Transconductance of HEMT Transistor
versus Drain-to-Source Voltage Using Model Residing in Device Library
. . . . . - V g s-o v (Sim ulated)
-------------V g s-0 v (M easured)
- - -O* - -V gs“ -0.2 v (Sim ulated)
O
u 50 -
V gs=-0.2 v (M easured)
- - A - - -V gs“ -0.4 v (Sim ulated)
A
V gs=-0.4 v (M easured)
- - X - - -V gs«^).6 v (Simulated)
X
Vgs” -0 .6 v (M easured)
l.5
2.5
Vds (v)
Figure 43.11 Measured and Modeled Output Conductance of HEMT Transistor
versus Drain-to-Source Voltage Using Model Residing in Device Library
96
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As demonstrated by the preceding plots, the simulated data does not match the
measured data accurately. This nonlinear model residing in the device library does not
permit alterations to the modeling equations to improve the fitting between the measured
and modeled data. A means of overcoming this limitation is through the use of a small
offset voltage in the simulations. In this model, it was determined that the fit between the
measured and modeled I-V curves is improved with an offset voltage o f 25 mV used for
the gate-to-source voltage (Vgs). In other words, for each measured I-V curve the
corresponding simulated curve is obtained with the gate-to-source voltage offset by 25
mV (Vgs-0.025). Employing this scheme, the measured and modeled dc data for the
drain-to-source current (/<&), transconductance (gm), and output conductance (gds) is
shown below in Figures 4.3.12 —4.3.16. The ac performance o f this model is shown in
Figures 4.3.17 - 4.3.19. The measured and modeled output power versus the input power
for the fundamental, second, and third harmonic frequencies and the measured and
modeled output power versus the fundamental frequency are shown for the FHX35LG
device. The IV curves of Figure 4.3.12 show good agreement between the measured and
modeled data. Great accuracy is obtained for Vds values up to 2 volts for all Vgs values.
For Vds voltages above 2 volts, the fit is not as good for the higher values of gate-tosource voltages. Figures 4.3.13 - 4.3.16, however, show that accurate agreement
between the measured and modeled transconductance (gm) and output conductance (gjs)
for this model is difficult to obtain, particularly for larger gate-to-source and drain-tosource voltages. The transconductance and output conductance plotted versus Vds
(Figures 4.3.13 and 4.3.16) show varying degrees of accuracy. For high values of Vgs the
transconductance shows the greatest error. As Vgs is decreased the accuracy improves
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significantly, particularly for V* less that 2 volts. The output conductance (Figure
4.3.16), on the other hand, shows good agreement over all voltage ranges. The
transconductance and output conductance plotted versus Vgs (Figures 4.3.14 and 4.3.15)
show inaccuracies between the measured and modeled data. A means of improving the
accuracy of Figures 4.3.14 and 4.3.15 could possibly be achieved by using an offset
voltage for Vds as was done for V ^. Nonetheless, this demonstrates a limitation o f this
model. Alterations in the equations describing the transconductance and the output
conductance are impossible. Figures 4.3.17-4.3.19 show good agreement between
measured and modeled data for the harmonics versus frequency and input power. Figure
3.16 shows the measured and simulated output power versus frequency. An excellent fit
is demonstrated in this figure, particularly for the fundamental and second harmonic
where deviations between the measured and modeled data are less than 1.5 dB. The
deviation between the measured and modeled data for the third harmonic is less than 4
dB. Figures 4.3.17 and 4.3.18 show the measured and modeled output power of this
device versus input power. In both of these plots an excellent fit is achieved for the
fundamental and second harmonic. The deviations between the measured and simulated
data for the third harmonic are less than 4 dB over all values of input power. These plots
demonstrate that after tweaking the bias voltages, the non-linear model for the FHX35LG
HEMT transistor gives good predictions. A sample test circuit for the Libra circuit
simulator and a sample test bench for an harmonic balance analysis for the FHX35LG
HEMT transistor are shown in Figures D. 1 and D.2 in Appendix D, respectively.
98
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Measured and Simulated IV Curves o f FHX35LG HEMT Transistor
40
35
——
30
Vgj=0 v (M eas)
.................Vgs*0 v (Sim )
25
•
-V gs= -0 2 v (M eas)
20
•
- Vgs«M) 4 v (M eas)
Vgs=-0 2 v (Sim )
15
* * * • ' Vgs**0 4 v (S im )
10
*•
■
-Vgs=~0 6 v (M eas)
• Vgs=*0 6 v (Sim )
5
0
15
05
2.5
3
Vds (v)
Figure 4.3.12 Measured and Simulated I-V Curves of FHX35LG HEMT Transistor
Measured and Simulated Transconductance (gm) of FHX35LG HEMT Transistor
80
70
"V g s-0 v (M eas)
60
. . . . .
it< 50
E
-•
Ygj=0 v (Sim)
- Vgs=-0 3 v (M eas)
Vgs=-0 3 v (Sim )
40
— <*— Vgs*-0 5 v (M eas)
30
• * a * - Vgs=-0 5 v (Sim )
20
10
0
0
0 .5
i
2.5
1.5
3
Vds (v)
Figure 43.13 Measured and Simulated Transconductance of FHX35LG HEMT
Transistor
99
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Measured and Simulated Transconductance (gm) o f FHX3SLG HEMT Transistor
90
■-
- V d s 883 v (M eas)
►- - - Vds=3 v (Sim)
-•
■
O
K
•
•
-0 6
-0 5
-0 4
-0 .3
-
0.2
-0.1
- Vds=2 v (M eas)
- Vds=*2 v (Sim)
Vds= I
2
v (M eas)
* Vds*I
2
v (Sim)
0
Vffttw)
Figure 4.3.14 Measured and Simulated Transconductance of FHX35LG HEMT
Transistor
20 V ds*) v (M easured)
-V d s* ) v (Sim ulated)
— X— Vds-1 2 V(M easured)
• -Vds*1.2 v (Sim ulated)
O1
Vds*0 6 v (M easured)
10 -
-Vds“ 0 6 v (Sim ulated)
1.6 v
V d s-3 v
-
0.6
-0.5
-0.4
-0.1
-0.3
0
V gs(v)
Figure 43.15 Measured and Simulated Output Conductance of FHX35LG HEMT
Transistor
100
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
80
70
V gs= 0 v
60
SO
'Sim ulated
40
Measured
30
20
10
0
0
*>
1.5
VgS“ -0 .7 v 0.5
3
2.5
Vds (v)
Figure 4.3.16 Measured and Simulated Output Conductance of FHX35LG HEMT
Transistor
15
10
5
E
B
0
Sim ulated Po % fo
M easured Po <§ fo
-5
--
-10
- -S im ulated Po % 2fo
— • — M easured Po % 2fo
- * ■ - Sim ulated Po % 3fo
■-
M easured Po % 3fo
-25
-30
-35
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
F re q u e n c y (G H z )
Figure 43.17 Measured and Simulated Output Power versus Frequency of
FHX35LG HEMT Transistor (Pin=0 dBm, Vgs—0.6 v, Vds=3.0 v)
101
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
20 -
M odeled Po ® fo
M easured Po ' g fo
* ♦ - - M odeled Po g 2fo
—•— M easured Po g 2fo
£.
3
- <►- -M odeled Po a.13fo
-20
-
M easured Po % 3fo
■
-30
-40
-I
0
I
Input Power (dBm)
Figure 4.3.18 Measured and Simulated Output Power versus Input Power of
FHX35LG HEMT Transistor (Freq.=3 GHz, Vgs—0.6 v, Vds=3.0 v)
20
15
10
5
M odeled Po g fo
M easured Po g fo
-M odeled P o g 2fo
a. -10
— *
£• -15
--
■M easured Po @ 2fo
- -M odeled Po g 3fo
■
® -20
M easured Po ' g 3fo
-25
-35
■5
-4
■3
0
3
4
5
Input Power (dBm)
Figure 43.19 Measured and Simulated Output Power versus Input Power of
FHX35LG HEMT Transistor (Freq.=3 GHz, Vgs—0.1 v, Vds=3.0 v)
102
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
4.3.1.3.4
Accurate Development o f PHEMT Models (Statz Model)
The convenience of the HEMT model residing in the simulation software
did not exist for the PHEMT transistor. The non-linear model for the HP/Avantek
ATF-36163 PHEMT does not exist within the simulation software packages
provided by the Hewlett-Packard Libra or MDS simulators. Therefore, this
necessitated the development o f an accurate non-linear equivalent circuit PHEMT
model as shown in Figure 4.3.1 for the ATF-36163 transistor. The manufacturer
of this PHEMT provides a Statz circuit model o f this device so. therefore, the
initial modeling efforts were undertaken employing the general Statz circuit
model residing in the Libra circuit simulator which uses the DC current equations
shown in equations 4.3.6 and 4.3.7. In efforts to implement the simulation o f the
intrinsic capacitors o f the Statz circuit model, the authors of the HP-Libra circuit
simulator note that the gate charge must be partitioned between the gate-source
and gate-drain branches. Therefore, the intrinsic capacitors are modeled using the
equations below [19]:
r - d Q * , d Q «*
(4.3.16)
r
(4.3.17)
&
dQg*
a is
■ dQgd
a r/
103
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
where
Vm
ax = F C »V B I
max
= \{ y * < + Vw+
v*i = j k . + ^
r«i = &
(4 .3 . 18)
+
+ y * ~ V ^ - ^ + W ) 2)
(4.3.19)
for Vnew > Vmax
Vn e w - V max
2»V BI
-
f
VBI
F
(4.3.20)
VBI
for Vnew < Vmax
(
2* VBI
(4.3.21)
\ - A \ - Vnew
VBI
while the gate-drain charge is:
(4.3.22)
Qgd ~ Cgdo • Kffi
As previously discussed, Figure 4.3.1 shows the non-linear device equivalent
circuit model. In this circuit model, the drain-to-source current Ids(Vgs,Vds) is a function
of the internal gate-to-source and drain-to-source voltages (Vgsi and V<jsi). Due to the
parasitic resistors (/?* Rd, and Rg) shown in Figure 4.3.1, the internal voltages are
104
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
different from the terminal gate-to-source and drain-to-source voltages (Vgst and Vdst)
[3,9]. The internal voltages are related to the terminal voltages by the equations shown
below [9]:
- v*, - U K - i, ( k + k )
<4 -3 -23a>
y^^Kv-LiK+K)
(4.3.23b)
Long and Butner state that the parasitic source resistance (Rs) is the most
important parasitic in the development o f the FET equivalent circuit model and efforts
should be undertaken to minimize this parasitic resistance in the design and layout o f the
transistor. As shown by equations 4.7a and 4.7b, this parasitic resistance reduces the
terminal (external) applied gate-to-source and drain-to-source voltages (Vgs,t and V^t). A
similar effect is observed for the transconductance and output conductance as exhibited
by their relationship with Rs. Defining the external transconductance available outside
the device as gme and the intrinsic (internal) transconductance as gnij, Long and Butner
relate the terminal (external) transconductance to the internal transconductance as:
<
1
'
1+ gmiR,
(4.3.23c)
and similarly for the output conductance,
105
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These equations (4.3.23a - 4.3.23d) show the effect o f the parasitic resistors on the dc
performance of the transistor. In order to improve the accuracy o f the equivalent circuit
model, the parasitic resistors were considered in the analysis. In the development of the
ATF-36163 circuit model, the manufacturer as shown in Table 4.1 supplied values for the
parasitic resistors, as well as the Statz model parameters.
Typical measured DC results for the HP/Avantek ATF-36163 PHEMT transistor
are shown below in Figures 4.3.20 - 4.3.23. The DC data was obtained using the HP
4155A Semiconductor Parameter Analyzer utilizing the block diagram shown in Figure
A. 1 in Appendix A as previously mentioned for measuring the I-V characteristics for the
HEMT transistor.
106
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Parameter
Beta (fi)
Threshold Voltage
(V ,.)or(V J
Alpha
(o r)
Lambda (A)
b
Units
Value
Yr-
0.1
V
Yv
Vv
Yv
F
—
R
—
CR
—
Cpo
C gdo
-0.55
5.0
025
1.5
0.5
350
0.1
pF
pF
C+.
pF
Ra
Q.
n
**
Q
4
nH
la
nH
4
nH
0.13
0.04
0.05
0.5
0.5
1.0
0.03
0.04
0.01
Table 4.1 PHEMT Model Parameters from Manufacturer
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
0.035
V gs-O v
0.03 V gs=-0 I v
0.025
V gJ=-0.2 v
0.02
-
Vgs=-0.3 v
0.015 0.01
V g s--0 4 v
0.005
V g W J.S v
V gs=-0 6 v
0.5
I
1.5
2.5
Vds (V)
Figure 4.3.20 Typical Measured Drain Current of PHEMT Transistor versus Drainto-Source Voltage
0.035
'0 3
• Vds=3
0.02
c.
E
■Vds=2.5
■Vds=2
9
0.015
T5
o.oi
- Vds= 1.5
-Vds=l
0.005 -
-0.7
-
0.6
-0.5
-0.4
-0.3
-
0.2
-0.1
0-^
0
Vgs (volts)
Figure 43.21 Typical Measured Drain Current of PHEMT Transistor versus Gateto-Source Voltage
108
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
0.07 0.06
0.05
>
<
B
V d s-2 .5
0.03 -
V ds=2
V ds- 1.5
0.02
BC
-
V ds-1
0.01
V d s-0 .5
-0.7
-
0.6
-0.5
-0.4
-0.3
-
0.2
-
0
0.1
0.1
Vgs (V)
Figure 4.3.22 Typical Measured Transconductance of PHEMT versus Gateto-Source Voltage
0.07
0.06
V gs= 0.1
Vgs^O
£ 0.04
<
w*
Vgs=-0.1
* - — - Vgs- -0.3
■5
ct 0.03 -. \ .
Vgs- -0.4
— ----- Vgs=-0.5
0.02
0.01
0
0.5
1.5
2
2.5
3
Vds (V)
Figure 4 3 2 3 Typical Measured Output Conductance PHEMT versus Drainto-Source Voltage
109
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4.3.1.3.4.1
Statz model as implemented in Libra
As an initial step, the accuracy of the Statz circuit model provided from the
manufacturer is determined by inserting the model parameters into the model equations
and comparing the resulting data with the measured data. Table 4.1 in the previous
section tabulates the Statz model parameters provided by the manufacturer for the
PHEMT device. Inserting these parameters into the Libra model produces the simulated
results shown in Figures 4.3.24 - 4.3.26. As mentioned in the preceding section, the
Statz circuit model utilized by the Libra circuit simulator employed the DC I-V equations
shown in Equations 4.3.6 and 4.3.7 and the intrinsic capacitor equations shown in
equations 4.3.16 - 4.3.22. A sample test circuit utilized by the Libra circuit simulator is
shown in Figure D.3 in Appendix D for the Statz model representation o f the HP/Avantek
ATF-36163 PHEMT transistor. Figure 4.3.24 shows the measured and modeled drain-tosource current (/«&) versus the drain-to-source voltage (Vds) for various gate-to-source
voltages (Vgs). Unfortunately, this plot shows large discrepancies on the order o f 20 to
40% between the measured and modeled I-V curves for all Vgs and Vds voltage ranges.
Figures 4.3.25 and 4.3.26 show the measured and modeled output power versus the input
power for the fundamental, second, and third harmonic frequencies for gate-to-source
voltages of Vgs=-0.5 volts and Vgs=0 volts, respectively. Again, the discrepancies are
large and further modeling efforts are required. Discrepancies on the order o f 20 to 65%
are observed for the fundamental, second harmonic, and third harmonic frequencies.
110
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Simulated and Measured IV Curves for ATF-36163 PHEMT
30.0
-S u n
25.0
- M a s Vgs*0 v
- *•* - -Sim Vg*“ -0 1 v
^
<
E
*
M a s Vgy--0 I v
-
* -Sim Vgs»-0 2 •.
- •
1 ■M m Vgs- - 0 z v
-Sim Vgs*-0 3 v
15.0
Meas
■
Vgs*-0 3v
- - - - -Sim Vgs*-0 4 v
10.0
■♦
- ♦
M ess V gj*-0 4 v
* -Sim Vgs“ -0 5 v
■
50
M a s V gj*-0 ? v
0.0
0
0.5
1.5
2.5
Vds (v)
Figure 43.24 Measured and Modeled IV Curves for PHEMT Using Statz’s Model
with Parameters from Manufacturer
Simulated and Measured Pout vs Pin for ATF-36163 PHEMT (f-3 GHz, V d j»2J v, Vgs—-0.5 v)
15
10
5
0
* * - - -Sim ulated (3 fo
Measured 3 fo
•5
*♦
- -Sim ulated <3 2fo
• ' * 1M easured <3 2fo
* O ’ - -Sim ulated £2 3fo
15
•
M easured % 3fo
■20
■25
■8
-6
-t
0
4
6
8
10
Pin (dBm)
Figure 4.3.25 Measured and Modeled Output Power versus Input Power for
PHEMT Using Statz’s Model with Parameters from Manufacturer
ill
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Simulated and Measured Pout vs Pin for ATF-36163 PHEMT ( W GHz. Vds-2.5 v. Vgs—0 v)
-----------Simulatcdl^fo
-10
6
s
------------ Measured <3 fo
-15
■ • ♦ * -Simulated (9 2fo
a
Measured <3 2fo
3 . .7 0
a
- - — * -Simulated (2 31b
£
- a - ■ Measured (g 3(b
-30 ^
• -
-35 t
-10 y'
-4 5 * '
-5 0 -5 5 i -
-10
-8
-6
.7
0
7
4
6
8
10
Pin (dBm 1
Figure 4.3.26 Measured and Modeled Output Power versus Input Power for
PHEMT Using Statz’s Model with Parameters from Manufacturer
As demonstrated by the preceding figures, the model parameters provided by the
manufacturer do not provide accurate fits between the simulated and measured data. The
errors obtained between the measured and modeled data are substantial for the dc circuit
model as well as the ac circuit model. Improving the fit between the simulated and
measured data is a focal point of the ensuing modeling efforts.
Optimization of the Statz PHEMT model
In device circuit modeling, it is important that accurate predictions o f the device
are achieved. A method o f improving the predictions allowing an accurate fit between
the measured and the modeled data is through optimization. Optimizing the model
parameters of the mathematical equations, such as the /<&equation, is a common approach
utilized for improving the fit between the measured and modeled data. One method of
112
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
achieving this is by changing the values of the model parameters in the mathematical
equations o f the circuit model manually, and after each manual change, the model
equations are recalculated with the results compared against the modeled data to
determine its accuracy. Depending on the observed fit between the measured and
modeled data, further optimizations may or may not have to be undertaken. Manual
optim iz atio ns have various drawbacks. This technique is very time consuming and
inefficient, particularly for mathematical equations with a substantial number of model
parameters. Without sufficient knowledge o f the sensitivity o f the parameters on the
modeling equations, the modeling efforts are very laborious and often, not very
rewarding.
Another optimization approach, which is most efficient, is through the use o f
computer optimizers. Computer optimizers are mathematical algorithms which seek to
m in im ize the error between measured data and the prediction of the mathematical
equations by allowing the computer to alter the parameters in a mathematical procedure.
In this optimization technique, a computer program representing the mathematical
equation, such as the drain-to-source equation, is developed and entered into the
optimizer. In the computer optimizer utilized in this research project, a Fortran program
is developed for the mathematical equation and entered as a subroutine to the optimizer,
and from this Fortran program, a sensitivity analysis is performed on the mathematical
equation with respect to each modeling parameter. This analysis presents a mathematical
study delineating the sensitivity of the modeling equations with respect to each
parameter. This sensitivity study presents a significant advantage in that this provides
information as to which parameters should be emphasized heavily and which parameters
113
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
have little impact on the equation over the domain of interest (in this case, the drain-tosource and gate-to-source bias voltage ranges of interest). Once this information is
obtained the optimizer can be setup to emphasize optimizing the model parameters with
the greatest impact on the modeling equation without having to arbitrarily choose
parameters.
Both optimization techniques posse varying degrees o f accuracy and both are
explored in the modeling efforts o f the PHEMT device. The initial optimization
considered, though very time consuming, is the manual technique where the model
parameters are varied manually and the resulting effect observed and compared with the
measured data. The final optimization, which is very efficient and provides rewarding
results, is with the computer optimizer where the computer alters the model parameters.
These subjects will be revisited in the following sections in greater detail.
Parameter Extraction
From the I& equation (equations 4.3.6 and 4.3.7), the parameters a and X
determines the knee of the I-V curve which is defined as the region where the I-V curves
no longer behaves linearly (Vds« 0.5 volts) and the slope of the I-V curve in the
saturation region (Vds ^ 0.6 volts), respectively. As an initial starting point for the
extraction of a and X used in the Ids equation, approximations for their values are
obtained by varying their magnitudes in equations 4.3.6 and 4.3.7 independently with
Vgs=0 v and observing the effect in the simulated of the I-V curves. These parameters
determine the performance o f the current equation around the knee region and the slope
of the I-V curve in the saturation region. Thus, observing the change in the simulated I-V
114
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
curves as a and X are varied, respectively, gives good approximations of their values. As
stated, this technique approximates the I-V curve around the knee and the slope of the
measured results o f the I-V curve o f the transistor and gives initial starting values for a
and X but does not affect the pinch-off region. As previously mentioned, the pinch-off
voltage (Vp) of equations 4.3.6 and 4.3.7 is easily assumed from the measured I-V curves.
The pinch-off voltage represents the gate-to-source voltage where the drain-to-source
current reduces towards zero and can be obtained from the measured I-V curves. These
three parameters (a, X, and Vp) give a good starting point for the development o f the dc
model. These values, along with the remaining two parameters (/? and
b)
in the Statz Ids
expression (equations 4.3.6 and 4.3.7), can be optimized to give an accurate fit between
the modeled and measured data.
Initial Optimization Procedure
The first attempt at this optimization routine was performed manually in a brute
force manner. One of the parameters was changed and the resulting effect on the
simulated data was compared against the measured data to determine the accuracy o f the
fit. This process was time consuming but, nonetheless, improved on the accuracy o f the
model over the initial model parameters provided by the manufacturer. The dc
parameters of the Ids expression (J3,
b, cl,
X and Vp) were varied until the measured and
modeled data fit as accurately as possible. The results of this initial optimization
procedure are shown below in Table 4.2. Using the parameter values o f Table 4.2 the
simulated performance can be recalculated as shown in Figure 4.3.27. Figure 4.3.27
shows the improved fit in the I-V curves o f the PHEMT using this technique. The
115
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
greatest error exhibited in this figure is shown for 0.5 < Vds < 1.5 volts, particularly as Vgs
decreases. Unfortunately, errors on the order of up to 40% are obtained.
Parameter
Beta (fi )
Threshold Voltage
<yto)o r (V p)
Alpha (a )
Lambda (A)
Units
Value
fr-
0.073
V
-0 575
%
4.0
%
0.36
%
1.85
b
FC
—
RC
—
CRF
—
0.5
450
0.1
C g jo
pF
0.225
C gdo
pF
0.175
Cd s o
K
K
*,
L*
Ld
Ls
pF
a
n
a
nH
nH
nH
0.15
0.5
0.75
0.5
0.8
025
0.2
pF
0.15
pF
0 15
Table 4.2 Statz PHEMT Model Parameters After Manual Optimization
116
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
25.00
-
5_vgs*0
m_vgs=0
20.00
s_vgs=-0.1
mvgs=-0.1
•<
E
s_vgS“-0.2
15.00
mvgs=-0.2
Wi
s_vgs=-0.3
■3
10.00
mvgs=-0.3
s_vgs=-0.4
mvgs=M)4
5.00
5 vgS"-0.5
mvg5»-0 5
0.00
0
0.5
3
1.5
Vds (volts)
Figure 4.3.27 Measured and Modeled IV Curves for PHEMT Using Statz’s Model
and Initial Manual Optimization Analysis
The ac characteristics o f the transistor have to be evaluated and modeled as well.
From the circuit model of Figure 4.3.1, the intrinsic capacitors of the model affect the ac
performance o f the transistor. As initial starting values, the parameter values provided
for the capacitors from the manufacturer are used in the circuit model along with the
improved dc parameters shown in Table 4.2. Accounting for the package and other
external parasitics, external capacitors (Cpg and Cpd) are added to the gate, drain, and
source of the transistor to give a realistic representation. Using these parameters in the
complete circuit model, the measured and simulated output powers versus the input
power o f the PHEMT at the fundamental, second, and third harmonic frequencies are
fitted by varying the ac parameters. This is accomplished by manually varying the value
o f the intrinsic capacitors and observing the simulated output power at the fundamental
117
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
and higher harmonics. Next, the values of the parasitic inductors are varied and the
simulated output power recalculated to observe the effects of these changes. This process
is repeated for the parasitic resistors and packaging capacitors until an accurate fit
between the measured data and the simulated data is achieved. This optimization is
performed manually and, as previously stated, is not very time efficient. The results of
this routine are demonstrated in Figure 4.3.28 where the measured and simulated output
power versus the input power is shown. An excellent fit is achieved between the
measured and modeled data for all harmonics up to
Pj„
~ 4 dBm. Figures 4.3.27 and
4.3.28 show drastic improvements in the circuit model accuracy as compared to Figures
4.3.24 and 4.3.25, respectively.
15
Sim ulated % fo
M easured
fa) fo
• - ♦ - - Sim ulated % 2fo
•
-20
.-
*
M easured
— •— M easured
-25 -
-40
-10
-2
0
2
10
P in (d B m )
Figure 4.3.28 Measured and Modeled Output Power versus Input Power for
PHEMT Using Statz’s Model and Initial Optimization Analysis (Freq.=3 GHz,
V,u=2.5 V, Vgs=-0.5 V)
118
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
2fo
- -Sim ulated fa) 3fo
3fo
Computer Optimization
The initial optimization routine mentioned above uses manual optimizations. As
an initial starting point for the optimization routine using the computer algorithm, the
modeling equation (Ids, equations 4.3.6 and 4.3.7) are programmed into a Fortran
algorithm, which will be utilized by the optimizer. The computer model performs a
sensitivity analysis o f the Ids equation with respect to the input parameters o f the Ids
equation (fi, Vp, a. X and b). As previously discussed the purpose of this analysis is to
determine which parameters are most influential to the Ids equation as a function of the
bias voltages (V* and Vg*). As previously noted, the purposed of the optimizer is to fit
the measured and simulated data. The measured data is entered into the optimizer
through an input data file. This input data file consists o f the measured data, the initial
values o f the model parameters (fi, Vp, a, X, and b), the model parameters which are to be
optimized along with variation ranges o f the optimized parameters. The optimizer
utilizes the input data file along with the Fortran algorithm to fit the measured and
modeled data. The results o f this optimization are seen in an output data file produced by
the optimizer. Examples of the optimizer algorithms along with input and output data
files will be presented in a following section discussing the Chalmer’s model (section
4.3.1.3.4.2).
As an initial starting point, the I-V curve for Vgs=0 v is analyzed. An accurate fit
is desired between the measured data and the simulated data of equations 4.3.6 and 4.3.7.
The optimization program fits equations 4.3.6 and 4.3.7 to the measured data by varying
the parameters of the equations (fi, Vp, a, X, and b). The first step in this optimization
technique is calculating the sensitivity o f the Ids equations (equations 4.3.6 and 4.3.7) to
119
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the various parameters over the various bias ranges. This indicates which parameter
influences the mathematical equation in the particular bias regions. Once this
information is obtained, the optimizer can be constructed to optimize accordingly. As an
initial example, the sensitivity analysis for the Statz circuit model is shown in Appendix
B for gate-to-source voltages from 0 volts to -0.5 volts. The analysis for Vgs=0 volts
show that for Vds > 0.7 volts a has no effect on the drain current equation. This indicates
that for the saturation region (Vds > 0.7) a does not influence the equation and, for the
most part, can be set to any value. On the other hand, this indicates that a is important in
the optimization for Vds < 0.7 volts. This process can be repeated for each parameter to
determine the significance o f each in the respective bias regions.
Utilizing the procedure discussed above, the I-V curve for Vgs=0 is optimized
using the computer optimizer. After this is accomplished, each individual IV curve is
optimized to fit the respective, measured data to equations 4.6 and 4.7. Eventually, a
series of fitting parameters are derived (fin,Vpn, a n,An,b n ) for the specified Vgs values
where n=l for Vgs=0 v, n - 2 for V ^—0.1 v, etc. The tabulated results for this
optimization are given in Table 4.3. Figure 4.3.29 shows the results o f this computer
optimization demonstrating the fit between the measured and modeled I-V curves using
this technique. As can be seen, the accuracy of the fit is significantly better than the fit
demonstrated in Figure 4.3.27 using a manual optimization technique. Considerable
improvement is obtained for 0.5 < Vds < 1-5 volts.
120
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P
Vp
a
>.
b
Vgs=0 V
0.0713
-0.601
3.995
02882
1.7312
Vgs=-0.l V
0.0657
-0.553
5.367
0.5131
1.9229
Vgs=-0.2 V
0.0657
-0.553
3.119
0.6041
2.309
Vgs=-0.4 V
0.0825
-0.5782
3262
0.7626
1.8487
Vgs—0 5 V
0.11226
-0.5772
42837
0.6849
2215
Table 4 3 Statz PHEMT Model Parameters Optimizing Individual IV Curves
V gs-0 V
20
Vgs~-0.1 V
15
10
5
0
00
0.5
1 .0
1.5
2.0
2.5
30
Vds (V)
Figure 43.29 Measured and Modeled IV Curves for PHEMT Using Statz Circuit
Model
The optimization procedure delineated above produces a series of dc parameters
(/?„, Vptt, a 0 ,An, bn) for the dc circuit model. However, it is desired that one set of global
dc parameters can be determined to accurately predict the dc performance of the
121
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transistor. This is difficult to achieve using the Statz circuit model because the dc
parameters are not defined by global equations. In other words, the dc parameters are not
defined as functions of
and Vg* but rather as constants independent of the
and Vgs
values. Expressing the dc parameters globally would improve the accuracy o f the Statz
model. Nevertheless, one set o f dc parameters which provides the best fit for the
measured and modeled is determined by manually optimizing the measured data with the
simulated results of equations 4.3.6 and 4.3.7. The results o f this analysis are shown in
Figure 4.3.30. This plot shows that the accuracy o f the fit between the measured and
modeled I-V curves decreases as a result of using one set o f parameters for the circuit
model.
25.0 -
V gs*0 V
20.0
Simulated
<E
15.0
Measured
10.0
0.0
0
0.5
1.5
2.5
3
V ds (v)
Figure 4.330 Measured and Modeled IV Curves for PHEMT Using Statz Circuit
Model with One Set of Parameters
122
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43.1.3.4.2
C halm ers Model
A recent model has been developed specifically for MESFET/HEMT transistors
[20- 25.]. One o f the added advantages in using this model is that it has been derived
specifically for HEMT transistors and, therefore, improves the accuracy in modeling the
transconductance (gm)- Golio [2] has shown that the transconductance is critical to the
accurate prediction o f large-signal effects and the modeling of the transconductance o f
HEMT transistors is different than that o f typical FET transconductance, and Maas [26]
has pointed out that not only the Ids and Vds characteristics, but the derivatives must be
properly modeled for accurate prediction o f intermodulation distortion. In contrast to the
previous models mentioned in section 4.3.1.3.2, the Chalmer’s model specifically fits the
measured and modeled transconductance initially, and then fits the drain-to-source
current. The success o f the Chalmer’s model lends credence to this being a significant
impact on the success o f developing an accurate circuit model.
The equations for the drain-to-source current in the Chalmer’s model are given as
[20-25]:
/* = / At(l + ta n h (v ))ta n h (a ^ X l + * V j
(4.3.24)
where
=
- v j + P,{v„ - v j
(4.3.25)
where Ipk is the drain current at maximum transconductance, VPk is the gate voltage at
which maximum transconductance is achieved, k is the channel length modulation
parameter and is the same as that used in the Statz model, and a is the saturation voltage
parameter and is also the same as that in the Statz model. Creating a plot o f the
123
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transconductance and drain current versus gate-to-source voltage for the device measured
in the saturated region (Vds-2.5 v in this analysis) defines Pi and Vpk of equation 4.3.25.
As outlined by the authors of this model, a first approach for Pi shows:
/> *
' Ipk ,
(4.3.26a)
where gms is the maximum transconductance, IPks= Ipk is the maximum drain current at
gms, and Vpk is the gate-to-source voltage for which gms is achieved. Figure 4.3.31
shown below demonstrates the extraction of Pi, gms Ipks, and Vpk from a typical
transconductance and drain-to-source current versus
plot. From this example plot it is
observed that gms=58 mA/V, 1^= 20 mA, Vpks=-0.I9 V, and thus P\=2.9.
Typical Transconductance and Drain Current
0.07
0.06 :
0.05
0.04
0.03
0.02
0.01
-0.7
-
0.6
-0.5
-0.4
-0.3
-
0.2
-
0.1
0
Vgs(V)
Figure 4.331 Typical Extraction Plot for Implementation of Chalmers Model
124
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As an additional exercise to gather insight into the origin of equation 4.3.26a used
by the developers of the Chalmer’s model, consider the drain-to-source current equation
given by equations 4.3.24 and 4.3.25. Calculating the transconductance (gm) from
equations 4.3.24 and 4.3.25 gives:
Sm
au
^
= / „ ta n h (o ^ Xl +
) ■•a t^
s y ^(T )
(4.3.26b)
= / „ ta n h ( a ^ Xl + X V . Xsec h! v )
•W
- r * ) + 3 P ,K ~ y j ]
(4.3.26c)
and
ms
=m \ y%s=ypkjpk=ipks =l Pk, tanhCflrf^)
•
0 + k v * ts e c h 2 'i’)P]i
(4.3.26d)
At the peak value of Vgs (Vgs=Vpk), *F=0 from equation 4.3.25 and. therefore, solving for
Pi in equation 4.3.26d gives:
P'
V tan h fc^X l +
(4326e)
In the saturation region,
(l + XV^ ) ta n h ( a ^ ) * 1
(4.3.26f)
125
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so, therefore, inserting equation 4.3.26f into equation 4.3.26e gives
(4.3.26g)
It has been shown that when the device operates in the saturated region. Pi and
Vpk can be considered constant [25]. However, in this particular modeling application
(i.e. for use in multiplier circuits) it is important that accuracy is achieved at lower drain
voltages as well {Vds close to zero volts). In an attempt to accomplish this, the global
behavior of the transistor as a function of the drain-to-source voltage has been modified
by the authors o f the Chalmer’s model as [23-25]:
(4.3.27)
(4.3.28)
(4.3.29)
where VPk0 = gate-to-source voltage occurring at maximum transconductance (gm<,) at
Vds close to zero volts (Vds=0.2 v, in this case)
gm0 = maximum transconductance measured at Yds close to zero
Volts (Vds=0.2 v)
126
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Ipko
= drain current measured at gm<,
B = a constant (initially * 1.5a)
The drain-to-source current has been shown to exhibit accurate matches between the
measured and modeled data when the saturation parameter (a) is given by a global
definition as well. These authors have shown this as:
a = a r + a,[l + ta n h ^ ) ]
(4.3.30)
where a r and a, are constants.
From the measured transconductance and drain current o f the PHEMT transistor
plotted versus Vgs for V<js=2.5 volts, parameters Ipks, Vpics, and gms are determined and
from equation 4.10, P/s is calculated. (In this initial analysis, IPks-23 mA, Vpks=-0.1 V,
gms=58 mA/V, Pis = gm /Ipkj = 2.52, Pis=Pi, andPi= P 3 -O.) Using these values, the
dl
drain-to-source current (/<&) (equations 4.3.24 and 4.3.25) and gm, where gnt = — — , are
dV
easily calculated. In order to obtain optimum performance, computer optimization
techniques were employed to optimize these parameters as in the case of the Statz circuit
model.
One o f the significant differences in the Chalmer’s model is that this circuit model
requires fitting the measured and simulated transconductance at the initial point o f the
model development in contrast to the other models discussed which begins with a fit for
the drain current alone. Once a fit is established for the transconductance, the match for
127
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the drain current should exist from the fitting o f the transconductance to within a constant
since the transconductance is the derivative of the drain-to-source current plus an
additional constant. Therefore, the initial computer optimization begins with the
development o f a Fortran program calculating the transconductance o f the Chalmer’s
model as shown in equation 4.3.35. The computer model calculates the sensitivity o f the
transconductance with respect to the modeling parameters (P/s, Pio. Pi, P3. Vpko, Vpks, ipk,
a, y/, and A.) from the Fortran program, as shown in Appendix B. The sensitivity
Qy
( S* = ---- —= — —) is calculated by taking the derivative o f the transconductance with
d ln x y dx
2
respect to the modeling parameter (e.g. SjT =
dlnfF iJ
_ £ u _ ^Sm etc y Performing
gm dP u
this sensitivity analysis highlights significant conclusions. This analysis demonstrates the
need for slight modifications to the original Chalmer’s model equation for Ids (equation
4.3.24). The computer model computes the sensitivity o f gm and Ids by calculating the
derivatives o f each equation o f the Fortran program with respect to the modeling
parameters. As seen by equation 4.14 for instance, a is a function of
and from
equation 4.3.25, !Pis determined by Vpk. Vpk, as noted from equation 4.11, is also a
function o f a so in affect a is defined by an equation, which is a function o f itself (a).
This relation is not allowable for the computer model to perform properly. Thus, the
original Chalmer’s equations (4.3.24,4.3.27,4.3.28, and 4.3.30) are now modified to
give:
/* = / M(l + tanh(>P))taiih(a,^X l+AF*)
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(4.3.31)
W * ) =
+(v* - ^ J t a n h f o r J
cosh2(l.5acF j
(4.3.32)
(4.3.33)
(4.3.34)
a v = a r + a, [l + ta n h ^ )]
h + 2 P ; (rp - r J + 3 P , ( r , , - r , t )i ]
m = ipk O + ^Kfc)-
cosh2( o r ^ )
(4.3.35)
a)
Individual Curve Modeling
As an initial, simple application of the modified Chalmer’s model as developed
by the author, the equivalent circuit for the PHEMT is modeled without the global
definitions of equations 4.3.27- 4.3.30 and fitted for the drain-to-source current
(equations 4.3.24 - 4.3.26) without regard to the transconductance. At this juncture, to
reiterate the objective, the goal is to match the measured I-V data measured in the
laboratory as shown below in Figure 4.3.32 to the mathematical equation (equations
4.3.24 - 4.3.26). Since the global modeling of the transistor is of greater importance than
the localized modeling at specific bias points, the optimizer programs and data files will
be shown for the global modeling. The initial analysis is begun by the computation o f the
sensitivity of the /<&equation using the non-global definitions with respect to the
129
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modeling parameters {Pi, Vpk) Ipkl a, and X). The sensitivity analysis shown in Appendix
B in TableB.2 shows the dependency o f the drain current equation to the modeling
parameters from 0 <
< 3 v for various values of Vgj. As seen from the sensitivity
0 04 .
0.035 V gs-0 v
003
0025
-
2M
002
0015
001
0 005
0
05
IS
2
2.5
3
V d s (V )
Figure 4 J 3 2 Measured IV Curves of PHEMT Transistor
analysis for Vgs 0-2 v, a influences the drain current equation significantly for low
drain-to-source voltage (V& < 0.4 v) but its affect diminishes for higher drain-to-source
voltages. This implies that optimization for a is important for low drain-to-source
voltages but not so significant for higher voltages. Conversely, X significantly affects the
drain-to-source current at higher drain-to-source voltages while having little impact at
lower voltages. Using this information, an input data file is constructed delineating the
model parameters which are to be optimized along with the measured drain-to-source
current. Afterwards, the input data file is provided to the optimizer algorithm. As in the
130
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development o f the initial Statz model previously discussed, the initial Chalmer's model
optimization is implemented for individual Vgs values fitting the measured drain-tosource current to the /* equations (equations 4.3.24 and 4.3.25). This optimization
technique optimizes Pi, Vpkj Iph a, and X of equations 4.3.24 and 4.3.25 for each value of
and provides a series of parameters {Pin, Vpkn lpkrb a„, X„) for the Ids equations which
fits the individual measured I-V curves for Vgs. The tabulated results o f this optimization
for the HP/Avantek-36163 PHEMT transistor are shown in Table 4.4. Figure 4.3.33
shows the measured and modeled results of this initial application of the Chalmer’s
model. Excellent fitting is observed between the measured and simulated data over all
voltage ranges.
1*
Vpk
a
X
Pi
Vgs=0 V
0.01255
-0.14109
3.0516
031612
4.583
Vgs=-0.2 V
0.0136
-0.1
3.713
0.411
3327
Vgs=-0.4 V
0.0228
-0.1
03834
0.1194
2.425
Vgs=-0.6V
0.01365
-0.1
03429
03135
3327
Table 4.4 Chalmers PHEMT Model Parameters Optimizing Individual IV
Curves Using Non-global Equations
131
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40 Vgs=0 V
Measured
Simulated
30 -
~ 25 -
Vgs=-0.2 V
<
I. 20 M
15 -
0
0.5
1.5
2
2.5
3
Vds (V)
Figure 4 3 3 3 Measured and Modeled IV Curves for PHEMT Using
Chalmer’s Circuit Model
b)
Global Modeling
As previously mentioned, the modified Chalmer’s model defines the parameters
o f the Ijs and gm equations with global equations as shown by the author’s revised
equations 4.3.25 and 4.3.31 - 4.3.35 with alterations to the original equations. Since the
global behavior of the PHEMT is o f greater interest, the input and output data files, the
Fortran program used by the optimizer, the sensitivity analysis, and various output data
files are presented in Appendix B and C. In order to take advantage o f this global
behavior, equations 4.3.25 and 4.3.32 - 4.3.34 are inserted into the gm equation (equation
4.3.35). The global modeling development is governed by two Vds voltages: 1)
132
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in
saturation (Vds=2.5 volts in this case) and 2)
close to zero volts (Vds=0.2 volts in this
case). Initially, a sensitivity analysis for g„ is performed using equation 4.3.35 with
respect to the modeling parameters (Pis, Pio, P2. Pi, Vpko. VPks Ipk, a* , <*r,, ctu and A) for
several
values as shown in Appendix B. With reference to Table B.3 in Appendix B,
this sensitivity analysis shows that for Vds=2.5 v, Pio, Vpko, and etc do not influence gm
significantly (the sensitivity analysis produces values o f zero over the entire bias range)
and that a r and <X[ have less of an influence on gm as Vgs increases (the sensitivity values
decrease as Vgs increases). For V ^O .2 v, Pio, VPko, and Oc impacts gm (these sensitivity
values are non-zero) and ar and ai influences gm over the entire Vgs range. This analysis
indicates which parameters should be optimized to fit the measured and modeled
transconductance at the appropriate bias ranges. The final conclusion is that for Vds=2.5
volts, parameters Pn, P 2 , P3, VPk* Ipk, ctr, at, and A should be optimized and for V<js=0.2
volts <Xa P 1o, Vpko, and or/ should be optimized.
The previously determined values for IPks, Vpks, and P u (Ipks=23 mA, Vpks=-0.1 V,
and P i s = 2 . 5 2 ) obtained from the transconductance and drain-to-source current versus
gate voltage extraction plot (similar to Figure 4.3.31) are substituted into equation 4.19
with Vds=2.5 volts. The parameters defined in equations 4.3.27 and 4.3.28 for Vjs values
close to zero volts ( V Pko,
P io ,
and gm0) have little affect on the transconductance when
operating in the saturation region. Therefore, having yet to define these parameters (Vpko,
Pio, and gm0) poses no problems in this initial calculation o f gm with Vds~2.5 volts.
Using the optimization program to fit the transconductance further, an excellent global
fitting between the measured and modeled transconductance data is achieved as shown
below in Figures 4.3.34. The further optimization is mainly used to optimize the values
133
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o f ar and a/. Figure 4.3.35 shows the measured drain current and the resulting modeled
drain-to-source current from equations 4.3.31 - 4.3.34 using the extracted and optimized
model parameters. As seen by these plots, excellent fitting is achieved for the
transconductance and drain current at V<b=2.5 v and from Figure 4.3.35, optimizing the
drain-to-source is not required as demonstrated by the excellent fit. The computer
programs (Fortran program for g„, input file, and output file) for this VdS=2.5 v
optimization are given in Appendix C.
70
60 -
M easured
Sim ulated
-0.7
-0.6
-0.5
-0.4
-0.3
-0 .2
-0.1
0
0.1
0.2
0.3
V gs (V )
Figure 4 3 3 4 Measured and Simulated Transconductance o f Chalmer’s
Model Using Global Equations (Vds=2.5 volts)
134
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50
M easured
Simulated
_
-0.7
-
0.6
-0.5
-0.4
-0.3
-
0.2
-
0.1
0
0.1
—
0.2
-—
» -
0.3
V gs (V )
Figure 4.335 Measured and Simulated Drain Current of Chalmer’s Model
Using Global Equations (Vds=2.5 volts)
As mentioned, in order to develop the revised Chalmer’s model globally, a second
drain-to-source voltage close to zero volts has to be modeled as well. In this application,
this voltage is chosen to be Vds=0.2 volts. The measured transconductance and drain
current extraction plots of the transistor for Vds=0.2 volts are used to determine the final
parameters o f the global circuit model (VPko, Pio, Ipko, and gm0) as done similarly for the
case ofVds=2.5 volts. Substituting these values along with the values obtained from the
saturation region (Vpks, Pis, and Ipks. ccr , and a{) defines the complete global equation for
the Chalmer’s model. The transconductance and drain current model parameters are
optimized simultaneously using the computer optimization programs to get accurate fits
between the measured and modeled data. Figures 4.3.36 and 4.3.37 show the
transconductance and drain current o f the measured and modeled data for Vds=0.2 volts.
135
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As seen by these plots, modeling at low drain-to-source voltages presents more of a
challenge than modeling in the saturation region. The fit between the transconductance
and drain current in the saturation regions of Figures 4.3.34 and 4.3.35 is better than that
demonstrated by the region close to V ^ O volts o f Figures 4.3.36 and 4.3.37.
35 -
M easured
S im ulated
-0 .7
-
0.6
-0.5
-0.4
-0.3
-
0.2
-0 . 1
0
0.1
0.2
0.3
V gs (V )
Figure 4.336 Measured and Simulated Transconductance of Chalmer’s
Model Using Global Equations (Vds=0.2 volts)
136
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14
12-10
-
M easured
Sim ulated
-0.7
-0 6
-0.5
-0.4
-0.3
-
0.2
-
0.1
0
V g s (V )
Figure 4.337 Measured and Simulated Drain Current of Chalmer’s Model
Using Global Equations (Vds=0.2 volts)
The accuracy of the global modified Chalmer’s model at other bias voltages is of
interest also. Figures 4.3.38 and 4.3.39 show the transconductance and drain current
versus Vgs for Vds=2.0. These plots continuously demonstrate great fits between the
measured and modeled data utilizing this model. Figure 4.3.40 shows the complete I-V
curves for the modified global circuit model presented by the author. Accurate fits
between the measured and simulated data are demonstrated in this plot. The tabulated
results o f the parameters in equations 4.3.25 and 4.3.31 - 4.3.34 for the global modeling
of the revised Chalmer’s model are shown below in Table 4.5.
137
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60 -
M easured
S im ulated
0
-0.7
•0 6
-0.5
-0 4
-0.3
-
0.2
-
0.1
0
0.1
~
0.3
0.2
Vgs (V)
Figure 4 J J 8 Measured and Simulated Transconductance of Chalmer’s
Model Using Global Equations (Vds=2.0 volts)
M easured
40
Sim ulated
-0.7
-
0.6
-0.5
-0.4
-0.3
-02
-
0.1
0
0.1
0.2
0.3
Vgs
Figure 4 3 3 9 Measured and Simulated Drain Current of Chalmer’s Model
Using Global Equations (Vds=2.0 volts)
138
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40
-
35
_
M easured
M odeled
30
25
20
15
V gs“ -0.3 v
10
V gs=-0.4 v
5
V gs=-0.5 v
0
V gs=-0.6 v
0
0.5
■>
1.5
3
2.5
Vds
Figure 4.3.40 Measured and Simulated Drain Current of Chalmer’s Model
Using Global Equations
Ipk
P is
P .o
P2
P3
V pk0
Vpks
0.017
1.971
3.34007
0.3439
2.443
-0.3014
-0.0021
0.26375
Ctc
Ctr
e ti
0.68
0.1168
1.25
Table 4.5 Chalmer’s PHEMT Global Model Parameters
The final dc parameter evaluated is the output conductance. As mentioned under
the discussion for the Statz model, X defines the slope o f the I-V curves. This parameter
in the Chalmer’s global model is identical to that used in the Statz model, therefore, the
139
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value for k in the Statz model for the PHEMT provided an initial starting point in the
Chalmer's model. Figures 4.3.41 and 4.3.42 show the measured and modeled output
conductance using the modified Chalmer’s model versus
and Vds, respectively,
exemplifying good agreement between the measured and modeled data. The greatest
discrepancy is seen for the Vds=0.5 volts curve in Figure 4.3.41. This trend was observed
for small Vds values for the output conductance in the HEMT device model as shown in
Figure 4.3.15. At this juncture it should be noted that if the agreement between the
measured and modeled output conductance were not acceptable, an additional
optimization cycle would have to be implemented.
50 -
M eas (V ds= 2.5)
Sim (V d s -2 .5 )
— x — M eas (V d s -2 .0 )
• - x- - - Sim (V d s -2 .0 )
— A— M eas (V d s -1 .0 )
- - ■ A -- S im ( V d s - 1.0)
— i— M eas (V d s -0 .5 )
-S im (V d s -0 .5 )
V g s(v )
Figure 4.3.41 Measured and Simulated Drain Output Conductance of
Chalmer’s Model Using Global Equations
140
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
■+— Meas. (V gs= 0)
Sim (V gs^O )
-o— M eas. (V g s—0.2)
Sim (V g s—0.2 )
■X— M eas. (V g s—0 4)
Sim (V gs—0.4)
A — Meas. (V g s —0.6)
Sim (V g s—0.6)
Figure 4.3.42 Measured and Simulated Drain Output Conductance of
Chalmer’s Model Using Global Equations
AC Performance o f Chalmer’s Model
The ac performance of the Chalmer’s circuit model is governed by the parameters
discussed previously in this section and the intrinsic capacitors (Cgs, Cg& and C*) shown
in Figure 4.3.1 and package capacitors which are not shown in Figure 4.3.1. Therefore, a
means of simulating the equivalent circuit model capacitors is necessary. Chalmer’s [25]
used a simple capacitor junction model to simulate the capacitors Cgs and Cgj. As
mentioned by the reference to Golio in section 4.3.1.3.2, Golio notes that the simple
junction capacitance expressions fail to predict accurate capacitance values for low drainto-source voltages. With regards to this observation, the author is using the StatzRaytheon capacitance expressions (equations 4.3.8 - 4.3.15) to model the gate-to-source
and the gate-to-drain capacitors o f the ATF-36163 PHEMT transistor. Figures 4.3.43 to
141
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4.3.46 show the simulated Cgs and Cgd capacitor values used for modeling the PHEMT
transistor. Figures 4.3.43 and 4.3.44 show Cgs and Cgd versus the gate-to-source voltage
for various
values while Figures 4.3.45 and 4.3.46 show Cgs and Cgd versus the drain-
to-source voltages for various Vgs values.
0.225
0.2
0.175
0.15
0.125
-0.5
-0.45
-0.4
-0.35
-0.3
-0.25
-0.2
-0 15
-0.1
-0.05
0
Vgs (volts)
Figure 4.3.43 Simulated Gate-to-Source Capacitance {Cgs) o f ATF-36163
PHEMT
142
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.Or+7Tl"l
17505
0.17495
Vds*2 v
Vds=2.5 v
0.1749 .
Vds=3 v
0.1748 -
-0.5
-0.45
-0 .4
-0.35
-0.3
-0.25
-0.2
4 )1 5
-0.1
-0.05
0
Vgs (voits)
Figure 43.44 Simulated Gate-to-Drain Capacitance (C g<t) of ATF-36163
PHEMT
0.24 .
0.22 ;
0.2 - Vgs“ 0 v
sZ
c.
srt
,ef>
0.18
- Vgs=-0.2 v
V g sM M v
0.16
- Vgs=-0,5 v
0.14
0.12
0.1
0.3
1
1.5
2.5
Vds (volts)
Figure 4.3.45 Simulated Gate-to-Source Capacitance (Cgs) of ATF-36163
PHEMT
143
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
0.22
0.21
0.2
c.
0 19 \
-3
so
0.18
0 17
0.16
0
0 .5
1
1.5
2
2.5
Vds (volt)
Figure 4.3.46 Simulated Gate-to-Drain Capacitance (C ga) of ATF-36163
PHEMT
The Chalmer’s model has shown great results with the measured and modeled
data fitting quite well as demonstrated in the previous plots. This model was specifically
developed for MESFET and HEMT transistors and this account for the great accuracy
achieved in this modeling effort as expected. Additionally, the inclusion o f the global
modeling parameters contributes to the improved accuracy as well. This model is fairly
practical to implement and offers an excellent technique for modeling PHEMT
transistors.
144
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4.3.2
4.3.2.1
Q uantification of Nonlinearities
Introduction
As previously mentioned, frequency multipliers are harmonic generators which
produce various frequency multiplies of an input (fundamental) frequency. A
prerequisite o f producing frequency harmonics is the availability of a nonlinear
component such that when excited by a fundamental frequency generates a spectrum of
output harmonics which are multiples of the fundamental frequency. Therefore, it is
apparent that the nonlinear component is a crucial and vital element in the generation of
frequency harmonics and warrants a detailed evaluation. For this reason, the following
discussion is devoted solely to the quantification of the nonlinearities required for the
design o f passive and active frequency multipliers.
4.3.2.2
Passive Devices
Frequency multiplication in passive devices can be achieved by the exploitation
of the nonlinear properties o f nonlinear resistors, nonlinear inductors, or nonlinear
capacitors. Exciting these nonlinear devices by an input fundamental frequency
generates an output frequency spectrum at multiples of the input frequency. Typical
nonlinear devices used for designing passive multipliers include rectifying metalsemiconductor junctions with their nonlinear current-voltage characteristic, reversebiased metal-semiconductor or pn-junctions with their nonlinear capacitance, and
nonlinear transmission lines having distributed nonlinear capacitance. [86,87]
As an example demonstrating the feasibility o f a passive multiplier exploiting the
nonlinear capacitance, consider a varactor diode with is frequently the nonlinear element
145
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responsible for producing frequency harmonics in passive multipliers. The varactor
diode possesses a nonlinear charge-voltage and, subsequently, a capacitor-voltage
characteristic that is ideal for producing a frequency spectrum when excited by a
fundamental frequency. The varactor, as shown in the model below (Figure 4.3.47),
exhibits a nonlinear capacitance-voltage characteristic that varies as a function o f the
applied voltage across the nonlinear capacitor. The junction capacitance o f the diode
provides a varying reactance that varies nonlinearly as a function o f the applied voltage.
The nonlinear capacitance o f Figure 4.3.47 is given in equation 4.3.36 shown below as
[88].
o
Rs
WNA
C(v
O
Figure 43.47 Simple Model of a Varactor
(4.3.36)
146
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
where <J>= built-in potential
V = applied voltage
Cj0 = value o f Cj with V = 0 volts
Expanding
C j(V )
in a binomial expansion yields
c/n =c,„o-w/:
=Cj0[l + i ( W
+
- ± ( V /t? + ...]
=a 0 + a xV + a 2 V 2 + a y 3 + ...
(4.3.37)
where ag = Cjg
a l = c j& ( 2 <
t>)
a 2 = 3Cj(/ < 8 f )
a j = -5Cjq/( 16(f?)
Also from Equation (4.3.36),
ocn =\cj(V)dv
=J(a0 +axV+ a2V2 +...)dV
=a0V +j a y 2 + j a y 3 +j a y 4 +...
147
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
(4.3.38)
This allows the current through the diode to be represented as:
m
=
dQ
dt
4[ar„r + iar1K! + ia,F J+...]
dt
‘
1
(4.3.39)
As an example demonstrating the effect of exciting the pn junction diode with a
fundamental frequency signal, consider the junction excited by a sinusoidal source of V(t)
= cos cot where
qj is
the fundamental frequency. Then, inserting this sinusoidal voltage
into Equation (4.3.27) gives
Cj{t)
=Cj0 + ^ c o s r y r + ^ ^ [ ! ( l + c o s 2 ry 0 ]-^ j[|c o s < y r + :rcos3<yr]
o<p~ ~
Ztp
C ,o +
3C J 0
16^2
16<p
3r jO\
15CJ0^
5C>0
cosruf+
cos 2 cot —
cos3ruf+...
2<
f> (A tf
64^ 3
16f ' j
0
(4.3.40)
and using (4.3.40) into equations (4.3.38) and (4.3.39) yields
m
3Ci0a \
(2coCj 0
yo sin 3cot +...
s m cotsin 2 cot= - Ci0Q) + —
32^
„ '
,
148
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
(4.3.41)
Equation 4.3.41 shows that the output current has frequency components at co. 2co. 3<o.
etc., even though the junction was only excited by a single fundamental frequency. Thus,
this example illustrates the frequency spectrum generated at the frequencies co, 2 co. and
3co, etc., and how this nonlinear device can be utilized in the designing frequency
multipliers. From this analysis, it is seen that the diode parameter of most significance
for harmonic generation is its nonlinear capacitance (Cj (V)) which varies instantaneously
with applied voltage.
4.3.2.3
Active Devices
The previous section discussed a mechanism for producing harmonics utilizing
passive devices. Active elements provide nonlinear characteristics that can be exploited
in the design o f frequency multipliers as well. This section will quantify the
nonlinearities pertinent to active devices that lend them useful to the design of
multipliers.
As previously mentioned, a nonlinear element (e.g. such as a nonlinear capacitor
illustrated above) excited by a single frequency source produces a spectrum o f frequency
harmonics. In the design o f active multipliers, the nonlinear element typically includes
any of several transistor classes such as BJT, FET, MESFET, HEMT, etc. Figure 4.3.48
shows a circuit model of a nonlinear HEMT/PHEMT transistor demonstrating the
nonlinear elements of the transistor which are exploited in the generation of frequency
harmonics.
149
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Previous Analyses
In analyzing FET performance several authors have addressed the issue o f
identifying the elements which contribute to the nonlinear behavior of FET transistors
[2,28,29,32,39,46,50,51.54]. Maas [39] analyzes the nonlinear behavior of MESFET
transistors. In his study, Maas* has provided the magnitude o f all parasitic components
(Ls, Lg, Ld, Rp Rs, and Rj) and intrinsic components* (/?/, Rd* CgS, Cgd, and gm) in tabular
form for various bias voltages which provides insight on the nonlinear behavior o f these
components. Maas’ data for the parasitic inductors (Z* Lg, and Ld) show that the
magnitudes of these inductors are very small and are on the order o f hundredths o f nH.
Their values vary from 0.03 to 0.08 nH for Ls, from 0.09 to 0.12 nH for Lg, and 0.06 to
0.07 nH for Ld or, at a worst case analysis, their magnitudes vary by only 0.05 nH over
the bias ranges. This indicates that at an arbitrary frequency of 1 GHz, the impedance o f
this inductance variation is approximately 0.25 ohms. This implies that the parasitic
inductors can be approximated with fixed, constant values for all bias regions and,
therefore, do not contribute as a source o f nonlinearity to the MESFET. The magnitude
o f the parasitic resistors (Rg, Rs, and Rd) vary by only a few tenths o f an ohm as functions
o f applied voltage. Therefore, similar to the parasitic inductors, their magnitudes can be
fixed as constants in the device models as their resistance does not vary significantly as
functions of applied bias, and, thus, they do not contribute as a source of nonlinearity to
the MESFET.
Maas’ data shows that the output resistance o f the MESFET varies nonlinearly
over bias from approximately 10 ohms to 283 ohms [39]. This variation is significant
* Reference 39, pages 26-27 and 58-59
+ Rh not shown in Figure 4.3.1, is the charging resistor in series with Cp
150
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Maas’ data shows that the output resistance o f the MESFET varies nonlinearly
over bias from approximately 10 ohms to 283 ohms [39]. This variation is significant
and indicates that due to this nonlinear characteristic, the output resistance of the
transistors is one of the contributors to the nonlinear effects observed in the MESFET
transistor. The gate-to-source and gate-to-drain capacitors (Cgs and Cgd) also vary
nonlinearly as functions o f applied voltage. Cgs is shown to vary from 0.415 pF to 0.636
p F and Cgd varies from 0.049 p F to 0.266 pF. This nonlinear variation in Cgs and Cgj
indicates that they are viable contributors to the harmonic production of the MESFET as
well. The final element considered by Maas is the transconductance. The
transconductance shows significant nonlinear variation over bias particularly in the
saturation region as it varies nonlinearly from 61.3 mS to 89.2 mS. This nonlinear
variation indicates that it also contributes to the nonlinear behavior o f MESFET. In
summary, Maas’ study reveals that the elements significantly contributing to the
nonlinear behavior of the MESFET are Rds, Cgs, Cgd, and gm. The remaining elements (Ls,
Lg, Ld, Ru Rg, Rs, and Rd) do not vary nonlinearly and can be considered as constants in
the device models. The results o f Maas study was performed on a MESFET, however,
but this study can be referenced in the study of identifying the nonlinear contributors to
the HEMT and PHEMT transistors which will be discussed in later sections. This
analysis presented by Maas can also be presented graphically by plotting the intrinsic
parameters o f the device model as functions of applied bias. This graphical technique
will also be discussed and demonstrated in later sections.
Gopinath and Rankin [32,72] have performed a study identifying the relative
contributions o f the various nonlinear elements of MESFET’s valuable for harmonic
151
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generation. In their study, they emphasize harmonic generation at the second harmonic
frequency using computer simulations to aid their study. The conclusion of their work
identifies the major contributors to the nonlinear behavior o f the MESFET are: 1) Cgs and
Cgd 2) drain current nonlinearity which occurs from the drain current clipping when
swings below pinch-off or into forward conduction and 3) the nonlinearity of the drain
current equation representing Ids and 4) output resistance nonlinearity.
Gopinath and Rankin state that using their computer model, in the absence of
other nonlinear contributions, the second harmonic power level due to Cgs is on the order
o f 18 to 11 dB below the output power at the fundamental. In evaluating the effect of Ids
clipping, they neglect the transfer characteristic of Ids and perform a Fourier analysis of
the half-wave rectified waveform with Vgs=0 volts. They find that the second harmonic
output power level is 7.4 dB below the output power level at the fundamental. Gopinath
and Rankin analyze the nonlinear contributions from the Ids current equation nonlinearity
and the output resistance by simulating the harmonic response o f the FET with the drain
current represented by equations 4.3.42 and 4.3.43, respectively. The simulations show
that the second harmonic output power level is 16 dB below the output power level at the
fundamental using equation 4.3.42 to represent /*, and that the second harmonic output
power level is 15 dB below the output power level at the fundamental when using
equation 4.3.43 to represent Ids-
(
Id s
=
I* s
1
gs
4.3.42
p
152
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The conclusion of the work by Gopinath and Rankin is that the major contributor
to the nonlinearity of the FET is the Ids nonlinear clipping effect which produced second
harmonic output power 7.4 dB below the output power at the fundamental. Slight
contributions to the nonlinearity of the FET came from the
C gs
nonlinearity, output
conductance nonlinearity, and Id s transfer nonlinearity. The study performed by Gopinath
and Rankin uses approximations in the computer simulations, however. The computer
model neglects the gate-to-drain branch o f the circuit ( C gd and
D gd ) ,
the authors use a
predetermined unknown resistive load (R l), and the authors indicate that the results are
valid only for Rl « R d a where Rdo is the output resistance. A final observation of this
study is that measured data indicating the accuracy and practicality of the results are not
presented.
Dow [50], based on the work of Camargo [51], discusses the nonlinear
contributions o f the MESFET transistor using a graphical approach. He develops an
equivalent circuit model from measured S-parameters to evaluate the bias dependent
nonlinear circuit intrinsic elements, and, afterwards, presents curves representing g m ,
and G d s versus Vgs and
C g s,
to show the nonlinear behavior o f these parameters.
Examining the curves, Dow identifies particular bias regions o f Vgs and Vds where the
nonlinear variation o f gm and G d s is more prominent and significant for harmonic
generation. With regards to the contribution from
C gs,
Dow references the study
performed by Gopinath and Rankin as previously discussed in stating that second
153
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harmonic generation is weakly dependent upon
Cgs
nonlinearity. In conclusion. Dow's
study states that harmonic generation is obtained from three sources o f the MESFET 1)
nonlinearity o f the intrinsic parameters Cgs, gm, and Gjs 2) current rectification which
occurs when the gate voltage swings into forward conduction and 3) current clipping
occurring when the gate voltage swings below pinch-off. This graphical method will be
revisited in later sections in discussing HEMT transistors.
The previous discussions have been on the determination o f the nonlinear
elements responsible for harmonic generation in MESFET’s. Focusing on the HEMT
transistor, Golio [2] states that the major nonlinear elements of the HEMT device are 1)
the drain-to-source current Ids, from which the transconductance and output conductance
are derived 2) the gate-to-source and gate-to-drain capacitors (Cgs and Cgd) and 3) the
gate-to-source and gate-to-drain diodes (Dgs and Dgd).
In Golio’s analysis on HEMT transistors, he does not present data graphically or
in tabular form demonstrating the nonlinear characteristics of the intrinsic elements o f the
HEMT model.
Devices Used in This Study
a)
HEMT
Modeled drain-to-source current, transconductance, and output conductance data
for a Fujitsu FHX35LG HEMT is shown below to demonstrate the nonlinear
characteristics o f these types of active devices. Static I-V curves are shown in Figures
4.3.49 and 4.3.50 for the transistor using the modeling techniques previously discussed in
section 4.3.1.3.3 and the equivalent nonlinear model shown in Figure 4.3.48. From the
154
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static I-V curves, the transconductance and output conductance are derived and plotted
versus the drain-to-source (V ^ ) and gate-to-source (VgS) voltages as shown in Figures
4.3.51 - 4.3.54. These plots graphically display the nonlinearity o f the transconductance
and output conductance of the HEMT transistor as functions of the dc bias voltages. As
noticed by these plots, these elements show varying degrees of nonlinearity which are
dependent on the drain-to-source (V ^ ) and gate-to-source (VgS) voltages bias. The
exploitation of these nonlinearities with respect to the optimum bias conditions will be
discussed on the following section.
C
G a te
L
R
9
g
• — |V |’1-------VSAS-
He
Drai
R
D
ds ^ k Cds
V
ds
Ls
S o u rc e
Figure 43.48 HEMT/PHEMT Nonlinear Equivalent Model
155
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0
0.5
1
1.5
2
2.5
3
Vds (V)
Figure 4.3.49 Modeled Drain Current of HEMT Transistor versus Drain-toSource Voltage
35 V ds=3 V
V ds=2.4 V
V ds=2 V
V ds= l V
-
0.6
-0.5
-0.4
-0.3
-
0.2
-
0.1
0
Vgs (V)
Figure 4.3.50 Modeled Drain Current of HEMT Transistor versus Gate-toSource Voltage
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
0
0.5
1
1.5
2
2.5
3
Vds (V)
Figure 4.3.51 Modeled Transconductance of HEMT Transistor versus Drainto-Source Voltage
80
40
V d s-3 V
20
V d s-2 V
V ds-1 V
-
0.6
-0.5
-0.4
-0.3
-
0.2
-
0.1
0
Vgs (V)
Figure 4.3.52 Modeled Transconductance of HEMT Transistor versus Gate-toSource Voltage
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
80 —
70 *
Rd (m S)
60
-
V gs*o v
40
30 -
10
’ Vgsss~0.4Vsy,
0
= =
0
Vgs=-0.6 v
0( .5
■>
1.5
2.5
3
V d s (v)
Figure 4.3.53 Modeled Output Conductance o f HEMT Transistor versus
Drain-to-Source Voltage
20
-
Vds- 0 .6 v
10
-
Vds=3 v
-
0.6
-0.5
-0.4
-0.3
-
0.2
-
0.1
0
V g s (v)
Figure 43.54 Modeled Output Conductance of HEMT Transistor versus Gate-toSource Voltage
158
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b)
PHEMT
In perusal of the available literature, very little attention has been given
addressing the nonlinearity of a PHEMT transistor. The following discussion is
dedicated to the discussion o f the nonlinear effects o f a PHEMT transistor, an
HP/Avantek ATF-36163 PHEMT which was previously modeled in section 4.3.1.3.4.
The intrinsic elements of the PHEMT transistor are shown in the nonlinear model of
Figure 4.3.48. Drawing on the results of Maas’ study on MESFET’s, the conclusion is
that the parasitic resistors and inductors o f the PHEMT will not vary significantly as
functions of applied bias and, thus, can be considered as insignificant contributors to the
harmonic generation in the PHEMT.
The diodes Dgs and Dgd are inherently nonlinear devices which can be represented
by the exponential current equation below (Equation 4.3.44) where V is either
or Vgd
depending on the diode considered
4.3.44
The importance of these diodes is in modeling the transistor under forward conduction
and under avalanche breakdown conditions. The diode current becomes quite large when
the applied voltage (Vgs or Vg(j) increases significantly. In typical multiplier applications,
due to risk of device failure, the transistors are not driven significantly hard into forward
conduction such that the diode current becomes significantly large.
159
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The assessment of the diode current contribution to the nonlinear effect of the
transistor can be considered mathematically. As an example, consider the simple diode
current {Ig*) through diode Dgs as shown below in Equation 4.3.45
-1
4.3.45
Using power series expansion on equation 4.3.45 gives
v*
V.
—
+
1— ( V^
_£L
2v ^/
Applying a sinusoidal waveform,
&
\
4.3.46
i/
=Vcos(ot to Equation 4.3.46 shows that the current
becomes
00
\
I.V { y
( V2
1
r V '
'
V
2 "
------ j. --- r + 1 COS QX +
coslox +
cos 3cot + ...
24F2
v, [AV,
J
This expression shows the diode current at the various frequency harmonics which can be
used to evaluate the magnitude of the diode current at the various harmonics. Inserting
some typical values in the Ig!Sequation (Equation 4.3.47) gives the following diode
current magnitudes at the various harmonics:
160
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Freq.
V=1 mV
Harmonic Igs (pA)
dc
fo
2fo
3fo
0.04
40
0.04
0.0027
V=25mV
Igs (pA)
250
1125
250
41.6
V=600mV V=2V
Igs (uA)
Igs (nA)
144
1750
144
576
1.6
64.1
1.6
21.3
Table 4.6 Diode Currents at Various Harmonics
This analysis shows the small current magnitudes (on the order of micro-amps or less)
generated though the diode at the various harmonics. These small values emphasize the
minimal contribution at the various harmonics o f the diode current to the total harmonic
generation in typical applications and indicate that the diode current does not contribute
as a major source of harmonic generation to the PHEMT.
The nonlinearity of the intrinsic gate-to-source and gate-to-drain capacitors of the
PHEMT will be analyzed using the capacitor models mentioned in section 4.3.1.3.4.2.
Figures 4.3.55 and 4.3.56 show the simulated Cgs and Cgd values for the HP/Avantek36163 PHEMT as functions of applied bias, respectively.
161
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
0.24 _
0.22 .
0.2 .
. Vgs-0 v
£7
c.
0.18
— — — Vgs=-0.2 v
V '
0.16 > .
\
-r-
»
J
- — - - VgS"-0.4 v
^
— . . . . . . . . . . . . . . . . . _____ . . . . . . . . . . . . . . . . . . . _____ _______ Vgs*- 0 5 v
0.U .
0.12
0.1
0.5
I
1.5
2
2.5
Vds (volts)
Figure 43.55 Simulated Gate-to-Source Capacitance (Cgs) of ATF-36163
PHEMT
0.22
.
S
0 . |9
\
°
0.18
■a
0.17
0.16
0
0.5
1
1.5
2
2.5
3
Vds (volt)
Figure 43.56 Simulated Gate-to-Drain Capacitance (C gd) of ATF-36163
PHEMT
162
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Focusing on C gs , Figure 4.3.55 shows that C g S varies nonlinearly from 0.12 pF to
0.22 pF, depending on the gate-to-source bias. The voltage swing of a sinusoidal gate-tosource voltage causes the magnitude of Q , to vary nonlinearly and. as discussed in
previous sections, exciting a nonlinear device with a sinusoidal ac signal generates a
frequency spectrum. In the present case, applying a sinusoidal gate-to-source voltage
across C g s causes C gs to be a contributor to the nonlinearity o f the PHEMT. With regards
to
C gd,
Figure 4.3.56 shows interesting results. For
> 1 volt,
C gej
in the circuit model
can be replaced by a fixed, constant of approximately 0.176 pF. This indicates that C g(j is
not varying nonlinearly and, theoretically, does not contribute to the nonlinearity of the
PHEMT for
> 1 volt. For the region Vds < 1 volt, Cgd begins to vary nonlinearly with
its magnitude depending on the ac voltage swing of Vgs. The greatest variation occurs for
Vds ^ 0.4 volts.
It was established in previous sections that the nonlinearity o f the drain-to-source
current contributes to the nonlinearity of the MESFET through its clipping effects. This
phenomenon is also present in PHEMT transistors. Exciting the gate junction with a
large waveform signal causes the transistor’s current to clip when the device reaches
pinch-off or forward conduction. Conversely, small ac signals applied to the gate which
are not sufficiently large do not cause the transistor to reach pinch-off of forward
conduction and, thus, will not contribute to the nonlinearity o f the PHEMT through
clipping. The nonlinearity o f the drain-to-source current also contributes to the
nonlinearity of the PHEMT through other means. This additional nonlinearity is
exhibited through the transconductance and output resistance. The transconductance and
output resistance are derivatives o f the drain-to-source current with respect to Vgs and
163
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Vgd, respectively, and are thus interrelated to the nonlinear characteristic of Ids- Through
this venue, the transconductance and output resistance contributes to the nonlinearity of
the PHEMT.
As an additional analysis, consider the typical measured data for the
transconductance and output resistance o f a PHEMT as shown below in Tables 4.7 and
4.8 (this data was obtained from similar measurements shown in Figure 4.3.34 and
4.3.41). As an example, consider biasing the PHEMT at Vgs—0.3 volts, Vds=2 volts and
with enough ac voltage swing to swing the input signal 0.6 volts peak-to-peak (equivalent
to a -0.46 dBm input power). As seen in this data, this input voltage swing causes the
transconductance to vary nonlinearly from 9.6 mS at pinch-off to 60.2 mS at Vgs=0 volts.
A similar effect in observed in the output resistance in that its magnitude swings from
1092 ohms to 204 ohms at these same bias points. A significant outcome is observed
from this simple analysis. The transconductance and output resistance can not be
replaced by fixed constants, as in the case of Cg</(for V<js > 1 volt), for they vary
nonlinearly and thus become contributors to the nonlinearity of the PHEMT.
Vds
3
2.5
2
1.5
1
0.5
Vgs=0 v Vgs=-0.3 v Vgs=-0.6 v
51.5
21.2
75.5
53.9
51.9
14.2
60.2
50.5
9.6
5.4
60.6
52.7
58.5
45.3
3
48.1
0.86
33.6
Table 4.7 Measured Transconductance (mS) of PHEMT
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Vds
3
2.5
2
1.5
1
Vgs=0 v Vgs=-0.3 v Vgs=-0.6
117.1
379.9
145.3
245.1
271.7
710.2
334.4
1092.4
204.9
287.4
238.9
2406.2
211.9
374.8
4212.3
Table 4.8 Measured Output Resistance (ohms) of PHEMT
Summarizing, the nonlinear intrinsic parameters o f the PHEMT have been
discussed. The parameters contributing to the nonlinear behavior of the PHEMT are the
diodes (Dgs and Dgej), drain-to-source current clipping, transconductance, output
resistance, and the capacitors (Cgs and Cgej). The simple diode current analysis shows that
under typical operation, the diode currents are not major contributors to the PHEMT
nonlinearity. The simulated capacitance data o f Figures 4.3.55 and 4.3.56 indicate that
for
> 1 volt, which is typical operation for frequency multipliers, Cgd is not a major
contributor to the nonlinearity of the PHEMT as well. This permits the conclusion that
the major contributors to the nonlinearity o f the PHEMT transistor as indicated by this
study are 1) the clipping effect of the drain-to-source current 2) the gate-to-source
capacitance (Cgs) and 3) the transconductance and output resistance as they are
interrelated to the nonlinearity of the drain-to-source current.
165
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433
Nonlinearities Valuable for Frequency Multiplication
4.3.3.1
Introduction
The quantification o f the nonlinearities was presented in the preceeding sections
in a general case. This section delineates the nonlinearities valuable for frequency
multipication with a specific emphasis on active nonlinear devices used in the designing
o f active frequency multipliers. The choices for optimum bias conditions and general
impedances required for optimum performance are detailed.
4.3.3.2
Optimum Bias Selection
Golio [2] has noted that the drain-to-source current (Ids) contributes to the
nonlinear behavior of the HEMT transistor. In this accord, static I-V curves representing
the drain-to-source current are utilized to characterize two dominant nonlinear circuit
elements identified in section 4.3.2: the transconductance (gm) and the output
conductance
(g d s )-
These parameters plotted versus the drain-to-source ( Vds) ^ d gate-to-
source ( VgS) voltages as shown in Figures 4.3.49 - 4.3.54 show the nonlinearity of the
elements displayed as a function o f the dc bias voltages.
For the class of multipliers under consideration, the nonlinear behavior of the
drain-to-source current ( I d s ) produces harmonic generation through its clipping effect
[32,51]. In the case of harmonic generation, the conclusion has been advanced that
optimum harmonic generation occurs for either VgS = 0 or VgS = Vp [50,51,55,80]. If the
FET/HEMT is biased at VgS = 0, the input voltage waveform appearing across the gateto-source capacitance (CgS) is clipped and will be half-wave rectified due to the
conduction cycles experienced by the gate-to-source diode. This rectified waveform is
166
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transferred to Ids through the device’s transfer properties as reflected by the analytical
relation between Ids
[8] as shown in equations 4.3.6 and 4.3.7. When the device
is biased at the pinch-off voltage (VgS = Vp), however, the input voltage at the gate
causes the FET to turn on during the positive half-cycle of the input voltage and the
output voltage again becomes a half-wave rectified waveform. When the gate voltage is
biased between 0 volts and pinch-off (0 > VgS > Vp), and the input voltage swing is large
enough to cause clipping on both ends, the output current at the drain will resemble a
square wave. If the square wave is symmetrical, the second harmonic component will be
small but the third harmonic is large allowing frequency tripling [50].
It has been shown that rich harmonic generation is shown to result for Class A and
Class B operation of the transistor [50,51]. Class A operation occurs for Vgs=0 v and
causes drain current (Ids) rectification when the gate diode swings into forward
conduction. Class B operation occurs for vg s ~ vp, where Vp is the pinch-off voltage, and
causes the drain current to clip when the gate voltage swings below pinch-off. Dow and
Camargo state that Class A FET multipliers provide good multiplication gain and poor
DC to RF efficiency while Class B FET multipliers have poor multiplication gain and
good DC to RF efficiency.
Using the DC-to-RF efficiency equation given in Section 4.2 in equation 4.2.4,
the efficiency for typical HEMT frequency doublers simulated in section 4.5.2 of this
dissertation with vgs=vp and Vg s~ ° V’ respectively, can be computed. As an example,
evaluating various simulation data for Vg s=Vp , the DC-to-RF efficiency is 23.5 % and
for typical simulations for Vgs=0v, the DC-to-RF efficiency is 0.03 %. In each
167
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simulation the dc supply voltage ( Vfe) was 3 volts which causes the dc power for the
simulation with VgS=0 v to be considerable higher and. subsequently, reducing the DCto-RF efficiency. Usually, for Class A operation the device is biased at a lower V^s
voltage than the case presented here, thus, reducing the dc power and increasing the DCto-RF efficiency.
Focusing on the Fujitsu FHX35LG HEMT device, measured and modeled
measurements provide static I-V curves as shown in Figure 4.3.57. From this data,
measured and modeled transconductance and output conductance are derived. Figures
4.3.58 - 4.3.61 show the transconductance and output conductances plotted as functions
of the gate-to-source (VgS) and drain-to-source (Vfc) voltages. Recalling that the
optimum bias conditions are either FgS=0 or VgS=Vp , the HEMT transconductance and
output conductance plots o f Figures 4.3.58 - 4.3.61 show the nonlinear behavior of the
transconductance and output conductance at the optimum bias regions.
In Figures 4.3.58 and 4.3.60, oval circles representing the regions (Region I) of
optimum nonlinearity are indicated for vgs ~ 0 volts. These regions are identified as areas
where the nonlinear variation in the transconductance and output conductance is greatest.
In Figure 4.3.58, the variation in the transconductance is actually greatest for Vrfs <0.5
volts but in this area of operation the transistor does not supply appreciable gain thus
limiting its usefulness at these bias levels for significant conversion gains. For V^s > 1
volt, the transconductance tends to flatten with no significant variation for V ^ O volts.
This behavior is observed again in Figure 4.3.60 with the output conductance.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
40 0
Measured
Vgs= 0 v
S im ulated
<
E
Vgs= -0 3 v
■Mo
V gs= -0 5 v
V p = -0 7 v
00
00
0 5
10
20
1.5
30
2.5
V ds (V)
Figure 43.57 Measured and Simulated I-V Curves of FHX35LG HEMT Transistor
90 _
Region I
gm (mA/v)
Vgs=0 v
V gs=-0.3 v
40
M easured
30 .
S im ulated
V gs= -0.5 v
0
0 .5
1.5
2.5
3
V ds (v)
Figure 43.58 Measured and Simulated Transconductance of FHX35LG
169
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In Figures 4.3.59 and 4.3.61. regions (Region II) for optimum nonlinearity are
represented for vg s ~ vp ■ Again, areas where the nonlinear variation in the magnitudes of
the transconductance and output conductance is greatest are indicated by the oval circles.
In Figure 4.3.59, significant nonlinear variation in the transconductance is also seen in the
vicinity o f VgS— 0.3 volts. Operating in this vicinity is optimum for frequency
multipliers where the third harmonic (frequency tripier) is o f interest [50]. Biasing in this
vicinity with large voltage swings at the gate o f the FET causes the Ids waveform to clip
at both pinch-off and forward conduction and causes I d s to resemble a square wave,
which enhances the third harmonic frequency [50]. In Figure 4.3.59 significant variation
in the output conductance also occurs for VgS « 0 to - 0 .1 volts for lower Vds values (Vds
<0.6 volts). As mentioned previously, the gain o f the transistor diminishes significantly
in these bias areas thus causing the conversion gain o f the frequency multiplier to reduce
as well. From these curves the prominent nonlinearity regions for VgS=0 is Region I of
Figure 4.3.60 where gds is dominant and for Vg s=Vp, Region II of Figure 4.3.59 with gm
showing the dominant effect. Similar data for the PHEMT is shown in Figures 4.3.34 4.3.42.
170
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90
80
70
60
>
<
40
R egion II
Vds=2
M easured
Sim ulated
Vds=I .2 v
Q_
-0 6 0
-0 50
-0 40
- 0 .3 0
-
0.20
-0 10
0 00
VgS ( v )
Figure 4.3.59 Measured and Simulated Transconductance of FHX35LG
70
60
40
30
R eg io n I
Sim ulated
M easured
0
0 5
1.5
2
2.5
3
Vds (v)
Figure 43.60 Measured and Simulated Output Conductance o f FHX35LG
171
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:o
Vds=0 6 v
M easu red
S im ulated
V ds=l 2 v
R eg io n II
•0 6
•0 5
■0.4
■0 1
•0 3
V g s (v)
Figure 43.61 Measured and Simulated Output Conductance of FHX35LG
172
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4 3 .4
Q uantification of D etrim ental Parasitics
4.3.4.1
Definition of the parasitics
The equivalent circuit topology for the nonlinear FET transistor as given in Figure
4.3.1 includes the parasitic elements (Ls, Lg, Lj, Rs, Rd, and Rg). These parasitics arise
from the fabrication process in the development of semiconductor transistors and
influence the performance of the transistor and. thus, warrants inclusion into the
equivalent circuit model. The parasitic inductors (I* Lg, and Ld) primarily represents the
inductance associated with the metal contact pads deposited on the active channel layer
of the FET. The source and drain parasitic resistors (R, and Rd) represent the contact
resistance of the ohmic contacts underneath the metal contact pads and any bulk
resistance leading up to the active channel and the gate parasitic resistance (Rg) represents
the metalization resistance of the gate Schottky contact [2].
4.3.4.2
Description of parasitic effects
As described in section 4.3.1.3.4, the parasitic resistors produce IR (voltage)
drops which causes the internal gate-to-source and drain-to- source voltages to be
different from the terminal (external) voltages (Vgsland V^J) as shown in equations
4.3.23a and 4.3.23b and stated again in equations 4.3.48 and 4.3.49 below. Equations
4.3.48 and 4.3.49 show the relationship between the internal and external voltages as
functions o f the parasitic resistances. The voltage drops shown in these equations
produced by these parasitics degrade the drain current o f the FET.
(4.3.48)
173
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(4.3.49)
Long and Butner [3] state that the parasitic resistors cause a similar effect on the
transconductance o f the FET as well. Defining the external transconductance available
outside the device as gme and the intrinsic (internal) transconductance as gm„ Long and
Butner relate the terminal (external) transconductance to the internal transconductance as
shown below in Equation 4.3.50. As the source resistance increases in this equation, the
external transconductance decreases which is an undesirable affect.
=m,
r
1
v 1+ gmiR J
(4.3.50)
These results demonstrate the effect on the parasitic resistances on the performance of the
FET. The internal gate-to-source and drain-to-source voltages are reduced and therefore
degradation in 7* and gm is observed.
Applications requiring low noise and high gain are also affected by the parasitic
elements. The gate parasitic resistor (Rg) increases the noise figure of the FET which is
critical in the design o f low noise amplifiers. In high gain applications, the parasitic
inductors reduce the high frequency gain o f the transistor. As frequency increases the
impedance presented by the inductors (|Z | = coL) increases and causes the gain to roll-off.
For the reasons mentioned above, optimum FET performance is obtained when the
parasitic elements are m in im ized. Efforts are made in the design and layout of the
transistor to m inim ize the parasitic elements.
174
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4.3.5
O p tim u m Bias Selection R eferencing H arm onic Term inations
4.3.5.1
Introduction
A primary factor affecting optimum performance o f microwave multipliers
employing nonlinear devices is the proper termination o f the fundamental and other
harmonic frequency components with regards to bias selection. This section presents a
quantitative analysis leading to the assessment of optimum terminating impedances in the
design o f active frequency multipliers with special attention given to harmonics other
than those desired. The analysis includes computer modeled HEMT data and supporting
measured data for corresponding circuit realizations. Circuit designs are presented
utilizing HEMT transistors as the active element to verify modeled results. Based on
available literature, the results demonstrate, for the first time, the quantitative effects of
harmonic termination on active multiplier conversion gain and fundamental and higher
harmonic suppression. An experimental design, which will be discussed in section 4.5,
reveals an improvement in multiplier gain of 77% over the conventional approach and
data is presented which quantitatively illustrates the advantages of impedance termination
considerations under optimal bias conditions.
4.3.5.2
Background and motivation
Numerous techniques exist for realization o f frequency multipliers. At radio
frequencies these techniques typically employ a nonlinear device to generate the desired
frequency multiple. In the design of passive multipliers, the nonlinear element is typically
a varactor diode. In the active case, the nonlinear element typically includes any of
several transistor classes such as BJT, FET, etc.
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In many frequency multiplier design approaches, the operating performance is
improved by the proper selection o f input and output circuit terminating impedances at
the fundamental and harmonic frequencies [44-48,62,98]. In the literature there is
apparently little substantive in-depth quantitative coverage o f this topic with supporting
modeled and measured data for either BJT or FET family realizations [32.39,52,56-63].
In the case of HEMT multipliers, coverage of this topic with supporting data is
nonexistent. Stancliff [44] and Gilmore [45] state that in order to optimize the response of
the FET multiplier, the optimum output load at the fundamental frequency is an open
circuit shifted by the conjugate o f the output capacitance o f the FET, but they do not
discuss mechanisms or regions. Rauscher [46] has performed a detailed study o f doubler
performance based on the fundamental frequency drive level, the device output
terminating impedance at the fundamental frequency, and the device input terminating
impedance at the second harmonic frequency. He concluded that the optimal output load
at the fundamental frequency was a short-circuited stub at an optimal distance from the
FET drain. The excellent study performed by Rauscher can be strengthened. The FET
model used in Rauscher’s study used approximations and only simulated data was
employed in the conclusion on output termination effects. An experimental circuit built
by Rauscher based on his analysis provided responses which required trimming and
tuning screws to approximate simulations. In pursuit o f optimal performance, it is
important that the analysis contain both simulated and measured data. Measured results
show the practicality of the designs and the accuracy o f the models which contain
approximations. Camargo [47,51,55], who appears to have performed the most in-depth
research in this area, concluded that optimum MESFET doubler operation is obtained
176
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when the drain is terminated at the fundamental frequency by a purely reactive circuit
which resonates the transistor’s output capacitance, while Borg [48] suggests that the
optimum terminating impedance for a bipolar multiplier is a short circuit at the
fundamental frequency. Many authors, however, do not give substantial quantitative
attention to regions of nonlinearity, terminating impedance, or spectral purity.
This section presents a quantitative analysis of the optimization of active
multiplier conversion gain and spectral purity as governed by fundamental and harmonic
terminating impedances and regions o f nonlinearity. It is believed that access to this
quantitative information will be o f use for designers o f future circuits. HEMT transistors
are employed to represent the class o f nonlinear element to illustrate the approach. The
optimum terminating impedances are determined for the input and output ports of the
active device utilizing a recent nonlinear circuit model for HEMT transistors. This is in
marked contrast with earlier studies which used approximations in the simulated
performance predictions [32,45,46,51]. In the nonlinear model used by Rauscher [46], for
example, fixed values for the gate-to-source capacitance (CgS) and gate-to-drain
capacitance (C gj) were used. In the simulation process, he has assumed, for higher
harmonic matching conditions, that the input and output terminating impedances are zero
for third-order and higher harmonics. The nonlinear model employed by Camargo [51]
uses fixed values for all elements except the transconductance (gm) and output
conductance igrf), and according to the author, does not employ gate-to-drain capacitance
(,Cgd> nonlinearity. The results presented in this section incorporate dependencies
between the input and output harmonic terminating impedances which are not found in
preceding studies. For the multipliers examined in this section, these impedances include
177
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terminations at the fundamental, second harmonic, and third harmonic frequencies.
Measured data are presented which validate the practicality o f the designs and the
accuracy o f the simulations.
4.3.5.3
Nonlinear model
An accurate nonlinear circuit model is required for the assessment of optimum
terminating impedances in the design of active frequency multipliers. The equivalent
circuit model allows supporting simulated data to accompany any measured data which
further verify the results. With reference to section 4.3.1, an accurate nonlinear circuit
model development was presented. Specifically, an accurate nonlinear model was
developed for the Fujitsu FHX35LG HEMT which will be referenced at this juncture for
analyzing bias selection with regard to harmonic terminations.
The basic nonlinear model of the Fujitsu FHX35LG HEMT employed in this
analysis is shown in Figure 4.3.1 (case parasitics are included in the model but not shown
in the figure). Static I-V curves for this HEMT, obtained from the model of Figure 1 and
laboratory measurements (See Figure 4.3.57), as noted in sections 4.3.2 and 4.3.4, are
employed to characterize two dominant circuit element nonlinearities: transconductance
(gm) and the output conductance (gj). These parameters (modeled and measured), which
were derived from the above sources, are plotted versus the drain-to-source ( P ^ ) and
gate-to-source iYgS) voltages shown in Figures 4.3.57-4.3.61. These plots graphically
display the nonlinearity o f the corresponding HEMT elements as a function o f the dc bias
voltages. This is further explored in the following paragraphs.
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For the class o f multipliers under consideration, the nonlinear behavior of the
drain-to-source current (7 ^ ) produces harmonic generation through its clipping effect
[32,51]. In the case o f harmonic generation, the conclusion has been advanced that
optimum harmonic generation occurs for either VgS = 0 or VgS = Vp [49,51]. If the FET
is biased at VgS = 0 , the input voltage waveform appearing across the gate-to-source
capacitance (CgS) is clipped and will be half-wave rectified due to the conduction cycles
experienced by the gate-to-source diode. This rectified waveform is transferred to 7 ^
through the device’s transfer properties as reflected by the analytical relation between 1,^
and Vgy When the device is biased at the pinchoff voltage (VgS = Vp), however, the
input voltage at the gate causes the FET to turn on during the positive half-cycle o f the
input voltage and the output voltage again becomes a half-wave rectified waveform.
When the gate voltage is biased between 0 volts and the pinchoff voltage (0 > VgS > Vp),
and the input voltage swing is large enough to cause clipping on both ends, the output
current at the drain will resemble a square wave. If the square wave is symmetrical, the
second harmonic component will be small but the third harmonic is large allowing
frequency tripling [50].
In this analysis, high efficiency harmonic generation is shown to result for Class
A and Class B operation o f the HEMT. Class A operation occurs for VgS ~0 and causes
drain current (7^) rectification when the gate diode swings into forward conduction.
Class B operation occurs for VgS = Vp and causes the drain current to clip when the gate
voltage swings below pinch-off. It has been stated in some previous studies that Class A
FET multipliers provide good multiplication gain and poor DC to RF efficiency while
179
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Class B FET multipliers have poor multiplication gain and good DC to RF efficiency
[50,52,54]. The conclusions for the HEMT multiplier are presented quantitatively in
section 4.3.5.4.
Utilizing the HEMT transconductance and output conductance plots o f Figures
4.3.57-4.3.61, the prominent nonlinear regions for the optimum dc bias points (either
VgS = 0 or VgS = Vp) were identified in sections 4.3.2 and 4.3.4. From these curves the
prominent nonlinear regions for VgS ^ 0 are Region I of Figure 4.3.58 where g^ is
dominant and for Vgs = Vp , Region II o f Figure 4.3.57 with gm showing the dominant
effect. In the absence of embedding circuitry constraints, a preliminary conclusion on
optimal HEMT multiplier terminating impedances may be drawn at this juncture. If
fundamental frequency load lines are constructed for these regions, it is seen that Region
I requires an open-circuit impedance which allows a maximum
voltage swing and
Region II requires a short-circuit impedance which allows a maximum I^s current swing.
Using the static HEMT I-V curves, fundamental frequency load lines may be constructed
to qualitatively illustrate the optimum terminating load impedance for the fundamental
frequency signal as shown in Figures 4.3.60a and 4.3.60b. Figure 4.3.60a shows the
fundamental load line analysis for Region I ( Vgs=0). This form o f analysis indicates that
the optimum impedance for Region I ( VgS = 0) is an open-circuit impedance which
allows a maximum
voltage swing. Similarly, Figure 4.3.60b shows the fundamental
load line analysis for Region II (VgS = Vp) and indicates that the optimum impedance is a
short-circuit impedance which allows a maximum 1^ current swing [98]. These
qualitative assertions will be substantiated quantitatively in the ensuing discussion.
180
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The HEMT is a square law device which cannot generate harmonic components
o f just any order. This device, operated entirely in its square-Iaw region, can be used for
frequency doubling, but will produce a third harmonic frequency if the second harmonic
output signal feeds back to the input and mixes in the device with the input fundamental
signal [45]. As an example, consider the HEMT with the drain-to-source current for
Vgs ~
rePresented 35 [2]
I d s = P ( V g s - V p ) 2 f(V ds)
Allowing the input voltage to consist of the input fundamental signal and the second
harmonic reflected back to the input of the device:
Vgs = A | cos<D0t + A2 cos(2to0t + 0)
(4.3.52)
where A j is the amplitude o f the fundamental signal, A 2 is the amplitude of the reflected
second harmonic, co0 is the fundamental frequency, and
6
is the phase angle of the
reflected second harmonic. Utilizing equation 4.3.52 in the expression for Ids reveals
that frequency components are obtained at dc, (Oq, 2 (0 ^ 3co0 and 4co0, and the component
at 2 co0 can be enhanced or degraded by the reflected signal.
181
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SO ohm termination
( >pen circuit termination
out
50 ohm termination
Open circuit termination
t
Figure 43.60a Fundamental Load Line Analysis for Region I (F p =tf v)
182
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i L
Short circuit termination
V,
Vin
Figure 4.3.60b Load Line Analysis for Region II (Vgs=Vp)
183
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4.3.5.4
Computational Multiplier Design Referencing Harmonic Terminations
The above analysis provides motivation for development of an optimal design
approach. Toward this end, a specific illustrative multiplier design is employed as a
vehicle. The basic topology of the frequency multiplier utilized is illustrated in Figure
4.3.61. In this configuration, SCj, i = 1, N and O C j;j = I, M represent short-circuit and
open circuit terminating impedances, respectively, for the multiplier input network at the
respective frequencies. Similarly, SCfc k = I, O and O Q ; I = I, P represent short and
open-circuit terminating impedances for the multiplier output network. An infinite
number of circuit realizations exist which conform to the configuration o f Figure 4.3.61.
This provides the motivation for construction o f a matrix o f various circuit configurations
as illustrated in Table 4.9 which displays various harmonic terminating impedances on
the input and output ports o f the multiplier realization depicted in Figure 4.3.61. Tables
have been constructed for multiplier operation (up to the third harmonic) utilizing the
precision HEMT computer model with case parasitics which were discussed earlier. With
reference to Table 4.9, the left-hand vertical column represents various impedance
terminations of the input network at the fundamental, second harmonic, and third
harmonic frequencies. The top horizontal row represents various impedances of the
output network at the fundamental, second harmonic, and third harmonic frequencies.
To assess performance under various load terminations several load configurations
were analyzed. Based on previous discussions, fundamental and harmonic loads o f
interest fall into several categories: these loads may be short-circuited, open-circuited,
matched or 50 ohms.
184
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As a first case, the options shown in Tables 4.9 and 4.10 were selected. Since only
50 ohms, short and open loads are used, this choice o f terminations would appear to
provide a concrete basis for assessing the effects o f a variety o f other input and output
harmonic load conditions. Table 4.9 illustrates the conversion gains obtained employing
the FHX35LG HEMT utilizing a Harmonic Balance program with input and output
networks synthesized with lumped elements to realize the indicated harmonic
terminations w ith/^ = 3 GHz. (Figure 4.3.62 is a plot o f the reflection coefficient and
transmission magnitude for the input network which realizes row 2 consisting of an
impedance Z(f) which is 50 ohms @ f0, short circuit @ 2 f 0, and 50 ohms @ 3 fQ.) The
HEMT in this table is biased at pinchoff Vgs = Vp and driven with 0 dBm at the gate
terminal (Region II). This table is presented as a basis with which to measure the
quantitative impact o f a variety o f terminations on multiplier conversion gain. The
numbers to the right o f each entry in the table represent the powers obtained at respective
harmonics. It is instructive to consider a typical entry of interest in this table. The entry
located in the second row and second column, for example, shows that a conversion gain
of 1.5 dB is obtained if the input network terminates the fundamental f Q and third
harmonic 3fQ in 50 ohms while the second harmonic 2fQ is short-circuited. The output
network for this entry terminates the fundamental in a short circuit and all other
harmonics in 50 ohms. Several authors [46,51,52,55] have reported that the input network
should terminate the second harmonic in a short circuit. For lumped input circuit
realizations, however, this table reveals that this provides a 1.5 dB improvement over a
50 ohm or an open circuit termination at 2f0 (row 1, column 2 and row 5, column 2
respectively). While the conversion gains represented in this table is not large and the dB
185
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
values do not show great variation, several trends are seen to emerge and subsequent
results will substantiate their implications. In particular, the impact of input network
terminations show from the data in rows 2 and 3, that for doubler operation, a short
circuit termination at 2f Q provides the best conversion gain in all cases considered.
Output Network
Input Network
oc.
sc,
oc.
OC,
sc,
oc.
HEMT
SC,
Figure 4.3.61 Frequency Multiplier Realization
186
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
sc,
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Lumped Components
V g f-4 7 V
Output Nctmrk
m sx
O p e n d ra it0 To
SOohm0 2 b
o p « d ra ft 0 1 b
ihoet cmutt 0 To
SOohm 0 2 b
open d ra ft 0 1 b
opundrcstt 0 To
50 ohm 0 2 b
]Oohm 0 ) b
s io lu o ^ lb
SOobta0 2 b
opai d r a f t 0 1 b
V di-lV
hputNotumk
SOohm 0 lo
SOohm 0 2 b
50 ohm 0 1 b
M ih iS Ib
SOotuufl 2fo
5 O o tu u 0 1 b
Output 9om t (dBm)
Output 9 o w (dBm)
Output ^ o w ^ fitn )
Output f e w (dBm)
Output r o w (dBm)
Output h m (dBn)
5.9
900b
9001b
415
•71.2
•661
9 o 0 lb
9o0b
-71
9o0b
5.W
9o0b
•12
9002b
4.7
90021b
90021b
02
0 9002b
•1
ro ^ U o
9002b
•0.9
•94
9001b
•107
90011b
•715
•17.1
90011b
-14
Po0 llb
-14.7
9001b
9 o 0 ib
fwr-0 dBm
■ hoftdnuH gfe
3O ohm02fb
SOohm 0 1 b
9o0b
9o02b
9o01fo
465
•14
472
6.1
9o0b
9002b
9o01b
•729
9o0b
9002b
9o01b
46.1
4.5
47.7
461
41
•97.7
9O0B>
9o02tb
9001b
415
4.9
•109.6
900b
9o02b
9o01b
6.2
02
• 11.1
900b
9002b
9001b
415
•1.7
•106.6
9o0b
9002b
9001b
5.9
•12
1062
9001b
90021b
9001b
•94.5
900b
9002b
9001b
9001b
90021b
90011b
•71.1
0.1
•104
9o0b
9002b
9001b
416
•1
•109
900b
9002b
9 o 0 )b
•l.l
46
46.5
-l.l
•20
9001b
90021b
9o0!lb
•71
0.1
•104
900b
9002b
9o01b
46.5
4.9
•101
900b
9002b
9o01b
46.5
4.9
•17
9001b
9o02ft>
90011b
-71
0.4
-102
9o0b
9002b
9001b
415
4.7
•105
900b
9002b
9001b
9 b 0 lb
9o02lb
90011b
9o0b
9002/6
9 e 0 ifo
6
- 1.2
•11.4
9o0b
9o02b
9001b
-719
1.5
• 10.6
h> 0 fc
9e02b
ro 0 i(b
46.1
4.1
• 172
9001b
90021b
90011b
•711
900b
9o01b
9 a 0 ib
5.9
-12
-17.1
To 0 1 b
9o02/6
re 0 1 ft>
-71.2
• 1.1
-16.6
r o 0 fc
90021b
90011b
46.5
•712
•15.1
9 o 0 lb
90021b
90011b
JO o tm 0 b
c p tc M S U b
9o0b
9002b
9 e 0 ib
6.1
-1
• 15.9
r e 0 (b
9o02fo
ro 0 iib
-71
0
•15.1
9001b
9O02«b
90011b
•666
• 1.2
-21.2
SOotuii0 fo
e p m d ra ik 0 2 b
open dyouft 0 3fb
9o0b
9o02b
9o 0 ifo
6.1
4 .9
-15.7
9 o 0 fo
9o02b
9o01b
-71
0
-15.1
9o0b
9002b
90011b
5O okot0fo
3OoJua02fo
9o0b
r « 9 jfo
9 o 0 ib
6
41
• 141
9o0b
ra 0 2 fo
ro 0 iro
•71.1
0.1
•11.6
9o0b
90021b
90011b
SOotuu0 fo
JOotim 0 2fo
•712
4.2
44
•92
46.1
4.1
• 172
JO d a fb
(ton d n u it 0 2fo
12
0
<"»
fo ^ fo
9o02b
9o01fo
•106
-III
900b
9e02b
ro 0 iib
6.1
02
•11
1.6
419
1.1
49.1
•12
900b
90021b
9001fb
46.1
02
SOoluii0 2 b
•hott d ra ft 0 1 b
5.9
4.7
•104
900b
9002b
9001b
-719
1.5
- 10.6
9 o 0 fo
9o02b
9 o 0 ib
50 ohm 0 2 b
moil dram 0 1 b
9o0b
9002b
9o01b
900b
9002b
9001b
•711
9o0b
1002 b
9001b
JOekmQ fb
■fcotl drcuit 0 2fb
SOotun0 1 b
5O obo02b
thort d ra ft 0 1 b
0.7
• 100
1.2
41.1
9 0 0 to
9002b
9o01b
-719
41.1
9 o 0 fo
9o02b
9o01fo
-106
9o0b
IO0 2 b
9001b
•71.2
4.1
44.1
9o0b
9o02b
9o01b
467
•2.7
40.1
9o0b
9002b
9001b
6.1
41
•105
9o0b
9o02b
9o01fo
•71
42
•96 1
9o0b
9002b
9o01b
465
100.4
•1.2
462
900b
9002b
9001b
6.1
4.7
•101
9 o 0 fo
9002b
9001b
-71
42
•96
900b
9a02b
9001b
•665
•1.4
•991
6
• 1.1
44.4
9e0b
9002b
9 o 0 !b
6
4.5
•101
9o0b
9o02b
9001b
•71
42
41.9
9 o 0 fo
9o02To
9o01b
465
•1.4
•96 9
6.1
6.1
62
0.7
100.6
5.9
•11
1.2
Table 4.9 Doubler Simulations with Lumped Components (V g s= -0 .7 volts, P in = 0 d B m )
• IS
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
VgrOV
PbrOdBm
Vdb-lV
Input Nowort
90ohm0 *
50ohm0 2 *
90ohm0 1 *
Output Netwurk
H ota^lb
90ohm0 2 *
50ohm0 9 *
Output Power(dBm)
it i
PoO*
roQlfo
•101
.119
pt>oi*
ihondreuk0 *
opendrank0 b>
Jibht^fo
optndraJl^fb
■ W td n lljh
thotl drcuit 0 *
90bhmO*
50ohm0 2 *
90ohm0 2 *
90dMO2*
50ohm0 2*
90ohm071b
90dun 0 7 *
90ohm0 2 *
50ohm0 lib
90ohm091b
opattlrak 0 91b
opundrakO 9*
thondrank0 1 *
ihort drank0 1 *
bpatdrallOl*
Output f*wer(dBm)
Output rower (dBm)
Output font (dim)
Output bower(dBm)
Output bower(dBm)
Output Power (dBm)
Output Power(dBm)
-M2 r o o *
-4X1 P * 0 *
•42 PbO*
1X9 PbO*
Ml
•442 PbO*
12.9 PbO*
PoO*
-X4 PoOTlb
•10.2 1*01*
•10 1*02*
-10.4 PbOl*
•1 PbOT*
•10.9 PoOHb
•111
PoOT*
•91 PoOl*
•91 PbOl*
•44.1 PbOl*
-101 PbOl*
Pogirb
•10.7 1*09lb
•7.1 1*09*
41.1
opendrauit 0 *
50ohm0 2 *
thortdraukOl*
Output Power (dBm)
421
1*0*
•22
PoOT*
499
PoOl*
90ohm0 *
thondrorkO 2*
SOetan0Jfo
PoO*
1*01*
ro93fl>
11.4
• in
•14.1
1*0 lb
PoOl*
n g i*
-M
•14.7
•ll.l
r*0*
Poor*
rogi*
■*2.2
•1.4
•7.1
r*0*
PoOTlb
r<>0]fb
•44
•14.1
41.4
P»0*
1*07*
1*01*
; -42
•XI
•9X7
PbO*
PbOT*
PbOl*
1X4
-IM
•94.9
PbO *
PbOT*
PbOl*
1X9
•10.1
•101
PbO*
1*01*
1*01*
442
•19.1
4X2
PbO*
1*01*
PbOl*
42
•27
•191
90ohm0 *
rhondrarttO 2fo
that drank0 1 *
1* 0 *
PoOl*
poor*
12.4
-11.2
•ll.«
p*o*
r«02ib
PbOl*
M
-19.1
•I4.t
PoOlb
l*071b
r*Oi*
-42
•14
•9.9
PoO*
1*07*
PoOTlb
•44
•19.4
•109
1*0*
PbOl*
P*09*
•42
•XI
■94.1
PbO*
PbOT*
PbOl*
1X4
•10.9
4X7
PbO*
PbOT*
PbOl*
1X4
•ll.l
•109
PbO*
PbOl*
PbOl*
M.I
•111
41.1
PbO*
1*02*
PbOl*
424
•21
•71
90ohm0 *
90ohm01*
thettdraukOl*
1*0*1
1*02*
PoOl*
1X4
•10.2
•l*.l
ruOib
ruoifb
r«oiib
M.J
•11.2
•14.9
1*0 lb
i*OHb
1*09lb
•4X1
•1
•9.7
1*0*
PbOT*
p*ei*
M
•11.2
-17.1
PbO*
1*02*
1*01*
•4X1
•XI
•91.9
P*0* '
PbOT* '
PbOl*
1X9
•10.4
4X4
PbO*
PoOl*
PbOl*
1X4
•10
•109
PbO*
Po02*
PbOl*
44
•10.9
42.2
PbO*
PoOl*
PoOl*
421
•24
•71
90ohm0 *
opendreuk 0 2*
90ohm0 1 *
p*o*
1*02*
PoOl*
IXt
-9.1
-11.7
i* o fc
1*02*
roOifo
•Ml
•101
•10.1
PoO*
l*0Ub
PoOlIb
■42.1
•XI
•7.1
1*0*
PoOT*
1*09*
Ml
•10.1
-971
PbO*
PoOlfe
PbOl*
-4X1
•1.7
•9X4
PbO*
PbOT*
PbOl*
lit
4J
•94.4
PbO*
PbOT*
PbOl*
1X4
•9.2
•101
PbO*
PbOl*
PbOl*
44.1
• 107
41.9
PbO*
1*02*
PoOl*
411
•19
•194
»oh>eh
opendrank0 2*
opendrank0 9 *
poo*
PoOi*
reOlfo
IXt
•9.1
•11
1*0*
1*02*
r«0)ib
M
-101
4.7
1*0 lb
PoOTTo
PoOlfb
•42
•19
•7.1
PuO*
PoOT*
1*09*
M
-9.9
•949
1*0*
PbOl*
PbOl*
•4X1
•1.7
•91.4
1*0*
PbOT*
PbOl*
IXt
4J
•94.1
1*0*
PbOl*
PbOl*
124
4.2
•100
PoO*
1*02*
1*01*
M
-10.7
41.9
PoO*
1*02*
PoOl*
42
•II
•90 7
90ohm0 *
90ohm0 2 *
opendrank0 Ifo
1*0*)
PoOl*
roOJ*
12.9
-101
-III
i * 0 fc
ruoxib
rnOllb
M2
•10.1
•101
1*0 lb
l*OT!b
Pu09lb
-4X1
-22
-7.1
PbO*
PoOT*
1*09*
•441
•10.4
•941
1*0*
PbOl*
PbOl*
•4X1
•2
•91.4
PbO*
PbOT*
PbOl*
1X9
-141
-99.1
PbO*
PbOT*
PbOl*
1X9
4.9
•100
PbO*
PbOT*
PbOl*
M2
•111
42
PbO*
Po02fo
PbOl*
411
•2 1
•907
Table 4.10 Doubler Simulations with Lumped Components (V g s^O volts, P in = 0 d B m )
-10
_
as
3.
u
-20
.
-30 .
1
-40 .
I«
-50 :
S
-60 _
|S 2I|
|S l l |
-70 -80
2.50 3.00 3.50 4.00 4.50 5.00
5.50 6.00 6.50 7.00
7.50 8.00 8.50 9.00 9.50
Frequency (GHz)
Figure 4.3.62 Reflection and Transm ission M agnitude for Input Network (50 ohms
@fo , short circuit @ 2fo, and 50 ohms @ 3fo)
Furthermore, a perusal of output network termination responses show that a short
circuit a tf 0 provides the best performance using conversion gain as a basis.
Table 4.10 shows similar data when the HEMT is biased at Vgs - 0 (Region I).
This VgS value was chosen in accordance with our previous discussion on optimum bias
regions. While an important outcome o f the VgS = 0 table was typically lower
conversion gains in comparison with Table 4.9 where VgS = Vp, an even more significant
observation is the dramatic improvement (~12 dB) obtained by employing an open circuit
termination eXfQ in the output network, in contrast with a short circuit which was the
optimum case for Region II. Note that Table 4.9 predicts only a 1. 6 dB improvement for
the analogous comparison.
189
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Based on these results and the author's detailed studies for other cases, only results
will be presented for the specific case where the input network is short-circuited at 2f Q in
the ensuing discussion.
Table 4.11 presents the results obtained for Region II operation (VgS = Vp) when
the input network was synthesized to provide a matched load at the fundamental
frequency, f Q, and a short at 2fQ. In comparison with its counterpart in row 2 o f Table 4.9
which had a 50 ohm termination aty^, it is seen that, as expected, significant
improvements occur in conversion gains for all output network impedance terminations.
A perusal o f the values indicates that significant increases in conversion gain o f over 5
dB are typical in each case. Furthermore, the following quantitative results may be
observed for various output network terminations: (i) 3.0 dB better conversion gains are
obtained due to short circuiting as compared with open circuiting the fundamental (i.e.
8.0 vs. 5.0 dB) (ii) 1.5 dB better conversion gain will be obtained for a short circuit aty^
in comparison with a 50 ohm termination (notwithstanding the fact that the 50 ohm case
would require some form o f output circuit fundamental suppression) (iii) 1.2 dB of
additional conversion gain is obtained if the third harmonic is open circuited in contrast
with the frequently used short circuited third harmonic (8.6 vs 7.4 dB), and (iv) 3.8 dB
additional conversion gain is obtained over the case where an open circuit fundamental
and short circuit third harmonic output network are employed (i.e. 8.6 vs. 4.8 dB).
Table 4.12 presents the results obtained for region II operation when the output
network is synthesized to provide a matched load at the second harmonic {2f 0) versus the
previous cases where a simple 50 ohm load was employed. Based on these results, it can
be seen that for output network terminations where the fundamental has been short
190
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
circuited, an additional « 2 dB has been obtained over the results in Table 4.11 and
approximately 9 dB over Table 4.9 results.
Tables 4.13 and 4.14 display the results obtained utilizing microstrip line circuits
that were synthesized to provide shorted, open, and 50 ohm terminations at respective
fundamental and harmonic frequencies as employed in many traditional designs [32,4548,50-51,53-63]. Typical respective input and output network topologies used in
generating these tables are shown in Figure 4.3.63. Corresponding plots o f f i n / and f i 2i /
dB are shown in Figures 4.3.64 and 4.3.65 to illustrate the efficacy o f the networks in
achieving the desired performance. As explained above, all results are given for an input
network synthesized for 50 ohms at f Q, short circuit at 2fQ and 50 ohms at 3fQ.
o
-10
-20
-30
(S ill
-40
iS 2 l|
-50
-60
2.5
3
3.5
4
4.5
5
5.5
6
6.5
7
7.5
8
8.5
9
9.5
Frequency (GHz)
Figure 4.3.64 Reflection and Transmission Magnitude for Input Network (short
circuit @ 2fo)
191
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
M atch e d at Input
V g s--0 7 V
O u tp u t N etw ork
P in " 0 dB m
5 0 o h m ® fo
s h o rt c irc u it ® fo
o p e n c irc u it 3 fo
s h o rt circ u it ® fo
o p en circ u it ( § fo
SO o h m ® fo
50 o h m @ fo
sh o rt circ u it @ fo
V d s-JV
50 o h m ® 2fo
SO o h m ® 2 fo
50 o h m ® 2fo
50 oh m ® 2fo
50 o h m ® 2fo
50 oh m ® 2fo
9 0 o h m ® 2fo
50 o h m ® 2fo
50 o h m ® 2 fo
In p u t N e tw o rk
SO o h m @ J fo
SO o h m @ J fo
SO o h m ® J fo
o p en circ u it ® J fo
o p en circ u it @ J fo
s h o rt circ u it ® J fo
o p e n circuit ® I f o
sh o rt circ u it ® H o
s h o rt circ u it ® I f o
O u tp u t P o w er (d B m )
6 u tp u t P o w er (d B m )
O u tp u t P o w er (dB m )
O utput P ow er (d B m )
O utput P ow er (d B m )
O u tp u t P ow er (dB m )
o p en circ u it ® fo
O u tp u t P ow er (d B m )
O u tp u t P ow er (d B m )
6 u tp u l P o w er (d B m )
5 0 o h m ® fo
P o ® fo
596
P o ® fo
-217
P o ® fo
*210
P o ® fo
*215
P o ® fo
-208
P o ® fo
55
P o ® fo
4 1
P o ® fo
-216
P o ® fo
5 0 o h m 0 2 fo
P o ® 2 fo
-0 9
P o ® 2 fo
-0 3
P o ® 2 fo
-0 7
P o ® 2 fo
0 2
P o ® 2 fo
0 4
P o ® 2 fo
*3 9
P o ® 2 fo
0 3
P o ® 2 fo
*3 3
P o ® 2 fo
.4 2
50 o h m ® 3 fo
P o ® lf o
-14 7
P o ® 3 fo
.221
P o ® 3 fo
*231
P o ® 3 fo
-270
P o ® 3 fo
-270
P o ® 3 fo
-232
P o ® 3 fo
.2 3 7
P o ® 3 fo
-2 7 0
P » ® 3 fo
-270
O u tp u t P o w er (d B m )
O u tp u t P ow er (d B m )
O utput P o w er (dB m )
O utput P ow er (d B m )
O utput P ow er (dB m }
O u tp u t P ow er (d B m )
O u tp u t P ow er (d B m )
O u tp u t P ow er (d B m )
-209
O u tp u t P o w er (d B m )
M atch e d @ fo
P o ® fo
1)
P o @ fo
*65 7
Po ® fo
-62 3
P o ® fo
*65 7
P o ® fo
-62 5
P o ® fo
13
P o ® fo
13
P o ® fo
-6 5 6
P o ® fo
sh o rt c irc u it ® 2fo
P o ® 2 fo
6 5
P o ® 2 fo
8
P o ® 2 fo
5
P o ® 2 fo
86
P n ® 2 fo
5 2
P o ® 2 fo
61
P o ® 2 fo
6 9
P o ® 2 fo
74
P o ® 2 fo
4 8
5 4 o h m s ® 3fo
P o ® 3 fo
*6 7
P o ® 3 fo
-4 1
P o ® 3 fo
.7 9
P o ® 3 fo
-92 1
P o ® 3 fo
92 2
P o ® )fo
-87 6
P o ® 3 fo
94 9
P o ® 3 fo
.8 4 7
P o ® 3 fo
92 6
-62 2
Table 4.11 Doubler Simulations Matched on Input with Microstrip Transmission Lines (V g s= -0 .7 volts, P in= 0 d B m )
IS
M atch e d at In p u t a n d O u tp u t
V g s « ’0 7 V
O u tp u t N etw ork
P in - 0 dB m
SO ohm ® fo
s h o rt circ u it ® fo
o p en c irc u it ® fo
short circ u it
o p en circ u it ® fo
36 oh m s ® fo
37 o h m s ® fo
s h o rt circ u it ® fo
o p en circ u it ® fo
V d s -3 V
SO o hm ® 2fo
M atch e d ® 2fo
M atched ® 2fo
M atched ® 2fn
M atch e d ® 2fo
M atched ® 2fo
M atched ® 2fo
M atched ® 2fo
M atched ® 2 fo
In p u t N etw ork
5 0 o h m ® 3fo
85 o h m s ® Ifo
85 oh m s ® 3fo
o pen circ u it ® 3fo
o p e n circuit ® 3fo
short c i r c u i t® 3fo
o p en circ u it ® 3fo
sh o rt circ u it ® J fo
short c i r c u i t® J fo
O u tp u t P ow er (d B m )
O u tp u t P ow er (d B m )
O utput P o w er (d B m )
O utput P ow er (d B m )
O u tp u t P ow er (d B m )
O utput P ow er (d B m )
O u tp u t P ow er (d B m )
O u tp u t P ow er (d B m )
(fo
fo
O u tp u t P ow er (d B m )
M atch e d ® fo
P o ® fo
14 4
P o ® fo
70 2
P o @ fo
-61 9
P o ® fo
>70
P o ® fo
-61 5
P o ® fo
12 8
P o ® fo
125
P o ® fo
70
P o ® fo
s h o rt c irc u it ® 2 fo
P o ® 2 fo
6 4
P o ® 2 fo
101
P o ® 2 fo
4 7
P o ® 2 fo
10 4
P « @ 2 fo
5
P o ® 2 fo
9 1
P o ® 2 fo
7 3
P o ® 2 fo
9 5
P o ® 2 fo
5 1
54 o h m s ® 3fo
P o ® )fo
-2 9
P o ® !fo
P o ® 3 fo
16 2
P o ® Ifo
-89 5
P u ® )fo
99 |
Po® Ho
-95 1
P o ® J fo
.8 4 1
P o ® 3 fo
.9 6 7
P o ® 3 fo
MO)
8 1
Table 4.12 Doubler Simulations Matched on Input and Output with Microstrip Transmission Lines
(Vgs= -0 . 7 volts, P in= 0 d B m )
-6 0 6
Vgs*-0 7 v
Output Network
P u i-0 d B m
V d s -J V
SO o h m % fo
SO ohm @ 2fo
Input N etw ork
SO ohm % 2fo
open c ircu it rS) fo
SO ohm @ 2fo
sh o rt c ircu it 3 fo
62 o h m s (3 2fo
o p en circu it <3 fo
63 o h m s fS 2fo
4 9 o h m s <3 2fo
repeat sc @ Jfo
repeat o c
sh o rt c ircu it ( 3 Jfo
o p e n circu it r3 Jfo
o p en circu it <3 Jfo
sh o rt circuit 3 fo
SO ohm @ 3fo
3fo
27 o h m s >3 fo
O utput Pow er (d B m )
SO ohm % fo
SO ohm - 3 2fo
SO ohm i 3 3fo
Po 3 fo
Po<@2fo
P w 3 3 fo
O u tp u t P o w er (d B m )
O utput Pow er (dB m )
O utput P o w er (dB m )
O utput P ow er (dB m )
O u tp u t Pow er (dBm)
P o ifijfo
-17 3
5 96
Po % fo
-27 1
P o @ fo
-1 0 4
Po (3 fo
-25
Po (3 fo
4
P o f3 2 fo
04
-0 9
P iy 3 2 fo
06
Po@ 2fo
-O 9
Po<§2fo
-0 7
P o f3 2 fo
08
-14 7
P o O Jfo
-60 i
P o O Jfo
-36 2
P o fS Jfo
-52 9
P o r3 3 fo
-37 7
P o a S fo
-26 3
SO ohm (q fo
short c irc u it % 2fo
SO ohm <8f J fo
Po
fo
P w 3 2 fo
Po<33fo
10 7
4 3
-10 2
Po fat fo
-27 4
Pot§2fo
P w ilfo
54
-22 6
Po 3 fo
P « 3 2 fo
PcrfSJfo
-22
4 5
-21
P o i 3 fo
P t* § 2 fo
-1 9 9
77
P o r3 3 fo
-46 9
P o -3 fo
Po@ 2fo
P o f3 3 fo
-13 5
64
-61
Po 3 fo
P o 3 2 fo
P o (3 3 fo
9
72
-32
Table 4.13 Simulated Doubler Response with Microstrip Elements (Region II)
Vgs-o v
O u tp u t N etw ork
P in -0 dBm
SO ohm @ fo
SO ohm % 2fo
V d s-J V
Input N etw ork
SO ohm 3 fo
SO ohm % 2fo
SO ohm 3 3fo
SO ohm ( 3 fo
sh o rt circuit (3f 2fo
SO ohm (Si 3fo
sh o rt circuit <3 fo
SO ohm % 2fo
s h o rt circu it % fo
6 2 o h m s @ 2fo
o pen circu it @ fo
SO ohm @ 2fo
27 o h m s % fo
4 9 o h m s % 2fo
o p e n circuit (3 fo
63 o h m s (3 2fo
o p en circu it <3 Jfo
SO ohm @ Jfo
repeat o c @ Jfo
o p en c ircu it @ Jfo
repeat sc @ 3fo
s h o rt c ircu it (3 Jfo
O u tp u t P o w er (d B m )
O utput P o w er (dB m )
O u tp u t Pow er (dB m )
O utput Power (dB m )
O utput Pow er (dB m )
O utput P o w er (dB m )
P o @ fo
-2 2 9
Po '3 fo
-1 2 5
Po<3 fo
12 5
Po % fo
-20 2
Po<@ fo
-IS I
Po @ fo
111
P o (3 2 fo
-4
P ort|2fo
-10 1
Po@ 2fo
-1 1 4
P w g 2 fo
-10
Po @ 2 fo
-1 0 9
Po@ 2fo
-2 5
P o (3 3 fo
-49 J
P o (3 3 fo
-55 4
P o O Jfo
-13 9
P o O Jfo
-26 3
P o fS Jfo
-33 9
Po<33fo
-25 4
Po ( 3 fo
14 7
p o a fo
-is
Po t3 2 fo
Po t3 3 fo
-1 2 5
44
P0<32fo
Po(33fo
-13 1
-18 4
4
P o @ fo
Po<32fo
-14 4
18
P o (3 3 fo
-25 6
P o @ fo
Po @ 2 fo
P o f3 3 fo
-2 1 3
-10 4
-41
P o 3 fo
-111
Po*§2fo
P o i3 J fo
28
-52
P o 3 fo
Po (3 2 fo
P o 3 3 fo
Table 4.14 Simulated Doubler Response with Microstrip Elements (Region I)
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13 2
-10 6
-2 8
-10 >
cc
-20
V
3
e
a
oc
-30 .
ISUI
lS211
t
2.5
3
3.5
4
4.5
5
5.5
6
6.5
7
7.5
8
8.5
9
9.5
Frequency (GHz)
Figure 43.65 Reflection and Transm ission Magnitude fo r O utput Network
(short circuit @ fo)
With reference to Table 4.13 (Region II, VgS = Vp), a comparison of the effect of
the distributed input network (row 2, column 1) with a 50 ohm input network at f Q, 2fQl
and 3f0 (row 1, column 1) shows that 5.2 dB improvement in conversion gain
performance may be obtained by employing the distributed structure with a short circuit
at 2f0. Some additional conclusions obtained from a further perusal of this table are as
follows: (i) 8.6 dB conversion gain improvement may be obtained by providing a
distributed output network which is short circuited a t^ , and 3fQ as compared with 50
ohm input and output terminations (row 1, column 1 vs. row 2, column 4) (ii) with the
distributed input network terminated in a short circuit 1.3 dB improvement in conversion
gain may be obtained by short circuiting the output network s t f Q and 3f0 (column 4) as
compared with open circuits at 7^ and 3f0 (column 5) (iii) the difference in termination in
194
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the output network between open and short circuits at f Q is on the order of 1 dB. and (iv)
an additional 2.3 dB o f conversion gain is obtained by introducing an additional short
circuited stub at 3fQ.
Table 4.14 presents similar results for Region I (FgS *0) operation. Several
significant conclusions are evident from these results: (i) best performance is
considerably less (2.8 vs. 7.7 dB) than that for Region II operation (ii) Significant
conversion gain improvement is obtained when the output network is open circuited at f Q
in comparison with the short circuited condition (1.8 vs. -13.1 = 15 dB) (iii) 1 dB o f
conversion gain performance improvement is achieved by introducing an additional open
circuited stub at the third harmonic.
This topic will be revisited in section 4.5 in the discussion of active multiplier
design. Specific multiplier designs are illustrated demonstrating the efficacy of harmonic
terminations and optimum bias selection.
195
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4.4
Analysis T echnique an d Softw are
A significant amount o f the research work presented in this dissertation relies on
the capability of producing accurate computer simulations. Numerical methods for the
analysis o f nonlinear circuits are essential to microwave engineers. This section
discusses some analysis techniques used for simulating nonlinear circuits by microwave
engineers and the simulation process used in this dissertation for predicting the largesignal handling performance o f frequency multipliers.
4.4.1
Frequency-domain Technique (Power Series Analysis)
A simple frequency-domain technique used by microwave engineers for
determining the steady-state response of a nonlinear network excited by a sinusoidal
waveform is through power series analysis. In the power series analysis, the nonlinearity
o f the nonlinear element is expressed in polynomial form as a function of the input
excitation signal. Inserting the excitation signal into the polynomial gives an output
response in the frequency domain which readily express the harmonic amplitudes at the
various frequency harmonics.
As an example o f the power series analysis, assume that a sinusoidal wave is
applied to a nonlinear memoryless circuit which has a transfer function which can be
represented as:
V0ut=ai +c*2 Vin+as (V J 2 +a4 (Vin) 3
where for simplicity,
(4.4.1)
0 2 =0 3 = 0
Applying an input signal o f form Vin=Acosa>t into equation 4.4.1 and expanding gives:
196
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( 4 .4 .2 )
Vou, = a \ + a A( A COS OX f
= a. h
1
3a.A 3
a ,A 3
_
2— cos ax + —— cos3ntf
4
4
, , _
(4.4.3)
This simple power series analysis shows that an output spectrum is produced at dc (a/),
the fundamental frequency (3ctjA3/4), and the third harmonic frequency (a 4A 3/ 4 ).
The simple power series analysis, however, has drawbacks associated with its
application: 1) power series analysis does not solve differential equations because it can
not account for initial conditions and 2) power series analysis can only be applied to
memoryless nonlinear circuits, therefore, excluding circuits containing elements which
store energy (such as inductors and capacitors) which relate to the nonlinearity. [91]
4.4.2
Volterra Series Analysis
The Volterra series analysis is another technique commonly used to analyze
nonlinear circuits. Volterra series is a generalization o f the power series analysis,
however, without the limitations exhibited by the power series analysis. The Volterra
series analysis can handle circuits with memory (inductors and capacitors) in the
nonlinear circuit and is typically applied to systems with weakly nonlinearities. Weakly
nonlinear circuits are typically defined as those circuits where the nonlinearity function
can be represented by third order terms or less.
As an example of the Volterra series analysis, consider the system shown below
in Figure 4.4.1 with a nonlinear capacitor. The solution of this network shown in Figure
4.4.1 depends on the past history of the charge stored in the capacitor and solving this
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problem involves a convolution integral accounting for the previous conditions of the
charge in the final solution. The first order output response is expressed as [91]:
y>(') =
(4.4.4)
(t ~ r]x(r)dT
0
where hi (t) is the impulse response o f the network. A slightly more complicated integral
is required to evaluate higher-order terms. A two-dimensional convolution integral
represents the output associated with the second-order term, (y2 (0 )'
i i
(0= 0J0j*h (' - rPr - Mr, M r, ]drxd r 2
y2
t2
(4.4.5)
where /?2 (t) is the second-degree Volterra kernel. The higher-order terms can be
generalized and represented by conventional form for the n‘h order response o f a Volterra
analysis as:
x
30
—oc
—oo
y«(‘)=
f ^ (r p .- - ,r jf lx ( f - r ,) r f r (
and the complete output, y (t), is the sum of all n terms:
Taking the Fourier transform o f the Volterra kernel (equation 4.4.6) gives:
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(4.4.6)
X
H„{cDl.Q)1,....<on) =
X
J... J/i„(rI,....r,f)e'y(<,',r'~
-o o
-«
(4.4.8)
/S*I
where H„ (coi, 6)2........ &>n) is defined as the n'h order Volterra transfer function and
characterizes the nth order response of the network in the frequency domain. Hi (coi) is
the linear transfer function, H2 (coi, (02) is the second order term, H3 (coi.
0)3) is the
third order term, etc. After solving for H„ (a), the output is easily determined as shown:
n
^ (/)= ^
( » \
Hk{<o)eAn-2k)a*
(4.4.9)
A technique for solving the Volterra transfer function is delineated in the following
section.
x
y(t)
Figure 4.4.1 Example Circuit for Volterra Series Analysis
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4.4.3
Harmonic Balance
A commonly used method o f deriving the Volterra transfer functions for a
nonlinear circuit, and, subsequently, finding periodic solutions to nonlinear circuits is
through the use o f a harmonic balance technique. The great success o f the harmonic
balance technique has allowed it to be widely used in many nonlinear circuit simulators.
Harmonic balance decomposes the circuit into the minimum number of linear networks
and into the minimum number o f nonlinear networks as shown in a simple block diagram
in Figure 4.4.2. Afterwards, an excitation signal is applied to the network in the
frequency domain in the form o f Fourier coefficients, the linear portions are analyzed in
the frequency domain and the nonlinear portions are analyzed in the time domain. The
solution to the nonlinear portion is transformed into the frequency domain and is
compared to the solution of the linear portion at the interface, as shown below in Figure
4.4.2. Kirchoffs voltage and current laws mandate that the terminal voltage across each
network at the interface are congruent and the currents of the networks only differ in their
polarity. Solutions for i(t) and v(t) must satisfy the conditions imposed by the nonlinear
network and spectra for i(eo) and v(co) must satisfy the frequency-domain conditions
imposed by the linear network. As expected, exact solutions are often not trivial due to
the nonlinear components. In this regard, harmonic balance algorithms typically employ
error functions to compute the error between the parameters at the interface and use some
form o f iterative techniques to minimize the error. An initial solution is assumed and an
error function is computed. The iterative process begins at this juncture in efforts to
reduce the error to within some specified limits, and, consequently, produce a solution to
the network.
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4h
i(t)
t
Linear
Network
v(t)
Nonlinear
Network
Figure 4.4.2 Block Diagram of Harmonic Balance Analysis
A mathematical relation can be utilized to describe the principle idea behind the
harmonic balance analysis as shown below in equation 4.4.10 [Jerse].
Aem ‘ + BeJa'‘ + CeJOh' + ... = DeJtu'' + EeJOJl' + FeJ^ ‘ + ...
(4.4.10)
As an example showing the usefulness of equation 4.4.10, refer to Figure 4.4.2 and
assume that the left side o f equation 4.4.10 represents the amplitude coefficients of the
various harmonics of the linear portion of the divided network. Similarly, assume that
the right side of equation 4.4.10 represents the amplitude coefficients of the various
harmonics o f the nonlinear portion of the divided network. At the boundary, the
coefficients at each respective harmonic are equal and, therefore, solving for the
coefficients on either side o f the equation which represent one portion o f the network
gives the magnitudes o f the coefficients in the remaining portion of the network.
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Therefore, when equation 4.4.10 holds over a continuous interval of time for
a>i#a)2 * 6 )3 *..., then the amplitude coefficients (A. B, C, D, E, F ,...) for a particular
harmonic must be equal on both sides o f the equation (A-D . B= E, C=F, ...), and there
can be no other result if the equation holds over the continuous interval o f time. As
shown through equation 4.4.10, harmonic balance permits the solution for the amplitude
o f each harmonic to be made independently and complex signals can be broken into
equations that are more easily solved as will be demonstrated in the following sections.
The following steps are undertaken in solving for the nth order Volterra transfer
function, H„ (coi
coj: [91]
1) with a sinusoidal input o f the form
x{t) = eJU'‘ + eja,'J + ... + eJ<u"'
(4.4.11)
2) assume n-dimensional Fourier series for the output y(t) with complex
coefficients
y { t ) ^ c keJ^ '
(4.4.12)
*=1
3) write a harmonic balance equation and equate the coefficients
4) solve for the Fourier coefficients C*
5) calculate H„(o)i
o)^ as Ct/nl
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4.4.4
Harmonic Balance Simulator and Software
The nonlinear analysis performed in this dissertation is performed using a
commercial software package. This section will briefly describe the capabilities o f the
nonlinear simulator found in the EEsof CAD package of LIBRA [92].
The harmonic balance algorithm installed in the Libra simulator allows for the
analysis of linear and nonlinear circuits excited by large-signal, periodic sources to be
performed. This algorithm assumes that a steady-state solution exists which can be
approximated through an iterative process using a finite Fourier series. As previously
stated and shown in Figure 4.4.2, the amplitudes and phases of the currents and voltages
flowing into the linear elements are calculated in a frequency-domain analysis and the
amplitudes and phases of the currents and voltages flowing into the nonlinear elements
are calculated in the time domain. Using Fourier analysis, the amplitudes and currents in
the time-domain are transformed into the frequency domain, and using KirchofFs laws
the relations between the currents and voltages are established and the values of the
currents and voltages at the interface are compared. An error function is calculated to
determine the amount by which the KirchofFs laws are violated and gives an indication
to the adjustments which should be made in order to reduce the error to within a specified
range. If the error function is driven within the specified error value, the simulation
converges and the resulting voltage and current amplitudes and phases approximate the
steady-state solution.
The following procedure is outlined in the EEsof manual as a representative
analysis of the harmonic balance technique as performed by the circuit simulator:
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1) the number of harmonics and the simulation frequency are read into the
simulator
2) a DC analysis is performed to compute all node voltages in the complete
network
3) a sinusoidal excitation at the simulation frequency with the lowest specified
amplitude is applied
4) a linear analysis is performed to obtain the initial voltages. V”' (co,), and
currents, l[ (co,) into the nonlinear network at every nonlinear element
terminal k
5) an inverse Fourier transform is performed on Vj? (co,) to obtain vf(r)
6) the currents into the nonlinear elements /*'(/) are determined from v?(f)
7) a Fourier transform is performed on i?(t) to obtain
8) an error function compares /[(co,) to I?(co,) at each k
9) errors at the nodes will be large on the initial run so new voltages Vknl(co,) will
be obtained based on the previous results and the magnitude o f the error
function
10) the process is repeated beginning at step 4 with the new voltages V?(co,)
11) if the error is within tolerance, convergence has been achieved, otherwise
repeat the process from step 4
Some o f the factors which affect the simulation time o f the harmonic balance
analysis as delineated EEsof include [92]: simulation frequencies-the number of related
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frequencies applied affects the required memory and simulation time, power levelspower level which cause the degree of nonlinearities to increase will increase the
simulation time, harmonics and sample points- the greater the number of harmonics and
sample points analyzed, the greater the simulation time, error tolerances- small error
tolerances increases simulation time, and device model- the number of nonlinear
elements and components in the network will impact the simulation time.
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4.5
Active M u ltip lier Design Techniques
4.5.1
Existing Design Techniques
Over the last few years, numerous researchers have discussed numerous design
approaches leading to various design procedures utilizing various active devices and
topologies in different media and frequency ranges. This section presents various
existing design techniques and other techniques implemented by the author.
A fundamental topological representation for realization o f active microwave
multiplier circuits is shown in Figure 4.5.1. While this is not the most generalized
topology, it is one o f the most frequently used. The physical realization o f an efficient
frequency multiplier subject to design criteria utilizing this configuration is strongly
reliant on the synthesis of networks AO, A'!?, and N 3 , which are typically, but not always
passive [99]. The criteria for specification of AO, AO, and N 3 rely, as usual, heavily on
fundamental active device parameters. In the case o f multipliers, this is heavily
dependent upon bias conditions, input power level and frequency.
Only very seldom have designers purposely employed feedback (AO) in multiplier
designs in the realization o f such circuits. Synthesis o f AO is typically avoided due in part
to the potential creation o f stability problems [46,59,100]. This network, however, has the
potential of providing useful significant improvement in conversion efficiency by proper
combination o f harmonics emerging from the active device with the input fundamental at
the correct phase. The feedback network (AO) combines a harmonic component from the
drain (collector) o f the transistor with the fundamental component on the gate (base) of
the transistor. Theoretically, this produces an enhanced component at the desired output
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harmonic frequency on the drain (collector) assuming that in the ideal case, the phase o f
the feedback is optimal [59,100].
Transistor
Figure 4.5.1 Frequency Multiplier Realization
Some designers have selected a balanced version of the topology given in Figure
4.5.1 for doubler design with perceptions of superior doubler performance [44,62,6466,101-102]. This seems to have emerged from the truly real world advantages realized
in the design of diode doublers [103]. Developers o f such balanced active multipliers
state that these circuits are better due to the natural cancellation of the fundamental and
all odd harmonics thus providing a virtual ground at the output of the active devices and
permitting the location of any matching networks closer to the drain (collector) o f the
devices [52]. Furthermore, they indicate that such designs have the advantage of high
conversion efficiency, 3 dB better output power, better isolation, good harmonic
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suppression, and the elimination of potentially long (A/4) stubs which are common in
single-ended designs.
One o f the classes o f designs emphasizes the arrangement of two or more
transistors in one of several topological configurations as shown in Figure 4.5.2. The
technique shown in Figure 4.5.2a utilize two identical fundamental frequency signals
which are fed 180° out of phase to transistors F/ and T2 . The circuit functions as a type
o f active full wave rectifier in that when the voltage at port 1 is positive, F/ conducts and
F? is turned off and current flows through the emitter o f F/ to the load Zl- When the
polarity of the input signal V (ft) is reversed, F? conducts and 7/ is turned off and current
flows through the collector o f F? providing an output to Zl- This process effectively
provides a rectified output at Z l with the corresponding strong second harmonic content.
This approach has been demonstrated for doubler action over broad frequency ranges (17 GHz) in MMIC topology. Conversion gains range from 0 to 12 dB utilizing input and
output amplification stages. Fundamental rejections o f less than 10 dB appear to be
realizable.
A block diagram of a typical balanced multiplier design is shown below in Figure
4.5.2b. At the input, the input signal o f the multiplier is fed through a power
divider/phase shifter which divides the power between the two transistors with 180 0
phase difference between the input ports of the transistors. The drains (collectors) of the
transistors are connected on the output by a combiner. At the output, the fundamental
signals and other odd harmonic signals have opposite phase and, by destructive
interference, the fundamental and other odd harmonics cancel giving good harmonic
suppression. The second harmonic signals from the transistors have the same phase and,
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thus, interfere constructively. This constructive interference causes enhancement of the
signal at the second harmonic.
I
Figure 4.5.2a Block Diagram of Push-Push Topology of Frequency Multiplier
Phase
Shifter/
Power
Splitter
Transistor
Combiner
Transistor
Figure 4.5.2b Block Diagram of Typical Balanced Frequency Multiplier
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A perusal of the published literature o f such balanced designs reveals, however,
that they require complex components in their realization. In addition to 2 matched
active devices (some designers use more in their active matching stages), balanced
designs typically require large baluns or power splitter/phase shifter combinations. Tjunctions, and in some cases air-bridges. Some realizations also require complex
transitions and additional lengths of transmission lines to rotate the active device outputs
to achieve a pure reactance output, and, finally, only frequency doubler designs are
typically reported. Upon perusal of the literature, it is found that with all due
consideration to the importance o f the particular active device characteristics and
frequency bands, these designs in almost all cases are narrow band (~ 10 %) (ref 65 with
-9 dB conversion gain is one exception which uses an additional active device), have
modest (-5 to +5 dB) conversion gain (3 - 12 dB in one case), and frequently yield sparse
data on fundamental suppression (typically between 12 and 30 dB). Hiraoka [101]
developed a broad band MMIC balanced frequency doubler with a fundamental
frequency of 5 GHz consisting of a common-gate FET and a common-source FET
directly connected in parallel followed by an output matching network. A phase shifter
network precedes the common-gate FET to compensate for the phase error between the
outputs from the common-gate FET and the common-source FET. A conversion loss of
8 —10 dB was achieved for output frequencies between 6 and 16 GHz. Fundamental
frequency isolation (suppression) better than 17 dB up to output frequencies o f 20 GHz
was obtained. Unfortunately, the author did not provide any data on the third harmonic
isolation (suppression). Angelov [66] analyzes a 20 GHz to 40 GHz PHEMT balanced
doubler where two common-source PHEMTs are connected in parallel followed by
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sections of transmission lines on the gates before combining into a 3 dB coupler. The
input signal to the doubler is fed to a power divider which divides the power equally
between the two input ports with 180 degrees phase difference between the input ports.
Sections of transmission lines connect the power divider to the drain of the PHEMTs.
The completed doubler circuit provides approximately -1 dB of conversion gain with a 3 dB bandwidth of approximately 5%. The author notes that the bandwidth is limited
mainly by the 180° rat race coupler. The author does not provide data on the
fundamental and the third harmonic suppression. Takenaka and Ogawa [65] analyzed a
wide band MMIC balanced frequency multiplier utilizing line-unified HEMT
configurations. In line-unified HEMT configurations, coplanar lines such as slotlines and
coplanar waveguides are used to electrically connect the circuit. A coplanar waveguide
precedes a common-gate HEMT followed by slotline series T-junction which acts as an
out-of-phase divider to drive two parallel, common-drain HEMTs. The output of the two
HEMTs is connected to a coplanar waveguide followed by the load resistance. This
topology yields conversion loss o f 8-10 dB in the 4-40 GHz output frequency range and
fundamental frequency signal isolation of better than 21 dB above the input frequency of
7 GHz. The authors do not provide any data third harmonic isolation.
One final observation on balanced designs is the almost universal disregard for
the deleterious effects o f channel imbalances. It has been reported that for A phase
imbalances of 1 0 °, the output conversion gain at the second harmonic will decrease by 1
dB in a 4 dB design while a A amplitude imbalance of 0.3 dB produces the same 1 dB
decrease. A combination o f imbalances o f 10 °and 0.3 dB together results in a « 3 dB
decrease in a 4 dB conversion gain design [66,104]. For these reasons, balanced
211
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
realizations are not further considered in this dissertation, although obviously some
principles presented are directly transferable to balanced circuits.
Numerous investigators have reported designs for single-ended microwave
multipliers. Referring to Figure 4.5.1, these designs include networks T
V
/and T
V
?but are
without an “external” network (yV
j). Single-ended designs are based primarily on the
realization o f T
V
/and T
V
?. Traditional synthesis o f T
V
/ and T
V
?have followed along the lines
o f the passive case in that T
V
/ is traditional composed o f a bandpass/lowpass filter or
matching network tuned to a fundamental frequency and T
V
?is similarly a matching
network or bandpass/highpass filter timed to the appropriate harmonic frequency of
interest. Synthesis of these networks include the use o f cascades o f filters and matching
networks [40-41,50,52,61,63,77-78,81,100,105-107], transmission lines and stubs to
open-circuit or short-circuit specific harmonics [41,61,63,107], while some authors have
additionally considered these networks as a cascade o f matching and reflection network
[48,57,63,107]. Many of these techniques determine optimal networks utilizing load line
analysis [44-45], intuitive reasoning based on previous results [45,77], computer
optimization o f generalized models [59,61] and experimental techniques based on stub
tuner measurements [41,107].
Dow [50] develops a FET frequency doubler with a fundamental frequency o f 20
GHz utilizing matching networks and tuners. An input matching network designed to
match the fundamental frequency was placed on the gate o f the FET, and an output
matching network designed to match the second harmonic was placed on the drain o f the
FET. In addition to the matching networks, tuners were connected to the input and
output ports to optimize the performance of the frequency doubler. A maximum
212
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
conversion gain o f —1.8 dB was achieved utilizing this topology. Chen [40] develops a
MESFET frequency doubler utilizing filters and matching networks. A lowpass filter is
placed on the input o f the circuit which allows the fundamental frequency to pass through
to the gate of the device, and a highpass filter is placed on the output of the device to
allow the desired second harmonic to pass. In addition to the highpass filter on the
output, a matching network designed to match the second harmonic frequency is place in
series with the highpass filter. Utilizing this topology, Chen achieved 8 dB of conversion
gain. Borg [48] has developed BJT frequency doubler designs utilizing transmission
lines and stubs. In one o f the designs developed by Borg, a 50 ohm transmission line is
placed on the input o f the circuit and short-circuited stubs which short the second
harmonic are placed on the output of the device. This particular design shown by Borg
produces 2.5 dB o f conversion gain. Rauscher [46] provides a FET frequency doubler
utilizing transmission lines and stubs as well. On the input of the device, transmission
lines are utilized to form impedance transformations and an open circuited stub. On the
output of the device, transmission lines are utilized to provide an open circuited stub at
the fundamental frequency. Rauscher’s data show that -0.5 dB of conversion gain was
achieved in this design.
Stancliff [44] and Gilmore [45] determine optimal networks utilizing load line
analysis for their multiplier designs. Using the Ids versus
curves for a FET, they
employ fundamental load line analysis to demonstrate the output characteristics for a
fundamental frequency open-circuited load line placed on the output of the FET.
Stancliff uses this approach for a balanced multiplier design while Gilmore uses this
approach for the development o f a single-ended multiplier. Various authors have used
213
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
generalized large-signal device models along with various analysis techniques to develop
frequency multipliers [59,61]. El-Rabaie [61] uses a harmonic balance analysis
technique to optimize a MESFET frequency doubler utilizing a large-signal MESFET
device model. The optimization approach utilized by El-Rabaie determines the optimum
terminating impedances which should be presented to the multiplier for optimum
performance, while the approach utilized by Guo [29], determines optimum bias voltages
and optimum load impedances. Le [41] utilizes experimental techniques based on stub
tuner measurements to design frequency multipliers. In this approach, load-pull
measurements are performed to measure impedances at various frequency harmonics at
various bias voltages, and utilizing this data, frequency multipliers are designed
optimizing conversion gain and efficiency. Le uses this approach in the development o f a
frequency tripler which gave a conversion gain of -2.4 dB.
Single-ended designs using the previously mentioned design techniques have
exhibited excellent performances. Conversion gains approaching 9 dB, harmonic
suppression exceeding 40 dBc, and bandwidths approaching 35 % have been reported
[93,95]. A significant drawback o f some single-ended designs is the potentially large
size constraints required by matching and harmonic stubs. Potentially long stubs of
lengths approaching XJ4 are commonly used. For lower frequency applications,
however, discrete components offer a viable means of synthesizing required matching
and potentially long harmonic stubs. Even though the performance o f frequency
multipliers using these design techniques is excellent, applications where size constraints
are specified reduce the accessibility o f these designs in these particular applications.
214
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
4.5.2
Unified Design Technique
In the previous section, existing design techniques of frequency multipliers were
delineated. While these approaches suffice to produce multipliers which work in some
sense, they are not necessarily efficient in that proper synthesis of N/ and N? can yield
significant improvements in performance as measured by conversion gain. In this
section, a consistent design technique is proposed for the design of active frequency
multipliers using the topology shown in Figure 4.5.3 stemming from an outgrowth of
research on terminating impedance effects on active devices.
Due to the nature of the extraordinarily complex nonlinear circuit problem, it is
proposed that the technique, while heavily reliant on experimental measurements, is
based on in-depth computer oriented design. Based on a perusal of the literature there
appears to be little discussion on this topic for active multipliers other than an occasional
reference in concern o f power limitation in overdriving the drain in MESFET/HEMT
realizations. As with any such active design the first step requires the selection o f an
active device possessing the appropriate performance characteristics [66], and
particularly, in this case, developing accurate nonlinear device computer models. (In the
present case, a particular device on hand is selected based on convenience.) Here, for
example, can be considerations o f the effects of each device nonlinearity [e.g. Cgs, Cgd,
g d s, Id s (V gs, Vds)]
on augmenting a particular device harmonic [50]. At this point the
nonlinear device model should be accurately developed based on both dc and ac
characteristics which matches the measured performance of the transistor [1,66,98].
Angelov [66], as presented in section 4.3.1, developed an accurate nonlinear model for
PHEMTs. Utilizing this nonlinear model, Angelov designs a balanced millimeter wave
215
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
frequency doubler with PHEMT transistors exhibiting good agreement between measured
and modeled data.
Device
Characteristics
Termination
Matrix
Determination
Bias Point And
Input Power
Level
Synthesis of
ZfJl, Z \’2
Zw/. Zv2
Figure 4.5.3 Topology of Active Microwave Multiplier
The next step requires utilizing the device model and/or measured data to
determine optimum bias points and input power levels using both static and Pin versus
Pout data. Examples o f this process may be found in previous publications [50,100], At
this stage, it is important to develop the requirements on the termination networks N/ and
IV2 of Figure 4.5.1 leading to optimum multiplier performance. This process, to be more
effective, requires the use of expensive computer analysis to be efficient and time-wise,
although, as has been done by several researchers [41,61] some limited results can be
achieved by extensive time consuming measurements. As mentioned previously
mentioned, El-Rabaie [41] and Le [61] used computer optimization o f generalized
nonlinear models to optimize frequency multipliers. The outcome o f this process is the
prescribed driving point responses for networks Nj and N 2 when terminated in Rg and Rl,
respectively, where Rg is the source resistance and Rl is the load terminating impedance.
216
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
The final step (Figure 4.5.3) involves the synthesis of Zm and Z\ ? to realize the
prescribed impedances where Zsi is the impedance of network Ni and Zs 2 is the
impedance o f network N?.
4.5.2.1
Illustration of Unified Design Technique
This section describes the design o f an experimental frequency doubler based on
the above approach utilizing a Fujitsu FHX35LG HEMT transistor. This transistor was
modeled in section 4.3.1 where measured and modeled data was presented showing the
accuracy o f the nonlinear model subsequent to performing step 1 above.
Step 2 requires the determination o f optimum bias points and input power levels
from either measured or modeled data. Figure 4.5.4 - 4.5.7 shows simulated data for
various bias conditions and input power levels o f the FHX35LG transistor. Figure 4.5.4
shows the simulated output power at 3 GHz versus gate-to-source voltage ( Vgs) at the
fundamental frequency and the second harmonic frequency, Figure 4.5.5 shows the
simulated output power at the second harmonic frequency versus the drain-to-source
voltage ( Vds), Figures 4.5.6a and 4.5.6b show the conversion gain at the second harmonic
versus
for various input power levels, and Figure 4.5.7 shows the simulated output
power versus input power. Figures 4.5.4 and 4.5.6 show that good second harmonic
generation occurs for
vgs=ovolts and Vgs=Vp=-0.7 volts as indicated in section 4.3.3.
However, in the present case, the conversion gain is greater by approximately 9 dB (-1 dB
versus -10 dB) when operating at Vgs Vp with Pm~0 dBm (Figure 4.5.6 b) as compared to
operation with v ^ o volts. The results o f step 2 indicate that optimum bias and input
power values for the doubler are V ^ V P=-0.7 volts and Pm=0 dBm.
217
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
20 .
S
cc
1 -io
&
3
& -20
C
Po % fo
Pora) 2fo
-30
-40
Vg5 (v)
Figure 4.5.4 Simulated Output Power of FHX35LG HEMT versus
(.Pi„=0 d B m , K*=5 v ,f= 3 G H z)
o
^
E
as
•9
| -,o
■
Vgs *0 v
— — Vgs~-0.5 v
a.
- - - - V gs*-0.75 v
S- -15
Vgs=-I.O v
3
O
-20
0
0.5
1.5
2
2.5
3
3.5
4
Vds (v)
Figure 4.5.5 Simulated Output of the Second Harmonic versus V ,* for FHX35LG
HEMT {Pin=0 d B m , f = 3 G H z)
218
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Conversion Gain (dB)
- Pin- - 5 dBm
-30
. P in -0 dBm
-10
P in -5 dBm
-50 ,
-60
-70
-1.4
-1.3
-1.2
-1.1
-I
-0.9
-0.8
-0.7
-0.6
-0.5
-0 4
03
0 .2
0 .1
0
Vgs (v)
Figure 4.5.6a Simulated Conversion gain of FHX35LG HEMT versus Vgs
(Vds=3 V ,f= 3 G H z)
Conversion Gain (dB)
0
.
/
-1 0
Pin--5 dBm
P in-0 dBm
Pin-5 dBm
-18 1
-20 _
1.4
-
1.3
1.2
0.9
0.8
0.7
0.6
0.5
0.4
0.3
02
0.1
0
Vgs (v)
Figure 4.5.6b Simulated Conversion gain of FHX35LG HEMT versus Vgs
(Vds—3 V ,f= 3 G H z)
219
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
20 E
as
L.
U
*o
s
P o (§ fo
&
-10
O
-15
Poifij 2fo
-20
-10
-5
0
5
10
Input Power (dBm)
Figure 4.5.7 Simulated Output Power versus Input Power of FHX35LG
(Vgs=Vp= -0 .7 V, V ^ 3
V, f= 3 G
H z)
The next step requires the generation of matrix tables for the design o f a
frequency doubler operating at 3 GHz input. These matrix tables represent the simulated
output powers o f the HEMT frequency doubler for various combinations of the input and
output impedances (Z,v/ and Z^i) presented to the HEMT. In this case extensive
v and Vgs-V p=-0.7 volts [98], Several
terminating tables were generated for both
matrix tables are shown in Tables 4.5.1 - 4.5.10 similar to those shown in section 4.3.5.
220
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
lu m p e d C om ponent*
V g*-*0 7 V
O u tp u t N etw ork
P in - 0 dB m
50 o h m @ fo
short circ u it S fo
o p en c irc u it 01 fo
short circuit @ fo
o p e n circ u it § fo
50 cdim @ fa
50 oh m ( g fo
short circ u it @ fo
V ds"J V
50 o h m @ 2 fo
50 o h m 0 ) 2fo
50 o h m 0
50 o h m
50 o h m @ 2fo
50 o hm
50 o h m @ 2fo
5 0 o h m ® 2fo
50 o h m @ 2 f o
In p u t N etw ork
50 o h m @ J fo
50 o h m @ J fo
50 o h m @ J fo
o p en circ u it ® Jfo
s h o rt circ u it ® If o
sh o rt circ u it 0 ) J fo
O u tp u t P ow er d B m )
2fo
2fo
o p en circ u it (A J fo
o p en circuit
O u tp u t P ow er (dB m )
O u tp u t P o w er (d B m )
O u tp u t P ow er (d B m )
@
@
Jfo
@
2fo
sh o rt circ u it @ Jfo
O utput P ow er (dB m )
O u tp u t P ow er (d B m )
O u tp u t P ow er (d B m )
o p en circ u it § fo
O u tp u t P ow er (rJAm}
O u tp u t P o w er (d B m )
5 0 o h m @1 To
P o @ fo
596
P o 0 fo
• 7J
P o 0 > fo
•66 5
P o 0 )fo
73 2
P o T 3 fo
•66 5
P o @ fo
59
P o @ fo
59
P o ® fo
•73 2
P o @ fo
50 o h m 0 ) 2fo
P o ® 2 fa
-0 9
P o@ 2fo
0
P o ® 2 fo
1
P o@ 2fo
03
P o 0 )2 fo
•0 7
P o@ 2fo
•I 1
P o @ 2 fo
•0 7
P o ® 2 fo
•0 2
P o@ 2fo
•1 4
50 o h m 0
P o @ J fo
•1 4 7
P o ^ jr o
•14
P o @ lf o
• 178
P o@ 3fo
•72 5
P o @ 3 fo
• 107
P o @ Jfo
•94
P o @ J fo
• 104
P o @ Jfo
•94
P o@ 3fo
■97 2
•66 3
)fo
-66 5
5 0 o h m @ To
P o 0 )fo
62
P o @ fo
-72 9
P o @ fo
•66 3
P o ^ ro
•72 8
P o @ fo
66 3
P o 0 fo
62
P o @ fo
63
P o ® fo
•72 9
P o @ fo
t h o il c irc u it 0 ) 2 fo
P o @ 2 fo
03
P o @ 2 fo
15
P o @ 2 fo
-0 1
P n@ 2fo
18
P o @ 2 fo
02
P o@ 2fo
0
P o@ 2fo
07
P o ® 2 fo
12
P o@ 2fo
•0 5
5 0 o h m ® J fo
P o @ J fo
•II 8
P o 0 )3 fo
-1 0 6
P n @ J fn
• 172
P o @ Jfo
-6 8 9
P o @ 3 fo
• 106
P o 0 3 fo
•92
P o ® J fo
• 100
P o ® 3 fo
•91 I
P o @ lf o
•97 7
•66 )
5 0 o h m 0 ) To
P o @ fo
6
P o @ fo
-72 9
P o @ fo
•66 3
P o 0 l fo
•72 8
P o @ fo
•66 5
P o @ fo
62
P o @ fo
63
P o @ fo
•72 9
P o @ fn
s h o rt c irc u it @ 2fo
P o @ 2 fo
•I 2
P o @ 2 fo
15
P o ® 2 fo
•0 I
P o 0 )2 fo
18
P o @ 2 fo
•0 9
P o@ 2fo
03
P o @ 2 fo
07
P o 0 )2 fo
12
P o @ 2 fo
-0 5
s h o rt c irc u it @ J fo
P o @ J fo
•IJ4
P o @ 3 fo
• 106
P o @ J fo
•1 7 2
P o@ 3fo
-9 9 1
P o @ 3 fo
109 6
P o @ Jfo
•III
P o@ 3fo
• 1006
P o@ 3fo
•91 1
P o 0 |lf o
•97 7
50 o h m @ fo
P o @ fo
59
Po0K o
•73 2
P o @ fo
•6 6 5
P o @ fo
-73 2
P o @ fo
•6 6 5
P o @ fo
59
P o Q fo
59
P o @ fo
•73 2
P o @ fo
-66 7
50 o h m @ 2 fo
P o @ 2 fo
•2 2
P o @ 2 fo
•I 3
P o @ 2 fo
•2 3
P o@ 2fo
•1 2
P o @ 2 fo
•17
P o ® 2 fo
•1 3
P o @ 2 fo
•2 1
P o 0 )2 fo
•0 1
P o ^ 2 fo
2 7
P o@ 3fo
•17 1
P o @ J fo
• 161
P o @ J fo
• 158
P o@ 3fo
108 2
P o @ J fo
1066
P o @ J lb
•94 5
P o Q Jfo
• 108
P o ^ Jfo
•94 1
P o @ 3 fo
•9 0 S
•66 5
s h o rt circ u it
%
J fo
5 0 o h m @ To
P o 0 )fo
6 1
P o @ fo
•7J
P o @ fo
•666
P o @ fo
•7 J I
P o @ fo
-6 6 6
P o @ fo
6 1
P o @ fo
6 I
P o @ fo
•73
P o @ fo
o p e n c irc u it @ 2 fo
P o 0 2 ro
•1
P o @ 2 fo
0
P o ® 2 fo
-I 2
P o@ 2fo
01
P o @ 2 fo
•I
P o@ 2fo
•I 1
P o @ 2 fo
•0 8
P o 0 2 fo
•0 2
P o@ 2fo
•I 5
50 o h m @ J fo
P o @ 3 fo
•1 5 9
P o @ 3 fo
•15 3
P o @ )fo
•21 2
P o @ Jfo
•104
P o @ 3 fa
• 109
P o@ 3fo
•96
P o @ J fo
• 105
PCN§)fo
•96 1
P o @ lf o
1004
•6 6 5
•66 5
P o @ fo
6 1
P o 0 fo
•7J
P o @ fo
P o 0 | fo
•71
P o @ fo
•66 5
P o 0 fo
61
P o @ fo
6 1
P o @ fo
-73
P o @ fo
@
2fo
P o ® 2 fo
-0 9
P o@ 2fo
0
P o 0 2 fo
•1 1
P o@ 2fo
0 3
P o@ 2fo
-0 9
P o ® 2 fo
-1 2
P o 0 2 fo
•0 7
P o ^ 2 fo
■0 2
P o ^ 2 fo
•1 4
o p e n circ u it 0
J fo
p o ta n ro
• 157
P n ® 3 fo
•15 1
P o @ 3 fo
-20
P o@ 3fo
-104
P o 0 |J f o
• 108
PD ® 1fo
•96 2
P o ® 3 fo
• 105
P o @ lf o
•96
P o ^ Jfo
•99 8
•66 5
50 o h m 0
To
o p e n c irc u it
50 o h m 0 fo
P o @ fo
6
P o Q fo
-7 J 1
p o ( d fo
■66 4
P o 01 fo
-7J
P o 01 fo
•66 5
P o 0 )fo
6
P o ® fo
6
P o 0 t fo
•73
P o @ fo
4 0 o h m (<d 2 fo
Po(tfc2fo
•01
P o ra 2 fo
0 1
P o ® 2 fo
-0 9
P(X $2fa
04
P a ® 2 fn
-0 7
P o 0 )2 fo
•I 1
P o ® 2 fo
-0 5
P o@ 2fo
•0 2
P o @ 2 fo
•1 4
o p e n circ u it 0 ) J fo
P o ® 3 fo
• 14 J
P o ta i f o
116
P o0>3fo
-17
P o @ Ifo
•102
P o 0 |lf o
• 105
P o@ 3fo
•94 4
P o ® Jfo
• 103
P o@ 3fo
•93 9
P o @ 3 fo
•96 9
Table 4.5.1 Doubler Simulations with Lumped Components (KJP=s-0.7 volts, Pin-0dB m )
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
V k » -0 V
O u tp u t N e tw o tk
P in nO dB m
SO o h m 0 fo
s h o rt circ u it 0 fo
o p e n circ u it 0
sh o rt circ u it 0 fo
o pen circ u it 0 fo
SO oh m 0 fo
SO o h m 0 lb
sh o rt c irc u it 0 fo
V d s -3 V
SO o h m 0 2 f o
SO o h m 0
SO o h m 0 2fo
5 O o h m 0 2 fo
SO o h m 0 2fo
SO oh m 0 2fo
SO o h m 0 2 f o
SO oh m 0 2 fo
SO ohm 0 2fo
In p u t N etw ork
SO o h m 0 J f o
SO o h m 0 J fo
50 o h m 0
o p en circ u it 0 J fo
o p en circ u it 0 J fo
short circ u it 0
o p en circ u it 0 J fo
s h o rt c irc u it 0 J fo
sh o rt circ u it 0 J fo
6 u t p u t P o w e r (d b m )
J fo
O u tp u t P ow er (d B m )
to
Jfo
O u tp u t P ow er (d B m )
O utput P ow er (d B m )
O u tp u t P ow er (d B m )
J fo
O u tp u t P ow er (d B m )
O u tp u t P ow er (d B m )
op en circ u it 0 fo
O u tp u t P o w er (d B m )
6 u t p u t P ow er (d B m )
5 0 o h m 0 fo
P o 0 fo
US
P o 0 fo
•6 6 2
P o 0 fo
•62 1
P o 0 fo
•66 2
P o 0 fo
-62
P o 0 fo
US
P o 0 fo
12 S
P o 0 fo
•66 J
P o 0 fo
SO oh m 0 2 fo
P o 0 2 fo
-1 0 1
P o 0 2 ro
-1 0 9
P o 0 2 fo
-2 4
P o 0 2 fo
• 106
P o 0 2 fo
•2
P o 0 2 fo
• 102
P o 0 2 fo
• 10
P o 0 2 fo
•II 2
P o 0 2 fo
•2 2
SO oh m 0
P o 0 Jfo
*139
P o 0 3 fo
-1 0 7
P o 0 Jfo
■7 1
P o 0 3 fo
•98
P o 0 Jfo
-92
P o 0 Jfo
•94 8
P o 0 3 fo
•101
P o 0 3 fo
.91 8
P o 0 )fo
19 5
J fo
•62 1
S O o h m 0 fo
P o 0 fo
124
P o 0 fo
•66
P o 0 fo
-62 2
P o 0 fo
•66
P o 0 fo
-62
P o 0 fo
124
P o 0 fo
12 S
P o 0 fo
•66 2
P o 0 fo
•62
sh o rt c irc u it @ J fo
P o 0 Jfn
•II 1
P o 0 2 fo
-14 7
P o 0 2 fo
-2 6
P o 0 2 fo
•14 1
P o 0 2 fo
•2 1
P o 0 2 fo
•II J
P o 0 2 fo
• 108
P o 0 2 fo
■ IS )
P o 0 2 fo
•2 7
SO o h m 0
P o 0 Jfo
-14 1
P o 0 3 fo
•II t
P o 0 )fo
-7 J
P o 0 3 fo
•98 4
P o 0 Jfo
•92 7
P o 0 Jfo
.9 4 9
P o 0 3 fo
• 101
P o 0 )fo
-9 2 2
P o 0 Jfo
•89 8
J fo
SO o h m 0 fo
P o 0 fo
124
P o 0 fo
•66
P o 0 fo
-62
P o 0 fo
•66
P o 0 fo
-62
P o 0 fo
124
P o 0 fo
124
P o 0 fo
•66 I
P o 0 fo
-62 4
sh o rt c irc u it 0 J fo
P o 0 Jfo
•1 1 2
P o 0 2 fo
•IS J
P o 0 2 fo
•J 2
P o 0 2 fo
• 15 4
P o 0 2 fo
•2 2
P o 0 2 fo
•1 0 9
P o 0 2 fo
•II 1
P o 0 2 fo
•1 )1
P o 0 2 fo
-2 8
s h o rt c irc u it 0 J f o
P o 0 J fo
•1 1 6
P o 0 Jfo
• 146
P o 0 3 fo
59
P o 0 Jfo
• 105
P o 0 Jfo
•94 2
P o 0 Jfo
•12 7
P o 0 Jfo
• 109
P o 0 3 fo
•81 8
P o 0 )fo
-78
SO o h m 0 fo
P o 0 fo
124
P o 0 fo
•66 J
P o 0 fo
•62 1
P o 0 fo
-66
P o 0 fo
•62 1
P o 0 fo
US
P o 0 fo
124
P o 0 fo
•66
P o 0 fo
•62 J
SO o h m 0 J f o
P o 0 2 fo
•1 0 2
P o 0 2 fo
•1 1 2
P o 0 2 fo
•J
P o 0 2 fo
•II 2
P o 0 2 fo
•2 1
P o 0 2 fo
• 104
P o 0 2 fo
•10
P o 0 2 fo
• 109
P o 0 2 fo
•2 4
P o 0 3 fo
•II J
P o 0 Jfo
•1 4 9
P o 0 )fo
•5 7
P o 0 Jfo
-17 1
P o 0 )fo
•9 )9
P o 0 Jro
•12 4
P o 0 Jfo
• 109
P o 0 )fo
•12 2
P o 0 Jfo
•78
-62 1
sh o tl c irc u it 0
J fo
SO o h m 0 fo
P o 0 fo
126
P o 0 fo
•66 1
P o 0 fo
-62 1
P o 0 fo
-6 6 1
P o 0 fo
-62 1
P o 0 fo
126
P o 0 fo
126
P o 0 fo
•66 1
P o 0 fo
o p e n circ u it 0 J f o
P o 0 2 fo
•9 1
P o 0 2 fo
•10)
P o 0 2 fo
•2 1
P o 0 2 fo
-1 0 1
P o 0 2 fo
•1 7
P o 0 2 fo
•9 J
P o 0 2 fo
•9 2
P o 0 2 fo
• 107
P o 0 2 fo
•1 9
SO o h m 0
P o 0 )fo
•IJ7
P o 0 Jfo
•10)
P o 0 3 fo
•7 1
P o 0 Jfo
•97 8
P o 0 Jfo
•92 4
P o 0 )fo
•94 6
P o 0 )fo
•101
P o 0 )fo
•91 5
P o 0 )fo
•89 6
J fo
s o o h m 0 fo
P o 0 fo
126
P o 0 fo
•66
P o 0 fo
-62
P o 0 fo
-66
P o 0 fo
•62 1
P o 0 fo
126
P o 0 fo
126
P o 0 fo
•66
P o 0 fo
•62
op en circ u it 0 J f o
P o 0 2 fo
•9 J
P o 0 2 fo
-1 0 3
P o 0 2 fo
•1 9
P o 0 2 fo
-9 9
P o 0 2 fo
•I 7
P o 0 2 fo
•9 J
P o 0 2 ro
•9 2
P o 0 2 fo
• 10 7
P o 0 2 fo
•IS
o p e n circ u it 0
P o 0 Jfo
•II
P o 0 Jfo
-9 7
P o 0 Jfo
-7 J
P o 0 )fo
-9 6 5
P o 0 Jfo
-91 6
P o 0 )fo
•94 8
P o 0 Jfo
• 100
P O 0 Jfo
•91 S
P o 0 3 fo
■90 7
-62 1
J fo
SO oh m 0 fo
P o 0 fo
12 S
P o 0 fo
•6 6 2
P o 0 fo
•62 1
P o 0 fo
•66 1
P o 0 fo
•62 1
P o 0 fo
12 5
P o 0 fo
125
P o 0 fo
•6 6 2
P o 0 fo
5 0 oh m 0 2 fo
P o 0 2 fo
•10 1
P o 0 2 fo
• 108
P o 0 2 fo
•2 2
P o 0 2 fo
• 104
P o 0 2 fo
•2
P o 0 2 fo
• 102
P o 0 2 fo
.9 9
P o 0 2 fo
•II 2
P o 0 2 fo
•2 1
P o 0 1 fo
•IJ)
P o 0 Jfo
•10 1
P o 0 1 fo
•7 3
P o 0 )fo
•96 8
P o 0 Jfo
•9 1 6
P o 0 Jfo
*9S 1
P o 0 )fo
• 100
P o 0 )fo
•92
P o 0 )fo
•90 7
o p en circ u it 0
J fo
Table 4.5.2 Doubler Simulations with Lumped Components ( Vgs=0 volts, Pin^O dBm)
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Ideal T ra n sm issio n L in es
V p - 'O 7 V
O u lp u l N etw ork
P in » 0 dB m
50 o h m
V d s-J V
50 o h m
Input N etw ork
SO o h m 0 J fo
@
fo
s h o d circ u it @1 fo
o p en circ u it (u| fo
s h o d circ u it @ fo
op en circ u it
50 oh m ( § fo
50 o h m
2 fo
50 o h m @ 2fo
50 oh m 0 2fo
50 oh m 0 2fo
50 oh m ® 2fo
S 0 o h m @ 2 fo
5 0 oh m 0 2fo
50 oh m 0 2 fo
50 oh m @ 2fo
50 oh m 0
50 oh m @ Jfo
o p en circ u it 0 J fo
op en circ u it 0 J fo
s h o d circ u it 0 Jfo
o p e n circ u it 0 J fo
s h o d circ u it 0 J fo
s h o d circ u it 0 J fo
O u tp u t P ow er (d B m )
J fo
O u tp u t P ow er (d B m )
O u tp u t P ow er (d b m )
%
fo
O utput P ow er (d B m )
O u tp u t P ow er (d B m )
%
fo
s h o d circ u it
O u tp u t P ow er (d B m )
O u tp u t P ow er (d B m t
@
fo
o p en circ u it @ fo
O u tp u t P ow er (d B m )
O u tp u t P ow er (d B m )
5 0 o h m @ fo
P o @ fo
596
P o 0 fo
♦217
P o @ fo
•210
P o @ fo
•215
P n @ fo
•201
P o 0 fo
55
P o @ fo
4 1
P o @ fo
•216
P o @ fo
5 0 o h m @ 2 fo
P o 0 2 fo
•0 9
P o @ 2 fo
•0 3
P o @ 2 fo
-0 7
P o@ 2fo
02
P o@ 2fo
04
P o@ 2fo
•3 9
P o@ 2fo
03
P o@ 2fo
•3 3
P o@ 2fo
•4 2
50 ohm
P o @ 3 fo
•14 7
P o @ J fo
-221
P o 0 3 fo
•231
P o @ J fo
-270
P o @ J fo
•270
P o @ )fo
•232
P o @ J fo
•237
P o @ J fo
•270
P o Q lfo
•270
P o @ fo
105
P o @ fo
•213
P o @ fo
•207
P o @ fo
•211
P o @ fo
•204
P o @ fo
102
P o @ fo
17
P o @ fo
•212
P o @ fo
•206
P o@ 2fo
45
P o@ 2fo
54
P o@ 2fo
39
P o (0 2 fo
6
P o@ 2fo
52
P o@ 2fo
11
P o @ 2 fo
6 1
P o@ 2fo
25
P o@ 2fo
01
SO o h m @ J fo
P o @ J fo
•7 9
P o @ J fo
•215
P o@ 3fo
•224
P o@ 3fo
•270
P o @ J fo
•270
P o @ Jfo
•225
P o Q Jfo
-232
P o @ 3 fo
•270
P o @ 3 fo
•270
50 o h m
•207
@
J fo
5 0 o h m @| fo
s h o d circ u it
@
2fo
•209
p o 0 ro
17
P o @ fo
•215
P o @ fo
-201
P o ( 9 fo
•213
P o @ fo
•205
P o @ fo
13
P o @ fo
69
P o @ fo
•213
P o @ fo
s h o d circ u it @ 2 fo
fo ® 2 f o
25
P o@ 2fo
32
P o @ 2 fo
2
Po<Vi2fo
4 3
P o@ 2fo
21
P o@ 2fo
•0 7
P o @ 2 fo
4 3
P o @ 2 fo
01
P o@ 2fo
-0 9
s h o d circ u it @ 3fo
P o @ )fo
•126
P o @ J fo
-219
P o @ lf o
•232
P o @ J fo
-270
P o @ )fo
•270
P o@ 3fo
•229
P o @ 3 fo
•215
P o @ J fo
-270
P rt^ lf o
• 270
50 o h m @ fo
P o @ fo
54
P o @ fo
•211
P o @ fo
-211
P o @ fo
•216
P o @ fo
•201
P o @ fo
34
P o @ fo
34
P o Q fo
*217
Po@ To
-209
5 0 o h m @ 2 fb
P o @ 2 fo
•2
P o @ 2 fo
•I 4
P o@ 2fo
*2 5
P o (» 2 fo
•2 3
P o 0 2 fo
•2 3
P o@ 2fo
*4 1
P o@ 2fo
•2 1
P o @ 2 fo
•3 6
P o @ 2 fo
*5 1
s h o d circ u it @ 3 fo
P o @ )fo
-1 1 2
P o @ J fo
•213
P o (d 3 fo
-237
P o @ J fo
•270
P o @ Jfo
•270
P o@ 3fo
-220
P o @ 3 fo
•246
P o 0 3 ro
•270
P o t§ 3 fo
•270
•212
%
fo
50 o h m @ fo
P o @ fo
27
P o 0 fo
•221
P o @ fo
•213
P o 0 fo
•219
P o 0 fo
-211
P o @ fo
23
P o @ fo
06
P D 0 fo
•220
P o @ fo
o p e n circ u it @ 2fo
P o @ 2 fn
•4 4
P o @ 2 ro
•3 7
P o @ 2 fo
•4 1
P o@ 2fo
*4 1
P o@ 2fo
•3 1
P o@ 2fo
-6 5
P o@ 2fo
•4 2
P o@ 2fo
*6
P o ^ 2 fo
•7
S O o h m ® J fo
P o @ J fo
• 19 8
P o @ J fo
-227
P o @ J fo
•239
P o 0 ]fo
-270
P o@ 3fo
•270
P o @ J fo
•235
P o @ lf o
•246
P o @ 3 fo
•270
P o ^ Jfo
•270
•210
P o fafo
47
P o @ fo
•219
P o @ fo
-211
P o @ fo
•217
P o @ fo
-209
P o @ fo
43
P o @ fo
26
P o @ fo
•217
P o Q fo
o p en circuit 0 2fo
P o @ 2 fo
•2 7
P o @ 2 fo
-3 2
P o@ 2fo
•2 4
P o@ 2fo
.5
P o@ 2fo
•2 6
P o @ 2 fo
•4 9
P o @ 2 fo
•2 6
P o @ 2 fo
•4 1
P o ^ 2 fo
-4 9
o p en circ u it
P o @ )fo
-23 4
P o @ 3 fo
•219
P o @ J fo
•235
P o @ )fo
•270
P o 0 ir o
-270
P o @ J fo
•237
P o @ J fo
•231
P o @ J fo
•270
P o 0 3 fo
•270
•212
50 o h m
fo
@
J fo
P o @ fo
3
P o 0 fo
-221
P o @ )fo
•212
P o @ fo
•211
P o @ fo
•210
p o 0 ro
22
P o @ fo
12
P o @ fo
•220
P o @ fo
50 o h m @ 2fo
P o @ 2 fo
•4 3
P o@ 2fo
-4
P o @ 2 fn
-4 2
P o@ 2ro
•1 1
P o @ 2 fo
•2
P o@ 2fo
•1 1
Po<§2fo
•1 6
P o @ 2 fo
•1 2
P o (^ 2 fo
-1 3
o p e n circ u it @ J fo
P n @ lf o
•159
P o @ 3 fo
*222
P o @ 3 fo
•215
P o @ J fo
•270
P o@ 3fo
•270
P o @ J fo
•236
P o @ 3 fo
•232
P o @ 3 fo
•270
P o@ 3fo
•270
50 o h m
@
fo
Table 4.5.3 Doubler Simulations with Ideal Transmission Lines (Vgs=-0.7 volts, Pi„=0 dBm)
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Id e al T ra n sm issio n l.in e s
V g s-0 V
O u tp u t N etw ork
Pin^O dB m
50 o h m @ fo
sh o rt circ u it ( 3 fo
o p en circ u it @ fo
short circ u it @ fo
o p en circ u it ( 3 fo
S 0 o h m @ fo
50 o h m
V d s -lV
50 o h m ( 3 2fo
50 o h m ( 3 2fo
50 o h m @ 2fo
50 o h m @1 2fo
50 o h m ( 3 2fo
50 oh m ( 3 2fo
50 o h m ( 3 2fo
50 oh m ( § 2fo
50 o h m ( § 2fo
In p u t N etw ork
50 o h m @ J fo
40 o h m ( 3 J fo
50 o h m 0 J fo
o p en circ u it @1 J fo
o p en circ u it ( 3 Jfo
short circ u it
op en circ u it ( 3 J fo
sh o rt circ u it Q J fo
th o rt circ u it @ J fo
O u tp u t P o w er (dBm !
O u tp u t P ow er (dB m )
O u tp u t P ow er (d B m )
O u tp u t P ow er (d B m )
%
J fo
O utput P ow er (d B m )
O u tp u t P ow er (d B m )
%
fo
sh o rt c irc u it @ fo
O u tp u t P ow er (dB m )
op en circ u it (§1 fo
O u tp u t P o w er (d B m )
O u tp u t P ow er (dB m
40 o h m @ fo
P o @ fo
25
P o @ fn
.211
Po @ fo
-206
P o @ fo
-208
Po (3) fo
-201
P o @ fo
119
P o @ fo
M l
P o @ fo
-2 0 9
P o @ fo
4 0 o h m @ 2fo
P o @ 2 fo
01
P o @ 2 fo
11 J
P n @ 2 fo
-2
P o@ 2fo
•It
P o@ 2fo
•J J
P o@ 2fo
• 112
P o@ 2fo
-1 0 1
P o @ 2 fo
•1 4 2
P o t3 2 fo
.4
SO o h m <3 J fo
P o @ lf o
J 9
P o @ lf o
•219
P o @ lf o
•217
P o @ lf o
-270
P o ® J fo
•270
P o @ J fo
-212
P o @ lf o
•215
P o @ J fo
•270
P o @ Jfo
270
201
204
50 o h m ( 3 fo
P o < 3 fo
48
P o @ fo
•209
P o @ fo
-204
P o @ fo
•207
P o @ fo
-202
P o @ fo
14 2
P o @ fo
112
P o @ fo
•208
P o @ fo
th o rt c irc u it ( 3 2fo
P o@ 2fo
J 8
P o @ 2 fo
• II 8
P o @ 2 fo
J 2
P o@ 2fo
•1 1 2
PQ@ 2fo
J
P o ^ if o
-1 8 7
P o@ 2fo
*11 9
P o @ 2 fo
•1 4 7
P o @ 2 fo
02
5 0 o h m @ J fo
P o ^ Jfo
56
P o @ ir o
•211
P o @ 3 fo
-214
P o@ 3fo
-270
P ot& Jfo
•270
P o ^ ir o
•223
P o @ ir o
•226
P o @ ir o
-270
P o g lf o
270
204
SO o h m <3 fo
P o @ fo
J 7
P o @ fo
•210
P o ( 3 fo
-205
P o ( 3 fo
-207
P o @ fo
-202
P o @ fo
1J 2
P o @ fo
12 J
P o Q fo
•208
P o @ fo
th o r l c irc u it @ 2 fo
P o @ 2 fo
16
P o @ 2 fo
•198
P o @ 2 fo
1J
P o@ 2fo
-1 9 4
P o@ 2fo
06
P o@ 2fo
-1 5 7
P o@ 2fo
•1 1 9
P o @ 2 fo
•22 4
P o @ 2 fo
•2
ih o rt c irc u it ( 3 J fo
P o @ J fo
04
P o @ Jfo
•216
P o @ J fo
•214
P o @ )fo
-270
P o @ )fo
•270
P o @ Jfo
•228
P o @ J fo
•211
P o @ J fo
•270
P o Q lfo
270
204
50 o h m <3 fo
P o < 3 fo
24
P o @ fo
•211
P o ( 3 fo
•206
P o @ fo
-208
P o @ fo
•2 0 J
P o @ fo
119
P o (§ fo
10 9
P o @ fo
•210
P o < 3 fo
50 o h m <3 2 fo
P o @ 2 fo
•10
P o @ 2 fo
•9 J
P o @ 2 fo
-2 2
P o@ 2fo
-1 0 3
P o@ 2fo
•1 8
P o @ 2 fo
•1 2 6
P o @ 2 fo
-1 0 6
P o @ 2 fo
-1 2 8
P « 3 2 fo
-5
s h o rt c irc u it <3 J fo
P o @ J fo
9 J
P n @ )fo
■21J
P o ^ Jfo
•222
P o @ lf o
-270
P o @ )fo
•270
P o @ J fo
•224
P o ^ Jfo
•241
P o @ lf o
-270
P o ^ Jfo
270
50 o h m ^
P o @ fo
09
P o @ fo
•212
P o @ fo
•206
P o @ fo
•210
P o @ fo
•204
P o Q fo
10 J
P o @ fo
94
P o @ fo
•211
P o { 3 f*>
204
o p e n circ u it @ 2 fo
P o @ 2 fo
16
P o @ 2 fo
•1 1 6
Po<2)2fo
•6 1
P o@ 2fo
•1 2 4
P o ^ 2 fo
•8 2
P o @ 2 fo
•1 4 4
P o@ 2fo
•1 2 6
P o @ 2 fo
•14 1
P o ^ 2 ro
•8 5
SO o h m ( 3 J fo
P o @ J fo
94
P o @ lf o
•226
P o @ lf o
•222
P o @ Jfo
•270
P©@ Jfo
-270
P o @ Jfo
•2 J 6
P o @ J fo
-242
P b ^ Jfo
•2 7 0
P o @ lf o
27 0
fo
40 o h m ( 3 fo
P o @ fo
2 1
P o @ fo
-211
P o @ fo
-205
P o @ fo
-209
P o @ fo
•201
P o @ fo
116
P o @ fo
106
P o (§ fo
-210
P o @ fo
204
o p e n c irc u it ( 3 2 fo
P o @ 2 fo
07
P o@ 2fo
-IJ
P o @ 2 fo
-1 J
P o@ 2fo
-IJ 9
P o@ 2fo
•J 1
P o@ 2fo
•1 5 8
P o @ 2 fo
-11 7
P o (3 2 fo
-1 5 7
P o (3 2 fo
-4 J
o p e n circ u it ( 3 J fo
P o @ lf o
-2 1 4
P o @ lf o
•215
P o @ J fo
-217
P o @ Jfo
:270
P o 0 )fo
-270
P o (§ J fo
-226
P o @ lf o
•246
P o $ lf o
-270
P o ^ lf o
270
50 o h m @ fo
P o fg fo
09
P o @ fo
•212
P o (ft fo
•206
P o @ fo
•210
P o ftfo
-204
P o @ fo
101
P o ® fo
95
P o (2 ffo
•211
P o @ fo
205
50 o h m 0 2 fo
P o ^ 2 fo
J J
P o @ 2 ro
-1 0 4
P o @ 2 fo
-5 4
P o4»2fu
•9 4
P o@ 2fo
-6 4
P o @ 2 fo
-1 6 8
P o 0 2 ro
•1 1 6
P o ^ 2 fo
-1 4 4
P o (3 2 fo
-9 8
o p e n c irc u it ( 3 J fo
P o ^ tf o
98
P n ^ lf o
•228
P o ^ Jfo
-220
P o @ lfo
-270
P o ^ lf o
-270
P o @ lf o
•219
P o @ Jfo
•241
P c y ^ J fo
-270
P o ^ lf n
270
Table 4.5.4 Doubler Simulations with Ideal Transmission Lines (1^= 0 volts, Pi„=0 dBm)
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
V g j-0 7 V
O u tp u l Nctw ock
P in - 0 dB m
5 0 o h m @ To
s h o d circ u it @ fo
o p en circ u it
V d s-J V
5 0 o h m @ 2fo
50 o h m
50 o h m @ 2fo
In p u t N etw ork
50 o h m @ J fo
50 o h m @ J fo
O u tp u l P o w er (d B m )
(§
2fo
50 o h m
O utpul h o w e r (d B m )
@
s h o d circuit
D
J fo
Q
50 oh m @
50 o h m ( § 2fo
50 oh m @ 2fo
o p en circ u it @ Jfo
o p en circ u it @ J fo
s h o d circ u it
O utput P ow er (d B m )
O utput P ow er (d B m )
fo
Po@
P o@ 2fo
04
P o @ 2 fo
08
P o ^ lf o
•5 2 9
P o @ lf o
-20 5
86
P o @ Jfo
P o @ fo
P o@ 2fo
•4 J
P o@ 2fo
•5 2
•60 1
P o @ lfo
•26 9
P o @ Jfo
-37 7
P o @ Jfo
•41 8
P o @ lf o
•54 3
P o @ fo
•1 3 5
P o @ fo
105
P o @ fo
9
P o @ fo
•21 2
P o @ fo
•156
P o @ 2 fo
64
P o @ 2 fo
0 J
P o 0 2 fo
72
P o ^ 2 fo
1 J
P o@ 2fo
•04
■42 8
Po@>3fo
-61
P o @ )fo
•24
P o @ Jfo
• J2
P o ^ Jfo
*J7 1
P o Q Jfo
-41 8
P o @ fo
•22 2
P o Q fo
•15
P o @ fo
8
P o @ fo
68
P o @ fo
•2 J 6
P o @ fo
• 17
P o@ 2fo
55
P o @ 2 fo
46
P o@ 2fo
•2
P o@ 2fo
59
P o@ 2fo
•0 9
P o@ 2fo
•2 2
P o @ lf o
•46
P o @ J fo
•73 7
P o @ Jfo
•21 J
P o @ 3 fo
•304
P o ^ lf o
•35 6
P o@ 3fo
*47
•20
P o(3) fo
•23
P o @ fo
• 177
P o @ fo
5 5
J 7
Po@
•I 7
P o@ 2fo
P o @ 2 fo
•0 2
P o@ 2fo
•5
P o@ 2fo
02
P o t^ 2 fo
•5 6
P o@ 2fo
•5 7
•27 6
P o @ Jfo
•43 I
P o ^ Jfo
•33 5
P o ^ Jfo
-4 7 9
•0 7
P o@ 2fo
50 o h m @ J fo
P o @ J fo
■ 147
P o @ J fo
•26 J
P o @ Jfo
P o @ fo
10 7
P o @ fo
•27 4
P o @ fo
•22
Po@
P o @ 2 fo
4 J
P o @ 2 fo
54
P o@ 2fo
4 5
P o (§ 2 fo
50 o h m @ J fo
P o @ J fo
•1 0 2
P o fg J fo
•22 6
P o @ lf o
•21
fo
50 o h m ( $ fo
P o @ fo
B4
Po@
•24 5
P o @ fo
s h o d circ u it @ 2 fo
P o @ 2 fo
21
P o @ 2 fo
32
P o@ 2fo
s h o d c irc u it @ J fo
P o @ J fo
•8 7
P o @ J fo
•22
P o @ Jfo
50 o h m @ fo
P o @ fo
58
P o @ fo
•27 4
50 o h m @ 2 fo
P o @ 2 fo
-1 )
P o @ 2 fo
•0 2
P o@ 2fo
P o @ J fo
• 17
P o @ J fo
•29 I
P o@ 3fo
P o @ fo
J 1
P o @ fo
•2 1 4
P o @ fo
P o @ 2 fo
•J 9
P o @ 2 fo
•J 6
P o @ 2 fo
•3 6
P o@ 2fo
50 o h m @ J f o
P o @ J fo
•in
P o @ J fo
•43 8
P o@ 3fo
•43 8
P o @ )fo
5 0 o h m (3| fo
•1 9 9
@ 2 fo
21
P o @ fo
5 7
P o @ fo
•27 6
P o @ fo
@2fo
P o @ 2 fo
•1 1
P o @ 2 fo
•1
P o@ 2fo
o p e n c irc u it @ J fo
P o @ J fo
• 165
P o @ J fo
•JO 2
P o @ lf o
•44 2
o p e n circ u it
O u tp u t P ow er (d B m )
06
P o @ 2 fo
50 o h m @ fo
O utput P o w er (d B m )
P o @ 2 fo
-0 9
o p e n c irc u it
O u tp u t P o w er (d B m )
•5 1
P o @ 2 fo
@ Jfo
J fo
P o@ 2fo
50 o h m @ 2fo
s h o d c irc u it
s h o d circ u it @ J fo
%
•26 1
Po@
fo
50 ohm @ 2fo
s h o d circ u it <§| J fo
o p e n circ u it
J fo
op en circ u it @ fo
P o g fo
P o @ fo
Po @
50 ohm ( § 2fo
4
•27 1
fo
s h o d c irc u it §
50 o hm @ 2fo
P o @ fo
P n @ fo
2 fo
fo
50 o h m ^ fo
56
596
@
fo
%
O utput P ow er (d B m )
O utput P ow er (dB m )
•25
P o @ fo
50 o h m 0 fo
fo
o pen circ u it (£) fo
50 o h m @ fo
s h o rt c irc u it
fo
50 o h m @ 2 f o
50 o h m @ fo
Po<3) fo
29
P o @ fo
-35 5
P o @ fo
•28 3
5 0 o h m @ 2 fo
P o @ 2 fo
•5 2
P o @ 2 fo
.5
P o@ 2fo
-4 8
o p e n c irc u it @1 J fo
P o @ J fo
•164
P o @ lf o
•29
P c @ J fo
• 17 J
Po@
Po@
fo
fo
-18
Po@
fo
•1 8 9
■192
P o@ 3fo
•55 2
P o ^ Jfo
-74
P o@ 3fo
P o ffllfo
-2 1 2
P o @ fo
•2 0 1
P o @ fo
29
P o @ fo
09
P o @ fo
•30
P o @ fo
•21 3
P n@ 2fo
•2 9
P o@ 2fo
•7 I
P o (§ 2 fo
-3 3
P o 0 2 fo
•64
P o @ 2 fo
•7 6
-6 4 3
P o@ 3fo
•66 9
P o @ Jfo
•28 1
P o@ 3fo
•50 6
P o ^ Jfo
-43 2
P o 0 3 fo
•53
•26 4
Po
@
1fo
fo
@fo
•19
•25 7
P o @ fo
• 178
P o @ fo
5 5
P o @ fo
J 5
P o@ 2fo
•05
P o @ 2 fo
-0 I
P o@ 2fo
-5 I
P o@ 2fo
0
P o@ 2fo
•4 5
P o @ 2 fo
-4 9
P o @ lf o
-55 4
P o@ J fo
-6 0 5
P o @ Jfo
•29 2
P o @ J fo
• 18 8
P o ^ Jfo
•41 8
P o ^ lf o
•5 1 8
■216
Po
fo
Po@
-28 J
P o @ fo
•20 2
P o @ fo
2 J
P o @ fo
08
P o Q fo
•29 5
P o @ fo
P o@ 2fo
•4 2
Pn(S)2fo
•IS
P o@ 2fo
•10 f
P o@ 2fo
-4 2
P o ^ 2 fo
•9 7
P o@ 2fo
•9 7
P o @ Jfo
•50 1
P o @ J fo
• 54 5
P o @ Jfo
-3 5 4
P o @ lf o
•3 1 4
P o tg l f o
-47 5
P o ^ Jfo
•51 9
Pn<3)
Table 4.5.5 Doubler Simulations with M icrostrip Transmission Lines (Vgr=-0.7 volts, Pi„=0 dBm)
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
M icro strip
V g f-0 V
O u tp u t N etw ork
P in - 0 dB m
50 o h m @ fo
sn o rt circ u it (S) fo
o pen c irc u it @1 fo
short circ u it @ fo
op en circ u it @ fo
50 ohm @ fo
50 o h m @ fo
short circ u it (£} fo
V d s-J V
30 o h m (S| 2fo
50 o h m @ 2 fo
30 ohm @ 2fo
50 o h m @ 2 f o
50 o h m @ 2fo
50 ohm @ 2fo
50 o h m @ 2fo
50 o h m
In p u t N etw ork
5 0 o h m @ J fo
50 o h m @ J fo
50 ohm @ Jfo
op en circ u it (3) J fo
o p en circ u it @ J fo
sh o rt circuit @ J fo
o p en circ u it
O u tp u t P ow er (d B m )
O u tp u t P ow er d B m )
O utput P o w er (d B m )
O utput P ow er (d B m )
P o @ fo
•22 9
P o @ fo
• 125
P o @ fo
12
P o @ fo
II 1
P o @ fo
• 193
P o 0 fo
-1 0 1
P o@ 2fo
• 114
P o ® 2 fo
•2 5
P o@ 2fo
• 109
Po@)2fo
•4
P o@ 2fo
•139
P o @ 2 fo
-in
P o @ 2 fo
• IS 1
P o@ 2fo
•6
P o @ J fo
-13 9
P o @ J fo
•26 J
P o Q Jfo
•23 4
P o @ lf o
•49 3
F o @ J fo
•55 4
P o ^ Jfo
•28 9
P o @ J fo
•JJ 9
P o @ J fo
•3 9 1
P o @ J fo
•36 3
P o @ fo
14 7
P o @ fo
.1 8 4
Po@ To
•1 4 4
P o @ fo
•21 J
P o(S ) fo
•II 1
P o @ fo
14 2
P o @ fo
132
P o @ fo
-1 7 5
P o @ fo
•136
P o @ 2 fo
12 5
P o @ 2 fo
-IJ 1
P o @ 2 fo
18
P o@ 2fo
• 104
P n @ 2 fo
28
Po(S|2fo
• 17 1
P o @ 2 fo
•106
P o @ 2 fo
•17
P o @ 2 fo
•2 5
P o @ J fo
*8 4
P o @ 3 fo
•184
P o @ J fo
•2 5 6
P o @ Jfo
-41
P o @ 3 fo
•52
P o@ 3fo
•22
P o @ Jfo
•2 8
P o @ Jfo
•3 1 8
P o 0 3 fo
•34 5
• 139
5 0 o h m @ J fo
50 o h m @ J fo
O utput P ow er (dB m )
•15 I
P o @ 2 fo
2 fo
O u tp u t P ow er (d B m )
2fo
short circ u it 0 J fo
P o @ fo
50 o h m @ 2 f o
@
O u tp u t P ow er (dB m )
50 oh m ^
sh o rt circ u it @ J fo
-2 0 2
P o (3 fo
3 0 o h m (SI fo
O u tp u t P o w er (d B m )
J fo
o p en circ u it @ fo
2fo
P o @ fo
5 0 o h m @ fo
sh o rt c irc u it
O u tp u t P ow er (d B m )
%
Q
12 5
•14 3
P o @ fo
13 6
P o @ fo
•1 9 2
P o @ fo
• 146
P o @ fo
•2 1 9
P o @ fo
117
P o @ fo
IJ 2
P o @ fo
12 3
P o @ fo
•18 3
P o @ fo
2f<»
P o @ 2 fo
-1 1 5
P o @ 2 fo
-19
P o @ 2 fo
05
P o@ 2fo
•153
P n @ 2 fo
04
P o@ 2fo
•17 1
P o@ 2fo
• 112
P o@ 2fo
•22 8
P o @ 2 fo
•J
s h o rt c irc u it @ 3fo
P o @ J fo
9 J
P o @ J fo
•22 4
P o @ J fo
•21 8
P o @ Jfo
•45
P o @ J fo
•5 9 6
P o@ 3fo
•24 8
P o @ J fo
•28 8
P o Q Jfo
•35 J
P o @ )fo
•32 3
30 o h m @ fo
P o @ fo
12 6
P o @ fo
•20 2
P o @ fo
•15
P o @ fo
•22 9
P o @ fo
• 12 J
P o @ fo
12 1
P o ^ fo
II 1
P o @ fo
• 193
P o @ fo
•1 4 2
50 o h m @ 2 fo
P o @ 2 fo
-1 0 3
P o @ 2 fo
• 113
P o @ 2 fo
•2 6
P o@ 2fo
•II 1
P o @ 2 fo
•4
P o@ 2fo
•1 3 7
P o @ 2 fo
•1 0 4
P o @ 2 fo
• 147
P o @ 2 fo
•5 9
sh o rt c irc u it @ J fo
P o @ J fo
-1 7 5
P o ^ lf o
■29 7
P o @ J fo
•29 5
P o @ Jfo
-53
P o @ J fo
•5 J4
P o @ Jfo
•33 9
P o @ J fo
-36 5
P o O lfo
•4 2 8
P o @ 3 fo
•41
30 o h m @ fo
P o @ fo
112
P o @ fo
•2 1 6
P o @ fo
• 156
P o @ fo
24 4
P o @ fo
•13 1
P o @ fo
106
P o @ fo
P o @ fo
•2 0 7
P o @ fo
•1 4 7
P o @ 2 fo
*114
P o @ 2 fo
•116
P o @ 2 fo
-6 8
P o@ 2fo
II 9
P o@ 2fo
•S 3
P o @ 2 fo
•146
P o@ 2fo
• 12 1
P o @ 2 rn
•1 4 8
P o@ 2fo
•9 6
P o @ J fo
. ||9
P o @ )fo
•32 4
P o @ 3 ro
•32 3
P o @ Jfo
54 6
P o @ J fo
•6 0 4
P o @ Jfo
•32 7
P o @ 3 fo
-3 9 8
P o ^ Jfo
•45 2
P o (g )f o
•4 2 6
•1 3 9
3 0 o h m @ fo
sh o rt c irc u it
o p e n c irc u it
@
%
2 fo
50 o h m @ J fo
•
97
P o @ fo
12 7
P o @ fo
•20 2
P o @ fo
• 148
P o @ fo
22 9
P o @ fo
• 12 1
P o @ fo
122
P o @ fo
112
P o ( § fo
• 19 3
P o Q fo
2fo
P o @ 2 fo
-9 4
P o @ 2 fo
• II I
P o @ 2 fb
•I
P o@ 2ro
II 2
P o @ 2 fo
•2 9
P o 0 2 fo
-13 1
P o @ 2 fo
•105
P o ^ 2 fo
•14 3
P o@ 2fo
-4
o p e n c irc u it @ J fo
P o @ J fo
.1 3 5
P o @ J fo
•26 1
P o ^ tr o
•23 2
P o @ Jfo
30 2
P u @ 3 fo
•52 2
P o @ Jfo
•29 4
P o @ Jfo
• 33 1
P o Q Jfo
•392
P o O lfo
• 34
II
5 0 o h m 0 fo
o p e n c irc u it
@
P o @ fo
•25
P o @ fo
•1 5 8
P o @ fo
24 4
P a fQ tf n
•I) 3
P o @ fo
10 5
P o @ fo
96
P o @ fo
-2 0 7
P o @ fo
• 15
30 o h m @ 2fo
P o @ 2 fo
.1 2 1
P o@ 2fo
• 164
Po*ft2fo
-6 1
Po(Sf2fo
109
P o(3l2fo
1 3
P n@ 2fo
-1 6 2
P o @ 2 fo
•1 1 9
P o @ 2 fo
•1 4 3
P o@ 2fo
•1 0 2
o p e n c irc u it @ J fo
P o ^ Jfo
-18 8
P o @ J fo
-45 2
P o @ 3 fo
•27 7
P o @ Jfo
•57
P o @ )fo
•55 1
P o @ Jfo
•J 5 6
P o @ J fo
-J B 4
P o ^ Jfo
-4 7 J
P o (§ J fo
•J 9 5
30 ohm
@
fo
P o @ fo
Table 4.5.6 Doubler Simulations with M icrostrip Transmission Lines ( VKs=0 volts, Pi„-0 dBm)
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
M icro strip
V g i" * 0 7 V
O u tp u l N etw ork
P m " - 4 dB m
5 0 ohm 0 fo
sh o d circ u it 0 fo
SO o h m 0 fo
shod e ir c u it0 f o
o p e n circuit 0 fo
SO ohm 0 fo
o p en circ u it 0 fo
s h o d circ u it 0 fo
o p en circ u it S
V d s-J V
50 o h m 0 2 fo
5 O o h m 0 2 fo
50 o h m 0 2fo
50 o h m 0 2 f o
50 o h m 0 2fo
5 0 ohm 0 2fo
50 o h m 0 2fo
50 oh m 0 2fo
50 o h m 0 2fo
50 o h m 0
o p en circ u it 0 J fo
o p en circ u it 0
O utput P ow er (d B m )
O u tp u t P o w er (d B m )
In p u t N e tw o tk
s h o d circuit 0
SO o h m 0 J f o
SO o h m 0 J fo
s h o d circ u it 0
6 u tp u t P o w e r (d B m )
O u tp u t P o w er (ribm ^
O u tp u t P o w er (d B m )
J fo
J fo
3fo
O u tp u t P ow er (d B m )
O utput P ow er (d B m )
J fo
to
o p en circ u it 0 J fo
s h o d circ u it 0
O u tp u t P ow er (d B m )
d u lp u t P o w er (d B m )
J fo
50 o h m 0 To
P o 0 fo
OS
P o 0 fo
•J 2 7
P o 0 fo
0
P o 0 fo
• 31 6
P o 0 fo
•25 1
P o 0 fo
•1 5
P o 0 fo
•22 8
P o 0 fo
•J5 9
P o 0 fo
•24 2
5 O o h m 0 2 fo
P o 0 2 fo
*67
P o 0 2 ro
-6 1
P u 0 2 fo
•108
P o 0 2 fo
-10
P o 0 2 fo
•68
P o 0 2 fo
•4 9
P o 0 2 fo
•5 1
P o 0 2 fo
-4 8
P o 0 2 ro
•II 1
50 o h m 0
P o 0 1 fo
•21 3
P o 0 3 fo
• 34 3
P o @ 3 fo
•33 3
P o 0 3 fo
•48
P o 0 Jfo
•4 6 6
P o 0 Jfo
•43 4
P o 0 3 ro
•65 9
P o 0 3 fo
-6 0 6
P o 0 3 fo
•60 2
•|9 9
J fo
5 0 o h m 0 fo
P o 0 fo
6
P o 0 fo
•269
P o 0 fo
58
P o 0 fo
•25 9
P o 0 fo
•20 8
P o 0 fo
45
P o 0 fo
• 182
P o 0 fo
•29 5
P o 0 fo
s h o d c irc u it 0 2 fo
P o 0 2 fo
6
P o 0 2 fo
1
P o 0 2 fo
* 42
P o 0 2 fo
-3 2
P o 0 2 fo
•I
P o 0 2 fo
3
P o 0 2 fo
15
P o 0 2 fo
4 3
P o 0 2 fo
•5 2
50 ohm 0
P o 0 3 fo
*137
P o 0 3 fo
-2 6 6
P o 0 3 fo
•25 5
P o 0 3 fo
-3 9 4
P o 0 3 fo
-34 5
P o 0 3 fo
•36 2
P o 0 Jfo
-61 9
P o Q lfo
-49
P o 0 Jfo
•46 3
J fo
50 o h m 0 fo
P o 0 fo
-4
P o 0 fo
•29 9
P o 0 fo
27
P o 0 fo
•28 9
P o 0 fo
•22 8
P o 0 fo
15
P o 0 fo
•20 4
P o 0 fo
•J 2 7
P o 0 fo
•22
s h o d c irc u it @ 2fo
P o 0 2 fo
• II 1
P o 0 2 ro
•2 2
P o 0 2 fo
•7 4
P o 0 2 fo
•6 4
P o 0 2 fo
•3 6
P o 0 2 ro
03
P o 0 2 fo
•1
P o 0 2 fo
08
P u 0 2 fo
•7 9
s h o d c irc u it 0
P o 0 Jfo
•28 2
P o 0 3 fo
• 28 6
P o 0 3 fo
•27 1
P o 0 Jro
•41 6
P o 0 3 fo
•41 6
P o 0 3 fo
• 37 3
P o 0 3 fo
•72
P o 0 Jfo
•5 0 2
P o 0 3 fo
•52 9
J fo
5 0 o h m 0 fo
P o 0 fo
02
P o 0 fo
•33
P o @ fo
-0 1
P o 0 fo
•31 9
P o 0 fo
•25 4
P o 0 fo
-1 9
P o 0 fo
•23 1
P o 0 fo
•3 6 3
P o 0 fo
•24 5
50 o h m 0
P o 0 2 fo
•7 1
P o 0 2 ro
•6 I
P o 0 2 fo
•106
P o 0 2 fo
•9 5
P o 0 2 fo
•7 6
P o 0 2 fo
•5 6
P o 0 2 fo
•6 1
P o 0 2 fo
•4 4
P o 0 2 fo
•116
s h o d circ u it 0 J fo
P o 0 1 fo
-23 7
P o 0 3 fo
•34 9
P o 0 3 fo
•32 7
P o 0 3 fo
•45 8
P o 0 Jfo
-4 3 8
P o 0 3 fo
•53 8
P o 0 3 fo
•77 4
P o 0 3 fo
•65 1
P o 0 3 fo
•54
2fo
50 o h m 0 fo
P o 0 fo
•2 4
P o 0 fo
•35 8
P o 0 fo
•28
P o 0 fo
• 34 7
P o 0 fo
•27 7
P o 0 fo
-4 6
P o 0 fo
• 25 6
P o 0 fo
•1 9 I
P o 0 fo
•26 8
o p en c irc u it 0 2 fo
P o 0 2 fo
• 10 1
P n 0 2 fo
•9 4
P o 0 2 fo
•1 3 4
P o 0 2 fo
•1 2 8
P o 0 2 fo
•10 1
P o 0 2 fo
•9 1
P o 0 2 fo
•9
P o 0 2 fo
82
P o 0 2 fo
•1 3 9
50 o h m 0 J f o
P o 0 Jfo
•26 2
P o 0 3 fo
•39 7
P o 0 Jfo
•36
P o 0 3 fo
• 50 7
P o 0 3 fo
•5 0 6
P o 0 3 fo
•57 5
P o 0 3 fo
•75 2
P o 0 Jfo
•69 5
P o 0 3 fo
•60
•24 4
P o 0 fo
02
P o 0 fo
•33 1
P o 0 fo
0
P o 0 fo
•32
P o 0 fo
•25 1
P o 0 fo
•2
P o 0 fo
•23 3
P o 0 fo
• 36 5
P o 0 fo
o p e n c irc u it 0
2fo
P o 0 2 ro
•7
P o 0 2 fo
-6 7
P o 0 2 fo
• 108
P o 0 2 fo
•10 1
P o 0 2 ro
•7 1
P o 0 2 fo
•5 7
P o 0 2 fo
-6
P o 0 2 fo
-5 4
P o 0 2 fo
•II
o p en c irc u it 0
J fo
P o 0 Jro
-23 1
P o 0 Jfo
-37 2
P o 0 3 fo
• 35 8
P o 0 3 fo
•50 2
P o 0 Jfo
*49 6
P o 0 3 fo
•4 6 2
P o 0 3 fo
•61 7
P o 0 > ro
*66 1
P o 0 3 fo
•58
50 o h m 0 fo
50 o h m 0 fo
P o 0 fo
•2 6
P o 0 fo
•3 5 9
P o 0 fo
■3 2
P o 0 fo
•35 1
P o 0 fo
•27 7
P o 0 fo
•4 7
P o 0 fo
• 25 6
P o 0 fo
•19 2
P o 0 fo
•27
50 o h m 0 2fo
P o 0 2 fo
•II 1
P o 0 2 fo
• 109
P o 0 2 ro
• 158
P o 0 2 fo
• IS 3
P o 0 2 fo
•II 1
P n@ 2fo
-9 7
P o 0 2 fo
•9 7
P o 0 2 fo
•104
P n 0 2 fo
•1 5 8
P o 0 3 fo
•25 1
P o 0 3 fo
• 38 5
P o 0 3 fo
•45 3
P o 0 3 fo
•57 6
P o 0 3 fo
•46 5
P o 0 3 fo
•39 3
P o 0 1 fo
•62 9
P o 0 3 fo
•58 3
P o 0 3 fo
•62 1
o p en c irc u it 0
J fo
Table 4.5.7 Doubler Simulations with M icrostrip Transmission Lines (Vfpr-0.7 volts, Pin=-4 dBm)
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
M ic rm liip
V g i-0 V
O u tp u t N e tw o ti
P in a * 4 d B m
50 ohm
V d s -3 V
5 0 ohm @ 2fo
Input N etw ork
fo
®
sh o rt circ u it @ fo
o p en circ u it @ fo
s n o n circ u it @ fo
o p e n circ u it @ fo
50 ohm @ fo
50 ohm 0 fo
s h o n circ u it 0 fo
o p en circ u it
50 o h m @ 2fo
5 0 o h m @ 2fo
50 o hm ( § 2fo
50 o h m @ J fo
50 o h m ( § 2fo
50 o h m @ 2fo
50 o h m @ 2fo
50 o hm @ 2fo
5 0 o h m @ J fo
o p en circ u it @ J fo
o p en circuit @ J fo
short circ u it
o pen circ u it @ J fo
s h o n c irc u it @ J fo
s h o n circ u it 0
O u tp u l P ow er (d B m )
O utput P ow er (d B m )
O u tp u t P ow er (d B m )
O utput P ow er (d b m )
O u tp u t l>owcr (d B m )
O u tp u t P o w er (d B m )
b u tp u t h> w er (d ftm )
5 0 o hm @ J fo
50 o h m
6 u tp u t P o w er (d b m )
O u tp u t P ow er (d B m )
J fo
®
Jfo
78
To
J fo
P o @ fo
♦2J J
P o @ fo
*175
P o @ fo
•26
P o @ fo
• 15
P o @ fo
87
P o g jl f o
P o @ fo
•2 2 1
P o Q fo
• 166
50 o h m @ 2 fo
P o @ 2 fo
P o@ 2fo
*14 5
P o @ 2 fo
*172
P o@ 2fo
•14 2
P o@ 2fo
• 174
P o @ 2 fo
•181
P o @ 2 fo
•15 1
P o ® 2 fo
•1 8 2
P o Q 2 fo
•20 8
5 0 o h m @1 J fo
P o @ 3 fo
P o @ )fo
•J 8 7
P o @ lf o
-4 2 6
P o @ J fo
•61 3
P o @ Jfo
•6 8 6
P o@ 3fo
•381
P o @ J fo
-44
P o @ J fo
•51 7
P o @ J fo
•54
50 ohm
®
fo
P o @ fo
9 I
®
®
5 0 o h m (§1 fo
Po(fl) fo
P o @ fo
*20 2
P o @ fo
• 158
P o @ fo
•22 9
P o ($ fo
•132
P o @ fo
12
P o @ fo
109
P o Q fo
•19 1
P o @ fo
•15
s h o rt circ u it @ 2 fo
P o @ 2 fo
P o @ 2 fo
• 169
Po@)2fo
•6 8
P o@ 2fo
•1 4 2
P o@ 2fo
•5 8
P o@ 2fo
• 167
P o ^ 2 fo
•1 2 3
P o@ 2fo
•20 7
P o ^ 2 fo
•II 1
50 o h m @ J fo
P o @ )fo
P o @ 3 fo
*29 5
P o @ )fo
•31
P o 0 3 fo
•5 1 8
P o@ 3fo
•55 7
P o@ 3fo
*J2 5
P o @ Jfo
•J7 6
P o ^ lf o
•42 5
P o @ )fo
*45 J
50 ohm
P o @ fo
P o @ fo
*21 9
P o ® fo
• 166
P o @ fo
•24 7
P o (3 )f o
•14 1
P o @ fo
10 1
P o @ fo
9 1
P o @ fo
•21
P o @ fo
158
P o@ 2ro
-16 1
P o @ 2 fo
-12 1
P o ^ 2 fo
11 1
P o@ 2fo
•1 0 7
P o@ 2fo
•17 7
P o @ 2 fo
-1 2 9
PD@ 2fo
-20
P o@ 2ro
159
P o @ )fo
-14 5
P o @ )fo
-1 1 9
P o @ )fo
• 57 5
P o @ Jfo
•75 9
P o @ Jfo
• J5 7
P o @ 3 fo
• 39
P o @ J fo
-47 5
P n ^ lf o
49 2
16)
@
fo
s h o rt circ u it (fit 2fo
P o @ 2 fo
s h o rt circ u it
P o @ )fo
®
J fo
122
-14
P o @ fo
•21 J
P o @ )fo
•1 7 2
P o @ fo
•26 1
P o @ fo
•1 4 1
P o @ fo
88
P o @ fo
78
P o @ fo
•22 4
P o @ fo
50 o h m @ 2fo
P o @ 2 fo
P o @ 2 fo
*147
P o ® 2 fo
• 162
P o 0 2 fo
•1 4 8
P o@ 2fo
• 169
P o@ 2fo
•1 8 5
P o@ 2fo
•1 5 7
P o @ 2 fo
*179
P o@ 2fo
19 5
s h o rt circ u it @ J fo
P o @ J fo
P o@ 3fo
•J9 |
P o (£ )f o
•18 5
P o @ Jfo
•61 8
P o @ )fo
•63
P o@ 3fo
•40 9
P o @ 3 fo
•44 4
P o @ lf o
•52 7
P o ^ Jfo
518
5 0 oh m
®
fo
P o @ fo
5 0 o h m @ fo
o p e n c irc u it
®
P o @ fo
*25 1
P o @ fo
• 18 3
P o @ fo
•27 8
P o @ fo
•159
P o 0 fo
P o @ fo
62
P o @ fo
•24 2
P o ^ fo
174
P o @ 2 fo
P o @ 2 fo
*174
P o @ 2 fo
•20 9
P o@ 2fo
• 179
P o@ 2fo
•21 8
P o@ 2fo
•209
P o @ 2 fo
•186
P o<g2fo
•20 4
P o@ 2fo
2 )9
P o @ lf o
P o @ J fo
-4 J 1
P o @ 3 fo
-4 6 1
P o @ Jfo
•65
P o @ Jfo
*71 5
P o @ lf o
-41 4
P o @ J fo
-4 9 2
P o ^ ir o
•56 4
P o Q lfo
58 7
P o @ fo
2fo
50 o h m @ J f o
92
77
7 1
P o @ fo
*2J J
Po
fo
• 169
P o @ fo
•26 1
P o @ fo
*145
P o @ fo
9
P o @ fo
79
P o ^ fo
-22 4
P o @ fo
16 1
2fo
P o @ 2 fo
P o @ 2 fo
•14 J
P o @ 2 fo
•1 5 7
P o@ 2fo
• 146
P o@ 2fo
• 17
P o@ 2fo
•1 7 5
P o @ 2 fo
• 152
P o @ 2 fo
•1 7 3
P o @ 2 fo
186
o p e n circ u it @ J fo
P o @ 3 fo
P o @ J fo
•3 1 2
P o @ 3 fo
-4 0 3
P o @ )fo
•61 8
P o@ 3fo
*67
P o@ 3fo
•39 3
P o @ lf o
*42 9
P o @ lf o
•51 8
P o Q lfo
51 3
5 0 o h m @ fo
o p e n circ u it
®
P o @ fo
94
Q
P o @ fo
•30 3
P o (5) fo
•186
P o @ fo
•27 8
P o @ fo
•1 6 2
P o @ fo
7
P o @ fo
61
P o @ fo
•24 1
p o ^ fo
177
50 o h m @ 2 fo
P o @ 2 fo
P o @ 2 fo
•1 6 4
P o @ 2 fo
•22 J
P o@ 2fo
•1 7 5
P o@ 2fo
-2 J
P o@ 2fo
-22 9
P o@ 2fb
•186
P o 0 2 fo
•20 8
P o@ 2fo
26 6
o p en circ u it @ J fo
P o@ J fo
P o @ lf o
-45 2
P o @ lf o
*45 J
P o @ lf o
•67 4
Po(S)Jfo
-695
P o @ )fo
•43 8
P o @ J fo
•47
P o @ 3 fo
•58 1
P o @ lf o
57 5
50 ohm
®
fo
P o @ fo
75
Table 4.5.8 Doubler Simulations with Microstrip Transmission Lines (VfprO volts, Pin=-4 d B m )
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
M atched at Input
V g s » -0 7 V
O u tp u l N etw ork
P in * 0 dB m
VO o h m @ fo
s h o n circ u it ( § fo
o p en circ u it § fo
short circ u it (§) fo
op en circ u it ( 5 fo
50 o h m ( § fo
>0 o h m ( g fo
th o rt circ u it <& fo
V d s-J V
50 o h m @ 2fo
VO o h m <9 2fo
50 oh m @ 2fo
50 o h m
50 oh m ( 9 2fo
5 0 o h m @ 2 fo
50 o h m (3 )2 (0
50 o h m ( 9 2 f o
50 o h m ( 9 2fo
Input N etw ork
VO o h m @1 J fo
VO oh m
50 o h m @ Jfo
o p en circ u it ( 9 J fo
op en circuit ( 9 J fo
s h o n circ u it ( 9 J fo
o p en circ u it ( 9 J fo
s h o n circ u it ( 9 J fo
s h o n circ u it 0 J fo
O u tp u t P ow er (d B m )
%
J fo
O u tp u t P ow er (d B m )
O u tp u t P o w er (d B m )
@
2fo
O utput b o w e r (d b m )
O utput P ow er (dB m )
O utput b o w e r (d B m )
O u tp u t P ow er (d b m )
o p en circ u it ( 9 fo
O u tp u l b o w e r (d b m )
O u tp u t P ow er (d B m )
VO o h m ( 9 fo
Po
fo
V 96
P o @ fo
-217
P o @ fo
-210
P o @ fo
-215
P o @ fo
-201
P o < 9 fo
5V
P o @ fo
4 1
P o @ fo
-216
P o Q fo
VO o h m @ 2fo
P o ^ 2 fo
-0 9
P o @ 2 fo
-0 J
P o @ 2 fo
-0 7
P o @ 2 fo
0 2
P o @ 2 fo
0 4
P o @ 2 ro
-J 9
P o @ 2 fo
01
P o @ 2 (o
) J
P o @ 2 fo
*4 2
VO o h m @ J fo
P o @ )fo
-14 7
P o @ )fo
221
P o @ J fo
-2 3 )
P tX g Jfo
-270
P o @ J fo
-270
P o @ )fo
-2 J 2
P o @ J fo
-217
P o @ J fo
-270
P o @ J fo
-270
%
O u tp u l P o w er (d B m )
O u tp u t P ow er (d B m )
O u ip u l P o w er (d B m )
O utput P ow er (d B m )
O utput P ow er (d B m )
O utput P ow er (d B m )
M atch e d @ fo
P o @ fo
IJ
P o @ fo
-65 7
P o @ fo
-62 3
P o (U| fo
-65 7
P o @ fo
-62 V
s h o n circ u it @ 2fo
P o @ 2 fo
6 5
P o @ 2 fo
1
P o @ 2 fo
V
P o @ 2 fo
16
P o @ 2 fo
V4 ohm * @ J fo
P o @ lf o
-6 7
P o @ )fo
-4 1
P o @ )fo
-7 9
Po@ H o
-92 1
P o @ )fo
O utput P o w er (d B m )
O utput P ow er (d B m )
-209
O utput P ow er (d B m )
d
1J
P o @ fo
IJ
P o @ fa
-65 6
P o ( 9 fo
5 2
P o @ 2 fo
61
P o $ 2 fo
6 9
P o @ 2 fo
74
P o @ 2 fo
41
-92 2
P o @ 3 fu
-87 6
Po@ U o
-94 9
P o Q Jfo
14 7
P o @ )fa
92 6
Pd ^ T
*62 2
Table 4.5.9 Doubler Simulations Matched on Input with Microstrip Transmission Lines (Vfp=-0. 7 volts, Pin=0 d B m )
K
VO
M atched at Input a n d O u tp u l
V gs • ■
0 7 V
O u ip u l N ctw m k
(9 fo
<9 2fo
th o rt circ u it (9 J fo
P in a 0 dB m
50 o h m @ fo
s h o rt circ u it ^ fo
o p en circ u it $ fo
short circ u it @ fo
o p en circ u it @ fo
36 o h m s
@
fo
17 o h m s ( J f o
s h o rt circ u it @ fo
o p en circ u it
V d s-J V
50 o h m @ 2 f o
M atched
M atched @ 2fo
M atched <9 2fo
M atched ( 9 2fo
M atched
@
2fo
M atched
M atched @ 2fo
M atched
In p u t N etw ork
50 o h m
(9 J fo
O u tp u t P ow er (d B m )
@
2fo
(9 J fo
1 5 o h m s @ J fo
15 ohm s
O u tp u t P ow er (d B m )
O u tp u l P ow er (d B m )
o p en circ u it
(9 J fo
op en circ u it
O utpul P ow er (d R m )
(9 J fo
O utput P ow er (d B m )
%
2fo
sh o rt circ u it ( 9 J fo
short circ u it @ Jfo
o p en circ u it ( 9 J fo
O utput P ow er (dB m )
O u tp u t P ow er (d B m )
O u tp u l b o w e r (d B m )
O u tp u t P ow er (d B m )
M atched @ fo
P o ^ fo
14 4
P o @ fo
70 2
P o @ fo
-6 1 9
P o @ fo
*70
P o @ fo
*615
P o @ fo
121
P o @ fo
12 5
P o ( 9 fo
-70
P o ( 9 fo
s h o n circ u it @ 2fo
P o @ 2 fo
6 4
P o @ 2 fo
10 1
P o @ 2 fo
4 7
P o@ 2fo
10 4
P o @ 2 fo
5
P o@ 2fo
91
P o @ 2 fo
7 J
P o @ 2 fo
9 5
P o @ 2 fo
5 I
P n ta J f o
-2 9
P o @ )fo
-B 1
P o @ J fo
-16 2
P o @ J fo
-8 9 5
P o @ J fo
-9 9 )
P o @ J fo
-9 5 1
P o @ 1 fo
861
P o ^ Jfo
-96 7
P o @ J fo
110)
54 ohm *
(9 J fo
Table 4.5.10 Doubler Simulations Matched on Input and Output with Microstrip Transmission Lines
( Vrtt-O. 7 volts, Pin~0 d B m )
-60 6
Tables 4.5.1 and 4.5.2 show the output power simulations where lumped
elements, however, not always practical values, were utilized to present the various
impedances to the input and output ports of the HEMT for Vg; = 0 volts and vgs=vP. As an
example, Table 4.5.2 shows an analysis with the HEMT biased at V* =0 volts. The table
illustrates the wide variation in the conversion gain based on resistive termination and
pole/zero placement for both Nj (ZsO as the input network and V? (Znz) as the output
network. In particular, it is seen that if the device is driven from a Ni which admits a 50
ohm real impedance presented to the gate and is terminated in a real 50 ohm impedance
for N 2 seen from the drain that the conversion gain will have a value of-10.1 dB for
operation as a doubler or —13.9 dB as a. tripler and with all due consideration to unwanted
harmonics. However, if Nj presents an impedance to the gate of the HEMT of 50 ohms
at f0, a pole at 2f0 and 50 ohms at 3f„ and N 2 presents a pole at fo, 50 ohms at 2f0 and a
ploe at 3f0, the conversion gain increases 8.4 dB to a value o f-1.7 dB.
In efforts to realize impedances with transmission lines, ideal transmission lines
were used to present the various impedances to the HEMT. Ideal transmission lines were
employed to present ideal impedances to the HEMT without considering losses to obtain
a “best-case” scenario before proceeding to practical microstrip lines. Tables 4.5.3 and
4.5.4 show the simulations for the output power of the doubler for VgS
0
volts and Vgs=Vp
utilizing ideal transmission lines. Variations in the conversion gain, as observed in the
previous matrix simulation tables, are observed in the simulations which utilize ideal
transmission lines as well. Doubler simulations utilizing practical microstrip lines are
considered next. Figures 4.5.5 - 4.5.8 show simulations utilizing microstrip lines for
230
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
=0 v and VwTV, for input powers o f 0 and -4 dBm. Additional comments on the
microstrip line simulations will be made in the ensuing discussions.
A perusal of the matrix tables (specifically Tables 4.5.5 through 4.5.8) provides
requirements for both input and output network impedances to provide optimal
conversion gain performance for a frequency doubler. In Table 4.5.5, optimum
conversion gain is shown to be 8.6 dB (row 2, column 4) where the required input
termination is a short-circuit at the second harmonic frequency and the output network
consists of an open-circuit termination at the third harmonic frequency along with a
short-circuit termination at the fundamental. After the optimal impedances {Z^i and Zsi)
have been determined, the impedances have to be synthesized in order to construct a
physical frequency doubler to evaluate the efficacy o f the results. In this analysis, the
synthesis is performed using microstrip transmission lines. Figures 4.5.8 and 4.5.9 show
the transmission response of the input network (short-circuit at the second harmonic) and
the output network (short-circuit at the fundamental and an open-circuit at the third
harmonic), respectively. The measured and simulated response for IS2/I indicate that the
desired short-circuit effect is established at the second harmonic (6 GHz) for Z,v/ as
shown in Figure 4.5.8 and similarly for the measured and modeled response o f Zm in
Figure 4.5.9.
4.5.2.2
Experimental results
This section presents experimental results which will corroborate the analysis and
conclusions of the previous section o f this analysis. A comparison is made between a
231
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
multiplier designed using a conventional approach and one using the conclusions of this
analysis.
Several conventional doubler designs have employed a short-circuit termination at
the second harmonic frequency on the input network and a short-circuit termination at the
fundamental on the output network. The response of a typical realization of such a circuit
for the input network o f the experimental conventional doubler design (to be presented
below) is shown in Figure 4.5.8. These measured and modeled results for JS21/indicate
that the desired short-circuit effect is established at the second harmonic frequency (6
GHz) for this input circuit. Figure 4.5.9 shows the transmission ^ //freq u e n cy response
o f the output circuit for the conventional design. The short-circuit effect is obtained at
the fundamental frequency (3 GHz). The complete experimental doubler circuit of the
traditional doubler design was realized on 20-mil duroid and is shown in Figure 4.5.10.
The measured and simulated results for the HEMT doubler realization utilizing this
conventional approach realized on 20-mil duroid are shown in Figure 4.5.11. This circuit
is seen to have a conversion gain o f approximately 5 dB around the design doubler center
frequency o f 3 GHz, rising to 6.7 dB at 3.08 GHz.
232
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
-10
i
-15 -
(8P) US
-20
-25
-30
-35
-40
-45
-50
.
i
_
i
:
1
^
Simulated
M easured
3
4
6
5
7
9
8
Frequency (GHz)
Figure 4.5.8 Transmission Magnitude for Input Network ( Z s i)
-10
-15
(Hp) | j S
-20
-25
-30
-35
Sim ulated
M easured
-40
-45
3
4
5
6
7
8
9
Frequency (GHz)
Figure 4.5.9 Transmission Magnitude for Output Network (Z^)
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
f= 2 fo
0=180
0=90
Figure 4.5.10 Traditional Doubler Design Schematic
Conversion Gain (dB
8
_
7 _
6
5
4
3
2
Simulated
Measured
1
0
2.8
2.9
3
3.1
3.2
Fundamental Frequency (GHz)
Figure 4.5.11 Conversion Gain o f HEMT Doubler Utilizing Traditional Design
Techniques (Pin=0 d B m , V gs= -0 . 7 v)
234
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
9 8
Conversion Gain (dB)
7
6
5
4
3
Simulated
Measured
0
2.8
2.9
3.1
3
3.2
Suppression (dBc)
3
Fundamental Frequency (GHz)
4.5.12 Conversion Gain of HEMT Doubler Using Unified Technique
(Pm=0 d B m , VgS=—0 .7 v o lts, Vlb= 3.0 v o lts )
-20
^
-30 .
-40 y "
Sim ulated
fo
-50 i '
-60 r
■M easured @ fo
-70 :
. M easured
Sim ulated i2j 3fo
3 fo
-80 —
2.8
2.9
3
3.1
3.2
3.3
Fundamental Frequency (GHz)
Figure 4.5.13 Harmonic Suppression of HEMT Doubler Using Unified Technique
(Pin=0 d B m , Vg=-Q. 7 v o lts, V^=3.0 v o lts )
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
The performance of the frequency doubler designed using the optimization
techniques discussed in this section is shown in Figures 4.5.12 and 4.5.13. These figures
show the measured and modeled conversion gain and harmonic suppression versus the
fundamental frequency, respectively. This technique reveals that optimum performance is
achieved with the input network terminated with a short circuit at the second harmonic
frequency. On the output network, a short circuit at the fundamental frequency, 62 ohms
at the second harmonic frequency, and an open circuit termination at the third harmonic
frequency yields optimum performance. The transmission /S'?//frequency response of this
output network is shown in Figure 4.5.14. The resulting implementation o f the technique
is illustrated in Figures 4.5.12 and 4.5.13, where the realized multiplier is seen to have a
conversion gain of 8.5 dB, fundamental suppression of > 25 dBc, and third harmonic
suppression of > 50 dBc. Comparing Figures 4.5.11 and 4.5.12 shows that the
optimization approach used in this section yields and improvement o f 2.5 dB in the
conversion gain over the conventional doubler realization. The complete doubler
network realization is shown in Figure 4.5.15.
236
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
0
-
-10
-
S2I (dB)
-20
’
-30 1
-40 :
Sim ulated
-50 -
M easured
-60 -70 _
2
3
4
5
6
7
8
9
10
11
12
13
Frequency (GHz)
Figure 4.5.14 Transmission Magnitude for Output Network
(short circuit @ f = f 0 and open circuit @ f = 3 f Q)
f ~ 2fo
M o
M fo
0= 180
9= 90
Figure 4.5.15 Optimized Doubler Design Schematic
237
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
4.5.2.3
Summaryof results
This section has detailed the results o f a comprehensive in-depth study to
quantitatively determine the effects o f passive circuit terminations on microwave active
multiplier performance. Subsequent to a discussion of modeled and measured device
nonlinearities for the HEMT transistor employed, regions of optimal bias are delineated
and employed to quantitatively evaluate multiplier performance. These quantitative
results show considerable improvement o f frequency multiplier performance (in terms o f
conversion gain and harmonic suppression) with the addition of proper terminating
impedances. The optimizing technique shown in this section demonstrates the importance
of analyzing harmonic terminating impedances with special emphasis on higher-order
harmonic terminations which are typically not emphasized in multiplier design and
analysis. Modeled results are verified by an experimental design which shows an
improvement of 77% over a traditional approach.
238
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
4.5.3
Reflector Philosophy
Another single-ended design technique previously used by authors
[46,48,57,62,107] is through the use of reflector networks. This section presents the
development o f active doublers operating in S and C frequency bands with new
developments involving reflector networks not previously reported. These designs are
unique in that HEMT transistors (Fujitsu FHXLG) are employed in an unbalanced design
utilizing “reflector” networks to provide optimized performance. Reflector networks are
emphasized on the input and output o f the design simultaneously. In a common source
configuration, the input reflector network allows the fundamental frequency to pass but
reflects the higher harmonics signal back into the gate of the device. On the other hand,
the output reflector network passes the desired harmonic while reflecting the fundamental
frequency back into the drain of the device at the proper phase angle maximizing the
conversion gain of the multiplier. Measured and simulated results are given to strengthen
this design philosophy.
4.5.3.1
Reflector Networks
Numerous techniques exist for realization o f frequency multipliers. All
techniques at radio frequencies employ a non-linear device to generate the desired
frequency multiple. While HEMT’s are traditionally used in high-gain or low-noise
amplifiers, relatively little has been reported on their use in multiplier applications in
comparison with bipolar and FET devices. The basic configuration o f the single-ended
frequency multiplier realization is illustrated in Figure 4.5.13. As previously mentioned,
the input network allows the fundamental frequency to pass through to the gate o f the
239
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
transistor, in a common source configuration, while suppressing higher harmonic
frequencies. Likewise, the output network suppresses the fundamental and other
undesired harmonics, while allowing the desired harmonic to pass. The frequency
multiplier reflector network design philosophy implemented in this section is applied to a
frequency doubler with a fundamental frequency o f 3 GHz.
-W H
Input
N etw ork
HEMT
O utput
N etw ork
Figure 4.5.13 Frequency Multiplier Network Configuration
As mentioned above, a primary objective o f the output and input networks is to
suppress select harmonics. In the process o f suppressing the undesired signals, it appears
that relatively little attention is typically focused on the concept that the unwanted signals
can be reflected back into the device from the input and output networks simultaneously.
The non-linearity of the device causes these harmonics and the fundamental to mix with
other frequency components. This mixing process can either enhance or degrade the
signal at the desired second harmonic. Therefore, it is important for the reflected signal
to be properly phased such that it interferes constructively with the desired harmonic
(second harmonic in the case of the frequency doubler). Thus, the input and output
240
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
networks o f Figure 4.5.13 can be designed in such a way that they are reflector networks
meeting the above criteria in addition to their primary function of filtering.
Due to the complexity in calculating the actual effects of the reflector networks,
there is not a significant amount of literature on this topic until recently [110]. Using
reflector networks as a design tool for frequency doublers, Hirota [62] gives simulated
data on the effects of a reflector network on the output of a GaAs FET versus conversion
gain. Hirota develops balanced monolithic frequency doublers with output frequencies in
the 13 GHz and 26 GHz bands utilizing uniplanar structures employing coplanar
waveguides, slotlines, and air bridges. In the topology presented by Hirota, a
transmission line o f electrical length 0 connects the drain o f a MESFET transistor to an
output network which reflects the fundamental back into the drain of the MESFET to
investigate the affect of 0on the conversion gain. The plots provided by Hirota show the
simulated conversion gain of the frequency doubler versus the electrical length 9 for
various frequencies. Measured results o f the finalized fabricated doubler yielded
conversion gains o f 2.9 dB at 12.4 GHz and a minimum conversion loss o f 0.7 dB at 24.4
GHz. The author did not present any data on harmonic suppression. Borg [48] and
Rauscher [46] show that there is an advantage in using a reflector circuit on the input.
Borg has performed his study on a bipolar Darlington pair transistor where narrow,
medium, and wide-bandwidth frequency doublers were developed and evaluated to
demonstrate the effects and influence o f reflector networks on the performance o f the
doubler. The narrow-bandwidth doublers were used by Borg to characterize the
dependency o f the doubler’s performance on the fundamental output termination
synthesized as an output reflector network. Borg places a length of 50-ohm transmission
241
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
line on the collector o f the transistor followed by a quarter wavelength 50-ohm opencircuited shunt stub at the second harmonic frequency. The length of the transmission
line is varied between A and V* wavelength. At each variation, the modeled data obtained
from computer simulations and measured data representing the conversion gain is
presented by Borg versus the reflection coefficient o f the output reflector network. This
data has been reproduced for the narrow-bandwidth design, as shown in Figure 4.5.13b.
A maximum conversion gain o f 2.5 dB is achieved with the transmission line a A
wavelength which produces a reflection coefficient o f -180 degrees. Borg develops
medium-bandwidth designs with and without input reflector networks. The major
outcome of these designs is that in the case where an input reflector network was added
to reflect the second harmonic back into the base of the transistor, the conversion gain
improved by approximately 7 dB over the cases where the designs did not utilize an input
reflector network.
Rauscher has performed computer simulations on a GaAs FET frequency doubler
demonstrating the dependence o f doubler performance on the fundamental frequency
output termination as governed by reflector networks on the drain of the device.
Similarly, he demonstrates through computer simulations the influence o f the second
harmonic input termination at the gate of the transistor on the performance o f the doubler.
In depicting the effect o f the fundamental frequency output termination, Rauscher
presents the simulated large-signal conversion gain as a function o f second harmonic
output power and fundamental frequency reactive load impedance Z tl (fo) where the
fundamental frequency load reactance is expressed in terms o f Z tl (fo) = j 50 Han (9). In
this expression, Rauscher varies 0(the electrical length o f a fictitious short-circuited 50
242
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
ohm transmission line stub), which consequently varies the fundamental frequency load
reactance, and simulates the conversion gain for various values of 6 . A maximum
conversion gain o f 6.9 dB is achieved with
6
- 35° with second harmonic output power at
3.5 dBm. Demonstrating the influence of the second harmonic input termination on the
performance o f the frequency doubler, Rauscher varies the reactive input termination
impedance Z 77 (2fo) = jX n (2fo) Computer simulation results as demonstrated by
Rauscher’s plots where the conversion gain is given versus the second harmonic input
terminating reactance (Xn (2fo)) show that a maximum conversion gain o f 1 dB is
achieved with a reactance of approximately - 60 ohms (Xn (2fo) = -6 0 ohms). In the
study performed by Rauscher, however, the development process used simulated data
without measured data to verify the accuracy of the computer simulations. In the final
multiplier design, the multiplier possessed less that 0 dB o f conversion gain. Presently,
based on a perusal of the literature, there does not appear to be a substantial amount o f
multiplier designs incorporating the use of reflector networks, especially on both ports
(input and output) simultaneously with modeled and measured results.
243
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
4 -
M eaured
S im u lated
-180
-160
-140
-120
-100
-80
-60
-40
-20
0
Angle of Reflection Coefficient Presented to Transistor Output b y
Single Stub Load Network (degrees)
Figure 4.5.13b Conversion Gain of Narrowband Doubler as a Function of the phase
of the load reflection coefficient
The multiplier realizations presented in this section are unique in that the analysis
is performed on HEMT transistors and considers the effect o f reflector networks on the
input and output of the transistor simultaneously. This is significant because, in perusal
of the available literature, this is the first published case where reflector networks have
been utilized on the input and output simultaneously. Measured and modeled data is
presented throughout the analytical process to validate the results. These designs produce
high conversion gains, wide bandwidths, and operate with low dc power consumption
due to HEMT biasing at pinch-off (Vgs=Vp=-0. 7 volts). Alternate designs for reflector
networks are also discussed and employed in additional designs.
4.5.3.2
Consideration of Reflection Phase Angle
As mentioned above, the input and output networks o f Figure 4.5.13 should be
designed such that they are reflector networks, in addition to their primary function o f
244
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
filtering. The reflector networks developed in this section are analyzed on a frequency
doubler with a fundamental frequency of 3 GHz. The input network of Figure 4.5.13
should be designed such that for a frequency doubler it reflects the second harmonic back
into the gate o f the HEMT at the proper phase angle such that it interferes constructively
for optimum conversion gain. Similarly, the output network is designed such that it
reflects the fundamental signal back into the drain of the HEMT at the optimum phase.
h = \ J 2 @ f =f> - 3 GHz
rl = so n
I i=Ao/4 @ f= f0=3 GHz
Figure 4.5.14 Output Reflector Network
245
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Figure 4.5.14 shows a typical reflector network used as the output network in
Figure 4.5.13. Using standard impedance equations for a short-circuited transmission
line, the input impedance (Z/.vs) o f the shorted stub is
Z/xs ~ 0 3t f =f 0
(4.5.1)
Ziss &<x>a.tf= 2f0
(4.5.2)
and at/ = 2f 0
Using the relations for the input impedance of the stub at the fundamental (f0) and second
harmonic (2f0) frequencies as given by equations (4.5.1) and (4.5.2), respectively, the
input impedance of the reflector network (Z/X2 ) is
Z m «0 z tf= f0
(4.5.3)
Z/X2 ~ Z l —50 £2a t / = 2f0
(4.5.4)
Using ZfN2>the output reflection coefficient (Tout) is expressed by
r~
OUt
_
Z
-Z o
t'IN 2
y
(4.5.5)
y
IN2 +
o
For simplicity, Z0 is assumed to be 50 ohms and thus at f - f
0
rou t = l ^ - l 80 l
246
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
(4.5.6)
This shows that at the fundamental frequency (3 GHz), the signal is reflected back into
the drain of the HEMT at a phase angle o f -180 degrees. At the desired second harmonic
frequency, from equation (4.5.4), Z[\i = 50 ohms, thus all power is theoretically
terminated in the load as desired.
The analysis above was performed for the transmission line lj = "KJ2 at the
fundamental frequency in Figure 4.5.14. Similarly, this analysis can be repeated for
various lengths of U. Using equations 4.5.1-4.5.5, Table 4.5.11 shown below is generated
for various values of lz and will be used later in the analysis.
Z|N2 1f“2fo
'kJ 2
0
50
r tji
50Z -90°
50
IZ -90°
0
kJA
ao
50
IZ 0 °
0
Ao/8
50Z 90°
50
1Z 90°
0
0
0
50
I Z 180°
0
0o0
0
Z rm; 1f-fo
K
r 1f-f0
1,
r 1f-2To
0
Table 4.5.11 Reflection Coefficient of Output Reflector Network
A similar analysis can be performed for the input reflector network using the
analysis technique demonstrated above for the output reflector network. In the analysis
for the input reflector network, the second harmonic signal should be reflected back into
the gate o f the HEMT while allowing the fundamental to pass through to the gate. Figure
4.5.15 shows a typical input reflector network.
247
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
h = X J 2 at / = 2fa = <5 G/fc
/3= V 4 a t / = 2fa = 6 G/fc
Figure 4.5.15 Input Reflector Network
4.5.3.3
Effect o f Reflection Phase Angle on Conversion Gain
Using the results from the reflector networks shown in Table 4.5.11, optimization
o f the conversion gain o f the HEMT doubler can be performed as a function o f the
reflection phase angle or the transmission line lengths. As an example, replacing the
input matching network of Figure 4.5.13 with the reflector network o f Figure 4.5.15 and
varying the length o f U produces a series o f conversion gain simulations versus
transmission line lengths (U). Figure 4.5.16 shows the conversion gain simulations
versus the length o f U for various input powers where U varies from 0° to 260° (at 2f 0).
The output matching network o f Figure 4.5.13 is replaced with the output reflector
network of Figure 4.5.14, where l\ = XJA (at f 0) and h is nominally a half wavelength at
the fundamental frequency (h = KJ2 (at f 0)) for the simulations shown in Figure 4.5.16.
Figure 4.5.16 shows that the maximum conversion gain is with U ~200°. The HEMT is
biased for F<&=3 v and V ^ - 0 .6 v in this analysis. Similarly, Figure 4.5.17 shows the
24 8
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
conversion gain simulations o f the frequency doubler versus lj. In this analysis, the
output matching network of Figure 4.5.13 is replaced by the output reflector network o f
Figure 4.5.14, with h varying from 0 < h < hJ2 (180° at f Q), and the input matching
network o f Figure 4.5.13 is replaced by the input reflector network of Figure 4.5.15 with
h = ^o/4 (at 2f 0) and U is nominally a half wavelength at the second harmonic frequency
(/4 = XJ2 (at 2f0)). These simulations and figures demonstrate the conversion gain versus
the series transmission line length o f the input and output reflector network for various
input power levels.
8
.12
—
0
20
40
60
80
100
120
140
160
180
200
220
240
—
260
Input Transmission Line Length (degrees)
Figure 4.5.16 Simulated Conversion Gain of Frequency Doubler Versus Input
Transmission Line Length (I4) (F*=J v, V # = -0 .6 v)
249
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
-21
—
0
■—
20
40
60
1=---------- ■
SO
--------------------------------------
100
120
140
160
ISO
Output Stub Length (degrees)
Figure 4.5.17 Simulated Conversion G ain of Frequency Doubler Versus O utp u t
Transmission Line L ength (h) (Vds~3 v, Vp =-0.6 v)
The simulated results o f Figure 4.5.16 and Figure 4.5.17 can be strengthened by
experimental data. A series o f 8 circuits, each having a particular length o f input
transmission line (/4) ranging over the lengths 0 < U < XJ2 with h = XJA (at 2f a) have
been constructed and tested. The output network of the frequency doubler used in these
circuits is the output network shown in Figure 4.5.14 with l\ = XJA (at f 0) and h - KJ2 (at
fo). The results of this analysis are shown in Figure 4.5.18, which shows the measured
and simulated conversion gain versus the input transmission line length of the input
reflector network. Similarly, a series o f circuits with each having a particular length o f
output transmission line (li) ranging over the lengths 0 < h < XJ2 (at f 0) with h = Xo/4 (at
f 0) are constructed and tested with the input network o f these circuits the same as that
shown in Figure 4.5.15 (h = XJA (at 2fa) and U -
(at 2f0)). Figure 4.5.19 shows the
250
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
measured and simulated conversion gain versus the series transmission line length o f the
output reflector network. The results o f Figures 4.5.18 and 4.5.19 show two important
results: 1) the measured and modeled results are quite accurate, which lends confidence
in further designs using this HEMT model, and 2) the required transmission line length
and reflection angle yielding optimum conversion gain is easily extracted from these
figures.
10 _
5
0
-5
-10
Theoretical
-15
Measured
-20
0
100
200
300
400
500
600
700
In p u t T ransm ission L in e Length (mils)
Figure 4.5.18 Conversion Gain of HEMT Doubler Versus Input Transmission Line
Length (U) (Pin=0 d B m , V gt= -0.6 v)
251
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
10 -
co
■o
05
u
-Theoretical
. Measured
o
U
200
400
600
800
1000
1200
1400
1600
Output Transmission Line Length (mils)
Figure 4.5.19 Conversion Gain of HEMT Doubler Versus Output Transmission
Line Length ( h ) (Pm = 0 d B m , V # = -0 .6 v)
4.5.3.4
Narrowband Doubler Design
Referring to Figures 4.5.16 - 4.5.19, the optimum conversion gain achieved is 7
dB. This conversion gain is achieved with the series transmission line of the input
reflector network (/4) at the nominal value of 180° (722 mils) and the series transmission
line of the output reflector network (Jz) at 44 ’(340 mils). After identifying the
transmission line lengths for optimum results, a frequency doubler using these
dimensions (/4 = 180 °and lz - 44 °) is constructed and tested. The results of this
narrowband doubler design is shown below in Figure 4.5.20 where the measured and
simulated output power levels o f the fundamental, second, and third harmonic
frequencies versus the fundamental frequency is shown. The results show that the
fundamental and third order suppression are greater than 30 dBc at a fundamental
252
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
frequency o f 2.95 GHz. while the conversion gain is 6 dB. The use o f single stubs in the
input and output reflector networks account for the narrow bandwidth response observed
by the curves of Figure 4.5.20. Single stubs typically produce narrowband designs o f 5 1 0 %.
10 T
>x
E
JC
CD
■O
•x- - - Simulated Po <cv, f
-X— Measured Po a f
Simulated Po a 2 f
Measured Po 'S 2f
A * - Simulated Po S' 3f
3
c
•4— Measured Po tv, 3f
-40
2.7
2.75
2.8
2.85
2.9
2.95
3
3.05
3.1
3.15
3.2
Fundamental Frequency (GHz)
Figure 4.5.20 Narrowband HEMT D oubler Design with Reflector Network on In p u t
and O utput (Pm=0 dBm, Ve =-0.6 v)
The doubler design presented above demonstrates a simple narrowband design
optimizing the reflector networks. An alternative narrowband design incorporates a
simple 1-section, Chebyscheff, edge-coupled bandpass filter to produce a “rolling-off ’
effect in the response o f the conversion gain. The dimensions of this 1-section filter are
shown below in Table 4.5.12. In this design, the output matching network of Figure
253
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
4.5.13 is synthesized as a reflector network consisting of a series transmission line
followed by a 1-section bandpass filter. Referring to Figures 4.5.17 and 4.5.19 and Table
4.5.11, the optimum conversion gain o f the doubler was achieved with /2 o f the output
reflector at approximately 44° (/2 ~ 44 °). Using this value for /2 in Table 4.5.11, the
interpolated, theoretical corresponding reflection angle at the fundamental frequency
is approximately 93
Width (mils)
Wi=25
W2=25
Thus, the reflection phase angle presented by the cascaded
Spacing (mils)
Si=10
S2=10
Length (mils)
L,=352.5
L2=352.5
Table 4.5.12 Dimensions of 1-section Narrowband Bandpass Filter
series transmission line and bandpass filter combination should be 93 °for optimum
performance. This 93 ° reflection angle is achieved by adjusting the length of the series
transmission line until the reflection coefficient phase angle of the cascaded transmission
line and filter is rotated to 93 °. The synthesized input reflector network for this design
remains the same as in the previous design, i.e., U = XJ2 and Ij = XJ4 at the second
harmonic (6 GHz). The results o f this narrowband design are shown in Figure 4.5.21.
The maximum conversion gain is 6 dB with fundamental and third harmonic suppression
greater than 25 dBc. This narrowband design exhibited greater fundamental and third
harmonic suppression by approximately 10 dB over a wider bandwidth (7 %) than the
initial narrowband design. The increase in fundamental and third harmonic suppression
is due to the filter response. Increasing the number o f sections in the filter improves the
254
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
attenuation of the filter response and, thus, improves the fundamental and third harmonic
suppression of the doubler. Using these facts, a design is developed using a two-section
bandpass filter which improves the attenuation and the harmonic suppression even
further. The dimensions of this 2-section filter are shown below in Table 4.5.13 and the
response o f the overall multiplier design is shown in Figure 4.5.22. This figure shows
that the 3 dB bandwidth widens to approximately 9 % with a conversion gain o f 4.5 dB ±
0.5 dB. As expected, the fundamental and third harmonic suppression improves to 50
dBc due to the improvement in the attenuation o f the bandpass filter. This improvement
in harmonic suppression as at the expense of about 1 dB of conversion gain. In order to
get this improved attenuation, the passband insertion loss o f the filter increases, thus
reducing the overall conversion gain o f the multiplier. This design delineates the trade­
offs which are often encountered in multiplier design.
Width (mils)
Wj=30
W2=20
W3=30
Spacing (mils)
S,=10
S2=40
S3=10
Length (mils)
L,=355
L2=350
L3=355
Table 4.5.13 Dimensions o f 2-section Narrowband Bandpass Filter
255
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
a
■X.
a
c
•X
ft—
-30
-35
-Sim ulated
Po
M easured
Po
M easured
Po
■A r * -Sim ulated
Po
X
■' M easured
Po
• -X*
- -Sim ulated
Po
®
-A
m
t
a
c.
-40
2.85
2.9
2.95
3.05
3.15
Fundamental Frequency (GHz)
Figure 4.5.21 Narrowband HEMT Doubler Design with 1-Section Filter
(Pm =0 d B m , V g,= -0.6 v)
10 -
-20
-
in J m o
. . . . . •Sim ulated
Po
—
M easured
Po
M easured
Po
-X
- - A* - -Sim ulated
Po
— X — M easured
Po
(§>
-A
^
<g) i§>
-
- Sim ulated
Po
!<g>
(uigp) jJMttj
-10
<g!
0
-
-X
3.2
Fundamental Frequency (GHz)
Figure 4.5.22 Narrowband HEMT Doubler Design with 2-Section Filter
(P in= 0 d B m , Vgs= -0.6 v)
256
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
4.5.3.5
Medium Band and Wide Band Doubler Designs
As shown in the previous section, a means of extending the bandwidth o f the
doubler designs requires bandpass filters with greater bandwidth. In this accord, using
the same approach as shown with the narrow band designs which encompassed 1 and 2section bandpass filters, a 5-section, Chebyscheff, edge-coupled bandpass filter with a
15% bandwidth was designed and placed in the output network. The physical dimensions
o f this filter are shown below in Table 4.5.14, and the transmission response o f a typical
15 % bandwidth filter is shown below in Figure 4.5.23. As before, a section o f series
transmission line precedes the filter in order to rotate the reflection angle of the
transmission line and filter combination to 93 ° for optimum conversion gain. The input
reflector remains at its optimum state, i.e., U = KJ2 and h = XJ4 at the second harmonic
(6 GHz). The results of this design are shown in Figure 4.5.24. The conversion gain is
shown to be 4 dB ± 1 dB with a -3 dB bandwidth of 15%, and the fundamental and third
harmonic suppression is greater than 65 dBc. This design demonstrates the improvement
in the bandwidth and harmonic suppression o f the frequency doubler as impacted by the
filter over the previous designs.
257
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Width (mils)
Spacing (mils)
Length (mils)
L,=350
L2=345
L3=340
L4=340
Ls=345
L6=350
S,=10
S2=15
S3=20
S4=20
Ss=15
S6=10
W,=15
W2=50
W3=45
W4=45
Ws=50
W6=15
Table 4.5.14 Physical Dimensions of 15 % Bandwidth, 5-section Bandpass Filter
-10
S2I (d B )
-20
Measured
Theoretical
-30
-40
-50
-60
4.5
5
5.5
6
6.5
7
7.5
Frequency (GHz)
Figure 4.5.23 Typical 15 % Bandwidth Bandpass Filter Used in Medium Band
Doubler Design
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
10
0
-10
-
E
-20
-
............... •Sim ulated Po ^ f
-
-
a
a
r -40-
|a
a.
Measured Po '2) f
X----- Measured Po <&2 f
• • • * • • -Sim ulated Po (2f 2 f
-50 -
-
3
• • ^
-110
Measured Po <© 3f
• -Simulated Po
3f
—
—
2.7
ft
2.8
2.9
3
3.1
3.3
Fundamental Frequency (GHz)
Figure 4.5.24 Medium Band HEMT D oubler Design
(Pm=0 dBm, Vgs=-0.6 v)
Wide band designs for frequency doubler application are synthesized similar to
those of the narrow band designs. A wide band bandpass filter used in this design is a
fifth-order Minnis edge-coupled filter with a 45% bandwidth [89]. The physical
dimensions of this filter are shown below in Table 4.5.15, and the transmission response
o f a typical 45% bandwidth Minnis filter is shown below in Figure 4.5.25. The measured
and simulated results deviate at the higher frequencies due to over etching in the
fabrication of the filter. The spacing between the coupled lines o f the filter is on the
order o f 7.5 to 10 mils, which was very difficult to achieve with fabrication/etching
process employed. As before, a section of series transmission line precedes the filter in
order to rotate the reflection angle o f the transmission line and filter combination to 93 °
for optimum conversion gain. The input reflector remains at its optimum state, i.e.,
259
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
/4 =
and /3 = XJ4 at the second harmonic (6 GHz). The results of this design are
shown in Figure 4.5.26 which show the conversion gain as 3 d B ± I dB with a -3 dB
bandwidth of 35%. The fundamental and third harmonic frequency suppression is greater
than 45 dBc. which is excellent considering the bandwidth achieved. This design
demonstrates the improvement in bandwidth but at the expense o f the conversion gain for
the frequency doubler.
Width (mils)
W,=9
W2=9
W3=9
W4=9
W5=9
W6=9
Spacing (mils)
S,=7.5
S2=8
S3=10
S4=10
S5=8
S6=7.5
Length (mils)
Li=400.5
L2=397.2
L3=395.3
L4=395.3
L5=397.2
L6=400.5
Table 4.5.15 Physical Dimensions of 45 % Bandwidth, Minnis Filter
260
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
-10
-20
£9
Measured
Theoretical
-50
-60
3
4
7
6
5
9
8
Frequency (GHz)
Figure 4.5.25 Typical 45 % Bandwidth Minnis Filter Used in Wide Band Doubler
Design
10
st
-30
■a.
- - - - - -Simulated Po @ 2 f
|£ -40
x—*
^3 -50
c
-------------Measured Po @ 2 f
X
A.
•i4-». . •A "^--A-.
-60
-70 -
2.2
A
_ ^ - x — X — X-
-x
-80
2.3
2.4
Measured Po % f
- - -X- - -Simulated Po @ f
Measured Po @ 3 f
- - -A- - -Simulated Po (a) 3 f
2.5
2.6
2.7
2.8
2.9
3
3.1
3.2
Fundamental Frequency (GHz)
Figure 4.5.26 Wide Band HEMT Doubler Design
{Pin=0 d B m , Vgs=-0.6 v)
261
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
4.53.6
Alternate Design Topology
As mentioned previously, one of the functions o f the reflector network is to
attenuate undesired harmonics. Regarding the input reflector network, this network
should allow the fundamental signal pass while attenuating and reflecting other
harmonics. Theoretically, a low pass filter designed with a center frequency of 3 GHz
(fo) allows the fundamental to pass while attenuating the higher harmonics. An alternate
design topology for narrow band and wide band designs can be achieved by introducing a
low pass in the reflector network o f the frequency doubler. As previously shown in
Figures 4.5.16 and 4.5.18, the optimum conversion gain (7 dB) for the input reflector
network was achieved with U =
and /3 = XJA at the second harmonic (6 GHz) which
produced a reflection phase angle o f -180 degrees. Therefore, a low pass filter followed
by a series transmission line for tuning the reflection phase angle to -180 degrees was
used to synthesize the input reflector network. This topology for the input reflector
network and a 1-section bandpass filter on the output, such as that used in the preceding
section, was used to synthesize an alternate narrow band design. The physical dimensions
o f this 3-section, Chebyscheff, low-pass filter are shown below in Table 4.5.16, and the
results o f this alternate narrow band design are shown in Figure 4.5.27. These results
show a conversion gain of 3.5 dB with fundamental and harmonic suppression greater
than 30 dBc. Similarly, a wide band doubler design is developed using the low pass filter
in the input reflector and the Minnis filter previously discussed in the output reflector
network. The results o f this alternate wide band design are shown in Figure 4.5.28 and
show a conversion gain of 0 dB ± 1 dB and harmonic suppression greater than 50 dBc.
The conversion gain o f the frequency doublers using the low-pass filter topology is
262
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
reduced by approximately 2.5 dB and 3 dB for the narrow band and wide band designs,
respectively, over the designs which did not use the low-pass filters. The low-pass filter
utilized was a 3-secton Chebyscheff topology. The “roll-off” o f this 3-section filter
topology is not as steep as the single-stage stubs used in the previous designs so.
therefore, the higher harmonics were not attenuated as much on the input. Additionally,
using low-pass filters increases the size of the complete doubler circuit substantially and
is not very useful in applications where there are size constraints. Due to the bandpass
filters in the output reflector network, however, the harmonic suppression remained
excellent as demonstrated in the plots.
Width (mils)
Length (mils)
L[=170
L2=250
L3=170
W,=200
W2=20
W3=200
Table 4.5.16 Physical Dimensions of 3-section Low-pass Filter
263
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10
5
O utput Power <dB)
0
-5
-1 0
-
-15 — • 'Sim ulated Po 2 2 f
•-A
x
-25 -30
-r
T -* -
Measured Po
-X -
Measured Po (us 3f
X
Simulated Po 2 / 3 f
-40 —
2.8
2.85
2.9
3.05
2.95
Fundamental Frequency (GHz)
Figure 4.5.26 Alternate Narrow Band HEMT Doubler Design
(Pi„—0 d B m , Vgi=-0.6 v)
O utput Power (dBm)
Simulated Po @ 2f
■M easured Po @ 2f
Simulated Po 2 f
(vicasurea
r o ^iuj fe
Measured Po
X - ' 'Sim ulated Po (Sf 3 f
Measured Po @ 3 f
2.2
2.3
2.4
2.5
2.6
2f
A* - 'Sim ulated Po 2 f
-35 2.75
'a ;
■6 ■" ■ Measured Po 2 f
2.7
2.8
2.9
3
3.1
3.2
3.3
3.4
3.5
Fundamental Frequency (GHz)
Figure 4.5.27 Alternate Wide Band HEMT Doubler Design
{P in-0 d B m , Vgr^O.6 v)
264
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4.5.3.5
Summary
This section has presented design techniques for single-ended frequency
multiplier designs. These techniques incorporate reflector networks providing excellent
performance characteristics, which includes effective conversion gain and harmonic
suppression as demonstrated by the results. These results show the improvement in
conversion gain using reflector networks with proper phase angles on the input and
output network simultaneously, which are useful for narrow band and wide band
applications. Due to bandwidth constraints imposed by the use o f single stubs,
incorporating filters into the designs achieves bandwidth extension and improves
harmonic suppression. This improvement in bandwidth and harmonic suppression,
however, comes at the expense o f conversion gain as shown by the wide band designs.
Another advantage o f these designs is that they are single-ended which alleviates the
requirement for complex baluns or transformers.
265
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274
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Chapter 5
Conclusion
5.1
Summary
RF and microwave frequency multipliers represent an important class o f nonlinear
devices utilized extensively throughout the microwave arena. Their use includes
applications in radar and EW systems, transmitter and receiver systems while their use in
modem applications include wireless communication transmitters, receivers, transceivers,
and wireless local loop systems.
A summary of RF and microwave multipliers has been presented in this
dissertation beginning with classical passive multipliers. A detailed summary o f passive
frequency multiplier development is presented detailing the pertinent aspects o f passive
frequency multipliers including in-depth background and theoretical analysis on their
operation. Included in this discussion is an equivalent circuit model o f varactors, which
are utilized extensively in passive multiplier technology, the identification o f non-linear
mechanisms responsible for harmonic production, optimization of efficiency, and a
discussion on the classical and familiar Manley-Rowe equations which govern the power
considerations of nonlinear reactors.
Due to the nonlinear nature o f passive multipliers, microwave designers and
practitioners utilize nonlinear simulation techniques to analyze passive multipliers. One
valuable simulation technique for nonlinear simulations is the harmonic balance
technique. Fortunately, harmonic balance simulators often reside in some commercial
circuit simulations such as the commercial circuit simulator (EEsof Libra circuit
275
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simulator) used extensively in studies presented in this dissertation. In this regard, a
discussion is presented referencing the harmonic balance technique utilized in the Libra
circuit simulator.
Numerous classical realizations and synthesis techniques exist for the design of
passive multipliers. In perusal of the literature, several realizations are presented along
with synthesis techniques utilized by various authors. This includes realizations
beginning with simple single-series or single-shunt diode topologies and leading to
various multi-diode configurations and balanced configurations requiring baluns which
are often encountered throughout the industry.
The discussion on passive multipliers presented in Chapter 3 is a detailed
summary of passive multiplier development. Similarly, a discussion on active frequency
multipliers is presented in Chapter 4 where in-depth discussions on active multipliers
with several new contributions to active multiplier technology along with several new
designs are presented. It is in this area that the greatest contribution to multiplier
technology is presented.
One o f the most important tools utilized by the designer is the capability to
accurately model the active nonlinear device utilized in the development o f active
multipliers. In this regard, an extensive section on nonlinear modeling is presented
beginning with some classical nonlinear models and finalizing with modem nonlinear
models developed specifically for MESFET’s and HEMT’s. Incorporating the modem
models along with various new additions and contributions by the author, quite accurate
nonlinear models are developed for the active devices utilized in some o f the active
multiplier designs.
276
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Various discussions are presented on the nonlinear behavior associated the
nonlinear active device. Discussions are presented on quantifying the nonlinearities of
the active device as well as identifying the nonlinearities valuable for harmonic
generation, identifying the pertinent properties o f the active device, and identifying
optimum bias conditions for optimum performance. These are vital discussions which
are used extensively by the practitioner.
Numerous design techniques exist for the realization o f active frequency
multipliers with various performances, advantages, and disadvantages. A summary of the
existing techniques is presented delineating the various performances o f these designs.
New design techniques and ideas resulting from the author’s research are presented and,
where applicable, show the superior performance of these new designs over traditional
design methodologies. The results o f these new designs show measured and simulated
results for numerous designs where the simulated data results from the development of
nonlinear models alluded to previously. These new design techniques exhibit great
results and should provide additional design tools for the RF active multiplier designer.
5.2
Future work
This research work can be utilized as a basis for ensuing research work on
frequency multipliers, particularly in the area o f active multipliers. One pursuable and
interesting area is the quantitatively determination of the contributions of the individual
nonlinear parameters of the active device (i.e. transconductance, output conductance, and
nonlinear capacitances, etc.) to the overall nonlinearity of the device. Beginning with the
nonlinear circuit model (Chalmer’s model) developed by the author in Chapter 4, the
277
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nonlinear performance o f the multiplier can be evaluated while allowing one of the above
mentioned model parameters to vary in its nonlinear fashion, while all other model
parameters are fixed. Performing simulations such as these for each o f the nonlinear
parameters should give quantitatively, the nonlinear contribution of each parameter.
Once this is achieved, an additional study can be undertaken with emphasis placed on the
harmonic terminations and their interactions with the nonlinear parameters.
Another area of interest lie within transistor family designs. With regards to the
literature, there does not appear to be any information suggesting why a particular family
o f transistors (BJT, MESFET, HEMT, etc.) provides greater conversion gains than
another family. It is unknown if this is due to the fundamental (f0) gain o f the device or
the pertinent properties o f the nonlinear device. In conclusion, these topics represent
some o f the areas where there does not appear to be very much information residing in
the literature in the area o f active multipliers and would be worthwhile contributions to
the development of efficient frequency multipliers.
278
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A ppendix A
Block D iagram o f FE T IV C urve M easurem ent
Appendix B
Sample Sensitivity Data File of Computer Optimization
Program
Appendix C
Sample Computer Optimization Subroutine
Sample Input Data File of Optimization Program
Sample Input Data File of Optimization Program
Appendix D
Sample Test Program Files
Appendix E
Manufacture Data Sheet of Devices Used in this Study
Appendix F
Sample Test Data from Devices Used in this Study
Appendix G
Listing of Publications
279
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Appendix A
Block Diagram of FET IV Curve Measurement
280
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
HP 4155 A
Semiconductor Parameter Analyzer
50 n
Termination
son
Termination
Bias Tee
Bias Tee
FET
Bias Tee
50 n
Termination
Figure A.1 Block Diagram of FET IV Curve Meaurement
281
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Appendix B
Sample Sensitivity Data File of Computer Optimization Program
282
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
The tables shown below are the sensitivity analysis for Statz circuit model for -0.5 volts < Vts < 0 .1 volts. Column I of each table is the corresponding
value for the sensitivity analysis and column 2
represents the simulated value of 1&. Columns 3 - 7 of each table are the sensitivity of I* with respect to
the parameter at the head of each column.
Vgs=-0.I v
Vds
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3
Ids
3.17
5.692
7.615
9.01
9.962
10.575
10.973
11.292
11.607
11.923
12.238
12.554
12.87
13.185
13.501
13.816
14.132
14.448
14.763
15.079
15.394
15.71
16.026
16.341
16.657
16.973
17.288
17.604
17.919
18235
dlds/da
alpha
0.861
0.71
0.551
0.388
0.231
0.097
0.012
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
dlds/dp
beta
1
1
1
1
1
1
1
I
I
1
1
1
1
1
1
1
1
1
1
1
I
I
1
1
1
1
1
1
1
1
dIds/5Vt
Vt
1.855
1.855
1.855
1.855
1.855
1.855
1.855
1.855
1.855
1.855
1.855
1.855
1.855
1.855
1.855
1.855
1.855
1.855
1.855
1.855
1.855
1.855
1.855
1.855
1.855
1.855
1.855
1.855
1.855
1.855
aids/ax.
lambda
0.035
0.067
0.097
0.126
0.153
0.178
0.201
0224
0.245
0.265
0.284
0.302
0.319
0.335
0.351
0.365
0.38
0.393
0.406
0.419
0.431
0.442
0.453
0.464
0.474
0.483
0.493
0.502
0.511
0.519
dlds/dB
B
-0.468
-0.468
-0.468
-0.468
-0.468
-0.468
-0.468
-0.468
-0.468
-0.468
-0.468
-0.468
-0.468
-0.468
-0.468
-0.468
-0.468
-0.468
-0.468
-0.468
-0.468
-0.468
-0.468
-0.468
-0.468
-0.468
-0.468
-0.468
-0.468
-0.468
Table B.la
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Vgs—0.2 v
Vds
Ids
0.1
2.192
0.2
3.935
0.3
5.265
0.4
6.229
6.887
0.5
0.6
7.311
0.7
7.586
7.806
0.8
0.9
8.025
1
8.243
l.l
8.461
8.679
1.2
8.897
1.3
1.4
9.116
9.334
1.5
9.552
1.6
9.77
1.7
9.988
1.8
10.207
1.9
2
10.425
2.1
10.643
2.2
10.861
11.079
2.3
11.297
2.4
11.516
2.5
11.734
2.6
2.7
11.952
12.17
2.8
2.9
12.388
12.607
3
dlds/ca
alpha
0.861
0.71
0.551
0.388
0.231
0.097
0.012
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
clds/cP
beta
1
1
1
1
1
1
1
I
1
1
1
I
1
1
1
1
1
1
1
1
1
1
1
I
1
1
1
1
1
1
dlds/SVt
Vt
2.439
2.439
2.439
2.439
2.439
2.439
2.439
2.439
2.439
2.439
2.439
2.439
2.439
2.439
2.439
2.439
2.439
2.439
2.439
2.439
2.439
2.439
2.439
2.439
2.439
2.439
2.439
2.439
2.439
2.439
aids/dA.
lambda
0.035
0.067
0.097
0.126
0.153
0.178
0.201
0.224
0.245
0.265
0.284
0.302
0.319
0.335
0.351
0.365
0.38
0.393
0.406
0.419
0.431
0.442
0.453
0.464
0.474
0.483
0.493
0.502
0.511
0.519
clds/cB
B
-0.41
-0.41
-0.41
-0.41
-0.41
-0.41
-0.41
-0.41
-0.41
-0.41
-0.41
-0.41
-0.41
-0.41
-0.41
-0.41
-0.41
-0.41
-0.41
-0.41
-0.41
-0.41
-0.41
-0.41
-0.41
-0.41
-0.41
-0.41
-0.41
-0.41
Table B.lb
284
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Vgs=-0.3 v
Vds
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
I
l.l
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3
Ids
1.323
2.376
3.179
3.761
4.158
4.414
4.58
4.713
4.845
4.976
5.108
524
5.372
5.503
5.635
5.767
5.898
6.03
6.162
6.294
6.425
6.557
6.689
6.821
6.952
7.084
7.216
7.347
7.479
7.611
dlds/ca
alpha
0.861
0.71
0.551
0.388
0.231
0.097
0.012
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
<5Ids/cP
beta
I
1
1
1
I
1
1
1
I
1
1
1
1
1
1
1
1
1
1
1
1
1
I
1
1
1
1
1
1
1
SIds/dVt
Vt
3.477
3.477
3.477
3.477
3.477
3.477
3.477
3.477
3.477
3.477
3.477
3.477
3.477
3.477
3.477
3.477
3.477
3.477
3.477
3.477
3.477
3.477
3.477
3.477
3.477
3.477
3.477
3.477
3.477
3.477
5Ids/5A.
lambda
0.035
0.067
0.097
0.126
0.153
0.178
0.201
0.224
0.245
0.265
0.284
0.302
0.319
0.335
0.351
0.365
0.38
0.393
0.406
0.419
0.431
0.442
0.453
0.464
0.474
0.483
0.493
0.502
0.511
0.519
dlds/dB
B
-0.337
-0.337
-0.337
-0.337
-0.337
-0.337
-0.337
-0.337
-0.337
-0.337
-0.337
-0.337
-0.337
-0.337
-0.337
-0.337
-0.337
-0.337
-0.337
-0.337
-0.337
-0.337
-0.337
-0.337
-0.337
-0.337
-0.337
-0.337
-0.337
-0.337
Table B.lc
285
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Vgs=-0.4 v
Vds
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
j
dldsJda
Ids
0.611
1.096
1.467
1.736
1.919
2.037
2.114
2.175
2.236
2.297
2.358
2.418
2.479
2.54
2.601
2.662
2.722
2.783
2.844
2.905
2.966
3.026
3.087
3.148
3.209
3.27
3.33
3.391
3.452
3.513
alpha
0.861
0.71
0.551
0.388
0.231
0.097
0.012
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
aids/cp
beta
1
1
1
1
1
1
1
1
1
1
1
I
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
I
aids/avt
aids/SA.
Vt
5.768
5.768
5.768
5.768
5.768
5.768
5.768
5.768
5.768
5.768
5.768
5.768
5.768
5.768
5.768
5.768
5.768
5.768
5.768
5.768
5.768
5.768
5.768
5.768
5.768
5.768
5.768
5.768
5.768
5.768
lambda
0.035
0.067
0.097
0.126
0.153
0.178
0.201
0224
0245
0265
0284
0.302
0.319
0.335
0.351
0.365
0.38
0.393
0.406
0.419
0.431
0.442
0.453
0.464
0.474
0.483
0.493
0.502
0.511
0.519
dlds/dB
B
-0245
-0245
-0.245
-0.245
-0.245
-0245
-0.245
-0245
-0.245
-0245
-0245
-0245
-0245
-0245
-0245
-0245
-0245
-0245
-0.245
-0.245
-0.245
-0.245
-0.245
-0.245
-0.245
-0.245
-0.245
-0245
-0.245
-0.245
Table B.ld
286
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Vgs=-0.5 v
Vds
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3
Ids
0.13
0.234
0.313
0.371
0.41
0.435
0.451
0.464
0.477
0.49
0.503
0.516
0.529
0.542
0.555
0.568
0.581
0.594
0.607
0.62
0.633
0.646
0.659
0.672
0.685
0.698
0.711
0.724
0.737
0.75
dlds/dct
alpha
0.861
0.71
0.551
0.388
0.231
0.097
0.012
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2Ids/<?3
beta
1
1
1
1
1
I
1
I
1
1
1
1
1
I
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
olds/avt
Vt
14.399
14.399
14.399
14.399
14.399
14.399
14.399
14.399
14.399
14.399
14.399
14.399
14.399
14.399
14399
14.399
14.399
14.399
14.399
14.399
14.399
14.399
14.399
14.399
14.399
14.399
14.399
14.399
14.399
14.399
dlds/dA.
lambda
0.035
0.067
0.097
0.126
0.153
0.178
0.201
0224
0.245
0365
0.284
0.302
0.319
0.335
0.351
0.365
0.38
0393
0.406
0.419
0.431
0.442
0.453
0.464
0.474
0.483
0.493
0.502
0.511
0.519
dlds/dB
B
-0.122
-0.122
-0.122
-0.122
-0.122
-0.122
-0.122
-0.122
-0.122
-0.122
-0.122
-0.122
-0.122
-0.122
-0.122
-0.122
-0.122
-0.122
-0.122
-0.122
-0.122
-0.122
-0.122
-0.122
-0.122
-0.122
-0.122
-0.122
-0.122
-0.122
Table B.le
287
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
The tables shown below are the sensitivity analysis for Chalmer’s circuit model utilizing the nonglobal equations for various Vp values. This optimization routine was performed for 1^ without regard to
the transconductance (gm). Column 1 of each table is the corresponding
value for the sensitivity
analysis and column 2 represents the simulated value of I^. Columns 3 - 9 of each table are the sensitivity
of 1^ w'th respect to the parameter at the head of each column.
Vgs=-0.2
Vds
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
I
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3
Ids
5.346
9.571
12.302
13.917
14.887
15.528
16.01
16.418
16.79
17.147
17.496
17.842
18.187
18.531
18.874
19.217
19.561
19.904
20.247
20.59
20.933
21.277
21.62
21.963
22.306
22.649
22.992
23.336
23.679
24.022
dlds/dlpk dlds/dPl
Ipk
PI
I
-0.423
-0.423
1
I
-0.423
1
-0.423
-0.423
1
1
-0.423
I
-0.423
1
-0.423
-0.423
I
1
-0.423
1
-0.423
1
-0.423
-0.423
1
-0.423
1
1
-0.423
-0.423
1
1
-0.423
-0.423
1
1
-0.423
1
-0.423
-0.423
1
-0.423
1
-0.423
1
-0.423
1
1
-0.423
-0.423
1
-0.423
1
-0.423
1
-0.423
1
-0.423
1
dIds/3P2 5Ids/5P3 dlds/dV pk aids/ax
Vpk
lambda
P3
P2
0.024
0.423
0
0
0.423
0.048
0
0
0.07
0.423
0
0
0.423
0.091
0
0
0.423
0.111
0
0
0.423
0.13
0
0
0.423
0.149
0
0
0.167
0.423
0
0
0.184
0.423
0
0
0.423
0.2
0
0
0.423
0.216
0
0
0.423
0.231
0
0
0.423
0.245
0
0
0.259
0
0.423
0
0.423
0273
0
0
0.423
0.286
0
0
0.298
0.423
0
0
0.423
0.31
0
0
0.322
0.423
0
0
0.423
0.333
0
0
0.344
0.423
0
0
0.355
0.423
0
0
0.365
0.423
0
0
0.375
0
0.423
0
0.385
0.423
0
0
0.394
0.423
0
0
0.423
0.403
0
0
0.423
0.412
0
0
0.42
0.423
0
0
0.429
0.423
0
0
Table B.2a
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
5Ids/5a
alpha
0.901
0.674
0.439
0.261
0.147
0.079
0.041
0.021
0.011
0.005
0.003
0.001
0.001
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Vgs=-0.4
Vds
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
12
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3
Ids
1.959
3.507
4.507
5.099
5.455
5.689
5.866
6.015
6.152
6.283
6.411
6.537
6.664
6.79
6.915
7.041
7.167
1293
7.418
7.544
7.67
7.796
7.921
8.047
8.173
8.299
8.424
8.55
8.676
8.802
dlds/dlpk dlds/dPl
Ipk
PI
1
-1.692
1
-1.692
1
-1.692
1
-1.692
1
-1.692
1
-1.692
1
-1.692
1
-1.692
1
-1.692
1
-1.692
1
-1.692
1
-1.692
I
-1.692
1
-1.692
1
-1.692
I
-1.692
1
-1.692
1
-1.692
1
-1.692
1
-1.692
1
-1.692
1
-1.692
I
-1.692
1
-1.692
I
-1.692
1
-1.692
1
-1.692
1
-1.692
1
-1.692
1
-1.692
3Ids/3P2 cIds/5P3 dlds/dV pk aids/ek
lambda
P3
Vpk
P2
0.024
0.564
0
0
0.048
0.564
0
0
0.07
0.564
0
0
0.091
0.564
0
0
0.111
0.564
0
0
0.564
0.13
0
0
0.149
0.564
0
0
0.167
0
0
0.564
0.184
0.564
0
0
0.2
0.564
0
0
0.564
0.216
0
0
0.564
0.231
0
0
0.564
0.245
0
0
0.564
0.259
0
0
0
0
0.564
0.273
0.564
0.286
0
0
0.298
0
0.564
0
0.31
0
0
0.564
0.322
0.564
0
0
0
0.564
0.333
0
0.344
0
0
0.564
0.564
0.355
0
0
0.564
0.365
0
0
0.375
0
0.564
0
0.385
0
0
0.564
0.394
0.564
0
0
0.403
0
0
0.564
0.412
0.564
0
0
0.42
0
0
0.564
0.429
0.564
0
0
Table B.2b
289
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
clds/ca
alpha
0.901
0.674
0.439
0.261
0.147
0.079
0.041
0.021
0.011
0.005
0.003
0.001
0.001
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Vgs=-0.6
Vds
0.1
02
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
12
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3
Ids
0.593
1.061
1.364
1.543
1.651
1.722
1.776
1.821
1.862
1.902
1.94
1.979
2.017
2.055
2.093
2.131
2.169
2201
2.245
2.283
2.322
2.36
2.398
2.436
2.474
2.512
2.55
2.588
2.626
2.664
dlds/dlpk dlds/dPl
PI
Ipk
-3.104
I
-3.104
1
-3.104
1
-3.104
1
-3.104
1
-3.104
1
-3.104
1
-3.104
1
-3.104
I
-3.104
1
-3.104
1
-3.104
1
-3.104
1
-3.104
1
-3.104
1
-3.104
1
-3.104
1
-3.104
1
-3.104
I
-3.104
1
-3.104
1
-3.104
1
-3.104
1
-3.104
1
-3.104
1
-3.104
1
-3.104
1
-3.104
1
-3.104
1
-3.104
I
5Ids/cP2 <3Ids/cP3 clds/cV pk dlds/SX
Vpk
P3
lambda
P2
0
0.621
0.024
0
0
0.621
0.048
0
0.621
0.07
0
0
0.621
0.091
0
0
0.621
0
0.111
0
0
0.621
0.13
0
0
0.621
0.149
0
0.167
0.621
0
0
0.184
0
0.621
0
0.621
0
0.2
0
0.621
0
0.216
0
0.621
0
0.231
0
0.621
0
0.245
0
0.621
0.259
0
0
0.621
0
0213
0
0.621
0
0.286
0
0.621
0
0.298
0
0.621
0
0.31
0
0.621
0.322
0
0
0.621
0
0.333
0
0.344
0.621
0
0
0.621
0
0.355
0
0
0.621
0.365
0
0.621
0
0.375
0
0.621
0
0.385
0
0.621
0.394
0
0
0.621
0
0.403
0
0.621
0
0.412
0
0.621
0.42
0
0
0.621
0
0.429
0
Table B.2c
290
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
olds/ca
alpha
0.901
0.674
0.439
0.261
0.147
0.079
0.041
0.021
0.011
0.005
0.003
0.001
0.001
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
The tables shown below are the sensitivity analysis for Chalmer's circuit model utilizing the global equations for various VK, values. This optimization
routine was performed for the transconductance (gm). Column I of each table is the corresponding Vdl value for the sensitivity analysis and column 2 represents
the simulated value the transconductance (gm). Columns 3 - 9 of each table are the sensitivity of lds with respect to the parameter at the head of each column.
Vds=2.5 v
Vgs
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
gm
0.001
0.002
0.008
0.018
0.029
0.035
0.036
0.036
0.038
0.042
0.045
0.039
0.025
0.011
0.003
0.001
dgm/dlpk dgm/dP 1s dgm/dP 10 3gm/3P2 dgm/3P3 9gm/3VpkO 3gm/dVpks dgm/dA. dgm/dac dgm/dar
Ipk
Pis
PI0
AP2
AP3
VPK0
VPKS ALAMBD ALPHAC ALPHAR
0
1
•3.094
1.066
-4.172
0
-1.81
0
0.351
0.2956
1
0
-2.625
0.765
-2.514
0
0.351
0
-1.377
0.2765
1
-2.111
0
0.494
-1.274
0
-0.991
0.351
0
0.2153
1
-1.48
0
0.243
0
-0.629
0.1139
-0.383
0.351
0
0.149
1
-0.731
0
0.032
0
0.351
0
-0.305
0.0365
1
-0.006
-0.1
0
0
0
0.316
-0.086
0.351
0.008
0.579
1
0
-0.137
0.232
0
0
0
0.351
0.0015
0.938
-0.09
1
0
0.072
0
-0.026
0.351
0
0.0003
1
1
0
0
0
0
0
0
-0.092
0.351
1
0.769
0
0.06
-0.1
0
0.075
0
0.351
0
0.09
1
0
0.161
0
0
0
0.303
0.017
0.351
1
-0.33
0
0.026
0
0.272
0
0
0.154
0.351
-0.091
1
-1.025
0
0
0
-0.116
0.633
0.351
0
1
-1.665
0
-0.313
0
1.042
0
0
-0.64
0.351
-2.209
0
0
1
-0.545
-1.511
0
1.472
0.351
0
-2.689
0
1
-0.806
-2.741
0
1.932
0
0
0.351
Table B.3a
flgm/dal
ALPHA1
0.0013
0.0073
0.0236
0.0366
0.0256
0.0096
0.0027
0.0007
0.0001
0
0
0
0
0
0
0
w
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295
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Appendix C
Block Diagram of FET IV Curve Measurement
296
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
SUBROUTINE MODEL(VGS,PHIF,J,KEYON,IPP)
COMMON /PARAMS/X
COMMON /MDCM/RI ,R2, V1,V2
DIMENSION X(20),V 1(20).V2(20)
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
AIPK
APIS
AP10
AP2
AP3
VPKO
VPKS
ALAMBDA
ALPHAC
ALPHAR
ALPHA 1
VGS=0.0
REAL AIDS.GM
AIPK=12.
APIS=2.0679
API 0=3.1892
AP2=.95
AP3=5.
VPKO—. 1
VPKS=0.
ALAMBDA=.2161222
ALPHAC=3.
ALPHAR=.6
ALPHA I=1.7423
AIPK=X(1)
APIS=X(2)
AP10=X(3)
AP2=X(4)
AP3=X(5)
VPK0=X(6)
VPKS=X(7)
ALAMBDA=X(8)
ALPHAC=X(9)
ALPHAR=X( 10)
ALPHA1=X(11)
C
C
VDS=0.5
VGS—0.7
DO 1=1,16
P4029=0.
P4030=0.
P4031=0.
P4032=0.
P4033=0.
P4034=0.
297
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
P4035=0.
P4036=0.
P4037=0.
P4038=0.
P4039=0.
C
VDS=3.0
P4229=0.
P4230=0.
P4231=0.
P4232=0.
P4233=0.
P4234=0.
P4235=0.
P4236=0.
P4237=0.
P4238=0.
P4239=0.
ANUM1=ALPHAC* VDS
P4442=ALPHAC
P4429=0.
P4430=0.
P4431=0.
P4432=0.
P4433=0.
P4434=0.
P4435=0.
P4436=0.
P4437=VDS
P4438=0.
P4439=0.
ANUM2=EXP(-ANUM 1)
P4544=((EXP((0.-ANUM I )))*(0.-1))
P4529=0.
P4530=0.
P4531=0.
P4532=0.
P4533=0.
P4534=0.
P4535=0.
P4536=0.
P453 7=0.+P4544* P4437
P4538=0.
P4539=0.
ANUM3=EXP( ANUM1)
P4644=(EXP(ANUM 1))
P4629=0.
P4630=0.
P4631=0.
P4632=0.
P4633=0.
P4634=0.
P4635=0.
P4636=0.
P4637=0.+P4644* P4437
P4638=0.
P4639=0.
298
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
ANUM4=ANUM2/ANUM3
P4745=( 1/ANUM3)
P4746=((0.-ANUM2)/( ANUM3 **2))
P4729=0.
P4730=0.
P473I=0.
P4732=0.
P4733=0.
P4734=0.
P4735=0.
P4736=0.
P4737=0.+P4745*P4537+P4746*P4637
P4738=0.
P4739=0.
ANUM5= I .-ANUM4
P4847=(0.-l)
P4829=0.
P4830=0.
P483l=0.
P4832=0.
P4833=0.
P4834=0.
P4835=0.
P4836=0.
P4837=0.+P4847*P4737
P4838=0.
P4839=0.
ANUM6= I .+ANUM4
P4947=1
P4929=0.
P4930=0.
P493I=0.
P4932=0.
P4933=0.
P4934=0.
P4935=0.
P4936=0.
P4937=0.+P4947*P4737
P4938=0.
P4939=0.
ANUM7=ANUM5/ANUM6
P5048=(l/ANUM6)
P5049=((0.-ANUM5)/(ANUM6**2))
P5029=0.
P5030=0.
P503I=0.
P5032=0.
P5033=0.
P5034=0.
P5035=0.
P5036=0.
P5037=0.+P5048*P4837+P5049*P4937
P5038=0.
P5039=0.
ANUM8=VPKS-VPK0
P5129=0.
299
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
P5130=0.
P5131=0.
P5132=0.
P5133=0.
P5134=(0.-I)
P5135=1
P5136=0.
P5137=0.
P5138=0.
P5139=0.
VPK=VPKO+(ANUM8*ANUM7)
P5251=ANUM7
P5250=ANUM8
P5229=0.
P5230=0.
P5231=0.
P5232=0.
P5233=0.
P5234=I+P5251*P5134
P5235=0.+P5251*P5135
P5236=0.
P5237=0.+P5250* P5037
P5238=0.
P5239=0.
ANUM10=ALPHAC* 1.5*VDS
P5342=(ALPHAC* 1.5)
P5329=0.
P5330=0.
P5331=0.
P5332=0.
P5333=0.
P5334=0.
P5335=0.
P5336=0.
P5337=( 1.5* VDS)
P5338=0.
P5339=0.
ANUM 11=EXP( ANUM 10)
P5553=(EXP( ANUM 10))
P5529=0.
P5530=0.
P5531=0.
P5532=0.
P5533=0.
P5534=0.
P5535=0.
P5536=0.
P5537=0.+P5553*P5337
P5538=0.
P5539=0.
ANUM 12=EXP(- ANUM 10)
P5653=((EXP((0.-ANUM 10)))*(0.-1))
P5629=0.
P5630=0.
P5631=0.
P5632=0.
300
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
P5633=0.
P5634=0.
P5635=0.
P5636=0.
P5637=0.+P5653*P5337
P5638=0.
P5639=0.
ANUM 13=0.5*(ANUM 11+ANUM12)
P5755=0.5
P5756=0.5
P5729=0.
P5730=0.
P573I=0.
P5732=0.
P5733=0.
P5734=0.
P5735=0.
P5736=0.
P5737=0.+P5755*P5537+P5756*P5637
P5738=0.
P5739=0.
ANUM 14=(ANUMI 3)**2
P5957=(2*(ANUM 13 **(2-1)))
P5929=0.
P5930=0.
P5931=0.
P5932=0.
P5933=0.
P5934=0.
P5935=0.
P5936=0.
P5937=0.+P5957*P5737
P5938=0.
P5939=0.
ANUM 15=AP 10/AP1S
P6029=0.
P6030=((0.-AP 10)/(AP1S* *2))
P6031=(1/AP1S)
P6032=0.
P6033=0.
P6034=0.
P6035=0.
P6036=0.
P6037=0.
P6038=0.
P6039=0.
ANUM 16=ANUM 15-1.
P6160=1
P6129=0.
P6130=0.+P6160* P6030
P6131=0.+P6160* P6031
P6132=0.
P6133=0.
P6134=0.
P6135=0.
P6136=0.
301
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
P6137=0.
P6138=0.
P6139=0.
ANUM 17=ANUM 16/ANUM14
P6261=(1/ANUM14)
P6259=((0.-ANUM 16)/(ANUM 14* *2))
P6229=0.
P6230=0.+P6261* P6130
P6231=0.+P6261* P6131
P6232=0.
P6233=0.
P6234=0.
P6235=0.
P6236=0.
P6237=0.+P6259* P5937
P6238=0.
P6239=0.
AP1=AP 1S*( 1,+ANUM 17)
P6362=AP1S
P6329=0.
P6330=( 1.+ANUM 17)+P6362* P6230
P6331=0.+P6362* P6231
P6332=0.
P6333=0.
P6334=0.
P6335=0.
P6336=0.
P6337=0.+P6362*P6237
P6338=0.
P6339=0.
ANUM 18=VGS-VPK
P6440=l
P6452={0.-1)
P6429=0.
P6430=0.
P6431=0.
P6432=0.
P6433=0.
P6434=0.+P6452*P5234
P6435=0.+P6452* P5235
P6436=0.
P6437=0.+P6452*P5237
P6438=0.
P6439=0.
APSI1=AP 1*ANUM 18
P6563=ANUM18
P6564=AP1
P6529=0.
P6530=0.+P6563*P6330
P6531=0.+P6563*P6331
P6532=0.
P6533=0.
P6534=0.+P6564* P6434
P6535=0.+P6564*P6435
P6536=0.
P6537=0.+P6563*P6337+P6564*P6437
302
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
P6538=0.
P6539=0.
ANUM 19=(ANUM 18)* *2
P6664=(2*(ANUM 18**(2-1)))
P6629=0.
P6630=0.
P663I=0.
P6632=0.
P6633=0.
P6634=0.+P6664* P6434
P6635=0.+P6664*P6435
P6636=0.
P6637=0.+P6664* P6437
P6638=0.
P6639=0.
ANUM20=(ANUM 18)**3
P6764=(3 *(ANUM 18**(3-1)))
P6729=0.
P6730=0.
P6731=0.
P6732=0.
P6733=0.
P6734=0.+P6764* P6434
P6735=0.+P6764* P6435
P6736=0.
P6737=0.+P6764* P6437
P6738=0.
P6739=0.
APSI2=AP2* ANUM 19
P6966=AP2
P6929=0.
P6930=0.
P693l=0.
P6932=ANUM 19
P6933=0.
P6934=0.+P6966* P6634
P6935=0.+P6966*P6635
P6936=0.
P6937=0.+P6966* P6637
P6938=0.
P6939=0.
APSI3=AP3 *ANUM20
P7067=AP3
P7029=0.
P7030=0.
P7031=0.
P7032=0.
P7033=ANUM20
P7034=0.+P7067* P6734
P7035=0.+P7067*P6735
P7036=0.
P7037=0.+P7067* P6737
P7038=0.
P7039=0.
APSI=APSI 1+APSI2+APSI3
P7165=1
303
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
P7169=1
P7!70=l
P7129=0.
P7130=0.+P7165*P6530
P7131 =0.+P7165*P6531
P7132=0.+P7169* P6932
P7133=0.+P7170*P7033
P7134=0.+P7165* P6534+P7169* P6934+P7170* P7034
P7135=0.+P7165*P6535+P7169* P6935+P7170* P7035
P7136=0.
P7137=0.+P7165* P6537+P7169*P6937+P7170* P7037
P7138=0.
P7139=0.
ANUM21=EXP(-APSI)
P7271=((EXP((0.-APSI)))*(0.-1))
P7229=0.
P7230=0.+P7271*P7130
P7231=0.+P7271 *P7131
P7232=0.+P7271*P7132
P7233=0.+P7271*P7133
P7234=0.+P7271*P7134
P7235=0.+P7271*P7135
P7236=0.
P7237=0.+P7271*P7137
P7238=0.
P7239=0.
ANUM22=EXP(APS1)
P7371=(EXP(APS1))
P7329=0.
P7330=0.+P7371*P7130
P7331=0.+P7371*P7131
P7332=0.+P7371*P7132
P7333=0.+P7371*P7133
P7334=0.+P7371*P7134
P7335=0.+P7371*P7135
P7336=0.
P7337=0.+P7371*P7137
P7338=0.
P7339=0.
ANUM23=ANUM21/ANUM22
P7472=( 1/ANUM22)
P7473=((0.-ANUM21)/(ANUM22* *2))
P7429=0.
P7430=0.+P7472*P7230+P7473*P7330
P7431=0.+P7472*P7231+P7473*P7331
P7432=0.+P7472*P7232+P7473 *P7332
P7433=0.+P7472*P7233+P7473*P7333
P7434=0.+P7472* P7234+P7473* P7334
P7435=0.+P7472* P7235+P7473*P7335
P7436=0.
P7437=0.+P7472* P7237+P7473* P7337
P7438=0.
P7439=0.
ANUM24= 1.-ANUM23
P7574=(0.-l)
P7529=0.
304
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
P7530=0.+P7574*P7430
P7531=0.+P7574*P7431
P7532=0.+P7574*P7432
P7533=0.+P7574*P7433
P7534=0.+P7574*P7434
P7535=0.+P7574*P7435
P7536=0.
P7537=0.+P7574*P7437
P7538=0.
P7539=0.
ANUM25= 1.+ANUM23
P7674=!
P7629=0.
P7630=0.+P7674*P7430
P7631=0.+P7674*P7431
P7632=0.+P7674*P7432
P7633=0.+P7674*P7433
P7634=0.+P7674* P7434
P7635=0.+P7674*P7435
P7636=0.
P7637=0.+P7674*P7437
P7638=0.
P7639=0.
ANUM26=ANUM24/ANUM25
P7775=( 1/ANUM25)
P7776=((0.-ANUM24)/(ANUM25**2))
P7729=0.
P7730=0.+P7775*P7530+P7776*P7630
P7731=0.+P7775*P7531+P7776*P7631
P7732=0.+P7775*P7532+P7776*P7632
P7733=0.+P7775*P7533+P7776*P7633
P7734=0.+P7775*P7534+P7776*P7634
P7735=0.+P7775*P7535+P7776*P7635
P7736=0.
P7737=0.+P7775*P7537+P7776*P7637
P7738=0.
P7739=0.
ANUM27=ALPHA 1*( 1 +ANUM26)
P7877=ALPHA I
P7829=0.
P7830=0.+P7877*P7730
P7831=0.+P7877*P7731
P7832=0.+P7877*P7732
P7833=0.+P7877*P7733
P7834=0.+P7877* P7734
P7835=0.+P7877* P7735
P7836=0.
P7837=0.+P7877*P7737
P7838=0.
P7839=( 1.+ANUM26)
ALPHA V=ALPHAR+ANUM27
P7978=l
P7929=0.
P7930=0.+P7978*P7830
P7931=0.+P7978*P7831
P7932=0.+P7978*P7832
305
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
P7933=0.+P7978*P7833
P7934=0.+P7978*P7834
P7935=0.+P7978*P7835
P7936=0.
P7937=0.+P7978*P7837
P7938=l
P7939=0.+P7978*P7839
ANUM28=ALAMBDA*VDS
P8042=ALAMBDA
P8029=0.
P8030=0.
P8031=0.
P8032=0.
P8033=0.
P8034=0.
P8035=0.
P8036=VDS
P8037=0.
P8038=0.
P8039=0.
ANUM29= I .+ANUM28
P8180=1
P8129=0.
P8130=0.
P8131=0.
P8132=0.
P8133=0.
P8134=0.
P8135=0.
P8136=0.+P8180*P8036
P8137=0.
P8138=0.
P8139=0.
ANUM30=ALPHAV* VDS
P8279=VDS
P8242=ALPHAV
P8229=0.
P8230=0.+P8279*P7930
P8231=0.+P8279*P7931
P8232=0.+P8279*P7932
P8233=0.+P8279*P7933
P8234=0.+P8279*P7934
P8235=0.+P8279*P7935
P8236=0.
P8237=0.+P8279*P7937
P8238=0.+P8279* P7938
P8239=0.+P8279*P7939
ANUM31=EXP(-ANUM30)
P8382=((EXP((0.-ANUM30)))*(0.-1))
P8329=0.
P8330=0.+P8382*P8230
P8331=0.+P8382*P8231
P8332=0.+P8382*P8232
P8333=0.+P8382* P8233
P8334=0.+P8382*P8234
P8335=0.+P8382*P8235
306
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
P8336=0.
P8337=0.+P8382*P8237
P8338=0.+P8382*P8238
P8339=0.+P8382*P8239
ANUM32=EXP(ANUM30)
P8482=(EXP(ANUM30))
P8429=0.
P8430=0.+P8482* P8230
P8431=0.+P8482*P8231
P8432=0.+P8482*P8232
P8433=0.+P8482*P8233
P8434=0.+P8482*P8234
P8435=0.+P8482*P8235
P8436=0.
P8437=0.+P8482*P8237
P8438=0.+P8482* P8238
P8439=0.+P8482*P8239
ANUM33=ANUM31/ANUM32
P8583=(1/ANUM32)
P8584=((0.-ANUM31)/(ANUM32**2))
P8529=0.
P8530=0.+P8583*P8330+P8584*P8430
P8531=0.+P8583 *P8331+P8584* P8431
P8532=0.+P8583*P8332+P8584*P8432
P8533=0.+P8583*P8333+P8584*P8433
P8534=0.+P8583*P8334+P8584*P8434
P8535=0.+P8583* P8335+P8584* P8435
P8536=0.
P8537=0.+P8583 *P8337+P8584* P843 7
P8538=0.+P8583*P8338+P8584*P8438
P8539=0.+P8583* P8339+P8584* P8439
ANUM34=1 .-ANUM33
P8685=(0.-I)
P8629=0.
P8630=0.+P8685*P8530
P8631=0.+P8685*P8531
P8632=0.+P8685*P8532
P8633=0.+P8685*P8533
P8634=0.+P8685*P8534
P8635=0.+P8685*P8535
P8636=0.
P8637=0.+P8685*P8537
P8638=0.+P8685*P8538
P8639=0.+P8685*P8539
ANUM35=1 .+ANUM33
P8785=l
P8729=0.
P8730=0.+P8785*P8530
P8731=0.+P8785*P8531
P8732=0.+P8785*P8532
P8733=0.+P8785*P8533
P8734=0.+P8785*P8534
P8735=0.+P8785*P8535
P8736=0.
P8737=0.+P8785*P8537
P8738=0.+P8785*P8538
307
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
P8739=0.+P8785*P8539
ANUM36=ANUM34/ANUM35
P8886=( 1/ANUM35)
P8887=((0.-ANUM34)/(ANUM35**2))
P8829=0.
P8830=0.+P8886*P8630+P8887*P8730
P8831=0.+P8886*P8631+P8887*P8731
P8832=0.+P8886*P8632+P8887*P8732
P8833=0.+P8886*P8633+P8887*P8733
P8834=0.+P8886*P8634+P8887*P8734
P8835=0.+P8886*P8635+P8887*P8735
P8836=0.
P8837=0.+P8886*P8637+P8887*P8737
P8838=0.+P8886* P8638+P8887* P8738
P8839=0.+P8886*P8639+P8887*P8739
ANUM37=AIPK*(1 .+ANUM26)
P8977=AIPK
P8929=( 1.+ANUM26)
P8930=0.+P8977* P7730
P893 l=0.+P8977*P7731
P8932=0.+P8977*P7732
P8933=0.+P8977*P7733
P8934=0.+P8977* P7734
P8935=0.+P8977*P7735
P8936=0.
P8937=0.+P8977* P7737
P8938=0.
P8939=0.
ANUM38=ANUM37*ANUM29*ANUM36
P9089=(ANUM29*ANUM36)
P9081={ANUM37* ANUM36)
P9088=(ANUM3 7*ANUM29)
P9029=0.+P9089*P8929
P9030=0.+P9089* P8930+P9088* P8830
P9031=0.+P9089*P8931+P9088* P8831
P9032=0.+P9089* P8932+P9088* P8832
P9033=0.+P9089*P8933+P9088*P8833
P9034=0.+P9089* P8934+P9088* P8834
P9035=0.+P9089*P8935+P9088*P8835
P9036=0.+P9081*P8136
P9037=0.+P9089*P8937+P9088*P8837
P9038=0.+P9088*P8838
P9039=0.+P9088*P8839
AIDS=ANUM3 8
P9190=I
P9129=0 .+P9190* P9029
P9130=0.+P9190*P9030
P9131=0.+P9190*P9031
P9132=0.+P9190* P9032
P9133=0.+P9190*P9033
P9134=0.+P9190*P9034
P9135=0.+P9190*P9035
P9136=0.+P9190*P9036
P9137=0.+P9190*P9037
P9138=0.+P9190*P9038
P9139=0.+P9190*P9039
308
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
A IDS= 1000. *ANUM3 8
P9I90=I000.
P9129=0.+P9190*P9029
P9130=0.+P9190*P9030
P9131 =0.+P9190* P9031
P9I32=0.+P9I90*P9032
P9I33=0.+P9190*P9033
P9134=0.+P9190* P9034
P9135=0.+P9190*P9035
P9136=0.+P9190*P9036
P9I37=0.+P9190*P9037
P9138=0.+P9190*P9038
P9139=0.+P9190*P9039
ANUM39=AIPK*ANUM29*ANUM36
P9381=(AIPK*ANUM36)
P9388=(AIPK*ANUM29)
P9329=(ANUM29*ANUM36)
P9330=0.+P9388*P8830
P9331=0.+P9388*P8831
P9332=0.+P9388*P8832
P9333=0.+P9388*P8833
P9334=0.+P9388* P8834
P9335=0.+P9388*P8835
P9336=0.+P9381*P8136
P9337=0.+P9388*P8837
P9338=0.+P9388*P8838
P9339=0.+P9388*P8839
ANUM40=2.* AP2* ANUM 18
P9464=(2.*AP2)
P9429=0.
P9430=0.
P943l=0.
P9432=(2.*ANUM18)
P9433=0.
P9434=0.+P9464*P6434
P9435=0.+P9464*P6435
P9436=0.
P9437=0.+P9464* P6437
P9438=0.
P9439=0.
ANUM41=3 .*AP3 *ANUM 19
P9666=(3.*AP3)
P9629=0.
P9630=0.
P9631=0.
P9632=0.
P9633=(3.*ANUM19)
P9634=0.+P9666*P6634
P9635=0.+P9666*P6635
P9636=0.
P9637=0.+P9666* P6637
P9638=0.
P9639=0.
ANUM42=EXP(APSI)
P9871=(EXP(APSI))
P9829=0.
309
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
P9830=0.+P9871 *P7130
P9831 =0.+P9871*P713 1
P9832=0.+P9871*P7132
P9833=0.+P9871*P7133
P9834=0.+P987l*P7134
P9835=0.+P9871*P7135
P9836=0.
P9837=0.+P9871*P7137
P9838=0.
1*9839=0.
ANUM43=EXP(-APSI)
P9971 =((EXP((0.-APSI)))*(0.-1))
P9929=0.
P9930=0.+P9971*P7130
P9931=0.+P9971*P7131
P9932=0.+P9971*P7132
P9933=0.+P9971*P7133
P9934=0.+P9971*P7134
P9935=0.+P9971*P7135
P9936=0.
P9937=0.+P9971*P7137
P9938=0.
P9939=0.
ANUM44=0.5*(ANUM42+ANUM43)
PDW98=0.5
PDW99=0.5
PDW29=0.
PDW30=0.+PD W98* P9830+PDW99* P9930
PDW31 =0.+PD W98* P9831+PDW99* P9931
PDW32=0.+PDW98*P9832+PDW99*P9932
PDW33=0.+PDW98*P9833+PDW99*P9933
PDW34=0.+PDW98*P9834+PDW99*P9934
PDW35=0.+PDW98*P9835+PDW99*P9935
PDW36=0.
PDW37=0.+PD W98* P9837+PDW99* P9937
PDW38=0.
PDW39=0.
ANUM45={ANUM44)* *2
PDXDW=(2*(ANUM44**(2-1)))
PDX29=0.
PDX30=0.+PDXD W* PDW30
PDX31=0.+PDXD W* PDW31
PDX32=0.+PDXDW* PD W32
PDX33=0.+PDXDW*PDW33
PDX34=0.+PDXD W* PDW34
PDX35=0.+PDXD W* PDW3 5
PDX36=0.
PDX37=0.+PDXDW*PDW37
PDX38=0.
PDX39=0.
ANUM46=AP 1+ANUM40+ANUM41
PDY63=1
PDY94=I
PDY96=1
PDY29=0.
PDY30=0.+PDY63*P6330
310
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
PDY31=0+PDY63*P6331
PDY32=0.+PD Y94* P9432
PDY33=0.+PDY96*P9633
PDY34=0.+PDY94*P9434+PDY96*P9634
PDY35=0+PDY94*P9435+PDY96*P9635
PDY36=0.
PDY37=0.+PDY63*P6337+PDY94*P9437+PDY96*P9637
PDY38=0.
PDY39=0.
ANUM47=ANUM46/ANUM45
PDZDY=(1/ANUM45)
PDZDX=((0.-ANUM46)/( ANUM45* *2))
PDZ29=0.
PDZ30=0.+PDZDY*PDY30+PDZDX*PDX30
PDZ31=0.+PDZDY*PDY31+PDZDX*PDX31
PDZ32=0.+PDZDY*PDY32+PDZDX*PDX32
PDZ33=0.+PDZDY*PDY33+PDZDX*PDX33
PDZ34=0.+PDZDY* PDY34+PDZDX* PDX34
PDZ3 5=0.+PDZDY* PDY35+PDZDX* PDX3 5
PDZ36=0.
PDZ37=0.+PDZDY*PDY37+PDZDX*PDX37
PDZ38=0.
PDZ39=0.
GM=ANUM39*ANUM47
PEA93=ANUM47
PEADZ=ANUM39
PEA29=0.+PEA93 *P9329
PEA30=0.+PEA93 *P9330+PEADZ* PDZ3 0
PEA31=0.+PEA93*P9331+PEADZ*PDZ31
PEA32=0.+PEA93*P9332+PEADZ*PDZ32
PEA33=0.+PEA93*P9333+PEADZ*PDZ33
PEA34=0.+PEA93 *P9334+PEADZ* PDZ34
PEA35=0.+PEA93 *P9335+PEADZ* PDZ3 5
PEA36=0.+PEA93*P9336
PEA37=0.+PEA93*P9337+PEADZ*PDZ37
PEA38=0.+PEA93 *P933 8
PEA39=0.+PEA93*P9339
GM=I000.*GM
PEAEA=1000.
PEA29=0.+PEAEA* PEA29
PEA30=0.+PEAEA*PEA30
PEA31=0.+PEAEA*PEA31
PEA32=0.+PEAEA*PEA32
PEA33=0.+PEAEA*PEA33
PEA34=0.+PEAEA* PEA34
PEA3 5=0.+PEAEA* PEA3 5
PEA36=0.+PEAEA*PEA36
PEA37=0.+PEAEA*PEA37
PEA3 8=0.+PEAEA* PEA3 8
PEA39=0+PEAEA*PEA39
C
C
C
C
SENS 1=AIPK*PEA29/GM
SENS2=AP 1S* PEA30/GM
SENS3=AP10*PEA31/GM
SENS4=AP2* PEA32/GM
311
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
C
C
C
C
C
C
C
SENS5=AP3 *PEA3 3/GM
SENS6=VPK0*PEA34/GM
SENS7=VPKS*PEA35/GM
SENS8=ALAMBDA*PEA36/GM
SENS9=ALPHAC*PEA37/GM
SENS 10=ALPHAR* PEA3 8/GM
SENS I l=ALPHAl*PEA39/GM
C
C3
WRITE(36,3)VGS,GM,SENSI,SENS2,SENS3,SENS4
FORMAT(X,7(F7.3,2X))
C
C8
WRITE(37,8)VGS,GM,SENS5,SENS6,SENS7,SENS8
FORMAT(X.7(F7.3,2X))
C
C 12
WRITE(38,12)VGS,GM,SENS9,SENS 10.SENS 11
FORMAT(X,7(F7.4,2X))
C
C 10
C
C
WRITE(20,I0)VGS,GM.AIDS
FORMAT(X,7(F7.5,2X))
VGS=VGS+0.1
END DO
Vl(l)=P9129
VI(2)=P9130
V1(3)=P9131
Vt(4)=P9132
V1(5)=P9133
V1(6)=P9134
V1(7)=P9135
V1(8)=P9136
V1(9)=P9137
V1(10)=P9138
V l(l 1)=P9139
V2( 1)=PEA29
V2(2)=PEA30
V2(3)=PEA31
V2(4)=PEA32
V2(5)=PEA33
V2(6)=PEA34
V2(7)=PEA35
V2(8)=PEA36
V2(9)=PEA37
V2(10)=PEA38
V2(l 1)=PEA39
R1=AIDS
R2=GM
RETURN
C
STOP
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
C
END
NO ADDITIONS ARE REQUIRED
313
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
SYMBOL
P4029
P4030
P4031
P4032
P4033
P4034
P4035
P4036
P4037
P4038
P4039
P4229
P4230
P423I
P4232
P4233
P4234
P4235
P4236
P4237
P4238
P4239
P4442
P4429
P4430
P4431
P4432
P4433
P4434
P4435
P4436
P4437
P4438
P4439
P4544
P4529
P4530
P453I
P4532
P4533
P4534
P4535
P4536
P4537
P4538
P4539
P4644
P4629
P4630
P4631
P4632
P4633
P4634
P4635
P4636
DEPENDENT INDEPE1
AIPK
VGS
APIS
VGS
AP10
VGS
AP2
VGS
AP3
VGS
VPKO
VGS
VPKS
VGS
ALAMBDA
VGS
ALPHAC
VGS
ALPHAR
VGS
ALPHA 1
VGS
AIPK
VDS
APIS
VDS
AP10
VDS
AP2
VDS
AP3
VDS
VPKO
VDS
VDS
VPKS
ALAMBDA
VDS
ALPHAC
VDS
ALPHAR
VDS
ALPHA 1
VDS
VDS
ANUM1
AIPK
ANUM1
APIS
ANUM1
ANUM I
AP10
AP2
ANUM1
AP3
ANUM1
VPKO
ANUM I
VPKS
ANUM1
ALAMBDA
ANUM1
ALPHAC
ANUM1
ALPHAR
ANUM1
ALPHA 1
ANUM I
ANUM I
ANUM2
AIPK
ANUM2
APIS
ANUM2
APIO
ANUM2
AP2
ANUM2
AP3
ANUM2
VPKO
ANUM2
VPKS
ANUM2
ALAMBDA
ANUM2
ALPHAC
ANUM2
ALPHAR
ANUM2
ALPHA 1
ANUM2
ANUM I
ANUM3
AIPK
ANUM3
APIS
ANUM3
APIO
ANUM3
AP2
ANUM3
AP3
ANUM3
VPKO
ANUM3
VPKS
ANUM3
ALAMBDA
ANUM3
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
P4637
P4638
P4639
P4745
P4746
P4729
P4730
P4731
P4732
P4733
P4734
P4735
P4736
P4737
P4738
P4739
P4847
P4829
P4830
P4831
P4832
P4833
P4834
P4835
P4836
P4837
P4838
P4839
P4947
P4929
P4930
P4931
P4932
P4933
P4934
P4935
P4936
P4937
P4938
P4939
P5048
P5049
P5029
P5030
P5031
P5032
P5033
P5034
P5035
P5036
P5037
P5038
P5039
P5129
P5130
P5131
ANUM3
ANUM3
ANUM3
ANUM4
ANUM4
ANUM4
ANUM4
ANUM4
ANUM4
ANUM4
ANUM4
ANUM4
ANUM4
ANUM4
ANUM4
ANUM4
ANUM5
ANUM5
ANUM5
ANUM5
ANUM5
ANUM5
ANUM5
ANUM5
ANUM5
ANUM5
ANUM5
ANUM5
ANUM6
ANUM6
ANUM6
ANUM6
ANUM6
ANUM6
ANUM6
ANUM6
ANUM6
ANUM6
ANUM6
ANUM6
ANUM7
ANUM7
ANUM7
ANUM7
ANUM7
ANUM7
ANUM7
ANUM7
ANUM7
ANUM7
ANUM7
ANUM7
ANUM7
ANUM8
ANUM8
ANUM8
ALPHAC
ALPHAR
ALPHA!
ANUM2
ANUM3
AIPK
APIS
APIO
AP2
AP3
VPKO
VPKS
ALAMBDA
ALPHAC
ALPHAR
ALPHA 1
ANUM4
AIPK
APIS
APIO
AP2
AP3
VPKO
VPKS
ALAMBDA
ALPHAC
ALPHAR
ALPHA 1
ANUM4
AIPK
APIS
APIO
AP2
AP3
VPKO
VPKS
ALAMBDA
ALPHAC
ALPHAR
ALPHA 1
ANUM5
ANUM6
AIPK
APIS
APIO
AP2
AP3
VPKO
VPKS
ALAMBDA
ALPHAC
ALPHAR
ALPHA 1
AIPK
APIS
APIO
315
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
P5I32
P5133
P5134
P5135
P5136
P5137
P5138
P5139
P5251
P5250
P5229
P5230
P5231
P5232
P5233
P5234
P5235
P5236
P5237
P5238
P5239
P5342
P5329
P5330
P5331
P5332
P5333
P5334
P5335
P5336
P5337
P5338
P5339
P5553
P5529
P5530
P5531
P5532
P5533
P5534
P5535
P5536
P5537
P5538
P5539
P5653
P5629
P5630
P5631
P5632
P5633
P5634
P5635
P5636
P5637
P5638
ANUM8
ANUM8
ANUM8
ANUM8
ANUM8
ANUM8
ANUM8
ANUM8
VPK
VPK
VPK
VPK
VPK
VPK
VPK
VPK
VPK
VPK
VPK
VPK
VPK
ANUM 10
ANUM 10
ANUM 10
ANUM 10
ANUM 10
ANUM 10
ANUM 10
ANUM 10
ANUM 10
ANUM 10
ANUM 10
ANUM 10
ANUM 11
ANUM 11
ANUM 11
ANUM 11
ANUM 11
ANUM 11
ANUM 11
ANUM 11
ANUM11
ANUM 11
ANUM 11
ANUM 11
ANUM 12
ANUM 12
ANUM 12
ANUM 12
ANUM 12
ANUM12
ANUM 12
ANUM 12
ANUM 12
ANUM 12
ANUM 12
AP2
AP3
VPKO
VPKS
ALAMBDA
ALPHAC
ALPHAR
ALPHA 1
ANUM8
ANUM7
AIPK
APIS
AP10
AP2
AP3
VPKO
VPKS
ALAMBDA
ALPHAC
ALPHAR
ALPHA 1
VDS
AIPK
APIS
AP10
AP2
AP3
VPKO
VPKS
ALAMBDA
ALPHAC
ALPHAR
ALPHAI
ANUMI0
AIPK
APIS
AP10
AP2
AP3
VPKO
VPKS
ALAMBDA
ALPHAC
ALPHAR
ALPHA1
ANUM 10
AIPK
APIS
AP10
AP2
AP3
VPKO
VPKS
ALAMBDA
ALPHAC
ALPHAR
316
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
P5639
P5755
P5756
P5729
P5730
P5731
P5732
P5733
P5734
P5735
P5736
P5737
P5738
P5739
P5957
P5929
P5930
P5931
P5932
P5933
P5934
P5935
P5936
P5937
P5938
P5939
P6029
P6030
P6031
P6032
P6033
P6034
P6035
P6036
P6037
P6038
P6039
P6160
P6129
P6130
P6131
P6132
P6133
P6I34
P6135
P6I36
P6137
P6138
P6139
P6261
P6259
P6229
P6230
P6231
P6232
P6233
ANUM12
ANUMI3
ANUM13
ANUM13
ANUM13
ANUM13
ANUM13
ANUM13
ANUM13
ANUM13
ANUM13
ANUM13
ANUM13
ANUM13
ANUM14
ANUM14
ANUM14
ANUM14
ANUM14
ANUM14
ANUM14
ANUM14
ANUM14
ANUM14
ANUM14
ANUM14
ANUM15
ANUM15
ANUM15
ANUM15
ANUM15
ANUM15
ANUM15
ANUM15
ANUM15
ANUM15
ANUM15
ANUM16
ANUM16
ANUM16
ANUM16
ANUM16
ANUM16
ANUMI6
ANUM16
ANUM16
ANUM16
ANUM16
ANUM16
ANUM17
ANUM17
ANUM17
ANUM17
ANUM17
ANUM17
ANUM17
ALPHA1
ANUM11
ANUM12
AIPK
APIS
APIO
AP2
AP3
VPKO
VPKS
ALAMBDA
ALPHAC
ALPHAR
ALPHA1
ANUM13
AIPK
APIS
APIO
AP2
AP3
VPKO
VPKS
ALAMBDA
ALPHAC
ALPHAR
ALPHA1
AIPK
APIS
APIO
AP2
AP3
VPKO
VPKS
ALAMBDA
ALPHAC
ALPHAR
ALPHA1
ANUM15
AIPK
APIS
APIO
AP2
AP3
VPKO
VPKS
ALAMBDA
ALPHAC
ALPHAR
ALPHA1
ANUM16
ANUM14
AIPK
APIS
APIO
AP2
AP3
317
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
P6234
P6235
P6236
P6237
P6238
P6239
P6362
P6329
P6330
P633I
P6332
P6333
P6334
P6335
P6336
P6337
P6338
P6339
P6440
P6452
P6429
P6430
P6431
P6432
P6433
P6434
P6435
P6436
P6437
P6438
P6439
P6563
P6564
P6529
P6530
P6531
P6532
P6533
P6534
P6535
P6536
P6537
P6538
P6539
P6664
P6629
P6630
P6631
P6632
P6633
P6634
P6635
P6636
P6637
P6638
P6639
ANUM17
VPKO
ANUM17
VPKS
ANUM17
ALAMBDA
ANUM17
ALPHAC
ANUMI7
ALPHAR
ANUM17
ALPHA 1
ANUM17
API
API
AIPK
API
APIS
API
APIO
API
AP2
API
AP3
API
VPKO
API
VPKS
API
ALAMBDA
API
ALPHAC
API
ALPHAR
API
ALPHA 1
ANUM18
VGS
VPK
ANUM18
AIPK
ANUM18
ANUM18
APIS
ANUM18
APIO
AP2
ANUMI8
ANUM18
AP3
ANUM18
VPKO
ANUM18
VPKS
ANUM18
ALAMBDA
ANUM18
ALPHAC
ANUM18
ALPHAR
ANUM18
ALPHA 1
APSI1
API
APSI1
ANUM18
APSI1
AIPK
APSI1
APIS
APSI1
APIO
APSI1
AP2
APSI1
AP3
APSI1
VPKO
APSI1
VPKS
ALAMBDA
APSI1
APSI1
ALPHAC
ALPHAR
APSI1
ALPHA1
APSI1
ANUM18
ANUM19
ANUM19
AIPK
ANUM19
APIS
APIO
ANUM19
ANUM19
AP2
ANUM19
AP3
ANUM19
VPKO
ANUM19
VPKS
ALAMBDA
ANUM19
ALPHAC
ANUM19
ALPHAR
ANUM19
ANUM19
ALPHA 1
318
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
P6764
P6729
P6730
P673I
P6732
P6733
P6734
P6735
P6736
P6737
P6738
P6739
P6966
P6929
P6930
P6931
P6932
P6933
P6934
P6935
P6936
P6937
P6938
P6939
P7067
P7029
P7030
P7031
P7032
P7033
P7034
P7035
P7036
P7037
P7038
P7039
P7165
P7169
P7170
P7129
P7130
P7131
P7132
P7133
P7134
P7135
P7136
P7137
P7138
P7139
P7271
P7229
P7230
P7231
P7232
P7233
ANUM20
ANUM20
ANUM20
ANUM20
ANUM20
ANUM20
ANUM20
ANUM20
ANUM20
ANUM20
ANUM20
ANUM20
APSI2
APSI2
APSI2
APSI2
APSI2
APSI2
APSI2
APSI2
APSI2
APSI2
APSI2
APSI2
APSI3
APSI3
APSI3
APSI3
APSI3
APSI3
APSI3
APSI3
APSI3
APSI3
APS13
APSI3
APSI
APSI
APSI
APSI
APSI
APSI
APSI
APSI
APSI
APSI
APSI
APSI
APSI
APSI
ANUM21
ANUM21
ANUM21
ANUM21
ANUM21
ANUM21
ANUM18
AIPK
APIS
APIO
AP2
APS
VPKO
VPKS
ALAMBDA
ALPHAC
ALPHAR
ALPHA I
ANUMI9
AIPK
APIS
APIO
AP2
AP3
VPKO
VPKS
ALAMBDA
ALPHAC
ALPHAR
ALPHA 1
ANUM20
AIPK
APIS
APIO
AP2
AP3
VPKO
VPKS
ALAMBDA
ALPHAC
ALPHAR
ALPHA 1
APSI1
APSI2
APSI3
AIPK
APIS
APIO
AP2
AP3
VPKO
VPKS
ALAMBDA
ALPHAC
ALPHAR
ALPHA 1
APSI
AIPK
APIS
APIO
AP2
AP3
319
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
P7234
P7235
P7236
P7237
P7238
P7239
P7371
P7329
P7330
P7331
P7332
P7333
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P7339
P7472
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P7574
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P7674
P7629
P7630
P7631
P7632
P7633
P7634
P7635
P7636
P7637
P7638
P7639
P7775
ANUM2I
ANUM2!
ANUM21
ANUM21
AMUM21
ANUM21
ANUM22
ANUM22
ANUM22
ANUM22
ANUM22
ANUM22
ANUM22
ANUM22
ANUM22
ANUM22
ANUM22
ANUM22
ANUM23
ANUM23
ANUM23
ANUM23
ANUM23
ANUM23
ANUM23
ANUM23
ANUM23
ANUM23
ANUM23
ANUM23
ANUM23
ANUM24
ANUM24
ANUM24
ANUM24
ANUM24
ANUM24
ANUM24
ANUM24
ANUM24
ANUM24
ANUM24
ANUM24
ANUM25
ANUM25
ANUM25
ANUM25
ANUM25
ANUM25
ANUM25
ANUM25
ANUM25
ANUM25
ANUM25
ANUM25
ANUM26
VPKO
VPKS
ALAMBDA
ALPHAC
ALPHAR
ALPHA1
APSI
AIPK
APIS
APIO
AP2
AP3
VPKO
VPKS
ALAMBDA
ALPHAC
ALPHAR
ALPHAI
ANUM21
ANUM22
AIPK
APIS
APIO
AP2
AP3
VPKO
VPKS
ALAMBDA
ALPHAC
ALPHAR
ALPHA1
ANUM23
AIPK
APIS
APIO
AP2
AP3
VPKO
VPKS
ALAMBDA
ALPHAC
ALPHAR
ALPHAI
ANUM23
AIPK
APIS
APIO
AP2
AP3
VPKO
VPKS
ALAMBDA
ALPHAC
ALPHAR
ALPHA1
ANUM24
320
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
P7776
P7729
P7730
P7731
P7732
P7733
P7734
P7735
P7736
P7737
P7738
P7739
P7877
P7829
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P7832
P7833
P7834
P7835
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P7837
P7838
P7839
P7978
P7929
P7930
P7931
P7932
P7933
P7934
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P7936
P7937
P7938
P7939
P8042
P8029
P8030
P8031
P8032
P8033
P8034
P8035
P8036
P8037
P8038
P8039
P8180
P8129
P8130
P8131
P8132
P8133
P8134
P8135
ANUM26
ANUM26
ANUM26
ANUM26
ANUM26
ANUM26
ANUM26
ANUM26
ANUM26
ANUM26
ANUM26
ANUM26
ANUM27
ANUM27
ANUM27
ANUM27
ANUM27
ANUM27
ANUM27
ANUM27
ANUM27
ANUM27
ANUM27
ANUM27
ALPHAV
ALPHAV
ALPHAV
ALPHAV
ALPHAV
ALPHAV
ALPHAV
ALPHAV
ALPHAV
ALPHAV
ALPHAV
ALPHAV
ANUM28
ANUM28
ANUM28
ANUM28
ANUM28
ANUM28
ANUM28
ANUM28
ANUM28
ANUM28
ANUM28
ANUM28
ANUM29
ANUM29
ANUM29
ANUM29
ANUM29
ANUM29
ANUM29
ANUM29
ANUM25
AIPK
APIS
APIO
AP2
AP3
VPKO
VPKS
ALAMBDA
ALPHAC
ALPHAR
ALPHA 1
ANUM26
AIPK
APIS
APIO
AP2
AP3
VPKO
VPKS
ALAMBDA
ALPHAC
ALPHAR
ALPHA 1
ANUM27
AIPK
APIS
APIO
AP2
AP3
VPKO
VPKS
ALAMBDA
ALPHAC
ALPHAR
ALPHA 1
VDS
AIPK
APIS
APIO
AP2
AP3
VPKO
VPKS
ALAMBDA
ALPHAC
ALPHAR
ALPHA 1
ANUM28
AIPK
APIS
APIO
AP2
AP3
VPKO
VPKS
321
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
P8136
P8137
P8I38
P8139
P8279
P8242
P8229
P8230
P8231
P8232
P8233
P8234
P8235
P8236
P8237
P8238
P8239
P8382
P8329
P8330
P8331
P8332
P8333
P8334
P8335
P8336
P8337
P8338
P8339
P8482
P8429
P8430
P8431
P8432
P8433
P8434
P8435
P8436
P8437
P8438
P8439
P8583
P8584
P8529
P8530
P8531
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P8534
P8535
P8536
P8537
P8538
P8539
P8685
P8629
ANUM29
ANUM29
ANUM29
ANUM29
ANUM30
ANUM30
ANUM30
ANUM30
ANUM30
ANUM30
ANUM30
ANUM30
ANUM30
ANUM30
ANUM30
ANUM30
ANUM30
ANUM31
ANUM31
ANUM31
ANUM31
ANUM31
ANUM31
ANUM31
ANUM31
ANUM31
ANUM31
ANUM31
ANUM31
ANUM32
ANUM32
ANUM32
ANUM32
ANUM32
ANUM32
ANUM32
ANUM32
ANUM32
ANUM32
ANUM32
ANUM32
ANUM33
ANUM33
ANUM33
ANUM33
ANUM33
ANUM33
ANUM33
ANUM33
ANUM33
ANUM33
ANUM33
ANUM33
ANUM33
ANUM34
ANUM34
ALAMBDA
ALPHAC
ALPHAR
ALPHAI
ALPHAV
VDS
AIPK
APIS
APIO
AP2
AP3
VPKO
VPKS
ALAMBDA
ALPHAC
ALPHAR
ALPHA1
ANUM30
AIPK
APIS
APIO
AP2
AP3
VPKO
VPKS
ALAMBDA
ALPHAC
ALPHAR
ALPHA1
ANUM30
AIPK
APIS
APIO
AP2
AP3
VPKO
VPKS
ALAMBDA
ALPHAC
ALPHAR
ALPHAI
ANUM31
ANUM32
AIPK
APIS
APIO
AP2
AP3
VPKO
VPKS
ALAMBDA
ALPHAC
ALPHAR
ALPHA 1
ANUM33
AIPK
322
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
P8630
P8631
P8632
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P8634
P8635
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P8785
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P8977
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ANUM34
ANUM34
ANUM34
ANUM34
ANUM34
ANUM34
ANUM34
ANUM34
ANUM34
ANUM34
ANUM35
ANUM35
ANUM35
ANUM35
ANUM35
ANUM35
ANUM35
ANUM35
ANUM35
ANUM35
ANUM35
ANUM35
ANUM36
ANUM36
ANUM36
ANUM36
ANUM36
ANUM36
ANUM36
ANUM36
ANUM36
ANUM36
ANUM36
ANUM36
ANUM36
ANUM37
ANUM37
ANUM37
ANUM37
ANUM37
ANUM37
ANUM37
ANUM37
ANUM37
ANUM37
ANUM37
ANUM37
ANUM38
ANUM38
ANUM38
ANUM38
ANUM38
ANUM38
ANUM38
ANUM38
ANUM38
APIS
APIO
AP2
AP3
VPKO
VPKS
ALAMBDA
ALPHAC
ALPHAR
ALPHA I
ANUM33
AIPK
APIS
APIO
AP2
AP3
VPKO
VPKS
ALAMBDA
ALPHAC
ALPHAR
ALPHA I
ANUM34
ANUM35
AIPK
APIS
APIO
AP2
AP3
VPKO
VPKS
ALAMBDA
ALPHAC
ALPHAR
ALPHA 1
ANUM26
AIPK
APIS
APIO
AP2
AP3
VPKO
VPKS
ALAMBDA
ALPHAC
ALPHAR
ALPHA 1
ANUM37
ANUM29
ANUM36
AIPK
APIS
APIO
AP2
AP3
VPKO
323
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
P9035
P9036
P9037
P9038
P9039
P9190
P9129
P9130
P9131
P9132
P9133
P9134
P9135
P9136
P9137
P9138
P9139
P9190
P9129
P9130
P9131
P9132
P9133
P9134
P9135
P9136
P9137
P9138
P9139
P9381
P9388
P9329
P9330
P9331
P9332
P9333
P9334
P9335
P9336
P9337
P9338
P9339
P9464
P9429
P9430
P9431
P9432
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P9434
P9435
P9436
P9437
P9438
P9439
P9666
P9629
ANUM38
ANUM38
ANUM38
ANUM38
ANUM38
AIDS
AIDS
AIDS
AIDS
AIDS
AIDS
AIDS
AIDS
AIDS
AIDS
AIDS
AIDS
AIDS
AIDS
AIDS
AIDS
AIDS
AIDS
AIDS
AIDS
AIDS
AIDS
AIDS
AIDS
ANUM39
ANUM39
ANUM39
ANUM39
ANUM39
ANUM39
ANUM39
ANUM39
ANUM39
ANUM39
ANUM39
ANUM39
ANUM39
ANUM40
ANUM40
ANUM40
ANUM40
ANUM40
ANUM40
ANUM40
ANUM40
ANUM40
ANUM40
ANUM40
ANUM40
ANUM41
ANUM41
VPKS
ALAMBDA
ALPHAC
ALPHAR
ALPHAI
ANUM38
AIPK
APIS
APIO
AP2
AP3
VPKO
VPKS
ALAMBDA
ALPHAC
ALPHAR
ALPHA 1
ANUM38
AIPK
APIS
APIO
AP2
AP3
VPKO
VPKS
ALAMBDA
ALPHAC
ALPHAR
ALPHA 1
ANUM29
ANUM36
AIPK
APIS
APIO
AP2
AP3
VPKO
VPKS
ALAMBDA
ALPHAC
ALPHAR
ALPHA1
ANUM18
AIPK
APIS
APIO
AP2
AP3
VPKO
VPKS
ALAMBDA
ALPHAC
ALPHAR
ALPHA 1
ANUMI9
AIPK
324
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
P9630
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P9871
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P9839
P9971
P9929
P9930
P9931
P9932
P9933
P9934
P9935
P9936
P9937
P9938
P9939
PDW98
PDW99
PDW29
PDW30
PDW31
PDW32
PDW33
PDW34
PDW35
PDW36
PDW37
PDW38
PDW39
PDXDW
PDX29
PDX30
PDX3I
PDX32
PDX33
PDX34
PDX35
PDX36
ANUM41
ANUM4I
ANUM41
ANUM41
ANUM41
ANUM41
ANUM41
ANUM41
ANUM41
ANUM41
ANUM42
ANUM42
ANUM42
ANUM42
ANUM42
ANUM42
ANUM42
ANUM42
ANUM42
ANUM42
ANUM42
ANUM42
ANUM43
ANUM43
ANUM43
ANUM43
ANUM43
ANUM43
ANUM43
ANUM43
ANUM43
ANUM43
ANUM43
ANUM43
ANUM44
ANUM44
ANUM44
ANUM44
ANUM44
ANUM44
ANUM44
ANUM44
ANUM44
ANUM44
ANUM44
ANUM44
ANUM44
ANUM45
ANUM45
ANUM45
ANUM45
ANUM45
ANUM45
ANUM45
ANUM45
ANUM45
APIS
APIO
AP2
AP3
VPKO
VPKS
ALAMBDA
ALPHAC
ALPHAR
ALPHAI
APSI
AIPK
APIS
APIO
AP2
AP3
VPKO
VPKS
ALAMBDA
ALPHAC
ALPHAR
ALPHA1
APSI
AIPK
APIS
APIO
AP2
AP3
VPKO
VPKS
ALAMBDA
ALPHAC
ALPHAR
ALPHA 1
ANUM42
ANUM43
AIPK
APIS
APIO
AP2
AP3
VPKO
VPKS
ALAMBDA
ALPHAC
ALPHAR
ALPHA1
ANUM44
AIPK
APIS
APIO
AP2
AP3
VPKO
VPKS
ALAMBDA
325
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
PDX37
PDX38
PDX39
PDY63
PDY94
PDY96
PDY29
PDY30
PDY31
PDY32
PDY33
PDY34
PDY35
PDY36
PDY37
PDY38
PDY39
PDZDY
PDZDX
PDZ29
PDZ30
PDZ3I
PDZ32
PDZ33
PDZ34
PDZ35
PDZ36
PDZ37
PDZ38
PDZ39
PEA93
PEADZ
PEA29
PEA30
PEA31
PEA32
PEA33
PEA34
PEA3 5
PEA36
PEA3 7
PEA3 8
PEA39
PEAEA
PEA29
PEA30
PEA31
PEA32
PEA33
PEA34
PEA3 5
PEA36
PEA37
PEA38
PEA39
ANUM45
ALPHAC
ANUM45
ALPHAR
ALPHA I
ANUM45
API
ANUM46
ANUM46
ANUM40
ANUM41
ANUM46
ANUM46
AIPK
ANUM46
APIS
APIO
ANUM46
ANUM46
AP2
ANUM46
AP3
ANUM46
VPKO
ANUM46
VPKS
ALAMBDA
ANUM46
ANUM46
ALPHAC
ALPHAR
ANUM46
ALPHA 1
ANUM46
ANUM47
ANUM46
ANUM47
ANUM45
ANUM47
AIPK
ANUM47
APIS
ANUM47
APIO
ANUM47
AP2
ANUM47
AP3
ANUM47
VPKO
ANUM47
VPKS
ANUM47
ALAMBDA
ANUM47
ALPHAC
ANUM47
ALPHAR
ANUM47
ALPHA 1
GM
ANUM39
GM
ANUM47
GM
AIPK
GM
APIS
GM
APIO
GM
AP2
GM
AP3
GM
VPKO
GM
VPKS
GM
ALAMBDA
GM
ALPHAC
GM
ALPHAR
GM
ALPHA 1
GM
GM
GM
AIPK
GM
APIS
GM
APIO
GM
AP2
GM
AP3
GM
VPKO
GM
VPKS
GM
ALAMBDA
GM
ALPHAC
GM
ALPHAR
GM
ALPHA 1
326
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
TEST CASE
-0.7,0.6,0.,0.06,0..0.06,0.,0.06
1..1.
1..1..1..1.
2 .1..1..0.5.0..!.
0,1..-0.7,0.001,0.,0.
0,1.,-0.6,0.010799,0.,0.
0,1.,-0.5,0.027427,0.,0.
0,1 „-0.4,0.042035,0.,0.
0,1 ,,-0.3,0.050567,0.,0.
0,1.,-02,0.05443,0.,0.
0,1.,-0.1,0.0549,0.,0.
0,1.,0.0,0.05559,0.,0.
0,1.,0.1,0.05775,0.,0.
0,1., 02,0.06072,0.,0.
0,1.,0.3,0.05316,0.,0.
0,1.,0.4,0.05142,0.,0.
0,1.,0.5,0.04962,0.,0.
0,1 ,,0.6,0.04743,0.,0.
-2 3.4. 5. 6. 7.
1 1 0.012 0.
2
3
4
5
1 2.061 0.
1 3.1891 0.
1 0.95 0.
1 5.0 0.
6 1 -.10 0.
7 1 0.1 0.
8 1 02161222 0.
9 1 3.0 0.
10 I 0.6 0.
11 1 1.74 0.
0 7 2.3.
-2 50 IE-10 .01
0 6 2.3.
-2 50 IE-10 0.01
0 4 2.3.
-2 75 IE-8 025
0 5 2. 3.
-2 75 IE-8.25
-2-2 3 4
327
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
I TEST CASE
PAGE NUMBER 1
SOO
0
MAXIMUM ITERATIONS= 50
ITERATION STOPPING TOLERANCE= 0.100000E-09
MAXIMUM PER-UNIT PARAMETER CHANGE PER ITERATION= 0 .100000E+00
THE I ESTIMATED PARAMETERS HAVE INDEX-----
2
0
OCURRENT PARAMETER VALUES ARE----PARAMETER( I)= 0.120000E-0I
PARAMETER( 2)= 0.455000E+0!
PARAMETER( 3)= 0.318910E+01
PARAMETER( 4)= 0.I00000E+00
PARAMETER( 5)= 0.I00000E+00
PARAMETER( 6)= -0.100000E+00
PARAMETER( 7)= -0.140000E+00
PARAMETER( 8)= 0216122E+00
PARAMETER( 9)= 0.300000E+01
PARAMETER(10)= 0.200000E-01
PARAMETER( 11)= 0.174000E+01
PARAMETER( 12)= 0.000000E+00
PARAMETER( 13)= 0.000000E+00
PARAMETER(14)= O.OOOOOOE+OO
PARAMETER( 15)= 0.000000E+00
PARAMETER(16)= 0.000000E+00
PARAMETER(17)= 0.000000E+00
PARAMETERS 8)= O.OOOOOOE+OO
PARAMETER(19)= 0.000000E+00
PARAMETER(20)= 0.000000E+00
0
0
0 ITERATION INCREMENT
DEGREES
NUMBER CHANGES
0
6 0.60000E+01
1
4 0.52500E+01
INCREMENT
RATIO
0.I4666E-01
0.13248E-01
ERROR
ERROR
(1)
(2)
TOTAL
O.OOOOOE+OO 0.14666E-01
O.OOOOOE+OO 0.I3248E-01
ERROR
ERROR
0.95467E-02
0.91614E-02
PREDICTED
FREEDOM
27
27
328
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
2
4 0.45938E+01
1 TEST CASE
0.11999E-01
O.OOOOOE+OO
0.11999E-01 0.89592E-02
PAGE NUMBER 2
0.10983 E-01
0.10152E-01
0.96180E-02
0.93719E-02
0.92909E-02
0.92874E-02
0.92864E-02
0.9286 IE-02
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
0.10983E 01 0.89250E-02
0.10152E- 01 0.90163 E-02
0.96180E- 02 0.91529E-02
0.93719E-'02 0.92458E-02
0.92909E 02 0.92835E-02
0.92874E 02 0.92853E-02
0.92864E 02 0.92858E-02
0.9286 IE-02 0.92860E-02
PAGE NUMBER 3
27
27
27
27
27
27
27
27
0.9286 IE-02
0.92860E-02
0.92860E-02
0.92860E-02
0.92860E-02
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
0.92861 E-02 0.92860E-02
0.92860E-02 0.92860E-02
0.92860E-02 0.92860E-02
0.92860E-02 0.92860E-02
0.92860E-02 0.92860E-02
PAGE NUMBER 4
27
27
27
SOO
3
4
0.34453 E+01
0.25840E+01
3
0.19380E+01
6
0.96899E+00
7
O.OOOOOE+OO
8
O.OOOOOE+OO
9
O.OOOOOE+OO
10
0 O.OOOOOE+OO
1 TEST CASE
SOO
11
0 O.OOOOOE+OO
12
0 O.OOOOOE+OO
13
0 O.OOOOOE+OO
14
0 O.OOOOOE+OO
15
0 O.OOOOOE+OO
1 TEST CASE
SOO
0
OCURRENT PARAMETER VALUES ARE—
PARAMETERS 1)= 0.120000E-01
PARAMETERS 2)= 0.236502E+01
PARAMETERS 3)= 0.318910E+01
PARAMETER( 4)= 0.1 OOOOOE+OO
PARAMETERS 5)= 0.100000E+00
PARAMETER( 6)= -0.1 OOOOOE+OO
PARAMETER( 7)= -0.140000E+00
PARAMETER( 8)= 0.216122E+00
PARAMETER( 9)= 0.300000E+01
PARAMETER(10)= 0.200000E-01
PARAMETER( 11 )= 0.174000E+01
PARAMETERS 12)= O.OOOOOOE+OO
PARAMETER( 13)= O.OOOOOOE+OO
PARAMETER(14)= O.OOOOOOE+OO
PARAMETER(15)= O.OOOOOOE+OO
PARAMETER(16)= O.OOOOOOE+OO
PARAMETERS 7>= O.OOOOOOE+OO
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
2?
27
PARAMETER 18)= O.OOOOOOE+OO
PARAMETER! 19)= O.OOOOOOE+OO
PARAMETER(20)= O.OOOOOOE+OO
0
0
0 ITERATION INCREMENT INCREMENT
ERROR
ERROR
ERROR
PREDICTED
DEGREES
NUMBER CHANGES
RATIO
(I)
(2)
TOTAL
ERROR
FREEDOM
16
0 O.OOOOOE+OO 0.92860E-02 O.OOOOOE+OO 0.92860E-02 0.92860E-02
27
1 TEST CASE
PAGE NUMBER 5
SOO
0
0
0
STANDARD ERRORS AND COVARIANCES----0
PARAMETER( 1) IS O.I2000000E-OI
PARAMETER( 2) IS 0.23644974E+01 WITH STANDARD ERROR EQUAL TO 0.52239490E+00
PARAMETER! 3) IS 0.31891000E+0!
PARAMETER! 4) IS 0.10000000E+00
PARAMETER! 5) IS 0.10000000E+00
PARAMETER! 6) IS-0.10000000E+00
PARAMETER! 7) IS-0.14000000E+00
PARAMETER! 8) IS 0.21612220E+00
PARAMETER! 9) IS 0.30000000E+01
PARAMETER! 10) IS 0.20000000E-01
PARAMETER! 11) IS 0.17400000E+01
PARAMETER! 12) IS O.OOOOOOOOE+OO
PARAMETER! 13) IS O.OOOOOOOOE+OO
PARAMETER! 14) IS O.OOOOOOOOE+OO
PARAMETER! 15) IS O.OOOOOOOOE+OO
PARAMETER! 16) IS O.OOOOOOOOE+OO
PARAMETER! 17) IS O.OOOOOOOOE+OO
PARAMETER! 18) IS O.OOOOOOOOE+OO
PARAMETER! 19) IS O.OOOOOOOOE+OO
PARAMETER(20) IS O.OOOOOOOOE+OO
0 ERROR 1 IS
0.0093, ERROR2 IS
0.0000, TOTAL ERROR IS
0.0093 WITH 27 DEGREES OF
FREEDOM.
0 NORMALIZED ERROR I IS 0.25754362E-01, NORMALIZED ERROR2 IS O.OOOOOOOOE+OO, WHILE
NORMALIZED TOTAL ERROR IS 0.18545261E-01
0
0
NORMALIZED COVARIANCE MATRIX BY ROW IS---0PARAMETER! 2)
0.10000E+01
1 TEST CASE
DATASET 1
1 TEST CASE
DATASET 1
0.000
0.010
0.020
0.030
0.040
0.050
0.060
0.070
0.080
0.090
0.100
XO *
+ -0.7000
*
*
*
330
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
*
*
*
*
o*
-0.5700
*
*
*
*
* o
*
*
♦
*
+ -0.4400
*
*
*
♦
*
*
*
*
-0.3100
*
*
*
«
*
*
*
*
*
o
4-0.1800
*
♦
*
♦
*
*
*
*
*
*
o
-0.0500
«
«
..+.... 0...+.........+.........+........ +.........+ Y
331
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
*
*
*
*
0.0800
*
*
*
*
*
*
*
*
o
0.2100
*
*
*
*
*
*
*
*
+ 0.3400
*
*
#
*
*
*
*
*
*
o
o
0.4700
*
*
*
*
♦
*
*
*
*
o
o
+ 0.6000
XMIN = -0.700000
YMIN = 0.000000
1 TEST CASE
SOO
XMAX = 0.600000
YMAX = 0.100000
PAGE NUMBER 6
332
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
0
MAXIMUM ITERAT10NS= 50
ITERATION STOPPING TOLERANCE= 0.100000E-09
MAXIMUM PER-UNIT PARAMETER CHANGE PER ITERATION= 0.100000E+00
THE I ESTIMATED PARAMETERS HAVE INDEX-----
1
0
OCURRENT PARAMETER VALUES ARE----PARAMETER( I)= O.I20000E-0!
PARAMETER! 2)= 0236450E+01
PARAMETER! 3)= 0.318910E+01
PARAMETER! 4)= 0.1 OOOOOE+OO
PARAMETER! 5)= 0.100000E+00
PARAMETER! 6)= -0.1 OOOOOE+OO
PARAMETER! 7)= -0.140000E+00
PARAMETER! 8)= 0216122E+00
PARAMETER! 9)= 0.300000E+01
PARAMETER! 10)= 0.200000E-01
PARAMETER! 11)= 0.174000E+01
PARAMETER! 12)= O.OOOOOOE+OO
PARAMETER! 13)= O.OOOOOOE+OO
PARAMETER! 14)= O.OOOOOOE+OO
PARAMETER! 15)= O.OOOOOOE+OO
PARAMETER! 16)= O.OOOOOOE+OO
PARAMETER! 17)= O.OOOOOOE+OO
PARAMETER! 18)= O.OOOOOOE+OO
PARAMETER! 19)= O.OOOOOOE+OO
PARAMETER!20)= O.OOOOOOE+OO
0
0
ERROR
ERROR
ERROR
PREDICTED
0 ITERATION INCREMENT INCREMENT
DEGREES
NUMBER CHANGES
TOTAL
RATIO
ERROR
FREEDOM
(1)
(2)
0
60.60000E+01
0.92860E-02 O.OOOOOE+OO 0.92860E-02 0.59075E-02
27
0.83897E-02 O.OOOOOE+OO 0.83897E-02 0.59075E-02
1
30.45000E+01
27
3 0.33750E+01 0.75691 E-02 O.OOOOOE+OO 0.75691 E-02 0.59075E-02
27
1 TEST CASE
PAGE NUMBER 7
333
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
SOO
3
2
4
2
5
0
6
0
7
0
1 TEST CASE
SOO
0.16875E+O1
0.84375E+00
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
0.68963E-02
0.62973E-02
0.59891 E-02
0.59075E-02
0.59075E-02
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
0.68963 E-02 0.59075E-02
0.62973 E-02 0.59075E-02
0.59891 E-02 0.59075E-02
0.59075E-02 0.59075E-02
0.59075E-02 0.59075E-02
PAGE NUMBER 8
27
27
27
27
27
0
OCURRENT PARAMETER VALUES ARE—
PARAMETERS 1)= 0.188557E-01
PARAMETER( 2)= 0.236450E+01
PARAMETER( 3)= 0.318910E+01
PARAMETER( 4)= 0.1 OOOOOE+OO
PARAMETER( 5)= 0.1 OOOOOE+OO
PARAMETER( 6)= -0.1 OOOOOE+OO
PARAMETER( Tf= -0.140000E+00
PARAMETER( 8)= 0.216122E+00
PARAMETER( 9)= 0.300000E+01
PARAMETER(10)= 0.200000E-01
PARAMETER( 11)= 0.174000E+01
PARAMETER( 12)= O.OOOOOOE+OO
PARAMETER(13)= O.OOOOOOE+OO
PARAMETER(14)= O.OOOOOOE+OO
PARAMETER(15)= O.OOOOOOE+OO
PARAMETER(16)= O.OOOOOOE+OO
PARAMETER(17)= O.OOOOOOE+OO
PARAMETER(18)= O.OOOOOOE+OO
PARAMETER(19)= O.OOOOOOE+OO
PARAMETER(20)= O.OOOOOOE+OO
0
0
0 ITERATION INCREMENT
INCREMENT
ERROR
ERROR
ERROR
DEGREES
NUMBER CHANGES
RATIO
(1)
(2)
TOTAL
ERROR
8
0 O.OOOOOE+OO 0.59075E-02 0.00000E+00 0.59075E-02 0.59075E-02
PREDICTED
FREEDOM
27
334
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
1 TEST CASE
SOO
PAGE NUMBER 9
0
0
0
STANDARD ERRORS AND COVARIANCES-----
0
PARAMETER! 1) IS 0.I8855724E-01 WITH STANDARD ERROR EQUAL TO 0.17446480E-02
PARAMETER! 2) IS 0.23644974E+01
PARAMETER! 3) IS 0.3189I000E+01
PARAMETER! 4) IS 0 .10000000E+00
PARAMETER! 5) IS 0 .10000000E+00
PARAMETER! 6) IS-0.10000000E+00
PARAMETER! 7) IS-0.I4000000E+00
PARAMETER! 8) IS 0.21612220E+00
PARAMETER! 9) IS 0.30000000E+01
PARAMETER! 10) IS 0J20000000E-01
PARAMETER! 11) IS 0.17400000E+01
PARAMETER! 12) IS 0.00000000E+00
PARAMETER! 13) IS 0.00000000E+00
PARAMETER! 14) IS O.OOOOOOOOE+OO
PARAMETER! 15) IS O.OOOOOOOOE+OO
PARAMETER! 16) IS 0.00000000E+00
PARAMETER! 17) IS O.OOOOOOOOE+OO
PARAMETER! 18) IS 0.00000000E+00
PARAMETER! 19) IS O.OOOOOOOOE+OO
PARAMETER(20) IS O.OOOOOOOOE+OO
0 ERROR 1 IS
0.0059, ERROR2 IS
0.0000, TOTAL ERROR IS
0.0059 WITH 27 DEGREES OF
FREEDOM.
0 NORMALIZED ERROR 1 IS 020541729E-01, NORMALIZED ERROR2 IS 0.00000000E+00, WHILE
NORMALIZED TOTAL ERROR IS 0.14791736E-01
0
0
NORMALIZED COVARIANCE MATRIX BY ROW IS----0PARAMETER! 1)
0.10000E+01
1 TEST CASE
DATASET I
1 TEST CASE
DATASET 1
0.000
0.010
XO
*
+ -0.7000
+
+ -0.5700
0.020
0.030
0.040
0.050
0.060
0.070
0.080
0.090
0.100
*
*
*
*
*
*
*
o
*
*
*
*
*
*
335
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
o
*
+
+ -0.4400
*
o *
*
*
+
-0.3100
*
*
o
o
+
+ -0.1800
*
*
*
*
*
*
*
*
*
*
o
-0.0500
*
*
*
+ ..
...+
.+.........+ Y
0 ...+ .
*
♦
*
*
*
+ 0.0800
*
* o
336
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
o
+
+ 0.2100
*
*
*
*
*
o
*
*
0.3400
*
*
*
*
*
*
*
*
+
o
*
+ 0.4700
*
*
*
*
*
*
*
*
*
+ *
o
o
+ 0.6000
XMIN = -0.700000 XMAX = 0.600000
YMIN = 0.000000 YMAX = 0.100000
PAGE NUMBER 10
1 TEST CASE
SOO
0 MAXIMUM ITERATIONS= 75
ITERATION STOPPING TOLERANCE= 0.1OOOOOE+OO
MAXIMUM PER-UNIT PARAMETER CHANGE PER ITERATION3 0.250000E+00
THE 1 ESTIMATED PARAMETERS HAVE INDEX---4
0
0CURRENT PARAMETER VALUES ARE----PARAMETER( 1)= 0.188557E-01
PARAMETER( 2)= 0236450E+01
PARAMETER( 3)= 0.318910E+OI
337
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
PARAMETER( 4)= 0.1 OOOOOE+OO
PARAMETER* 5)= 0.1OOOOOE+OO
PARAMETER* 6)= -0.100000E+00
PARAMETER* 7)= -0.140000E+00
PARAMETER* 8)= 0.216122E+00
PARAMETER* 9)= 0.300000E+01
PARAMETER* 10)= 0.200000E-01
PARAMETER* 11)= 0 .174000E+01
PARAMETER* 12)= O.OOOOOOE+OO
PARAMETER* 13)= O.OOOOOOE+OO
PARAMETER* 14)= O.OOOOOOE+OO
PARAMETER* 15)= O.OOOOOOE+OO
PARAMETER* 16)= O.OOOOOOE+OO
PARAMETER* 17)= O.OOOOOOE+OO
PARAMETER* 18)= O.OOOOOOE+OO
PARAMETER* 19)= O.OOOOOOE+OO
PARAMETER(20)= O.OOOOOOF+OO
0
0
0 ITERATION INCREMENT
INCREMENT
ERROR
ERROR
ERROR
PREDICTED
DEGREES
NUMBER CHANGES
RATIO
(I)
(2)
TOTAL
ERROR
FREEDOM
0
8 0.24000E+02 0.59075E-02
O.OOOOOE+OO 0.59075E-02 0.58333E-02
27
1
8 0.24000E+02 0.59018E-02 O.OOOOOE+OO 0.59018E-02 0.58333E-02
27
1 TEST CASE
PAGE NUMBER 11
SOO
0
OCURRENT PARAMETER VALUES ARE----PARAMETER* 1)= 0.188557E-01
PARAMETER* 2)= 0.236450E+01
PARAMETER* 3)= 0.318910E+01
PARAMETER* 4)= 0.793120E-01
PARAMETER* 5)= 0.1 OOOOOE+OO
338
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
PARAMETER 6)= -0.1OOOOOE+OO
PARAMETER! 7)= -0.140000E+00
PARAMETER( 8)= 0J216122E+00
PARAMETER( 9)= 0.300000E+01
PARAMETERS 0)= 0.200000E-01
PARAMETER( 11)= 0 .174000E+01
PARAMETER(12)= 0.000000E+00
PARAMETERS 3)= O.OOOOOOE+OO
PARAMETER( 14)= O.OOOOOOE+OO
PARAMETERS 5)= O.OOOOOOE+OO
PARAMETERS 6)= O.OOOOOOE+OO
PARAMETERS 7)= O.OOOOOOE+OO
PARAMETERS 8)= O.OOOOOOE+OO
PARAMETERS 9)= O.OOOOOOE+OO
PARAMETER(20)= O.OOOOOOE+OO
0
0
0 ITERATION INCREMENT
INCREMENT
ERROR
ERROR
ERROR PREDICTED
DEGREES
NUMBER CHANGES
RATIO '
(1)
(2)
TOTAL
ERROR
FREEDOM
2
6 0.23250E+02 0.59018E-02 0.00000E+00 0.59018E-02 0.58410E-02
27
1 TEST CASE
PAGE NUMBER 12
SOO
0
0
0
STANDARD ERRORS AND COVARIANCES----
0
PARAMETER( 1) IS 0.I8855724E-01
PARAMETER! 2) IS 0.23644974E+0I
PARAMETER! 3) IS 0.31891000E+01
PARAMETER! 4) IS 0.60001802E-01 WITH STANDARD ERROR EQUAL TO 0.88748491E+00
PARAMETER! 5) IS 0.10000000E+00
PARAMETER! 6) IS-0.10000000E+00
PARAMETER! 7) IS-0.14000000E+00
PARAMETER! 8) IS 0J21612220E+00
PARAMETER! 9) IS 0.30000000E+01
PARAMETER! 10) IS 0J20000000E-01
PARAMETER! 11) IS 0.17400000E+01
PARAMETER! 12) IS O.OOOOOOOOE+OO
PARAMETER! 13) IS O.OOOOOOOOE+OO
PARAMETER!14) IS O.OOOOOOOOE+OO
339
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
PARAMETER 15) IS O.OOOOOOOOE+OO
PARAMETER^ 16) IS O.OOOOOOOOE+OO
PARAMETER( 17) IS O.OOOOOOOOE+OO
PARAMETER( 18) IS O.OOOOOOOOE+OO
PARAMETER( 19) IS O.OOOOOOOOE+OO
PARAMETER(20) IS O.OOOOOOOOE+OO
0 ERROR 1 IS
0.0059, ERROR2 IS
0.0000, TOTAL ERROR IS
0.0059 WITH 27 DEGREES OF
FREEDOM.
0 NORMALIZED ERROR I IS 0.20531895E-01, NORMALIZED ERROR2 IS 0.00000000E+00, WHILE
NORMALIZED TOTAL ERROR IS 0.14784654E-01
0
0
NORMALIZED COVARIANCE MATRIX BY ROW IS----0PARAMETER( 4)
0.10000E+01
1 TEST CASE
DATASET 1
I TEST CASE
DATASET 1
0.000
0.010
XO
*
+ -0.7000
+
+ -0.5700
0.020
0.030
0.040
0.050
0.060
0.070
0.080
0.090
0.100
*
*
*
«
*
*
*
o
*
*
*
*
*
*
«
o *
*
*
*
*
*
+ -0.4400
*
*
o *
*
*
*
*
*
*
+
*
-0.3100
O
*
*
340
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
*
*
o
+
+ -0.1800
*
*
*
*
*
*
*
«
*
o
+
-0.0500
*
*
*
+ 0...+
+.......+....... +....... + Y
*
*
+
0.0800
♦
*
*
*
o
+
0.2100
*
*
*
*
*
*
+
+ 0.3400
o
*
*
*
341
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
*
o
*
«
*
+
+ 0.4700
*
*
o
*
*
*
*
*
*
+
*
o
+ 0.6000
XMIN = -0.700000
XMAX = 0.600000
YMIN = 0.000000
YMAX = 0.100000
PAGE NUMBER 13
1 TEST CASE
S00
0 MAXIMUM ITERATIONS= 75
ITERATION STOPPING TOLERANCE= 0 .1OOOOOE-08
MAXIMUM PER-UNIT PARAMETER CHANGE PER ITERATION 0.100000E+00
THE 1 ESTIMATED PARAMETERS HAVE INDEX----7
0
0CURRENT PARAMETER VALUES ARE---PARAMETER( 1)= 0.188557E-01
PARAMETER( 2)= 0.236450E+01
PARAMETER! 3)= 0.318910E+0I
PARAMETER! 4)= 0.600018E-01
PARAMETER! 5)= 0.100000E+00
PARAMETER! 6)= -0.100000E+00
PARAMETER! 7)= -0.I40000E+00
PARAMETER! 8)= 0216122E+00
PARAMETER! 9)= 0.300000E+01
PARAMETER! 10)= 0.200000E-01
PARAMETER! 11)= 0.I74000E+O1
PARAMETER(12)= 0.000000E+00
PARAMETER(13)= 0.000000E+00
342
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
PARAMETER! 14)= O.OOOOOOE+OO
PARAMETER! 15)= O.OOOOOOE+OO
PARAMETER! 16)= O.OOOOOOE+OO
PARAMETER! 17)= 0.000000E+00
PARAMETER! 18)= O.OOOOOOE+OO
PARAMETER! 19)= O.OOOOOOE+OO
PARAMETER!20)= O.OOOOOOE+OO
0
0
0 ITERATION INCREMENT
DEGREES
NUMBER CHANGES
0
8 0.75000E+01
1
4 0.11250E+02
2
3 0.84375E+01
I TEST CASE
S00
3
6 0.81738E+01
4
4 0.12261E+02
5
3 0.91956E+01
6
6 0.89082E+01
7
4 0 .13362E+02
8
3 0.10022E+02
9
7 0.98651E+01
4 0.14798E+02
10
TEST CASE
SOO
11
3 0.11098E+02
4 0.16647E+02
12
3 0.12486E+02
13
14
9 0.12437E+02
4 0.18655E+02
15
16
3 0.13991E+02
17
4 0.20987E+02
3 0.15740E+02
18
TEST CASE
SOO
4 0.23610E+02
19
3 0.17708E+02
20
4 0.26562E+02
21
22
3 0.19921 E+02
4 0.29882E+02
23
4 0.26147E+02
24
25
6 0.25330E+02
4 0.37994E+02
26
TEST CASE
SOO
27
3 0.28496E+02
INCREMENT
ERROR
ERROR
ERROR
PREDICTED
TOTAL
ERROR
FREEDOM
RATIO
(I)
(2)
27
0.58970E-02 O.OOOOOE+OO 0.58970E-02 0.40962E-02
27
0.54889E-02 O.OOOOOE+OO 0.54889E-02 0.39463 E-02
27
0.52436E-02 O.OOOOOE+OO 0.52436E-02 0.38570E-02
PAGE NUMBER 14
0.49596E-02
0.47059E-02
0.45524E-02
0.43728E-02
0.42106E-02
0.41117E-02
0.39949E-02
0.38897E-02
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
0.49596E-02 0.37541 E-02
0.47059E-02 0.36626E-02
0.45524E-02 0.36072E-02
0.43728E-02 0.35426E-02
0.42106E-02 0.34841 E-02
0.41117E-02 0.34484E-02
0.39949E-02 0.34062E-02
0.38897E-02 0.33681 E-02
PAGE NUMBER 15
27
27
27
27
27
27
27
27
0.38250E-02
0.37477E-02
0.36997E-02
0.364I7E-02
0.35888E-02
0.35557E-02
0.35153E-02
0.34898E-02
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
0.38250E-02 0.33446E-02
0.37477E-02 0.33165E-02
0.36997E-02 0.32990E-02
0.36417E-02 0.32778E-02
0.35888E-02 0.32584E-02
0.35557E-02 0.32462E-02
0.35153 E-02 0.32313E-02
0.34898E-02 0.32219E-02
PAGE NUMBER 16
27
27
27
27
27
27
27
27
0.34584E-02
0.34385E-02
0.34138E-02
0.33980E-02
0.33782E-02
0.33655E-02
0.33517E-02
0.33381E-02
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
0.34584E-02 0.32103E-02
0.34385E-02 0.32030E-02
0.34138E-02 0.31938E-02
0.33980E-02 0.31879E-02
0.33782E-02 0.31806E-02
0.33655E-02 0.31759E-02
0.33517E-02 0.31707E-02
0.33381E-02 0.31656E-02
PAGENUMBER 17
27
27
27
27
27
27
27
27
0.33294E-02 O.OOOOOE+OO 0.33294E-02
0.31623E-02
343
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
27
4
28
4
29
30
6
31
4
32
4
33
6
34
4
:ST CASE
0.42744E+02
0.37401 E+02
0.36232E+02
0.54348E+02
0.47555E+02
0.46068E+02
0.69103E+02
0.33182E-02
0.33109E-02
0.33029E-02
0.32949E-02
0.32896E-02
0.32838E-02
0.32780E-02
O.OOOOOE+OO
0.00000E+00
0.00000E+00
O.OOOOOE+OO
O.OOOOOE+OO
0.00000E+00
O.OOOOOE+OO
0.33182E-02 0.31581 E-02
0.33109E-02 0.31554E-02
0.33029E-02 0.31524E-02
0.32949E-02 0.3I494E-02
0.32896E-02 0.31474E-02
0.32838E-02 0.31453E-02
0.32780E-02 0.31431 E-02
PAGE NUMBER 18
27
27
27
27
27
27
27
0.60465E+02
0.58575E+02
0.87863E+02
0.76880E+02
0.74478E+02
0.11172E+03
0.97752E+02
0.94697E+02
0.32741 E-02
0.32698E-02
0.32655E-02
0.32627E-02
0.32594E-02
0.32562E-02
0.32540E-02
0.32516E-02
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
0.32741 E-02 0.31416E-02
0.32698E-02 0.31400E-02
0.32655E-02 0.31384E-02
0.32627E-02 0.31373E-02
0.32594E-02 0.31361 E-02
0.32562E-02 0.31349E-02
0.32540E-02 0.31341 E-02
0.32516E-02 0.31331 E-02
PAGE NUMBER 19
27
27
27
27
27
27
27
27
0.14205E+03
0.12429E+03
0.12235E+03
0.18352E+03
0.16058E+03
0.15807E+03
0.23711E+03
0.20747E+03
0.32492E-02
0.32475E-02
0.32457E-02
0.32438E-02
0.32426E-02
0.32412E-02
0.32398E-02
0.32389E-02
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
0.32492E-02 0.31322E-02
0.32475E-02 0.31316E-02
0.32457E-02 0.31309E-02
0.32438E-02 0.31302E-02
0.32426E-02 0.31297E-02
0.32412E-02 0.31292E-02
0.32398E-02 0.31287E-02
0.32389E-02 0.31283E-02
PAGE NUMBER 20
27
27
27
27
27
27
27
27
0.20585E+03
0.30877E+03
0.27018E+03
0.26912E+03
0.40368E+03
0.35322E+03
0.35253E+03
0.52880E+03
0.32378E-02
0.32367E-02
0.32360E-02
0.32352E-02
0.32344E-02
0.32339E-02
0.32333E-02
0.32327E-02
O.OOOOOE+OO
O.OOOOOE+OO
0.00000E+00
0.00000E+00
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
0.32378E-02 0.31279E-02
0.32367E-02 0.31275E-02
0.32360E-02 0.31273E-02
0.32352E-02 0.31270E-02
0.32344E-02 0.31267E-02
0.32339E-02 0.31265E-02
0.32333E-02 0.31262E-02
0.32327E-02 0.31260E-02
PAGE NUMBER 21
27
27
27
27
27
27
27
27
0.46270E+03
0.69405E+03
0.52054E+03
0.78081E+03
0.68320E+03
0.66185E+03
0.99278E+03
0.86868E+03
0.32323E-02
0.32318E-02
0.32315E-02
0.32311 E-02
0.32308E-02
0.32305E-02
0.32302E-02
0.32300E-02
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
0.32323 E-02 0.31258E-02
0.32318E-02 0.31257E-02
0.32315E-02 0.31256E-02
0.32311 E-02 0.31254E-02
0.32308E-02 0.31253E-02
0.32305E-02 0.31252E-02
0.32302E-02 0.31251 E-02
0.32300E-02 0.31250E-02
PAGE NUMBER 22
27
27
27
27
27
27
27
27
0.85511E+03
0.12827E+04
0.11223E+04
0.11136E+04
0.16703E+04
0.14616E+04
0.14558E+04
0.32298E-02
0.32295E-02
0.32294E-02
0.32292E-02
0.32290E-02
0.32289E-02
0.32287E-02
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
0.32298E-02
0.32295E-02
0.32294E-02
0.32292E-02
0.32290E-02
0.32289E-02
0.32287E-02
CAA
4
35
36
6
37
4
38
4
39
6
40
4
41
4
42
6
:s t CASE
SOO
4
43
44
4
7
45
4
46
47
4
7
48
49
4
4
50
1 TEST CASE
SOO
51
8
4
52
4
53
54
9
4
55
4
56
57
10
4
58
:ST CASE
59
4
4
60
61
3
62
4
4
63
64
6
4
65
66
4
LST CASE
CAA
67
68
69
70
71
72
73
7
4
4
8
4
4
9
0.31249E-02
0.31248E-02
0.31247E-02
0.31247E-02
0.31246E-02
0.31245E-02
0.31245E-02
344
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
27
27
27
27
27
27
27
74
4 0.21838E+04 0.32286E-02 O.OOOOOE+OO 0.32286E-02 0.3I244E-02
I TEST CASE
PAGE NUMBER 23
SOO
75
4
0.19108E+04 0.32285E-02 O.OOOOOE+OO 0.32285E-02 0.31244E-02
76
4
0.28662E+04 0.32284E-02 O.OOOOOE+OO 0.32284E-02 0.3I244E-02
0
OUPDATED PARAMETER VALUES ARE----PARAMETER( 1)= 0.I88557E-0I
PARAMETER( 2)= 0.236450E+01
PARAMETER( 3)= 0.3189I0E+01
PARAMETER( 4)= 0.600018E-01
PARAMETER( 5)= 0.100000E+00
PARAMETER( 6)= -0.100000E+00
PARAMETER( 7)= -0.I36852E-03
PARAMETER( 8)= 0.2I6122E+00
PARAMETER( 9)= 0.300000E+01
PARAMETER( 10)= 0.200000E-01
PARA METE R( 11)= 0.174000E+01
PARAMETERS 2)= O.OOOOOOE+OO
PARAMETER^ 3)= O.OOOOOOE+OO
PARAMETER(14)= O.OOOOOOE+OO
PARAMETER(15)= O.OOOOOOE+OO
PARAMETER( 16)= O.OOOOOOE+OO
PARAMETERS 7)= O.OOOOOOE+OO
PARAMETERS 8)= O.OOOOOOE+OO
PARAMETERS 9)= O.OOOOOOE-t 00
PARAMETER(20)= O.OOOOOOE+OO
1 TEST CASE
1 TEST CASE
0.000
0.010
DATASET 1
DATASET I
0.020
0.030
0.040
0.050
0.060
0.070
0.080
0.090
0.100
XO*
+ -0.7000
*
*
345
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
27
27
27
*
*
*
*
*
+
-0.5700
*
*
*
*
*
*
*
*
♦
*
+
+ -0.4400
*
*
O
«
+
+ -0.3100
*
*
+
-0.1800
*
*
*
*
*
o
*
*
*
-0.0500
*
*
*
346
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
h
-r
■+•.........+......... +..... O...+*.........
..+......... + Y
*
*
*
*
*
+ 0.0800
*
o
*
*
*
*
*
*
*
* o
0.2100
*
♦
*
*
o
*
*
0.3400
*
*
O
*
*
♦
+ 0.4700
*
♦
o
*
*
*
*
*
*
O
+ 0.6000
XMIN = -0.700000
YMIN = 0.000000
1 TEST CASE
XMAX = 0.600000
YMAX = 0.100000
PAGE N U M B ER 24
347
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
0
SOO
MAXIMUM ITERATIONS= 50
ITERATION STOPPING TOLERANCE= 0.1OOOOOE-08
MAXIMUM PER-UNIT PARAMETER CHANGE PER ITERATION= 0 .100000E+00
THE
I ESTIM ATED PARAMETERS HAVE INDEX----5
0
OCURRENT PARAM ETER VALUES ARE----PARAMETER( 1)= 0.188557E-01
PARAMETER( 2)= 0.236450E+01
PARAMETER! 3)= 0.3I89I0E+OI
PARAMETER! 4)= 0.600018E-01
PARAMETER! 5)= 0.100000E+00
PARAMETER! 6)= -O.IOOOOOE+OO
PARAMETER! 7)= -0.136852E-03
PARAMETER! 8)= 0.216122E+00
PARAMETER! 9)= 0.300000E+01
PARAMETER! 10)= 0.200000E-01
PARAMETER! 11)= 0.174000E+01
PARAMETER! 12)= 0.000000E+00
PARAMETER! 13)= O.OOOOOOE+OO
PARAMETER! 14)= O.OOOOOOE+OO
PARAMETER! 15)= O.OOOOOOE+OO
PARAMETER! 16)= 0.000000E+00
PARAMETER! 17)= O.OOOOOOE+OO
PARAMETER! 18)= 0.000000E+00
PARAMETER! 19)= O.OOOOOOE+OO
PARAMETER(20)= 0.000000E+00
0
0
0 ITERATION INCREM ENT
INCREMENT
ERROR
ERROR
DEGREES
NUMBER CHANGES
RATIO
0)
(2 )
TOTAL
0
12 0.38400E+03 0.32283E-02 O.OOOOOE+OO 0.32283E-02
1
5 0.36000E+03 0.32242E-02 0.00000E+00 0.32242E-02
2
4 0.31500E+03 0.32200E-02 0.00000E+00 0.32200E-02
ERROR
PREDICTED
ERROR
FREEDOM
0.24414E-02
27
0.24552E-02
27
0.24695E-02
27
348
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
1 TEST CASE
SOO
3
4
4
5
5
4
6
4
7
5
8
4
9
4
10
4
1 TEST CASE
SOO
11
5
12
4
4
13
14
4
15
4
4
16
4
17
18
4
1 TEST CASE
SOO
19
3
4
20
21
3
22
3
23
3
24
3
2
25
26
2
1 TEST CASE
SOO
27
0
28
0
29
2
30
2
31
4
32
5
33
8
34
5
1 TEST CASE
SOO
35
2
36
4
37
5
38
3
39
14
40
5
41
2
42
4
1 TEST CASE
SOO
43
5
44
3
45
6
46
5
PAGE NUMBER 25
0.27563E+03
0.25840E+03
0.22610E+03
0.I9784E+03
0.I8547E+03
0.16229E+03
0.14200E+03
0.12425E+03
0.32153E-02
0.32101 E-02
0.32047E-02
0.31987E-02
0.31922E-02
0.31856E-02
0.31783E-02
0.31705E-02
0.32153 E-i02 0.24856E-02
0.3210 IE 02 0.25034E-02
0.32047E 02 035218E-02
031987E 02 0.25421 E-02
0.31922E 02 035644E-02
0.31856E 02 035871 E-02
0.31783E 02 0.26118E-02
0.31705E-02 0.26384E-02
PAGE NUMBER 26
27
27
27
27
27
27
27
27
0.11649E+03
0.10193E+03
0.89184E+02
0.78036E+02
0.68282E+02
0.59747E+02
0.52278E+02
0.45743E+02
0.31622E-02 O.OOOOOE+OO 0.31622E 02 0.26669E-02
0.31540E-02 O.OOOOOE+OO 0.31540E 02 0.26951 E-02
0.31452E-02 O.OOOOOE+OO 0.31452E 02 0.27248E-02
0.31362E-02 O.OOOOOE+OO 0.31362E- 02 037557E-02
0.31268E-02 O.OOOOOE+OO 0.31268E 02 0.27874E-02
0.31174E-02 O.OOOOOE+OO 0.31174E- 02 0.28194E-02
0.31079E-02 O.OOOOOE+OO 0.31079E- 02 0.28511 E-02
0.30987E-02 O.OOOOOE+OO 0.30987E- 02 0.28819E-02
PAGE NUMBER 27
27
27
27
27
27
27
27
27
0.34308E+02
0.30019E+02
0.22514E+02
0.16886E+02
0.12664E+02
0.94983E+01
0.47491E+01
0.23746E+01
0.30899E-02 O.OOOOOE+OO 0.30899E- 02 0 39 1 12E-02
0.30804E-02 O.OOOOOE+OO 0.30804E- 02 0.29423E-02
0.30721 E-02 O.OOOOOE+OO 0.3072 IE- 02 0.29691 E-02
0.30642E-02 O.OOOOOE+OO 0.30642E- 02 0.29945E-02
0.30573E-02 O.OOOOOE+OO 0.30573E- 02 0.30161 E-02
0.30522E-02 O.OOOOOE+OO 0.30522E- 02 0.30318E-02
0.30490E-02 O.OOOOOE+OO 0.30490E- 02 0.30412E-02
0.30473E-02 O.OOOOOE+OO 0.30473 E- 02 0.30465E-02
PAGE NUMBER 28
27
27
27
27
27
27
27
27
0.00000E+00
0.00000E+00
0.11873E+01
0.59364E+00
0.89046E+00
0.83481E+00
0.82829E+00
0.14495E+01
0.30471E-02 O.OOOOOE+OO 0.3047 IE- 02 0.30470E-02
0.30471 E-02 O.OOOOOE+OO 0.3047 IE- 02 0.30470E-02
0.30474E-02 O.OOOOOE+OO 0.30474E- 02 0.30462E-02
0.30472E-02 O.OOOOOE+OO 0.30472E- 02 0.30466E-02
0.30474E-02 O.OOOOOE+OO 0.30474E- 02 0.30461 E-02
0.30474E-02 O.OOOOOE+OO 0.30474E- 02 0.30460E-02
0.30475E-02 O.OOOOOE+OO 0.30475E- 02 0.30457E-02
0.30476E-02 O.OOOOOE+OO 0.30476E- 02 0.30454E-02
PAGE NUMBER 29
27
27
27
27
27
27
27
27
0.72475E+00
0.63416E+00
0.11098E+01
0.83233 E+00
0.83223 E+00
0.14564E+01
0.72820E+00
0.63717E+00
0.30473E-02
0.30474E-02
0.30476E-02
0.30474E-02
0.30475E-02
0.30476E-02
0.30473E-02
030474E-02
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
0.30473E-i02 0.30465E-02
0.30474E-!02 0.30462E-02
0.30476E- 02 0.30455E-02
0.30474E-1
02 0.30460E-02
0.30475E-02 0.30457E-02
0.30476E 02 0.30454E-02
0.30473E 02 0.30465E-02
0.30474E 02 0.30462E-02
PAGE NUMBER 30
27
27
27
27
27
27
27
27
0.11151E+01
0.83629E+00
0.81016E+00
0.14178E+01
0.30476E-02
0.30474E-02
0.30475E-02
0.30476E-02
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
0.30476E-02
0.30474E-02
0.30475E-02
0.30476E-02
27
27
27
27
0.00000E+00
0.00000E+00
0.00000E+00
0.00000E+00
0.00000E+00
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
0.30455E-02
0.30460E-02
0.30458E-02
0.30454E-02
349
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
47
2 0.70889E+00
48
7 0.69781 E+00
49
4 0.10467E+01
50
4 0.91588E+00
1 TEST CASE
SOO
51
4 0.80139E+00
0.30473 E-02
0.30474E-02
0.30476E-02
0.30475 E-02
0.30475E-02
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
0.30473 E-02 0.30465E-02
0.30474E-02 0.30461 E-02
0.30476E-02 0.30456E-02
0.30475E-02 0.30458E-02
PAGE NUMBER 31
27
27
27
27
0.30475E-02
27
0.30458E-02
0
OUPDATED PARAM ETER VALUES ARE
PARAMETER( 1)= 0.188557E-01
PARAMETER( 2)= 0.236450E+01
PARAMETER( 3)= 0 .3 18910E+01
PARAMETER( 4)= 0.600018E-01
PARAMETER( 5)= 0.977465E+00
PARAMETER( 6)= -0.100000E+00
PARAMETER( 7)= -0.136852E-03
PARAMETER( 8)= 0.216122E+00
PARAMETER( 9)= 0.300000E+01
PARAMETER( 10)= 0.200000E-01
PARAMETER( 11 )= 0.174000E+01
PARAM ETER(I2)= O.OOOOOOE+OO
PARAMETER( 13)= O.OOOOOOE+OO
PARAMETER( 14)= O.OOOOOOE+OO
PARAMETER(15)= O.OOOOOOE+OO
PARAM ETER(16)= O.OOOOOOE+OO
PARAM ETER(17)= O.OOOOOOE+OO
PARAMETER( 18)= O.OOOOOOE+OO
P ARAMETER( 19)= O.OOOOOOE+OO
PARAMETER(20)= O.OOOOOOE+OO
1 TEST CASE
1 TEST CASE
0.000
0.010
D A T A SE T 1
D A T A SE T 1
0.020
0.030
0.040
0.050
0.060
0.070
0.080
0.090
0.100
XO*
+ -0.7000
350
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
*
*
*
* o
*
+
*
-0.5700
*
*
*
*
O
*
+
-0.4400
O
+
+ -0.3100
*
o
*
*
*
*
o*
-0.1800
*
*
*
*
*
o
*
*
*
*
+
-0.0500
351
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
i-
0 ...+ ......... +■..........+..........+ ..........+ Y
*
*
*
*
*
+
*
0.0800
*
*
*
o
*
*
«
*
*
* o
+
*
0.2100
*
*
* o
*
*
*
+
0.3400
*
*
*
*
*
*
*
*
+
0.4700
+
*
*
*
*
*
*
♦
*
*
*
o
O
0.6000
XMIN = -0.700000
XMAX = 0.600000
352
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
YMIN = 0.000000 YMAX = 0.100000
I TEST CASE
PAGE NUMBER
SOO
0 MAXIMUM ITERATIONS= 50
ITERATION STOPPING TOLERANCE= 0.100000E-08
MAXIMUM PER-UNIT PARAMETER CHANGE PER ITERATION= 0.100000E+00
THE I ESTIMATED PARAMETERS HAVE INDEX-----
8
0
OCURRENT PARAMETER VALUES ARE----PARAMETER! 1)= 0.I88557E-01
PARAMETER! 2)= 0.236450E+01
PARAMETER! 3)= 0.318910E+01
PARAMETER! 4)= 0.600018E-01
PARAMETER! 5)= 0.977465E+00
PARAMETER! 6)= -0.100000E+00
PARAMETER! 7)= -0.136852E-03
PARAMETER! 8)= 0.216122E+00
PARAMETER! 9)= 0.300000E+01
PARAMETER! 10)= 0.200000E-01
PARAMETER! 11)= 0.174000E+01
PARAMETER! 12)= 0.000000E+00
PARAMETER! 13)= 0.000000E+00
PARAMETER! 14)= 0.000000E+00
PARAMETER! 15)= 0.000000E+00
PARAMETER! 16)= O.OOOOOOE+OO
PARAMETER! 17)= O.OOOOOOE+OO
PARAMETER! 18)= 0.000000E+00
PARAMETER! 19)= O.OOOOOOE+OO
PARAMETER(20)= 0.000000E+00
0
0
0 ITERATION INCREMENT INCREMENT
ERROR
ERROR
ERROR
DEGREES
NUMBER CHANGES
RATIO
!1)
!2)
TOTAL
ERROR
0
0 O.OOOOOE+OO 0.30476E-02 0.00000E+00 0.30476E-02 0.30220E-02
PREDICTED
FREEDOM
27
353
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
1
0 O.OOOOOE+OO 0.30220E-02
2
0 O.OOOOOE+OO 0.30220E-02
1 TEST CASE
SOO
O.OOOOOE+OO 0.30220E-02 0.30220E-02
O.OOOOOE+OO 0.30220E-02 0.30220E-02
PAGE NUMBER 33
27
27
0
OCURRENT PARAMETER VALUES ARE----PARAMETER( l)= 0.I88557E-01
PARAMETER( 2)= 0236450E+01
PARAMETER( 3)= 0.3I8910E+0!
PARAMETER( 4)= 0.600018E-01
PARAMETER( 5)= 0.977465E+00
PARAMETER( 6)= -0.100000E+00
PARAMETER( 7)= -0.136852E-03
PARAMETER( 8)= 0235177E+00
PARAMETER( 9)= 0.300000E+01
PARAMETER( 10)= 0.200000E-01
PARAMETER( 11)= 0.174000E+01
PARAMETER( 12)= O.OOOOOOE+OO
PARAMETER( 13)= O.OOOOOOE+OO
PARAMETER( 14)= O.OOOOOOE+OO
PARAMETER(15)= O.OOOOOOE+OO
PARAMETER(16)= O.OOOOOOE+OO
PARAMETER(17)= O.OOOOOOE+OO
PARAMETER(18)= O.OOOOOOE+OO
PARAMETER(19)= O.OOOOOOE+OO
PARAMETER(20)= O.OOOOOOE+OO
0
0
0 ITERATION INCREMENT INCREMENT
ERROR
ERROR
ERROR
PREDICTED
DEGREES
NUMBER CHANGES
RATIO
(1)
(2)
TOTAL
ERROR
FREEDOM
3
0 0.00000E+00 0.30220E-02 O.OOOOOE+OO 0.30220E-02 0.30220E-02
27
1 TEST CASE
PAGE NUMBER 34
SOO
0
0
354
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
0
STANDARD ERRORS AND COVARIANCES----0
PARAMETER! 1) IS 0.18855724E-01
PARAMETER! 2) IS 0.23644974E+01
PARAMETER! 3) IS 0.31891000E+01
PARAMETER! 4) IS 0.6000I802E-0I
PARAMETER! 5) IS 0.97746497E+00
PARAMETER! 6) IS-0.10000000E+00
PARAMETER! 7) IS-0.13685215E-03
PARAMETER! 8) IS 023 5 17747E+00 WITH STANDARD ERROR EQUAL TO 0.39845511E-01
PARAMETER! 9) IS 0.30000000E+01
PARAMETER! 10) IS OJ20000000E-01
PARAMETER! 11) IS 0.17400000E+01
PARAMETER! 12) IS O.OOOOOOOOE+OO
PARAMETER! 13) IS O.OOOOOOOOE+OO
PARAMETER! 14) IS O.OOOOOOOOE+OO
PARAMETER! 15) IS O.OOOOOOOOE+OO
PARAMETER! 16) IS O.OOOOOOOOE+OO
PARAMETER! 17) IS O.OOOOOOOOE+OO
PARAMETER! 18) IS O.OOOOOOOOE+OO
PARAMETER! 19) IS O.OOOOOOOOE+OO
PARAMETER(20) IS O.OOOOOOOOE+OO
0 ERROR 1 IS
0.0030, ERROR2 IS
0.0000, TOTAL ERROR IS
0.0030 WITH 27 DEGREES OF
FREEDOM.
0 NORMALIZED ERROR 1 IS 0.14692149E-01, NORMALIZED ERROR2 IS O.OOOOOOOOE+OO, WHILE
NORMALIZED TOTAL ERROR IS 0.10579556E-01
0
0
NORMALIZED COVARIANCE MATRIX BY ROW IS---0PARAMETER! 8) 0.1OOOOE+01
1 TEST CASE
DATASET 1
I TEST CASE
DATASET 1
0.000
0.010
0.020
0.030
0.040
0.050
0.060
0.070
0.080
0.090
0.100
XO*
+ -0.7000
.
*
*
*
*
*
*
*
* o
+ -0.5700
O
*
*
355
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
+
+ -0.4400
+
+ -0.3100
* o
*
*
*
*
*
*
o *
+ -0.1800
*
*
*
*
*
o
*
*
*
*
+ -0.0500
+........ + Y
*
*
*
#
+
+ 0.0800
*
o
*
*
*
*
*
*
*
*o
356
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
0.2100
*
*
*
*
*
*
*o
*
*
«
+
0.3400
*
*
*
*
*
*
*
o
*
*
+
0.4700
*
*
*
*
o
*
*
*
+
*
o
+ 0.6000
XMIN = -0.700000 XMAX = 0.600000
YMIN = 0.000000 YMAX = 0.100000
PAGE NUMBER 35
1 TEST CASE
SOO
0 MAXIMUM ITERATIONS= 50
ITERATION STOPPING TOLERANCE= 0.100000E-08
MAXIMUM PER-UNIT PARAMETER CHANGE PER ITERATION3 0.1OOOOOE+OO
THE 1 ESTIMATED PARAMETERS HAVE INDEX-----
10
0
0CURRENT PARAMETER VALUES ARE---PARAMETER( I )= 0.188557E-01
PARAMETER( 2)= 0.236450E+0I
PARAMETER( 3)= 0.318910E+01
PARAMETER( 4)= 0.600018E-01
PARAMETER( 5)= 0.977465E+00
357
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
PARAMETER* 6)= -0.100000E+00
PARAMETER* 7)= -0.136852E-03
PARAMETER* 8)= 0.235177E+00
PARAMETER* 9)= 0.300000E+01
PARAMETER* 10)= 0200000E-01
PARAMETER* 11)= 0.174000E+01
PARAMETER* 12)= O.OOOOOOE+OO
PARAMETER* 13)= O.OOOOOOE+OO
PARAMETER* 14)= 0.000000E+00
PARAMETER* 15)= O.OOOOOOE+OO
PARAMETER* 16)= O.OOOOOOE+OO
PARAMETER* 17)= 0.000000E+00
PARAMETER* 18)= O.OOOOOOE+OO
PARAMETER* 19)= 0.000000E+00
PARAMETER(20)= O.OOOOOOE+OO
0
0
0 ITERATION INCREMENT
DEGREES
NUMBER CHANGES
0
11 0.I9200E+03
1
3 0.14400E+03
2
4 0.12600E+03
TEST CASE
ouu
4 0.11025E+03
3
4
5 0.10336E+03
4 0.90439E+02
5
6
5 0.84787E+02
7
4 0.74189E+02
8
5 0.69552E+02
4 0.60858E+02
9
10
5 0.57054E+02
TEST CASE
SOO
4 0.49922E+02
11
12
5 0.46802E+02
13
4 0.40952E+02
14
5 0.38393E+02
4 0.33593E+02
15
INCREMENT
ERROR
ERROR
ERROR
PREDICTED
FREEDC
TOTAL
ERROR
RATIO
(1)
(2)
27
0.30220E-02 0.00000E+00 0.30220E-02 026810E-02
27
0.30185E-02 O.OOOOOE+OO 0.30185E-02 0.26814E-02
27
0.30139E-02 O.OOOOOE+OO 0.30139E-02 026820E-02
PAGE NUMBER 36
0.30087E-02
0.30029E-02
0.29968E-02
029901 E-02
0.29830E-02
0.29752E-02
029672E-02
029583E-02
O.OOOOOE+OO
O.OOOOOE+OO
0.00000E+00
0.00000E+00
O.OOOOOE+OO
0.00000E+00
0.00000E+00
0.00000E+00
0.30087E-02 026826E-02
0.30029E-02 026834E-02
029968E-02 026841 E-02
029901 E-02 0.26850E-02
0.29830E-02 026859E-02
029752E-02 0.26870E-02
0.29672E-02 0.26880E-02
029583E-02 026892E-02
PAGE NUMBER 37
27
27
27
27
27
27
27
27
0.29492E-02
0.29392E-02
0.29291 E-02
0.29181E-02
029070E-02
O.OOOOOE+OO
0.00000E+00
O.OOOOOE+OO
0.00000E+00
0.00000E+00
029492E-02
029392E-02
029291 E-02
029181E-02
029070E-02
27
27
27
27
27
0.26905E-02
026918E-02
026932E-02
0.26948E-02
026964E-02
358
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
16
5
17
4
18
4
TEST CASE
SOO
19
5
4
20
21
4
22
5
23
4
24
4
25
4
26
4
1 TEST CASE
SOO
27
4
28
4
29
4
30
4
31
4
32
3
33
3
34
3
1 TEST CASE
SOO
35
3
36
2
37
0
38
0
39
0
40
0
1 TEST CASE
SOO
0.31494E+02 0.28952E-02
0.27557E+02 0.28834E-02
0.24112E+02 0.28710E-02
O.OOOOOE+OO 0.28952E-02 0.26981 E-02
O.OOOOOE+OO 0.28834E-02 0.26998E-02
O.OOOOOE+OO 0.28710E-02 0.27017E-02
PAGE NUMBER 38
27
27
27
022605E+02
0.19780E+02
0.17307E+02
0.16226E+02
0.14197E+02
0.12423E+02
0.10870E+02
0.95111E+01
0.28580E-02
0.28455E-02
028327E-02
0.28197E-02
0.28077E-02
027958E-02
0.27844E-02
0J27737E-02
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
0.28580E- 02 027036E-02
0.28455E- 02 0.27055E-02
0.28327E- 02 0.27075E-02
0.28197E- 02 0.27096E-02
0.28077E- 02 0.27115E-02
0.27958E- 02 0.27134E-02
0.27844E- 02 0.27153E-02
0.27737E- 02 0.27171 E-02
PAGE NUMBER 39
27
27
27
27
27
27
27
27
0.83223E+Ol
0.72820E+01
0.63717E+01
0.55753E+01
0.48784E+01
0.36588E+01
0.27441 E+01
0.20581 E+Ol
0.27639E-02
0.27552E-02
0.27477E-02
027415E-02
0.27365E-02
0.27327E-02
027297E-02
027275E-02
0.00000E+00
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
027639E-02 0.27187E-02
0.27552E-02 0.27202E-02
0.27477E-02 0.27215E-02
0.27415E-02 0.27225E-02
0.27365E-02 0.27234E-02
0.27327E-02 0.27240E-02
0.27297E-02 0.27246E-02
0.27275E-02 0.27249E-02
PAGE NUMBER 40
27
27
27
27
27
27
27
27
0.15435E+01
0.77177E+00
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
0.27263E-02
0.27256E-02
0.27254E-02
0.27253E-02
0.27253 E-02
027253E-02
0.00000E+00
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
0.27263E-02 0.27252E-02
0.27256E-02 0.27253E-02
0.27254E-02 0.27253E-02
0.27253E-02 0.27253E-02
0.27253 E-02 0.27253E-02
0.27253 E-02 0.27253E-02
PAGE NUMBER 41
27
27
27
27
27
27
0
OCURRENT PARAMETER VALUES ARE
PARAMETER( 1)= 0.188557E-01
PARAMETER( 2)= 0.236450E+01
PARAMETER( 3)= 0.318910E+01
PARAMETER( 4)= 0.600018E-01
PARAMETER( 5)= 0.977465E+00
PARAMETER( 6)= -0.100000E+00
PARAMETER( 7)= -0.136852E-03
PARAMETER( 8)= 0.235177E+00
PARAMETER( 9)= 0.300000E+01
PARAMETER^ 10)= 0.601305E+00
PARAMETERS 11)= 0.174000E+01
359
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
PARAMETER! 12)= 0.000000E+00
PARAMETER! 13)= 0.000000E+00
PARAMETER! 14)= O.OOOOOOE+OO
PARAMETER! 15)= O.OOOOOOE+OO
PARAMETER! 16)= 0.000000E+00
PARAMETER! 17)= O.OOOOOOE+OO
PARAMETER! 18)= 0.000000E+00
PARAMETER! 19)= 0.000000E+00
PARAMETER(20)= O.OOOOOOE+OO
0
0
0 ITERATION INCREMENT
DEGREES
NUMBER CHANGES
41
0 0.00000E+00
1 TEST CASE
SOO
INCREMENT
ERROR
ERROR
ERROR
PREDICTED
RATIO
TOTAL
ERROR
FREEDOM
( 1)
(2)
0.27253E-02 O.OOOOOE+OO 0.27253E-02 0.27253 E-02
27
PAGE NUMBER 42
0
0
0- -STANDARD ERRORS AND COVARIANCES0
PARAMETER( 1) IS 0 .18855724E-01
PARAMETER( 2) IS 0.23644974E+01
PARAMETER! 3) IS 0.31891000E+01
PARAMETER! 4) IS 0.60001802E-01
PARAMETER! 5) IS 0.97746497E+00
PARAMETER! 6) IS-0.10000000E+00
PARAMETER! 7) IS-0.13685215E-03
PARAMETER! 8) IS 0.23517747E+00
PARAMETER! 9) IS 0.30000000E+01
PARAMETER! 10) IS 0.60120267E+00 WITH STANDARD ERROR EQUAL TO 0.16452514E+01
PARAMETER! 11) IS 0.17400000E+01
PARAMETER! 12) IS O.OOOOOOOOE+OO
PARAMETER! 13) IS O.OOOOOOOOE+OO
PARAMETER! 14) IS 0.00000000E+00
PARAMETER! 15) IS 0.00000000E+00
PARAMETER! 16) IS O.OOOOOOOOE+OO
PARAMETER! 17) IS O.OOOOOOOOE+OO
PARAMETER! 18) IS O.OOOOOOOOE+OO
PARAMETER! 19) IS O.OOOOOOOOE+OO
PARAMETER(20) IS O.OOOOOOOOE+OO
0 ERROR 1 IS
0.0027, ERROR2 IS
0.0000, TOTAL ERROR IS
0.0027 WITH 27 DEGREES OF
FREEDOM.
0 NORMALIZED ERROR 1 IS 0.13952277E-01, NORMALIZED ERROR2 IS O.OOOOOOOOE+OO, WHILE
NORMALIZED TOTAL ERROR IS 0.10046788E-01
0
360
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
0
NORMALIZED COVARIANCE MATRIX BY ROW IS----OPARAMETER( 10)
0.10000E+01
1 TEST CASE
DATASET I
I TEST CASE
DATASET 1
0.000
XO
+ -0.7000
+
-0.5700
0.010
0.020
0.030
0.040
0.050
0.060
0.070
0.080
0.090
0.100
*
*
*
*
*
*
*
*
o *
*
*
*
*
*
♦
*o
*
*
«
*
*
+ -0.4400
*
*
* o
*
*
*
*
*
*
+
*
-0.3100
+
+ -0.1800
*O
*
*
*
*
*
*
o *
*
*
*
*
361
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
*
*
*
o
+ -0.0500
*
*
*
*
+
h
0. . . + . . .
.+
*
♦
*
*
*
*
+
+ ............+ Y
+ 0.0800
O
*
*
*
*
*o
+
0.2100
*
*
* o
*
*
*
+
+ 0.3400
*
*
o
*
♦
+
+ 0.4700
*
*
362
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
XMIN = -0.700000 XMAX = 0.600000
YMIN = 0.000000 YMAX = 0.100000
PAGE NUMBER 43
1 TEST CASE
SOO
0 MAXIMUM ITERATIONS= 50
ITERATION STOPPING TOLERANCE= 0.1OOOOOE-07
MAXIMUM PER-UNIT PARAMETER CHANGE PER ITERATION 0.100000E+00
THE 4 ESTIMATED PARAMETERS HAVE INDEX---1 2 5 8
0
0CURRENT PARAMETER VALUES ARE----PARAMETER( I)= 0.188557E-01
PARAMETER! 2)= 0.236450E+01
PARAMETER! 3)= 0.318910E+01
PARAMETER! 4)= 0.600018E-01
PARAMETER! 5)= 0.977465E+00
PARAMETER! 6)= -0.100000E+00
PARAMETER! 7)= -0.136852E-03
PARAMETER! 8)= 0.235177E+00
PARAMETER! 9)= 0.300000E+01
PARAMETER! 10)= 0.60I203E+00
PARAMETER! 11)= 0.174000E+01
PARAMETER! 12)= O.OOOOOOE+OO
PARAMETER! 13)= O.OOOOOOE+OO
PARAMETER! 14)= 0.000000E+00
PARAMETER! 15)= O.OOOOOOE+OO
PARAMETER!16)= 0.000000E+00
PARAMETER!17)= 0.000000E+00
PARAMETER! 18)= 0.000000E+00
363
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
P A R A M E T E R 19)= O.OOOOOOE+OO
PARAMETER(20)= O.OOOOOOE+OO
0
0
0 ITERATION INCREMENT
DEGREES
NUMBER CHANGES
0
7 0.12000E+02
1
3 0.90000E+01
2
4 0.78750E+01
1 TEST CASE
SOO
3
3 0.59063 E+Ol
4
3 0.44297E+01
5
3 0.33223E+01
6
2 0.16611E+01
7
2 0.83057E+00
8
0 O.OOOOOE+OO
9
2 0.41528E+00
10
0 O.OOOOOE+OO
I TEST CASE
SOO
11
21 0.39604E-06
12
4 0.49506E-07
13
3 0.37129E-07
14
4 0.32488E-07
15
3 0.24366E-07
16
4 0.36549E-07
17
4 0.31980E-07
18
4 0.4797 IE-07
1 TEST CASE
SOO
2 0.23985E-07
19
20
5 0.71956E-07
2 0.35978E-07
21
2 0.17989E-07
22
23
3 0.13492E-07
24
5 0.I2649E-07
2 0.63243E-08
25
26
7 0.7589 IE-07
1 TEST CASE
SOO
27
3 0.56918E-07
2 0.28459E-07
28
29
3 0.21344E-07
30
2 0.10672E-07
31
4 0.16008E-07
32
0 0.00000E+00
33
5 0.28014E-07
34
4 0.42022E-07
1 TEST CASE
SOO
35
0 O.OOOOOE+OO
36
2 0J21011E-O7
INCREMENT
ERROR
ERROR
ERROR
PREDIC
RATIO
TOTAL
FREEDC
ERROR
(1)
(2)
0.27253E-02 O.OOOOOE+OO 0.27253E-02 0.I2151E-02
24
0.25438E-02 O.OOOOOE+OO 0.25438E-02 0.12111E-02
24
0.23436E-02 O.OOOOOE+OO 0.23436E-02 0.12066E-02
24
PAGE NUMBER 44
0.21565E-02
0.19586E-02
0.17600E-02
0.I5749E-02
0.13735E-02
0.12369E-02
0.11848E-02
0.1I847E-02
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
0.21565E-02 0.12025E-02
0.19586E-02 0.11982E-02
0.17600E-02 0.11943 E-02
0.15749E-02 0 .11909E-02
0.13735E-02 0.11876E-02
0.12369E-02 0.11855E-02
0.11848E-02 0.11847E-02
0.11847E-02 0.11847E-02
PAGE NUMBER 45
24
24
24
24
24
24
24
24
0.11847E-02
0.11847E-02
0.11847E-02
0.11847E-02
0.11848E-02
0.11847E-02
0.11847E-02
0 .11847E-02
0.00000E+00
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
0.11847E-02 0.11847E-02
0.11847E-02 0.11847E-02
0.11847E-02 0.11847E-02
0.11847E-02 0.11847E-02
0.11848E-02 0 .11847E-02
0.11847E-02 0.11847E-02
0.11847E-02 0.11847E-02
0.11847E-02 0 .11847E-02
PAGE NUMBER 46
24
24
24
24
24
24
24
24
0.11847E-02
0.11847E-02
0.11847E-02
0.11847E-02
0 .11847E-02
0.11847E-02
0.11847E-02
0.11847E-02
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
0.11847E-02 0.11847E-02
0.11847E-02 0.11847E-02
0.11847E-02 0.11847E-02
0.11847E-02 0.11847E-02
0.11847E-02 0.11847E-02
0.11847E-02 0.11847E-02
0.11847E-02 0.11847E-02
0.11847E-02 0 .11847E-02
PAGE NUMBER 47
24
24
24
24
24
24
24
24
0.11847E-02
0.11847E-02
0.11847E-02
0.11847E-02
0.11847E-02
0.1I847E-02
0.11847E-02
0.11847E-02
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
0.11847E-02 0.11847E-02
0.11847E-02 0.11847E-02
0.11847E-02 0.11847E-02
0.11847E-02 0.11847E-02
0.11847E-02 0.11847E-02
0.11847E-02 0.11847E-02
0.11847E-02 0.11847E-02
0.11847E-02 0.11847E-02
PAGE NUMBER 48
24
24
24
24
24
24
24
24
0.11847E-02 O.OOOOOE+OO 0.11847E-02 0.11847E-02
0.11847E-02 O.OOOOOE+OO 0.11847E-02 0.11847E-02
364
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
24
24
37
5
38
5
2
39
40
0
41
4
42
5
EST CASE
SOO
0
43
44
4
45
0
46
5
47
5
5
48
49
4
2
50
1ST CASE
SOO
2
51
0.36769E-07
0.64346E-07
0.32173 E-07
O.OOOOOE+OO
028151 E-07
0.26392E-07
0.11847E-02
0.11847E-02
0.11847E-02
0.11847E-02
0.11847E-02
0.11847E-02
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
0.11847E-02 0.11847E-02
0.11847E-02 0.11847E-02
0.11847E-02 0.11847E-02
0.11847E-02 0.11847E-02
0.11847E-02 0.11847E-02
0.11847E-02 0.11847E-02
PAGE NUMBER 49
24
24
24
24
24
24
O.OOOOOE+OO
0.23093 E-07
O.OOOOOE+OO
0.21650E-07
0.20296E-07
0.60889E-07
0.91334E-07
0.45667E-07
0.11847E-02
0.11847E-02
0.11847E-02
0.11847E-02
0.11847E-02
0.11847E-02
0.11847E-02
0.11847E-02
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
O.OOOOOE+OO
0.11847E-02 0.11847E-02
0.11847E-02 0.11847E-02
0.11847E-02 0.11847E-02
0.11847E-02 0.11847E-02
0.11847E-02 0.11847E-02
0.11847E-02 0.11847E-02
0.11847E-02 0.11847E-02
0.11847E-02 0.11847E-02
PAGE NUMBER 50
24
24
24
24
24
24
24
24
022833E-07
0.11847E-02
O.OOOOOE+OO 0.11847E-02
0.11847E-02
0
OUPDATED PARAMETER VALUES ARE----PARAMETER( 1)= 0218418E-01
PARAMETER( 2)= 0.170379E+01
PARAMETER( 3)= 0.31891OE+01
PARAMETER( 4)= 0.600018E-01
PARAMETER( 5)= 0.204579E+01
PARAMETER( 6)= -0.100000E+00
PARAMETER( 7)= -0.136852E-03
PARAMETER( 8)= 0.197857E+00
PARAMETER( 9)= 0.300000E+01
PARAMETER(10)= 0.601203E+00
PARAMETER( 11)= 0.174000E+01
PARAMETER(12)= O.OOOOOOE+OO
PARAMETER( 13)= O.OOOOOOE+OO
PARAMETER(14)= O.OOOOOOE+OO
PARAMETER(15)= O.OOOOOOE+OO
PARAMETER(16)= O.OOOOOOE+OO
PARAMETER(17)= O.OOOOOOE+OO
PARAMETER(18)= O.OOOOOOE+OO
365
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
24
PARAMETER^ 19)= O.OOOOOOE+OO
PARAMETER(20)= O.OOOOOOE+OO
1 TEST CASE
I TEST CASE
DATASET I
DATASET 1
0.000
0.010
XO
*
0.020
0.030
0.040
0.050
0.060
0.070
0.080
0.090
0.100
+ -0.7000
*
*
*
*
o
*
*
+
*
+ -0.5700
*
*
o
*
*
*
*
*
+
*
-0.4400
o
+■
*
*
*
*
*
*
*
*
+ -0.3100
+
o *
*
*
*
*
*
*
o*
*
♦
+ -0.1800
366
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
o*
+
+ -0.0500
* ..................+ ................... - i-..
+
+ ..
..+........ + Y
0.0800
O
O
0.2100
*
o*
*
*
*
+ 0.3400
*
*
♦
*
*O
*
*
+ 0.4700
367
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
o
+
*
*
*
o
+ 0.6000
XMIN = -0.700000 XMAX = 0.600000
YMIN = 0.000000 YMAX = 0.100000
-END OF THIS SET OF ESTIMATION JOBS-
368
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Appendix D
Sample Test Program Files
369
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
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371
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Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
por t - l
. IND
GAASFE^
C -1 0 0 0
L -IO D O
n)
m
PORT
P2
p o r t —2
H-1000
FET2
“
AREA-1
M O O EL-FET1
M O O C -n o n lIn o a r
ocvs
-SRC1
-DC—_ b 1 0 ( 2
ocvs
U l
CAP
C2
C—1 00 0
-D C -.b lo o t
to
<
STATZ
FET1
B E T A - 0 .10
VTO— 0 . 5 5
A LP H A -5
LA M B DA -0.2 5
T H E T A -1 .5 0
TA U -0
V B R -0
Figure
D .3
IS—1 oo.-o#
N-1
V B I— 0 . 7 0
F C - 0 .5 0
RC—3 5 0
C R F - O .10
RD—0 . 5 0
Samp I e
RG-1
R S - 0 .5 0
R IN -1
COSO-O.1 3
CGDO—0 . 0 4
D E L T A 1 -0 .2 0
0 E L T A 2 -O .2 0
C D S -0 .0 5
CG S -0
C C D -0
K F -0
A F -1
TNOM-27
X T I-3
Ci rcu i t
EG—1 .1 1
VTOTC-O
B ETATCE-0
F F E -1
Listing
of
PHEMT
S i mu I a t i o n
Appendix E
Manufacture Data Sheet of Devices Used in this Study
373
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
| T 5 | HEW LETT*
1 2 E I PA CKA RD
1.5 • 18 GHz Surface Mount
Pseudomorphic HEMT
Preliminaiy Technical Data
ATF-36163
Features
Surface Mount Package
* L ow Minimntn N oise Figure:
I dB Typical at 12 GHz 0.6 dB Typical ax 4 GHz
(SOT-363/S C-70)
* Associated Gain:
9.4 dB Typical at 12 GHz
15.8 dB typical at 4 GHz
* Maximum Available Gain:
I I dB typical at 12 GHz
17 dB typical at 4 GHz
* L ow Coat Surface M ount
Sm all Plastic Package
* Tape-and-Reel Packaging
O ption A vailable
Applications
* 12 GHz DBS Downconverters
* 4 GHz TVRQ D ownconverters
• 8 o r L Band Low Noiae
A m plifiers
Pin Connections and
Package Marking
SOURCE
SOURCE
cnl
m CO
o>
OATS U
TT1 ORAM
ID SOURCE
t n
SOURCE
Note; Package marking provides
orientation and Identification.
Description
The Hewlett-Packard ATF-36163
is a low-noise Pseudomorphic
High Electron Mobility Transistor
(PHEMT), in the SOT-363/SC-70
package. When optimally matched
to the minimum noise figure, it
will provide a noise figure of 1 dB
at 12 GHz and 0.6 dB at 4 GHz.
Additionally, the ATF-36163 has
low noise resistance, which
reduces the sensitivity of noise
performance to variations in
input impedance match. This
feature makes the design of
broad band low noise amplifiers
much easier. The performance of
the ATF-36163 makes this device
the ideal choice for use in the 2nd
or 3rd stage of low noise
cascades. The repeatable per­
formance and consistency make it
appropriate for use in Ku-band
Direct Broadcast Satellite (DBS)
TV systems, C-band TV Receive
Only (TVRO) LNAs, Multichannel
Multipoint Distribution Systems
(MMDS), X-band Radar detector
and other low noise amplifiers
operating in the 1.5 -18 GHz
frequency range.
This GaAs PHEMT device has a
nominal 0.2 micron gate length
with a total gate periphery
(width) of 200 microns. Proven
gold-based metallization system
and nitride passivation assure
rugged, reliable devices.
374
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
2
ATF-36163 Absolute Maximum Ratings! *1
S ym b ol
Vug
Vcs
VCD
Id
Pt
''
n
• j max
-CH
Tstc.
Param eter
Drain - Source Voltage
Gate - Source Voltage
Gate Drain Voltage
Drain Current
Total Power Dissipation
RF Input Power
Channel Temperature
Storage Temperature
Units
V
V
V
mA
mW
dBm
°C
•c
Therm al R esistance:
«=i6o*c/w
A b solu te
M aximum
+3
-3
-3.5
Note:
1. Operation of this device shove any one
or these panm eten may cause
pennanent damage.
Id-
180
+ 10
150
-65 to 150
ATF-36163 Electrical Specifications
Tc ” 25*C, Zq = 50 C,
S ym bol
NF
G
6m
I*.
Ve 104«
BVeoo
1.5 V, 1^ = 10 mA, (unless ocherwise noted).
Param eters and T e s t Conditiona
f = 12.0 GHz
Noise Figure^!
Gain at NFlU
f = 12.0 GHz
Transconductance
Vqs = 1.5 V, Vqs = 0 V
Saturated Drain Current
VM = 1.5 V, Vqs = 0 V
Pinchoff Voltage
Vos = 1.5 V, Ids = 10% of I*,
Gaxe Drain Breakdown Voltage
I© « 30 pA
U nits
dB
dB
mS
mA
V
V
Min.
9
50
r 15"
-1.0
Typ.
1.2
10
60
25
-0.35
Max.
40
-0.15
-3.5
Note:
1. Meaaored in a lest circuit omedfar atypical device.
ATF-36163 Typical Parameters
C
/1
Tc = 25°C, Zq = 50 £1,
= 2 V, 1^ = 15 mA, (unless otherwise noted).
Sym b ol
P aram eters and T est Conditions
Fnu,
f = 4 GHz
Minimum Noise Figure ( T k v k * ~ Fiot)
f = 12 GHz
f - 4 GHz
Associated Gain
G*
f = 12 GHz
Maximum Available Gain(11
f = 4 GHz
f = 12 GHz
f = 4 GHz
Output Power at 1 dB Gain Compression
PldB
f = 12 GHz
under the power matched condition
Vos - 2.0 V
Gate to Source Voltage for Iqs = 15 mA
Note:
1■G— “ MAG for K > 1 and Gmrr “ MSG for K < X, which is shown on the S-parameters tables
375
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
U nits
dB
dB
dB
dB
dB
^
dB
dBm
dBm
V
Typ.
0.6
1.0
15.8
9.4
17.2
10.9
°
5
-0.2
i
|
ATF-36163 Typical Scattering Parameters, Common Source, Zp = 50 Q. VD6= 1-5V, ID- 10 mA
Freq.
GHz
0.5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Mag.
0.99
0.98
0.96
0.93
0.87
0.81
0.75
0.67
0.61
0.57
0.57
0.69
0.63
0.67
0.72
0.78
0.82
0.87
0.90
su
Aug.
dB
12.85
-11
-22
12.70
-42 -12.48
-61
12.37
-83
12.30
-106
12.16
-131
11.94
-158 U -47
176
11.01
143
10.47
9.66
108
76
8.53
50
7.39
26
6.10
6
'4.81
-11
3.49
-24
2.20
-38
0.59
-62
-1.63
8*1
Mag.
4.39
4.31
4.21
4.16
4.12
4.06
3.95
3.75
3.56
3.34
3.04
2.67
2.34
2.02
1.74
1.50
1.29
1.07
0.83
Aug.
168
158
138
118
97
76
55
33
12
-10
-32
-54
-74
-93
-U l
-128
-146
-164
178
dB
•37.72
-31.70
•26.02
-22.73
-20.45
-18.71
-17.52
-16.77
-16.36
-15.97
-15.92
•16.48
-17.14
-18.27
-19.74
-21.41
-23.10
-25.04
-29.12
N ote:
1 Gnu - MAG for K > 1 and Gw = MSG for K £ 1.
Si*
Mag.
0.01
0.03
0.05
0 .0 7
0.10
0.12
0.13
0.15
0.15
0.16
0.16
0.15
0.14
0.12
0.1 0
0.09
0.07
0.06
0.04
K
Sj*
Mag. Ajug.
0.51
•9
0.50
-18
-36
0.48
-63
0.45
-71
0.40
0.34
-92
0.27 -116
0.18 -144
0.10
174
0.12
93
0.22
53
28
0.33
0.41
9
•8
0.49
0.56
-22
-33
0.63
0.67
•43
-63
0.73
0.78
-65
Ang.
79
71
65
40
23
6
-12
-30
-45
-61
-77
-93
-106
-119
-129
-138
-144
-151
-169
0.11
0.17
0.24
0.33
0.43
0.51
0.58
0.69
0.79
0.85
0.91
0.99
1.07
1.18
1.30
1.38
1.44
1.46
1.80
Gma*111
dB
25.24
22.26
19.28
17.56
16.38
15.43
14.73
14.12
13.69
13.22
12.80
12.50
10.66
9.64
8.9 9
8.81
8.70
8.79
8.58 j
2.4
2.0
ATF-36163 Typical Noise Parameters
Common Source, Zq = 50 £1, VDS = 1.5 V, ID * 10 mA
Freq.
Kn/Zp
Ga
F adn
ropt
GHz
dB
dB
Blag.
Ang.
0.48
18.77
0.78
28
2
0.38
16.75
3
0.53
0.75
0.32
41
4
0.57
55
15.17
0.68
0.26
0.61
71
0.20
5
14.14
0.60
6
0.66
0.65
88
13.23
0.15
0.71
7
12.06
105
0.12
0.48
0.77
8
119
0.38
11.22
0.10
10.50
9
0.83
0.32
138
0.07
10
0.89
170
0.07
10.02
0.23
0.97
9.44
11
0.18
-141
0.09
12
1.05
8.92
0.13
0.20
-92
1.14
13
8.45
0.26
-46
0.21
1.24
14
8.12
0.36
-16.
0.32
15
1.37
0.48
4
8.08
0.44
19
0.5.9
1.51
8.11
0.60
16
17
7.97
0.64
34
1.68
0.79
18
1.89
61
7.59
0.70
1.15
o
0
2
4
•
I
10
12
14
l(
II
FREQUENCY (QHa)
Figure 1. ATF-36163 Mlnlmnm NoLie Figure and
Aaeoeiatod Gain va. Frequency for
VDg = 1.5 V, I0 e 10 nuL
24
20
11
M
AC
4
0
FREQUENCY(CHS)
Figure 2. Maximum Available Gain, Maximum
Stable Gain & Inaertion Pow er Gain va.
Frequency for VM - 1.5 V, ID s 10 mA.
376
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
4
A l l 1.3 6 1 6 3 T y p ic a l S c a tte r in g P a ra m e te rs , Comrnon Source, Zp «■ 50 Q, Vd s =1.5V, ID = 15 mA
Freq.
GHz
0.5
1
2
3
4
5
6
m
i
8
9
10
11
12
13
14
15
16
17
IS
Mag.
0.99
0.98
0.96
0.92
0.66
0.80
0.74
0.66
0.59
0.56
0.56
0.59
0.63
0.68
0.73
0.79
0.83
0.87
0.91
Sin
Ang.
-12
-22
-43
-63
•85
-108
-133
-160
173
141
106
74
49
25
5
-12
-25
-38
-53
dB
13.56
13.40
13.16
13.00
J° 07
10.74
9.89
8.74
7.59
6.29
5.01
3.70
2.43
0.84
-1.33
S ii
Mag.
4.76
4.68
4.55
4.47
4.40
4.30
4.16
3.91
3.68
3.44
3.12
2.74
2.40
2.06
1.78
1.53
1.32
1.10
0.86
Ang.
168
157
137
116
96
75
53
31
11
-11
-33
-54
-74
-93
-110
-127
-144
-163
180
dB
-38.42
•32.40
-26.56
-23.22
-21.01
-19.25
-18.13
-17.39
-16.95
-16.54
-16.42
-16.83
-17.39
-18.42
-19.74
-21.31
-22.85
-24.73
-28.87
N ote:
Gnu
K
Su
Mag.
0.01
0.02
0.05
007
0 .0 9
0.11
0.12
0.14
0.14
0 .1 5
0.15
0.14
0.14
0-12
0 .1 0
0.09
0.07
0.06
0.04
Ang.
79
71
56
40
24
7
-11
-28
-42
-58
-73
-88
-102
-115
-124
-133
-139
-148
-155
Mag.
0.45
0.45
0.43
0.40
0.35
0.28
0.21
0.13
0.06
0.12
0.23
0.34
0.42
0.50
0.57
0.64
0.68
0.73
0.78
Ang.
-9
-18
-36
-52
-70
-92
-116
-146
156
73
44
23
6
-10
-23
-34
-44
-54
-66
---------
0.12
0.18
0.26
0.35
0.46
0.55
0.62
0.74
0.84
0.90
0.95
1.03
1.10
1.19
1.29
1.35
1.39
1.39
1.67
2.4
MAC for K > 1 u td
= MSG for K £ I.
ATF-36163 Typical Noise Parameters
1JB
mA
Freq.
GHz
2
3
4
5
6
(
8
9
10
11
12
13
14
15
16
17
18
< W I!
dB
25.82
22.86
19.87
18.13
16.94
15.98
15.25
14.62
14.14
13.63
13.16
11.78
10.62
9.72
9.15
8.99
8.93
9.06
8 92 |
P eUa
dB
0.49
0.54
0.58
0.63
0.68
0.73
0.79
0.86
0.91
0.99
1.07
1.17
1.27
1.40
1.54
1.72
1.93
l~ept
dB
18.87
17.20
15.75
14.49
13.61
12.36
11.54
10.82
10.32
9.73
9.22
8.68
8.41
8.36
8.37
8.10
8.00
Mag.
0.84
0.74
0.66
0.59
0.54
0.46
0.37
0.30
0.21
0.17
0.20
0.26
0.38
0.49
0.60
0.62
0.71
m
Rn/Zo
Ang.
28
42
57
72
90
106
121
140
174
-133
-83
-40
-12
7
21
35
52
0.1
0.38
0.31
0.25
0.19
0.15
0.11
0.09
0.08
0.08
0.10
0.14
0.22
0.34
0.46
0.64
0.85
1.18
0
2
4
•
•
10 12
14
18 I I
FREQUENCY (GHx)
Figure S. ATF-36L63 Minimum N'oiac Figure
and A ssociated Gain vs. Frequency for
VDJ - 1.5 V, I„ - 15 mA.
24
20
16
MSG
12
MAC
4
0
0
2
4
•
•
10 12
14 18 18
FREQUENCY (OHx)
Figure 4. Maximum Available Gain, Maximum
S table Gala A Insertion Pow er Gain ve.
Frequency for Voa « 1.5 V, ID a 15 mA.
377
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
5
ATF-36163 Typical Scattering Parameters, CommonSource, Zb =*50 Q, Vpg = 2.0 V,
Ip * OmA.
Freq.
GHz
0.5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Blag.
0.99
0.99
0.96
0.93
0.87
0.81
0.75
0.67
0.60
0.57
0.56
0.58
0.62
0.67
0 72
0.78
0.82
0.87
0.91
Sa
Ang.
-11
-22 .
-42
-62
-83
-106
-131
-157
176
144
109
77
50
26
6
-10
-24
-37
-52
s
S g i
dB
13.06
12.90
12.69
12.57
12.51
12.38
12.15
11.70
11.25
10.73
9.95
8.86
7.75
6.49
5.24
3.96
2.68
1.08
-1.16
Mag.
4.50
4.42
4.31
4.25
4.22
4.16
4.05
3.84
3.65
3.44
3.14
2.77
2.44
2.11
1.83
1.58
1.36
1.13
0.88
Ang.
168
158
138
118
97
76
55
33
13
-10
-32
-53
-73
-93
-110
•128
-146
-165
177
dB
-37.72
-32.04
•26.38
-22.97
-20.72
•18.94
-17.79
-17.08
-16.65
•16.25
-16.25
-16.77
-17.39
-18.56
-19.91
-21.51
-23.10
-24.88
-28.64
K
Gmaxt1)
dB
0.11
0.16
0.24
0.32
0.42
0.51
0.58
0.69
0.79
0.85
0.91
1.00
1.08
1.19
1.31
1.38
1.42
1.38
1.63
25.46
22.46
19.60
17.77
16.61
15.67
14.98
14.38
13.96
13.50
13.10
12.52
10.82
9.85
9.24
9.07
9.03
9.28
9.06
u
Mag.
0.01
0.03
0.05
0.07
0.09
0.11
0.13
0.14
0.15
0.15
0.15
0.15
0.14
0.12
0.10
0.08
0.07
0.06
0.04
Ang.
79
71
56
40
23
6
-12
-30
-44
-60
-76
-91
-104
-117
-126
-134
-139
-147
-153
Mag.
0.55
0.55
0.53
0.50
0.44
0.38
0.31
0.21
0.13
0.10
0.18
0.29
0.37
0.46
0.53
0.60
0.65
0.71
0.78
Ang.
-9
-18
-35
-62
-70
-90
-112
-137
-168
116
61
32
12
-5
-19
-30
•40
-50
-63
N oti!
1. CM «■ MAG far K > I nnci Cl<nt = MSG fa r K £ I
2.0
ATF-36163 Typical Noise Parameters
14
Common Source, Zp « 60 Q, VD9 = 2.0 V, In = 10 mA
Freq.
GHz
F nit
dB
G*
dB
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
0.46
0.50
0.54
0.59
0.63
0.68
0.74
0.80
0.86
0.94
1.02
1.11
1.22
1.35
1.51
1.69
1.92
18.60
16.75
15.55
14.20
13.37
12.12
1 1.35
10.59
10.11
9.57
9.08
8.59
8.30
8.29
8.32
8.07
7.G8
r 09t
Mag.
0.84
0.76
0.67
0.61
0.56
0.49
0.39
0.33
0.23
0.17
0.18
0.24
0.34
0.47
0.58
0 .0 0
0.66
03
E b/Zo
a.
Ang.
28
41
56
70
88
103
118
135
165
-145
-93
-47
-16
m
D
19
34
50
0.38
0.31
0.25
0.20
0.15
0.12
0 .1 0
0.07
0.07
0.09
0.12
0.19
0.30
0.42
0.57
0.76
J.10
04
FREQUENCY (OMz)
Flgnra 8. ATF-S8183 Minimum Nolaa Figure
u d A n o c U tw l G ala w . Frequency for
VD1 - 2.0 V, I„ - 10 blA.
msq
S'
5-
s<
UAQ
a
FREQUENCY (OHS)
Figure s . M « T i m i i m A n llib l* Gain, MUtaREB
S u b la G ala A In sertio n P ow ar Gala vs.
iN q u n tjr fo r Vq, ■ 2.0 V, Ip ■ 10 n u t
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
6
ATF-36163 Typical Scattering Parameters, Common Source, Zo = 50 n, Vos - 2 V,
Ip = 15 mA
Freq.
GHz
0.5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Mag.
0.99
0.98
0.96
0.92
0.86
0.79
0.73
0.65
0.69
0.65
0.66
0.58
0.63
0.68
0.73
0.78
0.83
0.88
0.91
Su
Ang.
-12
•22 .
-43
-63
-85
-108
-133
-160
173
141
107
.7 5
49
26
6
-11
-24
-38
•52
dB
13.85
■13-70
13.45
13.29
13 i6
!
4
’
li. . J
11.63
11.06
10.23
9.11
8.00
6.75
5.49
4.22
2.99
1.42
-0.79
S*i
Mag.
4.93
4.84
4.70
4.62
4.65
4.45
4.30
4.04
3.81
3.57
3.25
2.86
2.51
2.17
1.88
1.63
1.41
1.18
0.91
Ang.
168
157
137
117
96
75
63
32
11
-11
-32
-53
-73
-92
•110
-127
-145
-164
178
dB
-38.42
-32.40
-26.74
-23.48
-21.31
•19.58
-18.42
-17.72
-17.27
•16.83
-16.77
-17.14
-17.72
-18.71
•20.00
-21.41
-22.73
-24.44
-27.96
Su
Mag.
0.01
0.02
0.05
0.07
0.09
0 .1 1
0.12
0.13
0.14
0.14
0.15
0.14
0.13
0.12
0.10
0.09
0.07
0.06
0.04
K
Aug.
79
71
56
40
24
7
-10
-28
-42
-57
-72
-87
-99
-112
-121
-129
-135
-143
•149
Mag.
0.51
0.50
0.48
0.45
0.40
0.33
0.26
0.17
0.09
0.09
0.19
0.30
0.38
0.47
0.54
0.61
0.66
0.72
0.78
Ang.
-9
-18
•35
-52
•69
•90
-112
-136
-171
93
51
27
9
-7
-20
-31
•41
-51
-63
0.12
0.17
0.26
0.35
0.46
0.55
0.62
0.75
0.84
0.90
0.96
1.04
1.11
1.20
1.30
1.35
1.36
1.31
1.50
dB
26.10
23.11
20.13
18.40
17.22
16.26
15.54
14.93
14.46
13.95
13.50
11.93
10.85
10.00
9.45
9.30
9.31
9.56
9.44
N ote:
l . G _ - MAGfor K > 1 tad G „ - MSG for K£ 1.
ATF-36163 Typical Noise Parameters
— 2.0 V, ID = 15 mA
Freq.
GHz
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
dB
0.48
0.52
0.56
0.61
0.65
0.70
0.76
0.82
0.88
0.95
1.03
1.12
1.23
1.35
1.49
1.65
1.86
G.
dB
18.97
17.27
15.75
14.54
13.6?
12.47
11.66
10.94
10.44
9.88
9.38
8.90
8.63
8.59
8.63
8.68
8.32
i'opt
Mag.
0.83
0.74
0.67
0.60
0.55
0.46
0.37
0.31
0.21
0.15
0.18
0.25
0.36
0.48
0.58
0.65
0.70
R»/Zo
Ang.
28
41
56
71
89
104
118
136
168
-137
-85
-41
-13
7
20
34
51
0.37
0.31
0.25
0.19
0.15
0.11
0.09
0.08
0.07
0.09
0.13
0.21
0.32
0.44
0.60
0.79
1.10
■
T>
J
<U
0.4
FREQUENCY (GHZ)
Figure 7. ATF-36163 Minimum NoUe Figure
end A eeodeted Gain va. Frcqntacy fo r
VM = 2 V, ID - 18 mA.
24
20
12
4
0
FREQUENCY(GHi)
379
Figure S. M udm om AvalUbla G ila, M u d n n n
S tsb le G ain a Inaertion Power Gain va.
Frequency fo r VM ■ S V, ID » IB mA.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
F lfa re 0. Sm ith Ckart w ith N oice F itfw e u l A yillcb le
G ala CItcIcc a t 12 GHz, VM - LS V .Ig « I t mA.
Package Dimensions
Outline 63 (SOT-363/SC-70)
-HI
1JO (0451)
UQ&Mn
sjoo(Qn>
IJf
niffi
m
V
L -
-U iO ttC fM K )
ajotojtn
W(53TT)
A4 SS(0J 17)
TYP.
1
0.10
r-
040MP.
OF
140
OJO
OJO
1(0410)
0.10(0404)
o js ta o i
OMCNSION* ABE
m
MLUMETBtS (WCHKS)
Part Number Ordering Information
Part Number
ATF-36163-TRim
ATF*36163-BLK
No. of
Devices
3000
100
Container
r Reel
antistatic bag
380
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
HEW LETT*
PACKARD
Device Orientation
TOP VIEW
END v ie w
|4*m '
f» j
f
o
■m
I
©
i
I
e
i
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Tape Dimensions
For Outline 63
<1 (CARRIER TAPE THICKNESS)
\^r^reuuL
n
^*oo c sa w n o N
CAVITY
LENOTH
WQTH
DEFTH
FfTCH
BOTTOM MOLE DIAMETER
PERFORATION
SYMBOL
■B E (sun)
•B E (INCHES)
AS
■*
Ko
9
Oi
2 4 4 * 0 .1 0
2 4 4 * 0 .1 0
1 4 2 * 0.10
4 4 0 * 0 .1 0
1 4 0 * 04*
04 * 0 * 0 4 0 4
0402*0004
0440*0404
0.1*7 * 0 4 0 4
0430*0410
DIAMETER
FfTCH
ROSmON
0
«*o
E
14**04*
4 .0 0 * 0 .1 0
1.75 * 0.10
0401 * 0 4 0 2
0 .1 * 7 * 0 4 0 4
04*0*0004
CARRIER TAPE
WIDTH
THICKNESS
w
»1
040*040
04SS*0413
041**0412
0410*0400*
INSTANCE
CAVITY TO FERFORATION
(WDTH OStECnON]
F
U »*0«
0.1JO * 04 02
408464-8075
0470*0402
F irE u t/A w trelu U : (Bfi) 290-6306
CAVITY TO PERFORATION
(LENGTH M IC T IO N )
Pa
2 4 0 • 0.05
For technical «««i«mw o r the location of
your nearest Hewlett-Packard sales office,
distributor or representative call:
Amerlcaa/Ceaad ' £00-235^1312 or
Japan: (81 3) 33314111
Europe: CaS your local HP sales office
ttsced layear tdspfaene directory. Ask for
a Components reptwemative.
Data tufaiect to ctvante.
381
Copyright C 1996 Hewlett-Packard Co.
Printed Hi U S4.
6964-4068E (1/96)
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
_L) C.\ J ^d
( UV
cO
FUJITSU
MICROWA
FHX15 Series / FHX16 Series
DATA SHF ^
SuperHEMT ™
_________________________________ ^
DESCRIPTION
The FHX15/FHX16 series SuperHEMT™ is intended for applications where low noise
perform ance and high gain are of param ount im portance. This performance is
ach iev ed with a sub quarter-micron g a te length an d InGaAs technology.
The FHX15FA and FHX16FA are recom m ended for hi-rel applications.
FEATURES
Low noise figure
High associated gain
G ate Length
G ate width
Available in chip form
NF
Gas
Lg
Wg
=
<
=
0.55 dB a t 12 GHz (FHX15)
11.5 dB a t 12 GHz
0.25 jim
200 pm
SELECTION TABLE
PART NO
FHX15FA
FHX15LG
NF (typ.)
G a s (typ.)
0.55 dB
0.55 dB
FHX15X
0.55
0.65
0.65
0.65
11.5 dB
11.5 dB
11.5 dB
FHX16FA
FHX16LG
FHX16X
dB
dB
dB
dB
11.5 dB
11.5 dB
11.5 dB
F
FA P a c k a g e
LG P a c k a g e
E dition 1.3 Prelim inary
J a n 1992
382
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
C?
CHIP
FHX15FA/LGX
FHX16FA/LG/X
ABSOLUTE MAXIMUM RATINGS (A m bient Tem perature Ta = 25* C)
Item
Sym bol
Unit
R a tin g
C o n d itio n
D rain S o u rc e V o lta g e
VDS
3.5
V
G a te - S o u r c e V o lta g e
Vq s
-3.0
V
T otal P o w e r D issipation
p to t
180
mW
S to r a g e T e m p e ra tu re
Tstg
-65 t o +175
d e g .C
C h a n n e l T e m p e ra tu re
Tc h
175
deg. C
ELECTRICAL CHARACTERISTICS (A m bient T em perature Ta = 25* C.)
Limit
Item
S ym bol
Unit
Test C o n d itio n s
Min.
Typ.
M ax.
S a tu ra tio n Drain C u rre n t
•d s s
VDS = 2V. VDS = 0V
10
30
60
mA
Tr a n s c o n d u c t a n c e
gm
VDS = 2V. Iq s = 10m A
35
50
-
mS
P in c h -o ff V o lta g e
VP
= 2V - Id s = lm A
-0.1
-0.7
-1.5
V
lG S = 10pA
-3.0
-
-
V
-
0.55
0.65
dB
10.0
11.5
-
dB
-
0.65
0.75
dB
10.0
11.5
-
dB
G a t e S o u rc e
B re a k d o w n V o lta g e
N o ise Figure
v G SO
v ds
NF
FHX15
A s s o c ia te d G a in
G as
N oise R g u re
NF
V d s =2V . <d s = 10m A
f = 12GHz
FHX16
A s s o c ia te d G a in
G as
POWER DERATING CURVE
c
o
a
DRAIN CURRENT vs. DRAIN-SOURCE VOLTAGE
200
40
150
E 30
Vgs = 0 V
-0.2 V
Q
100
O 20
<D
$
o
2o:
-0.4 V
50
o
i—
-0.6 V
.-0.8 V.
50
100
150
200
A m b ie n t T e m p e r a tu r e (C.)
D rain S o u rc e V o lta g e (V)
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
X-BAND
SuperHEMT”
s
NF & G a s vs. Iq 5
NF & G a s VS. FREQUENCY
3
12
f= 12GHz
VDS =2V
Gain(dB)
CO
G as
CD
O 2
©
5
a>
10 -o
Associated
6 2
©
<n
O
NF
NF
0
10
F re q u e n c y (GHz)
NF & G a s vs. TEMPERATURE
— - -^ G a s
15
CD
T>
w
00
*0
0)
w
3
O)
10
1.0
C
o
0
T>
©
O
u_
©
«
O 0.5
2
5
O
f= 12GHz
VDS =2V
Gain M atche d
without RF
Id s = 15mA
E
CD
S 10
©
o
/
3
t
O
y Noise Fig ure M atched
'
Q_
without GF
ids = iom A
5
" ’^ N F ^
0
100
200
300
A m b ie n t T e m p e r a tu r e (K)
30
OUTPUT POWER vs. INPUT POWER
15
f= 12GHz
VDS=2V
' ds =iomv\ —
20
Drain C u rren t (mA)
400
-10
-5
0
In p u t P ow er (dBm)
384
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
FHX15FA/LGX
FHX16FA/LG/X
FHX15FA/LG, 16FA/LG
+j50
N oise P aram eters
v D S =2 v -
lD S = 10m A
,+j250
+jlO
Freq.
(GHz)
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
J250
Topt = 0.57 L
Rn /50 = 0.05
NFmin = 0.55dB
f = 12 GHz
VDS = 2V
Ids = iomA
NFmin
Topt
(MAG) (ANG ) (dB)
0.82
0.79
0.76
0.73
0.71
0.68
0.66
0.63
0.61
0.59
0.57
0.56
0.54
0.52
0.51
0.50
0.49
17.3
36.1
53.2
69.0
83.5
97.0
109.6
121.5
133.0
144.2
155.3
166.5
178.0
-170.0
-157.3
-143.8
-129.2
Ga(max)&IS21(2vs. FREQUENCY
15
G a (max)
5
0
4
6
8 10 12
20
F r e q u e n c y (GHz)
0
385
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
0.33
0.33
0.34
0.3 5
0.37
0.38
0.41
0.44
0.47
0.51
0.5 5
0.59
0.64
0.7 0
0.76
0.82
0 .8 9
Rn/50
0.59
0.50
0.42
0.34
0.28
0.22
0.17
0.13
0.10
0.07
0.05
0.04
0.04 .
0.04
0.06
0.08
0.11
X-BAND
SuperHEMT
FHX15X, 16X
+j50
N o ise Param eters
v DS =2V- *DS -1 0 m A
+jlO
,+j250
Freq.
(GHz)
2
4
6
8
10
12
14
16
18
20
22
-j250
r o p t = 0.59 L 93
Rn/50 =0.19
NFmin = 0.55dB
ro p t
NFmin
(M AG) (ANG) (dB)
0.80
0.75
0.71
0.67
0.63
0.59
0.55
0.52
0.49
0.47
0.44
17
33
48
64
78
93
106
119
131
143
152
0.33
0.34
0.37
0.41
0.47
0.55
0.64
0.75
0.90
1.10
1.32
R n/50
0.62
0.51
0.42
0.32
0.25
0.19
0.15
0.12
0.10
0.09
0.08
f = 12 GHz
VDS = 2V
bs = 10mA
EQUIVALENT CIRCUIT
Ga(max)&IS211 vs. FREQUENCY
06
Gate
J^V W
0 In n
0 7n
=63
QIBof
15
0 8 5 OS 1.
AjSh-^SllSL,11 a
0 InH
62ms
G a(m ax)
'OS 5.29 mS
03
a
c
o
0.8Q
10
CD
5
S21
Note: inductance of 25 nm Au bonding wires is included
0
0 12
20
Number of wires (Length = 0.3 mm)
G ate
2
Drain
2
Source
4
F r e q u e n c y (GHz)
386
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Dtam
FHX15FA/LG/X
FHX16FA/LG/X
FHX15FA/LG, I6FA/LG
+/50
+90*
+j!00
+j25
S 21
GHz
+jl0
,+j250
0.1GHz
100
'250
1 6.1GHz |_
±180*1—
12GHz
S 12
Scale lor i Sj j ■
ODd
20 GHz
S22
-jlO
H250
20 GHz
L12
±25
sn
1.16.
-jlOO
-90“
-j50
S-Parameters
VQg =2V. lQg=10mA
FREQ.
GHz
0.1
0.5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Sll
m ag
1.000
0.998
0.990
0.966
0.930
0.890
0.845
0.803
0.770
0.742
0.714
0.694
0.671
0.645
0.620
0.601
0.583
0.561
0.534
0.498
0.459
0.404
S21
an g
-2.1
-9.5
-19.4
-37.7
-55.6
-72.4
-88.0
-102.5
-116.1
-128.8
-139.8
-150.2
-161.0
-171.9
178.2
167.6
158.2
147.4
136.8
124.8
112.6
101.0
m ag
4.445
4.433
4.386
4.255
4.041
3.829
3.589
3.349
3.131
2.918
2.738
2.603
2.506
2.403
2.315
2.235
2.180
2.163
2.137
2.111
2.105
2.077
ang
177.8
170.6
161.1
143.1
125.7
109.5
98.9
79.3
65.4
51.9
39.6
27.6
15.6
3.4
-8.6
-20.5
-32.3
-44.6
-57.4
-71.2
-86.0
-100.4
S12
m ag
ang
0.002
86.7
0.008
81.9
0.015
77.3
0.030
64.1
0.041
52.8
0.051
41.3
0.057
31.6
0.062
23.2
0.064
15.3
0.065
7.9
0.065
3.0
0.066
-1.8
0.065
-6.0
0.067 -11.8
0.068 -14.8
0.068 -19.7
0.069 -25.4
0.070 -34.8
0.074 -40.2
0.075 -50.5
0.080 -64.7
0.080 -79.0
S22
an g
m ag
-1.7
0.555
-7.9
0.552
0.549
-15.5
0.538
-30.5
0.526
-44.8
0.510
-58.6
0.497
-71.8
0.491
-84.6
-96.4
0.489
0.496 -107.7
0.503 -117.4
0.514 -126.5
0.522 -135.5
0.533 -145.6
0.550 -154.4
0.569 -163.4
0.596 -171.5
0.619 -179.4
0.641
172.5
0.657
163.5
0.662
153.8
0.659
144.8
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
X-BAND
SuperHEMT
FHX15X, 16X
+j250
Scale fo t Sto '
.1
-j250
NOTE: Inductance of 25pm Dia. Au
bonding wires is included
Number of wires (Length = 0.3 mm)
G a te 2
Drain 2
Source 4
S-Parameters
- 2v i d s ==10mA
Freq.
Sll
MHz
m ag
ang
0.1
-0.9
1.000
0.5
0.999
-4.6
1
-9.3
0.995
2
0.981
-18.4
3
-27.4
0.960
4
-36.1
0.932
5
-44.6
0.900
6
-52.6
0.865
7
-60.4
0.829
8
-67.8
0.793
9
0.759
-75.0
10
-81.8
0.726
11
-88.4
0.696
12
-94.8
0.668
13
-101.0
0.642
14
-107.1
0.620
-112.9
15
0.599
16
-118.6
0.581
17
-124.2
0.566
18
-129.6
0.553
19
-134.9
0.542
20
-140.1
0.533
21
0.526
-145.1
22
0.520
-150.0
S12
S21
m ag
4.682
4.676
4.660
4.596
4.496
4.366
4.215
4.052
3.883
3.713
3.547
3.388
3.236
3.093
2.960
2.835
2.719
2.611
2.511
2.418
2.332
2.252
2.177
2.107
ang
179.2
176.0
172.0
164.1
156.4
149.0
141.9
135.2
128.8
122.8
117.2
111.9
106.8
102.1
97.5
93.2
89.1
85.2
81.4
77.7
74.2
70.8
67.5
64.3
m ag
0.001
0.006
0.013
0.025
0.037
0.048
0.058
0.066
0.074
0.081
0.087
0.092
0.096
0.101
0.105
0.108
0.112
0.116
0.120
0.124
0.128
0.133
0.138
0.143
ang
89.6
87.8
85.5
81.2
77.1
73.3
69.8
66.8
64.2
61.9
60.0
58.7
57.6
56.8
56.3
56.1
56.1
56.3
56.6
57.1
57.6
58.2
58.8
59.4
S22
m ag
0.600
0.600
0.598
0.591
0.580
0.566
0.550
0.533
0.515
0.496
0.479
0.462
0.446
0.431
0.417
0.404
0.391
0.380
0.369
0.359
0.349
0.340
0.331
0.323
388
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
ang
-0.5
-2.3
-4.5
-9.0
-13.3
-17.4
-21.1
-24.7
-27.9
-30.9
-33.7
-36.3
-38.7
-41.1
-43.3
-45.6
-47.8
-50.0
-52.2
-54.5
-56.9
-59.4
-62.0
-64.7
0 15 0.2
FHX15FA/LG/X
FHX16FA/LG/X
HANDLING PRECAUTIONS FOR PACKAGED DEVICES
1. Handling
Proper static grounding must b e used on all equipm ent
an d personnel. For example, wrist straps, ta b le mats,
antistatic co ats, etc.
2. Testing
a) All test equipm ent, tools an d personnel must b e
properly g ro u n d e d .
b) A regulated bias supply is recom m ended.
c) The following turn-on procedure should b e observed
to RF test th e HEMT.
1. Apply the g a te voltage a t a b o u t -0.45V.
2. Slowly apply 2 volts to th e drain-source
3. Re-adjust the g a te voltage to obtain the required
drain current.
4. Apply RF drive.
d). The following turn-off procedure should b e observed
after RF test.
1. Remove RF drive.
2. Remove drain voltage.
3. Remove g ate voltage
PACKAGE DIMENSIONS
C ase Style 'FA"Metal-Ceramic Hermetic P ackage
C ase Style "LG"
Metal-Ceramic Hermetic P ackage
1.0 Min.
(0.039)
(0.157 Mm)
O
lO M n
(0039)
se
05
.(0.021
TO 15
1.78
18*0 15
(0.07)
(0.07)
o~ -
li
I t
4 <5=
0(0.004)
1
1.
2.
3.
4.
Gate
Source
Oram
Source
;
t
0 1
(0.004)
1 Gate
2 Source
3 Oran
4 Source
Urnt mm metres)
Unit: m m m e tre s )
389
Reproduced with permission o f the copyright owner. Further reproduction prohibited without permission.
X-BAND
SuperHEMT
ASSEMBLY PRECAUTIONS FOR CHIPS
1. Chip Handling
All operations must b e performed in a clean, dust-free, an d dry environment. Caution must b e exercised to
prevent static build up by proper grounding of all equipm ent a n d personnel.
2. Storage Condition: Store in a clean, dry Nitrogen environment.
3. Die-Attach
3.1 The d ie-attach station must have a c c u ra te tem perature control, and an inert forming gas should b e used
3.2 Chips should b e kept a t room tem perature e x ce p t during die-attach.
3.3 Place p a c k a g e or carrier on th e h e a te d stage.
3.4 Place th e solder preform a t the position w here th e chip will b e bonded.
3.5 Lightly grasp th e chip ed g es using tweezers a n d scrub the die onto the Au-Sn solder preform. The die attach
condifions are: 300 to 310' for 30 to 60 seconds. The Au-Sn (80-20) solder preform volume should b e
a b o u t 4 x 10"3 mm^ .
4. Wire Bonding.
4.1 Bonding Condition
The bo n d er must b e property grounded. Wire bonding should b e performed with a thermal compression
bonder using 0.7 to 1.0 mil diam eter half hard. 3-8% elongation Gold wire.
4.2 Wire Layout
The wire bonding should b e performed as shown in th e following example.
CHIP OUTLINE
* 4 4 — -------------- 9 6
BONDING WIRE LAYOUT
(Unit iitn)
*
Die thickness
450? 20
100 ♦20um
390
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Appendix F
Sample Test Data from Devices Used in this Study
391
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Vgs=-0.5
-2.82E-06
0.000151
0.000229
0.000283
0.000334
0.000385
0.000441
0.000498
0.00056
0.00062
0.000683
0.000744
0.000803
0.000859
0.000912
0.000963
0.001014
0.001062
0.001109
0.001092
0.00116
0.001219
0.001271
0.001321
0.00137
0.001418
0.001465
0.001521
0.001577
0.001653
0.001742
0.001853
0.001973
0.002105
0.002233
0.002353
0.002472
0.002585
0.002689
0.002789
0.002889
0.002991
0.003098
0.003207
0.00332
0.003434
0.003552
0.003674
0.003796
0.003921
CO
Vgs=-0.4
-8.97E-06
0.000701
0.001119
0.001344
0.001555
0.00174
0.00192
0.002095
0.002269
0.002435
0.002599
0.00275
0.002893
0.003022
0.003147
0.003264
0.003375
0.003477
0.003572
0.003674
0.003763
0.003853
0.003939
0.004028
0.004114
0.004198
0.004288
0.00439
0.0045
0.00464
0.004813
0.00502
0.005242
0.005455
0.005657
0.005847
0.006026
0.006195
0.006346
0.006498
0.006646
0.006805
0.006962
0.007119
0.007279
0.007437
0.0076
0.007758
0.007923
0.008086
1
-1.44E-05
0.001529
0.002667
0.003441
0.003991
0.004407
0.004768
0.005093
0.0054
0.005688
0.005959
0.006209
0.006439
0.006649
0.006843
0.007017
0.007184
0.007346
0.007491
0.007631
0.007764
0.007897
0.008016
0.008139
0.008256
0.008378
0.008494
0.008626
0.008768
0.008943
0.009152
0.009411
0.009687
0.009964
0.010221
0.010469
0.010692
0.010911
0.011103
0.011283
0.011432
0.011637
0.011829
0.012018
0.012206
0.012389
0.012577
0.012758
0.012943
0.013126
</>
£
CO
IV Data for PHEMT (11/13/96)
Vgs=0
Vgs—0.1 Vgs=-0.2
-2.20E-05 -1.80E-05 -1.74E-05
0.00302 0.002717 0.002235
0.005926 0.005235 0.004158
0.008597 0.007435 0.005678
0.011074 0.009341 0.006862
0.013216 0.01088 0.007737
0.015121 0.01208 0.008423
0.016693 0.013072 0.008977
0.018007 0.013882 0.009467
0.019057 0.01454 0.009897
0.019927 0.015114 0.010294
0.020636 0.015596 0.010646
0.021237 0.016027 0.010972
0.02174 0.016405 0.011253
0.022176 0.016755 0.011384
0.022564 0.017051 0.011673
0.022902 0.017329 0.011924
0.02321 0.017586 0.01215
0.023491 0.017821 0.012346
0.023748 0.018038 0.012538
0.023984 0.018234 0.012711
0.024211 0.018429 0.012877
0.0186 0.013032
0.024416
0.024613 0.018784 0.013188
0.024792 0.018949 0.013332
0.02497 0.019112 0.013472
0.025143 0.01927 0.013615
0.02531 0.019429 0.013767
0.025466 0.019587 0.013916
0.025641 0.019762 0.014094
0.025815 0.019951 0.014309
0.026021 0.020186 0.014565
0.026248 0.020452 0.014854
0.026519 0.020758 0.015171
0.026816 0.021076 0.015468
0.027138 0.021385 0.015753
0.027451 0.021677 0.016011
0.027751 0.02196 0.016261
0.028033 0.022215 0.016491
0.028297 0.02246 0.016703
0.028541 0.022639 0.016897
0.028752 0.022714 0.017094
0.02882 0.022801 0.017285
0.028883 0.022906 0.017413
0.028957 0.023028 0.017535
0.029045 0.023162 0.017674
0.029151 0.023323 0.017835
0.029277 0.023511 0.01802
0.029423 0.02372 0.018233
0.029598 0.023963 0.018479
I
S
’
Measured
Vds
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.55
0.6
0.65
0.7
0.75
0.8
0.85
0.9
0.95
1
1.05
1.1
1.15
1.2
1.25
1.3
1.35
1.4
1.45
1.5
1.55
1.6
1.65
1.7
1.75
1.8
1.85
1.9
1.95
2
2.05
2.1
2.15
2.2
2.25
2.3
2.35
2.4
2.45
-1.10E-06
1.54E-05
2.35E-05
2.99E-05
3.65E-05
4.37E-05
5.18E-05
6.09E-05
7.10E-05
8.18E-05
9.36E-05
0.000105
0.000108
0.000123
0.000137
0.000149
0.000163
0.000175
0.000187
0.000199
0.000211
0.000223
0.000236
0.000248
0.000261
0.000274
0.000287
0.000301
0.000316
0.000334
0.000354
0.00038
0.000411
0.000448
0.000491
0.000535
0.000581
0.000627
0.000673
0.000718
0.000764
0.000811
0.000854
0.0009
0.000951
0.001001
0.001057
0.001114
0.00117
0.001237
392
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Vgs=-0.7
-6.38E-07
-2.00E-07
5.96E-07
1.54E-06
2.15E-06
2.81 E-06
3.56E-06
4.31 E-06
5.17E-06
6.07E-06
7.01 E-06
7.93E-06
8.88E-06
9.85E-06
1.09E-05
1.26E-05
1.43E-05
1.61 E-05
1.78E-05
1.95E-05
2.13E-05
2.31 E-05
2.49E-05
2.68E-05
2.86 E-05
3.06E-05
3.26E-05
3.47E-05
3.67E-05
3.92E-05
4.18E-05
4.46E-05
4.77E-05
5.14E-05
5.59E-05
6.14E-05
6.77E-05
7.52E-05
8.31 E-05
9.21 E-05
0.000101
0.000111
0.000118
0.00013
0.000142
0.000154
0.000167
0.000181
0.000195
0.000211
2.5
2.55
2.6
2.65
2.7
2.75
2.8
2.85
2.9
2.95
3
0.029802
0.030029
0.030299
0.030607
0.030954
0.03132
0.031697
0.032059
0.032413
0.032756
0.0331
0.024243
0.024559
0.024911
0.025289
0.025696
0.026102
0.026513
0.026901
0.027283
0.027654
0.028027
0.018753
0.019063
0.019405
0.01978
0.020183
0.020592
0.02102
0.021447
0.021868
0.022274
0.022674
0.01331
0.013492
0.013672
0.013845
0.014072
0.014341
0.014663
0.015016
0.015401
0.015807
0.016234
0.008253
0.008421
0.008596
0.008768
0.00895
0.00913
0.00932
0.009511
0.009711
0.009916
0.010133
0.00405
0.004183
0.004321
0.004464
0.004612
0.004763
0.004928
0.005091
0.00527
0.005448
0.005643
0.001307
0.001381
0.001458
0.00154
0.001627
0.00172
0.001821
0.001925
0.002039
0.002162
0.002294
393
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
0.000227
0.000246
0.000267
0.00029
0.000316
0.000344
0.000376
0.000411
0.000451
0.000495
0.000545
Typical transconductance (mA/V) o f HP/Avantek ATF36163 PHEMT transistor
Vds
0
0.2
0.6
1
1.4
1.8
2.2
2.6
3
3.4
3.8
4
Vgs=0 v Vgs=-0.l Vgs—0.2 Vgs=-0.3 Vgs—0.4
-9.79E06
30.3
49.6
53.8
57.9
62.1
66.2
70.2
74.3
78.3
82.4
84.4
V
V
V
V
-2.05E07
28
45.1
48.9
52.6
56.4
60.1
63.9
67.6
712
74.9
76.7
-4.40E09
24.6
38.9
42.2
45.5
48.8
52
55.3
58.5
61.7
64.9
66.5
-2.00E09
19.4
30.4
33
35.6
38.2
40.7
43.3
45.8
48.4
50.9
52.1
-2.00E09
11.7
18.2
19.7
21.3
22.9
24.4
25.9
27.5
29
30.5
31.3
Typical output conductance (mA/V) of HP/Avantek ATF-36163
PHEMT transistor
Vgs—0.5 Vgs—0.4 Vgs—0.3 Vgs—0.2 Vgs—0.1 Vgs==0
28.7
6.7
16.4
42.7
57.8
0.856
2.05
3.69
7.99
0.823
0.105
5.68
1.09
1.91
0.464
3.9
2.86
0.0575
1.09
1.91
3.89
0.057
0.446
2.85
1.9
1.09
3.87
0.445
2.84
0.0575
1.89
0.444
1.08
22
2.83
3.85
0.0575
1.89
3.84
0.443
1.08
2.82
2.6 0.0575
1.07
1.88
0.442
2.8
3.83
3 0.0575
1.07
1.87
0.441
2.79
3.81
3.4 0.0575
1.07
1.87
0.44
3.79
0.057
2.78
3.8
1.07
0.44
1.86
4 0.0575
2.78
3.78
0.2
0.6
1
1.4
1.8
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Meaured IV Curves o f FHX35LG HEMT transistor
Vds
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
Vgs=0 Vgs=-0.2 Vgs=-0.4 Vgs=-0.6
1.02E-03 1.44E-01 6.21E-02 1.98E-02
11.61
5.26 5.49E-01 2.84E-02
72
8.80E-01 3.72E-02
18.09
8.56
1.23 5.01E-02
20.95
9.7
1.63 6.88E-02
22.61
10.7
2.05 9.37E-02
23.9
2.49
25.04
11.6
I22E-01
12.54
2.97
1.69E-01
26.09
13.42
3.46 2.28E-01
27.08
1429
3.99 3.04E-01
28.03
28.94
15.13
4.53 4.02E-01
15.94
29.82
5.11
524E-01
16.74
5.7
30.66
6.77E-01
31.49
17.53
6.32 8.64E-01
18.32
6.96
1.091
32.28
19.12
33.07
7.63
1.32
Typical transconductance (mA/V) of FHX35LG
transistor
Vds
0
0.4
0.8
1.2
1.6
2
2.4
2.8
3
Vgs=0 Vgs=-02 Vgs=-0.4 Vgs=-0.6
0.407
02116 3.82E-31
-0.713
54.47
31.58
4218 1.00E-02
64.59
40.3
7.826
0.253
67.19
45.5
11.86
1.106
49.8
16.17
68.3
2.905
69
5.944
53
20.66
55.2
25.1
10.4
69.6
56.8
29.3
16.18
69.8
57.4
31.5
19.4
69.8
Typical output conductance (mA/V) of FHX35LG
transistor
Vds
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
Vgs=0 Vgs=-02 Vgs=-0.4 Vgs=-0.6
2.44 427E-02
58
25.6
9.67
32.4
1.66 4.41E-02
1.74 6.46E-02
14.2
6.81
5.67
2.02 9.35E-02
8.36
5.04
2.09
1.24E-01
6.42
4.49
5.7
2.21
1.43E-01
4.7
2.36 2.33E-01
528
4.42
2.49 2.98E-01
4.95
4.33
2.61
3.79E-01
4.73
4.19
2.75 4.89E-01
4.54
395
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
2.2
2.4
2.6
2.8
3
4.39
423
4.11
4
3.95
4.07
4
3.95
3.96
3.95
2.85
2.97
3.08
3.2
3.36
7.02E-01
6.73E-01
9.38E-01
1.13
1.15
396
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Appendix G
Listing of Publications
397
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
L ist of Publications
1)
D. G. Thomas, Jr. and G. R. Branner, "A New Technique For Optimizing ModeStirred Chamber Efficiency," 1995 IEEE International Symposium on Electromagnetic
Compatibility, pp. 374-377,1995.
2)
D. G. Thomas, Jr. and G. R. Branner, "Design of Low-Noise RF/Microwave
Amplifiers For Communication Systems Requiring Very Low Power Consumption,"
1995 Midwest Symposium on Circuits and Systems, Vol. 2, pp. 1007-1010, 1995.
3)
D. G. Thomas, Jr. and G. R. Branner, "Single-Ended HEMT RF/Microwave
Frequency Doubler Design Using Refllector Networks," 1995 Midwest Symposium on
Circuits and Systems, Vol. 2, pp. 1014-1017, 1995.
4)
B. P. Kumar, D. G. Thomas, Jr. and G. R. Branner, "A Reduced Size Planar
Baiun Structure For Wireless Microwave and RF Applications," 1995 Midwest
Symposium on Circuits and Systems, Vol. 1, pp. 526-529, 1995.
5)
B. P. Kumar, D. G. Thomas, Jr. and G. R. Branner, "Design of Microstrip T
Junction Power Divider Circuits For Enhanced Performance," 1995 Midwest Symposium
on Circuits and Systems, Vol. 2, pp. 1213-1215, 1995.
6)
D. G. Thomas, Jr. and G. R. Branner, "Optimization o f Active Microwave
Frequency Multiplier Performance Utilizing Harmonic Terminating Impedances," 1996
IEEE MTT-S International Microwave Symposium Digest, Vol. 2, pp. 659-662, 1996.
7)
D. G. Thomas, Jr. and G. R. Branner, "New Techniques For Reflector Network
Design In Single-Ended HEMT RF/Microwave Frequency Multipliers," 1996 Midwest
Symposium on Circuits and Systems, pp. 1359-1362, 1996.
8)
D. G. Thomas, Jr. and G. R. Branner, "Analysis o f Harmonic Termination
Impedance On RF/Microwave Multiplier Efficiency," 1996 Midwest Symposium on
Circuits and Systems, pp. 1343-1346, 1996.
9)
D. G. Thomas, Jr. and G. R. Branner, "Accuracy o f Residual Phase Noise
Characterization of Active RF/Microwave Devices," 1996 Midwest Symposium on
Circuits and Systems, pp.1371-1374, 1996.
398
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
10)
D. G. Thomas. Jr. and G. R. Branner. "Nonlinear Properties of PHEMT
Transistors Exploited in the Design o f Active RF/Microwave Frequency Multipliers."
1996 Midwest Symposium on Circuits and Systems, pp.245-248, 1996.
11)
A. Ching, D. G. Thomas, Jr. and G. R. Branner, "Reduced-Size Low Noise Low
Power Consumption Amplifier Designs For Communications and RF Applications."
1996 Midwest Symposium on Circuits and Systems, pp. 1379-1382, 1996.
12)
D. G. Thomas, Jr. and G. R. Branner, "Optimization o f Active Microwave
Frequency Multiplier Performance Utilizing Harmonic Terminating Impedances," 1996
IEEE Transactions on Microwave Theory and Techniques, Vol. 44, No. 12, pp.26172624, December 1996.
13)
D. G. Thomas, Jr., G. R. Branner, and P. B. Kumar, “Synthesis of networks for
optimum microwave multiplying applications,” 6th International Symposium on Recent
Advances in Microwave Technology Proceedings, pp. 611-614, Beijing, China. 1997.
14)
D. G. Thomas, Jr., G. R. Branner, “A unified technique for efficient active
microwave multiplier design,” 1997 Midwest Symposium on Circuits and Systems, pp.
116-119, 1997.
15)
D. G. Thomas, Jr., G. R. Branner, and B. Huang, “Improved Precision PHEMT
Models,” 1998 Midwest Symposium on Circuits and Systems.
16)
D. G. Thomas, Jr., G. R. Branner, and P. B. Kumar, “Microwave and Radio
Frequency Multipliers”, Encyclopedia o f Electrical and Electronics Engineering 1999.
(Accepted for publication).
17)
D. G. Thomas, Jr. and G. R. Branner, "Single-Ended HEMT Multiplier Design
Using Reflector Networks," IEEE Transactions on Microwave Theory and Techniques.
(Submitted for publication).
18) D. G. Thomas, Jr. and G. R. Branner, Low Power Device Research, University of
California, Davis, July 1994.
19)
S. O. Ojha, D. G. Thomas, Jr. and G. R. Branner, Low Power Transistor
Characterization, University o f California, Davis, November 1994.
20)
A. Ching, D. G. Thomas, Jr. and G. R. Branner, Low Power RF Electronics Part
1: Low Noise-Low Power Consumption Amplifier Design, University of California,
Davis, March 1995.
21)
A. Ching, D. G. Thomas, Jr. and G. R. Branner, Low Power RF Electronics Part
2: Low Noise-Low Power Consumption Amplifier Design - Miniaturized Lumped
Realization, University of California, Davis, August 1995.
399
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
22)
D. G. Thomas. Jr. and G. R. Branner, Residual Phase Noise Transistor
Characterization. University of California, Davis. January 1996.
400
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