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High -efficiency shared -current microwave power amplifier design

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University o f N evada, Reno
High-Efliciency Shared-Current Microwave Power Amplifier Design
A dissertation subm itted in partial fulfillment o f the requirements for the degree o f
D octor o f Philosophy in Electrical Engineering
By
Barry A. Lautzenhiser
Dr. Bruce Johnson / D issertation Advisor
August 2002
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UMI Number: 3068525
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UNIVERSITY
OF NEVADA
THE GRADUATE SCHOOL
RENO
We recommend that the dissertation
prepared under our supervision by
Barry Lautzenhiser
entitled
High-EfViciency Shared-Current Microwave Power
Amplifier Design
be accepted in partial fulfillment o f the
requirements for the degree of
DOCTOR OF PHILOSOPHY
ClJZ—
Brucd Johnson, P h.D ., Advisor
9v\.JLortK._____________ _________________
Jndira Chatterjee, Ph.D. , Committee Member
ohn KTepperPlf D ., Committee Member
Jim Hensen, P m D ., Committee Member
C.
Ronald Phaneuf, P h -& , At-Large Member
'
f
A /
----------------Marsha H. Read, Ph. D., Associate Dean, Graduate School
August, 2002
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A C K N O W LED G EM EN T
I w ould like to express my sincere appreciation and gratitude to m y advisor, Dr.
Bruce Johnson, for his excellent guidance and constant support during m y course o f
studies at the University o f Nevada, Reno. His continued encouragem ent and reassurance
have been invaluable during m y M aster o f Science and Doctor o f Philosophy studies, and
I truly look forward to continuing our relationship into the future.
I w ould also like to thank Dr. Indira C hatteijee, Dr. John Kleppe, Dr. Jim Hensen,
and Dr. Ron Phaneuf, members o f m y doctoral com m ittee, for their tim e and interest in
m y work. A special thanks to Dr. Indira C hatteijee for her teaching excellence and for
furthering m y interest in microwave engineering.
The project support from Em hiser Research, Inc. and the assistance o f all their
technicians and engineers is greatly appreciated. I would like to express m y thanks to my
uncles, Em hiser Research President Lloyd Lautzenhiser and M agitek.com founder John
Lautzenhiser, for their continual guidance and support and for the w onderful
opportunities they have given me.
I w ish to express my heartfelt appreciation to m y grandparents, to my parents
Gary and Leona, and to m y brothers and sisters for their constant love, encouragement,
and support during the course o f m y education. Finally, I wish to express my sincere
gratitude to m y wonderful wife Katie w hose endless love and deep friendship I will
treasure forever.
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A BSTRA C T
The objective o f this dissertation is to develop a new m icrowave p o w er am plifier
design using Gallium Arsenide Field Effect Transistors (GaAsFETs) to achieve
previously unattainable direct current (DC) to radio frequency (RF) conversion efficiency
while overcom ing GaAsFET bias limitations.
The pow er amplifier requires the m ajority o f available pow er in an y
com m unications system. Improving the efficiency o f the pow er am plifier results in many
advantages, from reduced heat sink size to sm aller, lighter batteries for airborne
applications. Before designing the new high efficiency pow er am plifier, com m on
am plifier term s and performance parameters are defined.
The m ost important step in designing a p o w er am plifier is selecting the correct
pow er transistor for the particular application. T h e m ost com m on m odem devices and
technologies are discussed, and a large signal m odel is simulated. W hen designing a
m icrowave circuit, component nonlinearities m ust be taken into account for optimal
performance. Detailed capacitor, inductor, and resistor m odels are presented and their
circuits sim ulated. M icrowave printed circuit board (PC B) effects and PC B parasitic
capacitances and inductances are also discussed.
A com plete high-efficiency shared-current m icrow ave pow er am plifier design is
developed for a military airborne application. T he DC bias network, decoupling
capacitor network, impedance matching networks, pow er splitter, pow er com biner, and
m ounting system are designed. The com plete design is simulated, fabricated, and tested
according to perform ance requirements, and a com parison between design param eters
and experim ental results is presented.
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TABLE OF CONTENTS
Acknow ledgem ent.......................................................................................................................... i
Abstract............................................................................................................................................ ii
Table o f C ontents.........................................................................................................................Hi
List o f Figures............................................................................................................................. viii
List o f T ab les................................................................................................................................. xi
Chapter I. In tr o d u ctio n ............................................................................................................ 1
1.1 Overview o f Pow er A m plifiers................................................................................1
1.2 Power A m plifier Term s and Definitions............................................................... 2
1.2.1
Pow er C om pression............................................................................... 2
1.2.2
G ain ............................................................................................................3
1.2.3
E fficiency................................................................................................. 5
1.2.4
B andw idth................................................................................................ 5
1.2.5
S-Param eters and Transistor Im pedance........................................... 6
1.2.5.1
Small Signal S-Param eters................................................. 6
1.2.5.2
Large Signal Im p ed an ce.....................................................7
1.2.6
S tab ility ................................................................................................... 10
1.2.7
Im pedance M atching........................................................................ ,. 11
1.2.8
DC Bias and C lasses.............................................................................13
1.2.9 L inearity..................................................................................................14
1.2.10 V S W R ......................................................................................................16
1.2.11 Pow er Splitters and C om biners.......................................................... 17
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iv
1.2.11.1
2-W ay and 2n-W ay........................................................... 18
1.2.11.2 n-W ay.................................................................................. 20
1.2.12 Thermal R esistance and Junction T em perature......................... 21
C hapter II. M icrowave Power T ransistors......................................................................24
2.1 Bipolar Junction Transistors (B JT s)................................................................... 24
2.1.1
Silicon BJTs (S iB JT s)........................................................................24
2.1.2
Silicon G erm anium Heterojunction BJTs (SiG eH B T s).............. 25
2.2 M O SFET s................................................................................................................. 26
2.2.1
Basic M O S F E T s................................................................................. 26
2.2.2
LD M O SFETs.......................................................................................27
2.3 Gallium Arsenide FETs (G aA sF E T s).................................................................28
2.3.1
M etal-Sem iconductor FETs (M E S F E T s)..................................... 30
2.3.2
Double-H eterojunction PHEM Ts (D H -P H E M T s)..................... 31
C hapter III. Microwave C om ponent M o d elin g ............................................................. 33
3.1
Resistor M o d elin g ...............................................................................................33
3.2
Inductor M odeling...............................................................................................36
3.3
Capacitor M odeling............................................................................................ 38
3.4
GaAsFET M o d elin g ........................................................................................... 42
3.5
3.4.1
Linear Small-Signal G aA sFET M odel.................................................. 43
3.4.2
Nonlinear Large-Signal G aA sFET M odels..........................................44
3.4.3
Package M o d e ls ......................................................................................... 49
Printed Circuit Board E ffe c ts........................................................................... 50
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V
Chapter IV. High-Efficiency Shared-Current M icrowave PA D e s ig n ................... 56
4.1
Design Specifications...........................................................................................57
4.1.1 Transistor Selection and PA T o p o lo g y ...................................................58
4.2
DC Bias Network D esig n ....................................................................................62
4.2.1 Transistor Bias P o in t...................................................................................62
4.2.2 Transistor Self-Biasing............................................................................... 63
4.2.3 Tum-On Time Issues...................................................................................71
4.3
Decoupling Network D esig n .............................................................................. 72
4.3.1
Capacitor Series Selection..........................................................................73
4.3.2 Broadband Decoupling D esig n ................................................................ 74
4.3.3 ESR M inim ization....................................................................................... 75
4.3.4 Decoupling Capacitor V alu es...................................................................76
4.4
Choke D esig n .........................................................................................................80
4.4.1 Quarter-W ave Transform er C h o k es........................................................ 81
4.4.2 Inductor C h o k es...........................................................................................82
4.5
Impedance M atching N etw o rk...........................................................................85
4.5.1
Stability A n aly sis........................................................................................ 85
4.5.2 Nonlinear Large Signal Transistor M o d e l.............................................86
4.5.3 Impedance M atching Network T o p o lo g y .............................................. 88
4.5.4 Optimized Impedance M atching N etw ork.............................................89
4.6
Power Splitter & C om biner D esign...................................................................96
4.6.1
Power Splitter T o p ology............................................................................ 97
4.6.2 Termination S election...............................................................................100
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vi
4.6.3
4.7
4.8
Sim ulated & Optim ized Power S plitter & C o m b in e r......................101
Transistor M o u n tin g .......................................................................................... 106
4.7.1
DC Isolated M ounting S tructure........................................................... 106
4.7.2
Total Therm al Resistance........................................................................108
4.7.3
M axim um Junction T em perature..........................................................109
Printed C ircuit Board D esig n .......................................................................... 110
4.8.1
C om ponent Layout................................................................................... 110
4.8.2
M icrostrip Layout......................................................................................111
4.8.3
Via D esign.................................................................................................. 113
4.8.4
C om plete PCB L ay o u t............................................................................ 113
C hap ter V. Experim ental R esults...................................................................................... 117
5.1
Preliminary T ests................................................................................................ 117
5.1.1
Pow er S plitter............................................................................................ 117
5.1.2
Pow er C o m b in e r.......................................................................................120
5.1.3
Single-Stage P A ........................................................................................122
5.1.4 Shared-Current PA T u n in g .....................................................................128
5.2
Perform ance T e s ts .............................................................................................. 129
5.2.1
DC B ia s ....................................................................................................... 129
5.2.2 O utput P o w e r.............................................................................................131
5.2.3 G a in .............................................................................................................. 133
5.2.4 E fficien cy....................................................................................................133
5.2.5
V S W R ......................................................................................................... 134
5.2.6 H arm onic and Spurious E m issio n s.......................................................135
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5.2.7
B an d w id th ................................................................................................. 135
5.2.8
S ize and W eight....................................................................................... 135
5.2.9
Environm ental Extrem es........................................................................ 136
5.2.9.1 Temperature E xtrem es....................................................................136
5.2.9.2 V ibration............................................................................................138
C hapter VI. C onclu sion s and Future W o rk .................................................................. 140
6.1 C o n clu sio n s.......................................................................................................... 140
6.1.1
Com parison Between T est Results and D esign Specifications
140
6.1.2
C om parison with M odem Performance S ta n d a rd s..........................142
6.1.3
A pplications o f High-Efficiency PAs and T ran sm itters.................146
6.2 Future W o rk.......................................................................................................... 147
6.2.1
D C Bias N etw ork..................................................................................... 147
6.2.2
P o w er Splitter/Com biner........................................................................ 148
6.2.3
Im pedance Matching N etw o rk ..............................................................149
6.2.4
W id er Bandwidth D e sig n s.....................................................................150
6.2.5
H igher Power Designs............................................................................. 151
6.2.6
T elem etry Transmitter D e sig n ..............................................................152
6.2.7
O th er Power Amplifier and Telemetry T ransm itter D esigns
154
R eferences................................................................................................................................... 155
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viii
LIST OF FIGURES
Figure 1.1
Pow er Com pression o f M icrow ave Pow er Transistors.
Figure 1.2
Load-Pull M easurement Test Equipm ent Set-Up.
Figure 1.3
T hird-O rder Intercept Point o f M icrowave Pow er Transistors.
Figure 1.4
4-W ay H ybrid Coupler Pow er Splitter / Combiner.
Figure 2.1
G aA sFET Gate Current vs. Input Pow er Level.
Figure 3.1
M icrow ave Circuit Model o f a Chip Resistor.
Figure 3.2
M icrow ave Circuit Model o f a Chip Inductor.
Figure 3.3
D istributed Capacitance and Series Resistance o f an Inductor.
Figure 3.4
M icrow ave Circuit Model o f a Chip Capacitor.
Figure 3.5
Effect o f Parallel Capacitors on Impedance.
Figure 3.6
G aA sFET Small Signal Equivalent Circuit Model.
Figure 3.7
G aA sFET Curtice-Ettenburg Nonlinear Circuit Model.
Figure 3.8
G aA sFET Package Equivalent Circuit Model.
Figure 3.9
PCB Trace Cross-Sectional A rea and Current Capacity.
Figure 4.1
Basic Shared-Current M icrow ave PA U tilizing GaAsFETs.
Figure 4.2
M easured Drain Current vs. G ate-Source Voltage.
Figure 4.3
Im pedance o f Parallel Capacitors w ith D ifferent Resonant Frequencies.
Figure 4.4
Sim ulated Impedance o f G aA sFET M icrow ave Decoupling Network.
Figure 4.5
Sim ulated Impedance o f Pow er Supply M icrow ave Decoupling Network.
Figure 4.6
Vertical Chip Capacitor Orientation.
Figure 4.7
Sim ulated Impedance o f a Self-Resonant Inductor.
Figure 4.8
Sim ulated Impedance o f G ate Choke.
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Figure 4.9
180-mil F langed Package Model.
Figure 4.10
Simulated L oad-P ull Contours for EPA720A-180F.
Figure 4.11
O ptimized EPA 720A -180F Impedance M atching Networks.
Figure 4.12
O ptimized EPA 720A -180F Pout & Gain vs. Pm Curve at 4.4 GHz.
Figure 4.13
O ptimized EPA 720A -180F Harmonic Plot at 4.4 GHz.
Figure 4.14
O ptimized EPA 720A -180F Pout & Gain vs. Pj„ C urve at 4.65 G H z.
Figure 4.15
Optimized EPA 720A -180F Harmonic Plot at 4.65 GHz.
Figure 4.16
Optimized EPA 720A -180F Pout & Gain vs. Pj„ Curve at 4.9 GHz.
Figure 4.17
Optimized E PA 720A -180F Harmonic Plot at 4.9 GHz.
Figure 4.18
5-W ay Fork H ybrid Power Splitter.
Figure 4.19
Optimized S im ulations Results for Two-Stage 3-W ay Fork Splitter.
Figure 4.20
Optimized T w o-S tage 3-W ay Fork Splitter Schem atic.
Figure 4.21
Optimized S im ulations Results for Single-Stage 3-W ay Fork Splitter.
Figure 4.22
Optimized S ingle-Stage 3-W ay Fork Splitter Schematic.
Figure 4.23
180-mil F langed Package Outline Drawing.
Figure 4.24
Isolated T ran sisto r M ounting Structure.
Figure 4.25
Relative H eights o f M ounting Structure.
Figure 4.26
H igh-Efficiency Shared-Current Microwave PA PCB Layout.
Figure 4.27
High-EfTiciency Shared-Current Microwave PA Schematic.
Figure 4.28
H igh-Efficiency Shared-Current Microwave PA Parts List.
Figure 4.29
H igh-Efficiency Shared-Current Microwave PA Brass Carrier.
Figure 5.1
Revised Shared-C urrent 4.5 - 4.8 GHz PA PCB Layout.
Figure 5.2
Revised Shared-C urrent 4.5 - 4.8 GHz PA Schem atic.
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X
Figure 5.3
Revised Shared-Current 4.5 - 4.8 GHz PA Parts List.
Figure 5.4
PA O utput Power vs. Frequency.
Figure 6 .1
Current Draw o f U H E and Conventional Transmitters.
Figure 6.2
Dissipated Power o f UHE and Conventional Transm itters.
Figure 6.3
Efficiency o f UHE and Conventional Transmitters.
Figure 6.4
Package Size o f U HE and Conventional Transmitters.
Figure 6.5
W eight o f UHE and Conventional Transmitters.
Figure 6.6
UHE Telem etry T ransm itter Block Diagram.
Figure 6.7
UHE Telem etry T ransm itter Package.
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LIST OF TABLES
Table 1.1
Transistor S-Parameters.
Table 3.1
Chip Resistor M axim um Pow er Dissipations and Tem peratures.
Table 3.2
Curtice-Ettenburg G aA sFET M odel Parameters.
Table 3.3
PCB Copper C ladding and Trace Thickness.
Table 4.1
Small Signal S-Parameters for EPA720A-180F.
Table 4.2
K.-A Stability Calculations for EPA720A-180F.
Table 4.3
Curtice-Ettenburg EPA 720A-180F M odel Parameters.
Table 4.4
Summary o f Impedance M atching Network Simulations.
Table 4.5
3-W ay Fork Hybrid Term ination Resistances and Power Ratings.
Table 4.6
Standard Resistor Sizes and Pad Layouts.
Table 5.1
Preliminary Power Splitter Test Results.
Table 5.2
Preliminary Power C om biner Test Results.
Table 5.3
Preliminary Single-Stage PA Test Results.
Table 5.4
Shared-Current PA Design M odifications.
Table 5.5
DC Bias M easurements w ith M icrow ave Signal Applied.
Table 5.6
Q -Point Shift o f Self-Biased Devices.
Table 5.7
Shared-Current PA G ain R elative to Frequency with 32 dB m Pm.
Table 5.8
Shared-Current PA Efficiency and Power-Added Efficiency.
Table 5.9
Power Dissipation and Junction Tem peratures o f Shared-Current PA.
Table 5.10
Shared-Current PA Input and Output VSW R.
Table 5.11
Shared-Current PA H arm onic and Spurious Emissions.
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Table 5.12
Shared-C urrent PA Low Tem perature Test Results
Table 5.13
Shared-C urrent PA High Tem perature Test Results
Table 6.1
Sum m ary o f Shared-Current PA Specifications and Test Results.
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1
CHAPTER 1
Introduction
1.1 Overview o f P ow er Amplifiers
The focus o f this research is to develop a high-efficiency, shared-current
microwave pow er am plifier (PA) to achieve previously unattainable DC to RF
conversion efficiency w hile overcom ing Gallium Arsenide Field Effect Transistor
(GaAsFET) bias lim itations. GaAsFETs are the prim ary solid-state devices for
amplification o f signals above 3 GHz. However, the maximum bias voltage, typically +8
V to +10 V drain-to-source, limits the use o f GaAsFETs in higher voltage applications,
such as airborne am plifiers and transm itters which typically operate at +28 V ± 4 V.
In the m ost basic sense, a m icrow ave pow er am plifier uses energy supplied from a
source, usually a D C source, to increase the pow er o f an input microwave signal to a
desired level. Since an am plifier increases signal power and is always less than 100%
efficient, the pow er required from the source is often very high. The PA requires the
m ajority o f available source power in any com munications system. Im proving the PA
efficiency results in less current draw from a supply, and therefore less dissipated pow er
in the amplifier. R educing current draw results in smaller, lighter batteries for airborne
applications making better com m unications possible, and reducing the dissipated pow er
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2
results in sim pler and smaller heat sink designs. Improving PA efficiency has many
advantages for systems designers.
The general design procedure for microwave PAs is identifying all performance
requirem ents, selecting the best suited transistor, performing a stability analysis on the
transistor, calculating the expected ju n ctio n temperature, m atching source and load
im pedances, designing the DC bias circuit, and if necessary, selecting topologies and
designing pow er splitters and com biners. Before discussing the new shared-current highefficiency m icrow ave PA design, com m on amplifier terms and perform ance parameters
are defined.
1.2 Power A m plifier Terms and Definitions
The objective o f this section is to identify and define the most com m on terms
associated w ith PA design.
1.2.1
Pow er Compression
Pow er compression is the decrease o f transistor output pow er from the linear
input-output curve as shown in Figure 1.1 [1].
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3
P \ (referred to o utput)
1dB
1dB com pression
point
-10
-20 i—
-30
-20
-10
0
10
20
(dBm)
Figure 1.1 Pow er C om pression o f Microwave Power T ransistors.
The curve has a slope o f 1 through the linear operating region o f the transistor but rolls
o ff or com presses as the transistor saturates due to being biased w ith lim ited pow er
supply voltage as the output pow er o f the transistor is increased. The point at which the
output pow er decreases by 1 dB from the ideal characteristic is defined as the I dB
com pression point P ub , and is typically expressed in terms o f output pow er for PAs.
1.2.2
Gain
Gain is the measure o f signal pow er increase from the input port to the output port
o f the PA. The equation is sim ply the PA output power divided by the PA input power.
G = Pout/Pin
(I)
G is often referred to as the sm all signal gain. The equation m ay also be expressed in
decibels (dB).
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G(dB) = Pout(dB) - Pin(dB) (dB)
(2)
The 1 dB com pressed gain, G ^ b, is the gain o f the PA at P ijb GidB = G(dB) - 1 (dB)
(3)
The expected gain o f a microwave PA is determ ined by transistor gain along with
gains due to im pedance matching the transistor to the source and load. The PA gain is
calculated w ith the following equations [1],
Source M atching:
Gs = (1 -|rs |2)/| 1- r i Nr s|2
(4)
Transistor:
Go = |S 2 i|2
(5)
Load M atching:
G L = (1 - |r L|2)/| 1-r 0uT rL|2
(6)
Total Gain:
G t = G sG oG l
(7)
Equations (4) and (6) are the non-unilateral forms o f the source and load m atching gain
equations w here Tin ^Sm and T out
^
22
since S 12 * 0 (non-unilateral transistor).
Maximum source and load m atching gains are achieved w ith sim ultaneous conjugate
matches on the transistor input and output (Tin = Ts* and T out = IY*).
In addition to gain, broadband PAs are characterized by gain flatness. Gain
flatness is the am ount o f variation in gain from a nominal gain value, typically expressed
in ± dB. The peak-to-peak (pk-pk) gain variation is tw ice the gain flatness.
PAs that m ust operate over a wide temperature range will exhibit gain variation
with temperature. U ncom pensated, the gain o f a GaA sFET PA will reduce linearly by
approxim ately 0.001 dB/°C per dB o f gain [2], The G aA sFET PA m ay be compensated
many ways, such as w ith a tem perature variable attenuator, DC bias com pensation, or
transistor tem perature control devices. The gain o f silicon bipolar transistor PAs
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5
decreases nonlinearly with increasing tem perature, w ith m axim um gain occurring at
around 0 °C [2],
1.2.3
Efficiency
Efficiency is the measure o f how effectively a PA converts the pow er consumed
from a pow er source to microwave signal power. The classical efficiency equation is
microwave output pow er divided by DC input power.
rj = 1 0 0 P o„,/P d c = 100Pout/(V mIm) (%)
(8)
Pout is the m icrow ave signal output pow er, V m is the pow er supply voltage, and I,n is the
current draw n from that source. This equation does not account for the input power to
the am plifier. The equation for pow er-added efficiency (PAE) includes the input power
and is therefore a better measure o f true PA efficiency.
t/PAE = 100(Pout - ?m)/? o c = 100POU,(1 - l/G )/(V mIin) = 100(1 - 1 / G ) I 7 (%) (9)
G is the num erical amplifier gain. Increasing the PAE o f a PA results in less power
dissipated in the PA. The dissipated pow er is the total input pow er less th e total output
power.
P d iss - P d c
1.2.4
+ Pm - Pout (Watts)
( 10)
Bandwidth
The bandw idth o f a PA is the range o f operating frequencies over w hich it is
designed to perform within the perform ance specifications. Bandwidth is typically
specified as a percentage and is calculated w ith the follow ing equation.
% BW = 100(fH - fL)/fc = 100Af/fc
(%)
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(11)
6
fH is the highest operating frequency, ft. is the lowest operating frequency, and fc is center
frequency. N arrow band typically refers to operation over a % B W o f less than 0.1 %, with
higher % BW operation being referred to as wideband o r broadband [3]. Bandw idth
requirem ents often determ ine the required transistor configuration for the PA, such as
cascode, com m on em itter (common source), or com m on base (comm on gate).
1.2.5
S-Param eters and Transistor Im pedance
1.2.5.1 Sm all Signal S-Parameters
S-Param eters are used to describe full 2-port characteristics o f transistors. Small
signal S-param eters are measured at low incident pow er levels, such as 0 dBm to +10
dBm. The S-param eters given in transistor data sheets are typically small signal and are
most useful for stability analysis. Table 1.1 shows the transistor characteristics as
described by S-param eters.
Transistor Characteristic
S-Parameter
Input Reflection Coefficient
S11
Transistor Gain
S21
Reverse Isolation
S12
Output Reflection Coefficient
S22
Table 1.1 Transistor S-Param eters.
For low pow er transistors, generally defined as transistors with 0 dBm < Pout <20
dBm, small signal S-parameters may be used for im pedance m atching network design.
However, for m edium pow er transistors, generally defined as those with 20 dB m < Pout —
33 dBm , and high pow er transistors, generally defined as those w ith Pout > 2W , large
signal im pedances are used for impedance matching netw ork design since the devices are
operating nonlinearly in compression.
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7
1.2.5.2 L arge Signal Im pedance
Sm all signal S-parameters do not accurately represent the characteristics o f
m edium and high pow er m icrow ave transistors operating at o r near P idB. Operating
frequency, output power, supply voltage, bias point, input pow er, harmonic signal levels,
tem perature, and other conditions all influence microwave transistor impedances. Large
signal transistor impedances are dependent on many variables and change with varying
operating conditions. For this reason the transistor must b e characterized under the exact
operating conditions o f the PA design.
Characterizing the transistor is usually accom plished one o f two ways. If a
nonlinear transistor model and param eters are given by the m anufacturer, such as a
C urtice-Ettenburg model, sim ulations m ay be performed o n the model to generate
representative impedance data. I f a model is not available, but load-pull data is, that data
m ay also be used to generate im pedance matching networks. Load-pull data is usually
given in the form o f load-pull contour plots in which perform ance parameters o f the
transistor are show n graphically versus the source and load im pedances. However, the
data is only accurate for the exact operating conditions under which the transistor
m easurem ents are recorded.
Load-pull data may be m easured w ith common laboratory equipment if data is not
available for the required PA conditions. W ith test equipm ent connected as shown in
Figure 1.2, load-pull data is m easured as outlined in the follow ing procedure.
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8
MANUAL LOAD PULL TEST SET-UP
o f POWER
METER
I RF SIGNAL
{ GENERATOR
s c s lic in g
s tu b s
j VECTOR
!
u c n w ra
t r a n s is t o r
te s t fix tu r e
"°= §
Figure 1.2 Load-Pull M easurem ent Test Equipm ent Set-U p.
M easurem ent Procedure:
1) The cascade driving network is calibrated with the power m eter to provide desired
microwave drive pow er at the output o f the directional coupler. The drive power
is determ ined by the desired output pow er less the expected gain.
2) For a GaAsFET, the transistor bias point is set by adjusting V gs to give a
particular Id for a constant V ds- The transistor is biased according to the required
class (A, B, A/B, C).
3) W ith the transistor biased and the drive pow er applied, the input stub tuners are
adjusted to maximize input pow er transfer by m inimizing return loss.
4) W ith input return loss m inim ized, the output stub tuners are adjusted for
maxim um output power. Tuning the output stubs changes th e input return loss
indicating the device is not unilateral under full power conditions.
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9
5) Steps 3 and 4 are repeated, iteratively, until minimum input return loss and
m axim um output pow er are obtained simultaneously.
6) The RF source, pre-amp, and all DC biasing are turned off, and the transistor is
rem oved from the test fixture.
7) Port 1 o f the network analyzer is calibrated at a single test frequency at the end o f
a test cable, and the display is adjusted to Sm ith Chart.
8) The center conductor o f the launcher is shorted to the outer conductor (ground)
and attached to the end o f the test cable.
9) A port extension is achieved by adding a tim e offset to the calibration point until
the impedance marker rotates to the short circuit point. This process accounts for
the electrical length o f the launcher to ensure accurate im pedance phase
measurements.
10) The launcher is removed from the test cable, and the short circuit removed.
11) The launcher is inserted into the transistor text fixture with the body bolted down,
and the center conductor soldered to the circuit board trace. T h e test cable is
connected to the launcher.
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10
12) T he vector netw ork analyzer now measures the input impedance o f the matching
network. The im pedance is measured by reading the m arker location on the
Sm ith chart display.
13) Steps 11 and 12 are repeated for the output m atching network.
14) F or maximum pow er transfer the transistor im pedances are the com plex
conjugates o f the input and output m atching netw ork impedances.
15) T he load-pull process may be repeated at o th er frequencies for a broadband
am plifier design. Since impedance data is obtained under actual device operating
conditions, the m easured data is used to design im pedance m atching networks for
optim al PA perform ance.
1.2.6
Stability
I f im properly im pedance matched, a pow er transistor may go into unstable
oscillations producing spurious signals and possibly dam aging the transistor. Oscillations
occur w hen either |T[n| > 1 o r IIoutI > 1.
To
test for unconditional stability, there are two
criteria the transistor m ust simultaneously meet, know n as the K-A stability test [1],
Sm all signal S-param eters are used in the K.-A stability calculations.
K = (1 - |S,,|2 - |S22|2 + | A|2)/(2|S12S2I|) > 1
(12)
|A| = |S11S22 - Si2S2,| < 1
(13)
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11
If a transistor fails either criterion, the device is not unconditionally stable, and stability
circles m ust be plotted to determ ine the values o f source and load m atching reflection
coefficients for which the device will be conditionally stable [1],
The K.-A test is lim ited to a single transistor since there are tw o constraints. For
m ultiple devices, a single stability calculation know n as the (i-iest is used to test for
unconditional stability [1].
li =
(1 - |S u |2 ) / ( |S 22 - A S u ’ l + IS12S21I) > 1
(14)
If fi > 1 the device is unconditionally stable, and all stability circles lie outside the
norm alized Smith Chart scale. Also, larger values o f /x indicate greater stability. Values
o f n greater than but close to one indicate that although a device is unconditionally stable
the stability circle(s) are close to the Smith Chart. Any m anufacturing tolerances or
changes in device characteristics with time or tem perature may result in the device
becom ing unstable.
1.2.7
Im pedance M atching
Impedance m atching is required on both input and output o f m icrow ave power
transistors for stable, efficient amplification. Im pedance matching m ay stabilize an
otherw ise unstable transistor.
PA gain is significantly improved by im pedance matching as show n in Equations
(4), (6), and (7). Achieving simultaneous input and output conjugate im pedance matches
results in maximum pow er sourced to the transistor and maximum p o w er delivered to the
load. For medium and high pow er transistors, large signal im pedance data, either in the
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12
form o f a nonlinear transistor model or representative load pull data, is required to
properly im pedance m atch the transistor under operational conditions.
As a rule o f thum b, discrete lum ped com ponents are prim arily used for im pedance
matching systems up to 1.5 GHz. Either discrete lumped com ponents or transmission
lines are used from 1.5 G H z to 3 GHz. A bove 3 GHz, transm ission lines are best suited
for impedance m atching. Below 1.5 GHz, printed lines are very long since the signal
wavelength is large, m aking the physical size o f the PA excessively large. Above 3 G H z
discrete com ponent nonlinearities introduced by package parasitics m ay cause circuit
instabilities if not properly accounted for in the design. H igh-Q (quality factor)
components should alw ays be used in PA design to m inim ize parasitic effects and losses.
W hether using discrete components or transm ission lines, the m atching elements m ust be
capable o f carrying the required DC and / o r RF currents.
Another factor to consider in im pedance m atching netw ork design is the
impedance transform ation ratio per elem ent. That is, m atching networks with only one or
two matching elem ents have high sensitivities to frequency changes and element
tolerances since the low transistor im pedance is transformed to system characteristic
impedance with o n e o r two elements. The im pedance transform ation ratio is calculated
by dividing the m agnitude o f the input im pedance with the elem ent attached to the
transistor or circuit b y the input impedance w ith the elem ent rem oved. Also, since
inductive and capacitive elements have a frequency response, the m atch may degrade
significantly w ith frequency changes, particularly when the transistor impedance and
element im pedance change in opposite directions as the operating frequency changes.
Matching networks w ith many elements have an overall low er transform ation ratio per
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13
elem ent and are therefore m ore broadband and may even h a v e desirable filtering
characteristics. However, caution m ust be taken to avoid h ig h insertion loss in multi­
elem ent m atching networks.
1.2.8
DC Bias and C lasses
M icrowave pow er transistors must be DC biased in so m e m anner in order to
am plify a microwave signal. The various types o f DC bias netw orks are categorized by
“class”, each having a unique definition. The type o f tran sisto r bias circuit is most often
defined by selecting the class that m axim izes PA efficiency w h ile m eeting linearity
requirem ents. The most com m on classes are defined below .
Class A amplifiers are biased such the transistor co n d u cts for the full 360 degrees
o f the applied microwave signal resulting in very linear am plification o f the signal.
System s requiring extrem ely linear amplification o f signals, such as C D M A or spread
spectrum communication netw orks, utilize Class A PAs. C la ss A biasing is generally
achieved when the quiescent bias current through the tran sisto r is on e-h alf its maximum
value (loss for FETs). O nce biased in Class A, the input sig n al m ust be kept small
enough to prevent the transistor from being driven out o f its lin ear region. The
theoretical efficiency limit for a Class A PA is 50 % w hen inductive o r transform er
coupled and only 25% w hen resistive coupled [4].
Class B amplifiers are biased such that the transistor conducts for 180 degrees o f
the applied microwave signal. C onducting for less than a fu ll cycle distorts the output
signal but results in increased efficiency. The theoretical efficien cy lim it for a Class B
PA is 78.5 % [4]. Two transistors, one conducting for the p o sitiv e 180 degrees o f the
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14
signal and the o ther conducting for the negative 180 degrees o f th e signal, m ay be used in
a push-pull configuration to maximize output pow er and efficiency w hile maintaining
linearity near that o f Class A designs.
Class A /B am plifiers combine the advantages o f Class A and Class B designs,
conducting for m ore than 180 degrees but less than 360 degrees o f the input signal. Class
A/B is generally achieved by biasing th e transistor for quiescent current equal to 10 % to
40 % o f the m axim um current. The theoretical efficiency limit for a Class A/B PA is 50
% to 78.5 %, depending on conduction angle [4]. Class A/B is a popular compromise
between efficiency and linearity requirem ents.
Class C am plifiers are highly nonlinear, conducting for less than 180 degrees of
the input signal. W hile the narrow conduction angle results in significant harmonic
distortion, the theoretical efficiency lim it for a Class C PA is 85 % to 90 % , depending on
conduction angle [4], With no signal applied, the transistor is m ost often biased at cutoff,
resulting in no quiescent current. C urrent flows through the transistor biased in Class C
only during the peak swings o f the input m icrowave signal.
Higher classes o f bias networks, such as Class D, E, and F, are high efficiency
designs that operate the transistor in various switch modes. The theoretical efficiency
limit o f these designs approaches
1.2.9
100
% , but signal distortion is very high.
Linearity
Linearity is a measure o f how accurately the PA output signal replicates the input
signal. D istortion m ay be introduced b y reduced conduction angles associated with
higher efficiency bias network designs o r m ay be introduced by transistor nonlinearities.
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15
Signal distortion induced by reduced conduction angles is referred to as harmonic
distortion. C lipping o r distorting a sinusoidal w ave results in harm onic signal generation.
The amplitude o f each harmonic depends on the shape and extent o f signal clipping.
Harmonic distortion is usually not a significant design problem since the harmonics are
out o f the passband and m ay be filtered with a low pass filter to avoid interference with
other com m unications systems.
Passing m ultiple carrier signals closely spaced in frequency through a PA
introduces a distortion com m only referred to as intermodulation distortion (IMD). The
intermodulation (IM ) products o f most concern are the third-order products, 2wi - W; and
2o>2 - o il , since th ese signals lie in or near the PA passband and cannot practically be
filtered. As the fundam ental signal voltage increases, the voltages o f the third-order
products increase as the cube o f the input voltage. Since power is proportional to the
square o f voltage, the output pow er o f the third-order products increases as the cube o f
the input power. T hird-order IM products increase in pow er rapidly as input power is
increased. This is show n graphically in Figure 1.3 where the slope o f the first order
product is one and the slope o f the third-order products is three [ 1 ].
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16
Intercept
- point
P 3 (referred to output)
P ! (referred to output)
1 dB
C om pression
-10
■o
-3 0 ^
P-i P 3 (referred to input)
-40 r
t
x
x
-50
-40
-30
i
-20
-10
0
10
Pj(dBm )
Figure 1.3 Third-O rder Intercept Point o f M icrow ave Power Transistors.
The hypothetical point at which the linear extensions o f the first- and third-order product
lines intersect is called the third-order intercept point (TOEP), P3 , referenced at the output
for PAs. P 3 is typically 12 dB to 15 dB larger than PidB [ 1]-
1.2.10 V SW R
V SW R is the voltage standing w ave ratio as m easured at the PA input and output
ports. Input V SW R is calculated b y m easuring the power reflected at the PA input w hen
driven b y a calibrated source. T he ratio o f reflected power to incident pow er is the return
loss. From the return loss, the reflection coefficient and V SW R are calculated.
i n = io (' RL(dBy20)
V SW R =
(1
+|r|)/(l -|r|)
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(is )
(1 6 )
17
O utput VSW R o f a PA is more difficult to m easure since the power level at
nom inal operating conditions is typically very high. A directional coupler configured to
m easured reflected pow er m ay be inserted betw een the PA output and load to determine
output V SW R . Often the P A is timed to output m axim um pow er to a 50 Q load and may
go unstable w ith other load impedances. In practice an isolator, a circulator with a
term ination on the third port, is placed between the PA output and the load to maintain
constant load impedance fo r the PA, to prevent oscillation, and protect the power
transistor(s) from large signal reflections.
1.2.11 Pow er Splitters and Com biners
By th e use o f pow er splitters and com biners a PA m ay output significantly more
pow er than available with a single transistor. The pow er splitter divides the input signal
into m ultiple paths, each containing a PA. The p o w er com biner then sums the amplified
signals back together for a higher output power. T h e pow er com biner is most often a
pow er sp litter w here the com biner input ports are th e splitter output ports and the
com biner output port is the splitter input port. W hen selecting a power splitter and
com biner, th e param eters o f m ost interest are num ber o f inputs or outputs, phase shift,
phase balance, am plitude balance, bandwidth, isolation, insertion loss, and power
handling capability. There are numerous power sp litter and com biner architectures. The
m ost popular are identified below.
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18
1.2.11.1
2-W ay and 2n-W ay
A 2-w ay pow er splitter divides the pow er o f a signal equally to tw o output ports,
with each output port having one-half, or - 3 dB, the pow er o f the input signal. A 2n-way
splitter is accom plished by cascading 2 -w ay splitters w ith each output port connecting to
the input o f another splitter. The m ost com m on 2-w ay and 2n-way pow er splitters are the
W ilkinson pow er divider, the hybrid coupler, and the T-junction.
The W ilkinson power divider consists o f a characteristic im pedance transmission
line that connects to two quarter-wavelength transm ission line transform ers o f impedance
equal to the square root o f two tim es the circuit characteristic impedance. The opposite
end o f the transform ers are cross-coupled w ith a term ination resistance equal to twice the
characteristic im pedance. This architecture results in equal power in-phase outputs and
provides high isolation between output ports. W hen used as a pow er com biner, one-half
the pow er difference entering the two input ports is dissipated in the term ination,
requiring a term ination o f adequate power handling capability. U nequal-split Wilkinson
designs are also possible by changing the transm ission line impedances appropriately.
The Hybrid Coupler is a 4-port pow er splitter in which the input pow er is split
equally between tw o output ports that are 90 degrees out o f phase. For this reason
hybrids are often called quadrature hybrids. The fourth port is the isolated port and
requires a term ination to circuit ground for proper port impedances. No pow er leaves the
isolated port unless there are reflections on the quadrature output ports. In this case, or in
the case o f a pow er com biner w ith unequal pow er entering the ports, o n e-h alf the power
difference is dissipated in the term ination connected to the isolated port. W hen using
hybrids for pow er splitting and com bining applications, attention m ust be given to the
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19
phases o f the signals to ensure the po w er w ill be summed in-phase at the ou tp u t port. An
exam ple o f a 4-way hybrid coupler pow er splitter and combiner circuit w ith p ro p er phase
shifting is shown in Figure 1.4.
N. Dgcg
Cdeq
/I
i
n
_ Z j [Z
fi!
[jsc -9i
\
CO^lE*
■TE0 M
lO L T
SC
deg
-301
~]
-9 0
Dj P.ES
01
X1
K<__
ce g
COJP'.-R
- Tgo
)
cj'
CCS
______
-Z Z
r
a)
f!5-
- * SG
Z T v
:
-JO
deq
'T C 5'
" I T
:
-'Pit?5 ,
’ 3 0 deg
;
0
OC
; )
\
H lSC ^3C«
3 ,C
-9 C dffG
^ n n z L
PF CU?\
-'3 0
-9 C
deq
deq
Figure 1.4 4-W ay H ybrid C ou p ler Power Splitter / Com biner.
A T-junction consists o f a characteristic impedance transm ission line that
connects to two quarter-w ave transform ers w hich transform the characteristic im pedance
to double its value. W hen the transform ers are connected in parallel, the im pedance at all
three ports is the same. T he advantage o f this architecture is the simplistic design.
However, the lack o f isolation betw een ou tp u t ports is a significant disadvantage,
particularly in high pow er applications. W hen used as a power combiner, the pow er
im balance entering the input port is split betw een the output port and the other input port
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20
according to the im pedance ratio at the point w here the three transm ission lines connect.
In high pow er applications the power out o f an input port due to pow er im balances
between the input ports m ay severely mistim e or dam age high pow er transistors.
1.2.11.2
n-W ay
An n-way p o w er splitter divides the signal pow er into n-ports, each at a pow er
level of-101og(n) dB relative to the input signal. The most com m on n-w ay pow er
splitters are the W ilkinson power divider, the T-junction, and the in-line, or serial, power
splitter.
The n-way W ilkinson Power D ivider has the same basic architecture as the 2-w ay
W ilkinson with all th e sam e advantages. H owever, the disadvantage is the term ination
from each output port connects to a com m on floating node. The connection o f all ports
makes planar layout difficult, such as with m icrostrip design.
The T-junction m ay also be configured for n-w ay power splitting. The isolation
between output ports increases as the num ber o f output ports increases, but overall
isolation is very low com pared to other architectures. The other m ain disadvantage to the
T-junction n-way splitter is the quarter-wave transform er impedance becom es very high
as the number o f outputs increases, requiring very narrow printed lines in stripline or
microstrip layouts. H igh impedance lines result in narrow bandwidth due to the high
im pedance transform ation ratio. Also unrealistic fabrication tolerances on narrow lines
m ay result in production inconsistencies.
The in-line p o w er splitter may have one o f several architectures. One such 3-way
design utilizes a 4.8 dB directional coupler follow ed by a 2-way pow er splitter such as a
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21
W ilkinson or quadrature hybrid. O ne-third the output pow er is coupled to th e directional
coupler coupled port, and the remaining tw o-thirds are equally split at the outputs o f the
W ilkinson or quadrature hybrid splitter, resulting in a 3-w ay equal-split pow er divider.
This architecture avoids high impedance lines w hile providing high isolation. However,
the planar layout m ay be large, and the line lengths m ust be carefully designed to ensure
the output signals are all summed in phase at the pow er com biner.
A nother in-line architecture utilizes an unequal-split W ilkinson, such as a onethird, tw o-thirds design followed by an equal-split W ilkinson or quadrature hybrid on the
tw o-thirds pow er port, resulting in a 3-way equal-split pow er divider. The com biner is
the x- and y-axis m irror o f the splitter, and again caution m ust be taken to account for all
phase shifts. This architecture may also be large since quarter-wave transform ers are
required to transform the unequal-split W ilkinson output port impedances to circuit
characteristic impedance.
1.2.12 Therm al Resistance and Junction T em perature
The pow er dissipated in a pow er transistor causes the temperature o f the device to
increase by an amount determined by the therm al resistance. Thermal resistance is the
resistance o f a structure o r material to therm al flow causing an increase in tem perature o f
the structure o r material, measured in °C/W.
The thermal resistance associated w ith pow er transistors is the junction-to-case
therm al resistance, 0 jc, specified on the m anufacturer’s data sheet.
0
JC is the therm al
resistance from the gate-source-drain junctions (for a FET) or base-em itter-collector
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22
junctions (for a BJT) to the package or case, most often a mounting flange for pow er
transistors.
There is a therm al resistance at every junction or interface o f m aterials. Two
surfaces appearing flat w ill often contact over less than one thousandth o f their common
surface area when pressed together due to im perfections on both surfaces [5]. Assuming
therm ally conductive grease is used between surfaces, such as a transistor flange and heat
sink, and the surfaces are fastened together w ith properly torqued screws, the thermal
resistance o f that interface is typically around 0.2 °C/W [ 6 ]. O ver-torquing the mounting
screws m ay result in flange “cupping” between the screws, increasing the therm al
resistance o f the interface. The therm ally conductive grease filling the air gaps between
the sink and transistor flange has much lower therm al resistance than air. For insulated
applications, electrically insulating, thermally conducting pads are available with thermal
resistances as low as 0.3 °Cin 2 /W . The use o f therm ally conductive greases and pads
significantly reduces the total therm al resistance o f a mounting system.
Thermal resistances are mathem atically m anipulated the sam e as electrical
resistances. That is, resistances add in series and divide in parallel. The goal o f a
transistor mounting system is to achieve the lowest possible thermal resistance.
The internal junctions o f a power transistor have a maximum tem perature rating.
Exceeding this rating will reduce the reliability o f the device and m ay cause im mediate
failure. The junction tem perature is calculated by adding the rise in tem perature due to
pow er dissipated to the m axim um ambient temperature.
T j = T Amb + 0 t P diss
(°C )
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(17)
23
TAmb is the m axim um am bient tem perature o f the heat sink, 0T is the total thermal
resistance o f the m ounting system, and PDiss is the total pow er dissipated in the transistor
as calculated with Equation (10).
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24
CHAPTER II
M icrowave Power Transistors
The perform ance o f a m icrowave PA is most heavily influenced by the selection
o f the power transistor. In this chapter the most common m odem transistor technologies
are discussed, and the advantages and disadvantages o f each technology are examined.
2.1 Bipolar Junction T ransistors (BJTs)
2.1.1
Silicon BJTs (SiBJTs)
Silicon bipolar ju n ctio n transistor (SiBJT) technology is the most established and
least expensive o f all m icrow ave power transistor technologies. SiBJTs are usually o f
npn type and m ost com m only used in applications below 3 G Hz. SiBJTs are capable o f
high gain and high pow er at low microwave frequencies, but device performance,
particularly gain, degrades w ith increasing frequency due to large base-emitter
capacitances and relatively low electron mobility. The gain reduction with increasing
frequency results in low PAE at frequencies above 3 GHz, requiring better heat sink
design and higher pow er driver am plifier stages. The upper frequency limit o f operation
or the unity-gain frequency (fi) is defined as the frequency at w hich the short-circuit
current gain is unity [ 1 ].
/ r = g J(2 7 tC ,) (Hz)
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(18)
25
Cz is the equivalent rc capacitance from the hybrid- 7t equivalent circu it model, and gm is
the transconductace.
SiBJTs are typically used in common base configuration for broadband
perform ance above 1 G H z or in common em itter configuration for high gain below I
GHz. SiB JT devices are inexpensive and readily available in low to very high power
applications with a w ide range o f supply voltages. SiBJTs exhibit excellent thermal
conductivity which, along with high supply voltages, m akes possible very high power
devices.
2.1.2
Silicon G erm anium Heterojunction BJTs (SiG eH B T s)
To improve the high frequency performance o f SiBJTs, sm all am ounts o f
germanium are doped into the base region to reduce the carrier transit tim e from collector
to em itter. This is due to the increased electron m obility o f germ anium . Additionally,
the germ anium is doped in graded composition from around 5% at the emitter-base
junction to around 15% at the collector-base junction. This introduces a built-in field to
further reduce electron transit tim e and improve the speed o f the transistor by a factor o f
about 1 .7 over hom ogeneously doped SiGe [7], The distance through w hich the electrons
must travel is shortened w ith a “heterojunction” o r “heterostructure” . In conventional
transistors the electrons travel horizontally, requiring the transistor b e m ade thinner to
decrease the path length. The am ount the transistor can be thinned is lim ited by
increasingly difficult fabrication processes, expensive fabrication equipm ent, and device
performance param eters such as power dissipation and lot consistency. The electron flow
in a heterojunction BJT (HBT) is vertical. The height o f the transistor is easily reduced
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26
by thinning th e SiGe layer to decrease electron transit distance and tim e, resulting in
higher gains and higher efficiencies at higher frequencies as com pared to conventional
SiBJTs or SiG eB JTs. The unity-gain frequency (fr) for SiGeHBTs has been reported at
over 200 G H z [ 8 ].
SiG eH B Ts are typically operated in com m on em itter configuration for high gain
at m icrow ave and m m -w ave frequencies. D ue to the thin device geom etry, the available
supply voltages and output pow er capability are low er than SiBJTs. SiG eH BTs are also
more expensive as the w afer yield is typically m uch lower than that o f SiBJTs [7],
2.2 M O SFETs
2.2.1
B asic M O SFETs
M etal-oxide sem iconductor field effect transistor (M OSFET) technology, like
SiBJT technology, is very w ell established. M ost M OSFET m icrow ave transistors are
silicon, enhancem ent m ode, n-channel devices. M OSFETs are field-controlled devices as
opposed to B JTs w hich are current-controlled devices. MOSFETs exhibit better linearity
than SiBJTs since gate-source bias changes channel conductance in a very linear
relationship. M OSFETs are the preferred device for high linearity applications such as
cellular com m unications and CDM A systems. Therm al performance o f M OSFETs is
sim ilar to th at o f SiBJTs. M OSFETs offer hig h er gain and higher efficiency than SiBJTs
at low m icrow ave frequencies [4]. However, like SiBJTs, the gain o f M OSFET devices
degrades substantially at frequencies above 1 G H z due to large gate-drain and gatesource capacitances. T he unity gain frequency (fr) is calculated w ith Equation (19) [4],
/ r = g m/(27iC,ss) (H z)
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(19)
27
Ciss = Cgd + Cgs (Farads)
(2 0 )
C gd is the gate-drain capacitance, C sd is the gate-source capacitance, and gm is the
transconductance.
M O SFETs are typically operated in com mon source configuration for maximum
gain or linearity up to
1
GHz and are inexpensive and readily available in low to high
pow er applications w ith supply voltages up to 28 V.
2.2.2
LD M O SFETs
Laterally-diffused MOSFETs (LDM OSFETs) utilize an alternate device structure
to extend the gain and linearity advantages o f M OSFETs from 1 GHz to around 2.5 GHz
w hile m aking possible higher output power. The conventional M OSFET does not permit
very high pow er operation since the channel length m ust be increased to obtain high
breakdow n voltages necessary for very high power. Increasing the channel length
increases drain-source resistance and input capacitances, resulting in reduced gain,
efficiency, and unity-gain frequency. LDM OSFETs elim inate these tradeoffs by
shortening the channel while doping the body and drift regions accordingly to increase
breakdow n voltages. This combination extends the gain, efficiency, and linearity
advantages o f M OSFETs to higher frequencies w hile m aking possible output pow er up to
150 W atts per device. LDMOSFETs are designed for operation in com m on source
configuration, m ost often biased in Class A, A/B, or push-pull B for optim al linearity,
m axim um efficiency, o r maximum power. Calculation o f LDM OSFET unity-gain
frequency is the sam e as for MOSFETs.
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28
W hile LDM OSFETs offer m any advantages over conventional M O SFETs and
SiBJTs up to 2.5 GHz, LDMOSFETs have a significant disadvantage. Som e
LDM OSFET electrical parameters have show n a tendency to drift over tim e. Such
param eters include threshold voltage and drain current for a given gate voltage. Since
initial designs are often optimized for efficiency or linearity, any drift in electrical
param eters represents a reduction in perform ance. M any m anufacturers have addressed
this drift problem that is due to “hot electrons” w ith som e degrees o f success. However,
the general effort today seems to be in containing the problem rather than trying to solve
what appears unsolvable. Manufacturers presently specify a m aximum am ount o f drift
over a specified tim e period [9], Design engineers are left to design feedback circuits or
current control circuits to compensate for param eter drift over time.
2.3 G allium Arsenide FETs (GaAsFETs)
Com pared to SiBJT technology, gallium arsenide FETs (GaAsFETs) are a new
technology. GaA sFETs exhibit very high gain and efficiency into the m m -w ave
frequencies and are presently the dominant solid-state am plification devices for
applications above 3 GHz. GaAsFETs are fabricated w ith gallium arsenide (GaAs),
Group III-V elem ents, for increased frequency response and noise perform ance. Electron
m obility is 5 to 7 times greater in GaAs than in silicon [10]. Depending on the device
structure, a G aA sFET m ay be categorized as a M ESFET or DH-PHEM T. W hile
different in structure, M ESFETs and D H-PHEM Ts share m any characteristics.
GaA sFETs are m ost commonly fabricated as depletion mode, n-channel Junction
FET (JFET) devices. Although there are m any m anufacturers o f GaA sFETs and devices
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29
are readily available, G aA sFETs are presently the most expensive dollar-per-W att
devices because o f fabrication difficulty and low wafer yields. A n additional
disadvantage is the requirem ent o f either a dual voltage supply o r a self-bias circuit to
generate the required negative gate-source voltage to properly bias the “norm ally-on”
JFET devices.
GaAsFETs are typically used in com m on source configuration for high gain at
m icrowave and mm-wave frequencies. The geometry o f the G aA sFET gate determ ines
many param eters o f the device. The gate w idth, defined as the m axim um gate dim ension
perpendicular to current flow, is proportional to microwave p o w er handling capability.
The transconductance and input capacitances increase proportionally with gate w idth and
device resistances vary inversely with gate width [11]. The gate length, defined as th e
m axim um gate dimension parallel to current flow, determines unity-gain frequency as
shown in Equation (21) [12].
f T = gm/(27iC,) = vsat/(27iLG) (Hz)
(21)
Cj = C gs + C gd is the total input capacitance, gm is the transconductance, vsat is the
saturated carrier velocity, and Lg is the gate length.
D evice breakdown voltages limit the supply voltage m axim um rating for
G aA sFETs. An avalanche breakdow n occurs between the gate and drain when the draingate voltage crosses a critical level. The lim iting peak drain-source voltage is determ ined
by the gate-drain breakdow n voltage [13].
V l = V gd + |V p| (V olts)
V gd
is the gate-drain avalanche voltage, and V P is the JFET p in ch o ff voltage.
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(22)
30
The maximum drain-source voltage o f a G aA sFET should not exceed the following
m axim um level [13].
V ds = (V gd + |Vp| - V k)/2 (Volts)
V k is the drain-source knee voltage at which device saturation current
(23)
(Id ss)
is measured.
Attention m ust b e given to thermal calculations when utilizing GaAsFETs in PAs
since the thermal conductivity o f GaAs is about one-tenth that o f silicon [10]. The
m axim um junction tem perature o f GaAs devices is lower than that o f com parable silicon
devices requiring m ore efficient heat sink designs.
In addition to w idespread PA transistor usage, GaAsFETs are the preferred
devices for low noise applications, such as receiver low-noise am plifiers, since there is no
shot noise in G aA sFETs [13]. The prim ary noise sources in a G aA sFE T are gate bonding
pad resistances, flicker noise in applications below 50 MHz, therm al-generated channel
noise, and gate noise introduced by channel noise.
2.3.1
M etal-Sem iconductor FETs (M ESFETs)
The conventional GaAsFET architecture is m etal-sem iconductor GaAsFET
(M ESFET). M ESFETs are Schottky barrier type devices with the gate contact forming a
Schottky diode with th e semiconductor. R ather than an oxide layer isolating the gate as
in a M OSFET, the M E S F E T Schottky contact prevents DC isolation o f the gate. The
gate-source and gate-drain voltages must not exceed approxim ately 0.5 V to prevent
forward biasing o f the Schottky diodes. A pplying a higher gate-source o r gate-drain
voltage w ill result in th e gate electrodes fusing since the gate length is on the order of
0.25 pm to 2.0 pm. E ven a small gate current may have a current density as high as 106
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31
A /cm 2. Figure 2.1 illustrates G aA sFET gate current being bi-directional as microwave
input pow er is significantly increased [ 1 0 ].
2.30
S
3m
5
10
30
Figure 2.1 GaAsFET G ate Current V ersus Input Power Level.
C areful consideration must be given to the bias point o f the MESFET to ensure the peak
m icrow ave input voltage added to the DC gate-source voltage does not forw ard bias the
gate-source junction.
M ESFETs extend FET efficiency and linearity advantages to high m icrow ave and
m m -w ave frequencies but have bias limitations that m ust be carefully considered when
designing a PA.
2.3.2
Double-Heterojunction PH EM Ts (DH -PH EM Ts)
Double-heterojunction pseudomorphic high-electron mobility G aA sFET
transistors (DH-PHEM Ts) are the m ost efficient devices available today b u t are more
expensive than MESFETs and have lower breakdown voltages. In a conventional highelectron m obility transistor (H EM T) structure, the interface o f GaAs and A lG aA s create a
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32
heterojunction. The charge carrier saturation velocity is higher in AlGaAs than in GaAs,
resulting in a higher unity-gain frequency (fr). The heterojunction also increases
transconductance (gm) and decreases input capacitance (Cgs) resulting in higher gains at
higher frequencies th an possible with conventional M ESFETs. Also, the gate o f HEM T
devices is most often “m ushroom -shaped” to reduce gate contact resistance [ 1 2 ].
The D H -PH EM T utilizes dual heterojunctions created b y an
A lG aA s/InG aA s/A lG aA s structure to further improve HEM T performance. The AlGaAs
and InGaAs structures are slightly m ism atched resulting in a “pseudom orphic” structure
that requires the InG aA s layer be kept thin. The AlGaAs layer doping is then optimized
for higher breakdow n voltages [14], The use o f an InGaAs lay er results in an even higher
saturated carrier velocity than in AlGaAs, translating to a h ig h er fr . The DH-PHEMT
structure also m axim izes saturation current
(Id ss)
per unit gate w idth resulting in higher
available pow er densities [ 1 2 ].
D H-PHEM Ts, com pared to M ESFETs, exhibit higher unity-gain frequency, gain,
and efficiency with slightly reduced breakdown voltages and increased distortion. The
breakdow n voltage is typically 3-4 volts lower for DH-PHEM Ts, requiring drain-source
DC biasing o f 8 V m axim um . The increased distortion o f D H -PH EM Ts is due to the
peaking o f the transconductance versus gate voltage characteristic near the saturation
point [12]. The peak results in different gains across the m icrow ave signal voltage sw ing
w hen biased for Class A linear operation. However, the increased distortion is often
offset by the gain and efficiency advantages o f DH-PHEMTs.
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33
CHAPTER III
M icrowave C om ponent Modeling
Lumped com ponents used in m icrowave circuits have nonlinear behaviors due to
packaging parasitics and electrom agnetic effects. Component nonlinearities must be
taken into consideration w hen designing m icrow ave PAs to ensure stable operation and
optimal performance. C ircuit models are developed for capacitors, inductors, and
resistors. Small- and large-signal GaAsFET m odels and nonlinear p rinted circuit board
(PCB) effects are discussed and evaluated.
3.1 Resistor Modeling
Resistors are com m only used in m icrow ave circuits for transistor biasing,
im pedance matching, p o w er attenuating, pow er dividing, and other applications. Ideal
resistors have constant real electrical resistance over all frequencies and environmental
conditions. However, actual resistors have significant parasitic reactances due to
fabrication and packaging resulting in frequency-dependent impedance.
The most com m on resistor technology used in microwave circuits is the thin-film
chip resistor. Thin-film chip resistors have the lowest parasitic reactances and the highest
pow er dissipation per u nit volum e o f all resistors available today. T hin-film chip
resistors are fabricated b y vacuum depositing a resistive alloy onto a flat ceramic, glass.
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34
or silicon substrate. Photo-lithographic techniques are then used to define the final
geom etry and value o f the resistor [15].
The m icrow ave circuit model o f a chip resistor incorporating parasitic reactances
is shown in Figure 3.1 [16].
Figure 3.1 M icrowave C ircuit M odel o f a Chip Resistor.
The inductance originates from the chip resistor leads and is usually very small since chip
lead length to the resistive alloy is very short. The parallel chip end-caps and distributed
capacitance between individual alloy particles com prise the capacitance in the model
[17]. Equation (24) is the im pedance o f the m odel show n in Figure 3.1.
Z = R(1 + j27tfL/R )/(l - 4 tr¥ L C + j27tfRC) (Q )
The term
(24)
t f2LC is typically very small, sim plifying the im pedance equation [16].
47 2
Z = R(1 + j2 n fL /R )/(l + j2nfR C ) (Q )
(25)
The im pedance equation is now dependent on the L/R to RC ratio. If L/R = RC, then the
im pedance o f the resistor is equal to the resistance and is frequency independent.
Equalizing the L/R to RC ratio is not always feasible in practice, but if 0.8 < |Z|/R < 1.2
for all frequencies o f interest, the parasitic reactances have little effect on the frequency
perform ance o f the resistor, and the ideal resistor m odel m ay be used [16].
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35
The self-resonant frequency
(F sr)
o f th e resistor m odel show n in Figure 3.1
occurs at the frequency w here the im pedance m agnitudes o f the inductor and capacitor
are equal.
Fs r = 1 / ( 2 tiV(LC)) (H z)
(26)
The capacitor and inductor create a parallel resonant circuit th at will resonate with
m axim um im pedance at Fsr. The chip resistance limits, o r dam ps, the impedance o f the
parallel circuit at self-resonance.
The m axim um pow er dissipation rating o f a chip resisto r m ust be considered
w hen used in high pow er applications. Table 3.1 lists the industry standard power
dissipations according to chip resistor size [15].
C hip Size
(LLW W )
0201
0402
0603
0805
1206
1210
2010
2512
Max Pdiss
(Watts)
1/20
1/16
1/10
1/8
1/4
1/4
1/2
1
Temp. R ating
(°C)
125
125
155
155
155
125
125
125
T able 3.1 C hip R esistor Maximum Pow er D issipations and Tem peratures.
The m axim um pow er dissipation ratings are valid up to +70 °C am bient temperature,
above w hich the m axim um ratings are linearly de-rated to 0 W atts at the maximum
tem perature specified in Table 3.1. The chip size code is length by w idth, both specified
in hundreds o f an inch. For example, an 0805 package m easures 0.08” long by 0.05”
wide. The frequency perform ance o f a chip im proves as the package size decreases, but
the ability to dissipate pow er diminishes.
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36
3.2 Inductor M odeling
Inductors are used in m icrow ave circuits for chokes, transistor biasing, im pedance
matching, filtering, and other applications. Ideal inductors have linearly increasing
im pedance w ith frequency as represented by the following equation.
Z = j2 7 tfL (Q)
(27)
Inductors m ay be hand-wound o r packaged in chip form. W ire-wound chip inductors are
most com m on for microwave applications since the chip package exhibits low parasitic
com ponents. The inductor w ires m ay be wound around a ferrite core to increase
inductance.
T h e m icrowave circuit m odel o f a chip inductor incorporating parasitic
com ponents is shown in Figure 3.2 [18].
,
I
H-------'
•-— i/vv— •-vV'/
— •—•
»v«
Figure 3.2 M icrow ave Circuit M odel of a Chip Inductor.
Resistor Ri is a parallel resonance dam ping resistor derived by curve fitting the
im pedance equation to measured inductor response. Capacitor C is the distributed
capacitance betw een coil w indings. Resistor Ri is the DC resistance o f the wire.
Variable resistor
R var
is the w ire resistance due to skin effect at high frequencies. Skin
effect is a characteristic o f a conductor in w hich current density near the surface increases
with increasing frequency and current density near the center o f the conductor decreases
with increasing frequency assum ing constant current magnitude. Skin depth, a m easure
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37
o f current density depth, varies inversely to the square root o f frequency. The wire
resistance due to skin effect therefore increases proportionally to th e square root o f
frequency [18].
R var = kVf (Q )
(28)
The constant k is determined by w ire size and com position. Figure 3.3 illustrates the
distributed resistance and capacitance o f a coil o f w ire [17].
Cd
Figure 3.3 Distributed C apacitance and Series Resistance o f an Inductor.
T he im pedance o f the inductor model in Figure 3.2 is calculated with Equation
(29).
Z = R2 + (1 + i27cfCR. Vi27cfCRvAP - 4 ti¥ l C)
(Q )
(29)
1 - 4 jc¥ l C + j27tfC(RvAR + Ri)
The inductor m odel shown in Figure 3.2 resonates w ith maximum im pedance at F sr
where the inductive and capacitive impedances are o f equal m agnitude. Equation (26) is
used for calculating the self-resonant frequency o f an inductor. T he parasitic capacitance
dominates the im pedance characteristics o f the inductor for frequencies higher than Fsr.
For f >
F sr,
inductors may be used as capacitive elem ents provided th e DC short created
by the coil o f w ire does not disturb the circuit operation.
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38
The unloaded com ponent quality factor (Q) o f the parallel resonant circuit o f
Figure 3.2 is defined as the ratio o f the inductor’s reactance to its series resistance.
Q = X l/R t
Rt
(30)
is the sum o f R 2 and
R var-
Since
R var
increases with increasing frequency, the
quality factor decreases with increasing frequency. The parasitic resistances de-Q the
circuit at resonance and broaden the range o f frequencies over w hich the im pedance peak
occurs. Low-Q inductors m ake better broadband microwave chokes.
W hen selecting inductors for pow er applications, the DC resistance o f the wire
and m axim um current rating o f the inductors must be carefully considered. The DC
resistance results in voltage dro p s when large currents are carried in the wires. The
voltage drop results in power losses and increases the parasitic capacitance o f the
inductor since the parallel w ires have voltage drops between w indings [17]. Exceeding
the m axim um current rating o f th e inductor with either DC o r m icrow ave currents may
cause im mediate failure o f the inductor.
3.3 C apacitor M odeling
Capacitors are used in m icrow ave circuits for decoupling, DC blocking,
im pedance m atching, filtering, and other applications. Ideal capacitors have linearly
decreasing im pedance with frequency.
Z=l/(j27ifC)
Q
(31)
Like inductors, chip capacitors are m ost common for m icrowave applications since the
chip package exhibits low parasitic components.
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39
The m icrowave circuit model o f a chip capacitor incorporating parasitic
com ponents is shown in Figure 3.4 [19].
Figure 3.4 M icrowave C ircuit Model o f a C hip C apacitor.
C apacitor C is the nom inal chip capacitance. Inductor Ls is the equivalent, or effective,
series inductance (ESL) due to lead and capacitor plate inductance. C apacitor Cp is the
chip parallel capacitance due to the parallel chip end caps. Resistor Rs is the equivalent,
or effective, series resistance (ESR) o f the capacitor. The im pedance o f the capacitor
model shown in Figure 3.4 is determ ined w ith Equation (32).
Z = i27tfCpRc + C p/C - 47c¥ l <:C p (Q )
j2rrfCpRs + C P/C - 4 7 t¥ L sC P + 1
(32)
The ESR takes into account all capacitor losses and is usually expressed in milliohms. The ESR is com prised o f capacitor dielectric losses and m etal losses. The
dielectric losses are a function o f the capacitor dielectric material, each o f w hich has a
characteristic loss tangent. The loss tangent is equal to the dissipation factor (DF) and is
a measure o f the loss in the capacitor’s dielectric at microwave frequencies [20]. While
ceramic is the most com m only used capacitor dielectric, porcelain exhibits the lowest DF
o f all capacitor dielectrics com m only used today. The typical DF o f ceram ic is 0.002; the
typical DF o f porcelain is 0.00007 [21]. The metal losses are dom inated by the skin
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40
effect. Skin effect dom inates the ESR value at high frequencies w hile dielectric losses
dom inate the ESR value at low frequencies. The capacitor ESR is typically specified by
the manufacturer at a particular frequency, often 1 GHz. To determ ine the ESR at any
other microwave frequency, the following equation may be used as an approxim ation
[20].
ESR(f2) = ESR (ftW (f 2 /ft) «
(33)
ESR(fi) is the ESR specified by the manufacturer at ft, and f2 is the frequency at which
the ESR is unknown. T h e pow er dissipated in a chip capacitor is determ ined by the ESR.
P cap
= I2ESR (W atts)
(34)
I = V(P0 Ut/Z) (A m ps)
(35)
Pout is the circuit output pow er, and Z is the circuit characteristic im pedance.
The capacitor m odel shown in Figure 3.4 has both series and parallel self­
resonance characteristics. The series self-resonant frequency
F sr
occurs w hen the ESL
(Ls) and nominal capacitance (C) impedances are o f equal m agnitude. Equation (26) is
used for calculating the series self-resonant frequency o f a capacitor. T he parallel self­
resonant frequency
( F Pr )
occurs w hen the impedance magnitude o f parallel capacitor CP
is equal to the im pedance m agnitude o f C and Ls in series.
F Pr
= V( 1
-
Cp/C)/(27tV(LsCp)) (Hz)
(36)
The parallel self-resonant frequency is typically much higher than the series self-resonant
frequency since Cp is v ery small. The parasitic inductance dom inates the impedance
characteristics o f the capacitor for
F sr
< f<
F Pr.
In this frequency range, capacitors may
be used as inductive elem ents as long as the DC shortnorm ally provided by inductors is
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41
not required. At frequencies above
F p r,
the capacitor again behaves as a capacitor with
the im pedance determined by Cp.
A n “ ideal” capacitor with equivalent capacitance C e in series with the ESR may
be used to m odel a microwave capacitor for frequencies below
F Sr .
(37)
C E = C /(l - 4 tc¥ L sC) (Farads)
As frequency increases, the denom inator decreases, resulting in a larger effective
capacitance. Equation (37) is undefined at series self-resonance since the denom inator
goes to zero.
A t the series self-resonant frequency, the im pedance o f the capacitor is equal to
the ESR. For high power decoupling applications, the ESR m ust be minimized to avoid
pow er loss and potential instability. Placing series self-resonant capacitors in parallel
will reduce the overall ESR while m aintaining the same series self-resonant frequency.
Figure 3.5 shows the effect on im pedance o f paralleling 200 M Hz series self-resonant
capacitors [22].
10m
1
I i i- L
100MHz
16Hz
Frequency (Hz)
Figure 3.5 Effect o f Parallel Capacitors on Impedance.
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42
The overall ESR is reduced by a factor o f two when the n u m b e r o f parallel capacitors is
doubled. T he follow ing equations show the effects o f p arallelin g (n) capacitors on total
capacitance, ESL, and ESR.
Cfotai = nC
(Farads)
(38)
ESLtotai = ESL/n = Ls/n (Henries)
(39)
ESR-rotai = ESR /n = Rs/n (Q)
(40)
The series self-resonant frequency is unchanged by p arallelin g capacitors since the total
capacitance increases by a factor o f n and the inductance decreases by a factor o f n.
F sr = 1/2 tiV(nCLs/n) = l/2nV(CLs)
(Hz)
(41)
Placing capacitors in parallel increases capacitance, red u ces ESL, reduces ESR, and has
no effect on series self-resonant frequency.
The unloaded component Q o f the capacitor m odel o f Figure 3.4 is defined as the
ratio o f the capacitor’s reactance to its series resistance [17].
Q = Xc /R s = Xc/ESR
(42)
Since ESR increases w ith increasing frequency, the q u ality factor decreases w ith
increasing frequency. The ESR de-Q ’s the circuit at series resonance and broadens the
im pedance m inim um . High-Q capacitors have the low est insertion loss and are desired
for decoupling o r m icrowave shorting.
3.4 G aA sFET M odeling
A ctive devices such as power transistors have m an y nonlinearities that depend on
one another and on bias levels, packaging, temperature, an d other conditions. For highest
efficiency a G aA sFET device will be used in the high-efficiency shared-current
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43
m icrow ave PA design presented in Chapter IV. Sm all- and large-signal m odels are
presented for the GaAsFETs. For stability analysis o r low pow er applications, sm allsignal S-parameters or a device small-signal model m ay be analyzed. For pow er devices
operating at or near their 1 dB com pressed power, nonlinear m odels must be used for
im pedance m atching netw ork design.
The GaAsFET sm all-signal S-parameters, sm all-signal lumped element model, or
nonlinear model given by transistor manufacturers w ill typically represent the device in
chip form only. A secondary model called the package model m ust be used to surround
the chip model with parasitic inductances, capacitances, and resistances due to the
particular package style. T he package style, whether pill, flange, or integrated circuit
(IC), has unique parasitic elem ents. W hen simulating transistors, the package parasitics
from the package model m ust be added to the chip m odel for optimal simulation
accuracy.
3.4.1
Linear Sm all-Signal G aA sFET Model
The small-signal G aA sFE T model is often used for stability analysis o r m atching
netw ork design when the p o w er transistor is operating in its small-signal linear region
below th el dB com pressed p o w er level. The individual elements o f the G aA sFET smallsignal model are typically derived from curve-fitting th e calculated S-parameters o f the
lum ped element model to the m easured small-signal S-param eters within 10% accuracy.
A com m on small-signal G aA sFE T model is shown in Figure 3.6 [23].
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Figure 3.6 GaAsFET Sm all Signal Equivalent C ircuit M odel.
The drain-source current Ip is a function o f the device transconductance, operational
frequency, and voltage across the gate-source capacitive junction [23].
Id = (VGMe'JUI) (Amps)
(43)
G m and x are model parameters, V is the voltage across the gate-source capacitance, and
to = 2Trf w here f is the operational frequency. As frequency increases, the voltage across
the gate-source capacitor decreases, and the decaying exponential decreases resulting in
reduced device gain.
3.4.2
N onlinear Large-Signal GaAsFET M odels
N onlinear large-signal GaAsFET models are used for distortion analysis and
im pedance m atching network design for optimal pow er, efficiency, and gain. Nonlinear
m odels utilize mathematical relationships whose param eters have been linked through
curve fitting to the physical device behavior. The individual equations and elements o f
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45
any G aA sFET large-signal m odel are derived from curve-fitting device current/voltage
relationships to the measured d evice characteristic current/voltage curves. A dditional
param eters com pensate for tem perature effects and the inter-relation o f the elem ents and
device characteristics. Programs such as Agilent Technology’s IC-CAP perform model
param eter synthesis with m easured device characteristics [24].
G aA sFET m anufacturers w ill often show the nonlinear model param eters for their
devices for one o f three popular nonlinear models. The Curtice-Ettenburg, o r C urtice
Cubic, model utilizes a hyperbolic tangent curve to sim ulate the shape o f the drain-source
current/voltage (Id/Vds) characteristic curve and a cubic polynom ial to adjust th e height o f
the curve [25]. This model w as introduced by Dr. W alter C urtice in 1985 and is the most
com m on G aA sFET model used today. The Statz-Raytheon, o r Statz-Puce, m odel utilizes
a sim pler model but more com plex equations. The Statz-Raytheon model utilizes a
truncated series representation o f the I<i/Vds characteristic rather than a hyperbolic tangent
function. The defining characteristic o f the Statz-Raytheon m odel is nearly constant Ij
with increasing Vds [25], The T riq u in t’s Own Model (TO M ) is sim ilar to the StatzRaytheon model. The defining characteristic o f the TOM m odel is a linear increase in I<j
w ith increasing Vds [25], The C urtice-Ettenburg model is m ost accurate for devices at a
single bias point. For a wide range o f bias points, the Statz-Raytheon or TO M m odel
m ore accurately follows actual d ev ice characteristics [25].
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46
The Curtice-Ettenburg model is given by the m anufacturer o f the device selected
for the PA design presented in Chapter 4. T h e Curtice-Ettenburg m odel consists o f an
equivalent circuit for the GaAsFET that includes linear elem ents, nonlinear capacitances,
diodes, and a nonlinear current source representing Id. The equivalent circuit for the
Curtice-Ettenburg G aA sFET model is show n in Figure 3.7 [26].
.
►
:
CGo(Vgj.Va)
GATE o
— ♦ - ---- • -------• -------------
• ----- • ----- • ------------- • ------/ . V
o DRAiN
C gs(Vh.Vis)
>
•
:
«
•
«---------------
<
*"■
o
SOURCE
Figure 3.7 G aA sFET Curtice-Ettenburg Nonlinear C ircuit Model.
The internal voltages are the applied voltages less the voltage drops due to contact
resistances and other parasitic resistances. T h e drain current is a function o f internal
device voltages Vds and Vgs [26].
Id(V ds,Vds) = ( A o + A ,V , + A 2 V , 2 + A 3 V 13 )tanh(yVds)(l + XVds) (Amps)
(44)
V , = Vgsd-tKl + P(V d s0 - Vds)) (V olts)
(45)
Vds and V ^ are internal voltages, V dso is th e voltage at w hich the An polynom ial
coefficients are determ ined,
t
is the source-to-drain time delay, and
p,
y,
a.
are constants.
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47
The Curtice-Ettenburg nonlinear model param eters typically specified by GaAsFET
manufacturers are shown in Table 3.2. [27].
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48
Param eter
3
Y
V d s0
V to
Ao
A,
a2
a 3
T
R.
r 2
V bo
V bi
Rf
Is
N
R ds
C rf
Rd
Rg
Rs
R[N
C gso
C gdo
Fc
C ds
C gs
C gd
Kp4
Af
T nom
X ti
EG
V TO rc
P tce
F fe
D escription
Coefficient for pinch-off change w ith respect to Vds
Hyperbolic tangent function param eter
Output voltage at which Ao, A i, A 2, A 3 were evaluated
V alue o f Vi below which Ids = Ids(Vi = VTO, Vds)
C ubic polynomial Ids equation coefficient 1
Cubic polynomial Ids equation coefficient 2
Cubic polynomial Ids equation coefficient 3
C ubic polynomial Ids equation coefficient 4
Transit time under gate
Approximate breakdown resistance
Resistance relating breakdow n voltage to channel current
Gate-drain junction reverse bias breakdow n voltage (gate-source
junction reverse bias breakdow n voltage with Vds<0)
Built-in gate potential
Gate-source effective forward bias resistance
G ate junction reverse saturation current (diode model)
G ate junction ideality factor (diode m odel)
Additional output resistance for RF operation
U sed with R ds to model frequency dependent output
conductance
Drain ohmic resistance
G ate resistance
Source ohmic resistance
Channel resistance
Zero bias gate-source junction capacitance (diode m odel)
Zero bias gate-drain junction capacitance (diode m odel)
Coefficient for forward bias depletion capacitance (d io d e m odel)
Drain-source capacitance
Gate-source capacitance
Gate-drain capacitance
Flicker noise coefficient
Flicker noise exponent
Nominal am bient tem perature at w hich these model param eters
w ere derived
Tem perature exponent for saturation current
Energy gap for tem perature effect o f Is
V TO temperature coefficient
D rain current exponential tem perature coefficient
Flicker noise frequency exponent
T able 3.2 C urtice-Ettenburg G aA sFE T Model Param eters.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Unit
1/V
1/V
V
V
A
A/V
A/V 2
A
Sec
Q
Q
V
V
Q
A
-
Q
F
Q
Q
Q
Q
F
F
-
F
F
F
-
-
°C
-
eV
v /° c
% /°c
-
49
3.4.3
Package M odels
The shape, size, and construction o f the G aA sFET package determines the
package lumped elem ent model. Element values are determ ined by measuring Sparam eters with the chip in the package and then com paring them to the measured chip
S-param eter data. T he calculated S-parameters o f the package m odel are curve-fit to the
m easured S-param eter differences. Figure 3.8 shows a typical package equivalent circuit
model [28].
CP3
i
' 7~
CP4
i—
--------------------------------------- ;
GATE O
•
j
RP
LP1
|
!
;
I
IPG
LPD
I
i
I
ZZZ CP 1
«— o DRAIN
— • — rr-r-r^,---- j
v /W
LP1
RP
:
^
<
CP2
,
1 LPS
1
3
—
CP2
CP1
i- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - « - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * - - - - - - - - - - - - - - - - - - - - - - - - - • - - - - - - - - - - - - - - - -
j LP2
J
6
Figure 3.8 GaAsFET Package Equivalent C ircuit Model.
The input and output parasitic shunt capacitances and series inductances give the package
a low pass filter characteristic reducing high frequency perform ance o f the device. For
sim ulation and analysis, the FET in the center o f the model is replaced with either the
sm all-signal G aA sFET model or nonlinear G aA sFET m odel.
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50
3.5 Printed Circuit Board (PCB) Effects
The printed circuit board (PCB) layout significantly im pacts the perform ance o f
any microwave design. Every PCB trace, w hether embedded (m ulti-layer or stripline) or
single-sided (m icrostrip), has parasitic capacitance and inductance. The ratio o f
capacitance and inductance determines trace im pedance to the m icrow ave signal.
The selection o f the PCB substrate is often determined b y price, dielectric
constant, and required thickness. G lass-epoxy substrates are relatively inexpensive but
often have inconsistencies preventing design repeatability. Polytetrafluoroethylene
(PTFE)-based substrates are the most expensive but are very consistent and low-loss for
microwave applications. Each substrate m aterial has a unique dielectric constant, or
permittivity. The am ount o f capacitance and inductance per unit trace w idth and length is
determined by substrate dielectric constant and thickness. H igh-perm ittivity substrates
are desired for com pact designs since signal w avelength is inversely proportional to the
square root o f the perm ittivity and effective capacitance is proportional to permittivity.
However, low-permittivity substrates are b est for circuits utilizing m ostly discrete
components. The PCB lands for placing the discrete components add parasitic
capacitances and inductances to the circuit. U sing a lower perm ittivity substrate
minimizes these parasitic elements.
The layout o f individual circuit traces m ust be carefully designed to avoid
contributing excessive parasitic capacitance and inductance to the circuit. W hen bending
a trace carrying a m icrow ave signal, the trace m ust be com pensated to avoid excess
capacitance at the bend. Either a miter cut on the trace or an arc w ith a large radius may
be used to maintain constant impedance across the bend. Equation (46) is used to
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51
calculate the optimal 90° m itered bend length for constant im pedance and m inim al signal
reflection [29].
-l.35w/h-
L = V2(1.04 + l . 3 e ' 35w/h)w (mils)
(46)
The trace w idth is w, and the substrate thickness is h. The effective length o f the miter
bend is a function o f th e m iter length [29].
I = L/V2 (m ils)
(47)
A rule o f thumb for com pensating a 90° bend in a trace w ith an arc is to m ake the arc
radius at least 4 times th e thickness o f the substrate. H owever, the physical size o f the
arc is very large, prohibiting its usage in com pact designs. Optim ized charts and
equations are available to com pensate arbitrary angle trace bends [29].
Pow er splitters and combiners and m icrostrip im pedance matching netw orks often
have several steps in trace width. Each step in trace w idth introduces a parasitic low-pass
filter effect w ith series inductance and shunt capacitance. Compensating the step with a
linear taper moves the trac e’s inherent capacitance gradually into fringing capacitance,
keeping the trace im pedance constant to the end o f the taper [29], The desired impedance
change o f the step is m aintained while the parasitic elem ents associated w ith the step are
minimized.
High im pedance m icrostrip and stripline traces are m ade very narrow to maximize
the inductance to capacitance ratio. Utilizing thin copper cladding further increases trace
im pedance since the cross-sectional area o f the trace is reduced. The copper clad
thickness is specified as w eight in ounces per square foot. The standard copper clad
thickness and resulting trace thickness are given in Table 3.3 [30].
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52
Copper Clad Trace Thickness
(oz/sq.ft.) (mils) (microns)
0.25
0.35
8.75
0.5
0.7
17.5
1
1.4
35
2
2.8
70
Table 3.3 PCB C opper Cladding and T race Thickness.
Thin copper cladding increases im pedance for a given trace w idth and makes detailed
etching easier but reduces the trace’s current carrying capacity. The maximum current
capacity o f a trace is determ ined by the allowable tem perature rise o f the trace on the
substrate. Too much current on a narrow trace may cause substrate breakdown or peeling
o f the trace from the substrate. For DC circuits the m axim um DC current capacity o f a
trace m ay be approxim ated w ith maximum current equations for a round wire with
com parable cross-sectional area. In microwave circuits PCB traces m ust be capable o f
carrying the necessary D C current and/or peak microwave current. A design margin
should always be used since the m icrowave current will concentrate toward the outer
surfaces o f the trace due to the skin effect. Figure 3.9 show s trace w idth versus crosssectional area and m axim um current capacity versus cross-sectional area for given
tem perature rises o f the trace above ambient temperature [31].
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53
Encapsulated Conductor
20 0
150
12 5
100
©
Q.
E
CO
C
afc>
3
o
50
30
20
0
1
5 10 2 0 3 0
50 70 100
150
200
300
400
500
700
Cross-section (square mils)
Conductor Width (w) vs Cross-section
100
200
300
400
0
1
5 10 2 0 30
50 70 100
150
200
300
400
500
700
Cross-section (square mils)
Figure 3.9 PCB T race Cross-Sectional A rea and C urrent Capacity.
The current capacity versus trace cross-sectional area graph in Figure 3.9 shows
tem perature rise curves for embedded, or internal, traces such as those used in stripline
designs or m ulti-layer PCBs. During the PCB fabrication process, all external traces are
plated over during the via electroplating process. T hese traces are tw ice as thick as the
original copper traces and therefore have twice th e cross-sectional area and higher current
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54
capacity as show n in Figure 3.9 [31 ]. Since external traces are electroplated during the
PCB fabrication process to plate vias, the plating is tw ice as thick as the original copper.
Maintaining the continuous operating temperature o f the traces below 125 °C is
recommended for highest reliability [32]. For an am bient tem perature o f 25 °C, the
allowable trace tem perature rise w ould therefore be 100 °C.
The m anufacturing tolerance o f a narrow trace m ust be tightly controlled for
design repeatability. For example, a 75 Q trace on a 25-mil thick substrate with relative
permittivity o f 10.2 requires a trace w idth o f 7.4 mils. If the m anufacturing tolerance o f
that trace is ±3 m ils, the impedance m ay vary from 67 Q to 91 f2. Large trace impedance
variations m ay m istune a microwave PA or cause instability.
Plated-through holes, or vias, are often used to connect opposite side PCB traces,
top side traces to bottom ground plane, or connect signals on different layers o f multi­
layer PCBs. A via is a cylindrical hole drilled through the substrate w hose entire surface
is coated with a specified thickness o f conductive plating. The circuit model o f a via is
two shunt capacitors w ith a series inductor in between. The im pedance o f the via
depends on the cylinder geometry. The inductance is dominated by cylinder diameter
and length. T he capacitances depend on the size o f the connecting pads on the two
interconnected layers and the substrate thickness and permittivity. W hen a via is in series
with the signal path, its characteristic im pedance should be the sam e as the traces it is
connecting. T he characteristic im pedance o f a via is found with the lossless transmission
line im pedance equation where L and C are the inductance per unit length and
capacitance p e r unit length [29],
Z 0 = V(L/C) (Q )
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(48)
55
Vias are most co m m o n ly used for grounding in microwave PA design. W hen vias are
used for connecting to the ground plane, the inductance o f the via m ust be m inim ized and
accounted for in th e design. The following equation m ay be used to approxim ate via
inductance [29].
L = po[Aln {(A+V(r2 +/»2 ))/r} + l .5 {r-+V(r2+/i2)}]/27t (H enries)
Po is the free space perm eability ( 4 7 t x l 0
'7
(49)
H/m), h is the substrate thickness, and r is the
radius o f the via. A ru le o f thum b for approximating via inductance is 10 nH /inch o f via
length (h) [2 2 ].
In discrete com ponent circuits where via inductance m ust be m inim ized, the via
should be placed d irec tly in the m ounting pad o f the com ponent. T he via location in the
pad should place th e via center directly under the center o f the chip com ponent end cap.
M ultiple vias m ay be used in a single pad to reduce inductance since inductance divides
in parallel.
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56
CHAPTER IV
H igh-E fficiency Shared-Current M icrow ave PA Design
The inform ation presented in Chapters I, II, and III is used to design a highefficiency shared-current m icrowave PA in the 4.5 - 4.8 G H z m ilitary telemetry
frequency band. PA perform ance specifications are given and a complete circuit is
designed and sim ulated. An earlier high-efficiency shared-current microwave PA
utilizing the same technology presented in this chapter was designed in the 2.2 - 2.4 GHz
m ilitary telem etry band with successful results [33].
The high-efficiency shared-current microwave PA is intended to be the basis for a
new product line o f low-cost 4.5 - 4.8 GHz miniaturized airborne telemetry transmitters.
As allocated telem etry frequency bands have become overcrow ded, much interest has
developed in highly efficient modulation schemes and/or higher frequency bands.
Conventional transm itters utilize pow er devices with low unity gain frequencies,
prohibiting efficient transm ission in higher bands. Inefficient DC to RF power
conversion and h igher propagation loss due to higher frequencies have limited telemetry
system operation in the 4.5 - 4.8 GHz band.
Telem etry transm itters consist o f a frequency agile phase-locked loop followed by
driver amplifiers, a final am plifier, an isolator, and a harm onic filter. The final am plifier
consum es the vast m ajority o f supplied pow er in any com m unications system. Improving
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57
the efficiency o f the final am plifier significantly benefits th e telem etry system
perform ance in m any ways. The focus o f this chapter is developm ent o f the highefficiency m icrow ave PA according to the design specifications given in Section 4.1.
The PA utilizes series-biased GaAsFETs in a shared-current configuration to optimally
utilize the available supply voltage while minimizing current draw. Conventional 28 V
S-band (2.2 - 2.4 G H z) telem etry transmitters for sim ilar applications draw 1.8 Amps for
5 W atts m inim um output pow er and 3.3 Amps for 10 W atts m inim um output pow er [34],
The goal for the new telem etry transmitter design is utilization o f the high-efficiency
shared-current m icrow ave PA to achieve the same current draw as conventional 5 Watt
transm itters w hile doubling both the output power to 10 W atts and operational frequency
to 4.5 - 4.8 GHz.
4.1 Design Specifications
The required perform ance specifications are derived from product line goals and
military telem etry equipm ent standards.
Performance Specifications:
Operational Bandwidth:
1 dB C om pressed O utput Power:
1 dB C om pressed Gain:
Pow er V ariation:
A m plification Mode:
Input V SW R:
O utput V SW R:
Impedance:
Harmonic Em issions:
Spurious Em issions:
Pow er-A dded Efficiency:
Efficiency:
Incidental FM :
Incidental AM :
4.5 - 4.8 G H z
10 Watts N om inal
8 dB Nom inal
±1 dB, All C onditions
Continuous W ave (CW )
1.5:1 M axim um
1.5:1 M axim um
50 Q Nom inal
-30 dBc M axim um
-60 dBc, 100 M H z to 4th Harmonic
35% Nominal
40% Nominal
5 kHz pk-pk M axim um
5% M axim um
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58
Environmental C onditions:
Tem perature:
Vibration:
°C to +70 °C
14 Grins, 20 Hz to 2 kH z Random
-2 0
Physical Characteristics:
Dimensions:
Weight:
2.2” x 1.98” x 0.25” M axim um
2.5 oz. M axim um
Power Supply:
PA Supply Voltage:
PA C urrent Draw:
23V Regulated
1.2 Am ps M axim um
The PA must pass all perform ance specifications and pow er supply current draw at room
temperature (+25 °C) and during exposure to the above environm ental conditions.
4.1.1
T ransistor Selection and PA Topology
Selecting the m icrow ave transistor w ith highest pow er-added efficiency in the 4.5
- 4.8 GHz frequency band m axim izes the PA pow er-added efficiency. The DC bias
network, decoupling network, chokes, impedance m atching netw ork, pow er splitter and
com biner, transistor m ounting, and PCB are then designed to satisfy th e performance
specifications and physical characteristics.
Referring to Section 2.3.2, DH-PHEMTs are the m ost efficient amplification
devices for frequencies above 3 GHz. However, the gate-drain breakdow n voltage lim its
the supply voltage to approxim ately
8
V, and the depletion m ode n-channel devices
require a negative gate-source bias. The available supply voltage in th e telemetry
transm itter is regulated +23 V. The 15 V supply difference m ay be overcom e one o f
three ways. The least efficient approach is to linearly regulate the 23 V supply to
8
V. In
this case the pow er dissipated by the regulator would be extrem ely high, and the PAE
specification could not be met. A negative supply voltage is also required for gate-source
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59
bias. F or PAE o f 35% nominal w ith a 23 V supply, the transistor would have to be more
than 100% efficient when linearly regulated to
8
V. The second approach is to utilize a
sw itching regulator that converts pow er consum ed from the 23 V supply to pow er
available at
8
V less switching and regulation losses. A switching regulator is certainly
m ore efficient than a linear regulator. However, the switching action introduces spikes
onto the pow er lines which create spurious signals at the PA output. A negative supply
voltage is again required for the gate-source bias. Also, a switching regulator is relatively
large and expensive, making this approach not w ell suited for low-cost, m iniaturized
transm itters. The third approach is utilizing series-biased DH-PHEM Ts stacked in a
shared-current arrangement as show n in Figure 4.1.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
V
V
Mf
n>
156V
i
i
PO W E R
; SPLITTER
j
o
|
Mr
i
V
♦: 8 2 V
PO W E R
COM BINER i
M-
m
M!
= MATCHING N E T W O R K
A
}
\7
\7
Figure 4.1 Basic Shared-Current M icrowave PA Utilizing G aA sFETs.
The shared-current arrangement efficiently utilizes the available supply voltage without
introducing regulator losses, introducing spurious signals, exceeding D H -PH EM T
voltage ratings, and requiring a negative voltage source. The number o f devices stacked
in the circuit introduced in Figure 4.1 m ay be increased to however m any devices are
required to split a power supply voltage without exceeding device bias m axim um ratings.
The three devices essentially are in series for DC purposes and in parallel for microwave
purposes. The drain-source voltage o f the devices depends on the num ber o f devices
stacked, the supply voltage, and the quiescent gate-source voltage required for proper
class operation.
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61
V Ds
V g sq
=
(V p S -|V G S Q |)/n
(Volts)
(50)
is the required quiescent gate-source voltage (negative), VPS is the applied supply
voltage, and n is the num ber o f devices in the shared-current stack. For example, if the
quiescent gate-source bias to achieve the desired class operation is -0 .8 V and there are 3
devices stacked as in Figure 4.1, the drain-source voltage o f each device is (24-0.8)/3 =
7.4 V. The selected P A Class and DH-PHEM T characteristics determ ine the required
gate-source bias. T h e bottom device is self-biased with the gate choke to ground and the
source resistor to ground. Operational am plifiers (opamps) set the gate-source bias o f the
m iddle and top devices. In the above exam ple, the three devices w ill have equal drainsource voltages if th e gate-source voltages are equal. Adjusting the opam p circuits to
provide a gate potential 0.8 V lower than the source potential for the top two devices
results in equal bias o n all devices in the stack assum ing the Id/V gs characteristics o f the
devices are similar. F o r m icrowave signal am plification, decoupling capacitors and
chokes isolate adjacent devices in the stack. T he microwave input pow er is equally split
three ways, separately am plified, and com bined equally. The individual elements are
selected, and the entire circuit is designed in Sections 4.2 through 4.8.
The selected transistor m ust be capable o f producing at least one-third o f the
required PA output p o w er with 35% PAE w hen biased with approxim ately 7.4 V. A
thorough search o f all D H-PH EM T m anufacturers and their devices results in the
selection o f Excelics Sem icondutor’s EPA 720A-180F as the transistor best suited for the
requirem ents. The EPA 720A -180F is a A lG aA s/InG aA s D H-PH EM T w ith a 0.4x7200
m icron mushroom gate. Excelics Sem iconductor lists the following perform ance and
characteristics in the d evice data sheet [35].
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62
Parameter:________________________Typical:_____________ Test Conditions______
ldB Com pressed Power (Pijb):
3 7 . 5 dBm (5.6 W)
8 V, Id = 0 . 5 x I d s s
ldB Com pressed Gain (Gmb)
1 2 dB
4 GHz
Power-Added Efficiency (r]pAE):
52 %
2 GHz
Saturated Drain Current ( I d s s ) :
2160 mA
VDS = 3 V, V Gs = 0 V
Transconductance ( G m ):
2280 mS
VDS = 3 V, V GS = 0 V
Pinch-off Voltage (VP):
-1.0 V
V Ds = 3 V, ID = 22 mA
Drain Breakdow n Voltage (BVgd): -15 V
IGD = 7.2 m A
Source Breakdown V oltage (BV gs): -14 V
IGD = 7.2 m A
Thermal Resistance (0jc):
6 °C/W
The following maximum absolute and continuous ratings are also given in the device data
sheet [35].
Parameter:
Drain-Source Voltage (V DS):
G ate-Source Voltage (VGS):
Drain Current (IDS):
Forward G ate Current ( I G s f ):
Input Power (P m):
Channel Temperature (TCh):
Storage Tem perature ( T s t G):
Total Power Dissipation (P t):
Maximum:
12 V
-8 V
I dss
360 mA
35 dBm
175 °C
-65/175 °C
23 W
Continuous:
8 V
-3 V
1.6 A
60 m A
@ 3 dB Compression
150 °C
-65/150 °C
19 W
For m odeling purposes, a linear small-signal m odel, nonlinear Curtice-Ettenburg model,
and 180-mil flanged package m odel are given b y Excelics Semiconductor.
4.2 DC Bias Network Design
4.2.1
T ransistor Bias Point
The EPA720A-180F D H-PH EM T is designed for common source C lass A or A/B
operation. The device is inherently linear and m ost efficiently operates in C lass A/B. A
review o f class definitions and efficiencies is presented in Section 1.2.8. A typical bias
point for Class A/B devices is quiescent drain current equal to 10% to 40% o f the
saturated drain current loss [36]. T he bias point is selected at 40% o f IDss to maximize
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63
gain and output pow er w hile maintaining the higher efficiency o f C lass A/B operation.
The typical loss o f the EPA720A-180F is listed as 2160 mA. The self-bias circuit in
Section 4.2.2 is designed to achieve quiescent drain current o f 860 m A (40% o f 2160
mA).
4.2.2
T ransistor Self-Biasing
G aA sFETs require a negative gate-source voltage since they are depletion mode
JFET devices. N egative gate-source bias is conventionally achieved b y grounding the
device source and applying a negative gate voltage to the gate through an RF choke. The
PA circuit show n in Figure 4.1 achieves negative gate-source bias on all devices without
the use o f a negative voltage source. The gate o f the bottom device is connected to
circuit ground though an RF choke. W hen voltage is applied to the circuit, the drain
current through the stack creates a source potential across the resistor connecting the
source o f the bottom device to circuit ground. The gate-source voltage o f the bottom
device is equal to the negative o f the source potential o f that device.
V gsi
= “Vsi = - I d R s (Volts)
(51)
Rs is the resistor connecting the source o f the bottom device to circuit ground.
G aA sFET drain current is constant in a Class A amplifier. A pplying a microwave
signal o f any pow er level to a Class A PA does not change drain current since the device
is biased to conduct for 360° o f the input signal. However, because o f reduced
conduction angle, drain current increases in a Class A/B amplifier w hen an input
microwave signal is applied and the devices am plify the signal. Due to this current
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64
change the determ ination o f the source resistor (Rs) is a two-step procedure for Class A/B
amplifiers.
First th e drain current versus gate-source voltage characteristic curve must be
measured for the device. The gate-source voltage that results in the desired quiescent
drain current is determ ined from this Id/V gs curve. For the EPA 720A -180F the measured
-1.2 -1.2
-1
-0.9 -0.8 -0.8 -0.7 -0.6 -0.6 -0.5 -0.5 -0.4 -0.4 -0.3 -0.2 -0.2 -0.1
-0
Gatc-Source Voltage (V)
drain current versus gate-source voltage characteristic curve is plotted in Figure 4.2.
Figure 4.2 M easured Drain C urrent vs. Gate-Source V oltage.
The desired quiescent drain current
( I dq
= 860 mA) is achieved w ith a gate-source
voltage o f approxim ately -0 .5 V. The pin ch o ff voltage (Vp) is approxim ately - 1 ,2V.
The next step in calculating
Rs
is to find the “operational” drain current
(I d)
the device is am plifying in Class A/B. Solving the G aA sFET PAE equation for DC
current results in operational drain current.
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when
65
Id = Pom(l - 1/G )/(V dst| pae) (Amps)
(52)
PA E must be expressed as a decim al in Equation (52). For the EPA 720A -180F the
calculated Vds and expected Pout, G, and q PAE are used to solve for ID. W ith 23 V applied
to a stack o f 3 devices and 0.5 V required on the source o f the bottom device, Equation
(51) is used to calculate V Ds = (23 - 0.5)/3 = 7.5 V. The expected gain o f the EPA720A180F at 4 GHz is approxim ately 12 dB. For 4.5 - 4.8 GHz, a gain o f 8 dB is
conservatively estim ated.
8
dB is 108' 10 = 6.31 numerically. To achieve nom inal PA
output power o f 10 W , each device must output at least 3 1/3 W (35.23 dBm ). To
account for impedance m atching network losses, com biner network losses, and connector
losses approximated at total o f 0.3 dB, the output pow er from each device m ust be
approxim ately 3.6 W (35.53 dBm). The PAE o f the EPA720A-180F is specified as 52%
at 2 GHz. To account for gain reduction at higher frequencies, the PAE at 4.5 - 4.8 GHz
is estimated as 35%. U sing these numbers the operational drain current is calculated as
Id = 3.6(1 - 1/6.3 l)/(7.5x0.35) = 1.15 A.
Resistor Rs is calculated by dividing the required gate-source voltage by the
operational drain current.
(53)
Rs = |V GSq |/ I d ( f i )
F or the EPA720A-180F device, Rs is determ ined to be 0.5/1.15 = 0.44 Q . The power
dissipated in resistor Rs m ust be determined under operational conditions.
P rs - V s i I d - |V g s q |I d
(W atts)
(54)
T he pow er dissipated in resistor Rs is 0.5x 1.15 = 0.575 W. Two Vi W, 1.0 Q resistors in
the
2 0 1 0
package size connected in parallel satisfy the requirements o f Rs-
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66
P rovided the assumptions m ade in calculating Rs are accurate, the EPA720A180F will b e biased at a quiescent point (q-point) o f V
Gs q
= -0.5 V and
Id q
= 860 mA.
This is o n ly true w hen an input m icrow ave signal is applied and the device is amplifying.
Although th e operational drain current is larger than the quiescent drain current, Rs is
calculated so that the device is at the desired q-point (q-pointRF) under operational
conditions. W ith no applied input signal, the devices draw less current and the voltage
across Rs decreases resulting in a shifted q-point (q-pointoc)T he shifting o f the q-point has as chain effect on the devices w hen they are
stacked as in Figure 4.1. Since Vsi is lower w hen the device is not am plifying, VGsi is
higher resulting in reduced drain-source channel resistance. Lowering the channel
resistance o f the bottom device results in a low er voltage drop across the device (reduced
VDSi) if the current were kept constant. Since the middle device source is connected to
the bottom device drain through a choke, the potential o f those device term inals is the
same. W hen Vdsi decreases, the source potential o f the middle device (V s:) also
decreases, resulting in a higher V Gs 2 since the opam p bias circuit keeps VG: constant.
Increasing V GS: results in the channel resistance o f the middle device decreasing as well.
The q-point o f each device is shifted all the w ay up the stack. The shared-current stack
has a natural tendency to nearly balance the drain-source and gate-source bias o f the
devices w ith o r w ithout an applied input signal. The net effect o f the q-point shift is an
approxim ately equally increased VG$ and V Ds o f each device. Since VGs is increasing on
each device, the q-pointoc o f the devices will always result in a higher drain current than
would q-pointRF. As long as the gate-source voltages o f the devices are approxim ately
equal and th e Id/VGs characteristics are similar, the drain-source voltages o f the devices
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67
will also be equal. With no applied input signal, VSi is reduced. S in ce VGsi = -VSi,
Equation (50) requires the drain-source voltage o f each device increase. For the circuit in
Figure 4.1, the drain-source voltage o f each device increases by approxim ately one-third
the decreases in Vsi w hen the q-point shifts from q-pointRF to q-pointoc. The drainsource voltages decrease b y the sam e amount when the q-point shifts from q-pointoc to qpointRf. The change in drain-source voltage due to q-point shifting is on the order o f a
tenth o f a volt per d evice since Vs does not change significantly. S in ce the DH-PHEMTs
are biased at V DS = 7.5 V, small increases in Voscannot create an “over-bias” condition
that may dam age the d evices or reduce their reliability.
The gate voltages o f the upper devices must be set such that th e gate-source
voltages o f all devices are equal.
VGk = V sk - |V Gs q | = (k -l)V Ds (Volts)
(55)
The range o f index k is k = 2 .. .n, where k=2 represents the second device up the stack and
n represents the top device. For the circuit shown in Figure 4.1, the m iddle and top
devices must have gate voltage bias circuits.
VG 2
=
Vs 2
- 1VGs q |
V G,3 = V s 3 -
|V g $ q |
=
V ds
(V olts)
= 2Vps (V olts)
(56)
(57)
For the stack o f EPA 720A -180F devices, V G 2 = 7.5 V and V G3 = 2(7.5 V) = 15 V.
Figure 2.1 shows G aA sFET gate current may be bi-directional depending on input
drive power level. A n opam p configured as a buffer, or voltage follow er, is chosen for a
stable gate bias circuit. W hen biased w ith the buffer circuit, the gate voltage applied to
the gates o f the top two devices will be stable regardless o f gate current direction or
magnitude. A resistive voltage divider serves as a reference for the buffer as shown in
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68
F igure 4.1. A potentiom eter may be included between the resistors in the voltage divider
to allow adjustability o f the gate voltage. D ifferences in the Id/V Gs characteristics o f the
devices m ay require the gate bias o f the upper devices be adjusted slightly to balance the
drain-source voltage o f all devices. A recent purchase o f EPA720A-180F devices from
th e sam e w afer indicated a range o f saturated drain currents
(Id ss)
from 2040 m A to 2400
m A . Since loss is part o f the device I d/V gs characteristic curve, the gate bias voltages
n eed adjustm ent to ensure equal drain-source voltages across each device.
The resistors and potentiometer in the gate bias circuit may be conservatively
calculated by assum ing the source voltage o f the upper devices remains constant while
th e gate voltage is adjusted. The resistor and potentiom eter values m ay be relatively
large to reduce the current draw o f the divider. The adjustable voltage divider m ust be
calculated to ensure adjustm ent o f the potentiom eter can never result in forw ard biasing
th e G aA sFET gate-source Schottky diode or pinching o ff the device. Also, for m axim um
adjustability the gate voltage should be in th e m iddle o f this range with the potentiom eter
s e t at the center o f its tuning range. These th ree conditions combine to produce a set o f
th ree equations w ith three unknowns.
Vsk ^ Vps(Rik + R 2 k)/(Rik + R-2 k + R-3 k) (Volts)
V Sk - |V p |< V p SR lk/(R lk + R2k + R 3k)
(Volts)
Vsk - |Vp |/2 = Vps(Rik + R2 k/ 2 )/(R ik + R2k + R3O (Volts)
(58)
(59)
(60)
Vps is the pow er supply voltage, Rlk is the resistor connecting to ground, R 2 k is the
potentiom eter, R 3 k is the resistor connecting to the pow er supply, and k is the sam e index
as in Equation (55). The equations m ay be solved by matrix algebra o r by choosing a
standard value for one com ponent and solving for the other two. Since potentiom eters
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69
are m ost readily available in a limited num ber o f values, a value o f 5 kQ is selected for
R 22 and R 2 3 . A ny two o f Equations (58), (59), and (60) may then be selected to solve for
the tw o resistors. R 12 is 28.3 kQ , R 32 is 62.5 kQ ,
R
13
is 59.0 kQ , and
R
33
is 31.0 kQ. If
resistors R 12 and R 32 are chosen as 28.0 kQ (1% ) and 62 kQ (5%) respectively, then 6.78
V < V G 2 < 7.99 V as 5 kQ potentiom eter R 22 is adjusted. If resistors R 13 and R 33 are
chosen as 59.0 kQ (1%) and 30.9 kQ (1%) respectively, then 14.30 V < V G 2 ^ 15.51 V as
5 k Q potentiom eter R 23 is adjusted. The resistance between the 23 V supply and ground
is approxim ately 95 kQ for each voltage divider, resulting in a current draw o f 0.24 mA
each. The pow er dissipated in each resistor and potentiom eter is on the order a few
m illiW atts. 0603 resistors are selected.
The opam ps biasing the upper device gates m ust be capable o f operating with a 23
V supply and must have very low output noise. Any noise introduced into the gates o f
the devices will induce incidental am plitude m odulation (IAM) and phase noise due to
A M -to-PM conversion. M odulating the gate voltage o f the devices causes variations in
VGS and Vds- A small surface m ount package is also desired since the PA must be
com pact.
T he M icrel M IC 6211 IttyBitty Operation Amplifier is selected for the gate bias
circuits. The M IC 6211 com es in a compact 5-pin SOT-23-5 package and operates with a
supply voltage up to 32 V over a temperature range o f -4 0 °C to +85 °C. W ith a single­
ended supply, the M IC 6211 is capable o f sinking or sourcing 40 mA. The typical
quiescent current draw o f the M IC 6211 is 1.2 mA. The output noise voltage is less than
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70
4 |iV peak-to-peak from 0.1 Hz to 10 Hz and less than 10 fiV peak-to-peak for all other
noise frequencies [37].
The opamp bias circuits m ust connect to the gates o f the upper devices.
Broadband chokes, designed in Section 4.4, connect the bias circuits to the device gates.
M ultiple decoupling capacitors are connected from the choke to ground on the opamp
side o f the choke. T he M IC 6211 opam p output is short circuit protected to prevent
dam age or ringing on the opam p output at startup when the capacitors appear as a short
circuit to ground. The choke provides a very high im pedance at m icrow ave frequencies
to prevent the m icrow ave signal from getting onto the DC bias lines. W hat little signal
passes through the choke is shunted to ground with the decoupling capacitors. The
decoupling capacitors are selected to reduce low-frequency noise from the opamp,
prevent intermediate frequency ringing, and provide m icrow ave decoupling. The
selected decoupling capacitor values and types are 1 pF tantalum (25 V minimum rating),
1 nF ceramic, and 5.6 pF porcelain, respectively. The value o f the porcelain microwave
decoupling capacitor is chosen so that its capacitance and parasitic inductance and the
parasitic inductance o f the PCB via to ground are series self-resonant in the 4.5 - 4.8 GHz
range. This subject is discussed in much greater detail in Section 4.3 w here the
decoupling capacitor netw orks are designed.
For a self-biased device, adding a resistor between the gate choke and ground may
help stabilize the device at low frequencies and prevent excess gate current sinking or
sourcing [12]. For a device rated at approximately 60 mA m axim um gate current, the
recommended value o f gate resistance is 100 Q [38], A 100 Q resistor is inserted
between the gate choke and ground for the bottom device and betw een the gate choke and
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71
opam p output terminal for each o f th e upper devices. To maintain equal impedances at
the gate o f each device, three decoupling capacitors o f the same values discussed above
are attached from the point between the choke and resistor at the bottom device gate
circuit and circuit ground.
A resistor-capacitor (RC) low pass filter is inserted in the pow er supply line to the
opam p. The filter suppresses opam p noise and prevents ringing. A series 22 Q resistor
and shunt 10 nF ceramic capacitor provide opam p pow er line filtering.
4.2.3
T urn-O n Tim e Issues
The supply voltage must be applied to a p o w er GaAsFET in the proper sequence
to avoid dam aging the device. In a conventional G aA sFE T bias circuit, the negative gate
voltage is applied before the positive drain voltage to avoid forward biasing the device.
A self-bias circuit must provide the sam e protection for reliable operation.
In the circuit shown in Figure 4.1, all devices are self-biased. T h e current through
the series-stacked devices is determ ined by the resisto r (Rs) between th e bottom device
source and ground. The source resistor prevents forw ard biasing o f the gate-source
Schottky diode and also provides surge current protection.
All devices are biased at V Gs = 0 V at startup since there are no supply voltages
applied to the circuit. At V Gs = 0, the channel resistance is minimal. W hen the supply
voltage is applied to the stack, current runs through all devices and self-biases the bottom
device as the source potential rises. A s soon as th e bottom device’s source potential
increases, its channel resistance increases and drain-source voltage increases. Since the
drain voltage o f the bottom device increases, the source voltage o f the m iddle device
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72
increases. For reliable operation the gate voltage increases slightly after the source
voltage so that the device is always biased with VGs < 0 V. The opam p circuit will have
a slow er response tim e than the series FETs since the opam p is a complicated IC having
num erous internal devices and capacitances. The RC tim e constant created by the 100 Q
series resistor and decoupling capacitors also helps slow the response to ensure negative
gate-source biasing. F or the EPA720A-180F gate bias circuit, the tim e constant is 0.1
msec (100 f i x 1 pF). A t the same time the source voltage o f the middle device
increases, the source voltage o f the top device increases since the channel o f the middle
device has very low resistance. The opamp circuit biasing the gate o f the top device has
the sam e response tim e as the circuit biasing the gate o f the m iddle device so that both
devices bias at the sam e tim e without allowing a gate-source forward bias condition to
occur. The voltage increase per unit time at the output o f the opam p bias circuit for the
top device is greater than that o f the bias circuit for the m iddle device since the steadystate voltage m ust be higher on the top device gate. This m ay cause a problem for
shared-current stacks w ith many devices as the gate voltage o f the very top device m ay
increase faster than the voltages up the stack increase to bias that device’s source. The
RC tim e constants o f the upper devices’ opamp output circuits m ay be increased to
com pensate for the bias delay up the stack.
The rise tim e o f the power supply voltage m ust be slow er than the response tim e
o f the opam p gate bias circuits. If the rise time is faster, voltage is applied to the stack
before the gates are biased, resulting in the upper devices being biased below pinchoff
(high source voltages, low gate voltages). The voltage drop across the channel is
therefore very high and m ay exceed the device drain-gate breakdow n voltage. Ensuring
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73
the gate bias circuits respond faster than the m inim um pow er supply voltage rise time
avoids this potentially destructive condition.
4.3 D ecoupling N etwork Design
The capacitors between the device sources and ground in Figure 4.1 represent the
decoupling network. The GaA sFET source is conventionally connected directly to
ground. For optim al perform ance o f self-biased devices, the decoupling network must
m inim ize the im pedance between the device source and ground at the m icrow ave
frequencies o f operation.
4.3.1
C apacitor Series Selection
The m inim um series im pedance o f a capacitor occurs at the series self-resonant
frequency
( F s r ).
The impedance o f a capacitor at
F sr
is equal to the equivalent series
resistance (ESR). Utilizing decoupling capacitors w ith m inim al ESR at their F sr results
in m inim al im pedance to ground.
The capacitor series used for decoupling at the 4.5 - 4.8 GHz frequency band is
A m erican Technical Ceramics (A TC) 600S series porcelain 0603 chip capacitors. The
600S series capacitors are a high-Q , ultra-low ESR line o f microwave capacitors.
Perform ance plots in the 600S series data sheets show an ESR o f approxim ately 70 mQ
at 1 G H z for the capacitor values that are series self-resonant in the 4 - 7 G Hz frequency
range [39]. The individual values o f the capacitors are determ ined by sim ulations
perform ed in Section 4.3.4.
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74
4.3.2
Broadband Decoupling Design
A decoupling network m ay be made broadband by paralleling capacitors o f
different values and
dips at the
F sr
F sr.
The com bined im pedance o f the parallel capacitors w ill have
frequencies and small peaks between the dips as shown in Figure
4 .3 [ 2 2 ] .
£
■S
Target Impedance
100m
E
10m
1GHz
100MHz
Frequency (Hz)
v
v'
100m
10m
100MHz
1GHz
Frequency (Hz)
Figure 4.3 Im pedance o f Parallel Capacitors w ith Different R esonant Frequencies.
The top plot in Figure 4.3 shows the impedances o f tw o different capacitors, represented
by the thin and dashed lines, and their com bined im pedance represented b y th e wide line.
The bottom plot shows the same effect for three different capacitors w ith th e thin dashed
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75
lines representing the individual capacitor im pedances and the thick line representing the
com bined impedance.
R eferring to the top plot o f Figure 4.3, a peak occurs in the com bined impedance
curve betw een the two resonant frequencies that is higher than the im pedance o f either
capacitor individually. This “anti-resonance” betw een resonance points is due to one
parallel capacitor being capacitive and the other being inductive, creating a parallel
resonance circuit [22]. The anti-resonance effect is am plified by high-Q com ponents
w ith high parasitic inductance. In this case the dips are lower due to low E S R and the
peaks are higher due to high equivalent series inductance (ESL). Since high-Q capacitors
are desired to m inim ize ESR in decoupling networks, the inductance introduced by the
grounding vias m ust be minimized to reduce anti-resonance effects. Via inductance is
m inim ized by using thin substrates w ith large diam eter vias (high rih ratio) [22]. A nti­
resonance m ay also be minimized by utilizing m any capacitor values with m inim al
capacitance increments from one value to the next.
4.3.3
E SR M inimization
ESR is minimized by paralleling capacitors w ith the same F sr as show n in Figure
3.5. Paralleling series self-resonant capacitors divides the ESR ju st as resistance divides
in parallel. The num ber o f parallel capacitors required is typically determ ined by the
acceptable pow er loss in the decoupling network. For low-Q capacitors (high ESR), the
num ber o f parallel capacitors is often determ ined by the m axim um power dissipation o f
the individual capacitors.
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76
For the shared-current PA show n in Figure 4.1, the m axim um power loss in the
decoupling netw ork is chosen to be 10 mW (approximately 0.25% o f
P o u t)
for all
frequencies betw een 4.5 - 4.8 GHz. In practice the m axim um decoupling network ESR
across the operational frequency range is the largest value that d oes not cause device
input or output im pedances to change w hen the decoupling netw ork is connected.
Equations (34) an d (35) are used to solve for the maximum decoupling network ESR.
The current required to provide 3.6 W to a 50
load is determ ined with Equation (35) to
be V(3.6/50) = 268 mARMS. The m axim um decoupling network ESR is then determined
by solving E quation (34) for ESR. T he maximum ESR is (0.010/0.2682) = 0.139 Q =
139 m fi. The n u m b er o f parallel capacitors and the individual capacitor values are
determ ined in S ection 4.3.4.
4.3.4
D ecoupling Capacitor Values
To determ ine the decoupling netw ork response, a high-Q capacitor model is
created in E aglew are’s simulation program Genesys. The capacitor nominal value, ESR
at 1 GHz, F pr, and F Sr are collected from the ATC 600S series d ata sheet and entered
into the model. R eferring to the capacitor model in Figure 3.4, th e ESR at any frequency
is calculated b y G en esy s’ equation editor. Equation (33) is used to calculate the ESR at
frequencies other than 1 GHz. The ESL (Ls) is calculated by solving Equation (26)
where C and F sr are known, and Cp is calculated by solving E quation (36) where C, Ls,
and F pr are know n.
Each decoupling capacitor is connected to ground with a via. The chosen
substrate is R oger’s Corporation RO 4350 w ith a dielectric constant o f 3.48 [40], The
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77
substrate thickness and v ia diameter are chosen as 20 m ils and 31 m ils, respectively, to
m inim ize via inductance. Genesys simulations show the via contributes a parasitic
inductance o f approxim ately 85 pH. This inductance adds in series to the parasitic
inductance o f the chip c a p a c ito r resulting in a significantly low er com bined
F sr.
For
exam ple, a 7.5 pF A TC 6 0 0 S series capacitor has a series self-resonant frequency o f
approxim ately 5.7 G H z [3 9 ]. Equation (26) is solved for ESL = 0.1005 nH. The 85 pH
inductance for the gro u n d v ia is added, and the com bined F sr is 4.26 GHz. The via
inductance reduced the se rie s resonant frequency from 5.7 G H z to 4.26 GHz.
A circuit co n sistin g o f many values o f ATC 600S series capacitors in parallel,
each connected to a g ro u n d via, is optimized with G enesys to m inim ize decoupling
network ESR. The d eco u p lin g network is optim ized across the w ider bandwidth o f 4.4 4.9 GHz to account for c ap a cito r tolerances and sim ulation inaccuracies. Fourteen
capacitors are required to achieve an ESR less than 139 m Q across the 4.4 - 4.9 GHz
frequency band. The q u an tities and values are: (2) 6.8 pF, (4) 6.2 pF, (4) 5.6 pF, and (4)
5.1 pF. Two additional capacitors, 7.5 pF and 4.7 pF, are added to further extend the
decoupling network b an d w id th (frequency range for w hich ESR < 139 m Q ) to 4.02 - 5.36
GHz. The combined im p ed an ce o f the GaAsFET decoupling netw ork is shown in Figure
4.4.
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78
i
o
a>
i
s
i
9
.' oa
n o
n
jm o
m
«*»
aoo
sm o
yoo
ecu
med
Figure 4.4 Simulated Im pedance o f G aA sFE T M icrowave D ecoupling Network.
The m axim um decoupling network im pedance from 4.4 - 4.9 G H z is 111 m Q at 4.86
GHz.
The sixteen parallel ATC 600S series capacitors provide adequate decoupling o f
the device sources at the PA operational m icrow ave frequencies. Low and intermediate
frequency decoupling capacitors are also paralleled with the A TC capacitors. These
larger capacitors prevent lower frequency device oscillations and filter any lower
frequency noise that enters the PA from a noisy pow er supply. T he selected values and
capacitor types are 1 pF tantalum, 10 nF ceram ic, and 1 nF ceram ic. The tantalum
capacitor is polarized and m ust be rated for at least 23 V.
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79
The pow er supply decoupling circuit is connected betw een the pow er supply side
o f the choke on th e top device and ground. The low and interm ediate frequency
decoupling capacitors are selected as 1 pF tantalum, 100 nF ceram ic, 10 nF ceramic, and
1 nF ceramic. F our A TC 600S series capacitors, 5.1 pF, 5.6 pF, 6.2 pF, and 6.8 pF, are
chosen to shunt the m icrow ave signal that couples onto th e pow er supply lines. A
combined im pedance plot o f the pow er supply microwave decoupling capacitors is
shown in Figure 4.5.
4
a
1
ooo
<•60
Figure 4.5 Sim ulated Im pedance o f Power Supply M icrow ave Decoupling Network.
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80
The im pedance o f the power supply decoupling circuit is less than 0.5 Q across the 4.4 4.9 GHz frequency band. The frequency band across w hich the power supply decoupling
network ESR is less than 0.5 Q is 4.06 - 5.29 GHz.
The parallel self-resonance o f a m icrow ave capacitor may be shifted higher in
frequency b y vertically orienting th e capacitor as shown in Figure 4.6 [41].
INST'
Miorctri(Jine Conductor
When lie chip is mounted, the
loser moiting should appear
an one of lie verticil sides.
Figure 4.6 V ertical C hip C apacitor Orientation.
Positioning the capacitor as show n in Figure 4.6 reduces parallel resonance effects since
the capacitor plates are perpendicular to the m icrostrip conductor. Capacitors are
available w ith short microstrip leads configured for m ounting the capacitor in vertical
orientation [41].
4.4 Choke Design
The purpose o f a choke is to block a m icrow ave signal. Chokes are often used to
supply DC bias to a device while preventing m icrow ave signals from coupling onto the
DC supply lines. The function o f a choke is com plem entary to the function o f a DC
block. A choke passes DC and blocks the m icrow ave signal; a DC block passes the
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81
microwave signal and blocks DC. A minimum choke impedance o f ten tim es the circuit
characteristic im pedance (Z0) at the operational m icrow ave frequencies is required for
adequate signal isolation [42].
Chokes are required in the shared-current PA show n in Figure 4.1 to isolate
devices in the shared-current stack, to isolate the top device from the DC supply, and to
isolate the device gates from their bias circuits. Self-resonant inductors and quarter-wave
transformers decoupled at one end are most com m only used for chokes. Inductors
resonate with high im pedance at self-resonance. If a quarter-wave transform er is
decoupled at one end to create a microwave “short” to ground, the im pedance seen
looking into the o th er end is theoretically an open circuit. A microstrip radial stub that
projects a large capacitance to a single point may be used in place o f decoupling
capacitors to provide a m icrowave ground. Both a quarter-wave transform er and an
inductor with self-resonance occurring in the 4.4 - 4.9 GHz frequency range are evaluated
for the device drains. A physically smaller inductor w ith self-resonance betw een 4.5 4.8 GHz is selected for the gate chokes.
4.4.1
Q uarter-W ave Transform er Chokes
The im pedance o f a 75 Q quarter-wave transform er with one end grounded is
simulated from 4.5 - 4.8 GHz. The transformer is designed at 4.65 GHz, the center o f the
operational frequency band. The microstrip line dim ensions on the 20-m il thick RO4350
substrate are 21 m ils w ide by 398 m ils long.
Simulating the transform er with Genesys results in input im pedances at 4.5 GHz,
4.65 GHz, and 4.8 G H z o f 1021 £2, 9855 Q , and 1007 Q , respectively. T he transform er
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82
input impedance is m uch greater than ten times Zo from 4.5 - 4.8 Hz. T h e response o f the
transformer is com pared to the response o f a self-resonant inductor in Section 4.4.2.
4.4.2
Inductor C hokes
The Coilcraft 1606-10 Micro Spring A ir C ore inductor is evaluated for the drain
chokes. The nom inal inductance is 12.55 nH, and the minim um self-resonant frequency
is 4.6 GHz. The DC current rating o f the inductor is 1.6 A, which exceeds the 1.2 A
maximum PA specification [43],
The inductor m odel shown in Figure 3.2 and the element data given in [18] are
used to simulate the 1606-10 inductor with Genesys. The inductor data sheets indicate
minimum FSr o f 4.6 GHz. The simulation shows resonance at 6.22 G H z w ith inductor
impedance o f 2960 Q . The inductor impedances at 4.5GH z, 4.65 GHz, and 4.8GHz are
712 Q , 754 Q, and 877 Q , respectively. The sim ulation plot is given in Figure 4.7.
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83
v
.
ROD
.
«XC
t*x
«HO
0*3
STD
(OK
.
.
MX
.
IT O
M40
-V3C
Figure 4.7 Sim ulated Impedance o f Self-R esonant Inductor.
The im pedance o f both the quarter-wave transformer and 1606-10 inductor is greater than
ten times the circuit characteristic impedance o f 50 Q . Since the quarter-w ave
transform er im pedance is higher than the inductor impedance across the operational band,
the 75 Q quarter-w ave transform er is selected for the drain chokes.
T he C oilcraft 0603CS-15N 0603 chip inductor is chosen for the gate chokes. The
nominal inductance is 15 nH, and the minimum self-resonant frequency is 4.0 GHz. The
DC current rating o f this inductor is 700 mA, which is m uch higher than required for the
gate bias circuits [43].
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84
The gate c h o k e is sim ulated with Genesys using the same inductor model as is
used for the 1606-10 inductor. Simulated self-resonance occurs at 4.48 G H z where the
impedance is 6.45 k Q . The gate choke impedances at 4.5 GHz and 4.8 G H z are 6.41 kQ
and 2.72 kQ, respectively. The impedance o f the gate choke is m uch higher than the
required 500 Q from 4.5 - 4.8 GHz. The sim ulation plot is given in Figure 4.8.
■on
«ae
m
us
<so
«o
mco
m
h i
^
mod
♦ VMM
F igu re 4.8 Simulated Im pedance o f Gate Choke.
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85
4.5 Im pedance M atching Network
T he EPA 720A-180F DH-PHEMT must be im pedance m atched to the source and
load for stable operation, maximum power transfer, m axim um gain, and maximum
efficiency. However, before the matching networks are designed, the stability o f the
EPA 720A -180F is analyzed. For impedance matching, a nonlinear Curtice-Ettenburg
model is used to model the device to generate impedance d ata for the device under
operating conditions. The impedance matching network is optim ized for 1 dB
com pressed pow er and efficiency from 4.4 - 4.9 GHz. The EPA 720A -180F is im pedance
m atched across the w ider bandwidth to optimize perform ance across the narrower 4.5 4.8 G H z bandw idth.
4.5.1
Stability Analysis
T he EPA 720A -180F small signal S-parameters are used in the K-A test for
unconditional stability. Data is given for the device at 500 M H z intervals. The Sparam eters for the device at 4.0 GHz, 4.5 GHz, and 5.0 G H z are shown in Table 4.1 [35].
Frequency
(G H z)
4.0
4.5
5.0
|S .,|
0.845
0.825
0.814
T able 4.1
zs„
|Sj.|
Z S 21
IS.2 I
Z S 12
IS22 I
^S22
145.5
2.818
11.2
0.047
5.0
0.441
131.4
2.804
-6.8
-7.9
0.055
0.375
115.7
2.750
-23.2
-26.1
0.063
0.353
Sm all Signal S-Parameters for EPA 720A -180F.
117.9
96.0
69.3
|A| is found using Equation (13) and then inserted in Equation (12) to find K. The results
o f the K-A stability calculations are shown in Table 4.2.
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86
Frequency
(GHz)
4.0
4.5
5.0
|A|
K
0.444
0.404
0.408
1.09
1.11
1.09
T ab le 4.2 K-A Stability Calculations for EPA720A-180F.
Since the device satisfies |A| < 1 and K > 1 at all three frequencies, the device is
unconditionally stable from 4.0 to 5.0 GHz.
4.5.2
N onlinear Large Signal Transistor M odel
The nonlinear EPA720A-180F model is com prised o f a Curtice-Ettenburg
nonlinear m odel surrounded by 180-mil flanged package parasitics. The param eters for
the EPA720A-180F Curtice-Ettenburg model are show n in Table 4.3 [27].
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87
Parameter
3
Y
Vds0
Value
0.0244
Unit
1/V
1/V
2.16
V
4.25
V
-1.2
V to
2.34
A
Ao
A/V
A,
2.52
A
/V z
-2.45
a2
A/V*
-2.60
a3
Sec
3E-12
X
0
Q
R.
0
Q
r2
V
14
V bo
V
1
V bi
0
Q
Rf
A
9.75E-10
Is
N
1.2
34.3
Q
R ds
F
IE-8
C rf
0.167
Q
Rd
0.4
Q
Rg
0.09
Q
Rs
0
Q
R in
F
2.99E -11
C gso
F
1.07E-12
C gdo
0.5
Fc
F
1.14E-12
Cos
F
0
C gs
F
0
C gd
0
K f4
1
Af
°C
27
T nom
3
X ti
eV
1.11
EG
0
v
/° c
V T O tc
0
% /°c
P tce
1
F fe
nH
0.16
Ld
nH
0.06
Ls
nH
0.09
Lg
T able 4.3 Curtice-Ettenburg E PA -720A -180F Model Param eters.
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88
Inductances L d , L s , and L g represent the bond wire inductances from attaching the chip
transistor to the 180-mil flange package.
T he package model used to model the 180-mil flanged package is shown in
Figure 4.9 [44].
L p k g la
1 = 0 .1 7 2 nH
Lpkg3
L = 0 .0 7 9 nH
Lpkg2a
L=0 2 0 8 nH
Lpkg3a
1 = 0 0 7 9 nH
Lpkgl
L=0 1 7 2 n H
Lpkg2
L = 0 .2 0 8 nH
□ rain
G a le
_ _
C pkgl
C = 0 .4 0 8 pF
C pkgl a
C = 0 4 08 pF
C pdg2a
C =0 2 6 3 pF
C pkg2
C = 0 2 6 3 pF
S o u rc e
Figure 4.9 180-mil Flanged Package Model.
For sim ulation purposes, the drain terminal is connected to 7.50 V, the gate terminal is
connected to -0.5 V, and the source terminal is connected to circuit ground.
4.5.3
Im pedance Matching Network Topology
T he construction of the im pedance m atching circuit may include transm ission
lines (m icrostrip, stripline, coaxial, etc.), lum ped elem ents, or a hybrid utilizing both
lumped elem ents and transmission lines. W hen using lum ped elements for matching
networks, particularly for frequencies above 3 GHz, high-Q elements m ust be used for
optim al perform ance. Impedance m atching w ith m icrostrip lines is often accom plished
with either short / open circuit stubs or series stepped-im pedance lines. T h e termination
and dim ensions o f a microstrip stub determ ine w hether the element is capacitive or
inductive. The dim ension o f each m icrostrip stepped-im pedance element determ ines the
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89
element capacitance o r inductance. A sim ple topology to im plem ent w ith steppedimpedance m icrostrip lines is series L - shunt C matching. Long, narrow lines have high
inductance, and short, w ide lines have high capacitance.
The im pedance matching network for the EPA720A-180F consists o f high-Q
lumped elements and stepped-impedance m icrostrip lines. Lumped elem ents are used to
implement series capacitors and shunt inductors. Small values o f series capacitance and
shunt inductance m ay be realized in m icrostrip with interdigital lines and spiral lines,
respectively. H ow ever, the compact size o f the PA requires the use o f a hybrid
impedance m atching network.
4.5.4
O ptim ized Im pedance Matching Network
The input and output impedances o f the EPA720A-180F must be determ ined to
design the im pedance m atching networks. The nonlinear C urtice-Ettenburg circuit model
including package parasitics as shown in Figure 4.9 is simulated with M icrow ave Office
to find output im pedances at 4.4,4.65, and 4.9 GHz. Single-stub Ioad-pull tuners are
attached to the device m odel input and output to generate output pow er load-pull
contours. The load pull contours for the EPA720A-180F at 4.4, 4.65, and 4.9 GHz are
shown in Figure 4.10.
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90
Load Pull Data C ontour G raph Tor EPA720
Swp Min
Figure 4.10 Sim ulated Load Pull C ontours for EPA 720A -180F.
T he im pedance at the center o f each contour corresponds to maximum output power and
is used as a first approxim ation o f the large-signal device output im pedance.
The input impedance o f the EPA 720A -180F is approximated b y attaching the
180-m il flange package model to an S-param eter block utilizing the EPA 720A chip
sm all-signal S-parameters. The input reflection coefficient o f this m odel is used to
approxim ate the device input impedance.
Initial input and output im pedance m atching networks are synthesized with
G en esy s’ nonlinear Harmonic Balance sim ulator at 4.65 GHz using the above input and
outp u t impedances. The m atching netw ork im pedances used in the synthesis are the
com plex conjugate o f the device im pedances for maximum power transfer into and out o f
the device. The Pout vs. Pj„ curve is then optim ized at 4.65 GHz for gain and output
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91
pow er b y varying the lum ped element values and microstrip line dim ensions. This
process creates optimized im pedance m atching networks at the cen ter frequency o f
operation.
T he matching networks and device model are redrawn w ith M icrowave Office
where the circuit is optim ized for gain and output pow er from 4.4 - 4.9 GHz. The
resulting circuit is shown in Figure 4.11.
Figure 4.11 Optim ized EPA 720A -180F Im pedance M atching Networks.
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92
The Pout and gain vs. Pin and harm onic plots at 4 .4 ,4 .6 5 , and 4.9 GHz are shown in
Figures 4.12, 4.13,4.14, 4 .1 5 ,4 .1 6 , and 4.17.
Figure 4.12 Optimized E PA 720A -180F Pout & Gain vs. Pin C urve at 4.4 GHz.
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93
Figure 4.13 O ptim ized EPA720A-180F H arm on ic Plot at 4.4 G H z.
I
Figure 4.14 O p tim ized EPA720A-180F Pout & G ain vs. Pj„ C urve at 4.65 GHz.
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94
Figure 4.1S O ptim ized EPA720A-180F Harmonic Plot at 4.65 GHz.
i
P*C
•
•
® r~ P’£A4*0 •
Figure 4.16 O ptim ized EPA720A-180F Pout & Gain vs. Pin C urve at 4.9 GHz.
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95
net n ,
.a ,
i4*
I
ir x
>-
woo
‘
ia «
•«:;
I
M«
’* j :
^ry.j
* -* i ix jj
♦
~~
~
Figure 4.17 O ptim ized EPA720A-180F Harmonic Plot at 4.9 G H z.
Table 4.4 sum m arizes the data collected from the im pedance matching sim ulations.
Parameter
PldB
G .dB
Units
dBm
dB
dB
dBm
dB
dBc
4.40
Frequency (G H z
4.65
4.90
3 5 .9
3 5 .5
3 4 .4
8 .3
9 .1
8 .5
9 .3
9 .5
10.1
G (small signal)
3 5 .6
3 5 .9
3 5 .3
Pout @ 27 dBm Pm
8 .5
G @ 27 dBm Pm
8.8
8 .3
- 3 1 .6
Harmonic Level
- 3 3 .9
- 3 4 .2
yd
3rd
Largest Harmonic
Table 4.4 Sum m ary o f Im pedance M atching Network Sim ulations.
The I dB com pressed pow er (35.5 dBm nom inal) is low at 4.9 GHz. H owever, the
output power is near nom inal value and gain is above 8 dB at 4.9 GHz w hen driven with
27 dBm (0.5 W) input power. The third harm onic is the largest harmonic at each
frequency but is alw ays below -3 0 dBc. T he quarter-w ave transformer choke attenuates
the second harmonic, w hich is often the largest harm onic when using G aA sFETs [36],
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96
The quarter-w ave transform er choke is a short circuit to the 2nd harm onic since the
electrical length o f the transform er is one-half wavelength at the 2nd harm onic frequency.
4.6 Power Splitter & C om bin er Design
The shared-current PA shown in Figure 4.1 requires a 3 -w ay pow er splitter and
com biner designed for p lan ar layout. Wilkinson, T-junction, and in-line n-w ay power
splitters are discussed in Section 1.2.11.2.
For n>2, the W ilkinson pow er splitter requires a floating node to which all output
ports m ust attach with a term ination. Common connection o f all output ports may only
be realized in a single plane with the use o f crossovers. A design o f this type is possible
but requires careful sim ulations.
The T-junction sp litter has very limited isolation. Isolation is im portant for
stability o f devices when stacked as shown in Figure 4 .1. Poor isolation also makes the
devices difficult to tune for optim al power and efficiency in production.
The in-line splitter architecture requires one-third o f the pow er split to the first
port and then one-half p ow er each to the remaining two ports. P ow er splitting with a
one-third ratio may be accom plished with an unequal-split W ilkinson divider or a
directional coupler. The one-third / two-thirds W ilkinson requires four quarter wave
transform ers and a non-standard value termination for m atching on all three ports and for
good isolation between them . The physical size o f this approach is large and the high
im pedance o f the one-third pow er port requires very narrow m icrostrip lines. The onethird coupled power directional coupler (-4.77 dB) is also very difficult to realize in
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97
microstrip as th e broadside coupled line spacing is too small for practical fabrication.
Conventional n-w ay pow er dividers do not satisfy the constraints o f this PA design.
4.6.1
Power S p litter & Combiner Topology
The 3-w ay pow er splitter and com biner design chosen for the high-efficiency
shared-current PA is the fork n-way hybrid [45]. The fork splitter consists o f an input
line with characteristic impedance Zc that splits into n quarter-wave transform ers o f
characteristic im pedance Z0. The ends o f the n transformers are coupled to adjacent
transformers w ith term inations o f resistance R. Output lines with characteristic
impedance Zd are connected to the ends o f the transformers. All outputs o f a fork n-way
hybrid are in-phase. A 5-way fork hybrid pow er splitter is shown in Figure 4.18 [45].
X /4,
Figure 4.18 5-W ay F ork Hybrid Power Splitter.
The fork splitter is sim ilar to an n-way W ilkinson with a different arrangem ent o f
terminations. T he fork splitter com prom ises VSW R and isolation for planar layout.
Even at center frequency, the impedance m atch and isolation o f the fork splitter is not
perfect. H owever, the fork divider may b e generalized to a two-stage fork splitter for
better bandwidth, isolation, and VSWR.
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98
In reference literature [45], the fork splitter is optim ized w ith equal em phasis on
V SW R and isolation at all ports. For a single stage fork splitter, the impedance o f the
quarter-w ave transform ers depends on the number o f outputs (n), source im pedance (Zc),
and load im pedance (Zd) [45],
ZG= V(nZcZd) (fi)
(61)
For n = 3 and Zc = Zd = 50 Q , the impedance is calculated as Z0 = 50^3 Q = 86.6 Q . The
optim um Zd/R ratio for n = 3 is determined to be 0.57735 [45]. This ratio results in
w orst-case isolation o f 15 dB, between ports 2 and 4 w here port 1 is the input and port 3
is the center output, and return loss o f 15 dB (V SW R < 1.5 at port 3). The term ination
resistance R is also 86.6 Q (50/0.57735). The required pow er handling capability o f the
term inations is determ ined by dividing the maximum pow er dissipated in a term ination
due to the w orst-case failure o f a device by the norm al output (splitter) or input
(com biner) pow er. For n=3, this ratio is 0.696 [45]. F or the splitter, the required
term ination pow er rating is determined by the pow er into the devices. If the EPA 720A 180F must output 3.6 W with minimum gain o f 8 dB, th e m axim um input power to a
device is 570 mW . The splitter terminations must each be capable o f dissipating 69.6%
o f this power, resulting in a splitter termination pow er rating o f 397 mW. Since each
device must output at least 3.6 W, the com biner term inations m ust each be capable o f
dissipating 2.5 W (69.6% o f 3.6 W).
The tw o-stage fork splitter performs better than the single-stage in every aspect
but requires m uch m ore layout area. Like the single stage fork splitter, the characteristic
im pedances o f the first (Zoi) and second (Z q2) sets o f quarter-w ave transformers o f the
tw o-stage fork com biner depend on n, Zc, and Zd [45].
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99
Zoi = (nZc)3/4Zdl/4 (Q)
(62)
Z o 2 = (nZc)1/4Z / 4 (Q)
(63)
For n = 3, the tw o-stage fork splitter provides a perfect m atch w ith perfect isolation when
Zd/R.2 = 0.25 and RiZd/Ro2 2 = 0.75 [45]. Ri and R2 are the term ination resistances
between ports at the ends o f the first and second sets o f transform ers, respectively. With
Z c = Z d = 50 Q and n = 3, Z o i = 114 Q , Z 0 2 = 65.8 Q, R, = 65.0 Q , and R2 = 200 Q . The
term ination resistor pow er ratios are 0.333 for the first set o f terminations and 0.25 for
the second set o f term inations. For the pow er splitter, the m axim um power out o f the
ports is 570 mW . Ri and R2 must therefore be rated at for at least 190 mW and 142.5
m W dissipations, respectively. For the pow er combiner, Ri m ust be capable o f
dissipating 1.2 W, and R2 must be capable o f dissipating 0.9 W.
The tw o-stage fork power splitter is chosen for the high-efficiency shared-current
PA shown in Figure 4.1. The im pedance matches between the pow er splitter and
com biner and the EPA720A-180F im pedance matching netw orks are very good since all
are nom inally 50 Q . High isolation betw een two-stage fork splitter outputs (com biner
inputs) makes the tuning o f the devices in the shared-current stack much sim pler since the
tuning o f one device has little impact on the other devices. The two-stage fork com biner
requires m ore layout area than the single-stage, but the length o f the transformers at the
center o f the operational frequency band (4.65 GHz) is o n ly approxim ately 400 m ils on
the chosen substrate.
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100
4.6.2
Term ination Selection
Term inations are typically 50 £2 for quadrature hybrids and 100 Q for W ilkinson
splitters. Term inations o f any o th e r value are presently a custom item. Both the singlestage and tw o-stage 3-way fork splitters require non-standard term ination resistances for
input and output port im pedances o f 50 £2. Table 4.5 shows single-stage and tw o-stage
fork hybrid calculated term ination resistances, required power ratings, selected
resistances, and pow er ratings o f th e selected resistors.
Single-Stage Fork
Splitter C om bin er
R
R
86.6
86.6
Two-Stage Fork
Splitter
C om biner
R.
r2
r2
R.
C alculated
65.0
200
200
65.0
R esistance (£2)
86.6
Selected
86.6
64.9
200
200
64.9
1%
1%
1%
5%
5%
R esistance (£2)
1%
0.190
C alculated
0.397
2.5
0.9
1.20
0.1425
Pow er (W )
Selected Power
1/2
1/2
1/8
1/2
1/8
1/2
(W )
(2010)
(0805)
(2010)
(2010)
(0805)
(2010)
T ab le 4.5 3-W ay Fork H yb rid Term ination Resistances and Power R atings.
Standard 1% resistors (3 significant figures) are presently only available in packages up
to the 2010 (1/2 W att) size. This lim ited pow er rating may cause a problem in the singlestage fork com biner should a p o w er transistor fail. 1% resistors are required so that the
term ination resistances are as clo se to the calculated value as possible. C hanging
term ination resistances from the calculated values reduce isolation and increase VSW R.
T he tw o-stage fork co m b in er also requires high power dissipation if a device fails.
However, the m axim um pow er dissipation requirem ent is less than h alf o f the singlestage fork com biner. O ne-eighth W att resistors are used for the splitter term inations, and
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101
one-half W att resistors are used for com biner terminations. The resistors are only
required to dissipate p o w er when a device fails or there are pow er im balances at the
outputs o f the splitter o r inputs o f the com biner. Since each is device biased, decoupled,
and im pedance m atched the same, the pow er imbalances should b e minimal.
There are m ethods for increasing th e pow er dissipation rating o f a resistor. The
pow er rating o f resistors is commonly specified w ith the resistor dissipating energy in
open air. M ounting th e resistor to a PCB significantly increases its m axim um dissipation
rating. Applying a th erm ally conductive com pound to the bottom side o f the resistors
helps conduct heat from th e resistor to the PCB. Inserting a block o f therm ally
conductive foam or p ad d in g between the to p o f the resistor and a lid o r chassis also helps
conduct heat from the resistor.
4.6.3
Sim ulated & O ptim ized Power Splitter & Combiner
The two-stage fork splitter is m odeled and simulated w ith G enesys. On RO4350
0.020” thick substrate, a 50 Q line is 44 m ils wide. The quarter-w ave transformers are
designed at the center o f the frequency band (4.65 GHz.) The 114 Q transformers are 7
m ils w ide by 412 m ils long, and the 65.8 Q transformers are 27 m ils w ide by 394 mils
long. A microstrip cro ss is used to model th e junction o f the two outer transformers with
the input line, and a m icrostrip T is used to model the step in trace w idth from the 50 Q
input line to the center transformer. Port 1 is the input, and ports 2, 3, and 4 are the
upper, middle, and b o tto m outputs, respectively. Ideal resistors are used to model the
term inations since device m odels are not available from the m anufacturer. The resistors
are advertised for m icrow ave applications so the package parasitics are likely relatively
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102
small. As discussed in Section 3.1, the ideal resistor model m ay b e used provided 0.8 <
|Z|/R < 1.2 for all frequencies o f operation.
The initial sim ulation results o f the 3-w ay fork splitter show ed return loss and
isolation o f greater than 30 dB at all ports and insertion loss o f approxim ately 4.92 dB
between the input port and output ports. The ideal insertion loss for a 3-w ay splitter is
4.77 dB (10Iog(3)). T h e splitter is optimized for maximally flat insertion loss, isolation,
and return loss at all ports from 4.4 - 4.9 GHz. Like the decoupling netw ork and
impedance matching netw orks, the power splitter and combiner are optim ized across the
w ider bandwidth o f 4.4 - 4.9 GHz. Optim izing performance from 4.5 - 4.8 GHz may
result in good average perform ance from 4.5 - 4.8 GHz but reduced perform ance at the
band edges o f 4.5 and 4.8 GHz. The results are shown in Figure 4.19.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
103
•A
*bo
.
«m
■
***o
«ro
«sn
mta
<rx
tn c
mb
«uo
scdo
Figure 4.19 O ptim ized Sim ulations Results for T w o-Stage 3-Way Fork Splitter.
A fter optim ization, the w orst-case insertion loss from input to output is still 4.92 dB but
isolation im proves to 37 dB and return loss im proves to 37.7 dB (VSWR < 1.03). The
final optim ized circuit schem atic is shown in Figure 4.20.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
104
CR1
W T = 4 4 mil
W C = 7 mil
TL1
W =7 mil
L=401 mil
R = 64.9 ohm
TL4
W = 27 mil
L=393 mil
R3
R =200 ohm
( 1)
TL7
W = 4 4 mil
L=100 mil
ST P1
NA R=44 mil
W =7 mil
TL2
W =7 mil
L=408 mil
TL3
W =7 mil
L=401 mil
R2
R = 64.9 ohm
TL5
W = 27 mil
L=393 mil
R4
R =200 ohm
TL6
W = 27 mil
L=393 mil
Figure 4.20 O ptim ized Two-Stage 3-W ay Fork Splitter Schematic.
The first-stage transform er lengths are adjusted to 401 m ils for the outside transformers
and to 408 m ils for the inside transformer. The length o f each second-stage transformer
is reduced by 1 m il to 393 m ils
The single-stage 3-w ay fork splitter is sim ulated for com parison. The 86.6 Q
quarter-wave transform ers m easure 15 mils wide b y 403 m ils long on the 20-mil thick
RO4350 substrate. Ideal resistors are used to model the 86.6 Q terminations. The initial
simulation results show m inim um isolation o f 14.8 dB, m inim um return loss o f 14.8 dB
(VSW R = 1.44), and m axim um insertion loss from input to output o f 4.85 dB.
O ptim ization does not im prove the performance o f the fork splitter in the operational
frequency band b u t im proves perform ance outside the band. Figure 4.21 shows the
performance o f the optim ized single-stage 3-way fork splitter and the schematic is shown
in Figure 4.22.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
105
a
9
15
i
a
♦ w jh
#0(5:11
.mrxi
.c a w
• area
•
—arcwi
-tm o i
• - oan* 4
• ca w j
#■ wiw*
• ccrs*»i
Figure 4.21 O ptim ized Simulations R esults for Single-Stage 3-W ay Fork Splitter.
s
CR1
WT=44 mil
WC=15 mil
TL1
W=15 mil
L=392 mil
R1
R=86.6 ohm
5
TL4
W=44 mil
L=150 mil
0H O H
C
TD -I
STP1
NAR=44 mil
W=15 mil
TL2
W=15 mil
L=392 mil
R2
R=86.6 ohm
TL3
W=15 mil
L=392 mil
Figure 4.22 Optim ized Single-Stage 3-W ay Fork Splitter Schem atic.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
106
4.7 T ran sistor M ou n tin g
The E P A 720A -180F flange is connected to the device source. This is a com m on
m icrow ave p o w er transistor structure since it is a very efficient m eans o f conducting
dissipated energy o u t o f the device. T h e flange is conventionally screw ed dow n to a
chassis o r heat sink for maximum h eat transfer. However, w hen configured in the
shared-current arrangem ent shown in Figure 4.1, the transistor source cannot be
connected to chassis ground. In the telem etry transmitter application, the chassis is
circuit ground. T herefore, a device m ounting structure m ust be designed w ith sufficient
heat transfer and D C isolation.
4.7.1
DC Isolated M ounting Structure
The package outline o f the EPA 720A-180F DH-PHEM T is shown in Figure 4.23.
i
i
i
t
F igure 4.23 180-mil Flanged Package O utline D rawing.
For DC isolation and maximum therm al conductivity, the E PA 720A -180F is fastened to
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107
the heat sink, o r telem etry transm itter chassis, as show n in Figure 4.24.
NYLON
NYLON
SCREW r
SCREW
FET
I ^
PCB
FLANGE
(SOURCE)
HEATSINK
INSULATOR ~
ll
|J
i '
--------
BRASS
(CHASSIS)
/
Figure 4.24 Isolated T ransistor M ounting Structure.
A thermally conductive, electrically insulating pad is placed between the device flange
and the heat sink. The pad must be thin and have very low thermal resistance. W akefield
Engineering’s 173-7 DeltaPads are chosen for isolating the FET flange from the heat sink
[46], The 173-3 series is 0.007” thick and has therm al resistance o f 0.33 °Cin2/W . The
electrical breakdow n voltage o f the p ad is 4000 V, and the volume resistivity is 109 M Qcm. N on-conductive nylon 2-56x3/16” pan head screws fasten the flange and pad to the
heat sink. For a non-ferrous material, nylon has very high tensile strength, high
temperature rating, and low creep or stretch factor [47], The screws are m anufactured by
Non-Ferrous Fasteners.
The PC B m ounting structure is designed so that the FET gate and drain tabs are
slightly higher than the PCB top surface w hen the FET is fastened to the heat sink. The
180-mil flange is 82 m ils thick [35]. R eferring to Figure 4.23, the underside o f the gate
and drain tabs are approxim ately 11 m ils higher than the top o f the flange. This
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108
dim ension is added to the flange thickness and insulator pad thickness for a total tab
height o f 100 mils from th e heat sink. The 20-m il thick RO4350 substrate is sweatsoldered to a 62-mil (1/16” ) thick brass plate. B efore fabrication the PCB has 1 oz.
copper on both sides. To p late the vias, the PCB is plated with another 1 oz. copper. The
top side traces and ground plane then have a trace thickness equal to that o f 2 oz. copper
plating. Table 3.3 shows a copper thickness o f 2.8 m ils per side for 2 oz ./ft2 plating. The
total PCB thickness is therefore 25.6 mils (20 + 2.8 +■ 2.8). Sw eat-soldering the PCB to
the copper plate results in a total thickness o f 87.6 mils. When all structures are mounted
and fastened, the device tabs are approximately 12 m ils above the PCB traces. A side
view o f the mounting structure is shown in Figure 4.25.
Figure 4.25 Relative Heights o f M ounting Structure.
4.7.2
Total Therm al R esistance
In order to determ ine the maximum ju n ctio n temperature o f the EPA720A-180F
device, the total thermal resistance o f the m ounting structure shown in Figure 4.24 must
be determ ined. The EPA 720A -180F has a junction-to-case thermal resistance (Qjc) o f 7
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
109
°C/W [35]. The thermal resistances o f the boundaries betw een the 180-mil flange and
therm al pad and between the pad and heat sink are each approxim ately 0.2 °C /W [6], The
therm al resistance o f the 173-7 D eltaPad is 0.33 °Cin2/W . The surface area o f the 180mil flange is 0.108 in2 (0.18x0.6), resulting in a DeltaPad thermal resistance o f 3.05
°C/W. Since thermal resistances add in series, the total therm al resistance (0 t ) o f the
device m ounting structure is 10.45 °C/W (7 + 0.2 + 0.2 + 3.05).
4.7.3
M aximum Junction Tem perature
The maximum junction tem perature o f a pow er transistor is determ ined with
Equation (17). The maximum am bient temperature o f the PA is specified in Section 4.1
as +70 °C, and the total therm al resistance is determ ined in Section 4.7.2. T he maximum
pow er dissipated in the EPA 720A -180F m ust be determ ined to calculate the maximum
device junction temperature.
Equation (10) is used to determ ine the power dissipated in a device. T he
m icrowave pow er required from each EPA720A-180F is 3.6 W. Since the m inim um gain
o f each device is estimated as 8 dB, the maximum input pow er to a device is 570 mW.
The DC pow er into each device is the drain-source voltage times the m axim um current
draw. For the specifications given in Section 4.1 for the PA shown in Figure 4.1, the
m axim um DC power consumed by a device is 9.0 W (7.5 V x 1.2 A). The total power
dissipated in each device is then 9.0 W + 0.57 W - 3.6 W = 5.97 W.
The maximum junction tem perature o f each EPA720A-180F is 70 °C + (10.45
°C/W )(5.97 W) = 132 °C. The m axim um continuous ju n ctio n temperature rating o f the
device is 150 °C [35]. The reliability o f the PA design is not compromised since the
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110
devices are operating under their m axim um continuous tem perature rating at the highest
operational am bient tem perature.
4.8 Printed Circuit B oard Design
The substrate used in the impedance matching network design and pow er splitter /
com biner design is Rogers Corporation RO4350. The substrate thickness is 20 mils, and
the dielectric constant is 3.48. T he substrate is purchased with 1 oz. copper plating.
Another 1 oz. copper is added to the ground plane and top side traces w hen the vias are
plated. The outside dim ensions o f the PA PCB must be no greater than 2.2” x 1.98” .
4.8.1
C om ponent Layout
The discrete com ponents that must be incorporated into the layout are the
EPA 720A-180F devices, the pow er splitter and combiner term inations, the decoupling
networks, the chokes, and the gate bias circuits. The EPA 720A -180F devices are placed
in a channel that is milled out o f the PCB substrate. The channel is positioned in the
center o f the PCB and has dim ensions 0.200” x 1.850” . For the pow er splitter and
com biner terminations, the decoupling capacitors, and the chip com ponents in the gate
bias circuits, the standard pad layouts shown in Table 4.6 are used [48].
Min. Pad
Pad Spacing
Dimensions
(m ils)
( L x W , mils)
30x30
20
30x50
40
35x60
80
40 x 100
150
4 .6 Standard Chip Sizes and Pad Layouts.
Chip Size
(LLWVV)
0603
0805
1206
2010
Table
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
I ll
The M IC 6211 opam p pads are designed as recom m ended by the manufacturer [37],
4.8.2
M icrostrip Layout
The 3-w ay fork pow er splitter and com biner m icrostrip line widths and lengths
are optim ized in Section 4.6.3. The first stage transform ers are only 7 mils wide. The
current carrying capacity and tolerance o f those lines m ust be evaluated to ensure reliable
operation o f the PA.
The relationship between current carrying capacity o f a PCB trace and the trace
cross-sectional area is shown in Figure 3.9. With a m axim um am bient temperature o f 70
°C, the trace tem perature can increase 55 °C to the lim it o f 125 °C without com prom ising
design reliability. In Figure 3.9, a trace cross sectional area o f 20 square mils (7 mils
wide x 2.8 m ils thick) carries a current o f approxim ately t .25 A w ith a 45 °C trace
tem perature rise. The current carried on the 7-mil w ide trace is less than 0.3 A (I =
V(P0Ul/Z) = V(3.6/50)). According to Figure 3.9, this low current should cause a trace
tem perature rise o f less than 10 °C.
The second issue with the narrow trace width is fabrication tolerance. The vendor
used to fabricate the PCBs advertises a trace width lim it o f 5 m ils and guarantees
tolerance w ithin 5 mils [49]. Simulations show adding and rem oving 2.5 mils on the
width o f the transform ers in the two-stage fork splitter had little impact on insertion loss.
However, the V SW R o f the input port increases from 1.04 to over 1.4 in the worst-case
condition (4.5 m il w ide transformers).
The length o f each transmission line from the pow er splitter outputs to the
com biner inputs must be exactly equal for the signals to com bine in-phase. The length o f
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112
the optim al 50 Q m iter o f the 20-m il RO4350 substrate is determ ined with Equation (46)
to be 68 mils. The effective electrical length (in mils) o f the m iter is determined w ith
Equation (47) to be 48 mils. The m iters’ lengths are added to the transmission lines to
equalize the distance between splitter and combiner ports. The splitter input and
com biner output are aligned with the required PA input an d output locations for the
telem etry transm itter.
The im pedance matching netw ork is optimized w ith a combination o f discrete and
microstrip elem ents. The discrete elem ent pad layout follow s the minimum
recom m endations given Table 4.6. T he microstrip stepped-im pedance elements are
reduced in physical size, and tuning stubs are added to allow tuning o f the devices. The
nominal size o f each element is reduced by approxim ately 10 percent, with 20% o f tuning
added. This allow s the element to b e tuned to a value less or greater than its nom inal
value. Sm all tuning stubs are also added along the 50 Q transm ission lines for tuning
flexibility.
W hen optim izing a microstrip impedance m atching network with a sim ulation
program, the optim ized lines are often specified in im pedance and electrical length in
degrees. In order to com plete a circuit layout, the physical size o f the microstrip lines
m ust be determ ined. Equations and calculation programs are available to calculate the
trace length and the w idth o f one w avelength on a particular substrate for a particular
impedance. O nce the signal w avelength in mils is known, the physical length o f the
optim ized im pedance matching lines o r stubs may be calculated w ith Equation (64).
L = /L x/360 (m ils)
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
(64)
113
L>. is the length o f one w avelength on the chosen substrate, and / i s th e electrical length o f
the line in degrees.
4.8.3
Via Design
The 20-mil thick RO 4350 substrate is chosen to minimize parasitic via
inductance. V ia inductance is also minimized by positioning the via directly under the
end-cap o f chip com ponents to reduce electrical path length. Via diam eter is chosen as
31 m ils (1/32”) to m inim ize the h/r ratio.
4.8 .4
Com plete PCB L ayout
The complete PCB layout, circuit schem atic, parts list, and brass mounting plate
fabrication are shown in Figures 4.26,4.27, 4.28, and 4.29, respectively.
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114
'vD^g
3
Figure 4.26
H igh-Efficiency Shared-Current Microwave P A PCB Layout.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
115
>
j Atm » A
Figure 4.27
"
High-EfTiciency Shared-Current Microwave PA Schem atic.
H y-°«
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
116
Figure 4.28
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High-EfTiciency Shared-C urrent M icrowave PA Parts List.
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Figure 4.29
High-EfTiciency Shared-C urrent M icrow ave PA Brass Carrier.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
117
CHAPTER V
Experimental Results
T he high-efficiency shared-current 4.5 - 4.8 GHz PA designed in C hapter 4 is
fabricated and tested according to design specifications. Preliminary bench tests are
perform ed on the pow er splitter, the power com biner, and a single D H -PH EM T device to
verify proper operation before the shared-current configuration shown in Figure 4.1 is
fully tested.
5.1 Prelim inary Tests
5.1.1
Power Splitter
A pow er splitter test PCB is modified w ith signal launchers installed at the input
port and three output ports o f the 3-way two-stage fork pow er splitter. A Hewlett
Packard (H P) 8720D N etw ork Analyzer is used to measure the S-param eters o f the power
splitter.
Initial tests result in high insertion loss betw een the input port and output ports.
The ideal insertion loss for a 3-way splitter is 4.77 dB (101og3). The average measured
insertion loss above the 4.77 dB ideal loss is approxim ately 0.9 dB. The pow er splitter
response is optimal for 3.9 - 4.4 GHz, where V SW R , isolation, and insertion loss are
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118
m ost near their ideal values. The splitter frequency response must be increased to the 4.5
- 4.8 GHz frequency range.
To reduce shunt capacitance between the metalized chip resistor end caps and the
ground plane, the 0805 chip resistors are m ounted vertically. Changing the chip resistor
orientation improves insertion loss by approxim ately 0.1 dB.
The first- and second-stage fork splitter quarter-wave transform er lengths are
modified to improve insertion loss. To increase the frequency response o f the splitter, the
quarter-wave transform ers are shortened by soldering copper foil to the existing lines.
The 65.8 Q lines are shortened from 393 mils to 345 mils, and the 114 Q lines are
shortened from 401 m ils to 340 mils
The first- and second-stage fork splitter termination resistances are also adjusted
to reduce insertion loss. M inim al insertion loss is achieved with first- and second-stage
term ination resistances equal to 51 Q and 150 Q . Table 5.1 sum m arizes the pow er
splitter performance. P ort 1 is the input, and ports 2, 3, and 4 are the top, middle, and
bottom output ports, respectively.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
119
F r e q u e n c y (G H z)
P a ra m eter
(d B )
4.50
4.65
4.80
S ,,
-15.2
-34.3
-25.1
-17.8
-17.9
-20.1
-19.4
-5.31
-5.72
-5.72
0.54
0.95
0.95
-24.2
-29.7
-34.1
-15.5
-23.1
-33.5
-20.3
-4.98
-5.24
-5.35
0.21
0.47
0.58
-12.2
-21.9
-22.3
-20.3
-17.1
-17.9
-19.2
-5.43
-5.68
-5.72
0.66
0.91
0.95
-18.3
-26.9
-23.7
-18.5
-22.0
-27.0
-20.2
-5.05
-5.23
-5.39
0.28
0.46
0.62
-10.1
-17.1
-24.1
-27.5
-16.6
-16.1
-18.9
-5.65
-5.86
-5.88
0.88
1.09
1.11
-14.5
-17.1
-17.7
-29.7
-21.1
-22.9
-19.9
-5.20
-5.28
-5.34
0.43
0.51
0.57
S 22
O r ig in a l
M o d ifie d
T a b le S .l
S 33
S4 4
S 23
S34
S24
S2 I
S3 I
S4 I
IL P ort 2
IL P ort 3
IL Port 4
S 11
S22
S 33
S4 4
S 23
S34
S24
S 21
S 31
S41
IL Port 2
IL P ort 3
IL P ort 4
P r e lim in a r y P o w e r S p litt e r T e s t R e s u lt s .
M odifying the resistor orientation, transform er lengths, and term ination resistances
reduces insertion loss (S2i, S31, S41), increases isolation (S23, S34, S24), and increases
return loss (Si 1, S22, S33, S44) in alm ost all cases. The insertion loss (IL) given in T able
5.1 is loss above the ideal 4.77 dB for a 3-w ay splitter. M odifying the 3-way tw o-stage
fork pow er splitter reduces insertion loss by an average o f about 50% to 0.45 dB.
Average isolation between output ports is approximately 22 dB , w ith worst-case isolation
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120
o f 19.9 dB. Average return loss on the output ports is approxim ately 23.5 dB (VSW R =
1.14), w ith worst-case ou tp u t return loss of 15.5 dB (V SW R = 1.40). Average input port
return loss is approxim ately 19 dB (VSWR = 1.25), with w orst case input return loss o f
14.5 dB (V SW R = 1.47). The pow er splitter design m odifications are incorporated into a
revised PCB design.
5.1.2
Pow er Com biner
A pow er com biner test PCB is created with signal launchers installed at the three
input ports and output p o rt o f the 3-way two-stage fork pow er com biner. The same
Hewlett Packard (HP) 8720D Network Analyzer is used for pow er com biner Sparam eters measurements.
Like the power splitter, initial power com biner tests result in high insertion loss
between the input ports and output port. The average m easured insertion loss is
approxim ately 5.9 dB. T h e com biner response is also optim al for 3.9 - 4.4 GHz.
T he large 2010 term ination resistors induce significant shunt capacitance between
the m etalized chip end caps and the ground plane. O rienting the 2010 chips vertically
im proves insertion loss b y approxim ately 0.4 dB. For further insertion loss reduction, the
first- and second-stage quarter-w ave transformer lengths are shortened. The 65.8 Q lines
are shortened from 393 m ils to 345 mils, and the 114 Q lines are shortened from 401 m ils
to 370 m ils. The first stage term ination resistors are also increased from 64.9
to 75 Q
to reduce insertion loss. T he second stage termination resistors are not modified. Table
5.2 sum m arizes the pow er com biner performance. Port 1 is the output, and ports 2, 3,
and 4 are the top, middle, and bottom input ports, respectively.
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121
Design
Param eter
(dB)
Si i
Original
IL
IL
IL
M odified
IL
IL
IL
T ab le 5.2
4.50
-11.2
-22.2
S 22
-35.1
S 33
-18.5
S 44
-18.4
S 23
-16.8
S34
-15.9
S 24
-6.07
S 21
-5.85
S 31
S 41
-6.16
Port 2
1.30
Port 3
1.08
Port 4
1.39
S„
-18.6
-20.3
S22
-19.1
S33
-30.3
S 44
-28.1
S 23
-25.1
S 34
-16.3
S 24
-5.32
S 21
-5.25
S 31
-5.28
S 41
Port 2
0.55
Port 3
0.48
Port 4
0.51
Preliminary Power
Frequency (G H z)
4.65
4.80
-11.3
-10.9
-18.1
-18.2
-25.9
-15.0
-16.6
-19.2
-17.4
-16.7
-16.3
-16.1
-15.7
-15.6
-5.72
-5.75
-5.76
-5.93
-5.94
-6.12
0.95
0.98
0.99
1.16
1.17
1.35
-20.2
-19.6
-16.2
-13.9
-16.2
-13.9
-16.5
-12.4
-27.6
-26.4
-24.9
-25.4
-16.3
-16.5
-5.23
-5.16
-5.12
-5.21
-5.24
-5.27
0.46
0.39
0.35
0.44
0.47
0.50
C om biner T est Vlesults.
M odifying the p o w er com biner reduces insertion loss (S 2 1 , S3 1 , S 4 1 ), increases isolation
(S 2 3 , S 3 4 , S 2 4 ), and increases output return loss (S n , S 2 2 , S 3 3 , S 4 4 ) in alm ost all cases. On
average, return loss at the input ports is slightly but not significantly reduced. Modifying
the 3-way tw o-stage fork pow er com biner reduces insertion loss by an average o f 60% to
0.46 dB. Average isolation between input ports is approxim ately 23 dB, w ith worst-case
isolation o f 16.3 dB. A verage output port return loss is approxim ately 19.5 dB (VSWR =
1.23), with w orst-case output return loss o f 18.6 dB (V SW R = 1.27). A verage return loss
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
122
on the input ports is approxim ately 17.6 dB (V SW R = 1.30), w ith worst case input return
loss o f 12.4 dB (V SW R = 1.63). The pow er com biner design modifications are
incorporated into a revised PCB design.
5.1.3
Single-Stage PA
A single EPA 720A -180F PA circuit is built o n the PCB shown in Figure 4.26.
T he 50 Q transm ission lines into and out o f the input and output matching networks are
cut to allow insertion o f signal launchers. The single EPA 720A -180F is supplied w ith
8.0 V (V DS = 7.5 V, V s = 0.5 V) and driven with 27 d B m input power.
Initial tests result in output pow er greater than 3 W for frequencies 3.75 - 4.15
GHz. The single device output power is 1.25 W at 4.5 G H z and m onotonically decreases
to 0.6 W at 4.8 GHz. To troubleshoot the PA, the individual sections o f the design
affecting frequency response must be isolated and evaluated.
The decoupling network and im pedance m atching netw orks are the most
frequency-dependent parts o f the single device circuit. T o rem ove the decoupling
netw ork from the circuit, the capacitors and bias resisto rs are disconnected and the device
source is fastened directly to circuit ground with m etal screw s. A gate voltage o f -0 .5 V
is applied to the gate choke, and a drain voltage o f 7.5 V is applied to the decoupled end
o f the quarter-w ave transform er. With the decoupling netw ork removed, the frequency
response o f the PA is identical to the response w ith the decoupling network. Therefore
the im pedance m atching network must be m odified to im prove performance from 4.5 4.8 G Hz.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
The lum ped elem ents o f the input and output im pedance matching netw orks are
adjusted to optim ize PA perform ance from 4.5 - 4.8 GHz. Changing lumped elements
improved perform ance but not enough to meet design specifications. The steppedim pedance m icrostrip lines are cut and re-shaped to m axim ize pow er output and gain
from 4.5 - 4.8 GHz. Data is collected with the device biased conventionally. The
decoupling network is then re-attached, and com parison data is collected w ith the device
self-biased w ith an 8 V supply. Table 5.3 summarizes the single-stage PA perform ance.
Frequency (GHz)
Parameter
4.5
4.6
4.7
4.8
Initial Pou, (W)
1.10
0.98
0.9
0.8
3.4
3.0
Initial G (dB)
2.5
2.0
4.10
3.80
4.05
M odified Pout (W)
3.80
M odified G (dB)
9.1
9.1
8.8
8.8
4.45
4.30
Mod. Pout w/ D ecoupling (W) 4.00
3.65
9.0
9.5
Mod. G w / D ecoupling (dB)
9.3
8.6
Table 5.3 Prelim inary Single-Stage PA T est Results.
Re-attaching the decoupling netw ork slightly increases output pow er and gain. The
lowest gain w ith the decoupling circuit connected is 7.9 dB. The three stacked devices
m ay be “stagger-tuned” to im prove broadband perform ance in the final shared-current
configuration. In stagger tuning, devices in parallel are individually tuned for optimal
perform ance for different ranges o f a frequency band.
The design m odifications made to the circuit board to improve PA perform ance
from 4.5 - 4.8 GHz are sum m arized in Table 5.4.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
124
Initial Value
Final Value
E lem ent Type
C 2 1-23 = 0 .4 pF
C21-23 = 0.8 pF
D iscrete
C24-26 = 0.6 pF
C 24-26= 1.0 pF
D iscrete
L l-3 = 15 nH
L l-3 = 2.2 nH
D iscrete
O utput Series L (0.7 nH)
Shunt C (0.4 pF)
M icrostrip
O utput Shunt C (0.5 pF)
Series L (0.6 nH)
M icrostrip
Q tr-w ave Xmfr
Qtr-wave X fm r (moved)
M icrostrip
N /A
L4-6 = 1.8 nH
D iscrete
N/A
C86-88 = 5.6 pF
D iscrete
T able 5.4 Shared-Current PA Design M odifications.
The PCB shown in Figure 4.26 is updated w ith the pow er splitter, p o w er combiner, and
im pedance m atching netw ork m odifications listed in Table 5.4. T he revised sharedcurrent PA PCB layout, schematic, and parts list are shown in Figures 5.1, 5.2, and 5.3,
respectively.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
i f:--;
.
\
Figure 5.1 Revised Shared-C urrent 4.5 - 4.8 GHz PA PCB Layout.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
VO
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126
Figure 5.2 Revised Shared-C urrent 4.5 - 4.8 GHz PA Schem atic.
fM
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
127
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Figure 5.3 R evised Shared-Current 4.5 - 4.8 G H z PA Parts List.
Gate chokes L l-3 are replaced with 2.2 nH inductors to im prove im pedance m atching at
the device input. The o rd er o f the output m icrostrip elem ents is changed to increase
output pow er and gain. Changing the microstrip layout requires the quarter-wave
transform er to be repositioned as well. Bench testing indicates that a shunt inductor is
required at the device output prior to the DC blocking capacitor for maximum output
pow er and gain. However, a shunt inductor cannot be directly installed since an inductor
is a DC short circuit. A series-resonant 5.6 pF capacitor m ounted on a 31 mil via
provides the microwave ground for the shunt inductor. Perform ance tests in Section 5.2
utilize the revised PCB layout shown in Figure 5.1 with the design changes noted in
Table 5.4.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
128
5.1.4
Shared-C urrent PA Tuning
The shared-current microwave PA show n in Figure 4.27 is assem bled on the
revised PCB show n in Figure 5.1. All pow er splitter, power com biner, and impedance
matching network m odifications are incorporated into this assembly according to the
schematic and p arts list show n in Figures 5.2 and 5.3. Prior to recording data and
performing environm ental tests, the PA is tuned for optimal perform ance.
Upon initial pow er up, power supply voltage is supplied to the PA at a low level
to prevent possible dam age to the circuit. A n y problem s with the DC bias circuit may
result in the full su p p ly voltage being applied across a single device. S hould this occur
the device will not be dam aged if the supply voltage is less than a single d ev ice’s
m axim um continuous voltage rating. Once the DC bias circuit operation is verified and
each device is tuned, full voltage may be applied with the normal pow er supply voltage
and rise time as discussed in Section 4.2.3.
With 8 V supplied to the PA, VDS and V Gs are measured at each device. The gate
bias circuits for the upper devices are adjusted to minimum and m axim um voltages while
the devices’ VGS is m onitored. As long as VP < VGs < 0, adjustment o f the
potentiometers w ill not result in forward biasing the gate-source junction. The
microwave input signal is applied, and the im pedance matching netw orks are tuned for
maximum power from 4.5 - 4.8 GHz.
Tuning the shared-current PA for the first time involves applying a low voltage
signal, measuring th e DC bias o f each device, tuning the impedance m atching network
for maximum pow er, re-m easuring the DC bias, then increasing the su p p ly voltage and
repeating until full output pow er is achieved at full DC supply voltage. Increasing the
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
129
supply voltage in increments equal to one-h alf the nom inal rating o f a single device
provides over-bias protection w ith o u t excessive tuning iterations. In the case o f the
EPA 720A -180F devices, the PA is first tuned w ith 8 V supply voltage. The supply
voltage is then adjusted to 12 V, 16 V , 20 V, and finally 23 V with PA perform ance tuned
at each supply voltage level to en su re stable operation. At full supply voltage, the PA is
carefully tuned to meet or exceed d esig n specifications.
5.2 Perform ance Tests
T he high-efficiency shared-current m icrow ave PA performance tests are
conducted under the following conditions unless otherw ise indicated:
Tem perature:
25 °C ±5 °C
Supply Voltage:
23.0 V
Input Power:
32.0 d B m (approxim ately 27 dBm to each device).
All tests are performed at Em hiser R esearch, Inc. in Verdi, NV with all test equipm ent in
current calibration.
5.2.1
DC Bias
The DC bias o f each EPA 720A -180F is m easured with the m icrow ave input
signal applied. The results are sh o w n in Table 5.5.
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130
U nit
V
V d S!
V
V d S2
V
V d S3
V
V gsi
V
V g S2
V
V g S2
mA
Igi
mA
Ig2
mA
Ig 3
A
Id
T able S.S DC
4.50
7.75
7.53
7.18
-0.46
-0.50
-0.62
i
o
00
Parameter
-3.3
-4.1
1.02
Bias
Frequency (GH z)
4.55
4.60
4.65
4.7 0
4.75
7.78
7.81
7.73
7.41
7.36
7.54
7.57
7.67
7.34
7.46
7.16
7.09
7.05
7.54
7.69
-0.58
-0.47
-0.29
-0.22
-0.25
-0.57
-0.57
-0.42
-0.29
-0.26
-0.71
-0.81
-0.80
-0.66
-0.58
+0.6
-0.6 __ -3.3
-4.7
-4.6
-2.7
-3.1
-4.0
-3.5
-3.4
-3.4
-2.7
-2.2
-0.1
+0.6
0.98
1.03
1.05
1.14
1.15
M easurem ents with M icrowave S ign al Applied.
4.80
7.52
7.08
7.79
-0.30
-0.28
-0.39
-3.8
-4.9
-0.5
1.16
The subscripts 1, 2, and 3 represent m easurem ents on the bottom, m iddle, and top
EPA720A-180F DH-PHEM Ts, respectively. The Vos variance is due to different device
efficiencies, o r current draws, at different portions o f the frequency band. The worst-case
variance is 0.75 V for the top device. However, none o f the devices exceed the 8.0 V
maximum continuous rating. The average gate-source bias voltage is near the -0 .5 V
nominal value w ith low and high extrem es o f -0.81 V on the top d evice and -0.22 V on
the bottom device. The polarity convention for gate current m easurem ents is positive
current into the gate term inal and negative current out o f the gate term inal. The largest
current into a gate is 0.6 mA. The largest current out o f a gate is 4.9 mA. These bi­
directional gate currents are much less than the M IC 6211 opamp sin k and source current
limitations. The m axim um drain current is less than the 1.2 A m axim um specification
given in Section 4.1.
The q-point shift o f Class A/B devices is discussed in Section 4.2.2. W hen the
microwave input signal is removed, the q-point shifts since the reduced drain current
causes the bottom d evice’s VGs to increase. Table 5.6 compares the DC q-point to the
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131
microwave q-point during am plification. The microwave q-point d ata is an average o f
the data given in T able 5.5 except for the gate-source voltages. T he gate-source voltages
in the table below are the voltages m easured when the gate currents are n ear zero and the
voltage drops across the 100 Q gate resistors are negligible.
Q-Pt.
DC
Microwave
V DS1(V) V DS2 (V) V dS3 (V) V gsi (V) V CS2(V)
I d (A )
0.78
7.36
7.53
-0.38
7.63
-0.45
1.08
7.62
7.46
-0.46
7.36
-0.55
T able 5.6 Q -Point Shift o f Self-Biased Devices.
V gS3 0 0
-0.58
-0.65
Removing the m icrow ave input signal reduces the drain current from 1.08 A to 0.78 A
and increases the gate-source voltage o f each device by approxim ately 0.1 V.
5.2.2
Output Pow er
The shared-current m icrow ave PA is tuned for maximum output pow er when
driven with a 32 d B m 4.5 - 4.8 GHz input signal. M aximizing output pow er with a
constant input p ow er also m axim izes gain. The measured output pow er o f the PA with
respect to frequency is show n in Figure 5.4.
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132
12.50
i
12.00
t
11.50
I
j
!
11.00
• 10.50
*
o
0g
10.00
o.
O
9.50
i
;
9.oo
j
8.50
!
8.00
I
i
|
|
4.50
4.55
4.60
4.65
4.70
4.75
4.80
Frequency (Gfte)
_____________________________________
Figure 5.4 Shared*Current PA Output Power vs. Frequency.
The average output pow er from 4.5 - 4.8 GHz is 10.0 W. The m axim um pow er is 10.35
W at 4.67 GHz. T h e PA output pow er from 4.5 - 4.8 G Hz at room tem perature is within
the 10 W ± 1 dB (8 .0 W < Pout < 12.5 W) design specification.
The 1 dB com pressed output pow er (P ub ) is found by locating the output power
that is I dB less than the ideal linear output power w hen the input pow er level is
increased. To find P ub , the input drive power level is reduced to w here the gain o f the
PA is linear. The input drive level is increased while the output pow er is m onitored. The
PA is at P ub when th e PA gain reduces by 1 dB. P ub for the shared-current PA is 39.6
dBm (9.12 W) at 4.5 G Hz, 40.1 dBm (10.23 W) at 4.65 GHz, and 39.8 (9.55W ) dBm at
4.8 GHz. P ub is also w ithin the 10 W ± 1 dB design specification.
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133
5.2.3
Gain
The sm all signal gain o f the shared-current PA is m easured with the microwave
input pow er at a level 3 dB less than the input power at PidB- The small signal gain o f the
shared-current PA is 8.6 dB at 4.5 G H z, 9.7 dB at 4.65 G H z, and 8.3 dB at 4.8 GHz. The
1 dB com pressed gain (GidB) is 1 dB less than the small signal gain.
The gain o f the shared-current PA relative to frequency with 32 dBm input pow er
is given in Table 5.7.
Frequency (G H z)
Param eter
4.50
4.55
4.60
4.70
4.65
4.80
4.75
7.85
8.09
Gain (dB)
7.96
8.07
7.87
8.13
8.05
T able 5.7 Shared-Current PA Gain Relative to Frequency with 32 dBm Pin.
The average gain from 4.5 - 4.8 GHz is 8.0 dB. The design specification is 8 dB
nominal. The m axim um gain variation with frequency is ±0.15 dB from 4.5 - 4.8 GHz.
5.2.4
Efficiency
The m easured efficiency and power-added efficiency o f the shared-current PA are
calculated w ith 32 dBm Pin.
Frequency (G H z)
Param eter
4.50
4.55
4.60
4.70
4.65
4.80
4.75
41
44
43
39
43
36
38
q (% )
.
34
37
36
33
36
32
30
qpAE (%)
T able 5.8 Shared-Current PA Efficiency and Power-Added Efficiency.
The design specifications are q = 40 % nominal and q PAE = 35 % nominal. The average
efficiency is 41 %, and the average power-added efficiency is 34 %.
The total dissipated power o f the shared-current m icrow ave PA, average
dissipated pow er per device, EPA720A-180F junction tem perature rise, junction
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134
tem perature at room tem perature, and junction tem perature at +70 °C relative to
frequency are shown in Table 5.9.
Param eter
Unit
(W)
P d is s Total
(W)
P d is s E ach Device
T jIn crease
(°C)
Tj @ 25 °C
(°C)
T ab le 5.9 Power Dissipation and
Frequency (GHz)
4.50
4.65
4.80
15.4
15.4
18.6
5.1
5.1
6.2
53.6
53.7
64.7
78.7
78.6
89.7
Junction Tem peratures o f Shared-C urrent PA.
The m axim um continuous ju n ctio n temperature rating o f 150 °C is not exceeded at room
tem perature (25 °C). Provided the PA efficiency does not significantly degrade with
increasing temperature, the junction temperature rating w ill not be exceeded w ith ambient
tem peratures up to 85 °C.
5.2.5
V SW R
T he input and output V SW R o f the shared-current PA are determ ined by
m easuring the return loss (RL) o f the input signal into the PA and the output signal into
the load. RL is converted to a reflection coefficient (F) that is used to calculate VSWR.
The results are shown in Table 5.10.
Param eter
PA Input
PA Output
Frequency (GHz)
4.50
4.65
4.50
4.80
4.65
R L (dB )
14.2
15.1
19.9
15.3
18.5
0.19
0.18
0.17
0.10
0.12
r
VSW R
1.48
1.43
1.41
1.23
1.27
T able 5.10 Shared-Current PA Input and Output VSW R.
4.80
18.2
0.12
1.28
At 4.50 GHz, the input VSW R is near the specification limit o f 1.5:1. The PA meets the
input an d output 1.5:1 VSW R specification at all passband frequencies.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
135
5.2.6
Harm onic a n d Spurious Emissions
The output sig n al harm onics up to the 4 th harmonic and spurious emissions are
m easured with a sp ectru m analyzer. The results are shown in T ab le 5.11.
Frequency (G H z
Unit
Parameter
4.50
4.65
4.80
dBc
-34.5
2nd Harmonic
-33.5
-31.0
dBc
< -5 0
3rd Harmonic
< -5 0
< -5 0
4m Harmonic
dBc
< -5 0
< -5 0
< -5 0
Spurious
dBc
< -6 0
< -6 0
< -6 0
Table 5.11 Shared-Current PA H arm onic and Spurious Emissions.
The maximum h arm o n ic level o f -31 dBc at 9.6 G H z is below the - 3 0 dBc maximum
level specified in S ectio n 4.1. The noise floor o f the analyzer is at - 5 0 dBc when
m easuring harm onics and - 6 0 dBc when m easuring spurious em issions. No signals
above the noise flo o r are noted except for the 2nd harmonic.
5.2.7
Bandwidth
The b andw idth o f the shared-current PA is the frequency range for which the
condition 39 dBm < Pout ^ 41 dBm is satisfied. A t room tem perature this condition is
satisfied from 4.415 - 4.880 GHz. The bandw idth o f the PA is 465 M H z, or 10.0%
relative to center frequency.
5.2.8
Size and W e ig h t
The m axim um assem bled size and w eight o f the shared-current PA are measured
to ensure com pliance w ith the specifications given in Section 4.1. T he maximum
dim ensions o f the P A are 2.19” x 1.96” x 0 .2 0 ” . The maximum w eight is 1.9 oz. Both
measurements are b e lo w the maximum limits. Positioning the large 2010 termination
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136
resistors on edge to reduce parasitic capacitance increases the PA height from
approxim ately 0.17” to 0.20” .
5.2.9
Environmental Extrem es
Equipment designed for m ilitary applications m ust be capable o f surviving harsh
environm ents. The specified operational conditions typically include low tem perature
extrem e, high temperature extrem e, random vibration, shock, acceleration, high humidity,
and high altitude. The shared-current microwave PA is subjected to low tem perature,
high temperature, and vibration testing at the levels specified in Section 4.1.
5.2.9.1 Temperature Extrem es
A Tenny Jr. temperature cham ber is used to lower the temperature o f the sharedcurrent PA to -2 0 °C. The PA is soaked at the low temperature extreme for one hour
prior to testing. During testing the energy dissipated in the PA increases its temperature.
To m aintain low temperature, the PA is soaked in the temperature cham ber for one-half
hour after each test. The low tem perature test results are shown in Table 5.12.
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137
Param eter
Pout
Current
Gain
Efficiency
PAE
Average P Diss
Average Tj
V dsi
V dS2
V dS3
2nd Harmonic
3rd Harmonic
4ltl Harmonic
Spurious
Bandwidth
T ab le S.12
Frequency (G H z
4.65
4.80
10.40
9.85
0.98
1.16
8.17
7.94
46
37
39
31
4.57
6.14
27.8
44
V
7.28
7.91
V
7.20
7.49
V
7.95
6.94
-34.5
dBc
-30.5
< -5 0
dBc
< -5 0
< -5 0
dBc
< -5 0
< -6 0
dBc
< -6 0
GHz
4 .4 3 5 - 4 .8 6 0
MHz
425
9.1
%
Shared-Current PA Low T em perature T est Results
Unit
W
A
dB
%
%
W
°c
4.50
9.45
0.96
7.76
43
36
4.74
29.5
8.02
7.99
6.37
-31.5
< -5 0
< -5 0
< -6 0
The shared-current PA passes all design specifications at the low tem perature extreme of
-2 0 °C.
A convection oven is used to increase the tem perature o f the shared-current PA to
+70 °C. T he PA is soaked at the high temperature extrem e for one hour prior to testing.
Since the dissipated energy in the PA increases its tem perature during testing, the PA
temperature is m onitored with a therm ocouple during testing. W hen the PA temperature
exceeds +75 °C, the supply voltage is turned o ff until the tem perature falls below +70 °C.
The high tem perature test results are shown in Table 5.13.
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138
Param eter
Pout
Current
Gain
Efficiency
PAE
A verage PDiss
A verage Tj
V d si
V d S2
V d S3
2nd Harmonic
3rd Harm onic
4th H arm onic
Spurious
Bandw idth
T able 5.13
Frequency (G H z
4 .6 5
4.80
10.25
9.20
1.01
1.17
8.11
7.64
44
34
37
28
4.85
6.43
121
137
V
7.81
7.58
V
7.63
6.94
V
7.00
7.85
dBc
-32.5
-30.5
dBc
< -5 0
< -5 0
dBc
< -5 0
< -5 0
dBc
< -6 0
< -6 0
GHz
4.440 - 4.855
MHz
415
%
8.9
Shared-Current PA High T em perature T est Results
(Jnit
W
A
dB
%
%
W
°c
4.50
9.20
1.02
7.64
39
32
5.28
125
7.77
7.50
7.17
-32.0
< -5 0
< -5 0
< -6 0
The shared-current PA passes all design specifications at the h ig h tem perature extreme o f
+70 °C.
5.2.9.2 Vibration
Before vibration testing, non-conductive epoxy is used to stake the nylon
transistor screws, term ination resistors, and supply voltage ju m p e r wire. Chip
com ponents soldered to the PCB are n o t staked with epoxy. T he potentiom eter
adjustm ent screw s are staked with a sm all dab o f paint. A random vibration profile o f 0.1
g2/H z pow er spectral density (PSD) from 20 Hz to 2 kHz is applied to the PA for a
duration o f 10 m inutes in each the x-, y-, and z-axes. Equation (65) converts PSD to g
RM S w here A f is the random vibration bandw idth in Hz.
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139
g RMS = V(Af(g2/Hz))
(65)
The calculated and m easured g-level is 14.1 g ’s in all 3 axes. Output pow er, gain, current
draw, and harm onics are monitored throughout the vibration with no m easurable change.
The only perform ance parameters that change noticeably are incidental frequency
modulation (IFM ) and incidental amplitude m odulation (IAM).
LAM is caused by opamp noise induced on the device gates creating small
variances in the gate-source bias. Varying the gate-source bias varies th e drain-source
bias, which directly im pacts output power. The average output power is unchanged, but
instantaneous output pow er fluctuates a sm all am ount. The amount o f output power
fluctuation is LAM. An AM receiver is used to measure LAM during vibration. Worstcase measured LAM at the PA output is 1.9% during exposure to z-axis vibration. The
measured IFM is less than the 5% maximum specification.
In a pow er am plifier, IFM is com m only caused by AM-PM conversion. IFM is
measured with an FM receiver during vibration. The signal source and driver amplifier
exhibit static IFM o f approxim ately 10 kHz peak-to-peak (pk-pk). The IFM introduced
by the PA is the m easured IFM increase above 10 kHz pk-pk. W orst-case measured IFM
at the PA output is 3.5 kH z pk-pk greater then 10 kHz pk-pk during exposure to z-axis
vibration. The m easured IFM is less than the 5 kHz pk-pk maximum specification.
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140
CHAPTER VI
C onclusions and Future W ork
6.1 C onclusions
6.1.1
C om parison Between Test Results and Design Specifications
The high-efficiency shared-current 4.5 - 4.8 GHz PA passes all perform ance
specifications under all environmental conditions tested. Table 6.1 summarizes the PA
perform ance relative to design specifications.
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141
Param eter
Unit
Pout
dBm
40 ±1
W orstC ase
39.64
A
1.20 Max
1.17
M Hz
-
300 Min
1.5:1 Max
415
1.48:1
4.8 GHz
70 °C
4.8 GHz
70 °C
70 °C
4.5 GHz
-
1.5:1 Max
1.28:1
dBc
-30 Max
dBc
kHz
Pkpk
%
%
Efficiency
%
Dimension
in.
Current
BW
Input
V SW R
O utput
V SW R
Harmonic
Level
Spurious
Level
IFM
IAM
PAE
Specification
Condition
BestCase
40.17
C ondition
Spec.
Margin
0.64
465
1.41:1
4.65 GHz
-20 °C
4.5 G Hz
-20 °C
25 °C
4.8 GHz
4.8 GHz
1.23:1
4.5 GHz
0.22
-30.5
9.6 GHz
-20 °C
-34.5
9.0 GHz
25 °C
0.5
-60 Max
< -6 0
-
-
-
-
5 Max
3.5
V ibration
5 Max
35 Nom
1.9
28
40 Nom
34
V ibration
4.8 GHz
39
70 °C
4.8 GHz
46
70 °C
2.19x1.96x0.20
0.96
0.03
115
0.02
1.5
-
4.65 G Hz
-20 °C
4.65 G Hz
-20 °C
3.1
-
*
0.01x0.02
2.20x1.98x0.25
Max
x0.05
oz.
W eight
1.9
2.5 Max
0.6
Table 6.1 Summary o f Shared-C urrent PA Specifications and T est Results.
Since the gain o f GaAsFETs decreases w ith tem perature and the design is optim ally
tuned at the center o f the operational frequency band, optimal output pow er, current,
efficiency, and power-added efficiency occu r at 4.65 GHz at -2 0 °C. Since transistor
gain and efficiency decrease with increasing frequency, the lowest output power, highest
current, and lowest efficiency occur at 4.8 G H z at +70 °C. Most tests result in
com fortable specification margin. W orst-case current draw, input V SW R, and 2nd
harmonic level are very close to m axim um specifications. These param eters m ay be
im proved w ith further PA tuning.
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142
The design modifications m ade to the power splitter, pow er com biner, and
im pedance m atching networks significantly improved the perform ance o f the sharedcurrent PA. Standing the term ination resistors on edge, adjusting their value, and
shortening the transformer lengths on the pow er splitter and com biner reduce their
com bined insertion loss by about 1 dB and increase return loss and isolation. Changing
th e im pedance matching element values and position result in approxim ately 6 dB
additional gain from a single stage EPA720A-180F. Further pow er splitter, pow er
com biner, and impedance m atching network enhancements are discussed in Sections
6.2.2 and 6.2.3, respectively.
6.1.2
C om parison with M odern Perform ance Standards
The goal o f the shared-current PA design is to m ake possible an ultra high-
efficiency (U H E) telemetry transm itter that doubles both the operational frequency band
and output pow er o f conventional designs w hile consuming the sam e power. The DC
current draw o f a conventional 2.2 - 2.4 G H z 5 W telem etry transm itter is 1.8 A from a
28 V ± 4 V supply. The 4.5 - 4.8 G H z 10W shared current PA draw s less than 1.2 A
from a 23 V supply. The 4.5 - 4.8 G H z transmitter phase-locked loop, VCO, prescalers,
and driver am plifiers draw approxim ately 0.65 A from a 28 V ± 4 V supply. When
installed in the transmitter, the shared-current PA increases the transm itter current draw
to 1.85 A m axim um . The pow er required by a conventional 2.2 - 2.4 GHz transm itter is
50.4 W from a 28 V supply. The pow er required by a UHE 4.5 - 4.8 G H z transm itter is
51.8 W from a 28 V supply. The shared-current PA doubles the output pow er and
frequency o f a telem etry transm itter w hile requiring approxim ately the sam e power.
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143
The 4.5 - 4.8 G H z 10 W shared-current PA m akes possible telem etry transmitters
that are substantially m ore efficient than m odem conventional transm itters. Figures 6.1,
6 .2 ,6 .3 ,6 .4 , and 6.5 com pare the perform ance and characteristics o f the UHE telemetry
transm itter to conventional transm itters with the same operating frequency range, power
level, and supply voltage [50] [51] [52]. CT1, CT2, and CT3 are the conventional
transmitters.
8.00
jV' ?:
i
r^*.;
v.;£;
mm
2 5.00
8B & H
"
g 3.00
.-■-.V! •
Vr
%
asm*
?vS«gM
.J-a
n^-rvMm4k&m,
\\
i*rwAi
m m m
WMi'Cf-W
?:v-
.. .. .
0.00
UHE
CT1
CT2
CT3
Transmitter
Figure 6.1 C urrent Draw o f UHE and Conventional T ransm itters.
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-J
UHE
CT1
CT2
CT3
Transmitter
F igure 6.2 Dissipated Power o f UHE and C onventional Transmitters.
UHE
CT1
C T2
CT3
Transmitter
Figure 6.3 Efficiency o f UHE and C onventional Transmitters.
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14 5
80.0
T 50.0
~ 40.0
u
S.
2 0 .0
•r?rxw
*■.H*1- .*?*•.t - i
UHE
CT2
CT1
CT3
Transmitter
Figure 6.4 Package Size o f UHE and C onvention al Transm itters.
UHE
CT1
CT2
CT3
Transmitter
Figure 6.S W eight o f UHE and C onvention al Transmitters.
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146
The UHE transmitter exceeds com peting transm itter perform ance and characteristics by a
factor two or greater in every instance. The UHE transmitter dissipates 41.8 W worstcase. The closest com peting transm itter dissipates 88 W but is nearly 6 times as large
and weighs 4 times as much. The U H E transm itter package size and weight are 8.8 in3
and 12 oz., respectively. The closest com peting transm itter is 32.4 in3 and 29 oz. but
dissipates over 3 times as much pow er. The shared-current PA m akes possible m iniature,
low-cost, ultra high-efficiency transm itters that exceed modem transm itter standards.
6.1.3
Applications o f H igh-E fflciency PAs and Transmitters
The efficiency im provem ent o f the shared-current PA and UHE transm itter over
m odem conventional designs has m an y applications for systems engineers. Replacing a
conventional transmitter with a UHE transm itter may free up 1.7 to 5.7 A o f supply
current. The newly available current m ay be used for additional system processing
circuitry o r may result in pow er su p p ly savings.
Battery and heat sink size are often determ ining factors in flight time and range in
airborne applications. Reducing the transm itter size while significantly improving
efficiency reduces overall system size and weight. Higher efficiency transmitters require
less battery power and smaller, lighter heat sinks.
The shared-current PA concept has been utilized in L- and S-band (1.4 - 2.4 GHz)
applications to double transm itter efficiencies [53]. In these applications, a conventional
transm itter may be replaced with a U H E transm itter with approxim ately 50% savings in
current draw. Alternatively, a conventional transm itter may be replaced with a UHE
transm itter with twice the output pow er. Pow er dissipation and current draw both
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147
decrease. D oubling the output pow er o f a transm itter is required if the transmission
distance m ust double or the data rate must double with no change in received signal-tonoise ratio.
6.2 Future W ork
The application o f this research is to develop a high-efficiency PA for a new line
o f low-cost m iniature airborne telem etry transm itters in the 4.5 - 4.8 GHz military
telem etry frequency band. M any improvements may be m ade to the shared-current PA
designed in C hapter 4 to enhance performance, m anufacturability, and reliability. The
shared-current concept m ay also be applied to other frequency bands and power levels to
expand the application o f the new design to other markets.
6.2.1
DC Bias Network
The am bient, low, and high temperature tests on the shared-current PA show
variations in
V Ds , V Gs ,
and IG- W hile none o f the m easurem ents exceed maximum device
ratings, im provem ents may be made to the bias circuit to im prove PA reliability.
C onnecting a Zener diode from the source terminal to circuit ground on all the
devices except the bottom device helps prevent an over-bias condition. The reliability o f
a device significantly degrades as Vos exceeds the maximum continuous rating. The
Zener diode is installed with reverse bias so that when the applied voltage exceeds its
reverse breakdow n voltage, the resistance o f the diode is m inim al and node voltage is
regulated. For the shared-current PA designed in Chapter 4, th e Zener diode voltages are
selected to prevent more than V DS = 8 V on any one device. A 8.5 V Z ener diode
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148
connected from the m iddle device source to ground and a 16.0 V Z ener diode connected
from the top device source to ground protect all three devices from over-bias.
Installing Z en er diodes in the bias circuit helps prevent d am age to the other
devices when a single device fails. If no Z ener diodes are installed in the circuit and a
gate fuses to a drain o r source in any device, all three devices w ill be destroyed. When
the gate fuses, the voltage across that device reduces to IDss *
R -d s o ,
w here
R dso
is the
channel resistance w ith Vos = 0. Since the supply voltage is regulated, the voltage across
the other two devices increases substantially. Depending on w hich device fails, the other
two are destroyed b y over-bias or forward gate-source biasing o r both. Connecting Zener
diodes in the bias circuit regulates the m axim um node voltages an d prevents over-bias
and forward gate-source biasing. To fully protect the other devices w hen a device fails,
the Zener diode m ust be capable o f passing the maximum PA current.
A ny variation in gate-source bias changes the device channel resistance, resulting
in drain-source voltage variation. During operation, the gate current o f each EPA720A180F produces a voltage across the 100 Q gate resistor. Since g ate current changes with
frequency and tem perature, the gate-source bias o f each device also changes with
frequency and tem perature. Reducing the gate resistance reduces the gate-source and
drain-source voltage variations.
6.2.2
Power Splitter/C om biner
The combined insertion loss o f the m odified pow er splitter and combiner
m easures approxim ately 1 dB from 4.5 - 4.8 GHz. C haracterizing the terminations and
physical layout o f the p o w er splitter and com biner may result in low er insertion loss,
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149
higher isolation, and lower V SW R . A test fixture consisting o f signal launchers
connecting to 50 Q transm ission lines with term inations oriented on their edge inserted
betw een the lines may be sw ept in frequency w ith a vector network analyzer to
characterize the impedance o f each termination. The impedance measurements m ay be
incorporated into a sim ulation to optimize the pow er splitter and com biner performance.
The physical layout o f the transm ission lines m ay also be simulated with a 3-dim ensional
electrom agnetic simulator such as Sonnet to evaluate the proximity and shape o f the
lines.
O ther power splitter and com biner designs such as a modified 3-w ay W ilkinson
with crossover connected term inations may be evaluated and compared with the 3-way
tw o-stage fork power splitter and combiner. A n y reduction in insertion loss increases PA
gain, output power, and efficiency.
6.2.3
Im pedance M atching Network
The impedance m atching circuits used in the shared-current PA are derived from
bench tuning. The poor perform ance o f the initial im pedance matching network is likely
due to inaccurate C urtice-Ettenburg model param eters o r errors in the 180-mil package
model. A ny deviation from the conditions under which the Curtice-Ettenburg model
param eters and package model are developed causes inaccuracies in device m odeling and
sim ulations. The EPA720A Curtice-Ettenburg m odel parameters are derived w ith V ds =
8 V and
I dq
= 0.5 x lDss [27]. In th e shared-current PA, V DS = 7.5 V and IDQ = 0.4 x IDss
nom inally. T he other possible source o f m odeling error is that the devices are self-biased
in the shared-current configuration.
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150
To im prove gain and efficiency from 4.5 - 4.8 GHz, the input and output
impedances o f th e EPA 720A-180F may b e characterized under nom inal operating
conditions by load-pulling the device at several frequencies from 4.5 - 4.8 GHz. During
load-pulling, the gain and efficiency o f the device are optimized at a single frequency.
Device im pedances are m easured when perform ance is optimized w ith V ds = 7.5 V, Idq =
0.4 x loss, and the device self-biased. The m easured impedances m ay be used to create
an S-param eter model. D esigning an im pedance m atching network utilizing the
measured S-param eters optim izes device gain and efficiency.
6.2.4
W ider Bandw idth Designs
The 4 - 5 GHz m ilitary telemetry bands are 4.5 - 4.8 GHz (6.5 % bandwidth) and
a wider band from 4.4 - 5.0 G Hz (12.8 % bandwidth). The shared-current PA designed
in Chapter 4 m ay incorporate the enhancements discussed in Sections 6.2.1 though 6.2.3
for a final optim ized 4.5 - 4.8 GHz PA design.
The 4.5 - 4.8 G Hz shared-current PA does not incorporate enough impedance
matching elem ents for efficient operation from 4.4 - 5.0 GHz. The im pedance
transformation ratio per elem ent is too large for optim al perform ance across larger
bandwidths. A n experim ental rule o f thum b is 2.5 % maximum bandw idth per
impedance m atching elem ent without feedback. The 4.5 - 4.8 G H z PA designed in
Chapter 4 utilizes three input and three output im pedance matching elem ents limiting the
optimal bandw idth to approxim ately 7.5 % . The guideline requires at least five input and
five output m atching elem ents to impedance match the EPA720A-180F from 4.4 - 5.0
GHz. For m axim um gain and efficiency, the im pedances o f the EPA 720A -180F may be
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151
characterized by load-pulling the device from 4.4 - 5.0 GHz in 100 M H z steps. The gain
o f the device decreases as the operational bandwidth increases due to th e d ev ice’s finite
gain-bandwidth product.
The pow er splitter and com biner performance m ust also be evaluated from 4.4 5.0 GHz. The 3-w ay tw o-stage fork splitter and com biner may be expanded to a threestage architecture to im prove perform ance across the w ider 4.4 - 5.0 G H z bandwidth.
6.2.5
H igher Power D esigns
The 10 W shared-current PA is presently the highest pow er shared-current design.
The shared-current concept m ay be applied to higher pow er PAs. As o u tp u t pow er
increases, pow er supply and cooling system designs becom e increasingly com plex.
Improving the efficiency o f high pow er PAs may result in substantial co st savings.
The relationship betw een decoupling network ESR and device p o w er m ust be
more carefully evaluated as output pow er increases. Sixteen high-Q capacitors are
connected betw een the E PA 720A -180F source and circuit ground to p rovide an ESR less
than 125 m Q from 4.5 - 4.8 G H z. As ESR increases, the pow er dissipated in the
decoupling netw ork increases, and PA efficiency decreases. These effects are minimal
for very low decoupling netw ork ESR. Larger decoupling network ESR results in
changes in the input im pedance o f the device. An empirical relationship betw een
tolerable device input im pedance variance across the operational bandw idth and
decoupling netw ork ESR m ay be derived to determine the num ber o f decoupling
capacitors required for high p o w er applications.
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152
6.2.6
Telem etry T ransm itter Design
The shared-current 4.5 - 4.8 GHz PA is the foundation for developing 4.5 - 4.8
GHz 10 W and 4.4 - 5.0 GHz 10 W UHE telem etry transmitters. Existing L- and S-band
phase-locked loop designs m ay be used provided the VCO and prescalers are modified
for higher frequency operation and the loop bandw idth is adjusted. T he transm itter
housing, driver am plifier stages, and harmonic filter m ust be designed to com plete the 4.4
- 5.0 GHz and 4.5 - 4.8 GHz UHE telemetry transm itters. The shared-current concept
may be applied to the driver amplifier stages to m axim ize transm itter efficiency.
Prelim inary channelized transm itter layouts result in a maximum package size o f 8.8 in3.
A block diagram o f a channelized UHE telem etry transm itter is show n in Figure 6.6.
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153
_CCK
'6 .0 MHz
^ rence
re
■P R O G R A M M A B L E I
;
H
I
PH ASE
DETECTOR
niiiil
VhC
,______
AMP.PER i
5.RR!
i— i C AR
R IER
r REC
r*— !
i
!----
S 'A G E S
i
T
DP
’:L ” ER
■TREQUENCY
S E l ECT
1
■v\V
r i\A .
A \'T
“ ; :
.CW PASS
E '_ r ER
M O C J U T iC M
'N P 'jT
<\
Figure 6.6
^
DEV A ' I
*
AC-. OS'
UHE Telem etry Transm itter Block Diagram .
The package size, connectors, and connector pinouts for the UHE telem etry transm itters
are shown in Figure 6.7.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Figure 6.7
6.2.7
UHE Telemetry T ransm itter Package.
O ther Power A m plifier and Telemetry T ransm itter Designs
The most frequently used m ilitary telemetry frequency bands are 1.43 - 1.54
GHz, 1 .7 1 -1 .8 5 GHz, 2.2 - 2.4 GHz, 4.4 - 5.0 G Hz, and 5.25 - 5.85 GHz. A com plete
ultra high-efficiency telem etry transm itter line consists o f designs in these frequency
bands w ith output pow ers o f 2 W, 5 W, 10 W, and 20 W.
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155
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Pozar, David M., Microwave and RF Design of Wireless Systems, John Wiley &
Sons, pgs 98-106,189-222,2001.
[2]
DBS Microwave, “Application N otes”, www.dbsmw.conv AppnOO 1.htm,
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[3]
W eik, Dr. M., Communications Standard Dictionary, 2nd Edition, Van Nostrand
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[4]
Albulet, Mihai, RF Power Amplifiers, Noble Publishing, A tlanta, GA, 2001.
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Philips Semiconductor, “Therm al A spects o f Flange-M ounted R F Power
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[9]
Rice, Jed, “LDMOS Linearity and R eliability” , Microwave Journal. pp. 64-72,
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C alifornia Eastern Laboratories, “Application o f M icrowave G aA sFE T s”,
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[12]
Filtronic Solid State, “Application N otes - Discrete FET / PH E M T Devices”,
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156
[13]
Pengelly, Raymond P., M icrow ave Field-Effect Transistors, N oble Publishing,
Atlanta, 1994.
[14]
Bailey, Michael J., “PHEM T Devices O ffer High Power D ensity and Efficiency”,
M icrowaves and RF, pp. 61-70, February 1997.
[15]
V ishay Products, “Thin-Film Resistors” ,
w w w .vishav.com /products/resistors/thin film.html. 2001.
[ 16]
BC Components, “Choosing R esistors for M icrowave A pplications”,
w w w .arrowuk.com /newproducts/issue three.pdf. 2001.
[17]
Bowick, Chris, RF Circuit D esign, Newnes, pp. 1-43, 1982.
[18]
Coilcraft, “Modeling C oilcraft RF Inductors”,
w ww.coilcrafi.com/ds/model rf.pdf, Septem ber 2001.
[19]
AVX Corporation, “ Introduction to M icrow ave Capacitors” ,
w w w .avxcorp.com /docs/catalous/m icintro.pdf. pp. 81-92, 2002.
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