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Silicon-on-sapphire technology for microwave circuit applications

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UNIVERSITY OF CALIFORNIA, SAN DIEGO
UNIVERSITY OF CALIFORNIA, SAN OlEGO
SAN DCG O
3 1822 02342 9608
"3”i 822 023429608"
Silicon-on-Sapphire Technology
for Microwave Circuit Applications
A dissertation submitted in partial satisfaction of the
requirements for the degree Doctor of Philosophy
in Electrical Engineering (Applied Physics)
by
Robb Allen Johnson
Committee in charge:
Professor Peter M . Asbeck, Chair
Professor Lawerence E. Larson
Professor Edward T. Yu
Professor Guann-Pyng Li
Professor Michael J. Sailor
1997
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UMI Number: 9804518
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Copyright 1997. by UMI Company. All rights reserved.
This microform edition is protected against unauthorized
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Cop\Tight ©
Robb A. Johnson. 1997
All rights reserv ed
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The dissertation of Robb Johnson is approved,
and it is acceptable in quality and form for
publication on microfilm:
Chair
University of California. San Diego
1997
111
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To my family, friends
and loved ones.
iv
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Table of Contents
Signature Page.................................................................................................................... iii
Dedication............................................................................................................................ iv
Table of Contents..................................................................................................................v
List of Figures......................................................................................................................xi
List of Tables.....................................................................................................................xix
Acknowledgements............................................................................................................ xx
Vita....................................................................................................................................xxiv
Publications......................................................................................................................xxiv
Abstract............................................................................................................................ xxvi
1. Introduction........................................................................................................................1
1.1 Motivation................................................................................................................... I
1.2 Digital CMOS-on-Sapphire......................................................................................3
1.3 Dissertation Objectives............................................................................................. 4
1.4 References...................................................................................................................5
2. Silicon-on-Insulator Technologies..................................................................................6
2.1 Introduction.................................................................................................................6
2.2 Silicon-on-Oxide Technologies................................................................................6
2.2.1 Bonded Etch Back SOI (BESOI)...................................................................... 7
2.2.2 Separation by Implantation of Oxygen (S IM O X )............................................ 8
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2.2.3 Unibond™............................................................................................................9
2.3 Thin Film Silicon-on-Sapphire Technology...........................................................10
2.4 Summary................................................................................................................... 14
2.5 References................................................................................................................. 14
3. Microwave Field Effect Transistor............................................................................. 16
3.1 Introduction............................................................................................................... 16
3.2 Metal-Oxide-Semiconductor Field Effect Transistor............................................ 16
3.2.1 Operation........................................................................................................... 18
3.2.2 DC Characteristics............................................................................................21
3.2.3 AC Characteristics............................................................................................22
3.2.4 Noise Characteristics........................................................................................24
3.3 Silicon-on-Insulator MOSFET................................................................................ 25
3.3.1 Fully vs. Partially Depleted.............................................................................. 26
3.4 SOS M OSFET for Digital Applications................................................................ 28
3.4.1 Processing..........................................................................................................28
3.4.2 DC Characteristics............................................................................................32
3.4.3 AC Characteristics............................................................................................38
3.4.4 Circuit Performance..........................................................................................40
3.5 SOS M OSFET for Microwave Applications......................................................... 40
3.5.1 Microwave versus Digital................................................................................ 40
3.5.2 Device Processing.............................................................................................41
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3.5.3 DC Characteristics............................................................................................ 51
3.5.4 AC Characteristics............................................................................................ 5 1
3.5.5 Noise Characteristics........................................................................................ 53
3.5.6 Small Signal Modeling..................................................................................... 55
3.6 Conclusion................................................................................................................57
3.7 References................................................................................................................. 57
4. Polysilicon Sidewall Gate LDD M O S FE T.................................................................60
4.1 Introduction............................................................................................................... 60
4.2 Computer Simulations............................................................................................. 63
4.2.1 DC Characteristics............................................................................................ 64
4.2.2 AC Characteristics............................................................................................ 67
4.2.3 Design Tradeoffs - Johnson Figure of Merit................................................... 70
4.3 Device Processing.....................................................................................................71
4.3.1 Island Etch and LDD Implant...........................................................................72
4.3.2 LDD Stack Deposition and Etch...................................................................... 73
4.3.3 Channel Implant, Gate Oxide, and Gate Sidewall Formation....................... 73
4.3.4 LDD Etch and Source/Drain Implant............................................................... 76
4.3.5 Oxide Sidewall Formation and Salicidation................................................... 77
4.3.6 Backend Processing...........................................................................................77
4.3.7 T-Gate Processing..............................................................................................78
4.4 DC Characteristics.................................................................................................... 79
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4.5 Microwave Characteristics....................................................................................... 81
4.5.1 Gate-Drain Capacitance.................................................................................... 84
4.6 Key Processing Issues.............................................................................................. 85
4.6.1 Self-Aligned Silicide......................................................................................... 85
4.6.2 Leakage Current.................................................................................................91
4.7 Integration with Standard C M O S ............................................................................ 94
4.8 Conclusion................................................................................................................ 98
4.9 References................................................................................................................. 98
5. Passive Elements........................................................................................................... 99
5.1 Introduction............................................................................................................... 99
5.2 Spiral Inductors.........................................................................................................99
5.2.1 Processing........................................................................................................ 101
5.2.2 Microwave Characteristics...............................................................................103
5.2.3 Modeling.......................................................................................................... 105
5.2.4 Comparison with Bulk Silicon and S O I......................................................... 110
5.3 Metal-Insulator-Metal Capacitors.......................................................................... 114
5.3.1 Processing....................................................................................................... 115
5.3.2 Microwave Characteristics............................................................................. 118
5.4 Thin Film Resistors................................................................................................. 120
5.4.1 Processing.......................................................................................................120
5.4.2 DC Characteristics...........................................................................................123
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5.5 Conclusion.............................................................................................................125
5.6 References.............................................................................................................. 126
6. Microwave Circuits................................................................................................... 127
6.1 Introduction............................................................................................................ 127
6.2 System Requirements............................................................................................ 127
6.3 System Characterization....................................................................................... 129
6.3.1 Two-tone Linearity Characterization........................................................... 130
6.3.2 Noise Characterization.................................................................................. 132
6.4 Low Noise Amplifier........................................................................................... 133
6.4.1 Simulations....................................................................................................135
6.4.2 Measured Results.......................................................................................... 136
6.4.3 Comparison to Other Technologies..............................................................137
6.5 Mixer...................................................................................................................... 140
6.5.1 Simulations.................................................................................................... 141
6.5.2 Measured Results...........................................................................................142
6.5.3 Comparison to Other Technologies..............................................................143
6.6 Transmit/Receive Switch......................................................................................144
6.6.1 Simulations.................................................................................................... 146
6.6.2 Measured Results...........................................................................................148
6.6.3 Comparison to Other Technologies.............................................................. 150
6.7 Power A m plifier................................................................................................... 151
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6.8 Conclusion and Future Work.................................................................................153
6.9 References...............................................................................................................153
7. Conclusions and Future W ork.................................................................................. 156
7.1 Summary of the Dissertation.................................................................................156
7.2 Future W ork............................................................................................................158
7.2.1 Refinement of the T-gate MOSFET Processing.......................................... 158
7.2.2 Refinement of the SiGFET Processing......................................................... 159
7.2.3 Integrated Transceiver.................................................................................... 160
Appendix A. FET Parameter Extraction from S-parameters....................................... 162
Appendix B. Inductor Small-Signal Models................................................................... 181
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List of Figures
Figure 1-1. Block diagram of a transceiver........................................................................ 2
Figure 1-2. Realization of a multi-chip transceiver........................................................... 3
Figure 2-1. BESOI process sequence.................................................................................. 7
Figure 2-2. SIM O X process sequence.................................................................................9
Figure 2-3. Unibond™ process sequence......................................................................... 10
Figure 2-4. SOS process sequence..................................................................................... 12
Figure 2-5. Peregrine Semiconductor's UTSi® Silicon-on-Sapphire before
improvement (left) and after improvement (right)....................................................12
Figure 3-1. MOSFET proposed by Lilienfeld [1] and Heil [2]....................................... 17
Figure 3-2. Cross section of a modem day n-channel MOSFET.................................... 18
Figure 3-3. Band diagram of the channel region of an NMOS transistor in (a)
accumulation, (b) depletion, and (c)inversion.........................................................20
Figure 3-4. I-V characteristics of an ideal M OSFET...................................................... 22
Figure 3-5. Small signal model of the MOSFET.............................................................23
Figure 3-6. Equivalent circuit for noise analysis............................................................. 24
Figure 3-7. Cross section of a MOSFETs fabricated in (a) bulk silicon and (b) siliconon-sapphire.................................................................................................................. 25
Figure 3-8. Parasitics in a bulk CMOS process............................................................... 26
Figure 3-9. I-V Characteristics of a partially depleted SOI MOSFET...........................28
Figure 3-10. Process sequence for a digital MOSFET in SOS.......................................31
Figure 3-11. I-V characteristics of a 0.5 |im x 50 jim (left) and 0.5
x 100 |im
(right) n-MOSFET...................................................................................................... 32
Figure 3-12. Sub-threshold characteristics of a 0.5 (im x 100 |im NM OS....................34
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Figure 3-13. Sub-threshold characteristics of a 0.5 pm x 100 (im NM OS with edge
implant......................................................................................................................... 35
Figure 3-14. I-V characteristics o f a 0.5 Jim x 50 pm (left) and 0.5 pm x 100 pm
(right) p-MOSFET.......................................................................................................36
Figure 3-15. Sub-threshold characteristics of a 0.5 pm x 100 pm PMOS.................... 37
Figure 3-16. I-V characteristics of ten 0.5 pm x 100 pm NMOS across the wafer
38
Figure 3-17. Microwave performance of a 0.5 pm x 100 pm digital n-channel
M OSFET......................................................................................................................39
Figure 3-18. Microwave performance of a 0.5 pm x 100 pm digital p-channel
MOSFET......................................................................................................................39
Figure 3-19. Process sequence for a "T-Gate" transistor.................................................43
Figure 3-20. SEM cross section of a FET after spinning on planarization resist
44
Figure 3-21. SEM cross section of a FET after the planarization etch..........................44
Figure 3-22. SEM cross section of the metal "T-gate" (with resist).............................. 45
Figure 3-23. Size effect on planarization (a) small feature, (b) large feature.............. 46
Figure 3-24. Loading effect on planarization...................................................................46
Figure 3-25. Result of misalignment of gate metal photoresist.................................... 47
Figure 3-26.
SEM cross section of a FET destroyed during metal etch....................... 48
Figure 3-27. Improper T-gate planarization near a gate contact pad............................. 49
Figure 3-28. Test structure for T-gate planarization verification....................................50
Figure 3-29. Microwave performance of a 0.5 pm x 100 pm T-Gate n-channel
M OSFET..................................................................................................................... 52
Figure 3-30. Microwave performance of a 0.5 pm x 100 pm T-Gate p-channel
M OSFET..................................................................................................................... 52
Figure 3-31.
Noise figure of 0.5 pm x 100 pm T-gate MOSFETs.............................. 54
Figure 3-32.
Associated Gain of 0.5 pm x 100 pm T-gate MOSFETs........................ 54
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Figure 3-33. Small signal model of the SOS M OSFET................................................. 56
Figure 4-1. Cross section of a MOSFET with a symmetric lightly doped drain
61
Figure 4-2. Schematic cross section of the SiGFET....................................................... 62
Figure 4-3. SiGFET structure used for device simulations............................................ 64
Figure 4-4. Simulated I ds vs. V ds characteristics of a Lg = 0.25 (im SiGFET with L ldd
= 0.7 |im ...................................................................................................................... 65
Figure 4-5. Simulated transconductance vs. gate voltage of a Lg= 0.25 |im SiGFET
with L ldd = 0.7 pm.....................................................................................................66
Figure 4-6. Simulated B.V. vs. LDD length for a SiGFET with Lg = 0.25 pm
67
Figure 4-7. Simulated AC characteristics of a Lg = 0.25 pm SiGFET with LLdd = 0.7
pm................................................................................................................................ 67
Figure 4-8. Simulated/t vs. LDD length of a SiGFET with Lg = 0.25 pm SiGFET....68
Figure 4-9. Simulated transit time vs. LDD length of a SiGFET with Lg = 0.25 pm. .69
Figure 4-10. Simulated Johnson figure of merit for a Lg = 0.25 pm SiGFET with L ldd
= 0.7 pm.......................................................................................................................71
Figure 4-11. Processing steps of the SiGFET.................................................................. 72
Figure 4-12.
Polysilicon sidewall etch with H Br........................................................... 75
Figure 4-13.
Polysilicon sidewall etch without
HBr................................................ 76
Figure 4-14. Final structure of the SiGFET..................................................................... 78
Figure 4-15.
I Ds vs. V ds curves for a Lg = 0.25
pm,W g = 50 pm SiGFET.............79
Figure 4-16.
IDs vs. V ds curves for a Lg = 0.25
pm,W g = 100 pm SiGFET...........80
Figure 4-17. I ds vs. V Ds characteristics of a SiGFET (Lg = 0.25 pm, W g = 100 pm,
L ldd = L0 pm) at high gate bias................................................................................81
Figure 4-18. Microwave characteristics of a SiGFET with Lg = 0.25 pm and L ldd =
1.0 pm....................................................................................................................... 82
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Figure 4-19. Microwave characteristics of a T-Gate SiGFET (Lg = 0.25 pin, L ldd =
1.0 pirn) at V GS = 1.5 V, V DS = 4 V ........................................................................... 83
Figure 4-20. Microwave characteristics of a T-Gate SiGFET (Lg = 0.25 pm. L ldd =
1.0 pm) versus bias..................................................................................................... 84
Figure 4-21. SiGFET with sidewall gate (a) shorted and (b) not shorted to the gate
contact by silicidation................................................................................................. 86
Figure 4-22. Schematic representation of a SiGFET without shorting of the gates by
silicidation................................................................................................................... 87
Figure 4-23. I Ds vs. V DS characteristics of a SiGFET (Lg = 0.25 pm, W g = 50 pm,
L ldd = 1-0 pm) after application of V Gs = 10 V .......................................................88
Figure 4-24. IDS (at V GS = 10, V DS = 5 V ) as a function of time showing the time
necessary to charge the floating gate......................................................................... 89
Figure 4-25. I ds vs. V ds characteristics of a SiGFET (Lg = 0.25 pm. W g = 50 pm,
L ldd = 1-0 pm) after application of V GS = -10 V ..................................................... 90
Figure 4-26. I ds (at V GS = - 10, V ds = 5 V) as a function of time showing the time
necessary to discharge the floating gate.................................................................... 91
Figure 4-27. Simplified layout (top view) of the SiGFET showing the leakage path..92
Figure 4-28. SEM of a SiGFET with the leakage current path destroyed by laser
trimming...................................................................................................................... 93
Figure 4-29. I ds vs. V ds characteristics of a SiGFET before and after laser
annihilation..................................................................................................................93
Figure 4-30. I ds vs. V d$ characteristics of a SiGFET before and after leak path was
blown........................................................................................................................... 94
Figure 4-31. Integration of the SiGFET with standard CMOS processing................... 96
Figure 5-1. Cross section of the spiral inductors: (a) SOS, (b) Bulk Silicon.............. 102
Figure 5-2. Photograph of an 8 mm spiral inductor...................................................... 103
Figure 5-3. Inductance and quality factor for an 8 turn inductor on SOS....................104
Figure 5-4. Peak quality factor and self-resonant frequency of inductors on SOS.... 105
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Figure 5-5. Simple small-signal model for inductors on SOS.....................................105
Figure 5-6. Measured versus modeled, inductance and quality factor, for a 4 mm
inductor on SOS....................................................................................................... 106
Figure 5-7. Modified small-signal model for inductors on SOS................................. 107
Figure 5-8. Measured vs. modeled, inductance and Q, for simple and modified
inductor models........................................................................................................ 108
Figure 5-9. Improved small-signal model for inductors on SOS................................ 109
Figure 5-10. Measured inductance ans Q vs. modified model for an 8 mm inductor on
SOS............................................................................................................................110
Figure 5-11. Measured inductance and Q vs. modified model for an 8 mm inductor on
SOS and bulk silicon................................................................................................111
Figure 5-12. Self-resonant frequency and peak quality factor for inductors with 5 pm
width and 5 pm spacing........................................................................................... 111
Figure 5-13. Improved small-signal model for inductors on bulk silicon................... 112
Figure 5-14. Comparison of recently reported inductors on silicon.............................114
Figure 5-15. M IM capacitor and metal 1 to metal 2 via process sequence..................116
Figure 5-16. Layout of the M IM capacitor..................................................................... 117
Figure 5-17. Photograph of a fabricated M IM capacitor (200 pm x 200 pm).............117
Figure 5-18. Admittance (y 1 1 ) of four capacitors with different are and oxide
thickness.................................................................................................................... 119
Figure 5-19. Capacitance of four capacitors with different areas and oxide
thickness................................................................................................................... 119
Figure 5-20. Thin-film resistor process sequence.......................................................... 121
Figure 5-21. Mask layout of a thin-film resistor...........................................................122
Figure 5-22. Photograph of test patterns for thin-film resistors.................................. 122
Figure 5-23. Current-Voltage characteristics of nine resistor of various lengths and
widths........................................................................................................................123
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Figure 5-24. Sheet resistance of nine resistors of various lengths and widths
124
Figure 5-25. Wafer map of resistor sheet resistance...................................................... 125
Figure 6-1. Typical super-heterodyne receiver architecture.......................................... 128
Figure 6-2. Typical transmit architecture........................................................................ 129
Figure 6-3. Setup for two-tone measurements................................................................131
Figure 6-4. Output power vs. input power for a typical two-tone test.........................132
Figure 6-5. Setup for measuring system noise................................................................ 133
Figure 6-6. Schematic of the single stage low noise amplifier......................................134
Figure 6-7. Photograph of the fabricated low noise amplifier (The Size: 1.3 mm x 0.95
mm)..............................................................................................................................134
Figure 6-8. Measured gain and matching of the LN'A....................................................136
Figure 6-9. Power transfer characteristics of the LNA (V DS = 1.5 V. V GS = 0.7V. IDS =
8.5 m A )..................................................................................................................... 137
Figure 6-10. LN A Gain to DC Pow'er ratio versus noise figure for different
technologies................................................................................................................ 138
Figure 6-11. LN A linearity versus DC power dissipation for different technologies. 138
Figure 6-12. Schematic of the mixer............................................................................... 140
Figure 6-13. Photograph of the fabricated mixer (Die Size: 1.2 mm x 0.875 m m )... 141
Figure 6-14. Simulated results of the mixer....................................................................142
Figure 6-15. Measured two-tone power transfer characteristics of the mixer
143
Figure 6-16. Schematic of the transmit/receive switch.................................................. 146
Figure 6-17. Photograph of the fabricated transmit/receive switch (Die Size: 1.2 mm x
0-55 m m ).....................................................................................................................146
Figure 6-18. Simulated and measured insertion loss and isolation of the
transmit/receive switch..............................................................................................147
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Figure 6-19. Comparison of measured insertion loss and isolation of the
transmit/receive switch fabricated on SOS and SIM O X.......................................148
Figure 6-20. Measured power characteristics of the transmit/receive switch............ 150
Figure 6-21. Two-tone measurements of n-channel MOSFETs with L g = 0.5 urn and
W g = 600 urn............................................................................................................ 152
Figure 7-22. T-gate planarization using chemical mechanical polishing................... 15S
Figure 7-23. Sidewall gate transistor utilizing an insulator other than SiO; over the
LDD region.............................................................................................................. 159
Figure 7-24. Dual salicidarion process for a SiGFET..................................................160
Figure A -1. Small-signal model of a FET.................................................................... 162
Figure A-2. Layout of a MOSFET for microwave measurements.............................. 165
Figure A-3. Small signal model of the intrinsic FET with pad parasitics.................. 164
Figure A-4. Open circuit (left) and short circuit (right) structures for determining
pad parasitics............................................................................................................164
Figure A-5. Equivalent circuit of the short.................................................................. 165
Figure A-6. Typical fit of pad parasitic inductances.................................................... 166
Figure A-7. Small signal model of the intrinsic FET with pad inductance
removed.................................................................................................................... 166
Figure A-S. Equivalent circuit of the open....................................................................167
Figure A-9. Equivalent circuit of the open with inductances removed..................... 167
Figure A -10. Typical fit of pad parasitic capacitances................................................. 16S
Figure A -11. Small signal model of the intrinsic FET with pad capacitances
removed.................................................................................................................... 169
Figure A -12. Zero-bias small-signal equivalent circuit.............................................. 170
Figure A -13. Intrinsic FET with gate, source and drain resistance removed............. 171
Figure A-14. Typical plot of Cgd. Cds and Cgs versus frequency.............................. 175
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Figure A -15. Extracted device transconductances vs. frequency................................. 174
Figure A -16. Extracted channel resistance and phase delay versus frequency........... 175
Figure A -17. Measured (dots) and modeled (lines) FET S-parameters....................... 176
Figure A -18. Current, power, and unilateral gain for the measured and modeled
FET.......................................................... 1 ............................................................... 176
Figure B -l. Modified small-signal model of an inductor..............................................181
Figure B-2. Improved small signal model of an inductor..............................................183
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List of Tables
Table 3.1. f and/max for NMOS and PMOS transistors on SOS....................................53
Table 3.2. Comparison of noise figures for different technologies................................55
Table 3.3. Small-signal model parameter of an n-channel M OSFET........................... 57
Table 4-1. Etch conditions of the first polysilicon sidewall etch trial........................... 74
Table 4-2. Etch conditions of the second polysilicon etch trial......................................75
Table 4-3. Mask stpes necessary for the integration of standard CMOS and the
SiGFET........................................................................................................................ 97
Table 5.4. Component values of the modified model for various inductors on SOS and
bulk silicon................................................................................................................. 113
Table 6.1. Representative system requirements for IS-55 receive components
128
Table 6.2. Circuit element values for the LN A .............................................................. 135
Table 6.3. Simulated performance of the LN A .............................................................. 135
Table 6.4. Summary of recent CMOS LNA results....................................................... 139
Table 6.5. Summary of recently reported CMOS mixers.............................................. 144
Table 6.6. Comparison of TR switches for different technologies...............................150
Table A. 1 Small-signal parameter values for a 0.5 mm x 50 mm n-MOSFET.......... 177
Table A.2 Small-signal parameter values for a 0.5 mm x 100 mm n-MOSFET......... 178
Table A.3. Small-signal parameter values for a 0.5 mm x 50 mm p-MOSFET.......... 179
Table B. 1. Parameter values of the modified model for inductors on SOS.................182
Table B.2. Parameter values of the improved model for inductors on SOS................184
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Acknowledgments
The research and writing of a dissertation is not a task to be taken lightly, nor is
it one that can be taken alone. Only through the guidance, help and encouragement of
others can one attain the desired result: a doctorate. This section is devoted to these
people and their support and advice.
The first, and probably most important, person with whom I owe my degree is
Dr. Peter Asbeck.
Throughout my years of schooling, both undergraduate and
graduate, Dr. Asbeck has inspired and counseled me countless number of times. His
kind and gracious manner made him easily approachable with even the simplest of
questions and concerns. He has been a true pleasure to work for and I hope that in my
professional years, I can handle myself with the same demeanor. Thanks for
everything.
Second, I must thank the vision of Dr. S.S. Lau whom encouraged me to enter
graduate school. It was him (as well as a lack of job openings in 1992) that convinced
me to attend graduate school. He saw in me something that others didn't and I am
forever grateful for his support and encouragement.
I would also like to thank all the members of my graduate committee: Dr. Ed
Yu, Dr. Larry Larson, Dr. G.P. Li, and Dr. Mike Sailor.
All of their comments
throughout the years helped tremendously in writing my dissertation.
Thanks for
everything, you were too kind during my defense.
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My family and loved ones were also monumental in my making it through the
years. Their support, both monetarily and mentally, helped to no end. I will forever be
grateful to my parents for their support throughout my life, not just in graduate school.
Miss Van Teng, my fiancee, put up with my long work hours for four years without
too much complaining. She has given me many words of encouragement and support
and I look forward to her giving me many more in my years to come.
There are countless people to thank at NRaD for their help along the way.
Thanks to Dr. Isaac Lagnado for his monetary support and Graham Garcia for allowing
me to use the facilities at NRaD and trust me not to ruin any equipment. Paul “3912”
de la Houssaye has offered his time and help on countless occasions and has been a
pleasure to work with. Shannon Kasa was instrumental in the development of the T gate and sidewall gate process. Her views on life at NRaD were inspirational to say
the least. Thanks to George Imthum and Bruce Offord for their professional advice as
well as introducing me to the sport of rock climbing. Mike Wood was helpful in the
computer world as well as in the engineering world. His advice on computers lead me
to purchase the computer I used to write this dissertation. Mark Roser and Howard
Walker provided me with infinite laughs as well as knowledge of SOS.
Charley
Young is a master of the SEM and all the pictures in this dissertation I owe to him,
either directly, or indirectly because of teaching me his skills. Finally, I would like to
thank all the fab technicians for their help throughout the years. Maria, Sue, Gert,
Basia, and Julio helped push my lots through the lab as fast as possible. They saved
them a number of times be catching mistakes on my run sheets.
Thanks for
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everything. There are countless other people at NRaD whom helped out throughout
the years. If I missed anyone, I am truly sorry but you and I know whom you are and I
will forever be grateful.
I must thank all the members of the UCSD High Speed Devices Group for their
help, support, and friendship throughout the years; in order o f appearance. Charles
Chang has been a great friend and a wonderful hunting partner. His advice and start of
the SOS project are what began this dissertation. I owe him countless thanks for his
work and friendship. Chung-Yin "Ken" Kwok was instrumental in fueling my desire
to learn the Chinese language. It was this desire that lead me to enroll in Chinese class
whereupon I met Miss Teng.
For this I will be forever grateful.
Russ Gee was a
pleasure to work with. It was unfortunate that he wasn't around longer. Min-Chung
"Vincent" Ho has provided me with much information on what it means to be an
American. I knew he wouldn't go back to Taiwan after living in America. Hsin-Hsing
Liao also taught me what it means to be an American. He has been to more National
Parks than anyone I know. Too bad he has been to all the parks in the Western United
States, he should have taken a job back East. I should be able to catch up now that I
will be living in Vermont. Jayaraman Arun offered much advice for circuit design
while Yue-Ming "Tony" Hsin and Sang Park offered much processing advice, as well
as becoming good friends. Pin-Fan “Ed” Chen helped me with many test setups and
circuit designs as well as providing me with countless rides to the airport during the
last couple of months. Gary Hannington provided me with countless advice on both
business and marriage.
Look for my upcoming book of quotes from Gary at a
xxii
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bookstore near you. I'm sure it will hit the New York Times best seller list within a
week of its release. Matt Wetzel is taking over the SOS project and I wish him luck.
Last, but not least, Andre Metzger has provided me, as well as the rest of the group, a
guide as to what it means to be a graduate student. I envy his approach to graduate
school and wish I could have done the same. Andre, despite what people say, don't
change your ways.
All of the members of the High Speed Devices Group have
become good friends and I look forward to seeing them at future conferences. Be sure
to submit papers to all the major conferences so we can have a reunion. For those of
you whom have not yet graduated, good luck with the rest of your research.
Finally, if there is anybody I forgot to mention, I am truly sorry. Your help will
never be forgotten. Thanks to everyone who made this dissertation possible.
xxiii
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Vita
January 9, 1970
Bom, Gainesville, Florida
June 1992
B.S. Electrical Engineering
University of California, San Diego
December 1993
M.S. Electrical Engineering
University of California, San Diego
September 1997
Ph.D. Electrical Engineering
University of California, San Diego
Publications
■ R. A. Johnson, C.E. Chang, P.R. de la Houssaye, M.E. Wood, G.A. Garcia, P.M.
Asbeck, I Lagnado, “A 2.4-GHz Silicon-on-Sapphire CMOS Low Noise Amplifier,”
IEEE Microwave and Guided Wave Letters, vol. 7, no. 10, Oct. 1997.
■ R.A. Johnson, P.R. de la Houssaye, M.E. Wood, G.A. Garcia, C.E. Chang, P.M.
Asbeck, and I. Lagnado, "A Silicon-on-Sapphire MOSFET Transmit / Receive Switch
for L and S Band Transceiver Applications," Electronics Letters , vol. 33, no. 15, July
17th, 1997.
■ R.A. Johnson, S.D. Kasa, P.R. de la Houssaye, G.A. Garcia, L Lagnado, and P.M.
Asbeck, "Novel Polysilicon Sidewall Gate Silicon-on-Sapphire MOSFET for Power
Amplifier Applications," 1997 IEEE International SOI Conference, Fish Camp,
California, Oct. 1997.
■ F. Deng, R.A. Johnson, W.B. Dubbelday, G.A. Garcia, P.M. Asbeck, and S.S. Lau,
"Salicide Process for 400 A Fully-Depleted SOI-MOSFET Using NiSi," 1997 IEEE
International SOI Conference, Fish Camp, California, Oct. 1997.
■ F. Deng, R.A. Johnson, P.M. Asbeck, S.S. Lau, W. B. Dubbelday, T. Hsiao, and J. Woo,
“Salicidation Process Using NiSi and Its Device Applications. Part H,” Journal o f
Applied Physics, vol. 81, no. 12, June 1997.
■ F. Deng, R.A. Johnson, W.B. Dubbelday, G.A. Garcia, P.M. Asbeck, S.S. Lau, "Deep
Salicidation Using Nickel for Suppressing the Floating Body Effect in Partially Depleted
SOI-MOSFET," / 996 IEEE International SOI Conference, Sanibel Island, Florida, Oct.
1996.
xxiv
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■ P.F. Chen, R.A. Johnson, M.C. Ho, W.J. Ho, A. Sailer, M.F. Chang, P.M. Asbeck,
"Microwave and Thermal Characteristics of Backside-Connected Flip-Chip Power
Heterojunction Bipolar Transistors," Electronics Letters, vol. 32, no. 20, Sept. 1996.
■ R.A. Johnson, C.E. Chang, M.E.. Wood, G.A. Garcia, I. Lagnado, P.M. Asbeck,
"Comparison of Microwave Inductors Fabricated on Silicon-on-Sapphire and Bulk
Silicon," IEEE Microwave and Guided Wave Letters, vol.6, no. 9, Sept. 1996.
■ M.C. Ho, R.A. Johnson, C.E. Chang, W J. Ho, D.R. Pehlke, P.J. Zampardi, M.F. Chang,
and P.M. Asbeck, "Base-Collector Capacitance Reduction of AlGaAs/GaAs
Heterojunction Bipolar Transistors by Deep Ion Implantation," IEEE Electron Device
Letters, vol. 16, no. 11, Nov. 1995.
■ R.A. Johnson, C.E. Chang, P.R. de la Houssaye, G.A. Garcia, I. Lagnado, P.M. Asbeck,
"Microwave Characteristics of High /mx Low Noise Thin Film Silicon-on-Sapphire
MOSFETs," 1995 IEEE International SOI Conference, Tucson, Arizona, Oct. 1995.
■ P.M. Asbeck, M.C. Ho, R.A. Johnson, "AlGaAs/GaAs HBTs with High /max," 1995
GaAs and Related Compounds Conference, Aug. 1995.
■ M.C. Ho, R.A. Johnson, C.E. Chang, W J. Ho, D.R. Pehlke, P.J. Zampardi, M.F. Chang,
and P.M. Asbeck, "Base-Collector Capacitance Reduction of AlGaAs/GaAs
Heterojunction Bipolar Transistors by Deep Ion Implantation," 1995 IEEE Device
Research Conference., June 1995.
■ P.R. de la Houssaye, C.E. Chang, B. Offord, R.A. Johnson, P.M. Asbeck, G.A. Garcia,
I. Lagnado, "Silicon MOSFETs with Very Low Microwave Noise," 1995 IEEE Device
Research Conference, June 1995.
■ P.R de la Houssaye, C.E. Chang, B. Offord, G. Imthum, R.A. Johnson, P.M. Asbeck,
G.A. Garcia, I. Lagnado, "Microwave Performance of Optically Fabricated T-Gate Thin
Film Silicon-on-Sapphire Based MOSFETs," IEEE Electron Device Letters, vol. 16, no.
6, June 1995.
xxv
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Abstract of the Dissertation
Silicon-on-Sapphire Technology
for Microwave Circuit Applications
by
Robb Allen Johnson
Doctor of Philosophy in Electrical Engineering (Applied Physics)
University of California, San Diego, 1997
Professor Peter M. Asbeck, Chair
Due to its radiation hardness, silicon-on-sapphire (SOS) technology has
primarily been utilized for military and space-based digital applications. With recent
advances in wireless communication systems, the need to integrate low cost, low
power digital CMOS circuits, together with circuits operating at radio frequency (rf),
has become increasingly important. By developing CMOS transistors optimized for
operation at microwave frequencies along with passive elements needed in rf circuits,
it is shown in this dissertation that SOS technology is very well suited to wireless
applications.
A T-gate process featuring low gate resistance has been utilized to realize
optically defined 0.5 pm gate length MOSFETs with / and/max values above 20 GHz
xxvi
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and 60 GHz for n-channel devices and above 15 GHz and 40 GHz for p-channel
devices. These devices also have excellent noise figures below 1 dB at 2 GHz.
Microwave passive elements including inductors, M IM
capacitors, and
resistors, have been demonstrated for the first time in SOS technology. Due to the
sapphire substrate characteristics, inductors exhibited a factor of two higher quality
factor and 20% improvement in self-resonant frequency, over identical inductors
fabricated on bulk silicon.
A novel deep sub-micron FET designed for power amplifiers has been
investigated.
By utilizing a sidewall process, a 0.15 - 0.25 Jim gate length can be
realized without lithography to define the gate. The device also incorporates a lightly
doped drain region to improve the breakdown voltage of the device. Devices with Lg
= 0.25 |im exhibited/t values around 10 GHz and breakdown voltage of 13 volts.
Finally, initial circuit demonstrations for the rf front end in a wireless radio
application at 2.4 GHz have been done. A transmit / receive switch, mixer, and low
noise amplifier have been demonstrated.
All circuits performed well, and were
superior to bulk CMOS and other SOI technologies.
The successful realization of rf devices and circuits in SOS technology
demonstrated in this dissertation suggest that the integration of the rf front end and low
power digital CMOS used at baseband is eminently feasible and will lead to a
complete radio-on-a-chip solution for wireless communication applications.
xxvii
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1. Introduction
1.1 Motivation
With the recent explosion of the wireless communications market, there arises
a need for low power. low cost circuits operating at microwave frequencies.
Low
power is desirable in portable communication circuits in order to increase battery
lifetime. To address lower power needs in other circuits such as watches, calculators,
stereos and computers, complementary metal-oxide-semiconductor (CM OS) field
effect transistors (FETs) have been used.
While CMOS may meet the technology
requirements for low power, it typically does not meet other requirements for
microwave circuits such as high power gain and low noise.
For circuits operating in the GHz regime, circuit designers have predominately
turned to such technologies as GaAs and InP based heterojunction bipolar transistors
(HBTs) and metal-semiconductor field effect transistors (MESFETs).
Both of these
technologies can address the speed, power gain and low noise requirements but have
other disadvantages. For instance, HBT circuits require a non-zero standby current
that dramatically increases circuit power dissipation.
MESFETs can address this
power issue but as with other H I-V technologies, cost and wafer size limit its
performance to cost ratio.
Figure 1-1 shows a simplified block diagram of a single down conversion
transmitter / receiver (transceiver). This simplified block diagram omits filters and
1
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other elements necessary' in practical transceivers.
The basic blocks are: antenna,
transmit/receive switch. low noise amplifier (LNA). down-conversion mixer, digital
signal processing unit, up-conversion mixer, and power amplifier (PA). Signals
coming into the transceiver at radio frequencies (RF) are down converted to lower,
intermediate frequencies (IFi typically around 25-200 M Hz. For the transmit process.
EF signals out of the DSP unit are up-converted to RF and sent out the antenna.
Figure 1-1. Block diagram of a transceiver.
As mentioned before. CMOS is very useful for low power applications and is
typically used for the digital signal processing at IF.
However, the high speed
requirements of the LN A . PA and mixers typically require EH-V based circuits. For
example, many PAs are fabricated with GaAs MESFETs or HBTs due to their high
output power and high power added efficiency.
MESFETs due to their very low noise.
LNAs typically use GaAs or InP
Hence a typical transceiver package might
have chips of several technologies. A representation of this is shown in Figure 1-2.
Here the chips are assembled on a microwave substrate such as alumina. Chips are
connected to each other via microstrip transmission lines or bond wires. Due to their
parasitic inductances and capacitances, these interconnections can lead to many other
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system and circuit design problems.
If they can be eliminated or reduced by
combining all block into the same technology, including digital and microwave
circuits, the cost of the system is reduced. This integration also allows for a potential
increase in the system performance as well as a reduction in the power dissipation due
to the fact that output drivers, needed to drive the signals off chip to another chip, can
be eliminated. These output driver often account for a large percentage of the total
power dissipation of a chip.
Figure 1-2. Realization of a multi-chip transceiver.
1.2 Digital CMOS-on-Sapphire
The use of CMOS-on-sapphire for digital circuits has been practiced for
decades. Most of silicon-on-sapphire's (SOS) history has been driven by the militarv
and space applications due to SOS's radiation hardness. Because of decreased device
capacitances due to the insulating substraie. SOS CMOS can obtain high speeds with
lower power than bulk CMOS technologies. The power delay product of a 41 stage
ring oscillators with 0.5 pm gate lengths has been shown to be as low as 6 fj. SOS has
also achieved relatively high levels of integration needed for the digital signal
processing aspect of a typical transceiver architecture. To date, the largest circuit on
SOS has over 50.000 transistors. A 16 x 16 bit parallel multiplier with 0.75 urn gate
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4
lengths and a IK SRAM with 1.25 pm gate lengths have been reported by Offord [1],
The multiplier had a loaded gate delay of 243 pS at 5.0 volts supply voltage. The
SRAM exhibited an access time of 20 nS. Sadana [2] has demonstrated 0.25 jim SOS
devices with DC characteristics superior to devices fabricated on other SOI
technologies (SEMOX and BESOI).
1.3 Dissertation Objectives
With the well established digital process, all that is left to achieve the wireless
system integration described earlier is to develop the technology necessary' for circuit
operation at microwave frequencies. This technology includes passive elements such
as thin-film resistors, metal-insulator-metal (M IM ) capacitors, transmission lines and
inductors as well MOSFETs optimized for use at microwave frequencies. This thesis
investigates all of these technology road blocks on the road to RF and digital
integration on the same substrate.
After a brief discussion in Chapter 2 about silicon-on-insulator (SOD
technologies, including silicon-on-sapphire. Chapter 3 will discuss the fabrication of a
high performance metal-oxide-semiconductor field effect transistor (MOSFET). This
chapter discusses
basic
MOSFET
operation
and
then
the
fabrication
and
characterization of a M OSFET targeted for microwave circuit applications. Besides
transistors for microwave circuits, passive elements such as transmission lines, thinfilm capacitors, thin-film resistors and inductors are also needed.
These passive
elements are discussed in Chapter 4 with an emphasis on the inductors, the hardest of
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5
the passive elements to make. Besides a high speed MOSFET, a MOSFET with high
breakdown voltage is often needed for power amplifiers in transceiver application.
Chapter 5 addresses this issue with a novel MOSFET using a polysilicon sidewall gate
and an asymmetric lightly doped drain.
The processing challenges and device
characteristics will be discussed. Finally, by putting together all of the above, silicon
MOSFET based circuits operating at 2.4 GHz and higher will be discussed in Chapter
6. These represent some o f the highest frequency silicon MOSFET based circuits in
existence.
J. Frank Dobie once said, "'The average Ph.D. thesis is nothing more but a
transference o f bones from one graveyard to another." However, this thesis will not
merely raise silicon-on-sapphire from its grave and transfer it to another, it will bring it
back to life.
1.4 References
1. B.W. Offord, "Fully-Depleted Silicon-on-Sapphire and Its Application to
Advanced VLSI Design," 4th NASA Symposium on VLSI Design , University of
Idaho, Oct. 1992.
2. D.K. Sadana, "Fully-Depleted 0.25 pm n-MOSFETs on SOS, S IM O X and BESOI
Substrates," 1994 IEEE International SOI Conference, Oct. 1994.
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2. Silicon-on-Insulator Technologies
2.1 Introduction
In recent years, investigation and research on silicon-on-insulator (SOI)
technologies, including silicon-on-sapphire (SOS), has greatly increased.
This
increase is most notably due to the search for a low-cost, low-power technology for
VLS I applications. SOI structures are advantageous for many reasons: scalability of
device dimensions, improved isolation, resistance to latch up, increased packing
density, simplified processing, increased circuit speed, reduced hot electron effects,
and improved subthreshold slopes.
The two main competing SOI families are silicon-on-oxide and silicon-onsapphire. This chapter will briefly discuss several silicon-on-oxide technologies and
their advantages, disadvantages and respective preparation techniques.
It will also
introduce silicon-on-sapphire and its preparation. Finally, it will compare and contrast
SOS to other SOI technologies.
2.2 Silicon-on-Oxide Technologies
The silicon-on-oxide family has many derivations including BESOI (Bonded
Etch-back SOI), S IM O X (Separation by IMplantation of OXygen), and UNDBOND™
(another form of bonded SOI) to name a few. These technologies are similar in that
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they all have a thin (typically 1000-3000 A) silicon film on top of a thicker (typically
4,000-10,000
A) SiC
>2
layer which is on top of a bulk silicon wafer.
2.2.1 Bonded Etch Back SOI (BESOR
Bonded Etch Back (BESOI) wafers employ wafer bonding and polishing
techniques. The idea of wafer bonding was first demonstrated by Kenney in 1967
using high temperature (1225°C) and high pressure (2000 PSI). Anthony (in 1985) and
Frye (in 1986) were the first to use wafer bonding for SOI applications. Both used low
temperature (850-950°C) bonding techniques.
The process for the formation of
BESOI wafers is shown in Figure 2-1. First, two wafers, a handle wafer and an active
wafer, are thermally oxidized. These two wafers are then bonded by high temperature
(typically between 900-1100°C) anneal with a nitrogen ambient. Next the top active
wafer of polished and etched back to the desired final silicon thickness.
It
ft
Si Wafer (future SOI Layer) ~ k \
n I
Jt
Il | I IPolishing
I I /IEtching
I I
1 1
uTi
1 1 ,
Si Handle Wafer
Si Handle Wafer
(a) Bonding
(b) Thinning
Figure 2-1. BESOI process sequence.
One advantage of BESOI wafers is the excellent backside interface between the
active silicon and the buried oxide. This is due to the fact the buried oxide has been
thermally grown. As we will see next, this is not the case for S IM O X wafers. BESOI
also has several disadvantages. The first if the cost incurred by the sacrificial active
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8
wafer.
BESOI requires two wafers to obtain one.
A second disadvantage is the
difficulty in controlling the final silicon thickness during the polishing and etch back
process. This effect can be reduced by the incorporation of etch stop layers such as
heavily doped regions or porous silicon regions.
A final problem with all wafer
bonding techniques is the formation of voids and bumps in the wafers due to particles
on the wafer surfaces before bonding.
Theses voids and bumps create unbonded
regions and silicon film thickness variations respectively.
2.2.2 Separation by Implantation of Oxygen (SIMOX)
Another form of SOI is S IM O X (Separation by IMplantation of OXygen). In
this system, a high dose and high energy implant of oxygen is used to form the buried
oxide region. Wantanabe and Tooi (1966) were the first to use oxygen implant into
silicon to form SiOi [1]. The S IM O X acronym and first circuits were demonstrated by
Izumi at N T T in 1978. The first commercial (3 to 6 inch) S IM O X wafers became
available in 1987 by IBIS. The S IM O X process is shown in Figure 2-2. The first step
is to perform the high energy implant (typically 120-200 KeV, 2xlO l8/cm2). Both the
energy and dosage determine the final oxide thickness and silicon thickness. The next
step is an anneal process (1300-1600°C, 2-6 hours in N t or Ar) to removed damage
caused by the high energy implant.
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9
I
I
I
I
I
Oxygen Implant
I
Buried Oxide
Si Handle Wafer
Si Handle Wafer
(a) Implant
(b) Anneal
Figure 2-2. SIMOX process sequence.
The SIM O X process has an advantage over the bonded etch back technique in
that it requires only one wafer (eliminating the sacrificial wafer of BESOI). However,
there are some disadvantages with SIM O X.
The first is the formation of silicon
islands in the buried oxide. This is caused by the incomplete oxidation of the silicon
in the buried oxide region. A second disadvantage is the damage in the silicon film
caused by the implant.
This can mostly be removed by the annealing process.
However, as annealing time and temperature are increased, other problems start to
arise, such as oxide precipitation in the active region.
2.2.3 Unibond™
Unibond™ [2] is wafer bonding technique similar to BESOI but has several
features that make is more desirable. The process sequence for Unibond wafers is
shown in Figure 2-3 and is as follows. Before the bonding process both wafers are
oxidized as in the case of BESOI. However, for Unibond wafers, prior to bonding, the
top active wafer is given a proton implant (typically 200 keV, lx lO l7/cm2).
bonding at room temperature, the wafers are annealed around 600°C.
After
During this
anneal, the top wafer will separate at the buried implant plane due to thermal stress.
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10
Hence the depth of the proton implant determines the final silicon film thickness. A
200 keV, l x l 0 17/cm2 proton implant will yield about a 1 Jim thick silicon film with a
uniformity of about ±50 A.
The final step after the wafer separation is a 1100°C
anneal and a touch polish to increase film thickness uniformity.
Si Wafer (future SOI Layer)
S iO ,- ^
t
1
Zr
\
" If I
J. "t t t t t t " t t'"J_
I
Separation due to thermal stress - p
Buried H* Implant
Si Handle Wafer
Si Handle Wafer
(a) Bonding
(b) Annealing and separation
Figure 2-3. Unibond™ process sequence.
Besides the simplified process over that of BESOI, Unibond has another
advantage. Since the top wafer separates from the handle wafer without breakage, this
wafer can be reused. Typically, this wafer is oxidized and used as the handle wafer for
the next Unibond wafer.
Hence only one wafer is required to make one Unibond
wafer instead of the two required to make a BESOI wafer. This reduces the final cost
of the Unibond wafer.
2.3 Thin Film Silicon-on-Sapphire Technology
Silicon-on-sapphire has been around for many decades and was first proposed
by Manasevit and Simpson in 1964 [3].
The first commercial SOS wafers were
available in 1971 and presently 6 inch wafers are available from various manufacturers
including Union Carbide and Kyocera.
However, because of poor material quality,
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11
SOS never made its way to mainstream silicon processing. SOS’s main application
has been in space because of its radiation hardness [4]. With the development of a
crystal improvement process that consists of an implantation and double solid-phase
epitaxial (SPE) regrowth [5,6], SOS technology and film quality has dramatically
improved. Now lOOnm and thinner films can be achieved with high electron and hole
mobilities [7,8]. The SPE regrowth process sequence is shown in Figure 2-4. The
first step is the chemical vapor deposition (CVD) of the silicon film onto the sapphire
substrate. This film typically has a large number of twins and other defects. Next a
silicon implant (185 keV, 6 x l0 14/cm2) is done to amorphize the silicon film near the
sapphire interface. A solid-phase regrowth is then performed by a two step anneal of
550°C and 900°C. The first anneal is the SPE step and the second is used for further
defect removal.
During these anneals, the top silicon layer acts as a seed for the
amorphous silicon. Since this seed has decreased defect density, the regrown film also
has fewer defects. Finally, the film is thermally oxidized and stripped to obtain the
desired film thickness.
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12
<221 > twins
V
I I
CVD Silicon
/
I I
I
Si Implant
I
v t f I i fi i I I
. V M V__
t \ » »/ ^
/ \
» > / / ,x _
>• {, , ,AmiTOlioNSiy . ;>
(a) Bonding
(b) Amorphization with Si implant
Threading dislocations
Device Quality Silicon
fc) Solid-phase regrowth
(d) Oxidation / Chemical thinning
Figure 2-4. SOS process sequence.
Figure 2-5 shows a typical cross-section of a Peregrine Semiconductor UTSi®
SOS wafer as deposited by C VD (left) and after the improvement process (right). It is
evident in Figure 2-5 that the number of defects in the silicon film can be drastically
reduced by the improvement process.
UTSi wafer
U TSi'silicon
Figure 2-5. Peregrine Semiconductor's UTSi®
Silicon-on-Sapphire before improvement (left) and
after improvement (right).
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13
Silicon-on-sapphire has all the advantages of SOI technologies mentioned
earlier. In addition, as will become clear throughout this thesis, SOS has many other
advantages over other SOI technologies. These include reduced self heating effects
(due to higher thermal conductivity, 0.46 W/cm*K, of sapphire compared to SiOo,
0.014 W/cm-K), reduced device parasitic capacitances, radiation hardness, reduction
o f latch-up in CMOS devices, higher packing density, and improved isolation. SOS
also has lower minority carrier lifetimes (on the order of a nanosecond) that result in
higher source-drain breakdown voltage and reduced parasitic bipolar gain.
Another
SOS characteristic to note is that the silicon film is under compressive stress. This
stress splits the light and heavy hole valence bands leading to increased hole mobilities
over those of bulk silicon. At the same time, this stress also causes lower electron
mobilities as compared to bulk [9]. This is similar to the effects seen in SiGe on Si
[ 10].
Sapphire, and more generally poly-crystalline sapphire (alumina), has been
know for many decades to have excellent dielectric properties. The dielectric constant,
dielectric loss tangent and resistivity of sapphire are Er = 9.39, tan 8 < 0.0001 at 3
GHz, p = 1014 n-cm.
Hence, in addition to the desirable traits of other SOI
technologies, the sapphire substrate also make a very excellent microwave substrate
for passive elements such as transmission lines and inductors.
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14
2.4 Summary
There are a variety of SOI technologies, the majority of which are based on
using silicon dioxide as the insulating layer between the active silicon film and the
handling substrate (typically silicon). Silicon-on-sapphire is the only SOI technology
that offers a true insulating substrate. Moreover, sapphire is a very good insulator with
very desirable properties for microwave circuit applications.
As will be seen in this dissertation, the thin SiOi layer used in silicon-on-oxide
technologies can cause problems such as device self heating and poor microwave
performance due to capacitive coupling to the conducting silicon substrate. Siliconon-sapphire addresses these points due to its sapphire’s higher thermal conductivity
than SiOi and its insulating substrate with excellent dielectric properties.
2.5 References
1. M. Watanabe and A. Tooi, "Formation of SiOi Films by Oxygen-Ion
Bombardment," Japanese Journal o f Applied Physics , vol. 5, p. 737, 1966.
2. M. Bruel, U.S. Patent 5,374,564 (1994).
3. H.M. Manasevit and W .I. Simpson, "Title," Journal o f A pplied Physics, vol. 35. p.
1349, 1964.
4. J.G. Rollins, J. Choma, and W .A. Kolasinski, “Single-Event Upset in SOS
Integrated Circuits,” IEEE Trans, on Nuclear Science, vol. NS-34, no. 6, Dec.
1987.
5. S.S. Lau, S. Matteson, J.W. Mayer, P. Revesz, J. Gyulai, J. Roth, T.W . Sigmon,
and T. Cass, “Improvement of Crystalline Quality of Epitaxial Si Layers by IonImplantation Techniques,” Applied Physics Letters , vol. 34, 1979.
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15
6. T. Yoshii. S. Taguchi, T. Inoue, and H. Tengo. “Improvement o f SOS Device
Performance by Solid-Phase Epitaxy," Japanese Journal o f Applied Physics, 1982.
vol. 21, pp. 175-176.
7. G.A. Garcia, R.E. Reedy, and M.L. Burgener, “High-Quality CMOS in Thin (100
nm) Silicon on Sapphire,” IEEE Electron Device Letters, vol. 9, no. 1, pp. 32-34.
Jan. 1988.
8. G.A. Garcia and R.E. Reedy, “Electron Mobility within 100 nm of the Si/Sapphire
Interface in Double-Solid-Phase Epitaxially Regrown SOS.” Electron Device
Letters, vol. 22, no. 10, p. 537. 1986.
9. M . Roser. S.P. Clayton, P.R. de la Houssaye, G.A. Garcia, "High-Mobility FullyDepleted Thin-Film SOS MOSFET's." 7992 Device Research Conference
Proceedings, June 1992.
10. P.M. Garone, V. Venkataraman. J.C. Sturm, "Hole Mobility Enhancement in
MOS-Gated GexSi|.x/Si Heterostructure Inversion Layers." IEEE Electron Device
Letters, vol. 13, no. I, Jan. 1992.
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3. Microwave Field Effect Transistor
3.1 Introduction
As demand for improved circuit performance at increasingly higher frequencies
continues, the need for a faster and improved transistor grows in importance.
.As
circuit frequencies reach the L and S bands, conventional digital transistors are no
longer suitable. Hence the need for a MOSFET targeted toward high performance at
microwave frequencies arises.
This chapter discusses the differences between a M OSFET targeted toward
digital circuit applications and a MOSFET for microwave circuit applications. First a
general background of MOSFET device operation will be discussed.
Next the
differences between bulk MOSFETs and SOI MOSFETs will be examined, followed
by a discussion of SOS MOSFETs targeted toward digital applications. Finally, the
design, fabrication and electrical characteristics of an SOS “T-gate" MOSFET targeted
for microwave applications will be discussed.
3.2 Metal-Oxide-Semiconductor Field Effect Transistor
The metal-oxide field effect transistor (MOSFET) has been one of the main
driving forces of the semi-conductor world for the last several decades. Silicon based
MOSFETs are in almost every piece of electronics we buy today and will remain so
well into the next century. Therefore, it is necessary' to understand this transistor in
16
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17
great detail. This chapter discusses the basics of the M OSFET starting with the field
effect and continuing on with its DC and AC characteristics.
The term “field effect" refers to the phenomenon where by the conductivity of
a semiconductor is modulated by an electric field applied normal its surface. This
phenomenon was first discovered and patented by Lilienfeld [ 1] in the United States
and by Heil [2] in Germany in the early 1930's. A schematic diagram of the proposed
MOSFET is shown in Figure 3-1.
Insulator
Semiconductor
Ohmic Contacts
Figure 3-1. MOSFET proposed by Lilienfeld [1] and Heil [2].
This type of MOSFET is known as a surface field-effect transistor due to the
fact the application of an electric field brings majority carries to the surface of the
semiconductor-insulator interface. While the idea existed, the material quality' needed
to implement it did not. Early MOSFETs suffered from high interfacial state density'
at the semiconductor-insulator interface. This problem was realized by Bardeen in
1947 [3] and because of it MOSFET research slowed. However, in the late 1940's
MOSFET research increased and w'as reinvestigated by Shockley and Pearson [4].
Then in 1960. Kahng and Atalla made a great breakthrough by proposing and
fabricating the first M OSFET using a thermally grown oxide [5].
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IS
With the exception of improv ed manufacturing techniques and shrinking of the
device geometries not much has changed from the MOSFET of these earlv davs.
Therefore it is important to understand the operation of the M OSFET in term of its DC
and high frequency i A O performance.
3.2.1 Operation
A cross section of a modem n-channel MOSFET (NMOS i is shown in Figure
3-2. This device has three terminals referred to as the "gate”, "source", and "drain."
The basic operation of the FET can be thought of as a switch. A voltage applied to the
gate turns on the switch and connects the source and drain terminals. The MOSFET is
essentially a voltage controlled resistor with gain.
p-Type Silicon
Figure 3-2. Cross section of a modern dav n-channel
MOSFET.
To help understand the operation of the MOSFET. band diagrams under the
gate for the n-channel MOSFET are shown in Figure 3-3. When a negative voltage is
applied to the gate, holes from the bulk are attracted to the Si-SiO; interface and the
semiconductor is in “accumulation*' (Figure 3-3a). When this condition occurs, back to
back p-n diodes exist from source to drain and no current flows. If a small positive
voltage is applied, electrons are attracted to the interface and the semiconductor is
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19
“depleted” (Figure 3-3b).
In this condition some current may flow between the n '
source and drain contacts. Finally, when a large positive voltage is applied to the gate,
many electron are attracted to the interface and the semiconductor is “inverted” (Figure
3-3c). That is, the electron and hole concentrations are such that the semiconductor
has changed type from p-type to n-type.
When this occurs, a low resistance path
between source and drain occurs and large currents can flow.
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20
If
V<0
E,
(a)
Er
E„
v>o
E,
Er
E„
(b )
(C)
v>o
Ef
E„
Figure 3-3. Band diagram of the channel region of
an NMOS transistor in (a) accumulation, (b)
depletion, and (c) inversion.
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21
3.2.2 DC Characteristics
There have been many papers and books written describing the DC operation
of MOSFETs. The reader is referred to the following for a more in depth description
[6,7]. A summary of the DC operation follows.
As mentioned in the previous section, with the application of a positive voltage
to a p-type material, the semiconductor can be made to invert at the oxide
semiconductor interface. This voltage is know as the threshold voltage (Vy). For gate
voltages below Vy, the devices is off and no current passes between source and drain.
With applied voltage above V T, the device is on and current flows between source and
drain.
In the “on” state, there are two regions of operation, linear and saturation. In
the linear regime, if a small voltage is applied to the drain, a small current will flow
from the source to the drain through the conducting “channel.” This “channel” acts as
a resistor and drain current, I d, is proportional to drain voltage, Vp. However, if the
drain voltage is increased beyond a certain value, V DSa t \ the current will no longer
increase. This occurs when the channel is “pinched” at the drain side of the channel.
At this point the drain current will remain constant ("saturated") for increased values
of V D. The I-V characteristics of an ideal MOSFET are shown in Figure 3-4 and the
expressions for the current flow are given in (3.1).
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22
15
Linear Region
-LVolt*:..
2>Votte
SliY dtts
0
0
2
4
6
8
10
Vds (Volts)
Figure 3-4. I-V characteristics of an ideal MOSFET.
2
V DS
f o r V DS -
v cs
-
VT
(linear)
(3.1)
for VDS > VCS-VT (saturation)
Where W and L are the gate width and length respectively, Cox is the gate
oxide capacitance, p. is the electron mobility and V Gs, and V DS are the applied gate and
drain voltages. These equations are derived from the “gradual channel” approximation
and are a good approximation for long channel devices. However, when device gate
lengths are scaled to sub-micron values, these equations must be modified to include
many other effects.
3.2.3 AC Characteristics
There are two main figures of merit for the AC operation of the MOSFET.
These are the unity current gain frequency (f ) and the unity power gain frequency
(fmax)i also know as the maximum frequency of oscillation. These can be derived from
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23
the small signal model shown in Figure 3-5. Where Rg, Rs and Rd are the gate source
resistances respectively, Cgs, Cgd and Cds are the gate-source, gate-drain and drainsource capacitances respectively and Ro, Rj and gm are the output resistance, channel
resistance and transconductance respectively.
Intrinsic FET
Rs
o— ' V V
hrHi-TTT
ft
Off
?i S
ds
| R„
Figure 3-5. Small signal model of the MOSFET.
By small signal circuit analysis, it can be shown that:
§m
/,= 2nC.
/
J
max
=
/,
(3.1)
+ 2n f, RgCKti
Hence, in order to increase / t, the transconductance should be made as large are
possible while the gate-source capacitance should be minimized. At the same time, in
order to increase /max, the gate resistance and feedback capacitance Cgd should be
reduced.
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24
3.2.4 Noise Characteristics
The equivalent circuit for noise analysis of microwave FETs was derived by
Pucel, Haus and Statz [8] and first applied to GaAs FETs. This equivalent circuit is
shown in Figure 3-6. The noise sources ing, in<t, eng, ens represent the induced gate
noise, drain circuit noise, thermal noise of the gate resistance and source series
resistance respectively.
The es and Z* are the signal source voltage and source
impedance.
Intrinsic FET
Figure 3-6. Equivalent circuit for noise analysis.
Fukui [9] has shown that the optimal noise figure obtained from this equivalent
circuit is:
(3.2)
where Lg is the gate length, / is the frequency and K is a material dependent fitting
factor. Clearly we see that for low noise figure (desireable for microwave circuits), the
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25
gate length should be reduced and the parasitic source and gate resistances should be
reduced.
3.3 Silicon-on-Insulator MOSFET
The main differences between a MOSFET fabricated in SOS technology and
that o f a MOSFET fabricated in bulk silicon technology can be seen in the cross
section of the devices shown in Figure 3-7. Here we see that the SOS MOSFET lies
directly on top of the insulating sapphire substrate. This make isolation between the
devices very easy, compared to a more complicated isolation process such as LOCOS
or trenches. This simple isolation also allows the devices to be packed tighter together
than bulk devices allowing for potentially higher levels of integration.
Polysilicon Gate
LOCOS Isolation
p Substrate
n Well
(a) Bulk Silicon CMOS
B9B|
________I P* I P I n *~ l
SBH
In *
| n | p* |
Sapphire Substrate
(b) SOS CMOS
Figure 3-7. Cross section of a MOSFETs fabricated
in (a) bulk silicon and (b) silicon-on-sapphire.
In addition to isolation issues, the SOS MOSFET has several other key
advantages. The thin film of the SOS MOSFET allows the devices to be scaled to
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26
smaller dimensions much more readily than for bulk MOSFETs. In the bulk case, as
gate lengths shrink, junction depths must also decrease. However, this requires stricter
control of the implant and doping profiles. This is not as big a problem in SOS since
the junction depths are controlled by the thickness of the silicon film.
Parasitic capacitances and parasitic bipolar effects are decreased in SOS
devices. This can be see in Figure 3-8 where parasitic elements of a bulk CMOS are
shown. Several parasitic npn and pnp bipolar transistor exist in the structure. These
can leads to lower breakdown voltages and a phenomenon know as latch-up in which
the pnp and npn parasitic transistors form a thyristor for high current conduction. This
high current can cause damage in circuits. Parasitic capacitors in the CMOS structure
lead to a decrease in maximum frequency of operation achievable by the FETs.
Polysilicon Gate
p Substrate
(a) Bulk Silicon CMOS
Figure 3-8. Parasitics in a bulk CMOS process.
3.3.1 Fully vs. Partially Depleted
When considering the silicon film thickness used for any SOI technology, there
are basically two types: fully depleted and partially depleted. These depletion regions
are in reference to the state of the silicon film under the channel during the on state of
the transistor. When the gate is biased in the accumulation regime, a depletion region
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27
forms under the channel. In a “fully depleted” transistor, this depletion region extends
all the way to the silicon-insulator interface. In a “partially depleted” transistor, the
depletion region ends before reaching the silicon-insulator interface. The extent of the
depletion region is predominately governed by silicon film thickness and doping.
The main differences in the operation of fully and partially depleted MOSFETs
are observed in the DC characteristics.
A partially depleted M OSFET will have a
“kink” in the I-V characteristics. This is shown in Figure 3-9. The kink is a result of
the floating body effect created by impact ionization. At high V DS electron-hole pairs
are created by impact ionization. For an NMOS transistor, the electrons are quickly
swept into the drain. In a fully depleted MOSFET, the remaining hole would be swept
into the source. However, in the partially depleted case, the holes accumulate at the
back of the channel outside the depletion region. This raises the body potential and
changes the threshold voltage (akin to changing the body potential in a bulk silicon
NMOS).
For the NMOS, the threshold voltage is made less positive so that at the
same applied V gs, the drain current I d will be larger. This results in the kink observed
in the I-V characteristics.
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28
is
K in k '
10
= 4 V olts
= 3 V olts
5
= 2 V olts
= I V olts
0
0
2
4
6
8
10
VDS (Volts)
Figure 3-9. I-V Characteristics of a partially
depleted SOI MOSFET.
3.4 SOS MOSFET for Digital Applications
The relatively well developed MOSFET targeted toward digital applications
will form the foundation of a MOSFET targeted toward microwave applications. This
section discusses the processing, DC characteristics, and AC characteristics of both nand p-channel MOSFETs on SOS that are used in large scale integrated circuits.
Examples of digital circuits fabricated with these FETs will also be briefly discussed.
3.4.1 Processing
The processing sequence of the digital MOSFET-on-Sapphire is shown in
Figure 3-10. The first step in the process is the formation of silicon “islands” to define
the active area of the devices.
As mentioned earlier, island (or mesa) isolation is
preferred over LOCOS isolation due to process simplicity and increased packing
density.
The island etch is done by reactive ion etching with a combination of
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29
hydrogen bromide (HBr) and chlorine (CI2 ) with flow rates of 45 seem and 20 seem
respectively. At an RF power of 225 W , this combination has an etch rate of about
3800 A/min. This is the first masked step in the sequence. After the island etch, the
islands of the PMOS transistors are covered with photoresist and the NMOS devices
are implanted to adjust the threshold voltage to the desired level. This is the second
mask step of the sequence. These steps are shown in Figure 3 -10a. No implant is
needed to adjust the threshold voltage for the PMOS
After the island definition and implant, the gate oxide is grown and the gate
polysilicon is deposited (Figure 3 -10b).
The gate polysilicon thickness is typically
3800 A and is n-type doped for both n and p channel MOSFETs. The gate is then
defined by optical lithography, followed by a reactive ion etch using the third mask in
the sequence. The chemistry and power is used for the gate etch is identical to that
used for the island definition. After the gate etch, the source and drain implants are
done in a self aligned fashion using the gate polysilicon as the implant stop for the
channel region. This is shown in Figure 3 -10c. The implants require two additional
mask layers (forth and fifth) to define the NMOS and PMOS source and drains.
Next, a self aligned silicide (salicide) process is performed using titanium.
This process is depicted in Figure 3-10d through Figure 3-10g. This process requires
no photolithography steps. The first step is the formation of silicon dioxide sidewalls.
This is done by depositing 2000
A of Si02
conformally over the entire wafer (Figure
3-10d). Next a RIE etch is performed to etch 2000 A of SiOi. Since an RIE etch only
attacks the horizontal surfaces and does not attack the vertical surfaces, oxide
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30
sidewalls on the sides of the gate polysilicon remain after the etch (Figure 3-10e). 500
A of titanium is then deposited onto the entire surface of the wafer (Figure 3-100-
The
titanium is reacted, by rapid thermal annealing at 675°C for 60 seconds, with the
underlying silicon to form titanium monosilicide (TiSi). The titanium on the oxide
sidewalls will not react with the oxide and can be removed by a wet etch that
selectively removes titanium but does not etch titanium monosilicide [1011]. Finally,
the wafer is again rapid thermal annealed at 850°C for 60 seconds to change the phase
of the silicide from monosilicide to disilicide, TiSii (Figure 3-10g). This phase has
lower resistivity than TiSi [10] which is desirable to reduce gate, source and drain
resistance.
The final steps are collectively referred to as “backend’* steps.
salicide, a 3000
A SiOi
After the
layer is deposited over the entire wafer. This is the “contact"
oxide (Figure 3-1 Oh). By using the sixth mask step, contact openings are made in the
oxide to allows the first level metal to contact the source, gate and drain regions
(Figure 3-10i).
The first level metal (800
A
TiW. 4000
A
A ll% S i, 200
A
Ti) is
deposited and etched (mask level seven) to define the gate, source and drain contacts
(Figure 3-10j).
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(a) Island Etch. Channel Implant
(f) Titanium Deposition
Silicide.
p
s t lNnl">
sSN vX W \ \.
(b) Gate Oxide and Polvsilicon
(g) Silicide Formation
(c) Gate Definition. S/D Implant
(h) Contact Oxide Deposition
(d) Oxide Deposition
(i) Contact Etch
(e) Oxide Sidewall Formation
(j) First Level Metal
Figure 3-10. Process sequence for a digital MOSFET in SOS.
The processing sequence shown in Figure 3-10 does not show the mask steps
necessary for a two level metal process, two additional masks (via and metal two) are
needed. Also, to protect the wafer from moisture and scratches, a protection layer of
phosphosilicate glass (PSG) (9000 A) and LTO oxide (3000 A) are deposited on top of
the wafer. In order to make contact to the circuits, openings in this layer must be made
with one additional lithography step and wet etch. All in all. the full CMOS process,
with double level metal, requires 10 lithography steps.
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3.4.2 DC Characteristics
3.4.2.1 N-Channel MOSFET
The DC characteristics of the dexices were measured using an HP 4145. The
I ds '"s. V ds ( T V ) curves for 50 am and 100 tun wide devices are shown in Figure 5-11.
Both devices had a drawn gate length of 0.5 urn. These devices are well behaved with
a threshold voltage around 0.7 volts, a breakdown voltage greater than 5.5 volts, and a
high output resistance greater than 600 Ohms. Comparing the 50 pm and 100 urn
width FETs. we see that the current scales very well with width as predicted bv the DC
current equations.
V c j = 0 t o 2.0 V . S te p <L5 V
c s = 0 to 2 .0 V . S te p 0 .5 V
15
15
10
10
c
c
0
D
0
'
b
iV o h s i
05
I
V 'ns ( V o h s i
Figure 3-11. I-V characteristics of a 0 5 pm x 50 um
(left) and 0 5 pm x 100 pm (right) n-MOSFET.
The transconductance fgm) of the devices is around 120 mS/mm.
While
slightly low'er than the transconductance achievable by a bulk silicon MOSFET. the
transconductance is high enough for most circuit applications it>oth digital and
microwavet. This difference in transconductance is due to the slightly lower electron
mobilities observed in SOS. typically around SO^c the value of bulk silicon [12]. The
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
channel mobility of electrons in SOS is 500 cm'/V-s [13] as compared to mobility
values around 650 cm '/V s observed in bulk MOSFETs.
The degradation of the
electron mobilities is due to many factors: surface scattering, crystal defects and
compressive strain in the silicon film resulting from the difference in the thermal
expansion coefficients of the silicon and sapphire [14. 15].
To check the leakage characteristics, the sub-threshold characteristics of the
devices were measured.
The sub-threshold characteristics of a 0.5 um x 100 um
NMOS biased at a V DS value of 2 volts is shown in Figure 3-12. The sub-threshold
slope of the device is very near ideal around SO mV/dec. The "shoulder" in the curve
is due to the "edge” effect observed in mesa isolated FETs. Due to dopant segregation
and incorporation into the oxide during the gate oxide growth, the edges of the island
have a lower doping than the intrinsic part of the device.
This leads to a lower
threshold voltage, around 0 volts in this case for the "edge” FET.
Hence, the edge
FET turns on first as V ^ is increased resulting in a higher drain-source current. Next
the intrinsic FET turns on resulting in another increase if drain-source current. At V gs
= -1 volt, the channel is completely turned off and the leakage current is 30 nA.
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34
t
10
- Vds = 2.0 V
10
■j
to
10
■5
< 10
g 10
10
10
•7
-»
10
10
-1
- 0 .5
0
0 .5
1
1 3
2
V Gs (Volts)
Figure 3-12. Sub-threshold characteristics of a 0-5
pm x 100 p n NMOS.
The
“edge”
transistor
can
photolithography step and implant.
be
eliminated
by
the
addition
of
one
The edge of the island (typically 1 pm wide)
directly under the polysilicon gate can be implanted prior to gate definition.
This
implant raises the threshold voltage of the “edge” transistor such that the intrinsic
transistor turns on before the edge transistor and the shoulder is removed (Figure 313).
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35
I
10
10
10
*
•2
VDS = 2.0 V
-3
10
10
■5
s
10
10
•7
-1
-0 .5
0
0 .5
1
1.5
2
VGS (Volts)
Figure 3-13. Sub-threshold characteristics of a 0.5
Jim x 100 [im NMOS with edge implant.
3.4.2.2 P-Channel MOSFET
The I-V characteristics of 0.5 p.m gate length p-channel MOSFET with 50 fim
and 100 pm gate widths are shown in Figure 3-14. As in the case of the n-channel
MOSFETs, the p-channel MOSFETs exhibit good characteristics with high breakdown
voltage, high output resistance and good gate width dependence.
voltage of the p-channel FETs is around -0.9 volts.
The threshold
The transconductance of the
devices is 80 mS/mm. Again this number is slightly lower than expected for a bulk
silicon technology and is due to lower hole mobilities, but is still usable for our
applications. The channel mobility of holes in SOS is 200 cm2/V-s as compared to
mobility values around 80 cnr/V-s observed in bulk MOSFETs [13]. The increase in
hole mobility is also attributed to compressive stress in the film. However, as opposed
to electron mobilities which decrease with stress, hole mobilities are increased [14].
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36
15
15
V cs = 0 to -2.5 V , Step -0 3 V
V cs = 0 to - 2 3 V , Step -0 3 V
12
12
9
9
6
6
3
3
0
-3.5
-3
-23
-2
-IJ
-I
-0 J
V DS (Volts)
0
0
-33
-3
-2 J
-2
-1.5
-I
-03
0
V ds (Volts)
Figure 3-14. I-V characteristics of a 0.5 jim x 50 |im
(left) and 0.5 pm x 100 (im (right) p-MOSFET.
The leakage current of the p-channel MOSFETs was monitored by the sub­
threshold characteristic.
Compared to the sub-threshold characteristics of the n-
channel FET, it is obvious that the p-channel FET does not have an “edge” FET
characteristics. While the effect is still present in the PMOS device, the effect is such
that the threshold voltage is made more negative so that the “edge” FET turns on after
the intrinsic FET. Since the intrinsic FET conducts much more current that the “edge”
FET, the I-V characteristics of the “edge” FET (i.e. the shoulder) cannot be observed.
The sub-threshold slope of the PMOS device is very near ideal at 65 mV/dec. The
leakage current is on the order of 0.1 nA.
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37
VDs = -2.0 V
•10
■2
1
0
X
VGS (Volts)
Figure 3-15. Sub-threshold characteristics of a 0.5
Jim x 100 um PMOS.
3.4.2.3 Uniformity
A key to making circuits with good yield is device uniformity across the wafer.
To study this, the same MOSFET, a 0.5 |im x 100 |j.m NMOS, was measured in ten
fields across the wafer. The I-V characteristics of these devices are shown in Figure 316. This shows how the threshold voltage, as well as the series resistances, output
resistance, breakdown voltage, and transconductance can vary across the wafer. For
example, at a bias of V ds = 2.5 volts and V GS = 1.5 volts, the mean and standard
deviation of the drain current, I d, are 13.5 mA and 1.0 raA respectively.
The
variations apparent in Figure 3-16 can be due to many reasons. Silicon film thickness
is typically the main culprit in these variations. Film variations can cause differences
in series resistances and result in differences in doping levels which affect the
threshold voltage. Non-uniform processing, such as a non-uniform plasma in an RIE
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38
system, can also cause these variations. Generally speaking the results are good but
should be improved upon.
30
25
/•“ V
20
<
S
15
■Si
a
10
5
0
0
0 .5
1
1.5
2
2 .5
3
3.5
VDS (Volts)
Figure 3-16. I-V characteristics of ten 0.5 pm x 100
pm NMOS across the wafer.
3.4.3 AC Characteristics
The AC characteristics of the MOSFETs were measured using and HP 8510B
Network Analyzer.
The S-parameters were then converted to h-parameters and z-
parameters to plot the current gain and power gain as a function of frequency. From
these plots, the f and/max can be extrapolated. The small signal current gain (hii), the
maximum available gain / maximum stable gain (M A G /M SG ) are shown in Figure 317 and Figure 3-18 for 0.5 pm x 100 pm n-channel and p-channel digital MOSFETs
respectively.
The n-channel MOSFET has an f and /max of 22 GHz and 12 GHz
respectively while the p-channel MOSFET has an / t and /max of 18 GHz and 7 GHz
respectively.
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39
35
30
lh2,l
f t = 22 GHz
7™* - 12 GHz
25
20
15
10
5
0
Frequency (GHz)
Figure 3-17. Microwave performance of a 0.5 pm x
100 pm digital n-channel MOSFET.
35
30
25
20
15
M A G /M S G
10
5
0
Frequency (GHz)
Figure 3-18. Microwave performance of a 0.5 pm x
100 pm digital p-channel MOSFET.
The values of f
are typical for MOSFETs with this channel length.
Furthermore, as expected from (3.1), the /max was low due to the high gate resistance of
the silicided gate polysilicon (whose sheet resistance is typically 2-3 Q/L).
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40
3.4.4 Circuit Performance
Using the above MOSFETs, many high speed digital circuits have been
fabricated. As mentioned in Chapter 1, a 41 stage ring oscillators with 0.5 |im gate
lengths have shown power delay products as low as 6 fJ. V LS I circuits with 50,000
transistors have been fabricated. A 16 x 16 bit parallel multiplier with 0.75 pm gate
lengths and a IK SRAM with 1.25 pm gate lengths have been reported by Offord [16].
The multiplier had a loaded gate delay of 243 pS at 5.0 volts supply voltage. The
SRAM exhibited an access time of 20 nS. Sadana [17] has demonstrated 0.25 p.m
SOS devices with DC characteristics superior to devices fabricated on other SOI
technologies (S IM O X and BESOI).
The above examples illustrate the capability of silicon-on-sapphire for digital
applications. Once the necessary blocks are put in place to realize SOS operating at
microwave frequencies, the integration of digital and microwave circuits described in
Chapter 1 should quickly follow.
3.5 SOS MOSFET for Microwave Applications
3.5.1 Microwave versus Digital
As stated previously, for a microwave transistor, there arises a need to reduce
the gate resistance. For a silicided gate process with sheet resistance of 2-3 Q/L, the
gate resistance of a 0.5 pm x 50 pm transistor will typically be around 200-300 Q.
This is much too high for microwave circuit applications.
However, if the gate
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41
polysilicon is overlaid with first level metal (-3 0 m fl/L ), the gate resistance can be cut
to a few ohms.
3.5.2 Device Processing
To lower the gate resistance of standard digital CMOS transistors, a process to
overlay the gate polysilicon with first level metal was developed.
The process
sequence is shown in Figure 3-19 and is commonly referred to as a “T-Gate” or “metal
reinforced gate.” The process is as follows. First the silicon island is defined by a
reactive ion etch (RIE) silicon etch Figure 3 -19a. Next the gate oxide is thermally
grown and the gate polysilicon is deposited (Figure 3 -19b). The gate is then optically
defined by a photolithography step and RIE (Figure 3 -19c).
The next four steps involve the formation of self-aligned silicide (salicide).
The first step (Figure 3-19d) is to deposit 2000-3000 A of oxide. This oxide deposits
conformally and on the top and sides of the polysilicon gate. Next an RIE is used to
create oxide sidewalls.
Up to this point, the process sequence is the same as that of the digital
MOSFET. At this point, in a standard CMOS process, a contact oxide (3000 A LTO)
would then be deposited and contact openings to the source and drain etched.
However, in order to form a T-gate, this part of the process was modified. The first
step is to deposit a planarization oxide (SiOi) which, as in the sidewall case, is
conformal to the polysilicon gate (Figure 3-19h). Next a planarization resist (OLIN
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42
Microelectronic Materials AP1II) is spun at 2000 RPM onto the wafer (Figure 3 -I9i
and Figure 3-20).
The planarization resist is basically standard photoresist without a light
sensitive component. This resist has two important properties. First, the viscosity (4.7
CST) of the resist is such that it covers large features but flows over smaller feature
(such as transistor gates) to planarize the entire wafer surface. Second, its RIE etch
rate is roughly the same as that of oxide. This is a critical property important for the
next step.
After the planarization resist has been cured, the wafer is put in the RIE for
etching. As stated before, the oxide and resist etch at approximately the same rate, so
it is possible to etch the wafer until the tops of the gate are exposed (Figure 3-19j). An
SEM of a transistor after planarization is shown in Figure 3-21.
After the planarization, the wafer is masked to open the contacts to the source
and drain regions by RIE (Figure 3 -19k). Finally, first level metal is deposited and
patterned to define the source and drain metalization and to form the metal strap of the
gate polysilicon (Figure 3-191). If desired, a backend process can be done to form vias
and second level metal.
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(f) Titanium Deposition
(I) First Level Metal
Figure 3-19. Process sequence for a "T-Gate” transistor.
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P lan arizatio n Resist
Gate
Oxide
\
1 9K U
2 Q
4 KK
4 ? 0 r,
7$4 3
Figure 3-20. SEM cross section of a FET after
spinning on planarization resist.
Figure 3-21. SEM cross section of a FET after the
planarization etch.
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45
An SEM cross section of a fabricated “T-Gate” MOSFET is shown in Figure 322.
This device has a drawn gate length of 0.5 urns. The metal T-gate is clearly
visible and has about a 0.1 pm overlap of the gate polysilicon.
Photoresist
T-Gate
Metal
Gate
Polvsilicon
Oxide
Figure 3-22. SEM cross section of the metal "Tgate" (with resist).
3.5.2.1 Processing Difficulties
Although the processing steps discussed in the previous section seem simple
enough, there are a few problems that can occur in the process. The first is associated
with the planarization process and the second is associated with the misalignment of
the metal strap to the gate polysilicon.
So far we have only concerned ourselves with the planarization o f objects with
small cross section such as the 0.5 pm gate length. However, the planarization resist
tends to not planarize large structures very well as depicted in Figure 3-23. Here the
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46
0.5 pm gate length is well planarized, but the large feature next to it (possibly a gate
contact pad) is not planarized well. This size dependence can become a problem if the
gate width is very large. In this case, the gate polysilicon will not be well planarized
and the metal strap will only contact the gate polysilicon at the ends of the fingers. A
process control structure to monitor this aspect of the planarization will be discussed
in the next section.
Planarization Resist
Figure 3-23. Size effect on planarization (a) small
feature, (b) large feature.
Another problem with the planarization process is the loading effect. This is
similar to the effect described above but in this case, improper planarization occurs
over small features spaced close together. This effect is depicted in Figure 3-24.
Planarization Resist,
Figure 3-24. Loading effect on planarization.
Since the MOSFETs have 0.5 pm gate lengths (and sometimes smaller) the
alignment of the metal strap to the gate can be very difficult. For our devices, the gate
metal was designed to overlap the gate polvsilicon by 0.1 Jims. Hence a 0.5 urn gate
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length device would have a 0.7 pm metal width.
These tight tolerances can be
achieved if exceptional care is take during the photolithography and metal etch steps.
However, is misalignment should occur, the results can be disastrous.
Figure 3-25
show whai can happen when the gate metal is misaligned to die gate polysilicon by 0.2
pms.
(a ) M isaligned Photolithography
(b i Trenching o f gate durins RJE
metal etch
Figure 3-25. Result of misalignment of gate metal photoresist
If the photolithography is misaligned then the subsequent RIE to etch the metal
can destroy the device. Ideally, once the metal is completely etched away, the etch is
stopped. However, to ensure complete metal etch over the entire wafer, an over etch is
typically used- This would still not present a problem is the device is properly aligned
since the selectivity of the etch rate of the metal to SiO; is high.
However, in our
process, the etch selectivity of the metal etch to silicide and polysilicon is low. If any
silicide and polvsilicon are exposed due to misalignment, the etch can quickly etch
through the gate to the channel region resulting in shorts of the gate to the channel or
open circuiting the device by separating the channel from the source or drain contact
(Figure 3-25b). A cross sectional SEM of this is shown in Figure 3-26.
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4S
Figure 3-26. SEM cross section of a FET destroyed
during metal etch.
3>5.2.2 Process M onitor Structure
While the trenching problem can be solved with careful lithography and pre­
etch inspection of the photoresist, the problem with the planarization resist is tougher
to control. Therefore, it is necessary to monitor the planarization process carefully.
To do this, a test process monitor structure was developed.
As mentioned earlier, the planarization resist does not planarize well near large
objects such as a gate contact pads. This is schematically depicted in Figure 3-27.
Here the planarization oxide is thicker near the gate contact pad so that the metal does
not contact the gate polvsilicon until it is some distance, d. from the pad.
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49
Gate Contact Pad
Island
Top View
Side View
Figure 3-27. Im proper T-gate planarization near a
gate contact pad.
To get a rough estimate of this distance, and determine the quality of the
planarization the test structure shown in Figure 3-28 was developed. Here an extra
metal contact pad is added to the right and the metal contact between the gate contact
pad metal and the metal gate fingers is cut. By probing the gate contact pad and the
added metal 1 pad, a resistance can be measured that is dependent on the distance, d.
of the bowing of the metal near the gate contact pad.
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50
Gate Contact Pad
Island
Metal I
Top View
-*-d-*s
Side View
Figure 3-28. Test structure for T-gate planarization
verification.
The measured resistance is:
R
=
R co nl
+
R pad
+ R p aly + R c c n l + R mc,al
(3‘3)
where Rc0ni is the contact resistance between the metal and the gate contact pad, Rpad
is the resistance of the gate contact pad polysilicon, Rpoiy is the resistance of the gate
fingers, Rc0 n 2 is the contact resistance of the gate fingers to the metal strap, and Rmetaii
is the resistance of the metal strap. Since the gate contact pad is so large compared to
the gate fingers, Rc0ni and Rpad can be ignored. Also, if we assume that the current
either flows in the gate polysilicon or metal strap, the resistance can be written as:
R
= P poly •d • L g +
R con2
+ P m tta H
' W
g ~ d )
•L
g
(3.4)
where Ppoiy and Pmetaii are the sheet resistance of the gate polysilicon and first level
metal respectively and Lg and W g are the gate length and width. Clearly if d is equal to
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51
the width of the device (i.e. no planarization), the resistance will be infinite with no
current conduction path between the gate contact pad and metal 1 pad.
By measuring test structures of different gate length and widths, the distance of
the bowing, d, can be determined from (3.4). This distance can be correlated to gate
resistance as determined by AC measurements and
characteristics in Section 3.5.4.
In general, the larger the distance, the higher the effective gate resistance and the lower
the/ina*.
3.5.3 DC Characteristics
Since no changes, other than the metal T-gate have been introduced to the
MOSFET, the DC characteristics of the device remain the same. This is apparent from
the equations defining the DC operation of the MOSFET (3.1) in which we see that
there is no dependence on gate resistance. Therefore the DC characteristics of the Tgate MOSFET are expected to be the same as those observed in Section 3.4.2. This is
borne out by experimental measurements.
3.5.4 AC Characteristics
AC characteristics of the MOSFETs were measured on an HP8510B Network
Analyzer from 1 to 40 GHz.
The small signal current gain (hsi), the maximum
available gain (M A G ) and maximum stable gain (MSG), along with the unilateral gain
(U) for the 0.5 pm n- and p-channel MOSFETs are shown in Figure 3-29 and Figure 330 respectively. These show a current gain cutoff frequency and power gain cutoff
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52
frequency of 25 and 66 GHz respectively for the NMOS and 14 and 41 GHz for the
PMOS.
35
Uni late ral G iio
30
lh i,l
25
20
15
. MAG/PISG
10
5
0
1
10
100
Frequency (GHz)
Figure 3-29. Microwave performance of a 0.5 (im x
100 |im T-G ate n-channel M OSFET.
35
30
n ilatfral Gain
25
20
15
10
5
0
Frequency (GHz)
Figure 3-30. Microwave performance of a 0.5 (im x
100 fim T-G ate p-channel M OSFET.
Table 3.1 summarizes the AC performance of the T-gate transistors as well as
the AC performance of the digital transistors.
Clearly, the addition of the T-gate
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53
reduces gate resistance and dramatically increases /m ,.
The new transistors have
useful gain well into the microwave frequency regime.
Table 3.1. / t and fm
a
xfor NMOS and PMOS transistors on SOS.
Digital NMOS
T-Gate NMOS
T-Gate NMOS
Digital PMOS
T-Gate PMOS
T-Gate PMOS
m m i n
0.5
0.5
0.7
0.5
0.5
0.7
22
25
17
18
14
9
iiS B B lS fll
12
66
54
7
41
31
3.5.5 Noise Characteristics
n- and p-channel MOSFETs were characterized from 2 to 16 GHz at TRW
using an A TN automated noise figure measurement system (whose calibration is
traceable to NIST). Figure 3-31 and Figure 3-32 show the minimum noise figure and
associated gain of 0.5 pm n- and p-channel MOSFETs. Both devices had a sub-1 dB
noise figure at 2 GHz, the best reported noise figure of any silicon based field-effect
transistor. The associated gain of the devices was high with 17.5 dB and 12 dB of gain
at 2 GHz for the NMOS and PMOS respectively.
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54
NMOS
PMOS
2
6
4
8
10
12
14
16
Frequency (GHz)
Figure 3-31. Noise figure of 0.5 pm x 100 |Jjn T-gate
MOSFETs.
20
15
NMOS
10
5
PMOS
0
2
4
6
8
10
12
14
16
Frequency (GHz)
Figure 3-32. Associated Gain of 0.5 pm x 100 (im Tgate MOSFETs.
The excellent noise characteristics observed are once again due to the low gate
resistance achieved by the T-gate. In fact, the noise figures of our devices are the best
reported on any silicon based M OSFET technology. This can be seen from Table 3.2
which shows a comparison of the noise of the SOS MOSFETs with other silicon and
D I-V based technologies.
As expected, the HI-V and compound semiconductor
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55
devices have lower noise figure. However, the SOS devices have lower noise figure
and higher gain of any silicon-on-insulator technology.
Table 3.2. Comparison of noise figures for different technologies.
NMOS
PMOS
NM OS [18]
PMOS [18]
NM OS [19]
NM OS [20]
H B T [21]
H B T [22]
SOS
SIM O X
SIM O X
SIM O X
BESOI
SiGe
InP/InGaAs
P H E M T [23]
JFET [24]
M ESFET [25]
InGaP/InGaAs
GaAs
GaAs
0.5
0.25
0.25
0.9
1.5
2.7
0.6
0.8
1.0
5.0
2x0.6x8
3.5x3.5
0.15
0.5
0.25
0.5
0.46
13
18
15
17
6.4
1.3
3.25
4.7
8.5
1.6
9.8
12
0.8
1.0
11.6
1.4
2.0
0.2
0.33
0.41
0.4
0.4
1.7
2.2
6.8
13
1.6
3.5.6 Small Signal Modeling
In order to design circuits, a small-signal model of the transistors must be
developed. The small signal model used here is shown in Figure 3-33. Since sapphire
is an insulating substrate, the model used is identical to those used for GaAs based
MESFETs.
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56
Intrinsic FET
Figure 3-33. Small signal model of the SOS
MOSFET.
In order to determine the individual circuit element values of the model, an
extraction method utilizing S-parameter measurements was used. This is common for
HBTs, MESFETs and other three terminal devices. The extraction technique used is
discussed in Appendix A and the results are summarized here. After removing the pad
parasitics and converting the S-parameters to Y-parameters, the following equations
for the Y-parameters can be derived from small-signal analysis.
-v u —
(3.5)
from these equations, the individual circuit elements can be solved for.
Table 3.3
gives the circuit element values for a few bias point of a 0.5 pm x 100 pm n-channel
MOSFET.
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57
Table 3.3. Small-signal model param eter of an n-channel MOSFET.
■ MHH mMlMil l | B
1
2
3
i
i
2
5
5
5
2
2
2
2
2
2
i
i
i
205
245
200
58
58
57
33
30
30
20
20
20
12.4
14.2
15.0
1
1
1
3.6 Conclusion
SOS based n- and p-channel MOSFETs with optically defined gate lengths
down to 0.5 jims and metal strapped gates have been developed.
exhibited excellent microwave performance with /max and
Fmjn values
These FETs
among the best
reported to date for any silicon based FET technology. With their present/, and/max
values, these FETs are ideally suited for circuits operating in the I to 10 GHz regime.
3.7 References
1. J.E. Lilienfeld, U.S. Patent 1,745,175 (1930).
2. O. Heil, British Patent 439,457 (1935).
3. J. Bardeen, “Surface states and rectification at a metal semi-conductor contact,”
Physics Review 71,717, 1947.
4. W. Shockley and G.L. Peterson, “Modulation of Conductance of Thin Films of
Semiconductors by Surface Charges,” Physics Review 74, 232, 1948.
5. D. Kahng and M .M . Atalla, “Silicon-Silicon Dioxide Field Induced Surface
Devices,” IRE Solid-State Device Research Conference, Carnegie Institute of
Technology, Pittsburgh, PA, 1960.
6. S.M. Sze, Physics o f Semiconductor Devices, 2nd Edition, Chapter 8, Wiley, New
York, 1981.
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58
7. B.G. Streetman, Solid State Electronic Devices, 3rd Edition. Chapter 8, Prentice
Hall, 1990.
8.
R.A. Pucel, H.A. Haus, and H. Statz, “Signal and Noise Properties of GaAs
Microwave Field-Effect Transistors,” in L. Martin, Ed., Advances in Electronics
and Electron Physics, Vol. 38, Academic, New York, 1975, p. 195.
9. H. Fukui, “Optimal Noise Figure of Microwave GaAs MESFETs,” IEEE
Transactions Electron Devices, vol. 26, 1979.
10. T. Mogami, H. Wakabayashi, T. Saito, T. Tatsumi, T. Matsuki, and T. Kunio,
“Low-Resistance Self-Aligned Ti-Silicide Technology for Sub-Quarter Micron
CMOS Devices, IEEE Transactions Electron Devices, vol. 26, no. 6, 1979.
11.C.K. Lau, Y.C. See, D.B. Scott, J.M. Bridges S.M. Pema, and R.D. Davies,
‘Titanium Disilicide Self-Aligned Source/Drain + Gate Technology,” IEDM
Technical Digest, 1982.
12. S.M. Sze, VLSI Technology, Wiley, New York, 1981, p. 83.
13. G. Garcia, R. Reedy, and M. Burgener, “High-Quality CMOS in Thin (100 nm)
Silicon on Sapphire,” IEEE Electron Device Letters, vol. 9., no. 1, 1988.
14. S.T. Hsu, "Electron Mobility in SOS Films, " IEEE Transactions on Electron
Devices, vol. 25, no. 8, Aug. 1978.
15. A.J. Hughes, “Stress-induced Anisotrophy in the Electrical
S i/A L O j,” Journal o f Applied Physics, vol. 46, no. 7, July 1975.
Properties of
16. B.W. Offord, "Fully-Depleted Silicon-on-Sapphire and Its Application to
Advanced V LS I Design," 4th NASA Symposium on VLSI Design, University of
Idaho, Oct. 1992.
17. D.K. Sadana, "Fully-Depleted 0.25 pm n-MOSFETs on SOS, SIM O X and BESOI
Substrates," 1994 IEEE International SOI Conference, Oct. 1994.
18. M .H . Hanes, A.K. Agarwal, T.W. O’ Keeffe, H .M . Hobgood, J.R. Szedon, TJ.
Smith, R.R. Siergiej, P.G. McMuIIin, H.C. Nathanson, M .C . Driver, R.N. Thoms,
“M IC R O X ™ - An All-Silicon Technology for Monolithic Microwave Integrated
Circuits,” IEEE Electron Device Letters, vol. 14, no. 5, May 1993.
19. A.K. Argawal, M TT-S Workshop, May 1995.
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59
20. A.L. Caviglia, R.C. Potter. LJ. West. “Microwave Performance of SOI nMOSFET's and Coplanar Waveguides,” IEEE Electron Device Letters, vol. 12. no.
1. Jan 1991.
21. H. Schumacher. U. Erben, A. Gruhle, “Low-noise Performance of SiGe
Heterojunction Bipolar Transistors,” 1994 IEEE International M icrowave
Symposium , May 1994.
22. Y.K. Chen, R.N. Nottenburg, M.B. Panish, R.A. Hamm, D.A. Humphrey.
“Microwave Noise Performance of InP/InGaAs Heterostructure Bipolar
Transistors.” IEEE Electron Device Letters , vol. 10. no. 10. Oct. 1989.
23. M . Takikawa, and K. Joshin “Pseudomorphic N-InGaP/InGaAs/GaAs High
Electron Mobility Transistor for Low-Noise Amplifiers.” IEEE Electron Device
Letters, vol. 14, no. 8. Aug. 1983.
24. D. Scherrer. J. Kurse, J. Laskar, M. Feng, C. Takano, J. Kasahara. “Low-Power
Performance of 0.5-pm JFET for Low-Cost M M IC ’s in Personal
Communications.” IEEE Electron Device Letters , vol. 14. no. 9. Sept. 1993.
25. P.J. Apostolakis. J.R. Middelton. D. Scherrer, M. Feng, A.N. Lepore. “Noise
Performance of Low Power 0.25 Micron Ion Implanted D-Mode GaAs MESFET
for Wireless Applications.” IEEE Electron Device Letters, vol. 15. no. 7. Julv
1994.
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4. Polysilicon Sidewall Gate LDD MOSFET
4.1 Introduction
As was shown in the previous chapter, high speed optically defined MOSFETs
can be realized in silicon-on-sapphire.
However, these devices typically have
breakdown voltages around 4-5 volts. Unfortunately, these devices are not well suited
for power amplifier applications that typically require device breakdown voltages on
the order of three to four times that of the supply voltage. Hence a power amplifier
operating at a 3.3 volts power supply voltage would require a breakdown voltage
greater than 10 volts.
When device geometries are small, the electric field in the vicinity of the drain
can become quite high under normal bias conditions resulting in impact ionization and
the creation of electron-hole pairs.
This leads to increased current and eventually
avalanche breakdown. The traditional method of increasing the breakdown voltage is
by the inclusion of a lightly doped drain (LDD) into the device structure. An LDD
region increases the breakdown voltage of a MOSFET by reducing the electric fields
in the region of the drain and hence reducing the impact ionization. A cross section of
a device with an LDD is shown in Figure 4-1.
A comprehensive review of LDD
structures is given by Sanchez [1].
60
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61
IT
Figure 4-1. Cross section of a MOSFET with a
symmetric lightly doped drain.
In this case, the LDD region is "symmetric." That is. the processing steps for
necessary for the LDD also produce a lightly doped source region. This lightly doped
source has an adverse effect on de\ice performance by adding source resistance to the
derice. Ideally, an asymmetric LDD is needed in which only the drain region is Iightlv
doped.
Besides the advantage in breakdown voltage, an LDD region also has adverse
affects on derice performance.
Most notably are the increase in source and drain
resistance which can lead to decreased transconductance, higher knee voltages and
decreased microwave performance. A second affect is a decrease in the device transit
time leading to lower current cutoff frequencies (fy. This increased time comes about
from the time it takes electrons (or holes in a P-channel device) to traverse the LD D
region before being collected at the drain.
In addition to high breakdown voltage, a MOSFET for a power amplifier
operating at microwave frequencies needs to have a high /,. As we saw in previous
chapters, this can be achieved by reducing the gate length of the device.
Present
optical photolithography limits how small this gate length can be as is typically on the
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order of 0.35 to 0.4 pm. In order to achieve shorter gate lengths more elaborate and
expensive techniques such as electron beam lithography or x-ray lithograph} can be
used. These systems use electrons or x-rays to expose the resist instead ultraviolet
light used in standard lithography. They can result in gate lengths smaller than 0.1 um
but with great]}- increased processing costs and decreased manufacturability .
To overcome this gate length scaling problem (smaller = increased cost) a
lithograph}- less gate definition step is desirable. A sidewall process, like that used for
the SiO; sidewalls for self aligned silicide. can be applied to the gaie polysilicon
resulting in deep sub-micron gate lengths without lithography.
Putting the two above ideas together results in the Sidewall Gate FET
(SiGFET).
This combines a deep sub-micron gate length defined by a sidewall
process and an LD D region for increased breakdown voltage.
A schematic cross
section of the device is depicted in Figure 4-2. This device also benefits from the fact
that the LD D region is asymmetrical. Name!}, only the drain region is lightly doped
while the source region is heavily doped resulting in better device performance since
the device will not suffer from unnecessary source resistance effects.
Polvsilicon
Sidewall Gaie
n* Source
j
p channel
, n* Drain
n- LDD Region
Figure 4-2. Schematic cross section of the SiGFET.
Hence the SiGFET will allow a high breakdown voltage without suffering from
the speed limitations incurred by and LDD region. Namely , the increased transit time
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across the LDD region will be counteracted by the deep submicron gate length.
Furthermore, the **L“ shaped gate allows a lower resistance contact to the gate and as
in the case of the T-gate transistor, will lead to higher/m^.
4.2 Computer Simulations
Before beginning the process development and processing of the SiGFET.
optimal device parameters such as LDD oxide thickness. LDD doping had to be
investigated.
Moreover, a proof of concept had to be investigated.
To do this,
extensive computer simulations were performed.. These involved both device level
simulations for current flow, breakdown voltage, high speed performance and process
level simulations to determine implant energies and doses.
Device parameters, such as doping. LDD length. LDD oxide thickness and gate
length were investigated with a commercial device simulator (SILVACO's ATLAS').
A representative structure used for the simulations is shown in Figure 4-3.
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64
ATLAS
Data from mesh
Materials
Air
C o n d u c to r
0
0 *
08
12
IE
2
M icrons
Figure 4-3. SiGFET structure used for device simulations.
Before attempting simulations of the SiGFET, a traditional SOS MOSFET
structure like the T-Gate MOSFET was simulated to verify that the simulator's
parameter such as lifetime, impact ionization rate, mobility, etc.. properly predicted
the device performance.
4.2.1 DC Characteristics
A representative set of
I d s - V ds
characteristics for the simulations is shown in
Figure 4-4. This device has a 0.25 jim gate length, 0.7 pm LD D region and a 2000 A
thick oxide above the LDD region. As expected as a result of the LD D region, the
device has a high breakdown voltage around 12 volts. Also, despite the inclusion of
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65
the LD D region, the source and drain resistance, as observed from the linear region of
the I ds-V ds characteristics, remains low.
0 .4
. VGS = 0.5 to 4.0 V, Step 0.5 V
o.x
o
2
8
6
10
Drain Voltage (Volts)
4
12
14
Figure 4-4. Simulated IDS vs. V d s characteristics of a
Lg = 0.25 jam SiGFET with Lldd = 0.7 fim.
The transconductance of the devices was also examined. Figure 4-5 shows the
simulated transconductance of three SiGFETs with 0.25 |im gate length, 0.7 |im LDD
length and 1000 A , 2000
A,
and 3000 A this LDD oxides. The transconductance is
seen to increase as the LD D oxide thickness (tLoo) is reduced. This is because the
polysilicon above the n' region acts as a depletion mode M OSFET and the n' region is
modulated by the gate voltage. As in a normal FET, the thinner the gate oxide (in this
case the LDD oxide) the higher the transconductance.
However, the thinner LDD
oxide will also increase the input capacitance and result in a low er/t.
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66
80
E
E
Vi
E,
u
u
ac
* L D D O xide T hickness = 1000 A
• L D D O xide T hickness = 2000 A
■ L D D O xide T hickness = 3000 A
40
1
2
3
Gate Voltage (Volts)
Figure 4-5. Simulated transconductance vs. gate voltage
of a L g = 0.25 pm SiGFET with L Ldd = 0.7 |im.
Finally the breakdown voltage of the SiGFET was investigated.
Figure 4-6
shows the simulated breakdown voltage versus LDD length for a SiGFET with 0.25
Jim gate length. As expected, as the LDD length is increased, the electric fields are
reduced, reducing impact ionization and increasing breakdown voltage. However, as
we will see in the following sections, this increase in LD D length slows down the
operation of the device and results in a design tradeoff between speed and breakdown
voltage.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
67
so
0.6
0.7
0.9
1
LDD Length ((im)
Figure 4-6. Simulated B.V. vs. LDD length for a
SiGFET with Lg = 0.25 fun.
4.2.2 AC Characteristics
The AC characteristics of the devices were also studied. Figure 4-7 shows the
simulated magnitude of hii versus frequency for a SiGFET with Lg = 0.25 fim and
L ldd
= 0.7 fim. The unity gain cutoff frequency was observed to be
13
GHz.
VGS = 1.9 V
VDs = 7.0 V
S3
■o
f t = 13 GHz
-10
o.i
i
Frequency (GHz)
10
Figure 4-7. Simulated AC characteristics of a
Lg = 0.25 fim SiGFET with L Ldd = 0.7 fim.
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68
As mentioned in the previous section, as L D D length is increased, the
breakdown voltage increases.
However, due to the time necessary for electrons to
traverse the L D D region, the device speed, or f , decreases as the LDD length is
increased. This is highlighted in Figure 4-8 which plots f t versus LDD length for a
SiGFET with L g = 0.25 (im.
is
14
X
o
^
12
11
10
0 .5
0 .6
0 .7
0 .8
0 .9
1
LOD Length ( pm)
Figure 4-8. Simulated f t vs. L D D length o f a SiG FE T
with L g= 0.25 |im SiG FE T.
To verify that the electrons are traveling at saturated velocity across the LDD
region we can plot the transit time of electrons from drain to source (Tds = l/2it-/t )
versus LD D length for the SiGFET (Figure 4-9).
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0
0J2
0.4
0.6
0.8
I
LDD Length (pm)
Figure 4-9. Simulated transit time vs. LDD length of
a SiGFET with Lg = 0.25 pm.
As in the case of bipolar transistors, this transit time has the form of [2]
~
+ ^ ' ^LDD “
+
(4.1)
where tq is the delay time across the 0.25 pm channel and k is the delay time across
the LDD region per unit pm. The second term in (4.1) is the delay due to the hole
charge stored in the channel that is required to neutralize the charge of electrons
traversing the channel-drain depletion region (the length of the LD D region in this
case). The factor of two arises because only half of the charge needed to neutralize the
traveling carriers corresponds to hole charge in the channel; the remainder is
neutralized in the LD D region.
From Figure 4-9 we see that the slope of the line is 6.3 pS/pm which
corresponds to a saturation velocity
= 8 x 106 cm/sec., in good agreement with the
expected saturation velocity of 107 cm/sec.
Therefore we can conclude that the
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70
electrons are traveling at saturated velocity across the LD D region and that the LDD
region is optimized for speed.
4.2.3 Design Tradeoffs - Johnson Figure of Merit
Obviously from the proceeding sections, as design tradeoff exists between
maximizing breakdown voltage and maximizing f .
It is up to the circuit designer to
consider this tradeoff when designing a device for a particular application. It is also
important to note that despite all efforts to maximize bothy, and breakdown voltage at
the same time, there is a physical limit to how much the two can be increased. As first
discussed by Johnson [3], the product of the breakdown voltage and f of the device
can only be as high as 200 V-GHz (2 x 1011 volts/second) for a silicon based device.
This product is based on the breakdown field of silicon (2 x 105 volts/cm) and
saturation velocity (107 cm/sec.) of electrons in silicon.
Figure 4-10 shows this
simulated figure of merit for a SiGFET with Lg = 0.25 Jim and various LDD lengths.
It also compares the SiGFET with devices from other technologies.
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71
too
~
s.. ^.
s
sN
;^ * y
N
,.V
y,
Nj
N
:
1*
*©
>
CL
s
I
10
■w
.
BVX/ =5O
C
1■
<
N
V
yV
y
N 2 i
\
y
y
I'
N.
N
N
■
v
■
y
y
~ • s<3SSiC
»FE1
V _ ■ SO
ST-gateFE1
N. S.
y 1 Ts
\
_
A
Epi SiGeHBT
y
y
T
EpiSiBJT
%* ss,
- ►
► AIGaAs
AIGaAsHBT
HBT -------------------------k y’
~
s
y
■s >
♦ BulkCM
OS
\N.
'i>
_______
1-------i
_
_1
__
1 i U
-------1
—
i—
i—
i-L
— - rsl i r k
s
fc*
B
i
1
10
100
f t (GHz)
Figure 4-10. Simulated Johnson figure of m erit for a
Lg = 0.25 fim SiGFET with LLdd = 0*7 pm.
As can be seen from Figure 4-10, the B V /t product (Johnson figure of merit) of
the SiGFET is around 150 V-GHz. This is an improvement over the -100 V-GHz
observed for the T-gate SOS FETs discussed in Chapter 3.
4.3 Device Processing
Most of the processing of the SiGFET is compatible with normal MOSFET
processing steps. The two additional steps are: 1) polysilicon sidewall etch to form the
gate contact and 2) polysilicon and oxide etch to form the LD D region.
The
polysilicon and oxide etch steps to form the LDD region are straightforward but the
polysilicon sidewall requires process development. The following sections detail the
processing of the SiGFET from start to finish.
A schematic representation of the
process is shown in Figure 4-11.
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(f) LDD Etch, n+ Implant
(I) First Level Metal
Figure 4-11. Processing steps of the SiGFET.
4.3.1 Island Etch and LDD Implant
The first processing step is to define the active device are in the thin film
silicon. This also serves as an isolation step between devices. The silicon “island” is
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73
formed by standard photolithography and RIE etch until the silicon is cleared and the
sapphire is exposed (Figure 4-1 la). After formation of the islands, the entire wafer is
implanted to the desired n' doping of the L D D region.
4.3.2 LDD Stack Deposition and Etch
Next, the thick oxide and polysilicon over the LDD region are deposited
(Figure 4-1 lb). The oxide serves to separate the gate contact region from the drain
area. As mentioned in section 4.2, the thickness of the oxide is important. The 3800
A thick polysilicon serves as the area to which we make contact to the gate. After
deposition, the LD D stack is etched with an RIE to expose the source and channel
areas of the device (Figure 4-1 lc).
4.3.3 Channel Implant, Gate Oxide, and Gate Sidewall Formation
After completion of the LDD stack, the p channel implant is done, self aligned
to the LD D stack without lithography. The dosage of this implant must be controlled
to set the proper threshold voltage of the device. This implant must compensate the
earlier n' LD D implant. Next, a 120 A gate oxide is grown (Figure 4-1 lc) and the gate
polysilicon is then deposited over the entire wafer (Figure 4-1 Id) and finally doped by
flowing POCI3 . The thickness of this polysilicon is critical in that it determines the
final gate length of the device (e.g. 0.2 pm thick polysilicon will results in a 0.2 pm
polysilicon sidewall).
Hence it is possible to form deep sub-micron gate lengths
without lithography. The polysilicon is then RIE etched to form polysilicon sidewalls
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74
(Figure 4-1 le) in much the same way as oxide sidewalls are formed prior to
salicidation.
4.3.3.1 Polysilicon Sidewall Etch Initial Results
As stated before, the polysilicon sidewall is one of the two steps added to the
process and the only one that required process development.
As such, the etch
conditions had to be studied and perfected prior to implementation in the full device
process.
The first process implemented was the process being used to etch the
polysilicon gate in NRaD’s standard digital process.
The etch conditions are
summarized in Table 4-1. This etch used hydrogen bromide (HBr) and chlorine (CL 2 )
for the reactants. However, HBr has an adverse effect in that it produces a polymer
during the etch process. This results in “dog ears” forming on the tops of the sidewalls
(Figure 4-12).
Table 4-1. Etch conditions of the first polysilicon sidewall etch trial.
Pressure
HBr Flow Rate
C li Flow Rate
Etch Rate
Power Density
DC Bias
Substrate Temperature
15 mTorr
45 seem
20 seem
3000 A/min.
0.7 W /cn r
300 V
45°C
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75
Figure 4-12. Polvsilicon sidewall etch with HBr.
To overcome the dog ear problem. HBr was removed as one of the etching
species and the C l; flow was increased. These etching conditions are summarized in
Figure 4-12. As can be seen from Figure 4-13. the dog ears are no longer present and
the sidewall looks good when the HBr is removed.
Table 4-2. Etch conditions of the second polysilicon etch trial.
Pressure
Cl; Flow Rate
Etch Rate
Power Density
DC Bias
Substrate Temperature
15 mTorr
40 seem
9000 A/min.
0.7 W/cirT
300 V
45°C
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Figure 4-13. Polvsilicon sidewall etch without HBr.
The potential problems of removing the HBr are as follows.
selectivity of the polysilicon etch to the gate oxide is reduced.
First, the
This could lead to
shorting of the gate to the source. Also, the etch rate is increased from around 3500
A/min. to about 6000 A/min. Although not a significant problem, the increased etch
rate means a shorter etch time a less time to develop an accurate trace on the endpoint
monitor system. For example, a 0.2 pm gate length would only require a 20 second
etch. Typically. 10 to 15 seconds is needed to establish a stable signal for the endpoint
monitor system used in our reactive ion etcher.
4.3.4 LDD Etch and Source/Drain Implant
Now that the gate has been defined, we need to expose the drain region in the
middle of the device.
The LDD stack is etched for a second time.
In addition to
exposing the drain region, this etch is used to define the length of the LD D region
(Figure 4-1 If). The lithography for this step is very critical and must be tightly aligned
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to the existing polysilicon stack. If the mask is misaligned by 0.1 pm and the device
only has a 0.5 pm long LD D region, the desired LD D length will be off. plus or minus.
20%. In addition, since the device has two finger in parallel, one would have a 0.4 urn
LD length and the other would have a 0.6 pm LD D length. After the L D D etch, an
arsenic implant (55 KeV. 3 x 1015 cm'2) implant was done to form the n* source and
drain regions (Figure 4-1 If).
4.3.5 Oxide Sidewall Formation and Salicidation
As mentioned in Chapter 3. a self-aligned silicide process is used to reduce the
source and drain resistances. The next two process steps are the deposition (Figure 411g) and formation (Figure 4-1 Ih) of the SiO; sidewalls.
After the sidewall are
formed, titanium is deposited and then reacted to form titanium silicide (Figure 4-11 i).
4.3.6 Backend Processing
After salicidation. all that remains to complete the wafers is the backend
processing (contact opening and metalization).
For the contact opening, a 5000
A
thick oxide is deposited (Figure 4-11 j) and then patterned to etch contact holes in the
oxide to allow access to the gate, source and drain regions (Figure 4-1 lk).
After
etching, the first level metal is deposited and defined by RIE etch (Figure 4-111). If
necessary for circuits, an interlevel dielectric (5000
A SiO;)
is deposited and an etch to
form via opening from first level metal to second level metal is performed.
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78
Figure 4-14 shows the final structure of the SiGFET. Figure 4 - 14a shows a
close up of the intrinsic FET with Lg = 0.15 |im and L ldd = 1.0 |im, while Figure 4I4b shows the first level metalization contacts to the source and drain.
Poly-Si Sidewall
Polysilicon
SiO,
Sapphire
Drain
Figure 4-14. Final structure of the SiGFET.
4.3.7 T-Gate Processing
As mentioned in Chapter 3, a metal reinforced gate can reduce the gate
resistance of the transistor and increase microwave performance. This technique can,
and has been, applied to the SiGFET.
The same process steps from Chapter 3 are
followed after the formation of the SiOi sidewalls and silicide. As in will be seen in
the following sections, and as observed in Chapter 3, the incorporation o f the T-gate
increases the
of the transistor.
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79
4.4 DC Characteristics
For verification of the process sequence, the first run o f SiGFETs had only one
LD D oxide thickness (2000 A ) and doping (2 x 1017 cm'3) and one gate length (0.25
pm). Devices with varying L D D lengths and gate widths were processed. The
V ds
I ds v s .
characteristics of a 50 pm and 100 pm width SiGFET are shown in Figure 4-15
and Figure 4-16 respectively. As expected as a result of the incorporation of the LDD
region lead to a high breakdown voltage.
15
VGS = 0 to 3 V, Step 0.5 V
12
9
6
3
0
0
2
4
6
8
10
V d s (Volts)
Figure 4-15.
VDs curves for a Lg = 0.25
Wg = 50 p m SiGFET.
I ds vs.
pm ,
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80
15
■VGs = 0 to 3 V, Step 0.5 V
12
9
6
3
0
0
2
4
6
8
10
V ds (Volts)
Figure 4-16. IDs vs. VDS curves for a Lg = 0.25 |jm,
Wg = 100 [unSiGFET.
Unfortunately, as observed from Figure 4-15 and Figure 4-16, we see that there
are two problems with the FET: non-ohmic source/drain contacts and a leakage current
that doesn't allow the device to be pinched off. The non-ohmic contact is a result of
improper salicidation and the leakage current is a result of a periphery leakage current
and is not intrinsic to the device. Both of these effects will be discussed in more detail
in Section 4.6.1.1 and Section 4.6.2 respectively.
The
I d s - V ds
characteristics also show saturation at high
V gs
values. This is
due to velocity saturation within the LD D region. The maximum current that can be
carried when velocity is saturated is given by
I max
=
svml Wg
(4.2)
where Ns is the carrier concentration (generally given by the doping), vsat is the
saturation velocity of electrons, and W g is the gate width. For the above device with
N s = 2 x 10I2cm '\ vsat = 107 cm/sec and W g = 100 (im, IMAX = 32 mA. This is in good
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81
agreement with the observed onset of saturation at about 30 mA. This saturation also
indicates that the electron are traveling at saturated velocity as observed from the
interpretation of the/t results in Section 4.2.2.
40
VGS = -10 to 12 V, Step 2 V
35
Sa uration at high gate bis
30
0
1
2
4
3
5
6
7
8
V ds (Volts)
Figure 4-17. IDS vs. VDs characteristics of a SiGFET
(Lg = 0.25 pm, Wg = 100 pm, LLdd = 1*0 pm ) a t high
gate bias.
4.5 Microwave Characteristics
The microwave characteristics of the devices were measured on an HP 8510B.
Figure 4-18 shows the current gain (h2 i) and
maximum stable gain / maximum
available gain (M A G /M S G ) of a SiGFET with Lg = 0.25 p.m and Lldd = 1.0 p.m. The
/ t and/max of the device are 8 GHz, in fairly good agreement with the simulated value
o f/t = 10 GHz.
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82
25
Ilh,I
ca
■o
s
e
aefl
2
i
10
Frequency (GHz)
Figure 4-18. Microwave characteristics of a SiGFET
with Lg = 0.25 pun and LLdd = 1*0 |im.
The difference in the model versus experiment can be explained by many
factors. First, the pad parasitics can contribute to the reduction in f but more likely,
the models used in the simulation don't contain all physics that occur in the real
device. These include issues like the quality of the oxide-silicon interface above the
LD D region which can lead to increased surface scattering and lower f , difference in
the silicon film quality leading to lower than expected mobilities, and many more. In
general, the device simulations were used more as a proof of concept rather than a well
calibrated design tool. With more devices and more simulations, the simulator model
parameters can be adjusted and improved to realize accurate predictions of device
performance.
The microwave characteristics of a SiGFET with a T-gate is shown in Figure
4-19. As expected as a result of decreased gate resistance of the T-Gate, the/mm is
increase from 8 GHz to 27 GHz. However, as noted before, one of the advantages of
the “L” shaped gate is the reduced gate resistance provided by the wide contact.
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83
Hence the / max value of the SiGFET without a T-gate is still higher than what would
have been achieve with a conventional 0.25 jam gate structure.
25
4J
■o
3
oQ
n
C
M A G /M S '
1
10
Frequency (GHz)
Figure 4-19. Microwave characteristics of a T-Gate
SiGFET (L g = 0.25 pm, L ldd = 1-0 (im) at VGs = 1.5
V, VDs = 4 V.
Finally, th e/t of the a SiGFET is plotted in Figure 4-20 versus gate and drain
bias. It is evident that for a wide range of bias conditions, th e / remains fairly uniform
and hence can be operated with low power dissipation and still maintain its speed.
This is desirable in order to increase the power added efficiency of a power amplifier
that would be built from such a device.
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84
10
Figure 4-20. Microwave characteristics of a T-Gate
SiGFET ( L g = 0.25 |im , L ldd = 1*0 fim ) versus bias.
4.5.1 Gate-Drain Capacitance
The small signal model parameters were extracted as described in Appendix A.
Important values to note are the gate-source and gate-drain capacitances. For the Sparameters and bias condition shown in Figure 4-19 the values of the small-signal
model capacitances were Cg* = 18.5 fF, Cgd = 15.2 fF, and Cds = 29.2 fF. As expected,
the gate-drain capacitance, Cgd, is high as a result of the "L" portion of the gate
overlapping the LD D region. This value is close to predicted by simple parallel plate
capacitor theory.
eA
3.9 • 8.854 x 10- 1 8 fF /
02/m
100/Jm)
= \1 3 fF
(4.3)
where d is the thickness of the LDD oxide and A is the area of the polysilicon above
the LDD region
( L l d d = 1 .0
(im, W g =
100
jxm). The slight difference in the extracted
and predicted Cgd can be related to division of Cgd and Cgs in the model and other
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85
factors like oxide thickness uniformity, exact LDD length and fringing fields no taken
into account in the parallel plate approximation.
As we saw in Chapter 3 on the T-Gate transistor, in a normal high speed
MOSFET, Cgd is typically 0.5 x Cg*. For the SiGFET, Cgd is almost equal to Cg*. This
causes decreased microwave performance, but as we saw earlier in the chapter, this
overlap increases the DC performance of the device so again, a tradeoff exists.
4.6 Key Processing Issues
As mentioned earlier, there were a few problems found with the DC
characteristics o f the initial SiGFET.
These can be attributed to processing level
issues, particularly in the silicide process, and a mask level design issue that results in
the leakage current.
4.6.1 Self-Aligned Silicide
4.6.1.1 Ohmic Contact
As mentioned in Chapter 3, the silicide process relies on a tight control of the
titanium and silicon thickness prior to reaction. If either are in error such that the
silicide reaches the silicon-sapphire interface, the reaction can continue laterally
resulting in voids and dopant segregation from the n+ source/drain contact.
This
results in a metal (silicide) - semiconductor Schottky diode contact instead of the
desired ohmic contact. As a result, the linear region o f the DC characteristics show a
Schottky diode behavior as observed in Section 4.4.
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86
By careful control of the deposited titanium thickness and silicon thickness,
this problem can be minimized as observed by the
Figure 4-17.
I ds- V
ds
characteristics shown in
This device was processed in a different lot with a thinner titanium
deposition to reduce the chance of creating a non-ohmic contact as described above.
However, as will be discussed in the following section, using too thin a silicide can
create other problems for the device.
4.6.1.2 Bridging of the Gate (Floating Gate MOSFET)
The sidewall gate process follows the gate oxidization. As a result, an oxide
exists on the side (and top) of the LD D stack prior to formation of the sidewall gate.
Ideally, the silicide formation will cause a short between the gate contact and the
sidewall gate (Figure 4 -2 1a). However, if the silicide is made to thin (such as to avoid
Schottky behavior of the source and drain contacts) then the silicide won’t short the
gate contact polysilicon to the sidewall gate polysilicon (Figure 4 -2 lb). As a result,
there will be no control of the channel region.
Silicide
(a) Gate Shorted
(b) Gate Open
Figure 4-21. SiGFET with sidewall gate (a) shorted and (b) not
shorted to the gate contact by silicidation.
With no control of the channel region, the device does not operate as a normal
MOSFET. However, as was observed in one lot of SiGFETs, an EEPROM type effect
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87
will exist with the sidewall acting as the floating gate of the EEPROM and the gate
contact acting as both the controlling gate (select gate) for the EEPROM and the gate
of the depletion mode FET. This is pictured schematically in Figure 4-22.
Gate
Source o
- J T
/
J r L
- o
Drain
\
Floating gate Depletion Mode
MOSFET
MOSFET
Figure 4-22. Schematic representation of a SiGFET
without shorting of the gates by silicidation.
4.6.1.2.1 Charging of the Floating Gate
With application of a large positive gate voltage, electrons will tunnel from the
gate contact, across the oxide, into the sidewall gate.
Once the sidewall gate is
charged, the channel region is inverted and the device operates like a depletion mode
(normally on) MOSFET with a gate length corresponding to the length of the LDD
region and a gate oxide corresponding to the thickness of the L D D oxide. This effect
is shown in Figure 4-25.
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88
30
VGs = 0 to 10 V, Step 2 V
25
20
15
10
5
0
0
1
2
3
V DS
4
5
6
(Volts)
Figure 4-23. IDs vs. Vds characteristics of a SiGFET
(Lg = 0.25 (nn, Wg = 50 pm, L ld d = 1.0 fJJti) after
application of VGs = 10 V.
The time necessary to charge the floating sidewall gate was observed by first
discharging the gate by applying -10 volts to the gate and then monitoring the drain
current as a function of time when a Vgs = 10 volts, V DS = 5 volts bias was applied to
the device.
This time dependence is shown in Figure 4-24, which reveals a
logarithmic response.
This suggest that the transport is due to Fowler-Nordheim
tunneling and can be explained as follows. With no charge on the floating gate, there
are many traps available to capture an electron and the charge on the gate increases
rapidly (corresponding to a rapid increase in Id). A s these traps fill, the probability of
a tunneling event becomes smaller and the charge on the floating gate approaches a
maximum value, causing the drain current to saturate.
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89
40
35
30
25
20
15
10
5
0
0
5
10
15
20
Time (Seconds)
Figure 4-24. I ds (at VGS = 10, VDS = 5 V) as a
function of time showing the time necessary to
charge the floating gate.
4.6.1.2.2 Discharging of the Floating Gate
The charge on the sidewall gate can also be removed by the application of a
large negative gate bias. With a large negative bias on the gate contact, electrons from
the sidewall gate will tunnel across the oxide to the gate contact. With no charge on
the sidewall gate, the channel is depleted and little current will flow in the depletion
mode MOSFET. This is shown in Figure 4-25. Note that once the gate bias reaches
10 volts, and the sidewall gate is charged, the current is dramatically increased.
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90
30
gs
= 0 to 10 V, Step 2 V
25
20
15
10
5
0
0
1
2
3
4
5
6
V'ds (Volts)
Figure 4-25. I d s v s . V d s characteristics of a SiGFET
(Lg = 0.25 pm. Wg = 50 pm, Lldd = 1-0 pm) after
application of VGs = -10 V.
The above explanation can be verified by analyzing the I ds-V ds characteristics
of the depletion mode FET when the sidewall gate is positively charged (Figure 4-23).
For this case, the n' LDD doping was 2 x 1017 cm'2, the LD D oxide thickness was
3000 A. the LDD length was 1.0 pm and the gate width was 50 pm.
From these
values, the expected transconductance of the depletion mode MOSFET can be
estimated.
W
g.=-^nC0X-f-(va - v T)= ^-(400 V •cm / sec)
f 3.9- 8.854 x l ( T u F /c m ) ( 100pm)
v
3000 x 10"8 cm
j { \fim j
(4):
(4.4)
= 1.85 mS
From Figure 4-23 we see that the transconductance of the SiGFET is about 2 mS. in
good agreement with our approximation of 1.85 mS. This confirms the fact that the
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
modulation of the current is due to the depletion mode transistor and not the sidewall
gate transistor <as desired i.
To further verify the erase operation, the drain current was monitored as a
function of time when a large negative voltage iV GS = -10 V i was applied to the device
after programming. Figure 4-26 shows this drain current as a function of time. The
resolution of the instrument was unable to show the rapid decrease of the current on
order of a few hundred milliseconds but clearly the application of the negative bias to
the gate contact can discharge the floating gate and turn off the p-channel device.
4 .3
4J
4
3
ST
3 .8
0
3
4
6
8
10
Time tSeconds i
Figure 4-26. I ds <at VGs = -10. Yds = 5 V i as a
function of tune showing the time necessary to
discharge the floating gate.
4.6.2 Leakage Current
.4s mentioned in Section 4.4 there is a gate width-independent leakage current
associated with the de\ice.
The leakage current is believed to be a result of an
unintentional current path at the edge of the gate. This is shown in Figure 4-27. Since
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92
the gate fingers do not cross over the top of the island, there is a 0.5 pm wide path that
can allow current to flow even when the gate voltage is low (and the normal channel is
depleted). This layout was chosen to reduce the chance of the sidewall gate shorting to
the source and drain region but inadvertently caused the gate bias independent leakage
current.
Poly-Si
Sidewall
SiO,
Sidewall
Figure 4-27. Simplified layout (top view) of the
SiGFET showing the leakage path.
To verify' the existence of the leakage path, two methods were used. The first
used a laser trimming system to obliterate the area of the leakage path. An SEM of a
device after laser obliteration of the top of the device is shown in Figure 4-28.
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93
Figure 4-28. SEM of a SiGFET with the leakage
current path destroyed by laser trimming.
The
I ds- V
ds
characteristics of the above device were measured before and after
application of the laser and are shown in Figure 4-29. The drain current at Vds = 5
volts, Vgs = 0 volts was reduced by a factor of four from 0.8 mA to 0.2 mA.
VGS = 0 to 2 V, Step 0.5 V
—
Before Laser
- A fte r Laser
<
s
o
l
2
3
4
5
VDS (Volts)
Figure 4-29. IDS vs. Vds characteristics of a SiGFET
before and after laser annihilation.
The second way that the leakage current path was verified reduced was by
stressing the SiGFET to high bias. At a bias of V Gs = 0 volts, the drain voltage was
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94
swept from 0 to 13 volts. At a value around 11.8 volts, the current suddenly dropped.
When the
I d s - V ds
characteristics were run, a significant amount of leakage current had
disappeared. It is believed that the leakage path, with lower breakdown voltage than
the SGFET, "blew" like a fuse. As a result of the leakage path being destroyed, the
leakage current was drastically reduced.
8
VGS = 0 to 3 V, Step 0.5 V
6
<
5
VGS = 0 before leakage
path is destroyed
4
v.
Before stress
A fte r Stress
2
0
0
2
4
6
V
ds
8
10
12
14
(Volts)
Figure 4-30. IDs vs. VDs characteristics of a SiGFET
before and after leak path was blown.
Both of the above methods indicate that the leakage current is a result of the
edge o f the device and not intrinsic to the SiGFET.
By changing the layout and
modifying the processing, the leakage path should be able to be removed.
4.7 Integration with Standard CMOS
Finally, a method to integrate the SiGFET with a standard CMOS process is
necessary. This would allow high performance MOSFETs as discussed in Chapter 3
to be combined with the SiGFET on the same wafer.
In turn, this would allow
integration of a variety of high speed circuits and power amplifiers. This integration is
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95
well suited to portable communication systems where high performance circuits are
needed for signal processing while power amplifiers are needed to drive the antenna
and send out the signal.
Integration of the SiGFET with standard CMOS can be achieved rather easily.
Figure 4-31 shows the critical processing steps of this integrated process. The silicon
islands are formed in the normal fashion and appropriate implants (n well, p well and
LD D ) are performed. Next the LDD S i02 and polysilicon are deposited (Figure 4-3 la
and g). As before, this LDD stack is etched and defined by photoresist for the SiGFET
(Figure 4-31 b). However, for the standard MOSFET, this area is unmasked and the
device is cleared back to the silicon island (Figure 4-3 lh). At this time, the devices
are patterned for channel implants.
For a full CMOS process of both standard
MOSFET and SiGFETs, this could entail 4 photolithography steps and implants.
However, if dopants are chosen carefully, this could be reduced to two steps, one for
the NMOS transistors (standard and LD D ) and one for the PMOS transistors (standard
and LDD). Next the gate oxide is grown and the gate polysilicon is deposited (Figure
4-3 lc and i). Next, lithography is used to define the gate of the standard MOSFET.
Then, as before, an RIE etch is used to define the SiGFET’s polysilicon sidewall gate
(Figure 4-3 le).
During this etch, the standard MOSFET’s gate is protected by
photoresist and defined in the normal fashion (Figure 4-31 j). Next the LDD region is
defined by lithography and etched. During this time, the entire standard M OSFET is
covered with photoresist so it is not affected during this etch. Finally, the source and
drain implants (two lithography steps) are done and Si02 sidewall are formed (Figure
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96
4 -3 I f and k). The remaining backend steps (metalization and passivation) remain the
same as before.
SiGFET
Standard MOSFET
(a) Island Etch, L D D Stack
(g) Island Etch, L D D STack
Photoresist — i
(b) L D D Stack Etch
(h) L D D Stack Etch
(d) Gate Oxide and Polysilicon
(i) Gate Oxide and Polysilicon
Gate Photoresist
(e) Polysilicon Sidewall Etch
(j) Polysilicon Gate Etch
(0 L D D Etch, SiO , Sidewalls
(k) S iO , Sidewalls
Figure 4-31. Integration of the SiGFET with
standard CMOS processing.
Compete integration o f standard CMOS transistors with complementary
SiGFETs with double level metal would require 18 mask levels.
These steps are
broken down in Table 4-3.
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97
Table 4-3. Mask stpes necessary for the integration
of standard CMOS and the SiGFET.
Mask Level
Process Step
Technology
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Island Definition
p well
n well
p' L D D
n’ LD D
LD D Stack Definition
p channel implant
n channel implant
p channel implant
n channel implant
Gate Definition
n+ Source and Drain
p+ Source and Drain
Contact opening
Metal 1
Via
Metal 2
Passivation opening
Standard, SiGFET
Standard
Standard
SiGFET
SiGFET
SiGFET
Standard
Standard
SiGFET
SiGFET
Standard
Standard, SiGFET
Standard, SiGFET
Standard, SiGFET
Standard, SiGFET
Standard, SiGFET
Standard, SiGFET
Standard, SiGFET
The only foreseeable problems with integration lie in the formation of the
standard CMOS gate. Since this uses the polysilicon for the SiGFET, if the SiG FET’s
gate length is 0.1 pm, the thickness of the CMOS gate will be 0 .1 pm. This would
increase the gate resistance but could be overcome with a T-gate process.
A more
serious problem with the thickness lies in the fact that the source and drain implants
(self-aligned to the gate) may penetrate through the get polysilicon and into the gate
oxide and channel.
Hence the smallest gate length of the SiGFET would be
determined by the silicon island thickness and source/drain implant parameters.
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98
4.8 Conclusion
A novel MOSFET utilizing a sidewall gate contact in conjunction with a
lightly doped drain region has been developed for power amplifier applications. Gate
lengths as small as 0.15 jim have been demonstrated with the polysilicon sidewall gate
process. The sidewall process allows deep sub-micron gate lengths to be fabricated
with out expensive and time consuming electron beam lithography. The lightly doped
drain increases the breakdown voltage to above 10 volts for an Lg = 0.25 Jim device
without degrading device performance too much.
The combination of a deep sub-micron gate length (and corresponding high
speed) in conjunction with the lightly doped drain (and corresponding high breakdown
voltage) makes the sidewall gate ideally suited for power amplifier applications in the
L and S bands.
4.9 References
1. J.J. Sanchez, K.K Hsueh, and T.A. DeMassa, "Drain-Engineering Hot-EIectron
Resistant Device Structures: A Review," IEEE Transactions on Electron D evices ,
vol. 36, no. 6, June 1989.
2. S.M. Sze, Physics of Semiconductor Devices, 2nd Edition, Wiley & Sons, New
York, 1981, p. 159.
3. E.O. Johnson, "Physical Limitations on Frequency and Power Parameters of
Transistors," RCA Review, June 1965.
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5. Passive Elements
5.1 Introduction
Passive elements including inductors, capacitors and resistors are needed in
microwave circuits for a wide variety of applications.
Inductors can be used for
matching circuits as well as to provide RF chokes to signals on DC power supply
lines. Capacitors are also needed for matching circuits and for de-coupling DC and
AC signals. Resistors provide many functions such as bias circuitry and passive loads
for amplifier circuits.
This chapter discusses inductors, capacitors and resistors
developed for the SOS IC technology.
5.2 Spiral Inductors
Spiral inductors have been in existence for many years. Wheeler [1], Terman
[2] and Burkett [3] have discussed formulas for predicting the inductance of spiral
inductors. However, most of their equations were analytical and only approximate. In
1974, Greenhouse developed formulas for predicting inductance of rectangular spiral
inductors [4]. The formulas are built around the following concepts. Any length of
conductor has an associated self-inductance given by
L =0.002/ Hn
+ 0.50049 +
99
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(5.1)
100
where a, b, and I are the conductor width, thickness and length in centimeters.
Furthermore, two parallel conductors have a mutual inductance (either negative or
positive depending on the direction of current flow). Spiral inductors take advantage
of this mutual inductance. Greenhouse [4] showed that the total inductance of a spiral
inductor is the
sum of its self inductance and its mutual inductances,
Limlcuwr =
where M
^ M
(5.2)
is the mutual inductance (both positive and negative)between the
conductors. The mutual inductance of spiral inductors can be on the order of 60-70%
of the total inductance value.
Therefore, a large inductance can be achieved with
much less area than needed for a straight conductor.
Planar inductors on silicon were investigated in the 1960’s but it was initially
concluded that use on silicon integrated circuits was impractical [5]. Then in 1990,
Nguyen and Meyer published a paper showing that inductors could be used in silicon
IC ’s [6]. Here a 9.7 nH inductor was reported with a quality factor (Q) of 3 at 900
M Hz and a 1.9 nH inductor had a Q of 8 at 4.1 GHz.
This paper stirred many
researchers to re-investigate the potential of fabricating inductors on silicon.
To increase the performance of spiral inductors on bulk silicon, many novel
processing techniques such as deep trench etches under the inductor [7,8] and thick
gold metalization [9,10] have recently been reported. The inductors fabricated on SOS
use a standard digital CMOS process with aluminum metalization and rely only on the
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101
high dielectric quality sapphire substrate (er = 9.39, tan 5 < 0.0001 at 3 GHz, p = 1014
Q-cm) to improve their performance. This eliminates the need to develop costly and
less reliable process steps. As will be seen in this chapter, the SOS inductors have
higher self-resonant frequencies and higher Q than identical ones fabricated on bulk
silicon. This improvement will be borne out by small signal modeling of the inductors
fabricated on SOS and those fabricated on bulk silicon.
5.2.1 Processing
Circular spiral inductors with conductor width and spacing of 5 Jim were
fabricated using a double level metal process optimized for digital applications. For
comparison to bulk CMOS and other SOI technologies, the inductors were processed
on both SOS and bulk silicon (-8-10 Q-cm). For the latter case, a 1.7 pm thick SiOi
insulating layer was deposited on top of the bulk silicon wafers before fabricating the
inductors.
Second level metal (1.6 pm TiW /A l/Ti) was separated from First level
metal (0.5 pm TiW /A l/Ti) by a 1 pm inter-level dielectric of SiOi. Cross sections of
the inductor fabricated on SOS and bulk silicon are shown in Figure 5-1.
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102
2nd Level Metal
1 * L e vel M e fa l
1.0 pm S i02
Sapphire Substrate
(a)
2nd Level Metal
1“ L e v e l M e t a l
1.0 pm SiO,
1.7 pm SiO,
Si Substrate
(b)
Figure 5-1. Cross section of the spiral inductors: (a)
SOS, (b) Bulk Silicon.
In order to reduce parasitic resistance (to increase Q), vias were placed along
the length of the spiral, except in the overcrossing area.
This yielded a thicker
effective metalization, with an overall sheet resistance of -1 7 mO/sq. for the
combined metal layers.
The inductors were laid out for probing in a two-port
configuration with ground-signal-ground coplanar probes.
A photograph of a
fabricated inductor with 8 turns is shown in Figure 5-2.
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103
Figure 5-2. Photograph of an 8 turn spiral inductor.
5.2.2 Microwave Characteristics
Two-port S-parameter measurements were made using an HP8510B network
analyzer from 0.2 to 20 GHz in 0.2 GHz steps. Open and short circuit test patterns
were probed to measure pad parasitics for de-embedding as described in Appendix A.
Inductance and quality factor were extracted from the two-port data by converting it to
one-port data by shorting port 2 and then using
L=
JG 3
T
/
X
ImU^
^ 3 )
Re(c.)
Figure 5-3 shows representative extracted values of both inductance and
quality factor of an 8 turn inductor.
The inductance, peak quality factor and self­
resonant frequency of this inductor are 11 nH. 9.5. and 7 GHz respectively.
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104
u
V
rss
O'
Indactaoce
Quality Factor;
0.1
I
10
Frequency (GHz)
Figure 5-3. Inductance and quality factor for an 8
turn inductor on SOS.
Inductors with different number of turns, from 1 to 20. were measured. The
peak quality factor. Qpeak. and self-resonant frequency, /sr. of these inductors are
plotted as a function of the inductance in Figure 5-4. Peak quality factors above 10.
among the highest ever demonstrated in a silicon based technology, were achieved for
inductance values up to 25 nH. These values are on the order of those needed to make
high quality circuits operating at microwave frequencies.
Furthermore, the self­
resonant frequency is above 5 GHz. well suited for circuits operating at a few GHz.
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: 05
30
20
O'
s
-A
£
0
10
15
20
30
Inductance (nH)
Figure 5-4. Peak quality factor and self-resonant
frequency of inductors on SOS.
5.23 Modeling
5 3 3 .1 Simple Model
A circuit designer requires a model of the inductor for circuit simulations. A
simplified model of an inductor is shewn in Figure 5-5.
Tne model includes three
elements: an inductor, a resistor arising from the conductor resistance, and a capacitor
arising from the capacitance between the conductor windings.
L " R
Figure 5-5. Simple small-signal model for inductors
on SOS.
This model was used to fit the measured data: a representative fit of inductance
and quality factor is shown in Figure 5-6.
measured and modeled inductance.
There is a good agreement between the
However, the modeled aualin factor differs
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106
greatly from the measured value, especially at high frequencies. This can be explained
by the skin effect.
This effect causes the magnitudes of the magnetic and electric
fields, as well as current, to decrease exponentially as a function of distance of
penetration into a conductor. At low frequencies, current flows in the entire conductor
cross section and the resistance of the inductor is equal to its D C resistance.
Consequently, a good agreement in Q at low frequencies is obtained.
However,
around 2 GHz. the skin depth of aluminum is about equal to the total conductor
thickness, and at higher frequencies, it becomes smaller than the conductor thickness.
Hence, at high frequencies, current flows in the outer edges of the inductor coils and
the resistance increases causing Q to decrease from the value predicted by its DC
resistance.
20
15
10
lodnctaace
0
1
10
Frequency (GHz)
Figure 5-6. Measured versus modeled, inductance
and quality factor, for a 4 turn inductor on SOS.
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107
5.2.3.2 Modified Model
Ideally, the resistance in the simplified model should be modeled by frequency
dependent resistance that accounts for skin effects. However, circuit simulators such
as SPICE do not have this capability. Therefore, a modified model, using only fixed
resistors is needed.
This modified model is shown in Figure 5-7.
Here an extra
resistance, RShum, is added in parallel to the winding capacitance, C.
While this
resistance does not necessarily have any physical significance associated with the
inductor, it can dramatically improve the fit of the model to the measured data,
especially at high frequencies. This is shown in Figure 5-8 where the fit of Q for both
models, simple and modified, are shown. A good agreement between the measured
and modified model is apparent.
Figure 5-7. Modified small-signal model for
inductors on SOS.
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108
•
Measored
Modei
Simple Model
Modified Model
(nductai ice
1
10
Frequency (GHz)
Figure 5-8. Measured vs. modeled, inductance and
Q, for simple and modified inductor models.
The modified model was used to model all the inductors with various number
of turns. These models were later used in simulations of the circuits discussed in
Chapter 6. The parameter values of these models, along with analytical equations for
predicting them for an arbitrary number of turns, are given in Appendix B.
The
analytical equations are needed when an exact value of inductance, corresponding to a
not previously measured device, is required for a circuit. This equations may predict
an inductor with 3.25 turns in order to achieve a desired inductance. However, only
inductors with an even number of turn were fabricated for this experiment.
5.2.3.3 Improved Model
As mentioned before, the addition of R Shunt in the modified model can aid in the
fitting at higher frequencies, but is not necessarily physical.
Indeed, a better
understanding of the inductor, with regard to its frequency dependent resistance, is
necessary. To explore this, a microwave circuit simulator, HP/EEsof s LIBRA, was
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109
used.
This simulator has the capability of simulating skin effects in microstrip
transmission lines such as those used in the turns of an inductor by calculating the
frequency dependent resistance. Using this fact, a microstrip line (M L IN ) was used to
represent the resistance of the inductor in an improved model. This model is shown in
Figure 5-9.
munJFigure 5-9. Improved small-signal model for
inductors on SOS.
The incorporation of the microstrip line accounts for more than just the
frequency dependent resistance.
As mentioned at the onset of this chapter, any
conductor has a self-inductance given by (5.1). LIBRA take this into account such that
the self-inductance of the spiral is accounted for by the microstrip line. From (5.2) is
was noted that the total inductance of the inductor is the sum of its self and mutual
inductance. Therefore, only the mutual inductance, Lm, has to be added to the model.
Ln, is different from L in the simplified and modified models and can be estimated
from Greehouse’s formulae [4].
For the model, physical parameters of the microstrip line; width, length (the
total length of the spiral), and the resistivity (3.5 x 1C6 £2-cm), are all that need to be
specified to model the self-inductance and frequency dependent resistivity. The only
other parameter in the model that needs to be determined is the winding capacitance,
C.
This is best left as a fitting parameter and can quickly be determined by
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110
optimization routines within LIBRA. Figure 5-10 shows an example of the excellent
fit achievable with the improved model. Note that the quality factor is in excellent
agreement throughout the frequency range of interest.
L.
25
o
Mea sun d
Model
w
20
CB
3
O'
s
c:
o
u
s
ej
15
Iqdact! nee
10
5
ty Fa :tor
T3
C
0
0.1
10
Frequency (GHz)
Figure 5-10. M easured inductance ans Q vs. modified
model for an 8 turn inductor on SOS.
5.2.4 Comparison with Bulk Silicon and SOI
As stated before, the same inductors were fabricated on bulk silicon as a
comparison to inductors that would be fabricated in a bulk silicon process or SOI
process. The bulk silicon inductors were measured in the same way and the results for
an 8 turn inductor are shown in Figure 5-12 along with the same inductor fabricated on
SOS. The SOS inductor has a higher self-resonant frequency and a two fold increase
in the peak quality factor over the bulk silicon inductor. The self resonant frequency
and peak quality factor for various inductors are plotted versus inductance in Figure 512.
The SOS inductors have significantly better performance than the bulk silicon
inductors.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Ill
u
25
o
cs
£s«
20
A
3
O'
15
X
u
C
«
u
3
•O
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•
■
IVlcasu ■cd: iO i
ivicasui ced SC 1
““
Model
In d u ct; nee
10
5
Q uality Fa nor
0
0.1
10
Frequency (GHz)
Figure 5-11. Measured inductance and Q vs.
modified model for an 8 turn inductor on SOS and
bulk silicon.
25
. a J—
12peal;
20
JB
§L
15
SOS
N
X
10
5
0
4
6
8
10
12
Inductance (nH)
Figure 5-12. Self-resonant frequency and peak
quality factor for inductors with 5 pm width and 5
pm spacing.
The bulk silicon inductors were also modeled to better understand their loss
mechanisms.
Once again, the small-signal model had to be modified.
Using the
improved model with a transmission line, extra capacitance and resistance parameters
had to be added to account for capacitive coupling across the buried oxide to the
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112
conductive substrate and to account for resistive losses in the substrate. The model
used for the bulk silicon inductor is shown in Figure 5-13.
— I ML IN [
Figure 5-13. Improved small-signal model for
inductors on bulk silicon.
A comparison of the model and measured data, for both SOS and bulk silicon
inductors, is shown in Figure 5-11.
As in the SOS case, the model achieves an
excellent fit over the entire frequency range.
Table 5.4 summarizes, the inductor figures of merit and component values of
the modified model for 5 and 8 turn inductors on SOS and bulk silicon. We can see
from Table 5.4 that the parameter Lm does not change for the inductors on different
substrates. Over the frequency range studied the inductance (L) is only a function of
the number of turns, inner and outer radii of the spiral and the width and spacing of the
conductors [3,1]. The winding capacitance (C) is primarily dependent on the spacing
of the conductors. Note that the buried oxide capacitance Cox and substrate resistance
Rs are needed to accurately model the inductors on bulk silicon but are not necessary
for the SOS inductors. The substrate parameters Cox and Rs represent the capacitance
across the 1.7 pm thick insulating oxide and resistance associated with the conductive
silicon substrate.
For example, the area of a five turn spiral, including the under
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113
crossing is 14000 (im2. Using a simple parallel plate capacitor approximation (Cox =
eA/d) with d = 1.7 Jim yields a capacitance value of
284 fF.
This is in good
agreement with the value of 300 fF (2 x 150 fF) extracted for the model (see Table
5.4).
Due to current spreading, the substrate resistance is difficult to easily predict
with a simple expression like the capacitance.
Hence it is best left as a fitting
parameter in the optimization process. In general, as expected and as seen in Table
5.4, the substrate resistance decreases as the number of turns increases.
Table 5.4. Component values of the modified model
for various inductors on SOS and bulk silicon.
SUB!
Sapphire i
Sapphire i
Si
Si
i
l l i i
5
8
4.0
10.7
1 13.9 1
i 7.0
!
5
8
4.0
10.7
i
i
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3.4
i
i
11.9
9.9
3.6
3.0
2200 ! 1.3 1 35
4273 ! 5.4 ! 50
2200 \ 1.3 1 35
4273 ! 5.4 i 50
i
I
i
:
1 150 I 320
! 210 1 200
While the above discussion has centered around inductors that were made on
bulk silicon, Figure 5-14 compares the inductor fabricated on SOS with silicon
inductors recently reported [6, 9, 10, 11]. The SOS inductors are better than those
reported with the exception of the inductors reported by Lovelace [9] which utilize a
gold metalization to decrease the resistance and increase Q.
While this may work,
gold metalization is not considered a standard process for silicon technologies.
Therefore, our inductors remain the best reported inductors which utilize a standard
CMOS metalization process.
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114
30
•
25
a
O
a
te.
♦
■
20
1
SOS
I
A shby, et. a l„ A T & T
Lovelace, M oto ro la
Nguyen, e t a t , UC Berekelj
Yue, et a t , S tanford
10
100
Inductance (nH )
Figure 5-14. Comparison of recently reported
inductors on silicon.
5.3 Metal-Insulator-Metal Capacitors
Metal-insulator-metal (M IM ) capacitors are needed for impedance matching,
filtering and for power supply by-pass in microwave circuits. The capacitance of these
capacitors is given to a very good approximation by the simple expression C = eA/d
where e is the dielectric constant of the insulator, A is the area of the metal plates and
d is the thickness of the dielectric. In order to minimize die area, these capacitors need
to have a large capacitance per unit area, typically on the order of 0.2-0.3 fF/|im2. This
can be accomplished in two ways: 1) by reducing the thickness of the dielectric or 2)
by using a dielectric with a high dielectric constant. In our process using 1000 A thick
SiCh as a dielectric, capacitors with 0.35 fF/pm2 were achieved.
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115
5.3.1 Processing
M IM capacitors were fabricated using S i02 as the insulating dielectric. This
was chosen for process simplicity and due to an inability to deposit other dielectrics
such as the commonly used silicon nitride (SisN.*). To incorporate the capacitors into
the standard process, one additional mask step was added.
The process sequence,
along with that used for forming metal 1 to metal 2 interconnects (vias), is shown in
Figure 5-15. The first step (Figure 5 -15a) is to put down metal 1 and the interlevel
dielectric (ILD). This forms the first level interconnect and the bottom plate of the
capacitor. Next the additional capacitor mask is used to etch the ILD and define the
M IM capacitor (Figure 5 -15b).
Next the capacitor dielectric (S i0 2) is deposited
followed by a photolithography and etch step to form vias by removing the capacitor
dielectric and ELD to expose metal 1 (Figure 5 - 15c). Finally the second level metal is
deposited to form the top plate o f the capacitor and complete the metal 1 to metal 2
interconnection (Figure 5-15d).
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116
Metal 1 - Metal 2 Via
C a p a c ito r
Oxide
Metal 1^
Capacitor
Mask
(b)
Capacitor Oxide
Via Mask
(c)
Figure 5-15. MIM capacitor and metal 1 to metal 2
via process sequence.
The capacitors were laid out for on-wafer probing with ground-signal-ground
microwave probes. Figure 5-16 shows a schematic top view of an M IM capacitor and
Figure 5 -17 shows a photograph of a fabricated capacitor with dimensions of 200 pm
x 200 pm.
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117
Capacitor Mask
Metal 1
Metal 2
Figure 5-16. Layout of the MIM capacitor.
Figure 5-17. Photograph of a fabricated MIM
capacitor (200 pm x 200 pm).
Since only SiO; with a low dielectric constant could be deposited for the
capacitor dielectric, the thickness had to be reduced as much as possible. However,
the quality of deposited oxide is typically much poorer than thermally grown oxide.
As a result when the oxide thickness is reduced too much, pinholes in the oxide can
lead to shorting between the plates of the capacitors. Also, the deposition rate of the
oxide is also hard to control. A target thickness of 1500 A may have an error of ±100
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118
A (a 6.6% error). However, if the oxide thickness is scaled down to 500 A. to increase
capacitance per unit area, an error of ±100
A can
lead to a 20% error in capacitance
value. Therefore, it is critical to deposit a high quality, high uniformity oxide for use
in these capacitors. To study our oxide quality, four oxide thicknesses (2000 A. 1500
A. 1000 A. 500
A)
were deposited on different wafers. Results are summarized in the
following section.
5.3.2 Microwave Characteristics
The capacitors of various areas and oxide thickness were measured on an
HP8510B network analyzer from 0.2 GHz to 20 GHz in 0.2 GHz steps.
The S-
parameter data was de-embedded to remove pad parasitics as described in Appendix
A. By converting the S-parameters to Y-parameters. the capacitance can be extracted
from Y = jcoC. Figure 5-18 shows the measured admittance of two square capacitors
with 25 pm and 50 pm sides. It also show's the results of these capacitors fabricated
on two different wafers with 1000
A and 1500 A thick oxides.
.As seen from Figure 5-
18. the measured data remains very linear over a wide range of frequencies.
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119
OJ
*
*
—
0 .0 8
M easured (tux = 1500a )
M easured (tux = 1000AI
M odel
0 .0 6
50 pm x 50 pm
0 .0 4
<
0
6
4
8
10
12
14
16
18
20
Frequency (GHz)
Figure 5-18. Admittance (yu ) of four capacitors with
different are and oxide thickness.
The extracted values of capacitance, from Y = jtoC. are shown in Figure 5-19.
.As mentioned ai the beginning of this section, these values correspond to capacitance
per unit area values of 0.25 fF/urrf and 0.55 fF/um2 for the 1500 A and 1000 A thick
films respectively.
1C
M e a s u re d i t era = 150 0 .A )
i
•
M e a s u re d (to x = 1 0 0 0 A H
M odel
50 pm x 50 pm
0.8
0.6
0 .4
25pm x 251pm
A
OC
0
0
2
4
6
g
10
12
14
16
18
20
Frequency (GHz)
Figure 5-19. Capacitance of four capacitors with
different areas and oxide thickness.
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120
Capacitors with 500 A thick oxide were also fabricated but measurements
revealed that most of the capacitors were shorted due to poor oxide quality. Therefore,
for the circuits described in Chapter 6. an oxide thickness of 1000 A was used.
5.4 Thin Film Resistors
Thin film resistors are needed in circuits for a variety of applications such as
loads and for termination. Thin film resistors typically have sheet resistance values of
50 Q/L. The resistors implemented in SOS correspond to sheet resistances around 65
Of— These resistors were used to design circuits operating at microwave frequencies
as described in Chapter 6.
5.4.1 Processing
Unsilicided gate polysilicon was used for the thin film resistors.
polysilicon typically has resistance on the order of 60-80 Q /_.
This
As described in
Chapter 3 in the section on FET processing, after silicidation this resistance drops to
around 1-2 £2/_. For use as resistors, it is necessary to prevent the polysilicon from
being silicided.
Thin-film resistors are defined at the same time as the FET gates with the
polvsilicon gaie mask Figure 5-20a. However, they differ from a FET in that there is
no silicon island below the polvsilicon so the resistors are fabricated directly on top of
the sapphire substrate.
SiO; sidewalls used for self-aligned silicide are normally
formed without a photolithography step.
However, to implement the thin film
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121
resistors, an additional mask was used prior to sidewall formation. After deposition of
the SiC>2 , a mask was used to cover the thin film resistors (Figure 5-20b). By doing
this, the SiC>2 above the polysilicon thin-film resistor will remain after the formation of
the SiC> 2 sidewalls (Figure 5-20c) and hence won't be silicided during the silicide
formation (Figure 5-20d).
Resistor
■■■■ ■*-
T ra n sisto r
Gate Mask
Polvsilicon
Resistor Mask
Oxide
Silicide
Figure 5-20. Thin-film resistor process sequence.
A top view of a thin-film resistor layout is shown in Figure 5-21. The resistor
has a “dogbone” shape in order to realize the minimum design rules of contact opening
for metal 1. Also note that the resistor mask does not cover the contact regions so that
these regions will be silicided and thus have low contact resistance.
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122
Polysilicon
\
Resistor Mask
/
Contact opening for Metal 1
Figure 5-21. M ask layout of a thin-film resistor.
For test purposes, a number a resistors with varying width and length, along
with chains of resistors, were fabricated.
Figure 5-22 shows a portion of the test
pattern used for the resistors. The 15, 20, and 100 square resistors have a width of 2
(ims, while the 2, 3, and 4 square resistors have a width of 5 (ims. At the right of the
test cell, a pattern with 50 resistors in series was implemented to check the contact
from metal 1 to the resistor layer.
Figure 5-22. Photograph of test patterns for thin-film resistors.
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123
5.4.2 DC Characteristics
As previously mentioned, for process verification, a variety of thin-film
resistors with different widths and lengths were laid out. The thin-film resistors were
measured to determine the sheet resistance value and process uniformity. Figure 5-23
shows a typical plot of resistor current vs. voltage for nine resistors of various lengths
and widths in the same field of the wafer.
2
i
o
i
-2
-0 .5
-0 .2 5
0
0 .2 5
0 .5
Voltage (V)
Figure 5-23. Current-Voltage characteristics of nine
resistor of various lengths and widths.
The slope of the lines in Figure 5-23 and nominal resistor dimensions can be
used to determine the sheet resistance of the thin-film in ohms per square (£2/L).
Figure 5-24 shows the sheet resistance of the same nine resistors.
The mean and
standard deviation of the sheet resistance were 67 and 0.8 Q/L_.
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124
70
□
a
«
A
I
V
M
y
v
W
/v
/\iW
V
\J
69
68
If'"'-
o
E
2
67
fifi
66
u
u
■
E
c/3
’— |T
I
w v-
IT
I
a/V\A v V
t
-
- j w r v r
\ -y—
i
65
•
64
-0 .5
-0 .2 5
0
0 .2 5
0 .5
Voltage (V)
Figure 5-24. Sheet resistance of nine resistors of
various lengths and widths.
While Figure 5-24 shows the sheet resistance of resistors in a single field, in
order to accurately set bias point and maintain proper voltages within a circuit,
resistance values need to be accurately controlled. Figure 5-25 shows a wafer map of
sheet resistance values for a typical SOS wafer. The mean and standard deviation are
61.8 and 4.3 Q/L respectively. As can be seen from Figure 5-25, the resistance tends to
be slightly large at the center of the wafer.
This variation comes about from
differences in the polysilicon film thickness and doping non-uniformities. As for the
contact to the resistors, the test pattern with 50 resistors in series had excellent yield
above 96%.
This is expected since the contact to the resistors is identical to the
contact to the gate of a FET.
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125
Figure 5-25. W afer map of resistor sheet resistance.
The variation in the resistance across the wafer can be improved upon by using
a dedicated thin-film resistor layer such as NiCr or TaN.
However, this would add
many more steps (and cost) to the process sequence as opposed to the one additional
lithography step used here.
Furthermore, the resistance non-uniformity is not so
significant as to drastically affect yield of the circuits discussed in Chapter 6.
5.5 Conclusion
Inductors, metal-insulator-metal capacitors, and thin-film resistors have been
designed and fabricated on SOS.
The inductors showed excellent microwave
characteristics with high self-resonant frequencies and good quality factors.
The
capacitors and resistors performed as expected but care must be taken in processing to
ensure film thickness uniformity across the wafer (and lot) for both to avoid errors in
their respective values.
In general, the passive elements designed here meet the
requirements for circuits operating at microwave frequencies.
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126
5.6 References
1. H .A Wheeler, “Simple Inductance Formulas for Radio Coils,” Proceedings o f the
Institute o f Radio Engineers, XVT, Oct. 1928.
2. F. E. Terman, Radio Engineers’ Handbook, New Your, McGraw-Hill, Inc. 1943.
3. F.S. Burkett, Jr., “Improved Designs for Thin Film inductors,” Proceddings o f the
1971 Electronic Components Conference, Washington, D.C. 1971.
4. H. M . Greenhouse, "Design of Planar Rectangular Microelectronic Inductors,"
IEEE Transactions on Parts, Hybrids and Packaging, vol. PHP-10, no. 2, pp. 101109, June 1974.
5. R .M . Warner and J.N. Fordemwalt, Eds., Integrated Circuits, Design Principals
and Fabrication, New York, McGraw-Hill, 19675, p. 267.
6. N .M . Nguyen, R.G. Meyer, “Si IC-Compatible Inductors and LC Passive Filters,”
IEEE Journal o f Solid-State Circuits, vol. 25, no. 4, Aug. 1990.
7. J. Y. -C. Chang, et al, "Large Suspended Inductors on Silicon and Their Use in a 2pm CMOS RF Amplifier," IEEE Electron Device Letters, vol. 14, no. 5, pp. 246248, May 1993.
8. C. -Y. Chi, G.M. Rebeiz, "Planar Millimeter-Wave Microstrip Lumped Elements
Using Micro-Machining Techniques," / 994 IEEE MTT-S Digest, pp. 657-660.
9. D. Lovelace, et al, "Silicon M M IC Inductor Modeling for High Volume, Low Cost
Applications", Microwave Journal, p. 60, Aug. 1994.
10. K. B. Ashby, et al, "High Q Inductors for Wireless Applications In a
Complementary Silicon Bipolar Process," 1994 Bipolar/BiCMOS Circuits and
Technology Meeting, pp. 179-182.
11. C.P. Yue, C. Ryu, J. Lau, T.H. Lee, S. Wong, “A Physical Model for Planar Spiral
Inductors on Silicon,” 1996 International Electron Devices M eeting Technical
Digest, San Francisco, CA, Dec. 1996.
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6. Microwave Circuits
6.1 Introduction
By combining ail of the elements described in previous chapters, the use of
silicon-on-sapphire
investigated.
for
circuits
operating at
microwave
frequencies
can
be
To do this, we chose to develop basic building block circuits of a
transmitter / receiver (transceiver) operating at 2.4 GHz.
This frequency has been
allocated by the FCC for industrial, scientific, and medial research (ISM ).
After a brief discussion of system requirements for wireless systems such as a
transceiver,
this
chapter
discusses
the
design,
simulation,
fabrication
and
characterization of these circuit blocks which include a low noise amplifier, mixer,
transmit / receive switch, power amplifier, and distributed amplifier.
6.2 System Requirements
For wireless communications, a double down conversion superheterodyne
receive architecture is commonly used. A typical representation of this is shown in
Figure 6-1. From left to right, the elements are: antenna, band pass filter, low noise
amplifier, band pass filter, first (RF) mixer, band pass filter, amplifier, second (IF)
mixer, band pass filter, amplifier, and analog to digital converter.
Subsequently
baseband digital processing is carried out to extract the signal.
127
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128
RF Mixer
3°
OO
OO
oo
LNA
IF Mixer
00
CV
Oo
OO
AMP
LOl
oo
AMP
ADC
B a se ba n d
DSP
L02
Figure 6-1. Typical super-heterodyne receiver architecture.
For such an architecture, as used in IS-55 (digital dual-mode cellular
telephone), there are certain specifications (noise figure, gain, input IP3, etc.) that
typically emerge for each element in the receive chain. Table 6.1 gives representative
specifications for the LNA, and RF and IF mixers in this system.
Table 6.1. Representative system requirements for IS-55 receive components.
Signal Level (dBm)
-109.5
-107
Noise Figure (dB)
Although Table 6.1 indicates specific requirements for each block in the chain, there is
flexibility associated with these values according to the design. A critical specification
is the overall system noise figure, usually between 7 and 8 dB.
The overall noise
figure of a system is given by
F = F , + - ^ - + — ^ — + --------^ --------- + ••• + ----------- £ -----------
1 G,
G .-G ,
G , G 2 G3
G, ■G2 •• • G„_,
(6.1)
where F|, and G| are the noise and gain of the first block, Ft and Gi are the noise and
gain of the second block, and so on. Hence, the noise figure of the later stages in the
chain are less significant provided the gain of the previous stages are high enough.
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129
Hence, the overall system noise figure is dominated by the first LNA. So long as the
system noise figure remains within spec, the system designer is free to set noise figure
and gain requirements of each block as he sees Fit and according to what components
are available.
A block diagram of a transmit chain is shown in Figure 6-2.
After digital
signal processing at baseband, the digital signal is then converted to an analog signal,
and then up-converted to RF with the use of a mixer. Finally, the signal is amplifier
by a power amplifier before being sent to the antenna. Typical output power required
by the power amplifier are around 1 watt (30 dBm).
Upconvcrsion
M ix e r
B a se ba n d
DSP
DAC
PA
LO
Figure 6-2. Typical transm it architecture.
In general, the transmit chain is much simpler than the receive chain in that the
many filters for removal of image frequencies are not needed. However, the power
amplifier imposes other strict requirements like high output power, high linearity, and
high efficiency. These requirements can be difficult to address in many technologies.
6.3 System Characterization
Before discussing the circuits in detail, a definition of their figures of merit and
measurement techniques will be discussed.
These include two-tone linearity
measurements and noise figure measurements.
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130
6.3.1 Two-tone Linearity Characterization
One of the most useful characterization techniques for communication circuits
is the two-tone linearity measurement.
For this measurement, two high frequency
signals (fi and / 2) are input to the circuit. As a result of nonlinear distortion, these
single tones are output as a series of harmonics at frequencies given by m/i + n/2 where
m and n may be positive or negative integers. The order of the nonlinearity is defined
as Iml + Ini. Most harmonics are generally far from the fundamentals/ , a n d /2 and can
easily be removed by filtering, however, some third-order harmonics such as 2/i - / 2
and 2fz - f \ lie very close to the fundamentals and cannot be filtered even in a narrow­
band system.
These third-order two-tone are know as intermodulation products
resulting from the mixing of the two input signals. They are very important because
they may determine the dynamic range or bandwidth of the system.
A typical setup for a two-tone measurement is shown in Figure 6-3. It utilizes
two signal sources and a spectrum analyzer for determining the power levels of the
output harmonics. To calibrate the system, a “thru” is inserted in place of the device
under test (DUT).
The allows the losses in the lines, and in the case of on-wafer
probing as used for the circuits, the losses of the probes, to be eliminated from the
measurements.
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131
Source 1
C o u p le r
Source 2
DUT
Spectrum
Analyzer
Figure 6-3. Setup for two-tone measurements.
A typical output power vs. input power (on a dB scale) for a receiver circuit is
shown in Figure 6-4. Here we see the fundamental (Po) rising with a slope of one until
the system begins to saturate and the output power rolls off due to clipping of the
output waveform and signal distortion. This distortion manifests itself by diverting
part of the input power to the various harmonics. From Po we can determine the gain
(or loss) of the system. We also see the third order intermodulation distortion product
(P 3 ). As expected this has a much steeper slope than the fundamental, rising at a slope
of three. The point at which the Po and P3 intersect is know as the third order intercept
point (EP3) and can be input referred (IIP3) or output referred (OIP3) a shown in
Figure 6-4. The dynamic range of the system can also be determined from Figure 6-4
and is basically the range from the third-order intercept point to the noise floor.
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60
T h ir t f o r d c r in t e r c e p t* ^
40
s 20
5 o
£ .
-4 0
§ , -6 0
B
-80
-100
Dynam ic Range
N o is e F lo o r
-120
-7 0 -6 0
-50
-40
-30
-20
-10
0
10
20
30
Inpat Power (dBm)
Figure 6-4. Output power vs. input power for a
typical two-tone test.
6.3.2 Noise Characterization
In addition to quantifying the linearity' of each building-block circuit, it is also
important to know how much noise it introduces to the signal desired signal level. The
noise factor is defined as the ratio of the total output noise power of an amplifier to the
output noise power due to the source alone. The noise figure is simply ten time the
logarithm (base 10) of the noise factor. Hence, as the noise is increased, the dynamic
range is reduced and it becomes harder and harder to distinguish the desired signal
from unwanted signals input into the receiver.
To characterize the noise contribution of the system, a noise figure meter is
used, in this case an Hewlett-Packard 8970A. This setup utilizes a noise source and
the noise figure meter as shown in Figure 6-5.
The noise figure meter works by
injecting a noise signal of known power and frequency and then measuring the
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
respective total output noise power. Hence the noise factor (total output noise power /
input noise power ) can be computed.
As before, the system is calibrated on a thru and then the D U T is measured.
The automatic noise figure meter does all the work by measuring both the gain and
noise figure of the system. Typical accuracies of the system are within a few tenths of
a dB.
Noise
Source
DUT
Noise
Figure
M eter
Figure 6-5. Setup for measuring system noise.
6.4 Low Noise Amplifier
.An important element of a receive chain is the low noise amplifier (LNA) used
to amplify- the small input signal from the antenna. Since this is one of the first blocks
of the receiver its performance is critical in establishing the overall dynamic range. It
must have very low noise as well as high gain and high input third-order intercept
point (DP3).
Figure 6-6 shows the circuit schematic of the single-stage common-source
LNA used in this work. Spiral inductors were used to match the FETs to the minimum
noise figure at
ropt.
By inserting an inductor in the source leg. a smaller value of input
inductance can be used to achieve a given input impedance. This saves the valuable
real-estate needed by a larger inductor and allows the low inductance to be more easily
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154
realized. M IM capacitors were also used for matching at the output as well as for
bypass on the power supply lines.
out
m
Figure 6-6. Schematic of the single stage low noise
amplifier.
The circuit was laid out for on-wafer probing with 100 pm pitch coplanar
ground-signal-ground microwave probes for input and output and with built in bias
tees for the gate and drain biases. A photograph of the fabricated amplifier is shown in
Figure 6-7. Dimensions of the chip are 1.3 mm x 0.95 mm.
Figure 6-7. Photograph of the fabricated low noise amplifier
(Die Size: 13 mm x 0.95 mm).
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135
6.4.1 Simulations
Circuit simulations were carried out using HP/EEsofs LIBRA to determine the
optimal gate width of the MOSFETs and the value of the matching components.
Values of the circuit parameter are given in Table 6.2. For the simulations, raw 2-port
s-parameter data was used for the FETs. A gate length of 0.5 pm and gate width of
400 pm (8 x 25 pm fingers) was used for the FET. In representative designs, a wider
FET leads to lower channel resistance and lower noise.
However, as the device is
made larger, its becomes more difficult to match (requiring large inductance and
capacitance values) and also consumes more DC power.
Table 6.2. Circuit element values for the LNA.
0.5
400
|
14.8
4.4
40
0.3
2.6
12
60
The simulated results of the LNA operating at 2.4 GHz are tabulated in Table
6.3. These results were obtained at a bias condition around 40 mA and predict a 2.2
dB noise figure with over 11 dB gain.
Table 6.3. Simulated performance of the LNA.
1 M
M
2.2
I
stamm
11.2
-9.1
-11.5
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136
6.4.2 Measured Results
The LN A was measured with an HP8510B Network Analyzer from 1 to 5
GHz. The gain (S2 1 ) and matching (Sn, S2 2 ) of the amplifier versus frequency (at V DS
= 1.5, Vgs = 0.7 V, Ids = 8.5 mA) are shown in Figure 6-8. The LNA was found to
operate well even at low drain currents much smaller than predicted in the initial
design. This is beneficial in order to attain low power dissipation. The gain of the
LN A (at 2.4 GHz) was 10 dB. Furthermore, the LN A is well matched at 2.4 GHz
using the spiral inductors as observed by Sn and S2 2 - The output matching (S2 2 ) is
optimal at a frequency slightly lower than expected, around 2.1 GHz. However, it
should be noted that the input and output matching were optimized to yield low noise
figure and not necessarily match for gain to 50 £2. In general, the two conditions:
matching for gain and matching for noise do not necessarily require the same
impedance matching networks.
Gain (S21)
a
’3
O
-10
-1 5
•20
1
2
3
4
5
Frequency (GHz)
Figure 6*8. Measured gain and matching of the LNA.
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137
The noise figure was measured on an HP 8790A noise figure meter at 2.4 GHz.
At a bias of V ds = I V, V gs = 2 V, IDS = 3.5 mA, the measured noise figure was 2.8 dB
with an associated gain of 9.5 dB.
These results are in good agreement with
simulations which predicted 2.2 dB noise figure and 11 dB gain. This represent a
roughly 10% error in noise figure and gain.
Two-tone (/) - 2.4 GHz , / 2 = 2.425 GHz) measurements were performed at V DS
= 1.5 V, Vgs = 0.7 V , Ids = 8.5 mA and are shown in Figure 6-9. The LN A remained
linear for a wide range of input power and has a third-order intercept point of 16.5
dBm. This corresponds to a EP3 to Pdc ratio of 6.4. The ldB compression point of the
fundamental was unobservable due to test set limitations.
.
r
/ , = 2.400 G H z
/ j = 2.425 G H z
-2 0
£
-40
■g
-6 0
=
-80
a.
-100
•120
-70
-50
-40
-30
-20
-10
0
10
Input Power (dBm)
Figure 6-9. Power transfer characteristics of the LNA
( V ds = 1.5 V, VGs = 0.7 V, IDS = 8.5 mA).
6.4.3 Comparison to Other Technologies
Figure 6-10 shows the gain to DC power dissipation ratio for LN A of different
technologies [1, 2, 3, 4, 5, 6, 7],
Figure 6-11 plots the input referred third order
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138
intercept point (HP3). This is a linearity figure of merit for all amplifiers. All data in
Figure 6-10 and Figure 6-11 are at 2 GHz unless otherwise indicated. As expected, the
m -V LNAs have lower noise figure than the silicon LNAs. The SOS CMOS L N A has
about the same performance of the bulk silicon CMOS LNAs but is operating at
almost 2.5 times higher frequency.
SiGe HBT
£
=
ea
•o
GaA; HBT
G a A c M F .S F F T
I
>
Si BJT •
GaAs 4ESFET
C3
S i' rM OS
u
tom M H j I
Si B JT'
0.5
1.5
sosc MOS®
(2.4 C Hz)
2
2.5
3.5
Noise Figure (dB)
Figure 6-10. LNA Gain to DC Power ratio versus
noise figure for different technologies.
OS CMOS
■ s (2.4 GHz)
1.5
E
s
a
s
0.5
GaAs HBT
_ g <
tt"BJT "
• SiG< HBT
# GaAs 1UESFET G aAsMESFE T
•
(1.1 GHz)
10
15
si a lO S
(9001 4 Hz)
)■■■ - 1 ■
20
25
DC Power (raW)
Figure 6-11. LNA linearity versus DC power
dissipation for different technologies.
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139
Besides work in H I-V technologies, there has been a lot of work on CMOS
LNAs. In [8], Shaeffer gives an excellent summary of CMOS LNA performances to
date. Table 6.4 summarizes these recently reported LN A results. The LNAs with 20
dB or more gain are multistage LNAs unlike our single stage design. These LNAs
typically have increased power dissipation but both exhibit good noise figures. This is
due to the fact that by increasing the current, the transconductance will increase and
the optimum source impedance will decrease. Moreover, the high IP3 achieved in this
work can be attributed to low drain-source capacitance in the FETs and the absence of
the body effect in the SOS devices.
Table 6.4. Summary of recent CMOS LNA results.
H E P S fp n f
ggggf
ip R w m
m
This Work
0.5
2.4
10
2.8
Chang [9]
2
0.75
14
6.0
Karanicolas [1]
0.5
0.9
15.6
2.2
Sheng [10]
1
0.9
11
7.5
Shaeffer [8]
0.6
1.5
22
3.5
lliliil
14
-
12.4
-
12.7
g g g
4
Ifa lilll
4
-
-
-3.2
-
-
-
-9.3
0
14
7
20
36
30
With decreased gate lengths, comparable to those used by GaAs MESFET, the
SOS LN A gain to DC power ratio should improve. Since the design of an LN A is
strongly influence by the source resistance [11] it is necessary to reduce the source
resistance of the FET. Furthermore, the performance to cost ratio should be better for
the SOS due to the more inexpensive material and processing techniques required for
m -V based LNAs.
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140
6.5 Mixer
Another important component of any transceiver is the mixer used in up and
down conversion of the carrier (radio) frequency (RF) to the intermediate frequency
(IF). It is important for the mixer to have good isolation between the local oscillator
(LO) and RF as well as high IP3 and low noise figure. For our work we chose a mixer
topology shown in Figure 6-12. As opposed to a Gilbert cell mixer with high gain and
usually poor EP3, our design targets high IP3 with little or no gain. This is a viable
tradeoff in that it is easier to increase gain in the receiver chain (such as in the
following amplifier) than to increase IP3. For good LO and RF isolation, a doublybalanced configuration was chosen. The mixer uses a single transistor with LO fed
into the gate and RF fed into the source. The parallel RC network was used to further
reduce the LO and RF feed-through by low-pass filtering the IF output.
~ ~ j|
O
LO'1
— 1|—© R F
Figure 6-12. Schematic of the mixer.
The mixer was laid out for on-wafer probing with 150 pm pitch signal-groundsignal microwave probes for the RF, LO and IF inputs and with 150 pm pitch needle
probes for the DC power supplies. The DC bias of the RF and LO are done externally
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141
with bias tees. Figure 6-13 shows a photograph of the fabricated mixer. The chip
dimensions are 1.2 mm x 0.875 mm.
Figure 6-13. Photograph of the fabricated mixer
(Die Size: 1.2 mm x 0.875 mm).
6.5.1 Simulations
Spice simulations of the mixer were done with the carrier frequency at 2.4 GHz
and the LO frequency at 2.15 GHz. This corresponds to a 250 M H z EF frequency.
Figure 6-14 shows the simulated IF output voltage of the mixer. The period is 4 nS
corresponding to a 250 M H z signal as expected. A slight LO and RF feed through can
be observed superimposed on the EF sine wave.
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142
•40
-60
5
7
9
11
13
IS
Tim e (nS)
Figure 6-14. Simulated results of the mixer.
6.5.2 Measured Results
Two-tone
(/rfi
= 2.4 G H z , / r f 2 = 2.41 GHz) power transfer characteristics for
the mixer are shown in Figure 6-15. The local oscillator (LO) frequency and power
were 2.15 GHz and 0.7 dBm respectively corresponding to a 250 M H z IF.
At a
representative bias condition of V d d = 1.2 V and Iqd = 7 mA (including output source
followers) the total DC power dissipation (P d c ) was 8.4 mW. At the same time, the
fundamental power Po remains linear over a wide range of input power, leading to a
high input IP3 of 5 dBm.
This compares well with the IS-55 specification given
earlier. The mixer has about 5 dB conversion loss (consistent with its design to favor
high IP3 at the expense of gain).
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143
/i = 2.400 GHz
f 2 = 2.425 GHz
£
CO
•a
ra>
£
0
01
-2o
-40
-80
-70
-60
-50
-40
-30
-20
-10
0
10
20
Tnput Power (dBm)
Figure 6-15. Measured two-tone power transfer
characteristics of the mixer.
6.5.3 Comparison to Other Technologies
Through the use of SOS technology, the non-linearity of the substrate coupling
and body effect typical of bulk CMOS can be greatly reduced. This prevents LO and
RF signals from feeding through to the IF, as well as minimizing nonlinear distortion.
Further, due to the h ig h /t of our PMOS devices, current reuse schemes [12] can be
used to increase mixer performance. A summary of recently reported CMOS mixers
are shown in Table 6.5. The SOS mixer compares favorably, particularly with respect
to its high HP3 to DC power ratio and high frequency of operation.
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144
Table 6.5. Summary of recently reported CMOS mixers.
2000
250
-
-5
5
14
Gilbert
860
100
8
10.5
-4
25
-
Folded
Gilbert
900
100
6.7
8.8
-6
-
0
Gilbert
1900
250
10
0.5
-6
8.5
-8
«
o
-
1
1
0.5 pm
SOS
2 pm
CMOS
0.8 pm
CMOS
0.8 pm
CMOS
As mentioned earlier, the mixing function is controlled by the LO feeding the
gate resulting in a time-varying transconductance. Hence, the transconductance of the
MOSFET, including its linearity is of extreme importance. While SOS MOSFETs,
have lower transconductance, due to decreased mobilities, than bulk silicon and other
SOI technologies (as well as EH-V based FETs), the SOS mixer benefits from the
decreased parasitic capacitances allowing higher frequency of operation (compared to
bulk or SOI CMOS technologies). To further improve our mixer performance, devices
with increased transconductance should be realized.
This is possible by simply
decreasing the gate oxide thickness or by scaling the gate length to even smaller
dimensions.
6.6 Transmit/Receive Switch
A transmit / receive (TR) switch is needed in transceiver applications to
connect the antenna to the receiver chain (receive mode) or the transmit chain
(transmit mode). It is important for the switch to have very low insertion loss to not
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degrade the signal to noise ratio prior to the low noise amplifier on the receive side, or
reduce efficiency on the transmit side. At the same time, it is important for the switch
to have high isolation from one side to the other. When transmitting, usually at high
powers, it is important that the high power signal is well isolated from the receiver
chain since a very high signal level could damage the receiver's LN A or other
circuitry. Also since the incoming signal is typically very small, care must be taken to
ensure that it reaches the receiver circuitry and is not lost to the transmit side.
In most cases, this switch is a single-pole double throw (SPDT) switch. Figure
6-16 shows the circuit schematic of the SPDT switch which uses a combination of
series and shunt switch n-MOSFETs in each leg.
In transmit mode, when the
transistor ( M l ) from transmitter to antenna is turned on and the transistor (M 3) from
the antenna to the receiver is turned off. At the same time, the transistor ( M l) from
the transmitter to ground is turned off and the transistor (M 4) from the receiver to
ground is turned on. In this way. any signal that leaks through M3 will be shunted to
ground rather than coupling to the receiver input.
This targets the high isolation
specification of the switch. Since the switch is symmetric, the receive mode operates
in the same fashion but with opposite transistors turned on. DC voltages of 3.3 volts
are used to control the switch state. 1 KX2 resistors were inserted in the gate lines to
minimize signals being injected through the gate-source capacitance Cg* of the
transistors.
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14-6
■Antenna
T ransm itter
M2
M3
Receiver
XJMl
M4
' RX
Figure 6-16. Schematic of the transmit/receive switch.
The circuit was laid out for on-wafer probing with 100 pm pitch coplanar
ground-signal-ground microwave probes for the RF signals and 150 um pitch needle
probes for the two control the DC voltages enabling transmit and receive modes. A
photograph of the fabricated switch is shown in Figure 6-17. Dimensions of the chip
are 1.2 mm x 0.55 mm.
Figure 6-17. Photograph of the fabricated transmit/receive switch
(Die Size: 1.2 mm x 0.55 mm).
6.6.1 Simulations
Circuit simulations were carried out using HP/EEsof s LIBRA to determine the
optimal gaie width of the MOSFETs so that the circuit would have minimum insertion
loss and maximum isolation between transminer and receiver. For the simulations.
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measured 2-port S-parameter data was used for the FETs.
The circuit was left
unmatched to retain broadband operation and to save circuit area that would have been
used by on-chip inductors: despite this, it attains high performance.
Figure 6-18 shows the simulated (as well as measured) insertion loss and
isolation for the switch with gate widths of 300 pm for the FETs. This gate width
provided the optimum combination of lowest insertion loss and highest isolation. The
good agreement of the simulated and measured insertion loss was expected because
this factor is mostly a result of losses in the MOSFET.
-1 0
308754
sc
at
-3 0
Measured
s rmnhrtwf
-10
1*
-5 0
ZS
?
15
Frequency <GHzi
Figure 6-18. Simulated and measured insertion loss
and isolation o f tbe transmit/receive switch.
The discrepancy in the simulaied and measured isolation is due to the fact the
coupling between the FETs and transmission lines used in tbe circuit were not taken
into account during the simulation. This was done to simplify the simulation, in tbe
expectation thai the isolation would still be acceptable in the measured circuit.
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148
6.6.2 Measured Results
As a comparison to other SOI technologies, the switch was fabricated on by
SOS and SIM O X. The switches were measured on an HP8510 network analyzer from
1 to 5 GHz with and input power of 0 dBm. Figure 6-19 shows the insertion loss and
the isolation of the switches as a function of frequency. At 2.4 GHz. the SOS switch
had an insertion loss around 1.7 dB and an isolation greater than 30 dB. At 5 GHz the
insertion loss dropped to only 2.0 dB and the isolation remained greater than 25 dB.
On the other hand, the insertion loss and isolation of the same switch fabricated on
SIM O X were 4.9 dB and 36 dB at 2.4 GHz and considerably worse. 6.2 dB and 33 dB.
at 5 GHz.
-10
-20
-30
u
i.
sc
SOS
-to
S IM O X
1
1.5
4
4.5
-50
Frequency (GHz)
Figure 6-19. Comparison of measured insertion loss
and isolation of the transmit/receive switch
fabricated on SOS and SIMOX.
The differences in the insertion loss and isolation can be explained as follows.
Due to the capacitive coupling to the substrate in the transmission lines and MOSFETs
(see Appendices A and B). part of the signal is shunted to ground causing the insertion
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149
loss to increase.
At the same time, this coupling helps the isolation by shunting
unwanted signals to ground (in addition to the shunt transistors M l and M 4). While
the higher isolation is desirable, the dramatic increase in the insertion loss is
unacceptable for a transceiver application.
Since the isolation requirements of a switch are typically around 20 dB. the
insertion loss can be further improved, at the expense of isolation, by increasing the
gate width of the devices.
Also, without chip area constraints, spiral inductor and
capacitors would be used to match the switch to a specific frequency further
decreasing the insertion loss.
Two tone measurements (/i = 2.4 GHz, /> = 2.425 GHz) were carried out to
determine the linearity of the SOS switch. The power transfer characteristics of the
switch in transmit and receive mode (the same since the switch is symmetric) are
shown in Figure 6-20.
The fundamental power (Po) in Figure 6-20 shows that the
switch remains linear over a wide range of operation up to almost 20 dBm. The 3rd
order intercept point (IP3), extrapolated from the lowest intermodulation distortion
data (P 3 ), was around 18 dBm.
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150
/ , = 2.400 GHz
— f 2 = 2.42S GHz
-20
f t -40
•60
-80
-40
1IP3
-30
-20
-10
0
10
Input Power (dBm)
Figure 6-20. Measured power characteristics of the
transmit/receive switch.
6.6.3 Comparison to Other Technologies
A summary of switch performance attained in other IC technologies is shown
in Table 6.6. The SOS switch fabricated here is on the order of those reported in GaAs
MESFET technologies.
Despite a slight performance advantage of other
ni-V
technologies (stewing from higher electron mobilities which in turn allows lower onresistance), as mentioned before, the SOS switch has the ability to be integrated with
CMOS digital circuits.
Table 6.6. Comparison of TR switches for different technologies.
SOS CMOS
GaAs MESFET [13]
GaAs MESFET [14]
GaAs MESFET [15]
1 .0 -5 .0
1.9
6 - 19
2.5 - 3.5
1 .7 -2
1.5
2
2.0-2.5
30
35
30
35
18
35
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-
-
151
To improve the performance of our switch, the gate lengths should be scaled to
smaller dimensions allowing decreased on-resistance and lower insertion loss. At the
same time, the FET width should be increased to further improve insertion loss.
Keeping in mind that isolation will be degraded by this, the two must be traded off.
As in the case of the LNA, the linearity of the switch is high as a result of decreased
parasitic capacitance and the absence of the body effect. However, the DP3 should be
further increased to allow the typically 30 dBm output power to be transmitted to the
antenna. With this it is also important to note the breakdown voltage of the device.
The voltage swings incurred across the pass gate transistor can become quite high.
Hence SOS once again has an inherent advantage over other SOI technologies.
6.7 Power Amplifier
Power amplifiers are needed in the transmit leg of a typical transceiver, where
typical output powers for the transmit side approach 1 watt (30 dBm).
Moderately
large output power is also required in the receive leg where voltage ranges on the order
of I volt.
No specific power amplifier circuits have been attempted in this
dissertation; however, large gate width devices have been measured.
T-gate devices with Lg = 0.5 pm, W g = 600 pm were measured on wafer with
ground-signal-ground co-planar probes. The devices were not matched to the 50 Q
measurement system. A class AB power amplifier bias was chosen at
V ds = 2 .2
V Gs = 1.0 volts with a corresponding drain current of 43 mA.
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volts,
152
Figure 6-21 shows the two-tone (f\ = 2.4 GHz,/> = 2.425 GHz) power transfer
characteristics of a 0.5 (im n-channel MOSFETs with 600 |im gate width. The gain of
the device is around 15 dB with an output referred third order intercept of 20 dBm.
The fundamental power, Po, begins to roll-off around -8 dBm with a corresponding
output referred I dB compression point of 8 dBm.
40
/ , = 2 .4 0 0 G H z
— / , = 2 .4 2 5 G H z
•o
-4 0
■60
-8 0
-4 0
1IP3
-3 0
-2 0
-1 0
0
10
In p u t Power (dBm )
Figure 6-21. Two-tone measurements of n-channel
MOSFETs with Lg = 0.5 pm and Wg = 600 pm.
Unfortunately, the maximum output power achieved by the device is around 15
dBm (30 mW), nowhere near the 30 dBm require for most wireless applications. This
power can hopefully be increased by matching and proper circuit design but the power
capabilities of SOS seem limited. The SOS device exhibits about 0.5 W/mm of output
power. Other technologies, including GaAs and GaN are approaching 2 W/mm output
power levels. The output power can be increased by increasing the width of the device
(at the cost of circuit area) but may suffer from other associated problems such as
parasitic inductances and heating.
Generally speaking the heating of the substrate
won't be as bad as that observed in other SOI technologies due to sapphire's higher
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153
thermal conductivity.
However, bulk silicon should avoid this problem with the
expense of parasitic capacitances and other factors mentioned in Chapter 2. Finally, as
discussed in Chapter 4, the breakdown voltage of the devices must be high. Again,
SOS has an advantage over other SOI technologies, but clearly an optimized device
structure such as the SiGFET should be utilized.
6.8 Conclusion and Future Work
The circuits fabricated here represent some of the highest frequency RF CMOS
circuits reported to date.
The results compare favorable to those of other CMOS
technologies operating at lower frequencies. The logical next steps are to integrate the
individual circuit building blocks into a bona fide transceiver and to look at operation
at higher frequency, perhaps in the 5.4 GHz ISM band regime.
In addition to the
integration of the RF components into the transceiver, the digital circuitry of the radio
should be integrated as well to demonstrate the potential of SOS CMOS as a
multifunctional technology allowing both RF and digital circuits to be integrated on
the same chip thus improving performance and reducing cost.
6.9 References
1. A. Karanicolas, "A 2.7 V 900 M H z CMOS LNA and Mixer," International Solid
State Circuits Conference, 1996.
2. J. Long and M. Copeland, "A 1.9 GHz Low-Voltage Silicon Bipolar Receiver
Front-end for Wireless Personal Communication Systems," IEEE Journal or Solid
State Circuits, vol. 30, no. 12, 1995.
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154
3. H. Takeuchi, "A Silicon Wide-band M M IC Amplifier Family for L-S Band
Consumer Product Applications," 1991 IEEE MTT Symposium Digest.
4. J. Long, "RF Analog and Digital Circuits in SiGe Technology," International Solid
State Circuits Conference, 1996.
5.
K. Cioffi, "Monolithic L-band Amplifiers Operating at M illiwatt and SubMilliwatt DC Power Consumptions," 19 9 1 IEEE MMWMCS Digest.
6. S. Hara, "Miniature Low-Noise Variable M M IC Amplifiers with Low Power
Consumption for Portable Communication Applications," 1991 IEEE MTT
Symposium Digest.
7. K. Kobayashi, A.K. Oki, L.T. Tran, and D.C. Streit, "Ultra-low DC Power GaAs
HBT S- and C-band Low Noise Amplifiers for Portable Wireless
Communications," IEEE Transactions on Microwave Theory and Techniques, vol.
43, no. 12, 1995.
8. D.K. Shaeffer, T.H. Lee, "A 1.5-V, 1.5-GHz CMOS Low Noise Amplifier," IEEE
Journal o f Solid-State Circuits, vol. 32, no. 5, May 1997.
9. J.Y.-C. Chang, A.A. Abidi, and M . Gaitan, "Large Suspended Inductors on Silicon
and Their Use in a 2-pm CMOS RF Amplifier," IEEE Electron Device Letters,
vol. 14, no. 5, May 1993.
10. S. Sheng, L. Lynn, J. Peroulas, and K. Stone, "A Low-Power CMOS Chipset for
Spread-spectrum Communications," ISSCC Digest o f Technical Papers, vol. 39,
1996.
11. C. Baringer and C. Hull, "Amplifiers for Wireless Communications," in RF and
Microwave Circuit Design fo r Wireless Communications, L.E. Larson, editor,
Artech House, Boston, 1996, pp. 365.
12. A.N. Karanicolas, "A 2.7 V 900 M H z LN A and Mixer," 1996 IEEE International
Solid-State Circuits Conference Digest, pp. 50-51, Feb. 1996.
13. T. Tokumitsu, I. Toyoda, and M . Aikawa, "A Low-Voltage, High-Power T/RSwitch M M IC Using LC Resonators," IEEE Transactions on M icrowave Theory
and Techniques, vol. 43, no. 5, May 1995.
14. Y. Ayasli, R. Mozzi, L.D. Reynolds, "6-19 GHz GaAs FET Transmit-Receive
Switch," 1983 IEEE GaAs IC Symposium, 1983.
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155
15. C.W. Suckling, M J . Williams, T.B. Bambridge, R.S. Pengelly, K. Vanner, and
R.S. Butlin, "An S-Band Phase Shifter Using Monolithic GaAs Circuits," 1983
IEEE GaAs 1C Symposium , 1983.
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7. Conclusions and Future Work
7.1 Summary of the Dissertation
To meet the trends of the wireless communications, namely low power, low
cost, high performance, the need to synergistically combine both digital and rf circuits
on the same chip becomes increasingly important. Although not specifically covered
in this dissertation, digital CMOS-on-sapphire has been demonstrated and can meet
the needs of wireless communication systems. This dissertation has demonstrated the
capability of silicon-on-sapphire to operate at microwave frequencies to provide the
RF requirements for wireless communications.
T-gate MOSFETs
with high f , high / max and low noise have
been
demonstrated. These MOSFET represent the highest performance silicon based FETs
to date with noise figures below 1 dB at 2 GHz and/max values above 60 G H z and 40
GHz for n- and p-channel devices respectively.
This thesis has also demonstrated the importance and superior performance of
passive elements fabricated on sapphire versus those fabricated in a bulk silicon
process. Using a standard two level metalization process optimized for digital CMOS,
inductors fabricated on sapphire showed a factor of two improvement in quality factor
over inductors fabricated on bulk silicon. Moreover, the sapphire inductors showed a
roughly 25% improvement in self-resonant frequency allowing the inductors to be
used at higher frequencies than there bulk silicon counterparts.
156
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157
Initial work for a M OSFET targeted for power amplifier applications has been
demonstrated. This MOSFET utilizes a sidewall process to define deep sub-micron
gate length (0.15 |im - 0.25 pm) without the use of lithography. This allows a very
short gate length to be realized without the need for expensive and time consuming xray or deep UV photolithography. This MOSFET also incorporated a lightly doped
drain (LDD) region to increase the breakdown voltage. This high breakdown voltage
is necessary for power amplifier applications which typically require device
breakdown voltages 2 to 3 times power supply voltages. N-channel MOSFETs with
0.25 pm channel lengths were fabricated. Breakdown voltages greater than 10 volts
have been achieved with a corresponding value of / t = 9 GHz. The DC characteristics
of the device are still plagued by processing problems and an inability to completely
shut off the device (leakage current). It is believed that this leakage current is process
dependent and should be correctable in future runs.
Finally, circuit blocks required for transceiver applications have been
demonstrated at 2.4 GHz. These blocks include a transmit / receive switch, mixer, low
noise amplifier, and power amplifier.
These circuits represent some of the highest
frequency silicon MOSFET based circuits ever reported. Moreover, in most cases,
their performance is equivalent or better than similar reported CMOS circuits
operating at 900 M H z or 1.8 GHz.
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158
7.2 Future Work
Despite all the effort and time that goes into a dissertation, there is always
more that can be done. It is only through the kindness and mercy of the dissertation
committee members that anyone ever graduates. This section discusses the work that
should be done to refine the devices and circuits covered in this dissertation.
7.2.1 Refinement of the T-gate MOSFET Processing
While the processing of the T-gate has greatly improved over the years, it is not
a manufacturable process. Problems with incomplete and improper planarization, both
on a device level and across the wafer, still exist. In order to make the process more
manufacturable and increase planarization uniformity, chemical mechanical polishing
(CMP) should be considered.
This is process illustrated in Figure 7-22.
Here the
wafers are planarized by mechanically removing the SiC>2 to expose the gate
polysilicon. This eliminates uncertainties in planarization resist thickness discussed in
Chapter 3.
Figure 7-22. T-gate planarization using chemical mechanical polishing.
CMP machines are expensive and surely this process step should be done on a
trial basis first.
Several companies offer a CMP service that could be utilized to
demonstrate the increased uniformity of the planarization. Hence a decision could be
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159
made on the necessity of using CMP for planarization without incurring the cost of a
CMP machine.
7.2.2 Refinement of the SiGFET Processing
The SiGFET is troubled by several factors that need to be addressed. The two
primary concerns are the leakage current and the problems associated with contacting
the sidewall gate as a result of the gate oxide formation. Ideally there would be no
oxide between the gate contact area and the polysilicon sidewall. If the gate oxide was
grown prior to the deposition of the insulator and polysilicon above the LDD region,
this problem could be eliminated. However, this would require an insulator, other than
SiOa, to be used. Moreover, this insulator would require a selective etch to SiCL that
would allow it to be removed without destroying or harming the delicate gate oxide.
Now the formation of the sidewall would not be hindered by the oxide between the
contact region and sidewall. This is depicted in Figure 7-23.
(a) Gate Oxide Growth
(c) Bulk Etch
No oxide between contact
region and sidewall
Insulator other
than SiO,
(b) LDD Insulator and Polysilicon
(d) Sidewall Gate Formation
Figure 7-23. Sidewall gate transistor utilizing an
insulator other than SiC>2 over the LDD region.
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160
Another method to increase reliability of the contact between the sidewall and
the gate contact region could be utilized in devices with T-gates. .As mentioned in
previous chapters, the silicide thickness cannot be too thick for the source and drain
regions. However, to ensure good contact to the sidewall, a thick silicide is needed. In
T-gate devices, after the planarization step, an additional salicidation could be
performed to make the silicide thicker in the gate region. Since the source and drain
regions are covered by the planarization oxide, they would not suffer from non-ohmic
effects observed in the SiGFETs discussed in Chapter 4. This process is depicted in
Figure 7-24.
Silicide
(a) Standard Silicide Formation
(c i Titanium Deposition
Thicker Silicide
ib i T-Gaie Planarization
i d i Second Salicidation
Figure 7-24. Dual salicidation process for a SiGFET.
7.23 Integrated Transceiver
While discrete building blocks for a 2.4 GHz transceiver have been
demonstrated, the blocks should be integrated together to make a bona fide transceiver
operating at 2.4 GHz. Since the block have all been impedance matched to 50 £2. the
blocks alreadv designed should be readilv cascaded to achieve this integration. .Also.
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work ai higber frequencies, namely 5-2 GHz. should also be started. Since bulk silicon
CMOS and other SOI technologies are rapidly approaching performance levels of
silicon-on-sapphire. a jump to the next generation wireless sy'stem should be made.
Eventually, as frequencies continue to rise, bulk silicon and SiO; base SOI
technologies will no longer be able to complete.
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A. FET Parameter Extraction from S-parameters
A .l Introduction
Determination o f the parameter values in the small signal model of a FET
(Figure A - l) can be a long and cumbersome process involving many iterations. To
speed up the process and improve first estimate values, a method to extract these
parameters is necessary. There have been several papers written to address this issue
[1. 2. 3. 4]. With little exception, these methods involve transforming the equivalent
circuit S-parameters into v- and z-parameters and solving a system of equations for the
different element values.
Since the silicon-on-sapphire M OSFET has an insulating
substrate, extraction methods are similar to those used for GaAs MESFETs and
HEMTs.
Figure A-l. Small-signal model of a FET.
162
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163
A.2 Pad Parasitics
A typical layout of a MOSFET for microwave measurements is shown in
Figure A-2. The pads are laid out in a ground-signal-ground configuration with the
FET in the middle.
In this case the FET is configured in the common-source
configuration with source grounded, gate as the input, and drain as the output. The
pad parasitics, capacitances and inductances, can be on the order of the small signal
model parameters.
With an insulating substrate such as sapphire, these parasitics
values are small but can become large and frequency dependent for bulk silicon
MOSFETs. The equivalent circuit of the FET test structure is shown in Figure A-3. It
includes inductor and capacitors for the input (gate) and output (drain) pads as well as
the device under test (D U T), in this case a MOSFET.
Figure A-2. Layout of a MOSFET for microwave
measurements.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
164
Pad
padl
Device Under Test
Pad
I"
Figure A-3. Small signal model of the intrinsic FET
with pad parasitics.
Before determining the FET small-signal parameters, we must first “de-embed”
the pad parasitics from the measurements. This is done by determining the parasitic
inductances and capacitances and then doing matrix subtraction to remove them from
the data.
To determine their values, two additional test structures are needed: an
“open” and a “short”. These structures are merely pads with the same configuration as
the microwave FET (Figure A-2) but with the FET removed (open) and with the inputs
and outputs shorted to ground (short). These structures are shown in Figure A-4.
Figure A-4. Open circuit (left) and short circuit
(right) structures for determining pad parasitics.
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165
A.2.1 Removing Pad Inductances
To determine the pad inductances (for input and output ports), the “short”
circuit test pattern is measured. By shorting the pads to ground, the pad capacitances
are removed resulting in the equivalent circuit shown in Figure A-5.
Figure A-5. Equivalent circuit of the short.
To determine the individual inductance values, the S-parameter data of the
short is converted to z-parameters and then it is easy to see that Lpa(ji and Lpad2 can be
determined as follows:
LpadX
CO
(A. 1)
Im[z23]
Lpadl ~
CO
By Fitting the measured z-parameters of the short structure to the model in Figure A-5,
inductance values for the input pad and output pad can be determined. Figure A-6
shows a typical fit of the measured data to the model. For this case, values of 58 pH
and 70 pH for the input and output pad inductors were extracted.
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166
10
8
g
aJ; 6
Z
G
a
CJ A
Q. 4
E
2
•
0
1
M e a s u re d
M odel
10
Frequency (GHz)
Figure A-6. Typical fit of pad parasitic inductances.
After determination of the specific inductor values, they can be de-embedded
from the measured FET data. To do this, the FET S-parameter data is converted to zparameters. Then a simple matrix subtraction is done.
%2l
^12
Z„
z ,2
Z22
Zv
Z 22
0
0
where lower case z denotes the de-embedded (parasitic inductors removed) FET data
and uppercase Z denotes the measured FET data. The new equivalent circuit, without
pad inductors is shown in Figure A-7.
Pad
pad I
Device Under Test
Pad
rpad2
Figure A-7. Small signal model of the intrinsic FET
with pad inductance removed.
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167
A.2.2 Removing Pad Capacitances
Next the pad capacitances are determined in a similar manner. First the open
circuit S-parameter data is measured, converted to y-parameters and fit to the
equivalent circuit shown below in Figure A-8.
Pad
Figure A-8. Equivalent circuit o f the open.
Since pad inductance have already been determined, they can be removed (in
the same manner they are removed from FET data) by matrix subtraction resulting in
the equivalent circuit shown in Figure A-9.
Pad
Pad
'p a d ! ■
Figure A-9. Equivalent circuit of the open with
inductances removed.
The S-parameters of the open circuit with inductors removed are then
converted to y-parameters and it follows that
r padl = M -V n ]
co
Cpad 2
~
'
CO
R eproduced with permission of the copyright owner. Further reproduction prohibited without permission.
(A.3)
168
By fitting the measured y-parameters to the equivalent circuit (Figure A-9), values of
the input and output pad capacitances can be determined. A typical fit of the measured
data and model is shown in Figure A -10.
Extracted values for input and output
capacitors were 7.5 fF and 8.0 fF respectively.
0.6
•
1
M easured
Model
10
Frequency (GHz)
Figure A-10. Typical fit of pad parasitic
capacitances.
To complete the pad parasitic de-embedding from the FET, the pad
capacitances can be removed from the FET data by matrix subtraction in a similar
manner as the inductances were subtracted. For this, the de-embedded FET data with
inductances removed is converted to y-parameters and then the capacitances are
subtracted as:
Vn
yI2
3^21
3^22
S.
y,2
Yt^
j®Cpadl
0
0
where lowercase y denotes the fully de-embedded FET data (both pad parasitics
inductors and capacitors) and uppercase Y denotes the previously de-embedded (pad
R eproduced with permission of the copyright owner. Further reproduction prohibited without permission.
169
inductors only) data. The new equivalent circuit of the FET with pad inductors and
capacitors removed is shown in Figure A - 11.
Figure A -ll. Small signal model of the intrinsic FET
with pad capacitances removed.
A.3 Device Parameters
Now that the parasitics elements of the FET data have been removed, we can
now concentrate on the determination of the FET equivalent circuit parameters. First
the access resistors (Rg, Rd, and Rs) will be determined followed by the capacitances
(Cgs, Cgd, Cds) followed by the remaining elements (gm, t, Rj, and Ro).
A.3.1 Determination of Rg, Rd and Rs
Several methods have been proposed to determine the access resistances of the
equivalent circuit [3, 5, 6,7], The most common is the “cold” measurement where the
device is biased with V gs = 0 volts and V qs = 0 volts. This bias condition causes the
contribution of the voltage dependent current generator (gm) to become zero and
maximizes the drain-source capacitance (Cds)- A schematic of the zero-bias equivalent
circuit is shown in Figure A-12.
Other more elaborate extraction methods can
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170
determine the parasitic resistances under active-bias conditions [7] but are more
complicated and time consuming.
Intrinsic FET
Rg !
c8
»—/W H — II
M r-
Figure A-12. Zero-bias small-signal equivalent
circuit.
Converting the S-parameters of the zero-bias data to z-parameters, yields the
following:
Re(z„) = Rg + RS
Re(z„) = Rd + R s
(A.5)
Re(z21) = Re(zI2) = Rs
from which the gate, source and drain resistances can be evaluated.
A.3.1.1 Gate, Source and Drain Resistance De-embedding
Once the access resistors have been determined they can be removed from the
measured data to obtain only the intrinsic FET data. To remove the gate, drain and
source resistances, we first convert the FET S-parameter to z-parameters. Then the zparameters can be expressed as:
(A.6)
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171
where |Z| denotes the z-parameter matrix of the de-embedded (pad parasitics) FET, |z|
denotes the z-parameter matrix of the intrinsic FET, and |/?| denotes the z-parameter
matrix of the gate, drain and sources resistances. Namely,
^11
^12
Z 21
^22
Z 2.
Z ,2
R '+ R ,
^22
R«
R
K
(A.7)
After removal of the access resistances, all that is left is the intrinsic FET shown in
Figure A - 13.
c.
Figure A-13. Intrinsic FET with gate, source and
drain resistance removed.
A.3.2 Determination of Cgs, Cgdand Cds
By small-signal analysis, the y-parameters of the FET in Figure A-13 can be
expressed as:
r
RiC -o
vs )-
C.
JL.
y " - l + <o'-Cl,R?+JO) i + o ) 1c i R r +Cr</
V,2 = -j(O C
Sme
(A.8)
-JQJT
y si = ■
y n
= S
jcoC‘
d s +
+
C K d
)
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172
From (A.8) we see that Cgd can be determined from the imaginary part of y^.
Also, for a typical device, arCgjfRj2 is less than 0.01 so the denominator 1 - co2Cgs2Ri2
= 1. Therefore, Cds and Cgs can be determined from the imaginary part of y ^ and yi i
respectively. The equations for these parameters are summarized below.
Im[v,2]
(O
“
r
r
*
C
=—
Im fy ^ + Im jy,,]
co
*d ~
(o
sd
,, =
(
(D
}
a
Figure A -14 shows a typical plot of the extracted Cgd, Cds and Cgd versus
frequency for a 0.5 pm x 50 pm NMOS T-Gate FET. A line of best fit can be used to
determine a unique single value of the capacitances. This yields values of 58 fF and
34 fF for
and Cgd respectively.
Using a simple parallel plate capacitor
approximation (eA/toX), Cgs = 72 fF for the 120 A thick gate oxide.
higher than the extract value of 58 fF.
This value is
However, the parallel plate capacitor
approximation was done assuming a gate length of 0.5 pm. In reality, the effective
gate length should be used. A drawn gate length of 0.5 pms typically has an effective
gate length around 0.35 pms. This would yield a value of 50 fF for the parallel plate
capacitor approximation in good agreement with the value extracted from the Sparameters. In typical modem high speed FETs, Cgd is usually 1/2 to 1/3 the value of
Cgs so the extracted value of 34 fF for Cgd is reasonable.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Frequency (G H z)
Figure A-14. Typical plot of Cgd, Cds and
frequency.
versus
A 3 3 Determination of gm, x, R« and Rj
The next set of parameters to be determined are the transconductance (gm) and
output resistance (R<,). Again we use (A.8) to determine these parameters and get:
R
(A .10)
§mr = Re[y., ] - Im[y:i ]/?. C„Q> - a r C sd C„ R
gm = Re[ v:, ]/?, C „© + Im[ v;i ] 4- a C cd
Figure A -15 shows a typical plot of the extracted gm and gdS as a function of
frequency for a 0.5 pm x 100 pm NMOS T-Gate FET.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Frequency (GHz)
Figure A-15. Extracted device transconductances vs.
frequency.
Again, a line of best fit can be used to determine a single value for gm and g*.
A value of 13.8 mS (138 mS/mm) was obtained for gm in good agreement with the
value determined from DC measurements. A value of 5.3 mS for g^ yields a output
resistance of about 200 Ohms, again in good agreement with the measured DC result.
Finally we determine the channel resistance R, and the phase component of the
transconductance t. These are by far the most difficult parameter to extract due to the
fact that the parameters from which they are derived are usually quite noisy . From
(A.8) and (A.9) wre find that:
R =
(A. 11 >
— tan ‘j — - i
<»
V Smr )
Figure A - 16 shows the extracted values of R, and t versus frequency for a 0.5
um x 100 urn NMOS T-Gate FET. .As mentioned before, these values are often noisy
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
and difficult to extract. A values of 1.8 pS was extracted for ~ in good agreement with
topical values for current high speed devices reported in the literature. Finally a value
of 8_5 Ohms was extracted for R,.
14
12
Frequency iGHzi
Figure A-16. Extracted channel resistance and phase
delay versus frequency.
A.4 Verification of the Model Parameters
The above parameters can be quickly and easily extracted by means of a
spreadsheet or simple computer program.
In general the values extracted from the
above techniques give approximate values. These values are good starting point for
optimization routines within de\ice and circuit simulators such as HP/EEsof s LIBRA.
After extraction, the parameters should be refined by comparing the measured FET
and modeled FET S-parameters and then optimizing the individual values for a better
fit. Figure A -17 shows a smith chan displaying a typical fit of the measured FET to
the modeled FET after optimization of the extracted parameters. With the exception
of S~. a very good fit between the measurements and model was achieved.
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176
Figure A-17. Measured (dots) and modeled (lines)
FET S-parameters.
To further verify' the fit. we can plot the small signal current and power gains to
determine f and f m
This is shown in Figure A - 18.
35
30
1
U n ila te ra l G ain
10
100
Frequency (GHz)
Figure A-18. Current, power, and unilateral gain for
the measured and modeled FET.
R eproduced with permission of the copyright owner. Further reproduction prohibited without permission.
177
A.5 Extracted Model Parameters
The following tables give model parameters of 0.5 (im n- and p-channel
MOSFETs for a wide range of biases extracted using the above techniques.
Table A .l Small-signal param eter values for a 0.5 jxm x 50 pm n-MOSFET.
m m m m
m m m
0
i
0.5
i
1
i
1.5
l
2
i
2.5
i
3
i
2
0
0.5
2
1
2
1.5
2
2
2
2
2.5
3
2
0
3
0.5
3
1
3
1.5
3
2
3
2.5
3
3
3
0
4
4
0.5
1
4
4
1.5
2
4
4
2.5
3
4
w sm m m
m m m
13.4
3100
1050
10.5
9.4
550
9.7
300
9.5
160
110
8.5
8.2
85
8.7
3000
8.7
1500
7.5
1000
730
8.5
540
7.9
400
7.5
290
7.3
7.2
2500
7.1
1700
1200
7.6
1000
6.8
800
6.8
7.7
680
6.7
560
4.0
900
2.0
600
2.0
550
3.5
550
4.2
550
6.0
500
7.1
500
s &j&ssbk
m sm
32.7
40.4
42.7
43.2
42.0
40.7
40.4
32.6
39.9
42.7
43.9
44.3
44.6
43.8
33.3
39.3
42.2
43.5
44.2
44.6
45.0
37.8
40.4
42.3
43.4
44.5
44.7
45.1
m
m
m
m
17.8
18.9
20.8
24.2
28.4
31.1
32.4
17.4
17.8
18.4
19.3
20.6
22.2
24.4
17.1
17.3
17.7
18.2
18.8
19.6
20.4
17.2
17.4
17.5
17.8
18.1
18.4
18.9
w m m
m m
10.3
10.8
11.0
10.5
9.2
8.9
8.3
10.3
10.9
11.0
11.3
11.3
11.3
11.3
10.4
10.6
10.7
11.1
11.2
11.4
11.6
9.4
8.4
8.0
8.0
8.4
9.0
9.5
waanyiia
2.54
5.14
5.73
5.41
4.49
3.67
3.11
3.48
6.05
6.74
6.90
6.84
6.61
6.21
4.25
6.54
7.18
7.37
7.37
7.27
7.10
4.91
6.59
7.01
7.11
7.11
7.06
6.99
m m m
m p m
3.9
2.4
2.2
2.4
2.8
3.4
4.0
3.0
2.1
2.0
1.9
2.0
2.0
2.1
2.5
2.0
1.9
1.8
1.9
1.9
1.9
1.9
1.6
1.6
1.6
1.7
1.7
1.8
R eproduced with permission of the copyright owner. Further reproduction prohibited without permission.
178
Table A.2 Small-signal param eter values for a 0.5 |im x 100 fim n-MOSFET.
H
I
0
0.5
I
1.5
2
2.5
3
0
0.5
1
1.5
2
2.5
3
0
0.5
1
1.5
2
2.5
3
0
0.5
1
1.5
2
2.5
3
aMOBSsasunfl*
i
l
l
l
l
i
l
2
2
2
2
2
2
2
3
3
3
3
3
3
3
4
4
4
4
4
4
4
H P P
13.5
12.0
11.3
11.0
11.5
12.1
12.0
13.0
12.7
12.0
11.5
11.6
12.3
12.5
10.9
11.3
10.9
10.9
11.1
11.0
11.2
8.2
8.0
8.3
8.9
9.5
9.4
10.0
m
1220
460
250
128
73
51
41
1200
650
450
328
242
178
127
1100
700
550
440
360
310
250
400
300
275
275
275
260
250
62.5
77.7
82.6
82.2
79.9
77.7
76.4
61.8
76.2
81.3
83.1
84.4
84.2
83.5
63.2
75.2
80.0
83.0
84.4
85.1
85.7
72.1
76.8
80.5
83.1
84.7
85.5
86.7
31.4
33.4
37.3
44.9
53.1
57.8
60.2
30.7
31.4
32.8
34.7
37.2
40.7
45.3
30.1
30.6
31.4
32.4
33.6
35.1
36.9
30.1
30.6
31.0
31.5
32.2
32.9
33.7
m
5.08
19.9
10.08
20.3
20.1 1 11.09
10.20
18.4
8.31
15.6
6.80
14.1
5.83
13.6
7.14
20.3
11.98
21.2
13.33
21.7
13.66
21.6
13.54
21.6
13.04
21.4
12.15
20.8
8.68
20.6
12.99
21.0
14.27
21.5
14.63
21.6
14.60
21.9
14.38
22.2
14.02
22.4
9.76
18.8
13.08
17.3
13.96
16.3
14.17
16.2
16.7
14.13
14.01
17.8
13.82
18.5
3.6
2.3
2.1
2.3
2.8
3.5
4.2
2.8
2.1
1.9
1.9
1.9
2.0
2.1
2.4
1.9
1.8
1.8
1.8
1.9
1.9
1.8
1.6
1.6
1.6
1.7
1.7
1.8
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
179
Table A.3. Small-signal param eter values for a 0.5 pm x 50 pm p-M OSFET.
W & s im
m m m
-1.50
-2.00
-2.50
-3.00
-3.50
-4.00
-1.50
-2.00
-2.50
-3.00
-3.50
-4.00
-1.50
-2.00
-2.50
-3.00
-3.50
-4.00
-1.50
-2.00
-2.50
-3.00
-3.50
-4.00
-1.50
-2.00
-2.50
-3.00
-3.50
-4.00
-1.00
-1.00
-1.00
-1.00
-1.00
-1.00
-2.00
-2.00
-2.00
-2.00
-2.00
-2.00
-3.00
-3.00
-3.00
-3.00
-3.00
-3.00
-4.00
-4.00
-4.00
-4.00
-4.00
-4.00
-5.00
-5.00
-5.00
-5.00
-5.00
-5.00
m
m m
11.0
13.0
12.3
12.7
11.8
11.9
7.9
8.7
9.2
10.1
11.0
11.2
6.2
7.4
6.4
8.1
8.3
8.1
7.8
7.2
6.5
7.5
6.9
7.7
4.8
5.9
5.4
5.9
6.8
7.4
a
m
a p p
1150
530
280
190
155
130
1500
1050
730
500
340
250
1500
1150
940
750
590
450
1350
1150
980
850
730
630
980
900
900
850
800
720
P
m
i m
m m
38.6
39.2
38.9
39.0
39.0
39.1
38.4
39.6
40.4
40.6
40.1
39.8
37.7
39.6
40.4
41.1
41.5
41.2
38.0
40.0
40.7
41.2
41.7
42.2
38.4
40.2
41.4
42.1
42.3
42.6
m
w m m w $ m
r
28.0
31.4
33.7
34.7
35.1
35.3
25.3
26.3
27.7
29.6
31.6
33.1
24.3
24.9
25.6
26.4
27.6
29.0
23.7
24.0
24.5
25.0
25.7
26.5
23.3
23.6
24.0
24.4
24.9
25.6
a
14.4
14.2
13.0
11.9
10.9
10.2
14.0
14.2
14.2
14.1
13.6
12.8
13.7
14.0
14.2
14.1
14.4
14.3
13.8
13.9
14.0
14.3
14.6
14.5
13.6
13.7
14.1
14.3
14.6
14.6
a n a
4.26
4.17
3.63
3.14
2.79
2.55
4.65
5.15
5.26
5.10
4.70
4.26
4.94
5.49
5.74
5.81
5.76
5.57
5.22
5.77
6.02
6.14
6.15
6.09
5.77
6.28
6.48
6.54
6.52
6.43
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
3.6
3.8
4.3
4.9
5.5
6.0
3.1
3.0
3.0
3.1
3.4
3.7
2.9
2.7
2.7
2.7
2.7
2.8
2.7
2.6
2.5
2.5
2.5
2.5
2.4
2.4
2.3
2.3
2.4
2.4
180
A.6 Summary
Measured FET data can be used to determine the individual parameter values
of the small-signal model.
These values can be easily determined by use of a
computer program or spreadsheet. The extracted values provide a good starting point
to determining the exact values of the parameters by optimization within a simulator
such as LIBRA. Finally, before extraction, the parasitic inductances and capacitances
of the test structure pads must be removed from the data.
A.7 References
1. J.M. Golio, Microwave MESFETs and HEMTs. Artech House, pp. 207-277.
2. G. Dambrine, A. Cappy, F. Heliodore, and E. Playez, “A New Method for
Determining the FET Small-Signal Equivalent Circuit,” IEEE Trans. On
M icrowave Theory and Techniques, vol. 36, no. 7, July 1998.
3. D. Lovelace, J. Costa, and N. Camilleri, “Extracting Small-Signal Model
Parameters of Silicon MOSFET Transistors,” 1994 IEEE MTT-S Digest.
4. K. Shirakawa, H. Oikawa, T. Shimura, Y. Kawasaki, Y. Ohashi, T. Saito, and Y.
Daido, “An Approach to Determining an Equivalent Circuit for HEM Ts,” IEEE
Trans. On Microwave Theory and Techniques, vol. 43, no. 3, March 1995.
5. F. Diamant and M . Laviron, “Measurement of the Extrinsic Series Elements of a
Microwave MESFET Under Zero Bias Condition,” Proceedings 12th European
M icrowave Conference, 1982.
6. W .R. Curtice and R.L. Camisa, “Self-consistent GaAs FET models for Amplifier
Design and Device Diagnostics,” IEEE Transactions on M icrowave Theory and
Techniques, vol. 32, no. 12, Dec. 1984.
7. V. Sommer, “A New Method to Determine the Source Resistance of FET from
Measured S-Parameters Under Active-Bias Conditions,” IEEE Transactions on
M icrowave Theory and Techniques, vol. 43, no. 3, March 1995.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
B. Inductor Small-Signal Models
B .l Modified Small-signal Model (for SPICE simulations)
As discussed in Chapter 5, a modified small-signal model for an inductor on
SOS was developed (Figure B -l). This model utilizes and added resistance, RShUnt, to
aid in the fitting of the quality factor, Q, at higher frequencies. While not necessarily
physical, RShum accounts for skin effect in the inductors, that cannot be accounted for
by the straight DC resistance, R. This is useful in circuit simulator such as SPICE, that
do not have frequency dependent resistors necessary to accurately model R.
The
parameter values of the modified model for inductors with different numbers of turns
are shown in Table B .l.
Figure B -l. Modified small-signal model of an
inductor.
181
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
182
Table B.l. Param eter values of the modified model
for inductors on SOS.
H i
1
2
3
4
5
6
7
8
10
12
15
20
0.27
0.73
1.51
2.58
4.00
5.82
8.03
10.67
17.89
27.30
46.00
93.00
1.9
3.7
5.5
7.0
8.7
11.0
13.0
15.5
19.5
24.1
32.8
52.0
SjjnRfttB
15.0
18.0
25.0
30.0
37.0
41.0
47.0
53.0
62.0
69.0
83.0
105.0
3000
4000
5000
5000
7000
7500
8500
12000
15000
15000
16000
16000
Quite often a circuit design will require an inductance value not listed in the
above table.
For such a case, it is necessary to have a method of predicting the
parameter values and number of turns to achieve the desired inductance. Therefore,
analytical equations were Fit to the data in Table B.l with the number of turns, N, as
the variable. The equations for L, C, R, and Rshum are given in
(B .l).
L = -0.084+0.202 • N + 0.089 • N 2 + 0.007 • N }
C = 9 5 14 + 5524 -N -0 .0 3 8 • N 1
R = 0.410+1.483- N + 0.045 • N 2
(B.l)
R,huni = 1 1 + 1 2 8 9 ■N - 3 - N 2
For example, to achieve an inductance value of 3.25 nH, a 4.5 turn inductor would be
required. This inductor would have a C, R, and RShum values of 33.6 fF, 8 Q, and 5750
Q. respectively.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
183
B.2 Improved Small-signal Model (for LIBRA simulations)
As also discussed in Chapter 5, an improved small-signal model for the
inductors was developed (Figure B-2).
This model was developed for microwave
simulator such as HP/EEsof s LIBRA that accurately simulate high frequency effect
such as the skin effect. This model is a much more physical model than the modified
model in the previous section. Here a microstrip line is used to model the inductor
conductor. By putting in the physical parameters of the inductor conductor (width and
total length of the spiral and DC resistance), LIBRA can accurately calculate the
frequency dependent resistance and inductance of the conductor.
By adding in a
mutual inductance term and a capacitance between the turns, a very good fit to
measured data can be achieved.
Table B.2 summarizes the parameter values for
inductors on SOS with different number of turns.
uc
o
1ML IN I
O
Figure B-2. Improved small signal model of an
inductor.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
184
Table B.2. Param eter values of the improved model
for inductors on SOS.
msmmm
2
3
4
5
6
7
8
m m m m m sm m wmmm
0
0.1
0.5
1.3
2.3
3.7
5.5
691
1131
1634
2200
2828
3519
4273
15
22
30
35
40
45
50
R eproduced with permission of the copyright owner. Further reproduction prohibited without permission.
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