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Theory and design of active microwave frequency multipliers

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Theory and Design o f Active
Microwave Frequency Multipliers
By
JESSI ERNEST-JEROME JOHNSON
B.S. (University of Caiifornia, Davis) 1999
DISSERTATION
Submitted in partiai satisfaction of the requirements for the degree of
DOCTOR OF PHILOSOPHY
in
Electricai and Computer Engineering
in the
OFFICE OF GRADUATE STUDIES
of the
UNIVERSITY OF CALIFORNIA
DAVIS
Approved:
Committee in Charge
2004
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
UMI Number: 3126616
Copyright 2004 by
Johnson, Jess! Ernest-Jerome
All rights reserved.
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Abstract
Active frequency multipliers are very useful and advantageous components whieh are
utilized in many electronic systems. In the following work the basic principles behind
active frequency multiplier design are explored in-depth utilizing computerized
simulation o f idealized FET/HEMT transistor models. The use o f an idealized model
allows fundamental multiplication mechanisms to be shown and allows a thorough
eharacterization o f input and output network design techniques. In doing so, a major
contribution is provided to multiplier design theory, which typically utilizes very basie
design rules and then skips to the full level o f complexity. Also presented in this study is
a novel, generalized, large-signal, FET/HEMT modeling technique. Finally, some
practical frequency multiplier designs are presented including a frequency tripler with
unprecedented third harmonic conversion gain.
11
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Acknowledgements
This work is dedicated to the memory o f my grandfather
Ernest R. Berg “Boo-Boo”
I would like to thank my wife Annette (aka “the helper”) for her tremendous love and
encouragement. You are amazing and I am so thankful to be your husband.
Thanks to my family for always being there, and for all o f the encouragement along
the way. You mean more to me than words can express.
Thanks to Dr. G.R. Branner for making this work possible. I have enjoyed being your
student and it has been a pleasure getting to know you.
I would also like to acknowledge and thank all of those who I have worked in
laboratory with: Dr. Preetham Kumar, Dr. Robert Owens, J.P. Mima, Bob Wong,
Leonard Bryan, Cameron Blatter, Jon Putnam, Donovan Cheuk, Melissa Ghee, Nima
Shams, Dan Gudino, Raymond Guan, Wan Fung Chau, Amolak Singh, Amr Haj-Omar,
and several others.
Ill
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TABLE OF CONTENTS
L I S T O F T A B L E S ............................................................................................................................................................................... V I
L I S T O F F I G U R E S .......................................................................................................................................................................... V II
L I S T O F S Y M B O L S ........................................................................................................................................................................ X V
G U I D E T O I N P U T A N D O U T P U T B IA S V O L T A G E S A N D IN P U T S I G N A L L E V E L S S T U D I E D
IN T H I S W O R K ............................................................................................................................................................................... X I X
C H A P T E R 1.
I N T R O D U C T I O N A N D B A C K G R O U N D .......................................................................................... 1
1.1. In t r o d u c t io n .............................................................................................................................................................................. 2
1.11. A p p l ic a t io n s .............................................................................................................................................................................. 3
1 .III. S t a t e o f t h e A r t ....................................................................................................................................................................6
I .IV. D e s c r ip t io n o f R e s e a r c h ............................................................................................................................................... 10
C H A P T E R 2.
G E N E R A L I Z E D N O N L I N E A R F E T /H E M T M O D E L I N G ..................................................12
2.1. In t r o d u c t io n ............................................................................................................................................................................ 13
2.11. D e v ic e M e a s u r e m e n t s o n Im p r o v e d S y s t e m .......................................................................................................20
2.11.a. Overview....................................................................................................................................... 20
1.11.b. DC Measurements........................................................................................................................21
2.U.C. AC Measurements.........................................................................................................................26
2.111. G e n e r a l iz e d M o d e l in g B a s e d
on
M e a s u r e d R e s u l t s ................................................................................ 39
2. Hi. a. Optimization Approach................................................................................................................39
2.111.b. Modellmplementation.................................................................................................................40
2.Hie. DC Optimization..........................................................................................................................42
2.Hi.d AC Optimization..........................................................................................................................50
2.IV. C o n c l u s i o n ............................................................................................................................................................................. 62
C H A P T E R 3.
F U N D A M E N T A L S O F A C T IV E F R E Q U E N C Y M U L T I P L I E R D E S I G N
U T I L I Z I N G ID E A L I Z E D M O D E L S ....................................................................................................................................... 63
3.1. In t r o d u c t io n ............................................................................................................................................................................64
3 .11. H a r m o n ic G e n e r a t io n
v ia
V a r io u s I n p u t C o n d i t i o n s ................................................................................ 70
3. a. a. Input Signal and Bias.................................................................................................................. 70
3.11.b. Impedance Matching @ the Fundamental............................................................................... 107
3.H.C. Input Bias Network.....................................................................................................................118
3.11.d. N*fo Harmonic Input Reflection.............................................................................................. 141
3 .111. H a r m o n ic G e n e r a t io n
v ia
V a r io u s O u t p u t C o n d it i o n s ......................................................................... 178
3. Hi. a. Output Load and Bias.......................................................................................................... 178
3.111.b. Output Bias Network................................................................................................................. 211
3. Hie. n*fo Harmonic Output Reflection............................................................................................. 224
3 .IV H a r m o n ic G e n e r a t io n
v ia In p u t a n d
O u t p u t C o n d i t i o n s .....................................................................2 6 3
3.iv.a. Idealized Design #I, Parallel Output LC Circuit with Load Resistance Variation................264
3.iv.b. Idealized Design #2, m*fo Input Reflector andfo Output Reflector........................................279
3.iv.c. Idealized Design #3, m*fo Input Reflector andfo Output Reflector with Secondary n*fo Input
and Output Reflectors............................................................................................................................333
3.iv.d. Comparison o f Designs I Through 3 ........................................................................................ 362
3.V. S u m m a r y
C H A P T E R 4.
of
C h a p t e r 3 ...................................................................................................................................................3 6 9
P R A C T I C A L F R E Q U E N C Y M U L T I P L I E R D E S I G N .........................................................3 7 2
4.1. P r a c t ic a l F r e q u e n c y D o u b l e r D e s i g n ................................................................................................................373
4.i.a. Choice o f Bias Point....................................................................................................................373
4.ib. Input and Output Network Configuration................................................................................... 374
4. i. c. Implementation o f Reflector Elements........................................................................................ 375
4.id. Conversion Gain Response versus Reflector Lengths................................................................ 379
IV
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4.1.e. Fabrication................................................................................................................................ 384
4.1.f. Measured Response o f Doubler................................................................................................... 387
4.II.
P r a c t ic a l F r e q u e n c y T r ip l e r D e s ig n .............................................................................................................. 391
4. a. a. Introduction............................................................................................................................ 391
4.11.b. Choice o f Bias Point...................................................................................................................391
4.H.C. Input and Output Network Configuration..................................................................................392
4.11.d. Implementation o f Reflector Networks....................................................................................... 393
4. a. e. Optimizing Reflector Offset Lengths for Maximum 3foConversion Gain............................. 398
4.11.f. Fabrication o f Frequency Tripler............................................................................................... 402
4.11.g. Tripler Conversion Gain Response............................................................................................ 405
C H A PTER 5.
C O N C L U SIO N .............................................................................................................................410
A P P E N D IC E S............................................................................................................................................................... 412
APPEN DIX A,
GENERALIZED NONLINEAR FET/HEM T M ODELING APPENDIX DATA
413
A p p e n d ix A . i . D e v ic e M e a s u r e m e n t s
on
Im p r o v e d S y s t e m ..............................................................................4 1 4
A.i.a. DC Measurement Details........................................................................................................... 414
A.i.b. Characterization o f Dgs andDgd Diodes.....................................................................................415
A.i.e. S-Parameter Measurement Setup............................................................................................... 418
A.i.d. Measured S-Parameter Data...................................................................................................... 419
A.i.e. MATLAB Program to Average S-Parameter Data.................................................................... 423
A.i.f. Large-Signal Measurements........................................................................................................ 428
A p p e n d ix A . ii . G e n e r a l iz e d
m o d e l in g
B a se d
on
M e a s u r e d R e s u l t s ........................................................4 3 4
A.ii.a. ADS Schematic (SDD) o f Generalized Device Model.............................................................. 434
A.ii.b. Response o f Optimized Dgd Diode Model..................................................................................438
A.ii.c. ADS Diode Optimization Schematics........................................................................................ 439
A.ii.d. ADS Schematic o f DC Optimization Scheme.............................................................................442
A.He. ADS Schematic o f AC Optimization Scheme.............................................................................445
A.ii.f. S-Parameter Response o f Generalized Model at VG0=-0.6V................................................... 449
APPENDIX B.
FUNDAM ENTALS OF ACTIVE FREQUENCY M ULTIPLIER DESIGN
UTILIZING IDEALIZED M ODEL - APPENDIX D A T A .............................................................................451
B .i. H a r m o n ic G e n e r a t io n
v ia
V a r io u s In p u t C o n d it io n s - A p p e n d ix D a t a ........................................ 4 5 2
B. i. a. Input Signal and Bias - Appendix Data.....................................................................................452
B. i. b. Input Impedance Matching @ the Fundamental - Appendix Data:..........................................469
B. i.c. Input Bias Network - Appendix Data:........................................................................................ 470
B.i.d. nfo Input Reflector Networks - Appendix Data:.........................................................................478
B .ii. H a r m o n ic G e n e r a t io n
v ia
V a r io u s O u t p u t C o n d i t i o n s .........................................................................4 9 0
B. a. a. Output Load and Bias - Appendix Data:..................................................................................490
B.ii.b. Output Bias N etwork- Appendix Data:....................................................................................496
B.ii.c. nfo Output Reflector - Appendix Data:.....................................................................................497
B .iii. H a r m o n ic G e n e r a t io n
v ia
V a r io u s In p u t
and
O u t p u t C o n d it io n s - A p p e n d ix D a t a
514
B.iii.a. Idealized Design #1 - Appendix Data.....................................................................................514
B. Hi. b. Idealized Design #2 - Appendix Data.....................................................................................522
R E FE R E N C E S ......................................................................................... .... ...............................................................524
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List of Tables
Table 2.1. Sum m ary o f Nonlinear M odeling Designs Presented in the L iterature.....................................17
Table 2.2. AC Param eters for Generalized M o d e l............................................................................................... 56
Table 3.1. Input, Bias, and Loading Conditions for Study o f Harmonic Generation in M odel A
83
Table 3.2. Optimum D oubler Designs Using Idealized M odel........................................................................ 102
Table 3.3. Optimum Tripler Designs Using the Idealized M od el.................................................................. 104
Table 3.4. Sum mary o f Idealized Designs USING 2fo INPUT REFLEC TO R .......................................... 159
Table 3.5. Cases Exam ined in Further D eta il...................................................................................................... 162
Table 3.6. Optimum Conversion Gain Designs Utilizing a 3fo INPUT R EFLE C TO R .......................... 169
Table 3.7. M odels Tested in Output Load and Bias Study............................................................................... 179
Table 3.8. Cases Tested in Output Load and Bias S tu d y ................................................................................. 184
Table 3.9. Calculation o f R lopi and Resulting 3fo CG for Several Input Power L evels.......................... 275
Table 3.10. Sum mary o f M ultiplier Designs Using Configuration o f Figure 3.125.................................. 278
Table 3.11. Sum mary o f Results for Harmonic Plot for Ideal Doubler Design#2, C a s e B l................. 294
Table 3.12. Sum m ary o f Results for H armonic Plot for Ideal Doubler Design#2, C a se C l................. 310
Table 3.13. Sum m ary o f Results for Harmonic Plot for Ideal Tripler Design#2, C a s e A l.................. 325
Table 3.14. Sum m ary o f Designs Utilizing Circuit Configuration o f Figure 3 .1 2 9................................. 332
Table 3.15. Sum m ary o f Results for Section 3.iv.c............................................................................................ 361
Table 3.16. Sum mary o f Optimum 2fo Conversion Gain Designs................................................................362
Table 3.17. Sum mary o f Optimum 2fo M ultiplier Power (MP) D esig n s................................................... 365
Table 3.18. Sum m ary o f Optimum 3fo Conversion Gain Designs................................................................366
Table 3.19. Sum m ary o f Optimum 3fo M ultiplier Power (MP) D esig n s................................................... 368
Table 4.1. C ircuit Board Properties and Quarter-W avelength Stub D im en sion s................................... 376
Table 4.2. Initial and Optimized Quarter-W avelength Stub Dim ensions................................................... 378
Table 4.3. Initial and Optimized Reflector Offset Lengths..............................................................................380
Table 4.4. Designed (Sim ulated) and Actual Fabricated Dimensions o f Frequency Doubler Circuit386
Table 4.5. Sum m ary o f Pertinent Results for Simulated, Measured, and Back Analysis o f Frequency
D ou b ler..................................................................................................................................................................389
Table 4.6. Initial Param eter Values for Input and Output Reflector Elem ents........................................395
Table 4.7. Initial and Optimized Param eter V alues for Input and Output Reflector Elem ents
397
Table 4.8. Initial and Optimized Reflector Offset Lengths..............................................................................399
Table 4.9. Designed and Fabricated Dim ensions o f Frequency Tripler.......................................................404
Table 4.10. Sum m ary o f Pertinent Results for Simulated, Measured, and Back Analysis o f Frequency
Tripler: P in = 6d B m ............................................................................................................................................406
Table 4.11. Sum m ary o f Pertinent Results for Simulated, M easured, and Back Analysis o f Frequency
Tripler: P in = 4d B m ............................................................................................................................................408
Table A .I. Internal vs. Term inal Voltages o f PHEM T Transistor................................................................414
VI
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List of Figures
Figure 1.1. Block Diagram o f 94GHz Frequency Source Presented by [ 1 ] .................................................... 3
Figure 1.2. Block Diagram o f Downconverter System Presented by [2].......................................................... 4
Figure 1.3. Im proved Downconverter System Utilizing Large CG Frequency D oub ler............................ 4
Figure 2.1. DC M easurem ent Setup.......................................................................................................................... 21
Figure 2.2. IV R esponse o f 36163 PHEM T T ransistors......................................................................................24
Figure 2.3. M easured IV Response o f Dg* in Forward Conduction R egion.................................................. 25
Figure 2.4. M easured IV Response o f Dg, in Reverse Breakdown R egion.....................................................26
Figure 2.5. S-Param eter M easurem ent Results for VGO = O.IV, V dd = 2.5V ..............................................27
Figure 2.6. Block Diagram o f Im proved Large-Signal M easurement S ystem .............................................28
Figure 2.7. M EASURED output power vs. input power for VGO = O.IV, Vdd = 2.5V, fo=3G H z.........30
Figure 2.8. M EASURED reflected power vs. input power for VGO = O.IV, Vdd = 2.5V, fo = 3 G H z.... 31
Figure 2.9. M EASURED output power vs. input power for the first three harmonics: V dd = 2.5V,
VGO = 0.1 and -0.6V, fo = 3 G H z.................................................................................................................... 32
Figure 2.10. M EASURED reflected power vs. input power for the first three harmonics: V dd = 2.5V,
VGO = 0.1 and -0.6V, fo = 3 G H z.................................................................................................................... 33
Figure 2.11. M easured output power vs. frequency for the first three harmonics: Vdd = 2.5V, VGO =
0.1 and -0.6V, Pin = 7dBm ................................................................................................................................34
Figure 2.12. M easured reflected power vs. frequency for the first three harmonics: Vdd = 2.5V, VGO
= 0.1 and -0.6V, Pin = 7 d B m ........................................................................................................................... 34
Figure 2.13. M easured output and reflected power vs. gate bias for the first three harmonics: V dd =
2.5V, Pin = 7dBm , fo = 3G H z............................................................................................................................37
Figure 2.14. Schem atic o f Generalized PHEM T Using the Chalmers M odel...............................................40
Figure 2.15. M easured vs. Simulated DC IV Response o f the Gate-Source Diode (Dg,)........................... 44
Figure 2.16. Block Diagram o f DC Optimization Procedure............................................................................45
Figure 2.17. Ids versus Vgs and Vds o f Generalized PHEM T M odel Compared to M easured Data.. 47
Figure 2.18. g„ versus Vgs o f Generalized PHEM T M odel Compared to Measured D ata..................... 48
Figure 2.19. gd versus Vgs and Vds o f Generalized PHEM T M odel Compared to M easured Data ... 49
Figure 2.20. Response o f DC Param eters vs. Externally Applied Gate and Drain V o lta g es.................. 49
Figure 2.21. M easured vs. Simulated Output Power vs. Input Power Response: VGO = 0.1 and -0.6,
Vdd = 2.5, fo = 3 G H z ...........................................................................................................................................53
Figure 2.22. M easured vs. Simulated Reflected Power vs. Input Power Response: VGO = 0.1 and -0.6,
Vdd = 2.5, fo = 3 G H z ...........................................................................................................................................53
F igure 2.23. Block Diagram o f Optimization Procedure Versus VGO and f o ..............................................55
Figure 2.24. M easured vs. Simulated Output and Reflected Power vs. Gate Bias Response: fo =
3GHz, V dd = 2.5, Pin = 7dBm ...........................................................................................................................58
Figure 2.25. M easured vs. Simulated Output Power vs. Fundam ental Freq Response: VGO = 0.1 and
-0.6V , Vdd = 2.5, Pin = 7dBm ............................................................................................................................58
Figure 2.26. Measured vs. Simulated Reflected Power vs. Fundamental Freq Response: VGO = 0.1
and -0.6V , Vdd = 2.5, Pin = 7d B m ...................................................................................................................59
Figure 2.27. M easured vs. Simulated S l l response for VGO = O.IV, V dd = 2.5V, fo=2-4G H z.............. 60
Figure 2.28. M easured vs. Simulated S22 response for VGO = O.IV, Vdd = 2.5V, fo=2-4G H z...............61
Figure 2.29. M easured vs. Simulated S21 response for VGO = O.IV, Vdd = 2.5V, fo=2-4G H z...............61
Figure 3.1. Single-Ended Frequency M ultiplier Block D iagram ......................................................................64
Figure 3.2. PHEM T M odel Showing Five N onlinear E lem ents........................................................................ 65
Figure 3.3. Idealized M odel Schematic o f M odel A ..............................................................................................68
Figure 3.4. Input (M l) and Output (M2) Networks for Input Signal and Bias Study...............................70
Figure 3.5. Exam ple o f the Creation o f a Single-Sided, Clipped, Output Current W aveform .............. 73
Figure 3.6. Exam ple o f the Creation o f a Double-Sided, Clipped, Output Current W aveform ............ 76
Figure 3.7. Comparison o f Actual Versus Ideal PHEM T M odel (a) Ids vs. Vgs (b) Ids vs. V ds........... 80
Figure 3.8. Exam ple W aveform Plot (a) Ids vs. Vgs (b) Vgs(t) vs. tim e (c) Ids(t) vs. tim e (d) Ids vs.
V ds and Loadline (e) Vds(t) vs. tim e .............................................................................................................. 81
Figure 3.9. W aveform Plot for Case A 1....................................................................................................................84
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Figure 3.10. Fourier Series Representation o f Case A1 W aveform s (a) Vgs (b) Ids (c) V d s................ 85
Figure 3.11. Power Available at the Gate vs. Power Output at the Drain for Case A1 (VGO=Vmid). 86
Figure 3.12. Pow er A vailable at the Gate vs. Conversion Gain for Case A1 (VGO=Vm id).................... 87
Figure 3.13. Pow er Available at the Gate (Pin) vs. Reflected Power at the Gate (Pref) for M odel A,
Case A 1 ................................................................................................................................................................... 88
Figure 3.14. W aveform Plot for Case B 1 .................................................................................................................89
Figure 3.15. Fourier Series Representation o f Case B1 W aveform s (a) Vgs (b) Ids (c) V d s................ 91
Figure 3.16. Pow er Available at the Gate (Pin) vs. Power Output at the Drain for Case B 1.................. 92
Figure 3.17. Pow er Available at the Gate vs. Conversion Gain for Case B1 (VGO=Vp).......................... 93
Figure 3.18. Power Available at the Gate (Pin) vs. Reflected Power at the Gate (Pref) for M odel A,
Case B 1 ................................................................................................................................................................... 93
Figure 3.19. W aveform Plot for Case C l ................................................................................................................. 95
Figure 3.20. Fourier Series Representation o f Case C l W aveform s (a) Vgs (b) Ids (c) V d s................... 96
Figure 3.21. Pow er Available at the Gate vs. Power Output at the Drain for Case C l ........................... 97
Figure 3.22. Pow er Available at the Gate vs. Conversion Gain for Case C l (VGO=Vfwd)..................... 98
Figure 3.23. Pow er Available at the Gate (Pin) vs. Reflected Power at the G ate (Pref) for M odel A,
C a s e C l.................................................................................................................................................................... 98
Figure 3.24. W aveform Plot for C ase D 1............................................................................................................... 100
Figure 3.25. N orm alized Output Harmonic Current (Ids„/Ip) vs. Conduction Angle (2*(|))................. 101
Figure 3.26. Comparison o f Drain-Sonrce Current W aveforms for Optimum Tripler D esigns......... 105
Figure 3.27. C ircuit Configuration for Variation in Z mi at the Fundam ental F requency................... 108
Figure 3.28. Conversion Gain and Fundam ental Gate Reflected Power Level vs. Fundam ental Input
Im pedance o f M l, M odel A, Case A l, Pin = -10 d B m ............................................................................110
Figure 3.29. W aveform com parison for Case A l, Pin = -10 d B m ................................................................. 112
Figure 3.30. Conversion Gain and Fundam ental Gate Reflected Power Level Versus Fundam ental
Input Im pedance o f M l, M odel A, Case A l, Pin = 0 d B m ....................................................................113
Figure 3.31. W aveform Comparison for Case A l, Pin = 0 d B m ....................................................................113
Figure 3.32. Conversion Gain and Fundam ental Gate Reflected Power Level Versus Fundam ental
Input Im pedance o f M l, M odel A, Case B l, Pin = -10 d B m ................................................................ 114
Figure 3.33. W aveform Comparison for Case B l, Pin = -10 d B m ................................................................ 115
Figure 3.34. Conversion Gain and Fundam ental Gate Reflected Power Level Versus Fundam ental
Input Im pedance o f M l, M odel A, Case C l, Pin = -10 d B m ................................................................ 116
Figure 3.35. Circuit Configuration for Study o f Input Bias N etw ork...........................................................118
Figure 3.36. Detail Schem atic o f Input Configuration for Inpnt Bias Study............................................ 119
Figure 3.37. Expected Voltage W aveform Across D g,....................................................................................... 120
Figure 3.38. Expected Current W aveform in Dg,................................................................................................ 122
Figure 3.39. Gate waveform s for various values o f Rdc: C a seA l.1 .............................................................. 125
Figure 3.40. Gate waveform s for various values o f Rdc: C a s e A l.2 .............................................................. 126
Figure 3.41. Gate waveform s for various values o f Rdc: C a se A l.3 .............................................................. 126
Figure 3.42. G ate Harmonics for various values o f Rdc: C a se A l.3 ..............................................................127
Figure 3.43. Drain Current waveform s for various values o f Rdc: C a seA l.3............................................128
Figure 3.44. Drain harm onics for various values o f Rdc: C a se A l.3 .............................................................129
Figure 3.45. Pow er response for M odel A, Case A l for varying values o f Rdc......................................... 130
Figure 3.46. Pow er response for M odel A, Case B l for varying values o f R dc......................................... 132
Figure 3.47. Gate waveform s for various values o f Rdc: C aseC l.3 (VGO=Vfwd, P in =5d B m )
133
Figure 3.48. Pow er response for M odel A, Case C l for varying values o f Rdc......................................... 135
Figure 3.49. Shift in the DC Bias Level vs. Input Power for M odel A, Case A l ....................................... 136
Figure 3.50. Pout vs. Pin response o f M odel A for Rdc = 50 ohms, and Rdc = 1 ohm W ith Bias
A djustm en t.......................................................................................................................................................... 137
Figure 3.51. Output Current W aveform s Showing Effects o f Bias Compensation, Case A1.3
(VGO=Vmid, Pin=5dBm )................................................................................................................................. 138
Figure 3.52. Block Diagram o f n*fo Input Reflector Network S tu d y .......................................................... 141
Figure 3.53. The use o f an Input n*fo R eflector..................................................................................................142
Figure 3.54. S21 Response o f Separate 2fo and 3fo LC Reflectors Overlaid on the Same P lo t
146
Fignre 3.55. 2fo Conversion Gain vs. 2fo Reflector Phase Length: M odel A, Case A l ........................... 149
Figure 3.56. 3fo Conversion Gain vs. 2fo Reflector Phase Length: M odel A, Case A l .......................... 151
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Figure 3.57. Pin vs. Conversion Cain for M odel A, Case A l - Comparison o f Response with: No Input
R eflector (solid); 2fo Reflector Optimized for 2fo Output (dashed); 2fo R eflector O ptim ized for
3fo Output (d otted )............................................................................................................................................152
Figure 3.58. 2fo Conversion Gain vs. 2fo Reflector Phase Length: M odel A, Case B l .......................... 153
Figure 3.59. Pin vs. Conversion Gain for M odel A, Case B l - Comparison o f Response with: No Input
R eflector (solid); 2fo Reflector Optimized for 2fo Output (dashed) 2fo Reflector O ptim ized for
3fo Output (d otted )............................................................................................................................................ 154
Figure 3 .6 0 .2fo Conversion Gain vs. 2fo Reflector Phase Length: M odel A, Case C l .......................... 156
Figure 3.61. Pin vs. Conversion Gain for M odel A, Case C l - Comparison o f Response with: No Input
R eflector (solid); 2fo Reflector Optimized for 2fo Output (dashed) 2fo R eflector Optimized for
3fo Output (d otted )............................................................................................................................................ 158
Figure 3.62. Input im pedance o f 2fo Input Reflector N etwork vs. Phase Length in D egrees
160
Figure 3.63. 2fo Reflector Phase Length vs. Second Harmonic Gate Voltage M agnitude: M odel A,
Case C l (VGO=Vfwd, Pin=-10dBm ).............................................................................................................162
Figure 3.64. Comparison o f Gate-Source Voltage and Drain-Source Current W aveform s for Case A l,
Pin=-1 dBm, Optimized for 2fo C G .............................................................................................................. 164
Figure 3.65. Comparison o f Gate-Source Voltage and Drain-Source Current W aveform s for Case B l,
Pin=5 dBm , Optimized for 3fo C G ............................................................................................................... 165
Figure 3.66. Com parison o f Gate-Source Voltage and Drain-Source Current W aveform s for C ase C l,
Pin=-7 dBm , Optimized for 3fo C G .............................................................................................................. 167
Figure 3 .6 7 .3fo Conversion Gain vs. 3fo Input Reflector Phase: M odel A, Case A l ..............................168
Figure 3.68. Comparison o f Gate-Source Voltage and Drain-Source Current W aveform s for Case A l,
Pin=-1 dBm , Optimized for 3fo C G .............................................................................................................. 171
Figure 3.69. Comparison o f Gate-Source Voltage and Drain-Source Current W aveform s for Case B l,
Pin=5 dBm , Optimized for 3fo C G ............................................................................................................... 173
Figure 3.70. 3rd harm onic Gate Voltage M agnitude vs. 3fo Input Reflector Phase Length: M odel A,
Case A l (VGO=Vmid, Pin = OdBm).............................................................................................................. 174
Figure 3.71. Illustrated Effects o f Input Reflector on the Reflected Power Levels at O ther Harmonics
.................................................................................................................................................................................. 176
Figure 3.72. DC IV Curves o f M odel A, W ith Cases T ested............................................................................179
Figure 3.73. DC IV Curves o f M odel B, W ith Cases T ested ............................................................................181
Figure 3.74. DC IV Curves o f M odel C_2, W ith Cases T ested ....................................................................... 183
Figure 3.75. C ircuit Schem atic for Output Load and Bias S tu d y ................................................................. 185
Figure 3.76. Conversion Gain Response vs. Load Resistance for Case A l . l (VGO=Vmid, Vdd=Vddmid,
Vg=|Vp|/2), Comparison o f Models A, B and C _2....................................................................................188
Figure 3.77. W aveform Plot for M odel A, Case A l . l (VGO=Vmid, Pin=-7dBm , Vg=0.3 V ) ................192
Figure 3.78. Fourier Series Plot for M odel A, Case A l . l (VGO=Vmid, Pin=-7dBm , Vg=0.3 V )
192
Figure 3.79. W aveform Plot for M odel B, Case A l . l (VGO=Vmid, Pin=-7dBm , Vg=0.3 V )................. 194
Figure 3.80. Enlarged Plot o f Figure 3.79(c): Ids W aveforms for M odel B, Case A l . l .......................... 195
Figure 3.81. Fourier Series Plot for M odel B, Case A l . l (VGO=Vmid, Pin=-7dBm , Vg=0.3 V )
196
Figure 3.82. W aveform Plot for M odel C-2, Case A l . l (VGO=Vmid, Pin=-7dBm , Vg=0.3 V )
197
Figure 3.83. Enlarged Plot o f Figure 3.82(c): Ids W aveform s for M odel C_2, Case A l . l .....................198
Figure 3.84. Enlarged Plot o f Figure 3.82(b): Vgs W aveforms for M odel C_2, Case A l . l .....................199
Figure 3.85. Fourier Series Plot for M odel C-2, Case A l . l (VGO=Vmid, Pin—7dBm, Vg=0.3 V ).... 200
Figure 3.86. Conversion Gain vs Pin Response o f Models C_2 and M odel A, for Cases A l, A2 and A3
..................................................................................................................................................................................204
Figure 3.87. W aveform Plot for M odel C_2, Cases A2.1 and A3.1 (R l = 50 ohms. Pin = -7dBm ) .... 205
Figure 3.88. Conversion Gain vs Pin Response o f M odel C_2 and M odel A, for Cases B l, B2 and B3
206
Figure 3.89. W aveform Comparison o f M odel C_2 and M odel A for Case B l (VGO=Vp,
Vdd=Vdd„,id), Pin=10dBm ............................................................................................................................... 208
Figure 3.90. Conversion Gain vs Pin Response o f Models C_2 and M odel A, for Cases C l, C2 and C3
..................................................................................................................................................................................209
Figure 3.91. Circuit Configuration for Output Bias Network S tu d y............................................................211
Figure 3.92. Exam ple Ids W aveform ......................................................................................................................212
Figure 3.93. Detail V iew o f Output Circuit from Figure 3.91......................................................................... 213
IX
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Figure 3.94. Exam ple Calculated \ d s W aveform Using (Eq ( 3.38 ))............................................................214
Figure 3.95. Ids and Vds W aveforms for Case B l .l (VGO=Vp, Pin—7 dBm, Vg=|Vp|/2) and C ase B1.2
(VGO=Vp, P in=-ldB m , Vg=|Vp|), when R l = 50 ohms and Rdd = 0.1 o h m s.................................. 218
Figure 3.96. Ids and Vds W aveform s for R l = Rdd = 50ohms, Pin—10, -5 and 0 dBm (Corresponding
to Idsi, Ids 2 and Idss)......................................................................................................................................... 219
Figure 3.97. Shift in DC Drain Voltage Level W ith Increasing Input Power, Case B l (VGO=Vp,
Vdd=Vdd„,id)........................................................................................................................................................ 221
Figure 3.98. Drain Source W aveform s for C aseB l.2 (VGO=Vp, Vdd=Vddm-,d, P in=-ldB m ,V g=|V p|),
Showing Bias Compensation T ech niqu e.....................................................................................................222
Figure 3.99. C ircuit Configuration for nfo Output R eflection .......................................................................224
Figure 3.100. Detail V iew o f Output Circuit from Figure 3.99......................................................................225
Figure 3.101. Frequency Response o f Fundam ental Frequency (fo = 3 G H z) LC Short C irc u it
228
Figure 3.102. 3fo Conversion Gain vs. fo Output Reflector Phase Length for M odel A, Case A l .... 229
Figure 3.103. Output Conductance vs Drain Source Voltage o f M odel C_2: V G 0—0 .3 V ................... 231
Figure 3.104. 3fo Conversion Gain vs. fo Output Reflector Phase Length for M odel C_2, C a s e A l. 232
Figure 3.105. 2fo CG versus Output Reflector Length: M odel A, C aseA l (VGO=Vmid,Vdd=Vddmid)
..................................................................................................................................................................................233
Figure 3.106. 3fo CG versus Output Reflector Length: M odel A, C aseA l (VGO=Vmid,Vdd=Vddmid)
..................................................................................................................................................................................235
Figure 3 .1 0 7 .3fo CG versus Output Reflector Length Showing T rue 90 degree Optimum Length:
M odel A, C aseA l (VGO=Vmid,Vdd=Vdd„id)............................................................................................235
Figure 3.108. M agnitude o f the Im pedance o f the fo Reflector Network at the Fundam ental
Frequency (IZMiko)? vs. Reflector Phase L ength.......................................................................................237
Figure 3.109. Comparison W aveform Plot for M odel C_2, Case A l . l ........................................................237
Figure 3.110. IV Curves and Load-Line Plot (Zoomed in Plot o f Figure 3.109(d ))................................. 238
Figure 3.111. Gate-Source Voltage W aveform (Zoomed in Plot o f Figure 3.109(b))...............................239
Figure 3.112. Drain Current W aveform (Zoomed in Plot o f Figure 3.109(c)).......................................... 239
Figure 3.113. Drain-Source Voltage W aveform (Zoomed in Plot o f Figure 3 .109(e))............................ 240
Figure 3.114. Gate-Drain Current W aveform for M odelC_2, C a seA l.1 (VGO=Vmid, Vdd=Vddmid»
P in =-7d B m )..........................................................................................................................................................244
Figure 3.115. Comparison Frequency Domain Response for M odel C_2, Case A l . l ............................. 244
Figure 3.116. Load-line Trajectory Comparison for Various Output Reflector Lengths (Loutf„)... 246
Figure 3.117. Conversion Gain Comparison for M odel C_2, Case A l ........................................................ 248
Figure 3.118. 2fo M ultiplier Power (MP) versus Output Reflector Length: M odel A, C aseA l
(VGO=Vmid,Vdd=Vdd„id)............................................................................................................................... 251
Figure 3.119. 3fo M ultiplier Power (MP) versus Output Reflector Length: M odel A, C aseA l
(VGO=Vmid,Vdd=Vdd„id)............................................................................................................................... 252
Figure 3.120. M ultiplier Power (MP) Comparison for M odel C_2, Case A l .............................................253
Figure 3.121. 2fo Conversion Gain vs. Output Reflector Length (Loutf„), Case B l (VGO=Vp,
Vdd=Vdd„,id)........................................................................................................................................................ 255
Figure 3.122. 3fo Conversion Gain vs. Output Reflector Length (Loutf„), Case B l (VGO=Vp,
Vdd=Vdd„id)........................................................................................................................................................ 256
Figure 3.123. Conversion Gain vs Input Power Comparison for Case B l (VGO=Vp, Vdd=Vdd„id) 257
Figure 3.124. M ultiplier Power vs Input Power Comparison for Case B l (VGO=Vp, Vdd=Vddmid) 259
Figure 3.125. M ultiplier Topology Utilizing Parallel LC C ircuit.................................................................. 264
Figure 3.126. Second Harmonic Conversion Gain vs. Load R l for Case B l ..............................................270
Figure 3.127. Comparison o f Output Power, Conversion Gain and M ultiplier Pow er Response, R l
=377ohms: Case B l (VGO=Vp, Vdd=Vdd„id)............................................................................................272
Figure 3.128. Third Harmonic Conversion Gain vs. Load R l for Case A l, VGO=Vmid, Vdd=Vddmid?
P in=-2dB m ............................................................................................................................................................276
Figure 3.129. M ultiplier Topology Utilizing m*fo Input and fo Output Reflector N etw orks...............279
Figure 3.130. Second Harmonic Conversion Gain vs. fo Output Reflector Transmission Line Length
for Case B l: VGO=Vp, Vdd=Vdd„,id, Lin2f„=50deg, Pin=-10dBm .......................................................281
Figure 3.131. Second Harm onic Conversion Gain vs. fo Output Reflector Transm ission Line Length
for C ase B l: Zoom ed in Plot o f Figure 3.130.............................................................................................282
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Figure 3.132. Second Harm onic Conversion Gain vs. 2fo Input Reflector Transmission Line Length
for Case B l: VGO=Vp, Vdd=Vddmid, Loutf„=88.5 deg, Pin=-10dBm ................................................. 284
Figure 3.133. W aveform Plot for Design #2, Case B l (Linfo=88.5deg, Lout2fo=50deg, Pin=-10dBm ) 285
Figure 3.134. Enlarged Version o f Figure 3.130(b), Gate-Source Voltage W aveform for Design2,
C a s e B l...................................................................................................................................................................286
Figure 3.135. Enlarged Version o f Figure 3.130(c), Drain Current W aveform for Design2, C aseB l 287
F igure 3.136. Enlarged Version o f Figure 3.130(e), Drain-Source Voltage W aveform for Design2,
C a s e B l...................................................................................................................................................................287
Figure 3.137. Enlarged Version o f Figure 3.130(d), Load-Line Plot for Design2, C a se B l.................... 288
Fignre 3.138. Harm onic Plots for Ideal Doubler Design#2, Case B l, Various R eflector C om binations
..................................................................................................................................................................................293
Figure 3.139. Load-line Trajectory Comparison for Various Output Reflector Lengths (Loutf„)... 297
Figure 3.140. Conversion Gain vs. Input Power Plot for Design #2, Case B l (Loutfo=88.5 deg,
Lin2fo=50deg)....................................................................................................................................................... 299
Figure 3.141. MP vs. Input Power Plot for Design #2, Case B l (Loutf„=94deg, Lin2fo=46deg)
300
Figure 3.142. Second Harmonic Conversion Gain vs. fo Output Reflector Transmission Line Length
for Case C l for Pin = -lOdBm, Lin2fo = 4 7 d eg ........................................................................................ 301
Figure 3.143. Second Harmonic Conversion Gain vs. 2fo Input Reflector Transmission Line Length
for Case C l for Pin = -lOdBm, Loutf„ = 9 2 d eg ......................................................................................... 302
Figure 3.144. W aveform Plot for Design #2, Case C l (Linfo=92deg, Lin2fo=47deg, P in =-10d B m ). 303
Figure 3.145. Enlarged Plot o f the Gate-Source Voltage W aveform for Design2, C a se C l................... 304
Figure 3.146. Enlarged Plot o f the Drain Current W aveform for Design2, C a s e C l...............................304
Figure 3.147. Enlarged Plot o f the Drain-Source Voltage W aveform for Design2, C a s e C l.................305
Figure 3.148. Enlarged Plot o f the Load-Line Trajectory for Design2, C a se C l.......................................305
Figure 3.149. Harm onic Plots for Ideal Doubler Design#2, Case C l, Various Reflector C om binations
..................................................................................................................................................................................310
Figure 3.150. Conversion Gain vs. Input Pow er Plot for Design #2, Case C l (Loutf„=92 deg,
Lin2fo=48deg)....................................................................................................................................................... 314
Figure 3.151. M P vs. Input Power Plot for Design #2, Case C l (Lontfo=110deg, Lin2fo=44deg)
315
Figure 3.152. Third Harm onic Conversion Gain vs. fo Output Reflector Transmission Line Length
for Case A l for Pin = -lOdBm, Lin3fo = 30.5 d e g ................................................................................... 316
Figure 3.153. Third Harmonic Conversion Gain vs. 3fo Input Reflector Transmission Line Length
for Case A l for Pin = -lOdBm, Loutf„ = 89 d e g ........................................................................................ 317
Figure 3.154. W aveform Plot for Design #2, Case A l (Linfo=89deg, Lin3fo=30.5deg, Pin=-10dBm )318
Figure 3.155. Enlarged Plot o f the Gate-Source Voltage W aveform for Design2, C a se A l................... 319
Figure 3.156. Enlarged Plot o f the Drain Current W aveform for Design2, C a s e A l...............................319
Fignre 3.157. Enlarged Plot o f the Drain-Sonrce Voltage W aveform for Design2, C a s e A l.................320
Figure 3.158. Enlarged Plot o f the Load-Line Trajectory for Design2, C a se A l.......................................320
Figure 3.159. Harm onic Plots for Ideal Tripler Design#2, Case A l, Various Reflector C om binations
..................................................................................................................................................................................324
Figure 3.160. Conversion Gain vs. Input Power Plot for Design #2, Case A l (Loutf„=89 deg,
Lin3fo=30.5deg)....................................................................................................................................................329
Figure 3.161. Conversion Gain vs. Input Power Plot for Design #2, Extended to Lower Input Power
Levels, C ase A l (Loutf„=89 deg, Lin3f„=30.5deg)......................................................................................330
Figure 3.162. M ultiplier Topology Utilizing Extra n*fo Input and Output R eflector N etw orks
333
Figure 3.163. Second Harm onic Conversion Gain vs. 3fo Output Reflector Length, Case B l ............ 336
Figure 3.164. Second Harm onic Conversion Gain vs. 3fo Input Reflector Length, C ase B l ................337
Figure 3.165. Drain-Source V oltage W aveforms and Corresponding Harmonics: Case B l (VGO=Vp,
Vdd=Vdd„,id)........................................................................................................................................................ 338
Figure 3.166. Gate-Drain Current W aveform s and Corresponding Harmonics: Case B l (VGO=Vp,
Vdd=Vdd„id)........................................................................................................................................................ 340
Figure 3.167. G ate-Source Voltage W aveforms and Corresponding Harmonics: Case B l (VGO=Vp,
Vdd=Vdd„,id)........................................................................................................................................................ 341
Figure 3.168. Drain-Source Current W aveforms and C orresponding Harmonics: Case B l (VGO=Vp,
Vdd=Vdd„id)........................................................................................................................................................ 343
Figure 3.169. Second Harm onic CG, Pout, and MP vs. Input Power, Case B l, Design 3 ..................... 344
XI
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Figure 3.170. Second Harmonic CG, Pout, and MP vs. Input Power (Extended to Low er Pin), Case
B l, Design 3 ......................................................................................................................................................... 345
Figure 3.171. Second Harmonic Conversion Gain vs. 3fo Output Reflector Length, C ase C l ............ 346
Figure 3.172. Second Harmonic Conversion Gain vs. 3fo Input Reflector Length, Case C l ................347
Figure 3.173. Drain-Source Voltage W aveforms and Corresponding Harmonics: Case C l
(VGO=Vfwd, Vdd=Vdd™id)..............................................................................................................................348
Figure 3.174. Gate-Drain Current W aveforms and Corresponding Harmonics: Case C l (VGO=Vfwd,
Vdd=Vdd„,id)........................................................................................................................................................ 349
Figure 3.175. Gate-Source Voltage W aveforms and Corresponding Harmonics: Case C l
(VGO=Vfwd, Vdd=Vdd„,id)..............................................................................................................................350
Figure 3.176. Drain-Source Current W aveform s and Corresponding Harmonics: Case C l
(VGO=Vfwd, Vdd=Vdd„id)..............................................................................................................................351
Figure 3.177. Third Harmonic Output and Reflected Power Levels Before Use o f Extra Third
Harmonic Reflector N etw ork s.......................................................................................................................353
Figure 3.178. Second Harmonic CG, Pout, and MP vs. Input Power, Case C l, Design 3 ..................... 354
Figure 3.179. Second Harmonic CG, Pout, and MP vs. Input Power (Extended to Lower Pin), Case
C l, Design 3 ......................................................................................................................................................... 355
Figure 3.180. Third Harmonic Conversion Gain vs. 2fo Output Reflector Length, C ase A l .............. 357
Figure 3.181. Third Harmonic Conversion Gain vs. 3fo Input Reflector Length, Case A l ..................358
Figure 3.182. Output and Reflected Power Response with 3fo Reflectors Disabled (Tripler Design 2)
..................................................................................................................................................................................358
Figure 3.183. Third Harm onic CG, MP, and Pout vs Pin for Tripler Design 3, Case A l .................... 360
Figure 4.1. M easured 2fo Conversion Gain vs Gate Bias Voltage (VGO) for Several Input Power
L e v els..................................................................................................................................................................... 373
Figure 4.2. C ircuit Configuration for Practical Frequency Doubler D esign..............................................375
Figure 4.3. Initial |S21| Response o f Input and Output Quarter-W avelength S tu bs...............................377
Figure 4.4. Initial and Optimized |S21| Response o f Quarter-W avelength Stubs.................................... 378
Figure 4.5. Second Harmonic Conversion Gain vs fo Output Reflector Offset Length (Loutf„)
381
Figure 4.6. Second Harmonic Conversion Gain vs 2fo Input Reflector Offset Length (Lin 2 f„)
382
Figure 4.7. Simulated Conversion Gain Response vs Fundam ental Frequency........................................383
Figure 4.8. Sim ulated 2fo CG, M P and Pout vs Pin Response o f D o u b ler................................................. 384
Figure 4.9. Layout o f Frequency D oub ler.............................................................................................................385
Figure 4.10. Im age o f Practical Frequency D oubler.......................................................................................... 387
Figure 4.11. Conversion Gain vs Fundam ental Frequency o f Doubler Design: M easured, Simulated
and Back A nalysis..............................................................................................................................................388
Figure 4.12. M easured 3fo Conversion Gain vs Gate Bias for Several Input Power L evels.................392
Figure 4.13. C ircuit Configuration for Practical Frequency Tripler D esig n ............................................ 393
Figure 4.14. |S21| vs Freq of: (a)Output Reflector Network; (b) Input Reflector N etw ork ..................396
Figure 4.15. |S21| vs Freq of: (a)Output Reflector Network; (b) Input Reflector Network:
C omparison o f Initial and Optimized Response.......................................................................................398
Figure 4.16. Simulated Conversion Gain vs Frequency Response o f Practical Tripler Design:
(P in= 6d B m )..........................................................................................................................................................400
Figure 4.17. Sim ulated 3fo CG, M P and Pout vs Pin Response o f T rip ler................................................. 401
Figure 4.18. Circuit Board Layout for Fabricated T ripler..............................................................................402
Figure 4.19. Im age o f Practical Frequency T rip ler............................................................................................405
Figure 4.20. Conversion Gain Response o f Practical Frequency Tripler at Pin=6dBm ......................... 406
Figure 4.21. Conversion Gain Response o f Practical Frequency Tripler at Pin=4dBm ......................... 408
Figure A .I. M easurem ent o f Dg, and Dgj Using a Sem iconductor Param eter A n alyzer........................415
Figure A.2. M easured IV Response o f Dgd in Forward Conduction Region............................................... 416
Figure A.3. M easured IV Response o f Dgd in Reverse Breakdown R eg io n ................................................ 417
Figure A.4. S-Param eter M easurem ent S etup .....................................................................................................418
Figure A.5. S-Param eter M easurement Results for VGO = -0.6V, Vdd = 2.5V ......................................... 419
Figure A.6. S-Param eter M easurem ent Results for VGO = -0.4V, Vdd = 2.5V ......................................... 420
Figure A.7. S-Param eter M easurem ent Results for VGO = -0.2V, Vdd = 2.5V ......................................... 420
Figure A.8. S-Param eter M easurement Results for VGO = OV, Vdd = 2 .5 V ..............................................421
Figure A.9. S-Param eter M easurement Results for VGO = 0.2V, Vdd = 2 .5 V .......................................... 421
Xll
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Figure A.IO. S-Param eter M easurem ent Results for VGO = 0.4V, Vdd = 2 .5 V ........................................ 422
Figure A .l l . Im age o f Large-Signal M easurement S y stem ............................................................................428
Figure A.12. Pin vs. Pout M easurements for VG0=-0.6V, Vdd=2.5V, fo= 3 G H z......................................429
Figure A.13. Pin vs. P ref M easurements for V G0=-0.6V, Vdd=2.5V, fo=3G H z.......................................429
Figure A.14. Pin vs. Pout M easurements for VG0—0.6V, Vdd=2.5V, fo= 6G H z......................................430
Figure A.15. Pin vs. P ref M easurements for VG0—0.6V, Vdd=2.5V, fo=6G H z.......................................430
Figure A.16. Pin vs. Pout M easurements for VG0=0.1V, Vdd=2.5V, fo=6G H z........................................ 431
Figure A.17. Pin vs. Pref M easurements for VG0=0.1V, Vdd=2.5V, fo= 6G H z........................................ 431
Figure A.18. Pin vs. Pout Measurements for VG0=0.4V, Vdd=2.5V, fo=3G H z........................................ 432
Figure A.19. Pin vs. Pref M easurements for VG0=0.4V, Vdd=2.5V, fo= 3G H z........................................ 432
Figure A.20. Pin vs. Pout M easurements for VG0=0.4V, Vdd=2.5V, fo=6G H z........................................ 433
Figure A.21. Pin vs. P ref M easurements for VG0=0.4V, Vdd=2.5V, fo= 6G H z........................................ 433
Figure A.22. M easured vs. Simulated DC IV Response o f the Gate-Drain Diode (Dgd)........................438
Figure A.23. M easured vs. Simulated S l l Response for VGO = -0.6V, Vdd = 2.5V,
fo=2-4G H z.4 49
Figure A.24. M easured vs. Simulated S22 Response for VGO = -0.6V, Vdd = 2.5V,
fo=2-4G H z.4 50
Figure A.25. M easured vs. Simulated S21 Response for VGO = -0.6V, Vdd = 2.5V,
fo=2-4G H z.4 50
Figure B .I. Sym bolically Defined Device Representation o f M odel A ......................................................... 463
Figure B.2. Sym bolically Defined Device Representation o f Idealized D iodes.......................................... 463
Figure B.3. ADS Schem atic for Characterization o f Idealized M odels........................................................ 464
Figure B.4. ADS Schem atic for Fundamental Frequency Input Im pedance Study.................................469
Figure B.5. ADS Simulation Schematic for Input Bias Network Study.......................................................470
Figure B.6. Gate waveform s for various values o f Rdc using realistic M odel (M odel36a_Vgo_pO_l),
Case C1.3 (VGO = 0.8V, Pin = 5 dBm )......................................................................................................... 471
Figure B.7. Pin vs. Pout o f M odelA-4-b, Case A l adj, varying Rdc v a lu es...............................................473
Figure B.8. Pout vs. Pin Response o f Actual Device and Device M odel, Case A l_ a d j, V arying Rdc 474
Figure B.9. Gate V oltage W aveform s for Idealized (M odel A_4_b) and Realistic PHEM T M odel,
Case A l adj, Pin = + 5 d B m .............................................................................................................................475
Figure B.IO. M easured and Simulated Shift in the DC Bias Level vs. Input Power, C ase A l a d j... 476
Figure B . l l . Pout vs. Pin Response o f Realistic M odel (M odel36a-vgo-p0-l) for Rdc = 50 Ohms, and
Rdc = 1 Ohm W ith Bias Adjustm ent............................................................................................................477
Figure B.12. G ate-Source Current W aveforms for Case C l (VGO=Vfwd), at Pin=-7, -1 ,5 d B m ......481
Figure B .13.3fo CG versus Lin2fo for M odelA, Case B l ................................................................................ 483
Figure B .14.3fo CG versus Lin2fo for M odelA, Case C l ................................................................................ 484
Figure B.15. 2fo Conversion Gain versus 3fo Input Reflector Length for M odel A, Case A l
485
Figure B.16. Pin vs. Conversion Gain for M odel A, Case A l - Comparison o f Response with: No
Input R eflector (solid); 3fo Reflector Optimized for 2fo Output (dashed) 3fo Reflector
O ptim ized for 3fo Output (d otted )............................................................................................................... 486
Figure B .17.2fo Conversion Gain versus 3fo Input Reflector Length for M odel A,Case B l .............487
Figure B .18.3fo Conversion Gain versus 3fo Input Reflector Length for M odel A,Case B l .............487
Figure B.19. Pin vs. Conversion Gain for M odel A, Case B l - Comparison o f Response with: No
Input R eflector (solid); 3fo Reflector Optimized for 2fo Output (dashed) 3fo Reflector
Optimized for 3fo Output (d otted )...............................................................................................................488
Figure B.20. 2fo Conversion Gain versus 3fo Input Refleetor Length for M odel A,Case C l ............. 488
Figure B .21.3fo Conversion Gain versus 3fo Input Reflector Length for M odel A,Case C l ............. 489
Figure B.22. Pin vs. Conversion Gain for Model A, Case C l - Comparison o f Response with: No
Input R eflector (solid); 3fo Reflector Optimized for 2fo Output (dashed) 3fo R eflector
Optimized for 3fo Output (d otted )............................................................................................................... 489
Figure B.23. ADS Schem atic o f M odel B ............................................................................................................... 490
Figure B.24. A D S Schem atic o f M odel C _2...........................................................................................................491
Figure B.25. ADS Schem atic o f Dgd Diode M odel Used in M odelC _2......................................................... 492
Figure B.26. ADS Simulation Schem atic for Output Load and Bias S tu d y ............................................... 493
Figure B.27. Pin vs. Conversion Gain for M odel B, Cases A l, A2 and A 3 ................................................. 494
Figure B.28. Pin vs. Conversion Gain for Model B, Cases B l, B2 and B3.................................................. 495
Figure B.29. Pin vs. Conversion Gain for M odel B, Cases C l, C2 and C 3 ................................................. 495
Figure B.30. ADS Schem atic o f nfo Output Reflector Sim ulations...............................................................497
Xlll
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Figure B.31. W aveform s for M odel C_2, Case B l, Comparison o f Response W ith fo R eflector for
Optimum 2fo CG and W ithout Reflector.Pin = -7dB m .........................................................................498
Figure B .32.2fo Conversion Gain vs. Output Reflector Length (Loutf„), Case C l (VGO=Vfwd,
Vdd=Vdd„id)........................................................................................................................................................ 499
Figure B .33.3fo Conversion Gain vs. Output Reflector Length (Loutfo), Case C l (VGO=Vfwd,
Vdd=Vdd„id)........................................................................................................................................................ 500
Figure B.34. W aveform s for M odel C_2, Case C l, comparison o f response with fo reflector for
optimum 2fo CG and without reflector.Pin = -7 d B m .............................................................................501
Figure B.35. Conversion Gain vs Input Power Comparison for Case C l (VGO=Vfwd, Vdd=Vddmid)
..................................................................................................................................................................................502
Figure B.36. M ultiplier Power vs Input Power Comparison for Case C l (VGO=Vfwd, Vdd=Vddm-,d)
..................................................................................................................................................................................503
Figure B.37. 2fo Conversion Gain vs. Output Reflector Length (Loutf„), Case A2 (VGO=Vmid,
V d d = V k i).............................................................................................................................................................. 504
Figure B.38. 3fo Conversion Gain vs. Output Reflector Length (Loutfo), Case A2 (VGO=Vmid,
V dd = V k i).............................................................................................................................................................. 505
Figure B.39. W aveform s for M odel C_2, Case A2, comparison o f response with fo reflector for
optim um 2fo CG and without reflector. Pin = -7 d B m .......................................................................... 506
Figure B.40. Conversion Gain vs Input Power Comparison for Case A2 (VGO=Vmid, V d d = V k i).. 507
Figure B.41. M ultiplier Pow er vs Input Power Comparison for Case A2 (VG0=Vm id, V dd=V ki).. 508
Figure B.42. 2fo Conversion Gain vs. Output Reflector Length (Loutf„), Case A3 (VG 0=Vm id,
V dd = V rb d )...........................................................................................................................................................509
Figure B .43.3fo Conversion Gain vs. Output Reflector Length (Loutfo), Case A3 (VGO=Vmid,
V dd = V rb d )...........................................................................................................................................................510
Figure B.44. W aveform s for M odel C_2, Case A3, comparison o f response with fo reflector for
optim um 2fo CG and without reflector. Pin = -7 d B m .......................................................................... 511
Figure B.45. Conversion Gain vs Input Power Comparison for Case A3 (VGO=Vmid, V dd=Vrbd) 512
Figure B.46. M ultiplier Power vs Input Power Comparison for Case A3 (VGO=Vmid, V dd=Vrbd) 513
Figure B.47. 2fo CG vs Loutf„ Response for Design 2, Case B l: (-) with 2fo Input Reflector, (— ) w/o
2fo Input R eflector............................................................................................................................................. 522
X IV
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List of Symbols
2fo
3fo
a
a
aic
Second harmonic
frequency
Third harmonic
frequency
Chalmers Ids parameter
Incident gate power
signal at harmonic k
Clipping duration of
drain current waveform
at zero current
bk
Reflected gate power
signal at harmonic k
Drain-source
capacitance
Conversion gain
C ds
CG
Dgs
Gate-source diode
<l>
fo
G
Conduction angle
Fundamental frequency
Conductance o f
idealized diodes Dgs
and D g d in forward
conduction region
Conductance o f
idealized diodes Dos
and Dgd in reverse
breakdown region
Small-signal output
conductance
C rf
Clipping duration of
drain current waveform
at current saturation
b
Dgd
Gate-drain parasitic
feedback capacitance
Capacitance in RC
branch in PHEMT
model
Gate-drain diode
C pgd
Gb
gd
Cgd
Nonlinear gate-drain
capacitance
Gds
Nonlinear output
conductance
C gdo
Chalmers nonlinear C g d
parameter
ggs
Term in generic diode
equation
gm
Small-signal
transconductance
Cgdp
Chalmers nonlinear C g d
parameter
C gs
Nonlinear gate-source
capacitance
C g so
Chalmers nonlinear C g s
parameter
Id
Chalmers nonlinear C g s
parameter
Current into transistor
drain
lo g d
Current through gatedrain diode
lo g s
Current through gatesource diode
Ids
Drain-source current
IdSAC
AC component o f
drain-source current
C g sp
C pd
Cpdl
Cpg
C pgi
Reflection coefficient
o f input network at
frequency nfo
Drain parasitic
capacitance
Secondary drain
parasitic capacitance
Gate parasitic
capacitance
Secondary gate
parasitic capacitance
XV
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IdSAC
Maximum point o f AC
component o f drainsource current
Minimum point o f AC
component o f drainsource current
IdSA C
Minimum point o f AC
component o f drainsource current
IdSD C
DC component o f
drain-source current
IdSD C
DC component of
drain-source current
IdSR F
RF drain-source current
generator
IdSR F
RF drain-source current
generator
loss
Saturation current of
transistor
loss
Saturation current o f
transistor
Ig
Current into transistor
gate
Ig
Current into transistor
gate
Igs
Gate-source current
Igs
Gate-source current
IgSAC
AC component o f the
gate-source current
IgSAC
AC component o f the
gate-source current
IgSDC
DC component o f the
gate-source current
IgSoC
DC component o f the
gate-source current
Ij
Diode current in
generic diode equation
Ij
Diode current in
generic diode equation
Ik
Peak gate-source
current at harmonic k
Ik
Peak gate-source
current at harmonic k
Ip
Peak drain current level
Ip
Peak drain current level
Ipk
Drain current at peak
transeonductanee,
Chalmers Ids parameter
Ipk
Drain current at peak
transconductance,
Chalmers Ids parameter
Is
Diode saturation
current
Chalmers Ids parameter
Drain parasitic
inductance
Gate parasitic
inductance
Is
Diode saturation
current
Chalmers Ids parameter
Drain parasitic
inductance
Gate parasitic
inductance
L irin fo
Input reflector offset
length for nfo reflector
element
LiOnfo
Input reflector offset
length for nfo reflector
element
L i n nfo
Total offset length for a
"secondary" nfo input
reflector element
Lin nfo
Total offset length for a
"secondary" nfo input
reflector element
LL
Load-line trajectory
IdSA C
Ld
Lg
■
A.
Ld
Lg
XVI
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Pout
Power output from a
transistor or multiplier
circuit
Pref
Reflected power at the
gate
Pref
Reflected power at the
gate
RbiasX
Internal resistance of
bias-T network
Resistance in RC
branch in PHEMT
model
Chalmers RF current
generator parameter
Drain parasitic
resistance
Resistance in the gate
bias path
RbiasT
Internal resistance of
bias-T network
Resistance in RC
branch in PHEMT
model
Chalmers RF current
generator parameter
Drain parasitic
resistance
Resistance in the gate
bias path
Rdd
Resistance in the drain
bias path
Rdd
Resistance in the drain
bias path
re
Extra breakdown term
for diode equation
Gate parasitic
resistance
Generator internal
resistance
Load resistance at
output o f multiplier
circuit
Optimum load
resistance
re
Extra breakdown term
for diode equation
Gate parasitic
resistance
Generator internal
resistance
Load resistance at
output o f multiplier
circuit
Optimum load
resistance
RLopt^
Optimum load
resistance for a class A
power amplifier
RboptA
Optimum load
resistance for a class A
power amplifier
RlopV o
Optimum load
resistance for an output
harmonic mfo
RlopWo
Optimum load
resistance for an output
harmonic mfo
Rs
Source parasitic
resistance
S-Parameter
characterization
between ports j and i o f
a network
AC gate voltage level,
normalized to 1
Rs
Source parasitic
resistance
S-Parameter
characterization
between ports j and i of
a network
Rc
Rcw
Rd
Rdc
Rg
Rgen
Rl
Rbopt
Sij
V ac
Rc
Row
Rd
Rdc
Rg
Rgen
Rl
RlopI
Sij
X V ll
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Vg4155
Gate voltage applied by
curve tracer
Vgd
Gate-drain voltage
Vgd
Gate-drain voltage
V gd in t
Internal gate-drain
voltage, appearing
directly across Dgd
V gdint
Internal gate-drain
voltage, appearing
directly across Dgd
VoDrbd
Reverse breakdown
voltage o f gate-drain
diode
VoDrbd
Reverse breakdown
voltage o f gate-drain
diode
V gint
Internal gate voltage
Vg„int
Internal gate voltage
VgSAC
AC component o f gatesource voltage
VgSDC
DC component o f gatesource voltage
VgSint
Internal gate-source
voltage, appearing
directly across D gs
Vgt
DC voltage applied to
gate terminal
Vj
Diode voltage in
generic diode equation
Vk
Peak gate-source
voltage at harmonic k
Vki
Knee voltage o f
transistor
Gate-source bias
midway between Vp
and Vfwd
Pinchoff voltage
Vmid
Vp
Vpeakmin
Peak minimum gatesource voltage level
Vrbd
Reverse breakdown
voltage o f transistor
Voltage drop across
Rdc
Source voltage applied
by curve tracer
VRdc
VS4155
VSint
Internal source voltage
V St
DC voltage applied to
source terminal
Vt
Thermal voltage
X V lll
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Guide to Input and Output Bias Voltages and Input
Signal Levels Studied in This Work
The table below is a summary o f the bias points and input signal levels utilized for the
majority o f this work and Chapter 3 in particular. It is recommended that this page be
detached for quick reference since these cases are referred to very frequently throughout
this work.
Gate Bias
(VGO)
Gate Bias
Value (V)
Drain Bias (Vdd)
Drain Bias
Value (V)
Pin
(dBm)
AO input
Voltage Mag
(Vg)t
A ll
V p/2=V m id
-0 .3
(Vrbd+Vki)/2=Vdd_^.^
2.5
-7
IV p R
A 12
V p/2=V m ld
-0 .3
(V rbd+ V ki)/2= V dd^.j
2.5
-1
IVpl
A 1.3
V p/2=V m ld
-0.3
(V rbd+V kl)/2=V dd,^,j
2.5
5
2 '|V p |
A2.1
A 2.2
A 2.3
A3.1
A 3.2
A 3.3
V p/2=V m id
V p/2=V m id
V p/2=V m ld
V p/2=V m ld
V p/2=V m ld
V p/2=V m id
-0 .3
-0 .3
-0 .3
0.5
-7
-1
5
-7
IVplf2
iVpi
2*|Vp|
-0 .3
-0 .3
-0 .3
0.5
0.5
4 .5
4 .5
4 .5
-1
5
m n
IVpl
2 ’ IVpl
m 2
C ase Description
Label*
(A1) Midway Bias Gate
Midway B ias Drain
(A2) Midway B ias Gate
Knee Voit. Bias Drain
(B1) PlnchofTBias Gate
B1.1
Vp
-0 .6
Vkl
Vki
Vki
V rbd
V rbd
V rbd
(V rbd+V kl)/2=V dd^,^
2.5
-7
Midway B ias Drain
B 1 .2
Vp
-0 .6
(V rbd+V kl)/2=V dd^.^
2.5
-1
IVpl
8 1 .3
Vp
-0 .6
(V rbd+V ki)/2=V dd^.^
2.5
5
2*lVpl
B 2.1
B 2 .2
B 2 .3
Vp
Vp
-0 .6
-0.6
-0 .6
-0 .6
-0 .6
-0.6
Vki
Vkl
Vkl
0.5
0.5
0.5
iVpi/2
V rbd
V rbd
4 .5
4 .5
(A3) Midway B ias Gate
R everse BD B ias Drain
(B2) PinchofTBias Gate
Knee Voit. Bias Drain
(B3) PinchofTBias Gate
R everse BD B ias Drain
B3.1
B 3 .2
B 3 .3
Vp
Vp
Vp
Vp
4 .5
(01) Forward Cond-
C 1.1
Vfwd
0
V rbd
(V rbd+V kl)/2=V dd^.^
-7
-1
5
-7
-1
5
2.5
-7
Bias Gate
C 1 .2
Vfwd
0
(V rbd+V ki)/2=V dd^,,,
2.5
-1
IVpl
Midway B ias Drain
(02) Forward OondBias Gate
Knee Voit. Bias Drain
(03) Forward OondBias Gate
R everse BD Bias Drain
C 1 .3
Vfwd
0
(V rbd+ V kl)/2= V dd^,j
2.5
5
2*|Vp|
0.5
0
Vkl
C 2.1
Vfwd
0.5
0
Vki
C 2 .2
Vfwd
0.5
C 2 .3
Vfwd
0
Vki
4 .5
C 3.1
Vfwd
0
V rbd
4 .5
C 3 .2
0
V rbd
Vfwd
4 .5
C 3 .3
Vfwd
0
V rbd
* N o te th a tin c e rta in c a s e s th e input p o w e r level Is sw e p t, a n d in th e s e in s ta n c e s th e c a s e s a r e g e n erlc aiiy
to a s C a s e A l , C a s e B 1 , e tc . T his In d ic a te s th e g a te a n d d rain b ia s for a n Input p o w e r s w e e p
-7
-1
5
-7
-1
5
re fe rre d
tE a u iv a le n t V a to a lv e P in (aoprox)
X IX
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
IVpl
2*|Vpi
m 2
IVpl
2*|Vp|
|Vplf2
IVplf2
IVpl
2*|Vp|
m 2
jVpi
2”|Vp|
Theory and Design o f Active
Microwave Frequency Multipliers
By
JESSI ERNEST-JEROME JOHNSON
XX
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Chapter 1.
Introduction and Background
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1.i. Introduction
An active frequency multiplier is a component commonly used to provide high
frequency signals in an electrical system. It utilizes the nonlinear properties o f an active
device such as an HBT, MESFET or HEMT transistor to generate higher-order
harmonics o f a low frequency input signal. Active frequency multipliers have the
potential not only to increase the frequency o f an input signal, but also to raise its power
level. This property o f an active multiplier is characterized by the ratio o f the output
power at the desired harmonic frequency (Poutnfo) to the input power at the fundamental
frequency (Pinfo), and is called conversion gain (CG).
An active frequency multiplier can be utilized as a cost efficient building block in the
design o f signal sources and communication systems. In a system where a high
frequency signal is necessary a frequency multiplier can be utilized with a lower
frequency signal source. This can provide a significant cost advantage over directly
implementing a signal at a high frequency.
Another advantage o f active frequency multipliers is that they can be designed for
significant amplification o f the input signal. Thus, a system utilizing passive or low
conversion gain multipliers in combination with an amplifier can be streamlined by
replacing it with a single, large conversion gain, active frequency multiplier.
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1.H. Applications
The utility o f frequency multipliers is best conveyed by observing some real world
applications. The first example utilizes two frequency doublers in the implementation o f
a high-frequency signal source [1]. Figure 1.1 shows the block diagram o f the signal
source.
94GHz
Output
Amplifier
23.5-47GHz
Doubler
Amplifier
47-94GHz
Doubler
Figure 1.1. Block Diagram o f 94GHz Frequency Source Presented by [1]
C ;\Research\F igures\Ckts\wang_94ghz_freq_source.ai
This design utilizes a 23.5GHz voltage-controlled oscillator as a local source,
followed by a buffer amplifier. The 23.5GHz signal is then raised to 47GHz by a
frequency doubler and followed by another amplifier. Finally, a 47 to 94GHz frequency
doubler is used to achieve the desired 94GHz output. The two active frequency doublers
allow a 23.5GFlz oscillator to be utilized rather than designing an oscillator directly at
94GHz.
In the second example, several frequency doublers are utilized in a transceiver system
[2]. A block diagram o f the downconverter section o f the transceiver is shown in Figure
1.2. Similar to the previous example, this design uses a frequency doubler in order to
utilize an 1 IGFIz local oscillator in a 22GHz system.
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Mixer/Downconverter
20GHz
RF Input
LNA
IF
'Output
—►
t~ D > "
i ‘ LO
In 3Ut
BPF
BPF
Amplifier
Frequency
Doubler
Chain
11-22GHz
Doubler
Amplifier
11GHz
Figure 1.2. Block Diagram o f Downconverter System Presented by [2]
C:\Research\Figures\Ckts\lester_downconverter_bd_2.ai
Mixer/Downconverter
IF
'Output
20GHz
RF Input
LNA
LO
put
BPF
BPF
-3 H Large CG
Doubler
11-22GHz
I
Pad
Frequency
Doubler
Chain
I
I
-T LO
11GHz
Figure 1.3. Improved Downconverter System Utilizing Large CG Frequency Doubler
C :\Research\F igures\Ckts\lester_downconverter_bd_improved_2.ai
This design can also be used to show the possible advantages o f utilizing an active
frequency multiplier design with large conversion gain. If the second harmonic
conversion gain o f the doubler used in the frequency doubler-chain (Figure 1.2) could be
improved, the amplifiers could be eliminated. This would result an improved system,
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demonstrated in Figure 1.3. In this improved system, the use o f 2 amplifiers is
eliminated, resulting in savings o f chip space and DC power consumption. These savings
show the possibilities o f significantly improving a system’s efficiency with the use o f an
active frequency multiplier.
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1.iii. State of the Art
Several techniques for designing active frequency multipliers have been developed
over the years. Maas [3] presents a technique for multiplier design utilizing an input bias
level close to the pinch-off voltage o f a FET/HEMT transistor. When an AC voltage is
input into the transistor, the bias near pinchoff causes the transistor to switch on and off.
By varying the input bias around the pinchoff voltage and changing the AC input voltage
level, the time duration for which the transistor is turned on is varied. This time duration
o f transistor conduction, or conduction angle, varies the amount o f clipping occurring on
the transistor’s output. The resulting output current is a single-sided, clipped, sinusoidal
waveform which contains harmonic multiples o f the fundamental input frequency. Using
a Fourier analysis o f this single-sided, clipped sinusoid, the amount o f output current at
each harmonic can be calculated as a function o f the conduction angle. This allows input
bias and AC input voltage combinations for optimum output current (and subsequently
output power) to be found for each harmonic.
Fudem and Niehenke [4] present a technique to design frequency multipliers utilizing
double-sided, clipped output current waveforms. In this technique, the input o f a
PHEMT transistor is biased midway between pinchoff (Vp) and the forward conduction
voltage o f the gate-source diode (Vfwd). When the magnitude o f the AC input signal is
raised high enough, the gate-source voltage swings below pinchoff (on the low side) and
to the forward conduction voltage (on the high side). The transistor is turned o ff when
the gate-source voltage swings below pinchoff and is saturated (Ids=lDss= the saturation
current) when the gate-source voltage swings up to forward conduction. The
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corresponding output current waveform is a double-sided, clipped sinusoid. A Fourier
analysis o f this waveform reveals that it has strong odd-order harmonic content and no
even order harmonic content. A very large AC input signal is shown to create an output
current waveform closely resembling a square wave, which produces a large third
harmonic output.
O’Ciardha et al [5] present a generalized design technique to calculate the output
current harmonic content for an arbitrary input bias and AC input voltage. This
technique encompassed both single and double-sided clipping o f the drain current. The
technique led to discovery o f several input signal and bias combinations giving an
improved 2fo and 3fo output current level.
Other works expand on the above designs to include the output voltage and current
(not simply the current) by exploring the effects o f the choice o f load on the output o f the
transistor. Camargo [6] analyzes a frequency multiplier configuration using a load R l
with a parallel LC filter. He provides an analysis o f variation in the load resistance Rl,
and describes the expected effect on the output current and voltage waveforms. This
analysis defines the optimum choice o f load for an output current at a given harmonic
(n*fo).
Multiplier techniques are expanded further by considering not only the load presented
to the desired output harmonic, but the loads seen at the input and output o f the transistor
for several harmonic frequencies. Rauscher [7] utilizes a GaAs PET transistor to design a
frequency multiplier with a gate bias near pinchoff. At the input o f the device a variable,
reactive load is presented at the second harmonic (2fo). On the output a variable, reactive
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8
impedance is presented to the fundamental frequency (fo). These reactances are varied in
a computerized simulation to adjust and maximize the second harmonic conversion gain.
Beaulieu [8] utilizes an HBT transistor in a practical frequency tripler design. The
design uses a fundamental frequency impedance match at the input o f the transistor.
Additionally, the input circuit has a low-pass response which suppresses the higher order
harmonics. At the output o f the device an impedance matching circuit is designed to
match the transistor’s output impedance at 3fo. The output circuit has a high-pass
response which suppresses the fundamental and second harmonic.
El-Rabaie et al [9] utilize a realistic MESFET device model with an optimization
routine to design a frequency doubler with maximum output power at a fixed input
power. They utilize small-signal impedance matching on the input (at fo) and the output
(at 2fo), and optimize the offset length o f a fundamental frequency short circuit on the
transistor’s output.
From the U.C. Davis microwave laboratory, Thomas [10;11] utilizes and greatly
expands the techniques previously presented above and presents a unified design
technique. This technique consists o f several steps in multiplier development. The first
step is to select a device based on its performance characteristics, and then to develop an
accurate model for the device. Second, optimum bias point and input power levels are
chosen utilizing the model or measured data. Third, responses for the input and output
networks (at each harmonic) are developed. This consists o f simulating the device model
with various input and output load combinations and tabulating the results to find
optimum network configurations. Also, the use o f “reflector” networks is explored.
These reflector networks utilize typically unused harmonic power (for example the output
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power at fo, which is typically filtered out) at the output and the input o f the transistor by
reflecting them back into the device. A study o f the effects o f varying the phase o f these
reflected signals is conducted. Fourth, the optimized input and output network designs
are synthesized to “realize the prescribed impedances.”
Since the work o f Thomas, several other authors have presented generalized design
techniques. Colantonio et al [12] utilize a Materka MESFET model in a frequency
doubler design technique using their own harmonic balance simulator. The design
features a bias near the pinchoff voltage at a fixed input power level. The input network
provides an impedance match at the fundamental frequency and a variable, reactive
impedance at the second harmonic. The output network provides an impedance match at
2fo and a variable, reactive impedance at the fundamental. The reactive impedances are
varied to maximize the second harmonic conversion gain.
Kompa et al [13] utilize a very similar technique to Colantonio. A frequency doubler
is designed by utilizing a fo reflector at the output a realistic device model, as well as a
2fo reflector at the input. The phase o f the reflection coefficient o f the input and output
reflectors is varied to show the variation in the corresponding 2fo conversion gain. In
another work by Kompa et al [14], a similar approach is presented for frequency triplers.
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10
1.iv. Description of Research
In the current state o f the art described in the previous section, some serious
shortcomings can be seen. The initial works (Maas, Fudem, O’Ciardha, etc) utilize a
highly idealized device response to define a basic design procedure. They assume that
the input and output networks (if any) serve only to reject and filter out the unwanted
harmonics present in the multiplier circuit.
The more advanced works (Thomas, Colantonio, Kompa, etc) utilize a full device
model (representative o f an actual device) and complex input and output networks which
are manipulated to provide an optimum response. In order to fully understand the
processes involved in frequency multiplier design and to further expand and characterize
existing idealized design principles, a new approach is necessary.
In the following work, generalized and idealized techniques for designing frequency
multipliers are presented. In Chapter 2, the development o f a practical, large-signal
device model is presented. The chapter presents an extensive characterization o f a
PHEMT transistor, including DC, small-signal, and large-signal measurements. A novel
technique for developing a generalized model which is accurate over changes in DC bias,
input power level, and fundamental frequency is presented.
In Chapter 3, the realistic device model components are stripped away, leaving a
basic, highly idealized device model. Utilizing this idealized model, basic design
techniques are verified by computer simulation. By utilizing simulation, these techniques
are not only verified, but a concise understanding o f the mechanisms causing the
multiplication is gained. Once again utilizing simulation o f the idealized model, more
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11
complicated design techniques in which the networks on the input and output o f the
device are manipulated are explored. Through this study, a crucial missing link between
basic design techniques (utilizing only an idealized model, with no input or output
network manipulation) and complex design techniques (utilizing extensive input and
output network manipulation in a realistic device model) is provided. Furthermore,
Chapter 3 presents novel design techniques to design for large conversion gain and output
power simultaneously.
In Chapter 4 the realistic device model is re-introduced and utilized in doubler and
tripler designs which make use o f the design principles discussed in Chapter 3. Some
practical designs are fabricated and tested, showing large conversion gain. This includes
a 3 to 9GHz multiplier with the largest conversion gain ever reported in a tripler.*
Chapter 5 gives a summary o f the work presented and provides some suggestions for
further research.
B ased on perusal o f a large body o f literature.
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12
Chapter 2.
Generalized Nonlinear FET/HEMT
Modeling
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13
2./. Introduction
Development o f general CAD techniques for design o f frequency multipliers requires
a general model which gives a sufficiently accurate nonlinear response. Such a model
possesses several desirable properties:
1. Utilizes a sufficient set o f measured data, including nonlinearity effects
manifest at both the input and output o f the device via the input, output, and reflected
powers.
2. Generality in the sense that it is accurate for changes in bias, input power level,
and fundamental input frequency.
The first requirement o f the model is that it utilizes a sufficient set o f measurements.
Many authors utilize the S-Parameters, along with DC curves, in the optimization o f
nonlinear FET/HEMT models [16]. However, reliance on small-signal measurements to
design a large-signal model can be indirect and problematic [17]. Sandier et al [18]
utilize an expanded set o f measurements which include the magnitude o f the large-signal
output power at the first three harmonics versus the input power. They perform a
simultaneous optimization o f the DC drain current, S-Parameters, and large-signal Pin
versus Pout at several discrete bias levels and fundamental frequencies for a range o f
input power levels.
The advance o f new, state o f the art measurement systems such as the Nonlinear
Network Measurement System (NNMS) [19] and Microwave Transition Analyzer
(MTA) [20], capable o f measuring large-signal magnitude and phase data both at the gate
The information in Section 2.i, from pages 1 3 - 1 6 , w as published in [15] by this author.
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14
and drain o f a FET/HEMT, have raised new possibilities for the model optimization
problem.
Werthof et al [21] utilized these extended large-signal measurements [22] by conducting
a model optimization o f the magnitude and phase o f the large-signal output power versus
the input power. Schreurs et al [17] present an empirical model, using the Chalmers
implementation (note that the Chalmers model refers to the work o f Angelov [16], to be
discussed in detail below), which is optimized utilizing magnitude and phase data at the
drain and the gate for a large signal excitation at the gate. For a large-signal,
fundamental frequency excitation at the gate the magnitude and phase o f the incident and
reflected waves at the gate and drain were directly measured and used in model
optimization.
A model which also accounts for nonlinearity at the input of the device, such as
reported in this paper, is an important requirement. Specifically, reflected harmonic
power at the gate o f a device is a vital consideration in the design o f an input network o f
a frequency multiplier [23]. Although the optimization using these advanced, largesignal, vectorial measurements is advantageous, the equipment for performing these
measurements may not be readily available. However, the large-signal magnitude o f the
reflected power at the gate is readily available for measurement on common laboratory
equipment. In the following work this information was obtained by the addition o f a
precision, high directivity directional coupler and additional spectrum analyzer to a
traditional large-signal measurement system. Although the large-signal phase
information was not available using this method, the system was able to be implemented
with the use o f common laboratory equipment and presented a viable alternative to the
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15
use o f an NNMS to characterize the large-signal response at the input o f the transistor.
Phase information was obtained by measuring the S-parameter response o f the device and
including it in the optimization o f the model. By utilizing the extended large-signal data
and supplementing it with the DC and S-Parameter response, a high-fidelity, generalized,
large-signal model was obtained which sufficiently accounts for the nonlinear response at
the gate.
The second requirement o f the model is that it should have generality. Several authors
have presented nonlinear device models with various levels o f generality. Handler et. al.
[18] present a MESFET model optimized for DC (two bias points), S-Parameters (2 bias
points, 8 frequencies), and large-signal Pout versus Pin (3 harmonics, 3 input power
levels, 2 fundamental frequencies). The model response is shown to be very accurate for
Pout (fo, 2fo, 3fo) vs. Pin (fo) for one fundamental frequency and bias level (see fig. 4 in
[18]). The S-parameters S22 and SI 1 show a close response over a range o f frequencies
at one bias (see fig. 5 in [18]).
Angelov et al [24] present a PHEMT model optimized for DC (over a wide range o f
bias points) and S-Parameters (at several bias points over a range o f frequencies). The
model response is shown to be very accurate for DC and S-Parameters over a wide range
o f bias levels and frequencies (see figs. 3, 6, 7, 10, 11 in [16] and fig 15 in [24]). The
model is also shown to be accurate for the large-signal Pout(fo, 2fo, 3fo, 4fo) versus
Pin(fo) response for one fundamental frequency and input power level over a wide-range
o f DC bias levels at the gate and drain (see figs. 16 and 17 in [24]).
Fernandez-Barciela et al [25] present a model which also utilized DC and S-Parameter
measurements over a wide range o f bias levels and frequencies. The Y-Parameters are
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16
shown to be accurate over a wide bias range for a frequency o f 2GHz (see figs 4 and 5 in
[25]). The S-Parameters are shown to be accurate over a very large frequency range at
several bias points (see figs. 6, 7, 8 in [25]). The large-signal Pin(fo) versus Pout(nfo)
response is also shown to be accurate for four different bias level, fundamental frequency
combinations (see figs. 9-11, 14 in [25]). The authors also note that excellent results
were also achieved for a fundamental frequency range 2-20 GHz.
Although all o f the above models show some generality over variations in input power
level, bias, and frequency, the objective o f this work is to present, for the first time in the
published literature*, measured large-signal responses over variations in all three
variables as will be illustrated in Section 2.ii and present a model which has an accurate
response over all three variables and includes the nonlinear response at the gate as will be
illustrated in Section 2.iii.
The efficacy o f the modeling technique as compared to current techniques, including
the techniques described above, is summarized in Table 2.1. The table gives a brief
summary o f the models previously discussed above, as well as several other commonly
utilized models. The Curtiee-Ettenberg model [26] predicts the large-signal output versus
input power response at the first and second harmonic. The large-signal response is
shown at only one fundamental frequency and bias point. The Materka-Kacprzak model
[27] also predicts the large-signal output versus input power response, but only shows the
output power at the fundamental frequency. This model also only includes the response
at one fundamental frequency, however it utilizes several discrete gate and drain bias
points. Statz [28] shows a model optimized to measured DC-IV and nonlinear
capacitance data only. The large-signal response is not shown. The Triquint (TOM)
This is our finding based on a perusal o f a great body o f literature
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17
model [29] shows optimized DC-IV curves and presents the large-signal output power at
a single input power, fundamental frequency, and bias point. The Root model [30]
presents an optimized large-signal output versus input power response for the first three
harmonic frequencies. Several discrete DC bias points are shown, and a single
fundamental frequency is utilized.
Table 2.1. Sum mary o f Nonlinear M odeling Designs Presented in the Literature
B a n d w id th S how n
Year
B ia s e s S how n fo r L S R estrns
G a te B ia s
V a lu e s
D ra in B ia s
V a lu e s
R e fle a e d
P ower
H arm o n ic s
Included
S in g le F re q .
Only
-1 V
8V
N on e
fo ,2 fo
D C IV, P In v s .
Pout
No
10 to 2 0 d B m
S in g le F re q ,
Only
-.7 5 V .-1 .2 5 V
3 ,4 ,5 V
N on e
fo
D C IV, P In v s .
P o u t.S P a ra m e te rs
No
0 to 16 d B m
N ot Shown,
N ot
M e n tio n e d ,
U nknow n
N ot A p p lic a b le
N o t A p p lic a b le
N on e
N one
D C IV and
C g s .C g d
re s p o n s e only
No
N o t A p p lic a b le
S in g le F re q .
O nly
0 to 4 V
-,5 to + .7 V
N on e
fo
No
P in r e q d .fo r
Id B
c o m o re s s io n
S in g le F re q .
Only
T w o gate
b ia s e s (value
iin s n e d fle d l
2 .5 , 5 ,7 V
N on e
fo . 2( 0 , 3 fo
No
P o u t = 2 to 22
dBm
No
-1 5 t o + 1 0 d B m
No
10 to 3 0 d B m
Y es
0 dBm
No
-2 0 .4 t o -3 .4
dBm
S m a ll S ig n a l (S - L a rg e S ig n a l
P a ra m e te rs )
(P o u t vs. P in)
M odel
N o t S h ow n, N ot
M e n tio n e d ,
1 Inknow n
N o t S h ow n, N o t
1 9 8 5 M a te rk a -K a c p rz a k "
M e n tio n e d .
U nknow n
1 9 8 5 C u rtlc e -E tte n b e rg i
N o t S h ow n, N o t
M e n tio n e d .
U nknow n
O u tp u t P o w e r M e a s u re m e n ts
Tem p
H arm o n ics W h ic h M o d e l Is E ffe c ts
Included
B a s e d On
In cluded
1987
S ta tz iii
1990
M c C a m a n t, e ta l.
(T O M M odel)™
1991
R o o t"
1991
B a n d le r"!
175%
S in g le F re q .
Only
- ,3 7 V ,-1 .0 6 V
2 V .6 V
N on e
fo , 2fo, 3 fo
1993
W e rttio f""
N o t S h ow n, N o t
M e n tio n e d .
U nknow n
S in g le F re q .
Only
S in g le V alue
S in g le V a lu e
N on e
fo , 3fo
1999
A n g e lo v "!!!
200%
S in g le F re q .
Only
-1 to +.4 V
0 to 4 5 V
N on e
fo , 2 fo, 3fo,
4 fo
N o t S h ow n, N o t
M e n tio n e d .
U nknow n
N o t S h ow n, N ot
M e n tio n e d ,
U nknow n
U p t o 5 * f o v la U p t o 5 * f o v la
drain
g a te
w av e fo rm s
w av e fo rm s
2C 00
S c fire u rs (u s in g a
C h a lm e rs m o d e l)!*
N o t U s ed
S in g le F re q .
Only
-0 .5 V
15 V
2C 00
F e rn a n d e zB a rc ie la , e ta l*
200%
U nknow n
- I V , OV
IV , 1 5 V
In d ire ctly via
g ate
w av e fo rm s
fo , 2fo, 3fo
2003
T h is W o rk
87%
67%
-0 .6 t o + 0 .3 V
25V
fo , 2 fo , 3 fo
fo , 2fo, 3fo
D C IV, S m a ll
S ig n a l R d s , P o u t
(s in a le P Inl
D C IV, S P a ra m e te rs , P in
vs. P o u t
D C IV, SP a ra m e te rs , P in
vs. P o u t
D C IV. P In v s .
P o u t (Including
b h a se )
D C IV, SP a ra m e te rs , P in
vs P o u t
G a te a n d d ra in
L S w a v e fo rm s
Input P o w e r
R ange
D C IV, SP a ra m e te rs , P in
vs . P out, g a te Unknow n -3 0 t o + 2 0 d B m
a n d d ra in L S
w a v e fo rm s
D C IV, SP a ra m e te rs , P in
No
4 to 10 d B m
vs . P o u t. P re fv s .
Pout
(i) See R eference [26]; (ii) See Reference [27]; (ill) See R eference [28]; (iv) See R eference [29]; (v) See
R eference [30]; (vi) See R eference [18];(vii) See R eference [21]; (viii) See Reference [16]; (ix) See
Reference [17]; (x) See Reference [25].
File: C:\Research\Papers\ijmiccad2003\reedited_version\TableA_pubIished_model_summary.sxc
Bandler [18] presents a model which considers the DC-IV, small-signal, and largesignal response. The model predicts the measured large-signal output versus input power
response for the first three harmonies. Like the Root model, Bandler shows the largesignal response at several discrete bias points and a single fundamental frequency. This
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18
model also includes the small-signal S-Parameters over a 75% bandwidth. Werthof s
model [21] predicts the measured large-signal output versus input power response at the
fundamental and the third harmonic. It includes a prediction o f the phase o f the output
power. This large-signal response is shown at a single bias and fundamental frequency.
The Chalmers model (by Angelov et al [16]) greatly expands on the previous modeling
techniques. They present a model which accurately predicts the DC-IV response. It also
gives an accurate measured versus modeled S-Parameter response over a 200%
bandwidth. The large-signal response o f the model is also shown to accurately predict
the output power for the first four harmonics. The large-signal output power response is
shown over a range o f gate-source and gate-drain bias values, at a single input power and
fundamental frequency. Schreurs et al [17] show a model which utilizes the Chalmers
equations to accurately predict measured nonlinear waveform trajectories (such as the
response o f the drain current Ids(t) plotted versus the drain voltage Vds(t)) over a range
o f input power levels. The response is shown at a single bias and fundamental frequency.
Fernandez-Barciela et al [25] show a model optimized for the small-signal and largesignal response. The model predicts the measured S-parameters over a 200% bandwidth.
The model also predicts the measured large-signal output versus input power response for
the first three harmonics. The response is shown at several discrete bias points for a
single fundamental frequency.
This work expands on these previous techniques. It shows a model which accurately
predicts the measured DC-IV, small-signal, and large-signal response. The model shows
unprecedented generality by accurately predicting the measured large-signal output and
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19
reflected response versus the input power, gate-source bias, and fundamental frequency.
It includes the response at the first three harmonics.
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20
2.i7. Device Measurements on Improved System
2.ii.a. Overview*
An extensive set o f DC IV, S-Parameter, and large signal measurements were
conducted on a set o f representative Agilent ATF36163 PHEMT transistors. The DC
drain-source, gate-source, and gate-drain currents were measured on an HP4155
parameter analyzer for the bias range Vgs = -1 to +1V and Yds = 0 to 4.5V. The SParameters were measured on an HP8510 network analyzer over a frequency range o f 1
to 26GHz for a drain bias Yds = 2.5V and several gate bias levels from Vgs = -0.6 to
0.2V. Finally, the large signal measurement system was set up to measure the output and
reflected power at the first three harmonics for a swept input power (Pin = -10 to +10
dBm), fundamental frequency (fo = 2-6 GHz), and bias voltage range (Vgs = -0.6 to
+0.4V, Yds = 2.5V).
The information in Section 2.ii.a w as published in [15] by this author.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
21
2.ii.b. DC Measurements
HP 4155A Semiconductor
Parameter Analyzer
V94155
+
VGO
-
-
V dd
/
+
biasT
50n
Term
Bias-T
RF+DC
DC
500
Term
RF
source
DC
DC
Bias-T
DC
Vd,
v g.
FET/HEMT
RF
500
Term
Bias-T
Figure 2.1. DC M easurement Setup
C:\Research\Figures\4155 Measurement Setup 3.ai
Figure 2.1 shows the measurement setup for measuring the DC IV curves o f the
transistor using an HP4155 semiconductor parameter analyzer. The inlay shows the DC
components o f the PHEMT model, which includes the gate-source and gate-drain diodes
(Dgs and Dgd), parasitic resistances (Rj, Rg and Rd), and the drain-source current generator
(Ids). The details o f the model are discussed in detail in Section 2.iii, however, the DC
response o f each o f these elements must be considered when making the DC
measurements. Also note in the figure that the bias-Tees are used to present a 50 ohm
AC load at the terminals o f the transistor. This helps to ensure device stability. Finally,
note that the device is tested by applying various gate and drain DC voltage levels
(denoted Vg 4 i5 5 and Vd4 i5 5 ), while keeping the source voltage (VS4 1 5 5 ) at zero. The
resulting “external” applied voltage level at the gate is denoted VGO, and at the drain is
denoted Vdd, as shown in the figure.
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22
When measuring the IV curves o f the PHEMT, the parasitics Rs, Rd and Rg each cause
a voltage drop which affects the “internal” voltages applied to the gate and drain o f the
intrinsic device. Assuming the gate current is small, these “internal” voltages can be
calculated as [31];
( 2 .1 )
= V d,-Id(R ^ + R ,)
(2.2)
Where Vgt and Vdt are the voltages appearing at the device terminals and VgSint and
Vdsint are the internal voltages, as shown in Figure 2.1. An additional voltage drop
occurs across the bias-Tees, which have a small resistance (Rbiasx) associated with them.
Considering this voltage drop, and assuming the resistance of each bias-T is
approximately the same, the internal voltage is given as a direct function o f the voltages
applied by the 4155:
VgSinx = ^^4155 - i d
+ R^) = FGO - I d
Id{^R^ + R^ + 2R^-^^j^ = V d d - Id{^R^ +
+R^)
+
( 2.3 )
(2 .4 )
As a result o f Equation ( 2.3 ) and ( 2.4 ), a couple o f conclusions can be drawn. The
first is that the parasitic resistances can cause significant deviation between the intrinsic
(VgSint and Vdsmt) and the applied extrinsic (VGO and Vdd) voltages. This deviation is
shown to be greater than 5% in some cases, as shown in the calculation in Appendix
A.i.a. The second is that the application o f the correction results in an unequally spaced
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23
array o f intrinsic voltages, as described in [31]. This can make model implementation
and optimization difficult, as will be addressed in Section 2.iii.c.
In the course o f making these measurements, several other interesting conclusions
were reached. The first and perhaps most important discovery was that the variation
from part to part in the transistor was very significant. PHEMTs which came from
different lots could vary in drain-source current by as much as 20-25 mA at any given
bias point. In previous research at the UC Davis microwave laboratory [32;33], small
samples o f transistors which came from the same lot were used. When the sample ran
out, a new sample was used and it was assumed that the new sample had an
approximately equivalent response. This however was not a good assumption, and was a
significant source o f error in the modeling work. As a result, a large batch o f transistors
all coming from the same lot was obtained and used for the remainder o f the research
presented here. It is also worth noting that, even in a large batch o f PHEMTs coming
from the same lot, there was significant variation in the drain-source current o f up to
10mA. This discrepancy is also a significant source o f error.
The large-signal response o f a PHEMT depends largely on its DC response.
Depending on the choice o f input power level, the gate voltage swing on the input o f the
transistor may be quite large (up to around 2V maximum for this work). In previous
research at the UC Davis microwave laboratory [32;33], the IV curves o f the transistor
model were only optimized to match gate voltages up to OV. This may have caused
another source o f error in the previous model, especially for large input power levels. In
this work, the IV curves o f the transistor were measured over an extended voltage range
at the gate and the drain (VGO = -1 to +I V, Vdd = 0 to 4.5 V) to allow the creation o f a
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24
model which matched measured DC data over a larger range. Another improvement in
the DC measurements was to measure the IV curves using a smaller VGO and Vdd step
size, to allow a more accurate calculation o f the derivatives of the drain current (gm and
gd). Finally, a sample o f four transistors was measured to allow an average dataset to be
collected. Figure 2.2 shows the results o f the DC measurements; the response o f the four
transistors, along with the average is shown. Note that the figure uses the external
voltages, since the internal voltages are unequally spaced as described above.
o
o
o
o
-1+
+
-1-----------------
xtr36a-1
xtr36a-1
xtr36a-1
xtr36a-1
xtr36a-2
xtr36a-2
xtr36a-2
xtr36a-2
xtr36a-3
xtr36a-3
xtr36a-3
xtr36a-3
0 xtr36a-4
0 xtr36a-4
❖ xtr36a-4
0 xtr36a-4
+ xtr36a-avg
xtr36a-avg
+ xtr36a-avg
xtr36a-avg
C urves
S 0 .0 4
0^9
2
2 .5
Vdd (V)
3
Figure 2.2. IV Response o f 36163 PHEM T Transistors
C:\R esearch\l_B_l UndrstndngNL Mech\A Actl Dvce Char\i Dvce M eas\DC\36163axtr 8_21_02\Final DC Data
xtr36a\comparison2.fig
DC characterization o f the PHEMT also included measurement o f the gate-source and
gate-currents attributed to the gate-source and gate-drain diodes, Dgs and Dgd. The
method for characterization o f the diodes is based on observation o f the equivalent circuit
model for the PHEMT at DC, shown in Figure 2.1. As previously discussed, the
equivalent circuit model used in this research has six DC only components Rs, Rd, Rg,
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
25
D gs, D gd,
and Ids. When conducting D C measurements on the transistor, all six o f these
components are necessarily measured. In the D C Ids versus Yds and Vgs measurements
described above, the device was measured in a region where there was very little current
flow through D g s and D g d . However, if the values o f the parasitic resistances
R g, R d ,
and
Rg are known (note that here these have been set equal to the manufacturer’s data as
explained in Appendix A.i.a) and the drain-source current generator can be set to produce
a very small current, then the IV response o f Dgs and Dgd can be determined from
measurements. Utilizing the above technique, the IV response o f Dgs and Dgd was
measured for the PHEMT. Further details about the measurement setup are shown in
Appendix A.i.b.
Figure 2.3 and Figure 2.4 show the measured response o f the gate-source diode, Dgs.
0.01
0.008
0.006
xtr36a-1
xtr36a-2
xtr36a-3
xtr36a-4
xtr36a-avg
— 0,004
0.002
0.6
0.7
VgSin, (V)
Figure 2.3. Measured IV Response o f Dg, in Forward Conduction Region
C:\R esearch\l_B_l Undrstndng NL Mech\A Actl Dvce Char\i Dvce Meas\DC\36163a xtr
8_21_02\Diode_Measurements\xtr36a_Dgs_meas_fwd.fig
Figure 2.3 shows the IV response o f Dgs in the forward conduction region o f operation
and Figure 2.4 shows the response in the reverse-breakdown region. As the figures show.
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26
the response was measured for each o f the four sample transistors used for the D C
measurements shown in Figure 2.2. The response for the gate-drain diode
(D g d )
IV
was
similar to Dgs, and is shown in Appendix A.i.b.
-
0.002
-0.004
^
-0.006
(/)
^
-0.008
-
0.01
-
0.012
-
0.01
•
+
□
xtr36a-1
xtr36a-2
xtr36a-3
xtr36a-4
xtr36a-avg
-3.5
Figure 2.4. Measured IV Response o f Dg, in Reverse Breakdown Region
C:\Research\l_B_l Undrstndng NL Mech\A Actl Dvce Char\i Dvce Meas\DC\36163a xtr
8_21_02\Diode_Measurements\xtr36a_Dgs_meas_rev.fig
2.ii.c. AC Measurements
2.U .C .I.
S-Parameter Measurements
The S-Parameters o f the 36163 transistor were measured for four devices at several
bias points between gate-source voltages (VGO) o f -0.6 to 0.4 V at a drain-source voltage
(Vdd) o f 2.5V. A block diagram o f the S-Parameter measurement setup is shown in
Appendix A.i.c. The response o f the transistors seemed to show fair consistency for the
phase responses and the magnitude o f S21. The magnitude response o f S l l , S22, and
S12 however showed significant amounts o f variation among transistors. An example o f
the measurement results is shown in Figure 2.5, for VGO equal to O.IV and Vdd equal to
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27
2.5V. The S-Parameter measurements conducted at the rest o f the bias points are shown
in Appendix A.i.d. Note that a MATLAB routine was used to take the average o f the five
transistor measurements, including a routine to correctly average the phase around points
o f -180 to +180 degree phase shifts, the program details are shown in Appendix A.i.e.
mag(S11)
mag(S21)
mag(S22)
1
xtr36a-1
xtr36a-2
xtr36a-3
xtr36a-4
... .J
1
0.4
5
10
15 20
5
25
phase(S21)
phase(S11)
10
15 20
25
phase(S22)
200
II
1
1
1
100
1
0 fc. 1 - : i1
11
-100
10 15 20 25
Freq (GHz)
5
10 15 20
Freq (GHz)
25
-200
;
1
1
.!
1
1V
! ^
5
10 15 20
Freq (GHz)
25
Figure 2.5. S-Param eter M easurement Results for VGO = O.IV, Vdd = 2.5V
C :\R esearch\l_B_l Understanding NL Mech\A Actual Device Characterization\i Device Measurements\S_Parameters\Wan 8_20_02
Xtr36aMeas\xtr36a_avg_Vgo_p0_l_Vdd_2_5_noS12_noavg.fig
2.ii.c.2. Improved Large-Signal Measurement System
A typical large-signal measurement system utilizes a synthesizer and spectrum
analyzer system to provide an input power at a fundamental frequency, and measure the
resulting output signal at the fundamental and first three harmonics. Such a system is
explained in more detail in [34;35]. As described in Section 2.i, the development o f a
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
28
generalized nonlinear model necessitates the use o f an improved version o f this
measurement system which characterizes the large-signal response at the output and
input o f the transistor over changes in input power level, fundamental frequency, and bias
level.
Figure 2.6 shows the block diagram o f the improved measurement system. It consists
o f an HP 83620A synthesized sweeper, an Innowave IR-908 isolator, an HP broad-band
20dB directional coupler, an HP 8493C 6dB attenuator, an HP 11612A Bias-T, and an
HP 8563E Spectrum Analyzer on the input.
HPIB Interconnect
Spectrum
Analyzer
Synttiesized
Signal
Generator
Labview
PC
MuitlMeter
DC Bias
Supply
VGO
MuitiMeter
Vdd
Bias-T
Isoiator
Directional
Coupler
6dB
Atten
20 dB
Atten
Spectrum
Analyzer
Bias-T
Output Network
_
_j
Input Network
Figure 2.6. Block Diagram o f Im proved Large-Signal M easurement System"
C :\Research\F igures\PinPoutPrefBlockDiagram_publishC,ai
In order to ensure accurate characterization o f the device under test, the 4-port Sparameters o f the input network were measured on the Network Analyzer. The features
o f the input network were:
•
Insertion loss o f no more than 9 dB to allow the input power level into the device
under test (DUT) to reach up to lOdBm, without saturating the synthesizer output.
This figure w as also presented in [15] by this author.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
29
•
Low isolation leakage (45dB at worst) from portl to port3 allowing accurate
measurement o f the reflected power from the DUT.
•
A coupling o f 30dB or tighter from port2 to port4 to keep the reflected power
measurements above the 60dB noise floor o f the SA.
•
A low VSWR at port2 to ensure that the DUT was looking back into an
impedance close to 50 ohms.
•
Good isolation for the synthesizer from any reflected power signals.
On the output o f the measurement system was an HP 11612A Bias-T, an HP 8493C
20dB attenuator, and an HP 8563E Spectrum Analyzer. The 3-port S-parameters o f the
output network were also measured. The 20dB attenuator provided a good VSWR at
portl o f the output network, and suppressed the high power levels coming out o f the
DUT.
The measurement system was calibrated on the input by conducting an insertion-loss
(from portl to port2) and coupled (from port2 to port3) measurement using the
synthesizer, spectrum analyzer, and a calibration short. On the output a simple insertionloss measurement (from portl to port2) was conducted. As mentioned above, the
calibration and characteristics o f the input and output networks were also verified using
the Network Analyzer. A DC calibration was also conducted to correct for resistances o f
the DC cabling, including the internal resistance o f the bias-Tees.
A PC running LabView was utilized in the measurement system to control the
synthesizer, spectrum analyzers, DC bias supply, and multi-meters. This allowed
automated measurement o f the device under test over a large range o f variation in input
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
30
power level, fundamental frequency, and bias levels. An image o f the actual large-signal
measurement setup is shown in Appendix A .i.f in Figure A .l 1 (page 428).
The large signal response o f the four PFIEMTs was measured for an input power o f 10 to -1-10 dBm, for several gate bias (VGO) voltages between -0.6 and -I-0.4V, for a drain
bias (Vdd) o f 2.5V, and for input fundamental frequencies between 2 and 6GHz. Figure
2.7 and Figure 2.8 show an example o f the measurement results for a gate bias o f O.IV, a
drain bias o f 2.5V, and a fundamental frequency o f 3 GFIz.
-10
-10
m-15
"O
S -20
CO
-30
-30
-40
— xtr36a-2
X xtr36a-3
xtr36a-5
♦ xtr36a-6
-35
-60,
-45,
-10
Pin (dBm)
Pin (dBm)
Pin (dBm)
Figure 2.7. M EASURED output power vs. input power for VGO = O.IV, Vdd = 2.5V, fo=3G Hz
C:\R esearch\l_B_l UndrstndngNL Mech\A Actl Dvce Char\i Dvce Meas\Power\Pwr meas xtr36a
1 l_23_02\xtr36a_comp_vgo_p0_l_vdd_2_5_fo_3G_l l_24_02.fig
Figure 2.7 shows the input versus output power response o f the set o f four transistors
measured, while Figure 2.8 shows the reflected power. The figures show that, just as in
the DC measurements, there can be significant variation in the output and reflected power
levels from transistor to transistor, especially for the second and third harmonics. This
shows the importance o f taking measurements for a sample o f transistors and also is
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31
another warning that the variation among transistors can provide a significant source o f
error. Although significant error exists, the variation tends to decrease as the input power
level increases, which is o f benefit since the regions o f interest for multipliers tend to
occur at larger power levels, where larger amounts o f output power exist at the second
and third harmonics. Several plots for the measurements made at other bias points and
fundamental frequencies are shown in Appendix A.i.f.
-10
-15
— xtr36a-2
X xtr36a-3
xtr36a-5
♦ xtr36a-6
-20
-10
-15
S-25
CO
^-30
o)-25
-30
-35
-35
-405
-10
-40
12,
-45
-
Pin (dBm)
-45
Pin (dBm)
Pin (dBm)
Figure 2.8. M EASURED reflected power vs. input power for VGO = O.IV, V dd = 2.5V, fo=3G Hz
C:\R esearch\l_B_l Undrstndng NL Mech\A Actl Dvce Char\i Dvce Meas\Power\Pwr meas xtr36a
ll_23_02\xtr36a_Pref_com p_vgo_p0_l_vdd_2_5_fo_3G_noAVG_ll_24_02.fig
As stated, the output and reflected power was measured with variations not only in
input power, but also for with variations in bias level, and fundamental frequency. Figure
2.9 through Figure 2.13 show a cross section o f this measured data, note that the average
responses are shown for the remainder o f this work.
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32
Figure 2.9 and Figure 2.10 show the output and reflected power responses at the drain
and the gate respectively, versus the input power for a fundamental frequency o f 3GHz, a
drain bias o f 2.5 V, and gate biases o f O.IV (near the midpoint between pinchoff and
forward conduction) and -0.6V (near pinchoff). The purpose of this illustration is to
quantify the fact that each bias level shows a significantly different response in relative
harmonic content. For a gate bias (VGO) o f O.IV there exists significant second and third
harmonic power levels for larger values o f input power.
-20
-239
- -
a
O
D
-30
-35
-10
^
-5
to, VG0=0.1V
2fo,VG0=0.1V
3fo, VG0=0.1V
fo,VG0=-0.6V
2fo, VG0=-0.6V
3fo, VG0=-0.6V
0
10
Pin (dBm)
Figure 2.9. M EASURED output power vs. input power for the first three harmonics: Vdd = 2.5V,
VGO = 0.1 and -0.6V, fo = 3GHz*
C;\Research\l_B_l UndrstndngNL Mech\A Actl Dvce Char\i Dvce
Meas\Power\xtr36a_meas_comparisons_3_8_03\xtr36a_avg_pinpout_fo_3G_vgo_p0_l_and_m0_6_plot_3_8_03.fig
The device is driven into compression at an input power o f around 2dBm, where
significant higher order harmonics arise. A large variation in the output power in the
second and third harmonics is seen. The third harmonic output power varies from -20 to
This figure w as also presented in [15] by this author.
Reproduced with permission o f the copyright owner. Further reproduction prohibited without permission.
33
2 dBm for an input power o f 0 to +10 dBm. Similarly, the second harmonic output varies
from -20 to 0 dBm for the same input. For a gate bias (VGO) of-0.6V the fundamental
and second harmonic output levels are substantial for a low input power range. As the
input power level increases, the third harmonic rises. Figure 2.10 shows that significant
amounts o f higher order, reflected power are also present when the deviee enters the
compression region.
S -2 0
—« •«
O
□
^
-50
-10
VG0=0.1V
2fo,V G 0= 0.1V
3fo,V G 0= 0.1V
fo,V G 0=-0.6V
2fo, VG 0=-0.6V
3fo, VG 0=-0.6V
10
-5
Pin (dBm)
Figure 2.10. M EASURED reflected power vs. input power for the first three harmonics; V dd = 2.5V,
VGO = 0.1 and -0.6V, fo = 3GHz*
C:\Research\l_B_l UndrstndngNL Mech\A Actl Dvce Char\i Dvce
Meas\Power\xtr36a_meas_comparisons_3_8_03\xtr36a_avg_pinpref_fo_3G_vgo_p0_l_and_m0_6_plot_3_8_03.fig
Figure 2.11 shows the output power response versus the fundamental frequency for a
drain bias o f 2.5V, gate biases o f 0.1 and -0.6V, and an input power o f 7dBm.
T h is figu re w a s also presented in [15] by this author.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
34
20
10
*1
E
o
6
d
d
' *‘
1
m
r13-1
o
CL
—
fo,VG0=0.1V
2fo, VG0=0.1V
■■■■ 3fo,VG0=0.1V
O fo,VG0=-0.6V
n 2fo, VG0=-0.6V
^
3fo, VG0=-0.6V
-20
-30
^0
2.5
3.5
>■......
4
4.5
Freq (GHz)
5.5
Figure 2.11. M easured output power vs. frequency for the first three harmonics: V dd = 2.5V , VGO =
0.1 and -0.6V, Pin = 7dBm “
C:\Research\l_B_l UndrstndngNL Mech\A Actl Dvce Char\i Dvce
Meas\Power\xtr36a_meas_comparisons_3_8_03\xtr36a_avg_freqpout_pin_7dbm_vgo_p0_l_and_m0_6_plot_3_8_03.fig
-10
E
CL
-40
—
- -
O
-50
-60
D
^
fo, VG0=0.1V
2fo,VG0=0.1V
3fo,VG0=0.1V
fo,VG0=-0.6V
2fo, VG0=-0.6V
3fo, VG0=-0.6V
2.5
*•
• •
3.5
4 .5
5.5
Freq (GHz)
Figure 2.12. M easured reflected power vs. frequency for the first three harmonics: Vdd = 2.5V, VGO
= 0.1 and -0.6V , Pin = 7dBm
C:\Research\l_B_l UndrstndngNL Mech\A Actl Dvce Char\i Dvce
Meas\Power\xtr36a_meas_comparisons_3_8_03\xtr36a_avg_rreqpref_pin_7dbm_vgo_p0_l_and_m0_6_plot_3_8_03.f1g
T h is figu re w a s a lso presented in [15] by this author.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
35
This input power level represents a point with large second and third harmonic
conversion gain potential and was the mid-range value for the optimization conducted in
Section
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
36
2.iii below. The reflected power response versus fundamental frequency, shown in
Figure 2.12, also displayed large second and third harmonic levels for input power levels
greater than 5dBm.
Figure 2.11 and Figure 2.12 show the output and reflected power responses versus the
fundamental frequency for a drain bias o f 2.5V, gate biases of 0.1 and -0.6V, and an input
power o f 7dBm. This input power level represents a point with large second and third
harmonic conversion gain potential and was the mid-range value for the optimization
conducted in Section 2.iii.d below. The output power has significant variation with
respect to frequency, particularly in the second and third harmonics. For a gate bias o f
O.IV the second harmonic output power has a 7dB change between 2 and 4GHz.
Interestingly, the second harmonic power increases with frequency in this range. For a
gate bias o f -0.6V the output power shows less variation from 2 to 4GHz, however both
biases show a pronounced decrease in 3fo output for frequencies greater than 4GHz. For
the reflected power the variation with frequency is even more pronounced, at both gate
bias levels.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
37
20
10
T
P
O
0
^^***
------1----------------------------------------------------------- - - A
0
£
••••*****'
CO
s
n
!
0
:
0
!
n
.
1
0
-
-
-L.^
£ — £
□
ill *••!
Q_
od
>
>
>
-30
-40
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
— >
——
■" ■■
O
□
0
P out@ fo
P out@ 2fo
Pout @ 3fo
Pref @ fo
Pref @ 2fo
Pref @ 3fo
0.2
0.3
0.4
VGO (V)
Figure 2.13. M easured output and reflected power vs. gate bias for the first three harm onics: V dd =
2.5V, Pin = 7dBm, fo = 3GHz'
C:\Research\l_B_l Undrstndng NL Mech\A Actl Dvce Char\i Dvce
Meas\Power\xtr36a_meas_comparisons_3_8_03\xtr36a_avg_vgopoutandpref_fo_3G_pin_7dbm_plot_3_8_03.fig
Figure 2.13 shows the output and reflected power responses versus the gate bias level
for a fundamental frequency o f 3GHz, a drain bias o f 2.5V, and an input power level o f
7dBm. The output power shows great variation with respect to VGO. As described in the
area o f frequency multiplier design [3;6], gate bias levels near pinchoff (approx. -0.6 for
this device) and forward conduction (approx 0.8 for this device) show strong second
harmonic output power. Likewise, gate bias levels near the midpoint between pinchoff
and forward conduction show strong third harmonic output power [4]. These second and
third harmonic output power levels both vary by around lOdB over the gate bias range
-0.6 to -f0.4V. While the reflected power shows a less extreme change with gate bias, it
still has a difference o f up to 5dB in the fundamental and second harmonic. Perusal o f
T h is figu re w a s a lso presented in [15] by th is author.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
38
Figure 2.9 through Figure 2.13 hints at the difficulty involved with creating a generalized
model. Varying any one o f the input parameters can significantly change the large-signal
output. This variation becomes many times more pronounced when changing all o f the
input parameters simultaneously [15].
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
39
2. Hi. Generalized Modeiing Based on Measured Results
2.iii.a. Optimization Approach
Several types o f models are typically used in the creation o f an accurate, nonlinear
device model. These consist o f physical, table-based, and empirical models. Physical
models utilize the physical semiconductor properties o f the device to predict the electrical
response. Examples o f models utilizing a physics based modeling technique are shown in
[31;36;37]. Table-based models utilize a large array o f measurements, such as Sparameter measurements at multiple bias points, to predict the characteristics o f a device
[31]. Perhaps the most well known table-based model is the Root model [30]. Empirical
models define an equivalent circuit model for a device. An equation for the components
within the equivalent circuit o f the device is defined whose parameters can be optimized
to provide a good fit to measured data [31]. Classic examples o f empirical models are
shown in the work o f Statz et al [28] and Curtice [38]. In this work a novel technique
utilizing aspects o f empirical and table-based modeling was developed to obtain a model
with the required generality. The technique is described in Sections 2.iii.b through 2.iii.d
below. Section 2.iii.b describes the implementation o f the model. Section 2.iii.c
describes the optimization o f the DC response o f the model using detailed measurements.
Section 2.iii.d describes the two-step process used to optimize the model to the large and
small signal AC measurements.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
40
2.iii.b. Model [mplementatlon
The equivalent circuit for the nonlinear implementation is shown in Figure 2.14. The
model, based on the Chalmer’s formulation [16], was implemented in Agilent’s
Advanced Design System (ADS) as a Symbolically Defined Device (SDD). This
implementation includes the Ids current source [16], low frequency dispersion elements
(IdsRF and RC branch, Rc and Crf) [16;39], gate-drain and gate-source capacitors Cgd and
Cgs, diodes Dgs and Dgd, and parasitics at the gate, drain, and source. The figure also
shows the external Vgs and Vds terminal voltages, as well as the “internal voltages”
V gSint, V g d in t,
and V d sin t, which appear directly across the gate-source diode, gate-drain
diode, and the Ids current source respectively.
fpgd
+
Vgi nt
—
j—
^pg
■■
C gdH v
D a d |> j _
T
Cpg1
Vgdjnt
Ld
Rd
^4
VdSjnt
Crf
_
Cpdl
D
+
o
C pd
Idspp
RC
Branch
Figure 2.14. Schematic o f Generalized PHEM T Using the Chalm ers M o d ef
C:\Reseaich\Figures\model_schem_50percent_ver2.ai
* The information in the first paragraph and Equations ( 2.5 ) through ( 2.8 ) o f Section
2.iii.b w as published in [15] by this author.
^ This figure w as also presented in [15] by this author.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Vds
41
The expressions for the nonlinear elements are given by [16;39].
Ids = I
[ l + tanh (^^)] tanh i^aVds^^^) e
Idsifp = [ l + tanh
A.Vds,„
(2 .5 )
)]
(2 .6 )
Cg, = Cg,p+C^^ [l + twh(P,,+P,^Vgs,„,)][l + tanh{P^,+P^^Vds,,,)]
(2 .7 )
Cgd =
( 2.8 )
[ l + tanh (P 3 0 + P .y d s ^,,)] [ l + tanh
+ P^.Vgd^,,)]
Where Ipk, v(/, A,, a, Rcw, and the remaining parameters are described in the ensuing
discussion.
The diodes Dgs and Dgd are described by the basic exponential equation o f the Statz
model as implemented in ADS, the equations are given by [40].
^N*v,
id) I
Vj >-lO N *v,
V
/
-V,^+50v,<Vj<-l0N *v,
Ij =
(2 .9 )
V j< -K ,+ 50v,
Where the value ggs is given by:
-10
a
O gj-
T
= Js
J.
N*v,
‘
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
( 2.1 0 )
42
The parameters in the Equations ( 2.9 ) and ( 2.10 ) are as follows: Is is the saturation
current, Vt is the thermal voltage, N is the junction emission coefficient, and Vbr is the
junction reverse bias breakdown voltage. In order to make the diode model match
realistic measured diode data (for both Dgs and Dgd), Equation ( 2 .9 )(c) was modified by
the addition o f a factor “re” and a factor “N /’ as shown in Equation ( 2.11 ) below.
+/,(£-'" ~ l ) + g „ ( K , - 1 0 j V v , )
F j £ - V „ + 50v,
The addition o f these factors allowed an improved match in the reverse breakdown
region.
In addition to the above mentioned modification in the original model, a capacitance
Cpgd [41] was also found to be useful in providing an improved representation o f the
extrinsic case parasitics which resulted in an improvement o f the S-parameter response.
An ADS schematic o f the model is shown in Appendix A.ii.a.
2.iii.c. DC Optimization*
The D C components o f the model consist o f R d ,
of Rd,
R s,
R s , R g , D gd , D g s
and Ids. The values
and R g were taken from manufacturer’s data [II] while the parameters for the
other component equations (Equations (2 .5 ), (2 .9 )(a) and (b), and (2.11 )) were
developed from computer optimization.
The Equations ( 2.9 )(a) and (b), and ( 2.11 ) for the Dgs and Dgd diode responses were
used to improve the fidelity with the measured response via computerized optimization.
T he inform ation in S ectio n 2 .iii.c w a s p u blished in [15] b y this author.
Reproduced with permission o f the copyright owner. Further reproduction prohibited without permission.
43
The outcome o f this optimization is shown in Figure 2.15 for the gate-source diode. It
shows the gate-source current Igs versus the internal gate-source voltage (VgSint). Figure
2.15(a) shows the response in the forward conduction region of operation and Figure
2.15(b) in the reverse-breakdown region o f operation.
The optimized gate-drain diode gave similar results and is shown in Appendix A.ii.b.
Appendix A.ii.c shows a schematic o f the ADS diode optimization routine, as well as the
diode schematics.
As discussed earlier, the DC Ids current source was optimized using an
empirical/table-based approach similar to that given in [16]. This procedure employs
Equation ( 2.5 ) with parameters v|/, A,, and a as variables and Ipk a constant determined
from measured data. In optimization o f the DC Ids current generator the simulated
response o f the entire DC circuit (with the resistances Rg, Rg and Rj and the optimized
diodes Dgs and Dgd locked in place) is compared to the measured response. The external
voltages and not the internal voltages (as explained in Section 2.iii.b above) were used in
the initial optimization.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
44
0.01
(b) Reverse-Breakdown
(a) Forward Conduction
0.009
Meas
Sim
0.008
-0.005
■o 0.007
O 0.006
-
0.01
T3
5 0.005
< -0 .0 1 5
0.004
(/}
O)
w 0.003
TO
0.002
-
Meas
Sim
0.02
0.001
-0.025
0.5
0.6
0.7
0.8
-3.5
-2.5
Vgs,„, (V)
Figure 2.15. Measured vs. Simulated DC IV Response o f the Gate-Source Diode (Dg,)
C:\R esearch\l_B_l Undrstndng NL Mech\A Actl Dvce Char\ii Dvce Mod\DgsandDgdopt\xtr36a_DiodeOpt_8_21_02\
model36a_Dgs_final_sim_vs_meas_both_7_10_03.fig
The equation for the simulated Ids is optimized to estimate the measured Ids versus
Vds data over a range o f Vgs and Vds values (note that VgSint and Vdsint were not used
until the final step o f the DC optimization, shown on page 47). From a perusal o f
Equation ( 2.5 ) it is seen that the variables which are available to be employed in the
optimization process are Ipk, v]/. A., and a. Ipk is a constant which is determined from
measured data. This leaves \|/, A, and a to be employed in the optimization process.
Thus, the goal is to calculate values of v|/. A,, and a for any pair o f gate and drain voltages
Vgs and Vds such that the difference s in Equation ( 2.12 ) below, is minimized.
Ids{vds, Ipi^,y/,A.,a) - 1 ds (Vgs, Vds) = s
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
( 2.1 2 )
45
Where Ids represents the measured drain current as a function o f Vgs and Vds, and \|/,
X, and a are functions o f Vgs and Vds. The optimization technique is summarized by the
block diagram in Figure 2.16. At the end o f the step by step process depicted in Figure
2.16, a set o f matrix values will be obtained for \\i, X, and a as detailed below as
[ \ |/i j ] ,
and [aij]. In these matrices, the rows represent different values o f Vgs and the
columns different values o f Vds*.
lds(Vgs,Vds)
Choose
init. Vgsi,
Vds = const.
Choose
init. Vgsi,
Choose
init. Vgsi,
VdS;
Assume
Mnmze
via Opt
(a)
Pick
Next
VgS|
Val
(b)
VdSj
Pick
Next
Vgsj
Vai
Indep
Not
Used
(0 )
Pick
Next
VdSi
Minimize
Eii (eqtn?)
Not
Used
(d)
Pick
Next
Vgsj
Vai
Pick
Next
VdSi
(e)
Figure 2.16. Block Diagram o f DC Optimization Procedure^
C:\Research\Figures\DC_tableopt_schem4.ai
The procedure to develop the
[ \ |/ y ] , [A-ij],
and [aij] matrices is depicted in blocks (a)
through (e) o f Figure 2.16.
(a) The first step in the optimization process is to estimate initial values for v|/, X,
and a using a version o f the process given in [24].
(b) The ADS optimizer is then employed to minimize each Si in Equation ( 2.13 )
below, sweeping VgSi from i = 1 to 21 (representing Vgs values from -1
to
+1 V) and
setting Vds equal to a constant, midrange value o f Vds = 2.5 V.
* N ote that these same \|/jj values are em ployed in Equation ( 2 . 6 ) in the full (AC and D C ) m odel.
^ This figure w as also presented in [15] by this author.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
46
Ick\VdsJp^,y/^ (Vgs,,Vds),\[Vgs.,V(k),a^ [Vg^^,Vds)\-lds[Vgs^,Vds) = s.
\(/i, X i,
vectors
(2.13)
and t t i are utilized as the parameters to result in the development o f three
v|/ =
\|/2
\ |/ i ] ,
'k =
[A ,i,
and t t i ) is the one which minimized
and a
X2
•••, A,j],
8i
for a given
= [a i, a i a i ]
where each set (v |/i,
A,i,
V g S i.
(c) The next step in the optimization process is to form a 21X23 [\(/ij] matrix
consisting o f 23 identical column vectors, each equal to the \|/ vector computed above for
a Vds value o f 2.5V. This can be done since the [vj/ij] matrix is essentially independent o f
Vds (this fact is also illustrated in [16]).
(d) The next step is to minimize Equation ( 2.14 ) below for values o f VgSj and
Vdsj, (where Vgs, is swept from i = 1 to 21 as in part (b) and Vdsj is swept from] = 1 to
23, representing values from 0.1 to 4.5 V), by taking the [vj/ij] matrix from part (c) above,
holding it fixed and developing, through optimization, a set of A-ij, and ay parameters
which minimize each s y in Equation ( 2.14 ). This results in two 21X23 matrices [ A y ] ,
and [ t t y ] .
(2 -» )
(e) The next step is to constrain the [ \ |/ y ] matrix from part (c) and [ A y ] matrix from
part (d). The process is now repeated by computing a new [ay] matrix which further
minimizes the sy in Equation ( 2.14 ). At this point an optimum set o f [ \ |/ y ] , [ A y ] , and [ay]
matrices have been achieved which minimize the £y values.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
47
Finally, it is important for purposes o f the ensuing AC optimization to convert the
arguments o f the current source Ids from functions o f Vgs and Vds into functions o f the
internal voltages VgSi„t and Vdsint. Although easily obtainable from the DC simulation,
one problem remaining is that the internal voltages represent an unequally spaced array
o f values for variations in Vgs and Vds, which has also been observed by Anholt [31].
This makes the implementation o f the VgSj.^^ and Vdsj.^^ dependent parameter tables
difficult. This problem is circumvented by only converting to the VgSij^^ values in the
[\[/ij]
matrix, and only using the Vdsj.^^ values in the
[X ij]
and [aij] matrices.
The optimized values for each parameter in the matrices ([vi/y],
obtained within
1 0
and [ay]) are
optimizer iterations, which translates to an efficient extraction
process.
V ds= 0.5, 1,2, 3 ,4 V
Vgs = 0.8, 0.6, 0 .2 ,0 ,-0 .2 ,-0.6 V
solid-rmodsl
dots4meas
Vgs (V)
Vds 0/
Figure 2.17. Ids versus Vgs and Vds o f Generalized PHEM T M odel Com pared to M easured Data
C:\R esearch\l_B_l Undrstndng NL Mech\A Actl Dvce Char\ii Dvce Mod\xtr36a_DC_opt\d Empirical_Table
Modeling_chalm99\Opt_10_15_02\model36a_DC_chalm99_psi_Iam_alph_tbIb_gmtst_vs_measIV_IVonly_7_10_03.fig
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
48
Implementation o f the above process results in a model possessing an accurate DC
perfonnance. The efficacy o f the model in predicting DC performance is illustrated in
Figure 2.17, Figure 2.18, and Figure 2.19. These figures show the Ids, gm and gd
response o f the optimized model compared to the measured data.
Figure 2.17 shows the response o f the modeled DC drain-source current (Ids) versus
the gate-source (Vgs) and drain-source (Vds) voltage. The figure reveals that the
empirical-table based modeling approach provides a model with a close fit to the
measured Ids data as functions o f both Vgs and Vds. The accuracy is verified by Figure
2.18, showing the transconductance
(g m )
o f the model to closely fit measurements even
though it was not explicitly included in the optimization. The modeled output
conductance
(g d ),
*
+
—
shown in Figure 2.19 also agrees closely with measurements.
Meas, V d s=0.5V
Meas, V d s=2V
Meas, V d s=4V
Model, Vds=0.5V
Model, Vds=2V
Model. V d s=4V
0.04
-0.8
— *•
-0.6
*
-0.4
-0.2
Figure 2.18. g„ versus Vgs o f Generalized PHEM T M odel Compared to M easured Data
C:\R esearch\l_B_l Undrstndng NL Mech\A Actl Dvce Char\ii Dvce Mod\xtr36a_DC_opt\d EmpiricaI_Table
M odeling_chalm99\0pt_10_l5_02\ model36a_DC_chalm99_psi_lamb_alph_tblb_gmtst_vs_measIV_gmonly_07_10_03.(
Reproduced with permission o f the copyright owner. Further reproduction prohibited without permission.
49
0.1
0.08-
♦
+
•
-—
E
Meas, V d s=0.5V
Meas, V d s=2V
Meas, V d s=4V
Model, V d s=0.5V
Model, V d s=2V
Model, V d s=4V
0.06
Vgs (V)
Figure 2.19. gj versus Vgs and Vds o f Generalized PHEM T M odel Compared to M easured Data
C;\R esearch\l_B_l Undrstndng NL Mech\A Actl Dvce Char\ii Dvce Mod\xtr36a_DC_opt\d Empirical Table
Modeling_chalm99\Opt_10_15_02\model36a_DC_cha!m99j5si_lamb_alph_tblb_gmtst_vs_measIV_gdonly_07_10_03.fig
3.5
0.8
0.7
0.5
Vgs = -0.6
Vgs = -0.2
Vgs = 0.1
0.6
Vgs = -0.6
Vgs = -0.2
Vgs = 0.1
2.5
0.5
-0.5
0.3
0.2
0.5
-2.5
Vgs (V)
Vds (V)
Vds (V)
Figure 2.20. Response o f DC Parameters vs. Externally Applied Gate and Drain V oltages”
C ;\R esearch\l_B_l Undrstndng NL Mech\A Actl Dvce Char\ii Dvce Mod\xtr36a_DC_opt\d Empirical Table
Modeling_chalm99\Opt_l 0_15_02\ chalm99_DC_optnew_aIlparam_vals_publish_4_18_03 .fig
T his figu re w a s a lso presented in [1 5 ] by this author.
Reproduced with permission o f the copyright owner. Further reproduction prohibited without permission.
50
The final parameter values are shown in Figure 2.20. As the figure shows, the
[2 ,jj],
and
[a jj]
[v |/ij],
matrices have a fairly smooth response with variations in Vgs and Vds.
This is an important component o f the model and is necessary for correct interpolation
between parameter values.
An ADS schematic o f the optimization scheme for the Ids current source equation is
shown in Appendix A.ii.d.
2.iii.d. AC Optimization*
The optimization o f the model to provide a high fidelity AC performance in addition
to its DC performance requires that additional steps be performed. An initial step is to
choose a range o f parameter values tailored to the specific application, which in this case
is to provide a model which will be employed to design frequency multipliers. These
parameters were: input power range from 4 to 10 dBm, a fundamental frequency o f 3GHz
with a fractional bandwidth o f 60%; gate biases o f -0.6 and +0.1V; and a drain bias o f
2.5V.
The generalized model incorporating all circuit parameters was shown earlier in
Figure 2.14. In order to create a model which provides an accurate match to the
measured Pout vs. Pin, Pref vs. Pin, and S-parameter responses, it is necessary to utilize
the optimization option in ADS, employing those parameters which only affect the
model’s AC performance. Specifically, this includes the low frequency dispersion
elements (IdsRp, R C branch), the nonlinear capacitances
(C g s
and C g d ), and the parasitics
T he inform ation in S e c tio n 2 .iii.d w a s pu b lish ed in [15] by th is author.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
51
Cds, Ls, Lg, Ld, Cpg, Cpgi, Cpd, Cpdl, and Cpgd. Note that the low frequency dispersion
elements are an RF current generator (IdsRp) which has a parallel choke (L) and series
capacitor (C) so that the generator only conducts for an AC frequency [39], as well as an
RC branch (Rc, Crf) [16]. The optimization is accomplished in two steps as follows:
Step 1 - Development o f the model to match power response (Pout and Pref vs Pin and
S-Parameters at a single fundamental frequency and bias):
The first part o f the optimization consists o f optimizing the model to match the
measured large-signal output and reflected power levels vs. the input power and the Sparameters for a single fundamental frequency and bias point. This is accomplished
through simultaneous optimization of:
(a) Pout vs Pin for fundamental, second, and third harmonic simultaneously
given Pin at a fundamental frequency (fo) o f 3GHz and a single gate bias (VGO), utilizing
all AC parameters in the vector P described below.
(b) Pref vs Pin for fundamental, second, and third harmonic simultaneously
given Pin at fo = 3 GHz and a single gate bias, utilizing all AC parameters in the vector F
described below
(c) S-parameters SI 1, S21, and S22 at the fundamental, second, and third
harmonic, excluding |S1 l(fo)| and !S21(fo)|, which were not necessary or o f use due to
the large signal information developed from (a) and (b) above. Since the optimization
was conducted for a single fundamental frequency, including a wide S-parameter
frequency range was unnecessary.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
52
T his optim ization is all conducted utilizing the vector o f m odel parameters below:
P = i C ds ’ C p d ’ C pd\ ’ C pg ’ C p g l’ C pgd ’ Td ’ Tg ’ Ts ’ C gdo ’ C gdp
^g so ’ ^g sp
^2 0 ’ ^ 2 1 ’ ^ 3 0 ’ ^ 3 1 ’ ^40 ’ ^ 4 ] ’ ^ c ’ ^ c w )
( 2-15 )
Where Cds, Cpd, Cpdi, Cpg, Cpgi, Cpgd, Ld, Lg, Ls are the parasitic elements; Cgdo, Cgdp,
Cgso, Cgso, Cgsp, P i o ,
P i i , P 20, P 21, P 30, P 31, P 40, P41
are the Chalmers capacitance
parameters [16]; and Rc (the resistive element o f the RC branch described on page 40)
and Rcw (the parameter for the RF current generator, shown in Equation ( 2.6 )) are the
low frequency dispersion parameters.
The optimization steps in paragraph (a), (b), and (c) above were implemented in ADS.
It should be noted that the ADS optimizer allowed for simultaneous optimization o f (a),
(b), and (c) by defining goals comparing the modeled and measured large-signal response
for (a) and (b) and the modeled and measured small-signal response for (c). An error
function similar to that used by Bandler et al [18] (see Equation 12 in [18]) could then be
defined which was dependent on the large and small-signal response. The ADS
schematic o f the optimization preformed for Step 1 is shown in Appendix A.ii.e.
For (a) and (b) the input power was optimized at 6 , 7, and
8
dBm. This resulted in a
response matching well over the prescribed range o f 4-10 dBm. The optimization
process described above was conduced for two separate gate bias levels, a gate bias o f
O.IV and -0.6V. The modeled and measured responses are shown for the output (Figure
2.21) and reflected (Figure 2.22) power versus input power level for fo = 3GHz, for both
optimization runs (one at VGO = -0.6 V and the other at VGO = +0.1 V).
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
53
E
CQ
■D
£
00
3
O
Q.
—
-10
O
O
Meas, VG0=0.1 V
S im ,V G 0 = 0 .1 V
Meas, V G 0= -0.6V
Sim, V G 0= -0.6V
-20
Pin (dBm)
Pin (dBm)
Pin (dBm)
Figure 2.21. M easured vs. Simulated Output Power vs. Input Power Response: VGO = 0.1 and -0.6,
Vdd = 2.5, fo = 3GHz*
C:\R esearch\l_B_l Undrstndng NL MechlA Actl Dvce Char\ii Dvce Mod\xtr36a_AC_opt\mode]36a_pwr_comp_3_I0_03\
model36a_vs_meas_pinpout_vgo_p0_l_and_m0_6_fo_3G_3_10_03.fig
-10
-15
r
S
:r
O p
-10
-12 - i
-141^^
-16
/
-18 • /-
Pin (dBm)
—
O
- □
Meas, VG 0=0.1V
S im ,V G 0= 0.1V
Meas, V G 0=-0.6V
Sim, VG 0=-0.6V
-35
20’
Pin (dBm)
Pin (dBm)
Figure 2.22. M easured vs. Simulated Reflected Power vs. Input Power Response: VGO = 0.1 and -0.6,
Vdd = 2.5, fo = 3GHz^
C ;\R esearch\l_B_l Undrstndng NL Mech\A Actl Dvce Char\ii Dvce Mod\xtr36a_AC_opt\model36a_pwr_comp_3_10_03\
model36a_vs_meas_pinpref_vgo_p0_l_and_m0_6_fo_3G_3_10_03.fig
* T his figu re w a s also presented in [15] by this author.
^ T h is figu re w a s a lso presented in [15] by this author.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
54
The overall response o f the model matches well with measurements for the
fundamental, second, and third harmonic. For the optimization at a gate bias o f O.IV, the
average difference between modeled and measured response (for the output and reflected
power at all three harmonics), is 1.36 dB across the prescribed input power range.
Similarly, the average difference for a gate bias o f -0.6V is 1.37 dB.
Step 2 - Optimization versus bias level and fundamental frequency:
In the optimization described in Step 1 the input power variation was included (for a
range o f 4 to 10 dBm) but variations in bias and fundamental frequency were not. The
next logical step is to generalize the model to permit the bias, fundamental frequency, and
input power levels to be variables. Initial attempts to obtain a set o f parameters P which
gave a generalized response resulted in a model which did not possess the desired
accuracy. This desire to create a “global” model has led to the development o f a new AC
empirical/table-based hybrid approach which has provided the desirable accuracy
involving bias, fundamental frequency, and input power.
This procedure, outlined in Figure 2.23, is as follows:
(a) An initial gate bias voltage, VGOi = +0.1, was chosen.
(b) An initial fundamental frequency, foi = 3GHz, was chosen.
(c) At the given bias VGOi and fundamental frequency foi from (a) and (b)
above, the optimization routine described in Step 1 (paragraphs (a), (b), and (c)) above
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
55
was employed. Upon successful optimization, new VGOm and fon values o f interest are
chosen and the procedure o f Step 1 is repeated.
Optimize Model
for Pout vs Pin
Pref vs Pin and
Sjj for VGOm and
fOp @ fo,2fo,3fo
(Step1)
Choose
next
VG0m,fO|
cmbntn
(d) Set of
Pmn param
values
obtained
for each
(e) Form
table of
params
(f) Results
VGOm, f°n
cmbntn
Opt param
vector P-|-|
obtained
Figure 2.23. Block Diagram o f Optimization Procedure Versus VGO and fo"
C:\Research\Figures\ ADS_AC_opt_blockD3.ai
(d) This results in a set o f model parameters for each VGOm and fOn value o f
interest. Specifically the model was optimized for VGO = -0.6 and +0.1V and for fo = 2,
3, and 4 GHz. This resulted in 6 complete parameter sets represented by a 2X3 matrix
denoted
[P m n ]
where m represents the gate bias and n represents the fundamental
frequeney.
(e) The next step is to create a table o f values for the optimized parameters given
by the [Pmn] matrix. The final parameter values are funetions o f VGO and fo, and these
are shown in Table 2.2.
Next, an interpolation method determines parameter values for VGO and fo
values occurring between optimized points. The ehoice o f interpolation routine was
erucial in obtaining a response accurate with variations in VGO and fo. The accuraey o f
T his figu re w a s a lso presented in [15] b y this author.
Reproduced with permission o f the copyright owner. Further reproduction prohibited without permission.
56
the model obtained from the DC optimization enabled the composite model (both AC and
DC) to track well with modest changes in bias.
Table 2.2. AC Parameters for Generalized M odel'
VGO = -0.6V Parameters
2
3
4
fo (GHz)
VGO = O.IV Parameters
2
4
3
Cds (fF)
0.37
34.40
60.97
58.59
196.80 0.22
Cpd(ff)
190.11
199.38
132.68
35.18
208.05
294.58
Cpdi (pF)
12.72
75.87
76.86
0.11
1.44
234.09
Parasitic
Cpg (fF)
41.58
105.19
163.94
1.92
0.61
136.26
Elements
Cpgi (fF)
667.55
301.89
110.12
0.19
11.03
19.55
Cpgd (fF)
3.22
6.22
4.28
0.00
0.00
0.00
Ld (nH)
0.87
1.06
0.58
0.90
0.44
0.85
Eg (nH)
1.70
0.93
0.69
3.64
1.45
0.56
Ls(nH)
0.07
0.14
0.10
0.48
0.18
0.30
Cgdo(fF)
0.72
9.73
8.02
1.00
1.00
0.92
Cgdp(fF)
14.22
4.16
7.29
4.95
21.06
0.03
Cgso(fF)
138.51
80.84
158.20
45.42
90.52
230.02
Cgsp(fF)
5.74
9.06
10.51
0.14
11.26
18.99
Chalmer's
Pio
0.11
0.52
0.76
0.04
0.17
0.35
Nonlinear
Pii
2.06
0.78
1.55
0.27
1.23
1.26
Capactiance
P20
1.40
2.95
3.02
2.63
0.71
0.01
P21
0.07
1.09
2.10
6.13
2.03
0.02
P30
0.70
0.45
0.13
0.03
0.09
0.32
P31
0.02
0.58
0.18
0.26
0.95
0.63
P40
0.00
0.96
1.39
5.39
1.72
0.02
P41
0.01
0.99
0.08
-0.01
-0.04
0.58
Chalmer's
Rc (Ohms)
178
998
925
179
198
236
Dispersion
Rcw (Ohms)
1420
233
112
2045
625
425
Parameter Type
C:\R esearch\l_B_l Undrstndng NL Mech\A Actl Dvce Char\ii Dvce M od\xtr36a_AC_opt\m odel36ajwr_com p_3_10_03\
model36a_imp_wPref_pstc_tbl_both_3_ll_03.xls
For example the model which was optimized at VGO = -0.6 matched the measurements
well from -0.6 to -0.1 volts and the model optimized at VGO = -i-O.l matched well from •
T h is table w a s a lso p resented in [15] b y this author.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
57
0.1 to +0.3 volts. Therefore the interpolation method for VGO was simply to set limits
for which parameter set would be chosen. For VGO = -0.6 to -0.1, the VGO = -0.6
parameter set was used (represented by m=2 in the [Pmn] matrix) and for VGO = -0.1 to
+0.3 the VGO = +0.1 parameter set was used (represented by m=l in the [Pmn] matrix).
Using linear interpolation between value changes in fo provides a smooth and accurate
response vs. fundamental frequeney. The extraction process for the AC parameters,
outlined in parts (a) through (e) o f the procedure described above, was more involved
then the DC extraction. Optimization o f single set o f parameter values (As described by
Step 1 above) utilized a combination o f random/gradient approaches, thus requiring a
greater number o f iterations than in the DC case.
(f)
The final step in the model development was to verify the results versus
measured data. Figure 2.24 shows the modeled and measured response for the output
(and refleeted) powers vs. gate bias, for a fundamental frequency o f 3GHz and an input
power level o f 7dBm for the fundamental, second and third harmonics. The model
allows accurate tracking o f the measured output and reflected power response with
variations in the gate bias, with an average difference o f 1.45 dB between the model and
measurements across the gate bias range o f - 0 . 6 to +0.3V.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
58
20
x>
CO
Meas, Pout
Sim, Pout
— m Meas, Pref
O
Sim, Pref
O
-15
VGO (V)
VGO (V)
VGO (V)
Figure 2.24. M easured vs. Simulated Output and Reflected Power vs. Gate Bias Response: fo =
3GHz, Vdd = 2.5, Pin = 7dBm ”
C:\Research\l_B_l Undrstndng NL Mech\A Actl Dvce Char\ii Dvce
Mod\xtr36a_AC_opt\model36a_pwr_comp_3_10_03\model36a_vs_meas_vgo_vs_poutpref_bothmdl_pin_7dbm_fo_3G_3_l l_03.fig
) l - - - - - - - - - - - - - - - - - - 1- - - - - - - - - - - - - - - - - ) ►
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- 5
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1
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n■
- 1 ^
- 1 5
•
- 2 0
•
M eas,VG0=0.1V
VG0=0.1V
o_ Sim,
Meas, VG0=-0.6V
D
,0 “
- 2 5
Freq (GHz)
Sim, VG0=-0.6V
-
Freq (GHz)
Figure 2.25. M easured vs. Simulated Output Power vs. Fundam ental Freq Response: VGO = 0.1 and
-0.6V, Vdd = 2.5, Pin = 7dBm+
C:\Research\l_B_l Undrstndng NL Mech\A Actl Dvce Char\ii Dvce
Mod\xtr36a_AC_opt\model36a_pwr_comp_3_10_03\model36a_vs_meas_freqpout_vgo_p0_l_and_m0_6_pin_7dbm_3_10_03.fig
T h is figu re w a s a lso presented in [15] by this author.
^ T h is figu re w a s also presented in [15] by this author.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
59
10
m
6
£
5
m.2 0
2
qI
CL
-15
O
— □
M ea s ,V G 0 = 0 .1 V
S im ,V G 0 = 0 .1 V
Meas, V G 0 = -0,6 V
Sim, V G 0= -0.6V
1
- 20 .
Freq (GHz)
Freq (GHz)
-35.
Freq (GHz)
Figure 2.26. M easured vs. Simulated Reflected Power vs. Fundamental Freq Response: VGO = 0.1
and -0.6V, Vdd = 2.5, Pin = 7dBm ”
C:\Research\l_B_l Undrstndng NL Mech\A Actl Dvce Char\ii Dvce
Mod\xtr36a_AC_opt\model36a_j)wr_comp_3_10_03\model36a_vs_meas_freqpref_vgoj)0_l_and_m0_6__pin_7dbm_3_10_03.fig
Figure 2.25 and Figure 2.26 show the modeled and measured response for the output
(and reflected) powers versus frequency. As shown, the model interpolates well for the
67% bandwidth range about 3GFIz, covering 2 to 4 GHz.
Figure 2.27 through Figure 2.29 show the S-Parameter response o f the model for fo =
2, 3, and 4 GHz and VGO = +0.1V. Each figure shows the measured response across a
frequency band from 2 to 12 GHz. They also show the corresponding model response at
the discrete S-parameter optimization points as discussed in Step 1. In all three plots, the
S-parameter response o f the model when fo is 2 GHz (where the first three harmonics
occur at 2, 4 and 6 GHz) is shown as the circles. The corresponding response when fo is
set to 3GHz (shown at 3, 6 , and 9 GHz) is shown as the squares. Finally, the response
T h is figu re vvas a lso presented in [15] by th is author.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
60
when fo is 4 GHz (shown at 4, 8 , and 12 GHz) is shown as the diamonds. The Sparameter response o f the model was also tested at a gate bias o f -0.6V, and is shown in
Appendix A.ii.f.
S ll
\f=12GHz
/ \
t
■
♦
0
Meas 2-12GHz
fo = 2GHz
fo = 3GHz
fo = 4GHz
jO.5
Figure 2.27. M easured vs. Simulated S l l response for VGO = O.IV, Vdd = 2.5V, fo=2-4GHz"
C:\AC_Opt_ 12_8_02_wPref_p0_ 1\sp_plot_S 11_vgo_pO_ 1_on_9_4_03 ,ai
T his figu re w a s also presented in [15] by th is author.
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61
S22
\
\
jO.5
f=2GHz
/ / \
t
■
♦
Meas 2-12GHz
Sim,fo = 2GHz
Sim,fo = 3GHz
Sim,fo = 4GHz
/
/
Figure 2.28. M easured vs. Simulated S22 response for VGO = O.IV, Vdd = 2.5V, fo—2-4G H z
C:\AC_Opt_12_8_02_wPref_p0_l\sp_plot_S22_vgo_p0_l_zoomed_on_9_4_03.ai
S21
90
120
150
30
/
f=2GHz
t
180
■
♦
Meas 2-12GHz
Sim,fo = 2GHz
Sim,fo = 3GHz
Sim ,fo=4G Hz
330
210
f=12G H z
240^---------------300
270
Figure 2.29. M easured vs. Simulated S21 response for VGO = O.IV, V dd = 2.5V, fo=2-4GHz^
C:\AC_Opt_12_8_02_wPref_p0_l\sp_plot_S21_vgoj50_l_on_9_4_03.ai
* T h is figu re w a s a lso presented in [15] b y this author.
^ T h is figu re w a s also presented in [15] by this author.
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62
2.iv. Conclusion
A generalized PHEMT model which can provide an accurate response for variations
in input power level, fundamental frequency and bias is desirable for nonlinear CAD. The
large signal performance o f a PHEMT transistor has been characterized for large
variations in these input conditions using an easily implemented measurement system.
Based on these measurements, a successful PHEMT model has been developed using a
novel technique to achieve an accurate, generalized response including the large signal
response at the input.
The inform ation in S ectio n 2 .iv w a s pu blished in [1 5 ] b y this author.
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63
Chapter 3.
Fundamentals of Active Frequency
Multiplier Design Utilizing Idealized Models
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64
3J. Introduction
A typical active, single-ended frequency multiplier topology consists o f a transistor
surrounded by passive input and output networks M l and M2 as shown in Figure 3.1.
^M 1
I
M1
Zm 2
I
Vds
M2
Vgs
■gen =50Q
VGO
Vdd
Figure 3.1. Single-Ended Frequency M nltiplier Block Diagram
C:\Research\Figures\jj single_ended mult BD.ai
At the heart o f the multiplier is the transistor, which creates harmonics o f the input
signal at the fundamental frequency fo.
When utilizing a FET/HEMT as the transistor o f choice, there exist several sources o f
nonlinearity. Considering the full circuit model for the PHEMT transistor used in this
research (Figure 2.14 in Section
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65
2.iii.b, on page 40), five potential sources o f nonlinearity exist [42], These are shown in
the simplified model in Figure 3.2 to be the drain-source current generator (Ids), the gatesource and gate-drain diodes (Dgs and Dgd), and the gate-source and gate-drain capacitors
(C g s 3^nd C gd ).
N
©
OS
Figure 3.2. PHEM T M odel Showing Five Nonlinear Elem ents
C:\Research\Figures\model_schem_5nl_elements.ai
The design o f frequency multipliers typically constitutes exploiting one or more o f
these nonlinearities by choosing an AC input signal and DC gate bias level to create a
favorable output signal at the desired harmonic, then manipulating and enhancing the
response via the input and output networks M l and M2. Standard practice is to utilize
the drain-source current generator as the major source o f nonlinearity. Several authors
describe in detail the process o f “conduction angle” analysis whereby a clipped sinusoidal
drain current is created by biasing the transistor in such a way that the gate-source
voltage swings above and below the pinch-off voltage [3;43]. The resulting harmonic
content is deduced via a simple Fourier series expansion with which gate input signals
and bias points for optimal harmonic production can be determined.
Further studies utilize not only the pinch-off mechanism exhibited in the drain-source
generator, but also drain-source current saturation due to forward conduction in the gate-
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66
source diode [6 ]. This current saturation creates another clipping mechanism allowing
for the creation o f double-sided, clipped sinusoidal output waveforms [4;5]. The
exploitation o f this extra mechanism allows a more encompassing exploration of
optimum input signal and bias combinations for desirable harmonic production.
Both o f the above methods utilize a piecewise-linear response for the drain-source
current generator. Furthermore, the idealized calculation o f generated harmonics is made
independently o f the choice o f input and output networks M l and M2.
In addition to the two basic analyses above, design considerations for input and output
networks M l and M2 have also been presented. The input impedance response
Zmi
and
Zm2 (shown in Figure 3.1), o f M l and M2, determine what load the transistor will see at
the input and the output at each harmonic. O f primary consideration is the choice o f load
resistance R l (considered part o f M2 for this study). Many authors present the “loadline” technique to choose a load resistance that achieves maximum current and voltage
swing in the saturation region o f the transistor [3;6;44]. Another consideration is how to
use M2 to terminate the typically large fundamental frequency power on the output. This
is frequently addressed by using M2 to present a short or open circuit to the fundamental,
and is discussed in [3;6;45].
The design o f M l consists primarily o f providing an impedance “match” at the
fundamental frequency to allow maximum power transfer from the power source into the
transistor [3].
In recent literature, more comprehensive techniques for the networks MI and M2 have
been developed. At the U.C. Davis microwave laboratory, several authors have presented
“reflector-network” designs which utilize an output network M2 which reflects the
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67
fundamental and unwanted, higher order harmonic output power back into the drain o f
the transistor with varying phase. Likewise, the input network M l is designed to rereflect higher order harmonic power signals at the gate o f the transistor back into the
transistor with varying phase. Optimization o f the overall multiplier response is achieved
through optimization o f the phase o f the reflected signals [11 ;23;35;46-48]. The above
described techniques represent a problem containing a large number o f design variables.
They include the input signal level, gate and drain bias, and choice o f input and output
termination for the fundamental and higher order harmonics. The complexity o f the
problem and the degrees o f freedom necessitate a generalized design technique. This can
be achieved by an in-depth study o f the effects o f variation in each design parameter, as
well as the inter-relation among parameters. The complexity o f such a study requires an
expeditious method for analyzing and quantifying the above design variables. This is
best achieved through computerized simulation. Furthermore, the problem is best
approached by utilizing an idealized device response. By utilizing an idealized device
response, the theoretical calculation o f harmonics generated by creating single and
double-sided, clipped, sinusoids can be verified. The use o f a simplified model,
containing a drain-source current generator with a piece-wise linear response and an
idealized gate source diode, facilitates the above verification. A schematic o f the
simplified model, called model A for this study, is shown in Figure 3.3.
By approaching the multiplier design problem through the use o f the simplified model,
several advantages are brought about. Verification o f the aforementioned elipped
sinusoidal analysis provides a baseline for exploration o f variation in all o f the design
variables. Current design principles for the choice o f input signal level, bias, output load.
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68
and choice o f M l and M2 can be examined concisely, and new principles can be
discovered. At the same time, the simplicity o f the model, with the presence o f only two
nonlinear elements, allows for the mechanisms for frequency multiplication to be clearly
identified.
G
D
Ids
OS
Figure 3.3. Idealized M odel Schem atic o f M odel A
C:\Research\Figures\modelA.ai
The obvious shortcoming o f using such a model is its deviation from reality. Thus a
complete study necessitates re-introduction o f the model elements o f higher complexity
and characterization o f how realism degrades the idealized design principles. This must
be followed by exploration for methods to compensate for a more realistic situation.
In the current section (Chapter 3), a comprehensive study is presented which utilizes
the idealized model (shown in Figure 3.3), to verify standard clipped waveform theory,
explore current design procedures, and discover new techniques. Effects o f adding
elements o f higher complexity to the initial model are also considered. The study
explores the effects o f the design variables previously mentioned above. Specifically,
these variables consist o f several conditions on the input and output. Section 3 .ii below
presents the study o f considerations on the input, which consist of:
a.
Variation o f the AC input signal magnitude (Vg) and gate bias (VGO), which
encompasses theoretical clipped waveform analysis.
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69
b. The response o f the input network M l at the fundamental frequency. This
typically consists o f providing impedance “matching” to the transistor’s input.
c. The choice o f bias circuitry in the DC gate biasing circuit. Alternatively thought
o f as the DC response o f the network M l.
d. The response o f M l at the higher order harmonics, with focus on the highly
successful “reflector network” theory previously described.
Section 3.iii presents the study o f considerations on the output, which consist of:
a. The choice o f load resistance Rl and drain bias level Vdd, with particular
consideration to the principles o f “load-line” theory.
b. The choice o f bias circuitry in the DC drain biasing circuit. Alternatively thought
o f as the DC response o f the network M2.
c. The response o f M2 at the unwanted frequencies, with particular attention to the
typically large fundamental output power.
Finally, Section 3.iv presents a quantitative study on the interrelationships among the
considerations on the input and output*.
In th e se fo llo w in g se ctio n s, the gu id e to the bias and input sign al le v e ls u tilized in th is w ork (p a g e x ix )
w ill be h elp fu l.
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70
3.U. Harmonic Generation via Various input Conditions
3.ii.a. Input Signal and Bias
3.ii.a.l. Basic Considerations
The most basic design technique for active frequency multipliers consists solely o f
varying the bias and AC signal level at the input o f a transistor. As described above,
these two factors determine the amount o f clipping that occurs in the output current o f the
device. The design technique assumes a device with an idealized, piecewise linear
representation. This device representation has been implemented in ADS as model A,
shown in Figure 3.3. For this basic technique, the input and output networks M l and M2,
are not considered as design variables. The choice o f M l and M2 are therefore made as
shown in Figure 3.4.
M1
M2
Ids
Vds
R|_=50Q
Vgs
VGO
Figure 3.4. Input (M I) and Output (M2) Networks for Input Signal and Bias Study
C:\Research\Figures\jj m lm 2 input_study_a BD.ai
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71
M l constitutes a standard “bias-T” circuit which isolates the AC and DC sources from
each other using a DC blocking capacitor C, and an AC choke L. A seemingly odd
characteristic o f M l is the addition o f a resistance o f 50 ohms in the DC path (Rdc=50Q).
This resistance, although not representative o f a typical microwave circuit configuration,
sets the input impedance o f M l (Zmi in Figure 3.4) equal to 50 ohms at all frequencies,
including DC. This will prove important, and is studied in-depth in Section B.ii.c (page
118) where justification and the relation o f using the above impedance with reality is
explained. M2 also constitutes a basic “bias-T” circuit, used to separate the DC source
from the AC output signal. No DC path resistance is used for M2, as will be explained
and explored in further detail in Section B.iii.b (page 211). The output load resistance is
set to 50 ohms, as in a standard microwave system.
This study explores, using computer aided design in ADS, the design o f multipliers
considering only the adjustment o f the input signal and bias level, utilizing the
configuration shown in Figure B.4. The study is presented as follows: In Section B.ii.a.2
below, the theoretical calculations for harmonic generation in single and double-sided,
clipped, sinusoidal waveforms are reviewed. In Section B.ii.a.B, the specifics o f the
idealized model (model A), which can be used to verify the basic theory, are presented.
In Section B.ii.a.4, the basic principles o f harmonic generation are demonstrated through
the analysis o f an example set o f input and output waveforms. Section B.ii.a.5 presents a
comprehensive quantitative study o f harmonic generation using model A, through
analysis o f waveforms, Fourier domain signals, and power signals on the input and output
o f the transistor. Finally, Section B.ii.a. 6 presents a summary o f the findings.
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72
3.ii.a.2. Theoretical Calculations
The technique frequently used to design frequency multipliers, which was presented
by [3;5;43], utilizes clipping in the output drain current due to the turn off voltage o f the
transistor. In the absence o f forward conduction o f the gate-source diode, the voltage
signal at the gate o f the transistor, using the circuit configuration o f Figure 3.4, is given
by:
V g s ( t ) = V G O + V g » c o s ( c t> j)
(3.1)
Where VGO is the gate bias voltage and Vg is the magnitude of the AC input
signal. Note that when the gate-source diode conducts, the gate-source voltage
becomes non-sinusoidal, creating changes in the harmonic voltage levels (including
DC) at the gate, and Equation ( 3 . 1 ) no longer holds. Figure 3.5 shows an example o f
a single-sided, clipped drain current waveform being generated from an input voltage
signal such as that given by Equation (3.1 ).
Notice that the figure has three parts (a), (b) and (c), labeled in the upper left hand
comer o f each subplot. This convention is used throughout this work. Figure 3.5(a)
shows the piecewise-linear Ids versus Vgs relationship, the transistor tums o ff (Ids = 0)
for gate-source voltages below the pinehoff voltage (Vp). Figure 3.5(b) shows an
example gate-source voltage waveform input into the transistor via the AC source and
DC gate bias voltage. As the voltage swings below Vp, the device tums off and the
output current is clipped as shown in Figure 3.5(c). The clipping effects in the drain
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73
current cause harmonic generation, with different harmonic levels created depending on
how much clipping the waveform undergoes.
0.03
0.03
0.025
0.025
0.02
0.015
0.01
0.01
0.005
0.005
Vgs (V) I
X
10
time (sec)
-10
-10
E4
1
-0.8
-0.6 -0.4
Vgs (V)
-0.2
0
Figure 3.5. Exam ple o f the Creation o f a Single-Sided, Clipped, Output C urrent W aveform
C;\2_Stdy_Idlzd_Mdl\example_condang_wfplot2_5_7_03.ai
The time duration for which the transistor is turned on is represented by the
conduction angle (|), (Figure 3.5(b)), and is calculated as [43]:
(j) = cos
V p -V G O
Vg
,
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(3.2)
74
Where Vp is the pinehoff voltage, Vg is the voltage magnitude o f the AC input signal,
and VGO is the gate bias voltage level. (|) is utilized to calculate the Fourier
representation o f the clipped output current waveform, given by [43]:
Up
n
Ids„ =
\ —
c o s {(f) sin ( « ^ ) - n sin ( ^ ) c o s
n>\
n{n^ -l)(l-cos(^^))
(Z i-cos(^ )sin(^ )
------------V„„ /
yi = 1
(3.3)
l-c o s(^ )
sin (^ )-^ co s(^ )
n=0
l-c o s(^ )
Where, as shown in Figure 3.3, Ids is the drain to source current source, n is the
harmonic number and Ip is the peak drain current.
More recently, a generalized calculation has been developed by O’Ciardha et al [5]
which includes clipping due to the turn-off voltage as well as clipping due to forward
conduction o f the gate-source diode (Dgs). This utilizes a double-sided, clipped
waveform as shown in Figure 3.6. Figure 3.6(a) shows the piecewise linear Ids versus
Vgs response. Figure 3.6(b) shows the gate-source voltage waveform. This time, the
magnitude o f the AC input is driven high enough for the gate-source voltage to swing
below the pinehoff voltage (Vp), and up to the forward conduction voltage (Vfwd) where
the gate-source diode conducts and holds the voltage level constant. This gate voltage
signal results in double-sided clipping in the output drain current waveform, shown in
Figure 3.6(c). The pinehoff and forward conduction clipping durations are represented
by a and b, and are calculated as [5]:
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75
^ ^\ - V' D C ^
a = — cos
(o„
(3.4)
VAC
V
''vDC ^
bu = —1 cos - 1
V
co„
Where
V
'DC =
VAC
V dc
(3.5)
and V ac are normalized representations o f the gate voltage, given by [ 5 ]:
VGO-Vp
V fw d-V p
(3.6)
Vg
VJwd-Vp
(3.7)
The values a, b,
V dc,
and V ac are utilized to calculate the Fourier representation o f the
double-sided, clipped output current, shown in Equation ( 3.8 ) below [5]:
IV^Ip
nn
(- 1 )"^’ sm{rwJ})-sm{ruo^a)\^
+ V,clP (- 1 )” sin([n - 1 ] cojy^ - sin ([« - 1 ] a>^a)
[n-fjTT
(3.8)
+ V,cIP (-l)"sin([« + l]<zi,6 )-sin([n + l](y„a) + — sin(«^y„a)
(« + l) n
n>\
Ids„ =<
[sin(ty„Z)) - sin((u„a)] + 2V^Jp
n
+
[
27t
-
si n ( '2.(0^a) - sin (2o3jy)\+
Voclp 1 - 2
-A
a+b
^
K
1 awh
sin(fy^a)
77=:1
+ ^ ^ [s in ((o „ 6 )-sin(ft>„a)]+ ^
n
Where n is the harmonic current and Ip is the peak output current (equal to the saturation
current I d s s , as shown in Figure 3.6(c)). Note that in the reference [5], there is a
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76
typographical error in the equation for Idsi, which has been corrected for in Equation (
3.8 ). Also, the equation for Idso was not included in the paper by O’Ciardha et al. These
additions to Equation ( 3.8 ) were obtained by re-deriving this equation. The derivation is
shown in Appendix B.i.a.l (page 452).
DSS
DSS
T/2
-T /2
Vgs (V)
tim e (sec)
-T /2
./bPW-.
o
<a
,w,
>
<D
E
...........
T/2
vp
Vfwcl
Vgs (V)
Figure 3.6. Exam ple o f the Creation o f a Double-Sided, Clipped, Output Current W aveform
C:\2_Stdy_ldlzd_Mdl\ example_doubleclipped_wfplot_5_7_03.ai
Using this output current information and observing the output network M2 (Figure
3.4), the drain voltage harmonics can be calculated by:
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77
"
\Vdd
n = Q\
(3.9)
The corresponding output power levels at each harmonic can be calculated as [3]:
-K Q [V dsJds„]
Pout„ =
Vdd •Ids
« > 0
(3.10)
n= 0
The resulting conversion gain can be calculated as;
CG„ =
Pout„
Pavail^
(3.11)
Where Pavaih is the available power from the source at the fundamental frequency,
related to the peak AC generator voltage by [3]:
Pavail^ =
^Rgen
For this work, the conversion gain is defined as a function o f the available power
rather then the power input into the transistor. Although this definition deviates from
some standard texts [3;6], it is a straightforward way to characterize a multiplier, which is
typically measured in a system in which the available power is swept and the input power
is not always easily attainable. Furthermore, when utilizing model A, Dgs is typically an
open circuit into which the input power is zero, while a significant output power level
still exists. To define the conversion gain using the input power would then result in an
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78
infinite value, which would be o f little value in assessing harmonic generation in the
device in terms o f a gain related measure.
Appendix B.i.a.l (page 452) shows a derivation o f Equation ( 3.8 ). Appendix B.i.a.2
(page 457) shows a Matlab routine which utilizes Equations ( 3.2 ) through ( 3.12 ) and
the calculation shown in Appendix B.i.a.3 (page 462) to calculate the output harmonic
levels as a function o f the input signal. These idealized equations give a method to
design a frequency multiplier by simply varying the input signal level and the input bias
voltage.
It is important to note that Equations (3.3 ) and ( 3.8 ) are typically used to
adjust the gate bias VGO, and input voltage level Vg, to optimize the output current
level Ids„ at the desired multiple u of the fundamental frequency, resulting in a
maximum output power level. However, as Equation (3.11) shows, the conversion
gain of the multiplier is a function of the output power and available power level.
Since the available power level is also a function of Vg, optimizing the output power
only does not necessarily give the optimum response in terms of the conversion gain
and vice versa. This idea will be explored in more detail in Section 3.ii.a.5.e.
3.ii.a.3. Idealized Model Development (Model A)
In order to verify the theoretical design techniques above, an idealized model (model
A) was created which consists only o f the basic nonlinear properties used in the
theoretical calculation. The model was simulated in ADS to verify the theoretical
technique. This idealized model provides a baseline for analyzing more complex
phenomena occurring in frequency multipliers. The model contains only two nonlinear
elements, as previously described and shown in Figure 3.3. The characteristics o f the
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79
model are chosen to approximate the model for the actual device used in this research,
shown in Figure 2.14 (page 40). Several o f the complex model elements were removed
from Figure 2.14, leaving only the Ids current source and the gate-source diode Dgs. The
gate-source diode was simplified to approximate a short circuit (rj =
0 .0 1
F2 ) when biased
positively, and become an open circuit below OV (Vfwd = OV). The Ids current source
was simplified to give a linear response for Vgs inputs between pinch-off and zero volts,
to turn off for Vgs inputs below pinehoff, and to be independent o f Vds. Additionally,
when considering the fact that for gate-source voltages greater than zero, Dgs shorts out,
we can add the constraint that the current saturates for Vgs inputs greater than zero. The
final equation for Ids is [6;49]:
Vgs < Vp
0
Ids -
'■DSS
1
-
Vg^
Vp < Vgs < 0
(3.13)
Vp.
'D S S
Vgs > 0
This model was implemented in ADS as a symbolically defined device (SDD), and is
shown in Appendix B.i.a.4 (page 463). Figure 3.7 is a comparison o f the IV
characteristics o f the ideal and actual measured PFIEMT transistor. The values o f Vp and
loss were set so that the ideal model would have an IV characteristic that roughly
approximates the actual PHEMT.
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80
0 .0 3 5
0 .0 3 5
M e a s V d s = 2.5V
Ideal V d s = 2.5V
» •»
O
□
M eas Vgs = OV
M eas Vgs = -0.3V
M eas V g s = -0.6 V
Ideal Vgs = 0 V
Ideal Vgs = -0 .3
Ideal Vgs = -0.6
0.025<Mi*«*
0 .0 2 5
0 .0 1 5
0 .0 1 5
0 .0 0 5
-8 .6 -0 .5 -0 .4 -0 .3 -0 .2 -0.1
V g s (V)
0
1
V d s (V)
2
Figure 3.7. Comparison o f Actual V ersus Ideal PHEM T M odel (a) Ids vs. V gs (b) Ids vs. Vds
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\i Dev Idealized Models\Comparisons_w_Meas_data\
modelA_vs_model36a_final_l_17_03.fig
3.ii.a.4. Generating harmonics using the model
The idealized model (model A) is simulated utilizing the circuit configuration setup as
shown in Figure 3.4 with model A replacing the transistor representation. An ADS
schematic o f the full circuit simulation is shown in Appendix B.i.a.5 (page 464). An
extremely informative way o f analyzing this circuit and presenting performance is to
make several plots, and align them together into a “waveform plot” as shown in Kushner
[44] for the case o f power amplifiers. Figure 3.8 shows an example o f the time
waveforms o f the output signals, Ids(t) and Vds(t), obtained for a given AC input signal
Yg*sin(cOot), gate bias VGO, drain bias Vdd, and load Rl, where Vgs(t) (given by
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81
Equation ( 3.1 )* in the absence o f forward conduction) is the w aveform appearing at the
gate o f the transistor.
0.03
!
(a)
I
0.02
0.03
0.03
0.02
0.02
<
"«O
XJ
0.01
0.01
0.01
-1
-1.5
-0.5
Vgs (V)
Vds (V)
time (sec) x l o '°
,-io
,-10
xIO
x IO '
0
—
Vg = lVp|/2
Vg = |Vp|
Vg = 2|Vp|
6
1.5
■1
-0.5
V g s(V )
0
0
2
4
Vds (V)
Figure 3.8. Exam ple W aveform Plot (a) Ids vs. Vgs (b) Vgs(t) vs. tim e (c) Ids(t) vs. tim e (d) Ids vs.
V ds and Loadline (e) Vds(t) vs. tim e
C:\2_Stdy_Idlzd_Mdl\modelA_caseA_wfplot_l_21_03.fig
Note that each subplot is labeled (a) through (e) in the upper left hand comer as
previously explained. Part (a) o f the plot shows the DC Ids versus Vgs characteristics o f
the ideal transistor model. Part (b) shows the time waveform o f the input signal into the
gate with VGO set to half o f the pinchoff voltage (Vp/2). Part(c) shows the time
waveform o f the corresponding output current. Part (d) shows the DC Ids vs. Vds
characteristic o f the ideal transistor model (model A and Equation ( 3.13 )), along with
the load line for a chosen resistive load. Part (e) shows the time waveform o f the output
S e e n ote fo llo w in g E qu ation ( 3 . 1 ), page 72.
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82
voltage as it travels along the load line (the load line will be discussed in detail in Section
S.iii.a).
Figure 3.8(b), (c), and (e) each show three traces corresponding to three different Vg
input values (Vg = |Vp|/2, |Vp|, and 2|Vp|). As expected, in the cases where the input
signal Vgs(t) appearing directly across the gate becomes less than Vp or greater than 0,
the output current at the drain Ids(t) is clipped. The clipping effect is used to create
various non-linear effects in the output as previously described above. In the following
quantitative study presented in Section B.ii.a.5 below, various waveforms are analyzed
through the use waveform plots (similar to the above figure), as well as the Fourier
representations o f the waveforms and the corresponding output and reflected power
levels at the various harmonics.
3.ii.a.5. Study of Harmonic Generation in the Idea! Model
Table 3.1 shows the various input signal, bias, and load combinations tested in this
quantitative analysis to be given in the following study. Columns 1 and 2 show the
names o f the various cases, columns 3 and 4 show the bias conditions at the gate and the
drain respectively, columns 5 and 6 show the magnitude o f the AC input signal at the
gate, column 7 shows the conduction angle based on the input signal, and column
8
shows the choice o f load.
Typically, the drain bias (Vdd) and load resistance (Rl) is chosen to give maximum
current and voltage swing at the drain output. The choice o f output bias and load will be
discussed in further detail in Section B.iii.a. The load line (Figure 3.8(d)) represents the
current vs. voltage relationship for the output signal, as dictated by the choice o f load for
the circuit. This will also be discussed in Section B.iii.a.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
83
Table 3.1. Input, Bias, and Loading Conditions for Study o f Harmonic Generation in M odel A
Gate Bias
(VGO)
Drain Bias
(Vdd)
Pin
(dBm)
A1.1
A 1.2
A 1.3
B1.1
V p/2 = Vm id
V p/2 = Vm id
V p/2 = Vm id
Vp
(V rbd+V ki)/2
(V rbd+V ki)/2
(V rbd+V ki)/2
(V rbd+V ki)/2
-7
-1
5
-7
B 1.2
B 1.3
C 1.1
C 1 .2
Vp
Vp
0
0
(V rbd+V ki)/2
(V rbd+V ki)/2
(V rbd+V kl)/2
(V rbd+V ki)/2
-1
-1
C IS
D 1.1
D 1.2
0
3V p/2
5V p/4
(V rbd+V ki)/2
(V rbd+V ki)/2
(V rbd+V ki)/2
5
-7
-7
D 1.3
D 1.4
Vp
3V p/4
(V rbd+V ki)/2
(V rbd+V ki)/2
-7
-7
D 1.5
Vp/2
(V rbd+V ki)/2
-7
Case Description Label
(A1) Midway Bias
(B1) Pinchoff
Bias
(01) Forward
Conduction
Bias
(D1) Conduction
Angie Study
5
-7
AC Input
Voltage Mag
(Vg)*
Conduction Load
Angle: 2^
(R,)
(deg)
|V p^2
360
360
360
180
50
50
50
50
|V p^2
IVpj
180
180
180
180
50
50
50
50
2*|Vp|
|V p^2
|V p^2
180
0
60
50
50
50
|V p^2
180
120
50
50
360
50
IVpl
2*lVpl
lVp^2
IVpl
2*|Vp|
|VpF2
|V p^2
(E l) Speciai Cases S p e c ia l D e sig n C a s e s , S e e se c tio n 3 .ii.a .5 .v fo r d etails.
* E quivalent Vg to give P in (approx)
C:\2_Stdy_Idlzd_Mdl\table_of_cases_l_22_03.sxc
3.ii.a.5.i. Case A l, Midway Bias (VG0=Vp/2)
Case A l represents a typical “class A” bias and input configuration. For case A l, the
gate voltage swing is increased incrementally as shown in Table 3.1 on the sixth column.
The waveforms for this case are shown in Figure 3.9, using the layout described in
Section 3.ii.a.4 above. All three input signals are overlaid as traces in Figure 3.9(b). As
shown in the figure, when the AC input voltage magnitude (Vg) is less than |Vp|/2 (case
A 1.1), the output current waveform is proportional to the input at the gate.
Since the gate voltage is kept between zero and pinch-off for caseA l.l, the
corresponding output is linear. Once Vg becomes greater than lVpl/2, the gate voltage
goes beyond pinch-off (case A1.2 and A1.3) and the current waveform is symmetrically
clipped at loss and 0. At this point the input is no longer linearly related to the output,
and odd order harmonics arise. This generation o f odd harmonics can be shown by
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
84
plugging the input signal and bias level for cases A1.2 and A1.3 into Equations ( 3.4 )
through ( 3.8 ).
0,03
0.03
(a)
.0.02
.0.02
-------
■<0D
■
0.01
0.01
-1
-0.5
“
0.01
0
Vgs (V)
Vds V)
xIO
-1.5
----- Vg = lVp|/2 (Case A l l )
— Vg = |Vp| (CaseA1.2)
..... Vg = 2|Vp| (CaseA1.3)
-1
-0.5
0
Vds(V)
Vgs (V)
Figure 3.9. W aveform Plot for Case A l
C :\2_Stdy_Icllzd_Mdl\model A_case A_wfplot_l _ 2 1_03.fig
The equations also show that for these cases no even harmonics are generated. Figure
3.10 shows the ADS simulated Fourier series representation o f the waveforms for case
A l . Part (a) o f Figure 3.10 shows the Fourier representation o f the gate-source voltage
waveform. Part (b) shows the corresponding current and (c) shows the drain-souree
voltage. Case A 1.1 is represented by the circular trace, A 1.2 by the triangular trace and
A l .3 by the square trace. As shown in part (a) o f the figure, for case A l . 1 the input to the
gate consists only o f a DC, and fundamental component. For case A1.2 and A1.3, the
gate source voltage is clipped at zero volts due to the gate source diode turning on. The
corresponding spectrum is that o f a clipped sine wave, which contains harmonics other
than at the fundamental. It is further notable that the DC level at the gate increases from
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
85
0.3V to approximately 0.35V to approximately 0.52V. As shown in part (b), case A l.l
shows currents that correspond directly with the input voltage.
0.8
- - x I o ''
V \ ----(a) 11
------- 1
(b )
w
2.51
^
C ase A I.1
1
■
>
O)
(/)
D)
k
it.
.
D)
C a s e A 1 .2
-------
■
J 1.5
O)
T3
tn
•o
>
V
i
. ____
1
- ]
------
0.5
Lj
Freq (GHz^
C a s e A 1 .3
O)
0
3
J
.
Freq (GHz)
X
_
10
g
0
3
Freq (GHz)
X
10
g
Figure 3.10. Fourier Series Representation o f Case A l W aveforms (a) Vgs (b) Ids (c) Vds
C:\2_Stdy_Idlzd_MdlWmodelA_caseA_fsplot_l_24_03.fig
Case A l .2 and A l .3 show a current waveform that is clipped at both ends; at loss due
to the gate source diode turning on and at zero due to the Ids current source turning off
for gate voltages below pinch-off. The waveforms for these cases, which approach a
square wave as the value o f Vg is increased, show odd order harmonic content. Figure
3.10(c) shows that the Vds waveforms have the same relative output as the output current
Ids, scaled by the factor R l , as described by Equation ( 3.9).
In order to validate the response o f the idealized model, its power response was
compared with the theoretical response (calculated using the Matlab program described
in Appendix B.i.a.2, page 457), o f Section 3.ii.a.2 above. Figure 3.11 shows a plot o f the
output power at the drain vs. the available power (Pin) at the gate for case A l . Note that
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
86
for the power response, the input signal level is swept through a range o f values,
including the cases A l.l, A1.2, and A1.3, and is therefore referred to genetically as case
A l.
10
^
o
o
o
0
0
0
0
0
0
(1) o
o
o
o
(b
0
E -1 0
GO
■o
B
S im @
S im @
■■■■ S im @
O C alc @
X C alc @
□ C alc ®
0-20
-3 0
-4 0
-10
-5
fo
2 fo < -40d B m
3 fo
fo
2 fo < -40d B m
3 fo
0
10
P in (d B m )
Figure 3.11. Power Available at the Gate vs. Power Output at the Drain for Case A l (VGO=Vmid)
C :\2_Stdy_Idlzd_Mdl\ model A_caseA_pwrplot_ 1_22_03.fig
Figure 3.11 shows that when the available power is less than -7dBm (corresponding
to a Vg o f less than 0.3 V), the output power only occurs at the fundamental frequency,
and increases proportionally with the available power. As the available power passes 7dBm, the third harmonic begins to come up. As exhibited in the spectrum o f the output
current in Figure 3.10(b), no second harmonic exists for this case. The increase in the
“fundamental” output power is reduced as the third harmonic increases. The IdB
compression point at this bias occurs at around Pin = -5dBm. As Pin is increased further,
the waveform becomes very close to a square wave, and the responses at fo and 3fo flatten
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
87
out. As the figure shows, the idealized model gives a response which matches the
theoretical MATLAB calculation.
Conversion Gain
The conversion gain exhibited by the model can be calculated utilizing the above
output power response with Equation (3 .1 1 ). This is shown in Figure 3.12. Note that
the term “conversion gain” infers that the output signal has been converted to a different
frequency than the input signal. However, in this work the conversion gain has also been
defined for an output power at the fundamental frequency (the conversion gain at the
fundamental) for convenience and clarity. The term “conversion gain at the
fundamental” could be simply be replaced with “gain” in a conventional definition.
— CG @ fo
— CG @ 2 fo < -30d B
■■■ CG @ 3fo
••
-20
\
CG
2fo < -30dB
-30.
-10
Pin (dBm )
Figure 3.12. Power Available at the Gate vs. Conversion Gain for Case A l (VGO=Vmid)
C:\2_Stdy_Idlzd_Mdl\modelA_caseA_CGplot_9_29_03.fig
Note that the conversion gain o f the third harmonic (3fo) reaches an optimum value o f
-4.8 dB at an input power o f 0 dBm, however, this is close, but not equal to, the optimum
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
88
output power at 3fo. The corresponding output power at 3fo is equal to -4.8 dBm at the
conversion gain optimum. This is -3 dB below the maximum output 3fo power which
occurs at an input power o f 10 dBm. however the corresponding conversion gain here is
-11.8 dB.
Also o f interest when conducting this basic analysis on harmonic generation is the
reflected power at the gate. Figure 3.13 shows the reflected power at the gate versus the
input power level for this case.
E
m
S -15
'S
Sim @ fo
— Sim@ 2fo
"••• Sim@ 3fo
-25
-30
-35
-4q
-10
Pin (dBm)
Figure 3.13. Pow er Available at the Gate (Pin) vs. Reflected Power at the Gate (Pref) for M odel A,
Case A l
C:\2_Stdy_Idlzd_Mdl\ modelA_caseA_prefplot_l_22_03.fig
As the figure shows, second and third harmonic power begins to be reflected at the
drain as the available input power rises. This corresponds to conduction o f the gatesource diode (Dgs), and is evident by the waveforms o f caseAl.2 and A1.3 in Figure
3.9(a). Note that for a 3fo multiplier at the optimum conversion gain point (Pin=OdBm)
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
89
there is -17.2 dBm o f 3fo power which could be reflected to improve output 3fo power
and conversion gain. Also, in the actual real world device model, there is a nonlinear
capacitor which could mix fo and 2fo power for re-reflection of 3fo power. Thus, this
reflected harmonic power is of interest for the design o f frequency multipliers, as will be
discussed in Section 3.ii.d (page 141).
3. a. a. 5. a. Case B l, Pinchoff Bias
Case B l represents a typical “class B” bias and input configuration. For case B l, the
transistor is biased at the pinchoff voltage and the magnitude o f the AC input is increased
incrementally as shown in Table 3.1 on the fourth column. All three input signals (see
Table 3.1, column 4) are overlaid as traces in Figure 3.14(b). Figure 3.14 is generated
from ADS output.
0.03
. 0.02
CO
T3
0.03
f
(a)
/
0.03
0.02
/1
0.01
“
0.01
“
4
time (sec)j(
-1
Vgs (V)
xIO
(d)
0.01
6
1
\
2
Vds (V)
4
2
Vds (V)
4
----- Vg = |Vp|/2 (Case B 1.1)
Vg = |Vp| (Case 81.2)
..... Vg = 2|Vpl (Case 81,3)
0
e;.....
0-2
<
u
(0
|4
.......
*.......
6
-2
I
A '►j
-1
Vgs (V)
Figure 3.14. W aveform Plot for Case B l
C:\2_Stdy_Idlzd_Mdl\ mode!A_caseB_wfplot_l_21_03.fig
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
90
In this case, the output waveform is no longer proportional to the sinusoidal input.
Cases B l .1 and B l .2 show a current output waveform that is a half-wave rectified
sinusoid, whose magnitude increases as Vg is increased. This clipping effect is expected
to cause harmonics in the output. The Fourier series o f the half wave rectified sine wave
o f the current output waveform results in an output containing even-order harmonic
content proportional to the peak output current. This can be calculated by using plugging
the input signal and bias voltage for case B l.l and B1.2 into Equations ( 3.2 ) and ( 3.3 ).
The voltage output waveform at the drain is also a clipped sinusoid, following the
relationship with the output current given in Equation ( 3.9 ). For case B1.3, the large
magnitude o f Vg causes gate voltage clipping at OV, causing the output current waveform
to be clipped at both ends.
Figure 3.15 is a Fourier series representation which was obtained from ADS
simulation. The figure shows the harmonics for the waveforms in case B 1. Also o f note
is the shift in bias effect in the drain current. Figure 3.15(a) shows only a DC and
fundamental component at the gate for cases B l.l and B 1.2. Case B 1.3 shows other
harmonics due to the clipping at a gate voltage o f OV. Figure 3.15 (b) shows, for Case
B l.l and B 1.2, the fundamental and even order harmonics in the drain current. CaseB 1.3
shows even and odd harmonic output current, corresponding to a double-sided clipped
waveform which is not symmetric. From Figure 3.15(b), note that the DC drain current
increases from 3.9 to 7.5 to 10.5 mA. Figure 3.15 (c) shows output voltage harmonics
which correspond with the output current harmonics, as related by Equation ( 3.9 ).
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
91
1
0.9
(a)
►
1----■i
—
0.8
E
D)
CO
C ase B1.1
0 . 7 ■ __
0 . 6 J1
J ik k C ase B1.2
C ase B1.3
0.5
cn
C3)
> 0.4
0.3
ir
0.2
0.1
0
—
i
Freq (GHz)
X
9
10
Freq (G^z)
X
10
Freq (GHz)
X
10
Figure 3.15. Fourier Series Representation o f Case B l W aveform s (a) Vgs (b) Ids (c) Vds
C:\2_Stdy_Idlzd_Mdl\modelA_caseB_fsplot_l_24_03.fig
Figure 3.16 shows a plot o f the output power at the drain vs. the available power
(Pin) at the gate, for case B l. As expected, for an available input power o f below -1 dBm
(corresponding to a Vg o f 0.6) the output power only occurs at the fundamental and even
order harmonics (due to pinchoff effects). In this region, as the available input power is
increased, the value o f the peak current is increased proportionally. This translates to an
increase in the output power that is linearly proportional with the increase in the input
power. When Pin becomes greater than -1 dBm, the gate source diode begins to turn on.
The third harmonic rises and even and odd harmonics are present in the output current,
this is the result o f the gate voltage now being clipped (at the forward conduction
voltage). As Pin gets even larger, the output current waveform begins to resemble a
square wave, and the third harmonic becomes dominant, while the even order harmonics
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
92
drop down. Figure 3.16 also shows the agreement between the idealized model
simulation and theoretical calculation conducted on Matlab as previously described.
,
E
Q..Q..E1
-1
0
CO
•D -15
3
—
—
o
Q. -20
-25
O
-30
X
□
B
-35
4
_L
-40
10
Sim @ fo
Sim@ 2fo
Sim@ 3fo
Calc @ fo
Calc @ 2fo
Calc @ 3fo --------
-6
-2
0
2
Pin (dBm)
10
Figure 3.16. Power Available at the Gate (Pin) vs. Power Output at the Drain for Case B l
C:\2_Stdy_IdIzd_MdI\ modeIA_caseB_pwrplot_l_22_03.fig
Once again, Equation ( 3.11 ) is utilized to calculate the conversion gain response,
shown in Figure 3.17.
The above described circuit arrangement has been advertised (by Mass [3], Camargo
[6 ] and many others) as optimum for 2fo multiplication. As such, optimum 2fo output
power is obtained for an input power o f around 0 dBm. This input power also gives the
optimum 2fo conversion gain (Figure 3.17). However, here there is no 2fo power
available at the gate for reflection (as will be shown in Figure 3.18). Also o f note, for
higher input power levels o f around 6 dBm, 2fo and 3fo have about the same output
power and approximately equal conversion gains, but as will be shown in Figure 3.18,
there is 5 dB greater 2fo available at the gate for reflection.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
93
C G @ fo
C G @ 2 fo
C G @ 3 fo
-20
-3Q
-10
Pin (dBm )
Figure 3.17. Power Available at the Gate vs. Conversion Gain for Case B l (VGO=Vp)
C:\2_Stdy_Idlzd_Mdl\modelA_caseB_CGplot_9_29_03.fig
'S
Sim @ fo
Sim @ 2fo
Sim @ 3fo
-25
-30
-35
-4 0
-10
Pin (dBm)
Figure 3.18. Power Available at the Gate (Pin) vs. Reflected Pow er at the Gate (Pref) for M odel A,
Case B l
C:\2_Stdy_Idlzd Mdl\ modelA_caseB_prefplot_l_22_03.fig
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
94
As explained for case A l, the reflected power at the gate of the transistor is also o f
interest. Figure 3.18 shows the available (Pin) vs. the reflected power for case B l. Case
B l also shows significant levels o f reflected power at the second and third harmonics.
Similar to case A l, the second and third harmonic reflected power levels arise as the
gate-source diode is driven into conduction.
3. a. a. 5. Hi. Case Cl, Bias at Forward Conduction
Case C l represents a gate bias voltage o f OV, at the forward conduction voltage o f the
gate-source diode. Figure 3.19 shows a waveform plot o f the device for case C l.l, C1.2
and Cl .3. The output waveforms o f this case are the mirrors of case B 1. Therefore the
responses are the same in terms o f the magnitude o f the output harmonic content [5].
However, the input waveforms for case B l and Cl are quite different. For case C l.l and
C l.2, the clipping occurs at the gate (due to Dgs) where in case B l.l and B 1.2 it occurs in
the Ids current source (due to swinging below Vp). As a result, the harmonic content
appearing at the gate is significantly different between case B l and case C l. In fact, the
output power at the second harmonic for case C l.l and C 1 . 2 comes from amplification o f
the second harmonic voltage created at the gate by the Dgs diode.
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95
------- r
0.03
(a)
0.03
.0.02
.0.02
(/>
T3
0.01 ------- -------
.5
/
r / -------r '
/
-1
-0.5
Vgs{V)
0.01
(c) ;
0.03
—
\
.0.02
t
i f if
iV 1
tr r
=.\ /.=
■tt"
time (sec) xIO
(d)
■
0.01
10
;
Y
_ _
—
Vds(V)
Vg = |Vp|/2 (Case C l.l)
Vg = |Vp| (Case C l.2)
Vg = 2|Vp| (Case C l.3)
C’*'
C
-1
-0.5
Vgs(V)
Vds (V)
Figure 3.19. W aveform Plot for Case C l
C:\2_Stdy_Idlzd_Mdl\ modelA_caseC_wfplot_l_2 l_03.fig
This amplification can be described by expanding the gate-source waveform into a
Fourier Series and plugging it into Equation ( 3.13 ), giving:
^ FGO + VgSf„ c o s { q} J ) + Vgs^fo c o s { 2 q} J ) + • ■•
Ids = 1DSS
Vp
= /,D SS
Vp
(3.14)
So, for example, the amplification o f the resulting second harmonic current
component for case C1.2 (where Vgsafo = .12 V, as will be shown in Figure 3.20) is then
given by:
Ids 2f o
Vgs2fo
•^DSS
Vp
12F
= -25mA *--------- = 5mA
-0.6V
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
(3.15)
96
Figure 3.20 shows the ADS simulation o f the gate voltage (Figure 3.20(a)), drain
current (Figure 3.20(b)), and drain voltage (Figure 3.20(c)) harmonics. The second
harmonic content o f the simulated gate-drain current for case C l.l (Idsifo = 2.4mA) and
case C l.2 (Ids2 fo = 5mA) agree exactly with the calculated response using Equation (3.15
)•
0.025
:(b)
(C)
2.5J
0.02
fP
C a s e C 1 .1
C a s e d .2
-
<:
O)
0.015
B
5 1 .5
CD
■D
C ase 0 1 .3
0 .0 1
0.005
0
3
6
Freq (GHz),
0
xIO
3
6
Freq (GHz)
xIO
X
10
Figure 3.20. Fourier Series Representation o f Case C l W aveforms (a) Vgs (b) Ids (c) Vds
C:\2_Stdy_Idlzd_Mdl\modelA_caseC_fsplot_l_24_03.fig
The difference in gate harmonics between cases B l and Cl may become very
significant when considering the choices o f input network M l, which will manipulate the
various gate harmonic signals. Another consideration is DC power dissipation in the
gate-source diode, which is more significant for case Cl since the diode is always
conducting for a half-cycle. As exhibited by comparison o f Figure 3.15 and Figure 3.20,
case C l also has a significantly larger DC current flow at the drain.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
97
Figure 3.21 shows a plot o f the output power at the drain versus the available power
(Pin) at the gate, for case C l.
B
l
I
I
I
“
'^•* 61.
j _
0
*
S-15
"3
— Sim @ fo
—— Sim @ 2fo
. . . . Sim @ 3fo
Calc @ fo
0
X Calc @ 2fo
□ Calc @ 3fo
o
Q- -2 0
-25
ia
-30
-35
[ 1 -•
-40
-10
-0 -
-
d
- - 0
-2
-8
0
2
10
Pin (dBm)
Figure 3.21. Power Available at the Gate vs. Power O utput at the Drain for Case C l ”
C:\2_Stdy_Idlzd_Mdl\ modelA_caseC_pwq)lot_l_22_03 .fig
The power response for case Cl is equivalent to caseBl, as both the simulation and
MATLAB theoretical calculation show*. The corresponding conversion gain response
for case C l is shown in Figure 3.22.
* N ote that there is a negligible difference between case C l and B l shown in the 3 fo output pow er response
for an input pow er range o f -10 to -1 dBm. This difference occurs because, for sim ulation purposes, for
case C l the gate bias w as set slightly offset from the forward conduction voltage (V G 0=-0.01 V , instead o f
VGO=Vfwd=OV)
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
98
C G @ fo
C G @ 2 fo
C G @ 3 fo
CO
CD
____
^ ^ - 1 0
-20
-3Q
...........
-10
Pin (dBm )
Figure 3.22. Power Available at the Gate vs. Conversion Gain for Case C l (VGO=Vfwd)
C:\2_Stdy_Idlzd_Mdl\modelA_caseC_CGplot_9_29_03.fig
Figure 3.23 shows the reflected (Pref) vs available (Pin) power for case C l.
-10
-15
Sim @ fo
Sim @ 2fo
Sim @ 3fo < -40 dBm
-25
-30
-35
-40.
-10
Pin (dB m )
Figure 3.23. Power Available at the Gate (Pin) vs. Reflected Power at the Gate (Pref) for M odel A,
C aseC l
C:\2_Stdy_Idlzd_Mdl\ modelA_caseC_prefplot_l_22_03.fig
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99
Figure 3.23 shows a very interesting property for case C l. All o f the reflected power
for this case occurs at the second harmonic. This second harmonic power is at a
significantly larger level than in case B l, especially for smaller input power levels. This
extra reflected power may prove advantageous in the design o f a frequency doubler.
3.iLa.5.iv. C aseD l, Conduction Angle Study
As described in section 3.ii.a.2, a standard method o f designing frequency multipliers
is to utilize a varied, single-sided, clipping duration in the drain-source waveform by
varying the conduction angle <}) (given by Equation (3 .2 )). For case D1 the harmonics
generated for a varying conduction angle were studied utilizing the idealized model. As
shown in Table 3.1, column 2, the gate bias voltage was swept to effectively sweep the
conduction angle (|), resulting in varied harmonic output levels. Figure 3.24 shows a
waveform plot for case D 1.
Figure 3.24(a) shows the DC Ids versus Vds relationship,
as previously shown. Figure 3.24(b) shows the Vgs waveforms for case D 1. The input
voltage magnitude is left constant (Vg = 0.3V) and the DC bias VGO is swept from the
point where the device never turns on (VGO = 3 Vp/2 = -0.9V, Case D 1.1) to the point
where the device is conducting for a full cycle (VGO = Vp/2 = -0.3V, Case D 1.5). The
corresponding output current waveforms, shown in Figure 3.24(c), are sinusoids which
have undergone different amounts o f clipping. This clipping duration is represented by
the conduction angle, defined in Equation ( 3.2 ). As presented in Maas [3], variance in
the conduction angle equates to varying the amount o f clipping caused in the Ids current
source.
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100
0.03
VGQ=Vp/:j
< 0,02
< 0,02
200
-0,5
Vgs(V)
n
400
6 00
theta (deg)
VG0=Vp/2
S300
£500
-0,5
Vgs(V)
Figure 3.24, W aveform Plot for Case D1
C:\Research\Thesis\Multiplier Fundamentals old\Figs for ideal ckt modeling paper\figl2_fix2.ai
The resulting harmonic content in Ids as a function o f conduction angle (normalized to
the peak current), was presented in Equation ( 3.3 ), and is shown in Figure 3.25. The
simulated results in Figure 3.25 correspond with a typical calculated conduction angle
plot [3;43], where Idsn(([)) is plotted as a function o f 2(|) (Equations ( 3.2 ) and ( 3.3 )).
The figure shows points o f maximum output current at the first three harmonics. A
conduction angle o f about 60 ” (2^ =
1 2 0
°) represents a point o f maximum output current
at the second harmonic and a conduction angle o f 40° {2^ = 80°) represents a point o f
maximum output current at the third harmonic. Using these optimum points, a multiplier
with large amounts o f second and third harmonic output power can be designed. Further
exploration o f these optimum points is presented in the next section.
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101
0.6
0 .5
ld si/lp
0 .4
,JCL
ldS2/lp
of 0 .3
— Calculated
■ Simulated
0.2
ldS3/lp
2*({) (degrees)
Figure 3.25. Norm alized Output Harmonic Current (Ids„/Ip) vs. Conduction Angle (2*(|))
C:\Research\Thesis\Multiplier Fundamentals old\Figs for ideal ckt modeling paper\figurel3_fixed_c.ai
3.ii.a.5.v. CaseE - Special Cases: Optimum Designs Using Idealized Model
A benefit of using the idealized model (model A) is that it can be used to verify
existing design techniques and locate input and bias levels for optimum conversion
gain frequency multipliers. Model A was simulated for simultaneously swept* values
o f gate bias and input voltage level to obtain an optimum conversion gain design both for
second (doubler) and third (tripler) harmonic output. These designs are compared below
to the standard design techniques o f [3-5;43].
The simultaneous sw eep consisted o f varying both the gate bias voltage and input voltage level over
sp ecific ranges such that all gate bias voltage-input voltage level combinations were tested through A D S
simulation. Throughout this work the term “simultaneous sw eep” refers to a sw eep o f this nature, where all
com binations o f the variables under test are simulated.
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102
Designs for Large Second Harmonic Output
Several doublers were designed (in ADS) with model A using different techniques.
The first design was created by choosing the conduction angle for optimum 2fo output
(see Figure 3.25) as described by Maas [3;50] as well as Clarke and Hess [43]. The
second uses a generalized approach by O’Ciardtha et al [5], which chooses a bias level
and input voltage to create an output waveform which approximates a rectangular wave
with a 0.25 duty cycle. The third and fourth designs were created by simultaneously
sweeping* the input voltage and bias to find points o f maximum conversion gain. The
results are summarized in Table 3.2 (a) and (b).
Table 3.2. Optimum Doubler Designs Using Idealized M odel
fa) R esults o f O p tim u m D o u b le r D e s ig n s U sing de a lize d M odel (M oc el A)
P a va il fo P o u t 2fo
A u tho r
VGO (V) V g (V)
T e ch n iq u e
(d B m )
(dB m )
M aas
O 'C ia rd h a
T his W o rk
T his W o rk
C o n d . A ng le T echnique:
2<b= 120 dea
G e n e ra liz e d A p proach :
R ect. W a v e fo rm 0.25
D u lv C ycle
O p t f o r C G using
Ide a lize d M o d e l (N e a r
P inchoff)
O p t f o r C G using
Id e a lize d M o d e l (N e a r
V hvd)
-1 .2
1.2
5 .5 6
0 .7 5
-4 .8 2
-1 .5 6
1.86
9.37
1.68
-7 .6 9
-0 .5 9
0.56
-1
-2 .0 7
-1 .0 7
-0.01
0.56
-1
-2 .0 7
-1 .0 7
(b) C o m p a ris o n o f R e su lts o f T h is W o rk w it 1 P re v io u s A u th o rs
P re v io u s
A u th o r
M aas
APout 2fo
(This Work - Previous Author)
ACG 2fo
(This Work - Previous Author)
-2 .8 2
-3 .7 5
3 .7 5
6 .6 2
O 'C ia rd h a
C G 2fo
(d B )
C:\2_Stdy_Idlzd_Mdl\caseE optimum designs\table_of_results_l_28_03.sxc
As defined above on page 101.
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103
The results shown in Table 3.2 are quite interesting. Maas’ design shows a large
output power level at the second harmonic. As he states however (on page 402 o f [50]),
one o f the shortcomings o f using this optimum “short” conduction angle method is that
the required input signal level causes the conversion gain to be poor. The design using
the method o f O’Ciardha has the same drawback. It leads to an even larger output power
level, but its conversion gain is even worse. These methods point out a difference in
philosophy between current design techniques and the aim of this work, which is focused
on the design o f multipliers for conversion gain, rather than output power. The above
two results are obtained by maximizing the output power level, described by Equation (
3.10 ), when the aim o f this work is to maximize the conversion gain, described by
Equation (3 .1 1 ). By sweeping the input signal level and bias, points o f optimum
conversion gain were found for the second harmonic. As shown in Table 3.2, this
resulted in two designs, both o f which had a lower output power level than the previous
method but had significantly higher conversion gain. These optimum designs were found
at two biases; one very close to pinchoff and one very close to forward conduction. This
result corresponds with several known large conversion gain frequency doubler designs
[6;23;42;45;47], and also to the cases B l and Cl shown in this study. More details on
these designs can be found in Appendix B.i.a . 6 and Appendix B.i.a.7 on pages 465 and
466, respectively.
Designs for Large Third Harmonic Output
Some optimum tripler designs were also tested on the idealized model. The first uses
the optimum conduction angle for maximum normalized third harmonic output current
(Figure 3.25), described by Maas [3]. The second uses the method proposed by Fudem et
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104
al [4], which consists o f biasing the device midway between pinehoff and forward
conduction and overdriving the input to create a square wave. The third uses an approach
suggested by O’Ciardha [5], where a rectangular waveform with strong third harmonic is
created on the output. Finally, the model was simultaneously swept* to find a point o f
optimum conversion gain for the third harmonic (VGO, Vg). The results are summarized
in Table 3.3 (a) and (b).
Table 3.3. Optimum Tripler Designs Using the Idealized M odel
(a ) R e su lts o f O p tim u m T rip le r D e s ig n s U s in g Id e a liz e d M o d e l (M o d e l A)
P a v a il fo P o u t 3fo
(d B m )
(d B m )
C G 3fo
(d B )
A u th o r
T e c h n iq u e
VGO (V )
V g (V)
M aas
C o n d . A n g le T e ch n iq u e :
2d) = 80deq
-2 .5 6
2 .5 6
1 2 .1 6
-2 .2 7
-1 4 .4 3
Fudem ,
N Ih e n ke
O v e rd riv e n Input: S q u a re
W a v e fo rm on O utput
-0 .3
2 .5 2
12
-1 .7 3
-1 3 .7 3
O 'C ia rd h a
G e n e ra liz e d A p p ro a c h :
R e ct. W a v e fo rm (1/6)
D u tv C vcle
-3 .6
4 .2
1 6 .4 4
-2.51
-1 8 .9 6
T h is W o rk
O p t f o r C G u sing
Id e a liz e d M o d e l
-0 .2 9
0 .6 0
-0 .4
-5 .2 3
-4 .8 3
(b) C o m p a ris o n o f R e sults o f T h is W o rk wi th P re v io u s A u th o rs
P re v io u s
A u th o r
APout 3fo
(This Work - Previous Author)
ACG 3fo
(This Work - Previous Author)
M aas
Fudem ,
N ih e n k e
-2 .9 6
9.6
-3 .5
8.9
O 'C ia rd h a
-2 .7 2
1 4 .1 3
C;\2_Stdy_Idlzd_Mdl\caseE optimum designs\table_of_results_l_28_03.sxc
Table 3.3(a) shows that the previous methods [3-5] provide greater output power than
this work; however at the expense o f much larger required input power (from 12.4 to
* The gate bias (VGO) and input voltage magnitude (V g) w ere simultaneously sw ept as defined on page
101 .
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105
16.844 dBm more). The current work also provides from 8.9 to 14.13 dB more
conversion gain than any o f the previous ones.
Similar to the case o f doubler designs, current techniques for designing triplers result
in large output power levels at the third harmonic, but do not necessarily give the
optimum conversion gain. Interestingly, the optimum conversion gain did occur at a bias
o f approximately midway between pinchoff and forward conduction. This bias
corresponds with the design o f Fudem et al [4], and case A1 shown in this study. The
difference between this work and the design o f Fudem et al [4] becomes apparent by
comparing the drain-source current waveforms o f the two designs. Figure 3.26 shows the
drain-source current waveforms corresponding to the optimum designs o f this work (solid
trace) and Fudem et al [4] (dashed trace).
0.03
This W ork
Fudem e ta l
0.025
0.02
<
(/>
■o
0.0 1 5
0.01
0.005
-0 .0 0 5
Time (sec)
X
10
-10
Figure 3.26. Comparison o f Drain-Source Current W aveform s for Optimum Tripler Designs
C:\2_Stdy_Idlzd_Mdl\caseE optimum designs\trip_compare_fudem Jess_l 1_1 l_03.fig
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106
Figure 3.26 shows a vital consideration. In the work o f Fudem et al, where the
response is optimized for 3fo output power, the transistor is overdriven such that the
output current waveform resembles a square-wave, rich in third harmonic content. In this
work, where the response has been optimized for 3fo conversion gain, the output current
is still a double-sided, clipped sinusoid. However, in this work this drain-source current
waveform is trapezoidal in shape. Thus the more desirable Ids waveform from the
perspective o f conversion gain is a trapezoidal waveform, even though a square
waveform exhibits higher third harmonic output power.
More details on the designs o f Table 3.3 can be found in Appendix B.i.a . 8 (page 467)
and Appendix B.i.a.9 (page 468).
3.ii.a.6. Summary of Input Signal and Bias Study
A transistor model has been created to give an approximated and simplified response
based on the response o f an actual PHEMT transistor model. The model allows
quantitative exploration and analysis o f harmonic generation in an ideal sense. Several
non-linear simulations o f the model show a response that agrees with theory. This model
allows input and bias levels for optimum conversion gain to be found for the most
fundamental case. It also provides a baseline for further idealized frequency multiplier
designs and the quantitative analysis o f devices o f increased complexity.
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107
5.11.b. Impedance Matching @ the Fundamental
3.11.b.l. Basic Considerations
In addition to consideration o f the input signal and bias level, variation o f the input
network M l (Figure 3.1) is o f vital importance. For the previous section, the input
impedance Zmi was set to equal 50 ohms for all frequencies. The first step in exploration
o f the choice for M l is to vary the impedance presented to the fundamental frequency fo.
In small-signal amplifier design, it has been well established that transducer gain can be
optimized on the input side by using M l to present a conjugate impedance match to the
input o f the transistor [51]. In a large-signal multiplier design, the question o f input
matching becomes more complicated for several reasons.
1.
If the design is operating at a small enough power level, than using a small-
signal approximation may be sufficient to estimate the devices’ input impedance.
Flowever, at large input power levels, typical o f a frequency multiplier design, the
definition o f input impedance is less concrete. Maas raises the possibility o f using the
“large-signal impedance” at the fundamental frequency, which is defined by equation
3.1.29 in [3]:
Z
= ^ - Z
J
(co )
P)
( 3 .1 6 )
2,1
Where, Zi„ is the fundamental frequency input impedance. Vs is the AC input voltage
magnitude, l 2 ,i is the input current from the source, and Zs(cop) is the source impedance.
In this work. Vs is represented by Vg, l 2 ,i is represented by Ig, and Zs(cOp) is represented
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108
by Rgen as shown in Figure 3.27. Maas states that this input power level dependent
impedance Zin can be used to match the input o f a non-linear device, such as a diode.
Several authors [12;13] have presented techniques which use this “large-signal matching”
concept in the design o f frequency multipliers. Unfortunately, the specific details o f
calculation and utilization o f this large-signal concept cannot be found upon perusal o f
available literature.
2.
Even given the existence o f a “large-signal” matching concept, there is limited
knowledge about whether or not using this concept to provide a match at the fundamental
frequency represents the optimum condition for frequency multipliers.
In order to gain more understanding about presenting optimum impedance for the
fundamental frequency with the network M l, the idealized model (model A) is again
utilized. The input network M l is designed to present model A with a variable
impedance at the fundamental frequency ZMi(fo), without affecting the 50 ohm
impedance seen by the higher order harmonics. This is achieved using the circuit shown
in Figure 3.27.
M1
M2
Ids
2fo, 3fo
Isolator
Vds
Vgs
Vdd
:VGO
Figure 3.27. Circuit Configuration for Variation in Z mi at the Fundam ental Frequency
C:\Research\Figures\jj m lm 2 input_imp_b BD.ai
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109
An isolator is used to attenuate the reflected signals at the higher order harmonics.
This ensures that the second and third harmonic content at the gate is not manipulated by
the network M l, and does not contribute to any additional conversion gain. Behind the
isolator, a simple quarter-wavelength transmission-line is used to present a real
impedance to the fundamental frequency. The equivalent impedance
is given by
Equation ( 3 .1 7 ) below.
zo
Rgen
p
nfo
n=\
gen
n>\
Rdc
n-0
( 3 .1 7 )
Where Rgen and Rdc are equal to 50 ohms. Note that for n>l, the isolator suppresses
the reflected wave so that the input impedance looks like fifty ohms (no reflection occurs
looking into the isolator). The impedance Zmi^^presented is varied by varying the
characteristic impedance, ZOmi, o f the transmission-line. This allows the effects of
varying the impedance o f M l at the fundamental frequency on the conversion-gain o f the
idealized model to be observed. The effects o f varying Zmi^qwere conducted for
casesA l, B l, and Cl explained in Section S.ii.a (Table 3.1). A schematic o f the ADS
simulation is shown in Appendix B.i.b.l (page 469), the results are presented below.
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110
3.ii.b.2. Case Al;
■D
-1 0
-30
-40
CG @ 2fo
CG @ 3fo
-50
-60
100
200
300
400
500
600
700
800
900
1000
^M1. (Ohms)
Figure 3.28. Conversion Gain and Fundam ental Gate Reflected Power Level vs. Fundam ental Input
Im pedance o f M I, M odel A, Case A l, Pin = -10 dBm
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Figure 3.28 shows the conversion gain (at the first three harmonics) and reflected
power (at the fundamental frequency) versus the input impedance o f the matching
network M l at the fundamental frequency for an input power level o f -10 dBm. Note
that the previous section showed the output response in terms o f the power level,
corresponding to Equation ( 3.10 ). In order to examine harmonic generation relative to
the fundamental input power level, here the output response is shown in terms o f
conversion gain, corresponding to Equation (3.11 ). The “conversion gain” at the
fundamental frequency represents the gain o f the device, defined as the ratio o f the
fundamental output power to the fundamental available power (Pin). Figure 3.28 shows
an interesting phenomenon. As the fundamental input impedance o f M l is increased, the
fundamental reflected power at the gate begins to decrease. Simultaneously, the
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Ill
fundamental and third harmonic output power begins increasing. When the gate reflected
power reaches a minimum point, the optimum fundamental and third harmonic output
power levels are achieved. The effect o f this impedance is very significant. No third
harmonic output power exists for a 50 ohm impedance (corresponding to the input power
and bias level study in the previous section). As the input impedance o f Ml is increased
however, the third harmonic conversion gain reaches a maximum o f about -2 dB. The
point where the reflected power reduces to zero (less than -60dBm at Zmi^, = 680 ohms)
represents a “matching” condition in that, for an incident power at the fundamental
frequency fo, there is no fundamental reflected power. Another important phenomenon
the plot shows is that any impedance ZMq^ from around 400 up to 1000 ohms provides
about the same third harmonic conversion gain while also leading to very low reflected
power levels.
Perusal o f the gate voltage waveforms for this case shows that the use o f the optimum
value impedance for Zmi^-q, (Zmi^ = 680 ohms), increases the gate voltage swing for a
fixed input power level. This, in turn, causes the transistor to swing above the gatesource forward conduction voltage and swing below the pinchoff voltage. This results in
a double-sided, clipped output current waveform, which was shown in the previous
section (Section 3.ii.a) to have strong third harmonic output levels. The gate voltage and
drain current waveforms are shown in Figure 3.29.
The increase in the gate voltage magnitude can be attributed to the impedance
mismatch between the generator and the quarter-wavelength section. As the
characteristic impedance o f the quarter-wavelength transmission line section is increased,
the voltage standing wave ratio between the generator and the transmission line is
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112
increased. This, in turn, causes an increase in the voltage signal entering the transmission
line section and correspondingly the voltage appearing at the gate o f the transistor.
0 .0 2 5
0 .0 1 5
- 0 , 5 -------0 .0 0 5
ZM1 j^= 50ohm
ZMI = Opt
-0 .0 0 5
Time (sec)
^
q
Time (sec)
Figure 3.29. W aveform comparison for Case A l, Pin = -10 dBm
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A sweep o f the input impedance
was repeated for a larger input power level o f 0
dBm, and the conversion gain and reflected power was characterized as previously shown
in Figure 3.28 (for Pin = -lOdBm). The results are shown in Figure 3.30.
Figure 3.30
shows that the variation in Zmi^q is less effective for a larger input signal level. The
maximum third harmonic conversion gain attained is -4 dB for Zmi^^equal to 155 ohms,
which only represents a 1 dB improvement over the standard case when Zmi^^ is 50 ohms.
It is interesting to note, however, that the maximum conversion gain again occurs at the
point where the gate reflected power at the fundamental is minimized.
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113
■D - 1 0
S5-15
CG @ fo
CG @ 2fo
CG @ 3fo
Pref @ fo
-25
-30
1 0 0
150
ZM I. (Ohms)
200
250
300
Figure 3.30. Conversion Gain and Fundam ental Gate Reflected Power Level Versus Fundam ental
Input Im pedance o f M l, M odel A, Case A l, Pin = 0 dBm
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Match\inputmatch_swp_4_14_03\modelA_HB_wMl_matchswpJj_caseA_pin_0_plot_4_29_03.fig
0.2
0.03
50 ohm
155 ohm
0.025
-
D)
>
0.02
0.2
-0.4
^
- 0.6
-
<
0.015
CO
-
0.01
0.005
0.8
-0.005
Time (sec)
x10'^°
Time (sec)
x10'^°
Figure 3.31. W aveform Comparison for Case A l, Pin = 0 dBm
C;\Research\l_B_I Undrstndng NL MechVB Stdy Idlzd Mdls\ii Harm_Gen_via_Input_Cond\b fo Impedance
Match\inputmatch_swp_4_14_03\ modelA_HB_wM l_matchswpJj_caseA_pin_0_wfplot_4_29_03.fig
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114
Figure 3.31 shows the gate voltage and drain current waveforms for Zmi^^values o f 50
ohms and the optimum 155 ohms. Comparison o f the gate voltage waveforms reveals
that changing the
has a much less drastic effect for the larger input power level.
3.ii.b.3. Case Bl:
The study for case A l above was repeated for case B l (bias near pinchoff region), the
results are presented below.
20
■o - 2 0
c
CO
“ -30
■
■
-40
-50
-60
500
CG @ fo
CG @ 2fo
CG @ 3fo
Pref @ fo
1000
1500
ZMI^^ (Ohms)
2000
Figure 3.32. Conversion Gain and Fundam ental Gate Reflected Power Level Versus Fundam ental
Input Im pedance o f M l, M odel A, Case B l, Pin = -10 dBm
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Figure 3.32 shows the conversion gain (at the first three harmonics) and the reflected
power (at the fundamental) versus the fundamental input impedance o f M l (ZmIj-^) for an
input power level o f -10 dBm. Similar to the result for case A l when the input power
was -10 dBm, the effects o f the input impedance Zmi^, are drastic. The second and third
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115
harmonic conversion gains are both significantly increased when the reflected
fundamental power level is brought down with an increasing ZMif^- The second harmonic
conversion gain reaches a maximum o f about 8.5 dB for a
between 450 and 1500
ohms, where only -1 dB o f conversion gain occurred when Zmi^^was 50 ohms. This
represented a 9.5 dB improvement by utilizing a larger Zmi^,. Unlike case A l, however,
the maximum conversion gain did not occur exactly at the point where the reflected
power reached a minimum.
The mechanism for the substantial improvement is similar to that o f case A l, and is
illustrated by observing the gate and drain waveforms, shown in Figure 3.33.
0 . 0 2 5
-
0.2
0.02
- 0 . 4
+ 1
0 . 0 1 5
,- 0.6
“ 1
D)
I
CO
0.01
T3
I
-
I
0.8
I
I
I
0 . 0 0 5
f
ZM1j^ = 50 ohm
I
ZM 1, = 4 5 0 ohm
- 0 . 0 0 5
0
2
4
T im e (s e c )
6
xio"'°
T im e (s e c )
xIO
-10
Figure 3.33. W aveform Comparison for Case B l, Pin = -10 dBm
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Perusal o f the gate voltage waveforms in Figure 3.33 shows that the use o f a large
impedance value (Zmi^, = 450 ohms) greatly increases the gate voltage swing. This, in
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116
turn, increases the peak drain current obtained for the given input power level o f - 1 0
dBm. The increase in peak current correspondingly gives a larger output power at 2fo, as
evident by Equation ( 3.3 ).
3.ii.b.4. Case Cl:
A sweep o f Zmi^^was also conducted for case Cl (bias near Vfwd = OV).
D^Q
p
0
^
-10
Q.
■a
c
-2 0
05
S'
-3 0
;o^
C G @ fo
C G @ 2 fo
C G @ 3 fo
P ref @ fo
CD -4 0
O
-5 0
-60.
100
150
200
ZMI,
(O h m s)
250
300
350
Figure 3.34. Conversion Gain and Fundam ental Gate Reflected Power Level Versus Fundam ental
Input Im pedance o f M l, M odel A, Case C l, Pin = -10 dBm
C:\R esearch\l_B_l UndrstndngNL Mech\B Stdy Idlzd Mdls\ii Harm_Gen_via_Input_Cond\b fo Impedance
Match\inputmatch_swp_4_14_03\modelA_HB_wM I_matchswpJj_caseC_pin_mI0j)Iot_4_28_03.fig
Figure 3.34 shows the conversion gain (at the first three harmonics) and the reflected
power (at the fundamental frequency) versus the input impedance o f M l (ZmIj-^,), for an
input power level o f -10 dBm. For case C l, similarly to the other cases, the effects o f
ZMifo are significant. In comparison to case B l, case Cl also exhibits a strong second
harmonic output level. However, the second harmonic conversion gain is optimized for a
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117
much lower impedance for case C l. In fact, the optimum impedance for Zmi^, is close to
50 ohms for this case. Similarly to case A l, this optimum conversion gain point also
occurs where the reflected fundamental power level reaches a minimum.
The fact that the optimum conversion gain point occurs near 50 ohms for case C l may
be advantageous when compared to case B l, which necessitates a much larger value for
ZMifQ (which can lead to difficulty in implementation). However, for case B l a much
larger conversion gain is achieved.
3.ii.b.5. Summary of Input Impedance Matching Study
Through sweeping the input impedance o f the input network M l at the fundamental
frequency, some important characteristics have been found. The choice o f impedance
presented to the fundamental can have a drastic affect on the conversion gain o f a
multiplier. This is shown to occur for all three bias cases shown above. For all three
cases, optimum conversion gain (at 3fo for case A l and at 2fo for cases B l and C l), was
achieved close to the same impedance point where the fundamental reflected harmonic
power reached a minimum. Furthermore, some o f the cases exhibited a nearly constant
conversion gain over large changes in the input impedance value. This hinted that an
approximately optimum network could be sufficient to optimize the conversion gain.
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118
3.11.c. Input Bias Network
3.11.c.l. Basic Considerations
In Section S.ii.b, the response o f the input network M l at the fundamental frequency
was studied. The next consideration for the input network is its DC response or the input
bias network. The standard microwave DC biasing configuration, as described briefly in
Section S.ii.a.l, and shown in Figure 3.35, utilizes a separate AC and DC source path.
This setup is done with the use o f “bias-T” circuits, consisting o f a DC blocking
capacitance “C”, and an RF choke “L”, which isolate the AC and DC sources from each
other.
M2
M1
Ids
Vds
Rdc=Swept
Rl_=50Q
Vgs
VGO
Vdd
Figure 3.35. Circuit Configuration for Study o f Input Bias Network
C:\Research\Figures\jj m lm 2 input_bias_c BD.ai
As the AC and DC sources are isolated from each other, it is fairly commonplace to
consider the AC and DC circuits separately, and use the principals o f superposition to
consider the overall response. Unfortunately, in a nonlinear device such as a diode,
superposition cannot be used, as the AC and DC responses can interact with each other
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119
[43;52], On a very basic level, the input o f a FET/HEMT transistor is represented by an
ideal diode as shown in the ideal model (model A) utilized for this study (Figure 3.3). As
previously discussed in Section 3.ii.a, the nonlinearity o f this gate-source diode can be
utilized in the creation o f second and third harmonic content. A detailed schematic o f the
input-side o f the circuit configuration shown in Figure 3.35 is shown in Figure 3.36.
G a te
-O -n
gen =50Q
R d c= S w ept
VGO
— o -^
S ource
Figure 3.36. Detail Schem atic o f Input Configuration for Input Bias Study
C:\Research\Figures\jj m lm 2 input_bias_c BD_zoom.ai
Observing Figure 3.36, the overall current flowing through Dgs is the gate-source
current Igs. The use o f the bias-T forces the DC component o f this current (Igsoc) to
flow through the DC path and the AC component (IgSAc) to flow through the AC path.
Due to the nonlinear nature o f the diode, some DC current may be caused by the AC
input signal. This DC current component is forced by the bias-T network to flow through
the DC source path. Thus the consideration o f how the impedances in the DC and AC
paths interact with each other is important.
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120
The implication o f the interaction between the DC and AC signal can be illustrated by
example. If the gate-source diode o f the transistor is excited by an AC voltage with
magnitude Vg, and a DC bias voltage o f zero (VGO = OV), then the “expected” voltage
waveform appearing across the gate (Vgs) is as shown in Figure 3.37.
-
0.1
-
0.2
-0.4
-0.5
-
0.6
Vpeakmin ?=-Vg
-0.7
time (sec)
xIO
- 10
Figure 3.37. Expected Voltage W aveform Across Dgj
C:\ modelA_caseC_igswf2_l l_10_03.fig
The “expected” gate-source voltage waveform is equal to the AC input signal plus the
DC level when the gate-source diode is open, and equal to zero when the gate-source
diode is conduction, resulting in a gate-source voltage given by:
Vgs{t) =
VGO + Vg»cos(coj)
0
VGO + V g < 0
VG0 + V g > 0
The resulting minimum gate-source voltage swing is given by:
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( 3 .1 8 )
121
( 3 .1 9 )
V peak^ ^ = V G Q -V g
Which is equal to -Vg in this instance since the bias voltage is set to zero. The
corresponding current through the Dgs diode is given by:
VG0 + V g < 0
0
VGO + Vg»cos ( coj)
«------L _ ^
Rgen
VG0 + V g > 0
( 3.20 )
The resulting peak gate-source current is given by:
{VGO + Vg)
Rgen
Ip =
VG0 + V g > 0
( 3 .2 1 )
VGO + Vg < 0
0
Which is equal to Vg/Rgen in this instance when VGO is set to zero. The “expected”
gate-source current waveform is shown in Figure 3.38.
Consider now the impedance o f the input network to the Dgs diode. Due to the use o f
a bias-T, the impedance o f the input network is different for the AC and DC components.
The input impedance o f this circuit is:
[jRdc
Zm >
■gen
fo = 0
(DC)]
fo + 0
(AC)|
(3 .2 2 )
The fact that these DC and AC impedances are different has a significant implication
in the assumption o f what the waveforms in Dgs will be.
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122
0 .0 1 4
gen
0.012
0.01
^
0 .0 0 8
(0
-
0 .0 0 6
0 .0 0 4
0.002
T im e ( s e c )
xIO
-10
Figure 3.38. Expected Current W aveform in Dgs
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\ii Harm_Gen_via_Input_Cond\c Input Bias NetworkWVaveform
Plots\modelA_sim_vs_calc_2_4_03\calc_caseC2_Igs_plot_frmtd_2_4_03.fig
In Figure 3.38, the expected current waveform was a half-wave rectified sinusoid with
a peak current Vg/Rgen- A Fourier series analysis o f the waveform will show an average,
or DC current level of:
I p _ Vg
=
n nR
I g s DC = —
( 3 .2 3 )
Due to the action o f the bias-T, this DC current flowing through Dgs must flow
through the DC path, which contains the DC bias resistance Rdc. The resulting voltage
across this resistor Rdc (VRdc) is equal to:
VRdo=-IgSDc*^dc^-
Vg Rdc
n R,'gen
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( 3 .2 4 )
123
Since the DC supply is set to zero (VGO=OV) and the inductor o f the bias-T (L) is a
DC short, the value o f the DC level at the gate (Ygsoc) is equal to VRdc-
Vgs
' Rdc
( 3 .2 5 )
n
^ ^gen
Now, observing that the expected voltage waveform across Dgs in Figure 3.37 shows a
half-wave rectified sinusoid with a minimum voltage -V g, the DC voltage level can be
calculated by a Fourier analysis:
n
n
( 3 .2 6 )
In order for the idealized clipped waveforms to actually come out as expected, it is
clear that Equation ( 3.25 ) should be equal to Equation ( 3.26 ). This only occurs when
the chosen DC bias resistor Rdc is set equal to the AC generator resistance RgenA typical microwave circuit would have a 50 ohm AC source (Rgen = 50 ohms) and
zero ohms in the DC path (Rdc = 0 ohms), with extra, unwanted additions to Rdc due to
any resistance within the bias-T itself or the internal impedance o f the DC source. The
implications o f this are that an “ideal” clipped waveform analysis which includes clipping
due to Dgs will have unexpected results. In fact, when the value o f Rdc is very small, the
DC gate voltage level is forced to be equal to the bias voltage level VGO since there is no
DC drop across the choke in the bias-T [53]. The following sections will show, through
an in-depth analysis o f the idealized model, that the harmonic content generated by a
transistor can change significantly as a function o f the choice o f bias resistor Rde.
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124
3.11.c.2. Study Using Idealized Mode! (Model A)
In order to study the effects o f changing the DC bias resistor Rdc the circuit
configuration o f Figure 3.35 was utilized along with the idealized model (model A). The
input signal and bias levels o f cases A l, B l, and Cl (Table 3.1) were tested using the
ADS simulator. A schematic o f the ADS simulation used for this study is shown in
Appendix B.i.c.l (page 470). The waveforms generated by the model, the corresponding
harmonics, and the input versus output power levels were studied to determine how each
was affected as the value o f Rdc is varied.
3.11.c.2.i. CaseAl
Case A l.l
For case A l (VGO = Vmid), the value o f Rdc can have significant implications to the
assumption o f a square wave output waveform and the resulting harmonics at the output.
If the gate-source voltage (Vgs, as shown in Figure 3.35) is not driven past zero volts, no
clipping will occur to the gate-source voltage waveform. Thus no DC current is
generated through the diode, and the value o f Rdc is negligible. Figure 3.39 is a plot o f
the Vgs waveforms for case A TI (VGO = Vmid, Vg = 0.3V, Pin = -7dBm - as previously
shown in Table 3.1, page 83), using different values for the DC bias resistance Rdc.
Note that the “expected” waveform shown in the plot is that with the minimum
voltage given by Equation ( 3.18 ). As Figure 3.39 shows, the value o f Rdc does not
affect the waveform appearing at the gate in this case. However, once the magnitude of
the AC input voltage causes conduction in Dgs, the DC current component, Igsoc, is
generated. The resulting waveforms are affected by the choice o f the DC bias resistance
Rdc.
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125
O)
-
0.1
-
0.2
-0.3
-0.4
-0.5
—•
0
1
2
Rdc = 0.1
Rdc = 10
Rdc = 50
Rdc =100
Expected
4
3
time (sec)
5
6
x
10
'^°
Figure 3.39. Gate waveform s for various values o f Rdc: C a seA l.1
C :\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\ii Harm_Gen_via_Input_Cond\c Input Bias NetworkWVaveform
Plots\modelA_sim_vs_caic_2_5_03\modelA_caseAI_I_vgswf_plot_2_5_03.fig
Case A1.2
Figure 3.40 shows the ADS simulation o f the gate-source voltage waveforms for case
A l .2 (VGO = Vmid, Vg = 0.6 V, Pin = -1 dBm) where the input power is now increased
from -7 dBm to -1 dBm. Figure 3.40 shows that the waveforms generated across the gate
are different depending on the value o f Rdc. It is interesting to note that, as the value o f
Rdc is increased, the minimum voltage level o f the Vgs waveform is decreased. As a
result, the DC level becomes more negative as Rdc is increased. This trend makes sense
since there should be a larger voltage drop across a larger resistance Rdc. As the AC
input voltage level (Vg) is increased, the effects o f Rdc become even more significant as
shown next.
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126
-
0,2
if-
-
0.8
-1-—•
R dc = 0.1
R dc = 10
R dc = 5 0
R dc = 100
Expected
time (sec)
-10
xIO'
Figure 3.40. Gate waveform s for various values o f Rdc: C aseA l.2
C :\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\ii Harm_Gen_via_Input_Cond\c Input Bias NetworkWVaveform
PIots\modelA_sim_ys_calc_2_4_03\modelA_caseAI_2_vgswfj)lot_2_5_03.fig
Case A1.3
Figure 3.41 shows the gate-source waveforms for case A1.3 (VGO = Vmid, Vg =
1.2V, Pin = 5dBm).
-
0.2
-0 .4
-
0.6
>
03 -0 .8
D>
>
-1 .4
-
Rdc = 0.1
R d c = 10
Rdc = 50
R dc=100
Expected
1.6
tim e (sec)
-10
X 10'
Figure 3.41. Gate waveform s for various values o f Rdc: C aseA l.3
C :\R esearch\l_B _l Undrstndng NL Mech\B Stdy Idlzd Mdls\ii Harm_Gen_via_Input_Cond\c Input Bias NetworkWVavefonn
PIots\modeIA_sim_vs_calc_2_4_03\modelA_caseAI_3_vgswf_pIot_2_5_03.fig
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127
This case shows an effect similar to the previous case (case A 1.2), but the effects o f
changing Rdc are more severe. The waveform matches the theoretical, “expected”
calculation (as previously discussed in the introduction to this section and calculated
using the MATLAB routine shown in Section S.ii.a) when Rdc is equal to Rgen (50
ohms); this trend is observed in each case studied. Figure 3.42 shows the harmonic
content o f the waveforms for case A 1.3.
0.9
0.8
0.7
.'
•
Rdc = 0.1
A
Rdc =10
■
Rdc = 50
*
Rdc =100
0 6
<0
0.4
P>
i
0.2
Freq (GHz)
,9
xIO'
Figure 3.42. Gate Harmonics for various values o f Rdc: C aseA l.3
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\ii Harm_Gen_via_Input_Cond\c Input Bias NetworkWVaveform
Plots\modelA_sim_vs_calc_2_4_03\modelA_caseAI_3_vgsfs_plot_2_5_03.fig
This figure is a plot of the magnitude o f each harmonic in the input gate waveform as
Rdc is varied. As the figure shows, the smaller bias resistances tend to keep the DC gate
voltage levels closer to the .bias value input by VGO. When Rdc is allowed to vary, the
DC levels can very significantly. This is exhibited in the fact that for an Rdc o f 0.1
ohms, the magnitude o f the DC gate voltage level is 0.3 V compared to a level o f around
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128
0.6V when Rdc is increased to 100 ohms. Note that the DC bias level for the theoretical
waveform (i.e. the expected waveform shown in Figure 3.41) is equal to the DC level
when the resistance Rdc is 50 ohms.
In order to understand the implications on the overall conversion gain o f changing bias
resistance on the input, the corresponding outputs need to be observed. Figure 3.43
shows the output current waveform for caseAl.3 (VGO = Vmid, Vg = 1.2V, Pin = 5dBm)
above.
0.03
0.025
0.02
0.015
-— Rdc = 0.1
Rdc= 10
Rdc = 50
— - Rdc= 100
0.01
0.005
-0.005
time (sec)
xIO
-10
Figure 3.43. Drain Current waveforms for various values o f Rdc: C aseA l.3
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\ii Harm_Gen_via_Input_Cond\c Input Bias NetworkWVaveform
Plots\modelA_sim_vs_calc_2_4_03\modelA_caseAl_3_idswf_plot_2_5_03.fig
Figure 3.43 shows the implications o f the changing value o f Rdc. When Rdc is 50
ohms, the output waveform is symmetrically clipped and resembles a square wave as
explained in Section 3.ii.a. Flowever, as the value o f Rdc is decreased, the duty cycle o f
the clipped waveform is reduced. Similarly an increase in Rdc increases the duty cycle.
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129
This effect has a significant consequence for the resulting harmonic currents, shown in
Figure 3.44.
0.02
0.015
<
a>
ns
(/>
■a
•
Rdc = 0.1
▲
Rdc =10
■
Rdc = 50
*
Rdc =100
0.005
Freq (GHz)
,9
xIO'
Figure 3.44. Drain harm onics for various values o f Rdc: C aseA l.3
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\ii Harm_Gen_via_Input_Cond\c Input Bias NetworkWVaveform
Plots\modeIA_sim_vs_calc_2_4_03\modelA_caseAl_3_idsfs_plot_2_5_03.fig
As Figure 3.44 shows, changing the duty cycle o f the double-sided, clipped
waveforms o f Figure 3.43 causes the harmonic content o f the drain current to vary
significantly. As previously shown in Section 3.ii.a.5 (page 82), this case (case A1.3)
showed large third harmonic content and no second harmonic content. This result is
repeated in the response in Figure 3.44 when Rdc is equal to 50 ohms. However when
the value o f Rdc is dropped to 0.1 ohms, the second harmonic current rises up to around 5
mA and the third harmonic is reduced to about half o f its previous value (from 5 mA to
2.5 mA). Changing the bias resistance clearly has a significant effect on the output drain
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130
current. As a result, the output power response ean also be significantly different
depending on the value o f Rdc.
Figure 3.45 shows the output versus available power response (Pin) o f the model for
varying Rdc values for case A1 (VGO = Vmid). It also shows the theoretical response as
calculated using the methods described in Section 3.ii.a.2.
5
0
;
-5
0
'
-5
-1 0
E -10
m
S -15
£
ijji
1! / 1
n/ \
CM
@ -20
1
-35
0
Pin (dBm)
-40
10
-10
-20
lit '[ ----------Hi
i- 2 5
1
3
o
Ql -25
-30
^
a
----------:1
-----------
CL
- - - Rdc =0.1
Rdc= 10
Rdc = 50
...... Rdc = 100
• Theoretical
-30
a
1
r
f
■
«
-35
10
Pin (dBm)
-40
-10
0
Pin (dBm)
10
Figure 3.45. Power response for M odel A, Case A1 for varying values o f Rdc
C:\R esearch\l_B_l UndrstndngNL Mech\B Stdy Idlzd Mdls\ii Harm_Gen_via_Input_Cond\c Input Bias Network\PinPout
Comparisons\modelA_sim_2_5_03\ model A_caleA_pwr_plot_2_5_03. fig
The implications o f a changing Rdc value are shown here to be very significant. A
standard, idealized, “theoretical”, calculation such as shown in [3;5] corresponds to a
response where the DC bias resistance Rdc is equal to the generator resistance Rgen
(typically 50 ohms). Flowever a standard microwave configuration for a multiplier
circuit would consist o f a bias-T with very small resistance in the DC path. With this
bias, normally no second harmonic output is expected, however, a small value for this
resistance results in significant amounts o f second harmonic output power where none
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131
was expected, even for a very basic model (model A). Similarly, the third harmonic
output power may be significantly lower than expected. This effect is o f great
significance when designing a frequency multiplier using an idealized analysis. For
example, a frequency tripler designer wanting to create a square wave output current may
bias the device at the midway point (such as in this case, case A l, VGO = Vmid = -0.3V)
and overdrive the input waveform such as discussed in [4;5]. Observing Figure 3.45, an
input power o f 5 dBm would be expected theoretically to generate about -2 dBm of
output power at the third harmonic. When a realistic Rdc value is utilized however,
the third harmonic output power level is 8 dB lower (-10 dBm). Furthermore, when
Rdc is 0.1 ohms, about -2 dBm o f second harmonic output power exists when absolutely
none was expected. For this reason the choice o f bias resistance (Rdc) proves to be o f
vital consideration.
3 M .C . 2 J .
CaseBl
The effects o f varying Rdc were also simulated for the other gate bias levels
highlighted in this study. The output versus available power response for case B1 (VGO
= -0.6V) is shown in Figure 3.46.
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132
---Jff*. ■
1:
J1
'A
Ir
■U
UM
111 ;
U*- i-
1 1 1
a.
-20
-25 -
ill
10
30
10
-10
Pin (dBm)
Pin (dBm)
— Rdc = 0.1
Rdc= 10
— Rdc = 50
— Rdc= 100
• Theoretical
-30'
-10
10
Pin (dBm)
Figure 3.46. Power response for M odel A, Case B1 for varying values o f Rdc
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\ii Harm_Gen_via_Input_Cond\c Input Bias Network\PinPout
Comparisons\model A_sim_2_5_03\ modeIA_caseB_pwr_plot_2_5_03 .fig
Similar to the previous case, varying Rdc changes the gate voltage and drain current
waveforms and causes variation in the harmonic output power levels. For this case,
which is at a lower gate bias level, it takes a larger input power level to create clipping
in the gate voltage waveform. Thus the effects o f varying Rdc cannot be seen until an
input power level o f around 0 dBm.
3.ii.c.2.U. CaseCl
For the third case, where the gate is biased at the forward conduction voltage o f Dgs
(case C l, VGO = Vfwd = GY), an unintuitive response is found for a small value o f Rdc.
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133
WM«
-0.5
O)
Rdc = 0.1
Rdc = 10
Rdc = 50
Rdc= 100
Theoretical
time (sec)
xIO
-1 0
Figure 3.47. Gate waveform s for various values o f Rdc: C aseC l.3 (VGO=Vfwd, Pin=5dBm )
C :\R esearch\l_B_l UndrstndngNL Mech\B Stdy Idlzd Mdls\ii Harm_Gen_via_Input_Cond\c Input Bias NetworkWVaveform
Plots\modeIA_sim_vs_calc_2_4_03\modelA_caseCl_3_vgswf_plot_2_5_03.fig
Case C1.3
Figure 3.47 shows the gate voltage harmonics for varying Rdc values for case Cl .3
(VGO=Vfwd, Pin=5dBm, V g~l .2V). For an input power o f Pin = 5 dBm (Vg ~ 1. 2V)
the AC input signal should cause a significant voltage swing at the gate o f the transistor.
Flowever, the result for Rdc = 0.1 is somewhat troubling. The gate-source voltage shows
a very small swing, only reaching approximately -O.IV at minimum. This phenomenon
is due to the fact that, as previously discussed, when the value o f Rdc is small the DC
level o f the gate is forced to stay close to the bias level, which is around OV in this case.
With a larger value o f Rdc, the gate DC level can shift, allowing a more significant
voltage swing. This result should not be indicative o f a more realistic device model (such
as that previously presented in Section
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134
2.iii.b in Figure 2.14, page 40), which would contain significant resistances such as the
gate resistance (Rg) and source resistance (Rg), as well as parasitics at the gate (Cpg, Cpgi,
Lg), which would result in a less extreme response. Appendix B.i.c.2 (page 471) shows
the equivalent response o f Figure 3.47 utilizing the realistic PFIEMT model o f Chapter 2
(Figure 2.14, page 40). When using the realistic model (Figure 2.14), the bias must be
adjusted to account for the fact that the realistic forward conduction voltage value is not
0
but around 0.8V. Furthermore, when simulating the realistic model (Figure 2.14) a more
realistic minimum gate bias resistance is used (Rdc = 1 ohm). However, the results
shown in the Appendix give a fair comparison o f the significant difference between a
realistic and idealized gate voltage response for case C l. In the realistic model, a voltage
drop above the forward conduction voltage occurs due to the presence o f parasitics such
as the gate-drain capacitance which are in parallel with the gate-source diode. Also, the
IV characteristic o f the gate-source diode is a much more realistic one, which causes its
effect to be more gradual. As a result the realistic gate-source voltage waveforms shown
in the appendix show much less o f an extreme change than that shown in the idealized
model. However, the shifting o f the minimum gate-source voltage level with an
increasing Rdc value is a common trend for both the idealized and realistic model.
The output versus input power result for this case (case C l, VGO=Vfwd=OV) is shown
in Figure 3.48. As indicated by the waveforms o f Figure 3.47, the response for Rdc = 0.1
ohms is very different than for the other values. As shown in Figure 3.48 the theoretical
2fo output power reaches a maximum o f around -2 dBm for an input power o f 0 dBm.
Changing the Rdc value to 0.1 ohms reduces this second harmonic output power to less
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135
than -15 dBm. In terms o f a theoretical multiplier design, the choice o f the bias
resistance Rdc is clearly o f vital importance at this bias (case C l, VGO= Vfwd).
-1 0
-10
-15
73
?0 -20
-20
g -2 5
Q- -25
-10
-30 ■-
-30
-15
-20
-10
-35
-35
-40
-10
-40
-10
Pin (dBm)
Pin (dBm)
— Rdc = 0.1
Rdc= 10
— Rdc = 50
— Rdc= 100
• Theoretical
Pin (dBm)
Figure 3.48. Power response for M odel A, Case C l for varying values o f Rdc
C :\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\ii Harm_Gen_via_Input_Cond\c Input Bias Network\PinPout
Comparisons\modelA_sim_2_5_03\ modelA_caseC_pwr_plot_2_5_03.fig
3.ii.c.3. Compensation Technique
Although it is apparent from the above analysis that the expected waveforms are
obtained when Rdc is equal to 50 ohms, the phenomenon brings up some problems. A 50
ohm resistance can easily be inserted into the gate bias path, but the implications o f doing
such need to be considered. Figure 3.49 shows the values o f the DC voltage levels at the
gate with varying input power for case A l (VGO=Vmid). Note that for this study the
minimum Rdc value used was a 1 ohm (instead o f 0.1 ohms) which represented a
practical value (representing the internal impedance of the bias-T).
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136
- 0 .2
-0 .3
-0 .4
^
Compensation
Needed
When
Rdc=1 ohm
-0 .5
-
0.6
O)
-0 .7
-
0.8
R dc= 1
R d c = 10
Rdc = 50
R dc=100
-0 .9
-10
Pin (dBm)
Figure 3.49. Shift in the DC Bias Level vs. Input Power for M odel A, Case A l
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd MdlsMi Harm_Gen_via_Input_Cond\c Input Bias
Network\modelA_rdcswp_2_14_03\ modelA_CaseA_vgsDC_rdcswp_5_15_03.fig
The figure shows that for small DC path resistance (Rdc), the DC gate voltage level is
insensitive to the AC input level. As Rdc is increased, the DC voltage drops with
increasing AC input. In effect, the DC operating point o f the device is changing by a
significant amount. For a 10 dBm input power, the “expected” result occurring when
Rdc is 50 ohms shows a shift in bias from -0.3V to around -0.8V. One method to recover
the “expected” result, while keeping Rdc close to its practical value o f around 1 ohm, is
to shift the gate bias for each value o f Pin according to the amount o f shift that would
occur for Rdc equal to 50 ohms. Figure 3.50 shows a comparison o f Pin vs. Pout o f the
realistic model for Rdc equal to 50 ohms compared to Rdc equal to 1 ohm, where the bias
level has been adjusted exactly corresponding to the shift o f Rdc equal to 50 ohms. This
bias level is adjusted for each Pin to give the proper offset to reset the DC value (given
when Rdc is equal to 50). For example, at 0 dBm the bias was adjusted from -0.3V to
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137
-0.37V, and at Pin equal to +lGdBm, the bias was adjusted from -0.32V to -0.8V. The
results correspond well.
>
—
O
■
^
2
0
Pin (dBm)
fo, Rdc=50
2fo, Rdc=50 ( < -30dBm)
3fo, Rdc=50
fo, Rdc=1 w/bias adjustment
2fo, Rdc=1 w/adj (< -30dBm)
3fo, Rdc=1 w/adj
2
10
Figure 3.50. Pout vs. Pin response o f M odel A for Rdc = 50 ohms, and Rdc = 1 ohm W ith Bias
Adjustm ent
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\ii Harm_Gen_via_Input_Cond\c Input Bias
Network\modelA_rdcswp_2_I4_03\ modeIA_CaseA_vgsDC_compensation_plot_5_15_03.fig
The results o f Figure 3.50 imply that, rather than using the Rdc value o f 50 ohms to
get the expected response, Rdc can simply be left at 1 ohm and the gate bias voltage can
be adjusted accordingly. Thus an “ideal” multiplier design which assumes an “expected”
result (which is shown at Rdc = 50 ohms) will require significant adjustments in the gate
bias voltage level for the practical case o f a small Rdc. The amount o f adjustment will
depend on the input power level and the actual Rdc value, and is exhibited in Figure 3.49.
For example, at an input power level o f 5 dBm (case A1.3) the gate bias is adjusted from
around -0.3V to -0.5V. When this compensation technique is used, the output current
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138
waveform (for Rdc = 1 ohm) is brought in line with the expected output waveform,
shown in Figure 3.43 when Rdc = 50 ohms. This is shown in Figure 3.51, which shows a
comparison of the output current waveforms for case A1.3 (VG0=Vmid=-0.3V,
Pin=5dBm), when Rdc is 50 ohms, compared to the compensated case where Rdc is set
to 1 ohm and the gate bias voltage is adjusted to -0.5 V.
0 .0 3
0 . 02 :
0.02
<
0 .0 1 5
0.01
—
O
Rdc=50
Rdc=1 w/bias adjustment
0 .0 0 5
Tim e ( s e c )
xIO
-10
Figure 3.51. Output Current W aveforms Showing Effects o f Bias C om pensation, Case A1.3
(VGO=Vmid, Pin=5dBm )
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\ii Harm_Gen_via_Input_Cond\c Input Bias
Network\model A_rdcswp_2_l 4_03\ model A_CaseA_vgsDC_compensation_wfplot_6_26_03 .fig
3.ii.c.4. Study Utilizing Realistic Model and Measured Data
Perusal o f available literature reveals little published information on the subject o f the
effects described above. Richardson conducts several studies on the effects o f radio
frequency interference (RFI) on both bipolar [54;55] and FET [56] transistors. These
studies investigate the effect o f various resistances in the DC bias path. Similarly, Fermi
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139
et al [57] present a study on BJT behavior under RF excitation for various bias networks
with different base bias resistors and input power levels.
Due to the relative lack o f available information and the significant impact o f the
effect as illustrated by the idealized model, a more in-depth study of variation in the
DC bias resistance was conducted utilizing several more realistic device models, as
well as measurements on the actual device. These results are presented in Appendices
B.i.c.2, B.i.c.3, and B.i.c.4 (on pages 471, 472 and 476 respectively). They show a
similar trend as observed in the idealized model, with significant differences in the output
power level as the value o f Rdc is changed. The more realistic results, however, show a
less drastic effect than in the idealized model due to the presence o f parasitic elements, as
previously discussed.
3.ii.c.5. Summary of Input Bias Network Study
In summary, the effects o f varying the value o f Rdc have been investigated. It has
been discovered that a typical “idealized” multiplier design which contains gate clipping
due to Dgs actually assumes that the generator resistance Rgen is equal to the DC bias
resistance Rdc (typically 50 ohms). However, in a typical multiplier circuit setup, where
Rdc has a small value, a significantly different response can occur. The variation in
response due to the Rdc value has been investigated using the idealized device model
(model A). A method of recovering the expected waveforms corresponding to a value o f
Rdc equal to 50 ohms was presented. The method shows that the expected results can
be recovered simply by leaving the Rdc value small and making adjustments in the
gate voltage level. Thus any multiplier design which utilizes significant amounts o f Dgs
clipping was shown to require significant gate bias adjustment to approach the amount o f
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140
“expected” output power. To verify the effects described above, a more realistic device
model and an actual device have also been characterized.
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141
5.11.d. N*fo Harmonic Input Refiection
5.11.d.l. Basic Considerations
Sections 3.ii.b and 3.ii.c provided an in-depth analysis o f the response o f the input
network M l at the fundamental frequency and at DC respectively. The final
consideration for the input network is its response at the higher order harmonics o f the
fundamental (n*fo). It has been shown [23;35;47;58] that a network which reflects
second (and higher order) harmonic power at the input o f a transistor can be used to
increase the overall conversion gain in a frequency multiplier. In order to eharacterize
the effects o f a n*fo “reflector” network, the circuit o f Figure 3.52 was utilized.
M1
M2
Ids
nfo
Rflctr
ZO - Rgen
Vds
I Vgs
:VGO
Figure 3.52. Block Diagram o f n*fo Input Reflector Network Study
C:\Research\Figures\jj m lm 2 nfo_ref_d BD.ai
The use o f the input network M l, shown above, is the focus o f this section. In this
instance, MI includes a “reflector” element which reflects power at a given harmonic of
the fundamental frequency (n*fo). A section of 50 ohm transmission line with length
Linnfo is inserted in-between the gate o f the transistor and the n*fo reflector. Note that
for this study a DC path resistance (Rdc) of 50 ohms was used to obtain the expected
bias level as discussed in Section 3.ii.c.3, in practical cases this resistance can be
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142
decreased to a realistic value and the bias compensation technique previously discussed
on page 135 can be utilized.
The process by which the input network is used to generate harmonic output is shown
in Figure 3.53, which shows a subsection o f the circuit in Figure 3.52.
fo input
G ate
nfo
gen
nfo
Rflctr
Source
Figure 3.53. The use o f an Input n*fo Reflector
C:\Research\Figures\jj m l m2 nfo ref d BDzoomed.ai
As previously described in Section 3.ii.a (and shown in Figure 3.13 and Figure 3.18)
the action o f the diode Dgs creates higher order (n*fo) harmonic power at the gate,
traveling from the gate towards the AC input signal generator. Additionally, in a more
complex representation o f the transistor, extra amounts o f n*fo gate power may appear
due to feedback effects from the drain, as will be discussed below in Section 3.iii.a (page
178) and Section 3.iii.c (page 224). In a general sense, the harmonic power levels at the
gate can be characterized in terms o f incident and reflected power waves. The
characterization is based on the principles o f small-signal, linear S-Parameter analysis,
which relates an incident power signal “a” and a reflected power signal “b” to the voltage
appearing across the terminals o f the device, the current into the device, and the generator
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143
resistance. As shown in the work o f Sipila et al [59], these definitions can be expanded
to account for large-signal, non-sinusoidal signals resulting from nonlinear effects
appearing at the gate. The incident and reflected signals denoted “ak” and “bk” as shown
in Figure 3.53 are defined for each harmonic, k, by [59]:
V -R
k
T
^ /XTT—
( 3 .2 8 )
Where Vk and Ik are the peak values o f the gate-source harmonic voltage and current,
respectively, k represents the chosen harmonic and Rgen is the generator resistance. The
time-domain gate-source voltage and current are given by Equations ( 3.29 ) and ( 3.30 )
respectively.
j{kmj+^V^)
( 3 .2 9 )
’ k\'^
k=-co
J{ka,j+Zh)
A= - 0 0
^k\'^
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( 3 .3 0 )
144
Where Vo is the DC level o f the gate-source voltage and lo is the DC level o f the gate
source current. Considering the response o f the circuit o f Figure 3.53 before the n*fo
reflector is used, the gate reflected power at a desired harmonic can be calculated by:
Pref
- R e i b *b*] ~
Pret„^„-Ke|/j„
4
^ Rger,\h\
g
g en
Where the desired harmonic “n” is plugged in for the harmonic number “k”. A
derivation o f Equation (3.31 ) as well as an ADS verification of the equation is given
in Appendix B.i.d.l (page 478). Equations ( 3.27 ) - ( 3.31 ) provide an important
relationship between the power signals and voltage/current signals appearing at the gate.
If the voltage and current waveforms appearing at the gate are known, their harmonic
components can easily be determined via a Fourier Series analysis. Then, Equation (
3.31 ) can be employed to determine the reflected power level at each harmonic. For
example when the idealized device is biased at forward conduction (Case C l), the gatesource voltage waveform is a half-wave rectified sinusoid as shown in Figure 3.19 on
page 95 (note that the gate-source current waveform, is also a half-wave rectified
sinusoid and is shown in Appendix B.i.d.2 in Figure B.12, page 481). The resultant
harmonic voltage and current signals at the gate contain large second harmonic content,
while having no third harmonic content. As a result significant 2fo reflected power exists
while no 3fo reflected power is seen, as previously shown in Figure 3.23 on page 98.
To utilize the n*fo reflected harmonic power to obtain more drain output, it is then re­
reflected back into the transistor using the n*fo reflector element as shown in Figure 3.53.
The length o f transmission line Linnfo is inserted in-between the nfo reflector element and
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145
the gate, and this length is varied to vary the phase o f the re-reflected n*fo signal. The
combination o f the transmission line and the reflector element allow the extra nfo
harmonic power to be input back into the transistor with a variable phase. On the output
this results in one or both o f the following situations:
1. Additional n*fo output power is seen at the output from the effects o f the re­
reflected n*fo input signal. This additional output power is maximized by varying Linnfo
such that the extra n*fo output power is in phase (constructively interfering) with the
output power already present at n*fo.
2. Additional output power is seen at a different harmonic (m*fo) due to nonlinear
mixing o f the re-reflected signal (n*fo) and another harmonic. For example, if a 2fo
reflector element is utilized on the input, it can cause extra 2 fo power to mix with the
fundamental frequency fo to create additional third harmonic (3fo) output power. This
can also be maximized by varying Linnfo for optimum phase.
This use o f input reflector networks is very significant in frequency multiplier design
and has been shown to greatly enhance multiplier conversion gain and output power. The
following study will show that the input reflector can cause up to a 4.8 dB increase* in a
multiplier’s conversion gain. By utilizing the “idealized” model (model A), the basic
effects o f using 2fo and 3fo reflector networks on a transistor’s input are studied in the
next three sections as follows. In Section 3.ii.d.2, the n*fo reflectors are realized using a
simple, high-Q LC circuit. Section 3.ii.d.3 presents the results o f using a 2fo reflector on
the input to manipulate and maximize both the 2fo and 3fo output conversion gain.
T his is the b est increase w h ere a practical am ount o f C G is obtained, larger in creases are sh o w n but th e se
are irrelevant b eca u se th ey h ave a very lo w output p ow er level.
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146
Section 3.ii.d.4 repeats the procedure o f Section 3.ii.d.3, except it utilizes a 3fo input
reflector.
3.ii.d.2. Development of Idealized, Narrow Band, Second and Third
Harmonic Reflector
In order to study the effects o f 2fo and 3fo reflection at the input, a very high-Q
reflector element is necessary. This allows the network to reflect only the desired
harmonic (by looking like a short circuit at the subject harmonic frequency, rMi|^j.g=l),
while leaving all higher and lower order harmonics unchanged (by looking like an open
circuit). This network can be achieved with a basic series LC circuit connected to
ground. The LC values used for the second and third harmonic reflector networks were
constructed for High-Q, and are ideal. The deviation in the response due to the Q o f the
reflector network must be considered for a non-idealistic multiplier design.
0
-
0.1
-
0.2
r
2 fo R e flector
3 fo R e flecto r
-0 .3
S ' -0 .4
^
-0 .5
CN
CO - 0.6
-0 .7
-
0.8
-0 .9
-1
10
11
Freq (GHz)
12
xIO®
Figure 3.54. S21 Response o f Separate 2fo and 3fo LC Reflectors Overlaid on the Sam e Plot
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd MdlsMi Harm_Gen_via_Input_Cond\d Harmonic Reflection\Harmonic
Reflector Sweep 6_30_03\rflctr_ntwk_6and9GHz_pIot_6_30_03.fig
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147
Figure 3.54 shows the |S21| response o f the second and third harmonic reflectors. The
figure exhibits the very large Q o f the networks.
3.ii.d.3. Study of 2fo Input Reflection Using Idealized Mode!
Several studies [23;47;58] show that variation in length o f a 2fo reflector element can
cause large variation in the conversion gain o f a frequency multiplier. As described in
section 3.ii.d.l above, a 2fo harmonic reflector network is to be utilized on the input o f
the idealized model (model A). A section o f transmission line is inserted between the
gate o f the transistor and the 2fo harmonic reflector as represented in Figure 3.53 (when
n=2 in the figure). The length o f transmission line (Lin2 fo) is varied to vary the phase o f
the reflected 2 fo harmonic signal, and the corresponding harmonic output power at the
drain. In order to fully characterize the effects o f the 2 fo input reflector network a
simultaneous sweep* o f the input power level and reflector phase offset (Lin2 fo) was
conducted for the three cases A l, B l, and Cl (as previously described on page 83). The
resulting input power levels and reflector offset lengths which gave maximum 2 fo
conversion gain were obtained. In addition, the input power levels and reflector lengths
giving maximum 3fo conversion gain were also found.
In addition to characterizing the effects o f the 2 fo reflector on the output, the
relationship between the effects o f the 2 fo reflector and the initial 2 fo gate reflected
power is also explored. Several studies in the UC Davis microwave laboratory
[11;35;47;58] have explored the impacts of using 2fo (and 3fo) input reflector networks
with varied phase (varied Linnfo length). Other authors [14;60] have presented results o f
T he id ea o f a sim u ltan eou s sw e e p w a s describ ed in detail on p age 101. In th is ca se P in and L in 2fo are
sw ep t su ch that all com b in ation s o f the tw o variab les are tested.
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148
variation in the input impedance, an equivalent to varying the reflector networks.
However, although frequently used to enhance the output power o f frequency multipliers,
the relationship between the amount o f 2fo (and 3fo) power which is reflected at the gate
o f the transistor and the resulting impact o f the input reflectors on the output conversion
gain is not typically considered. If a large amount o f 2fo power is reflected at the gate,
then the effects o f a 2fo reflector may be very significant. Likewise, if there is no 2fo
reflected power present the use o f an input reflector may be quite futile. Although
several authors utilize input reflector networks, in perusal o f published literature, a study
o f the relationship between this reflected power at the gate and the resulting improvement
in output conversion gain due to the use o f a reflector network has never been found.
The characterizations described above were conducted via ADS simulation o f the
idealized model (model A), for each case (case A l, B l and C l) and are presented below.
An ADS schematic o f the circuit simulation is shown in Appendix B.i.d.3 (page 482).
Case A l (Bias VGO = Vmid = Vp/2)
The first case studied in this analysis was case A l (as previously shown in Table 3.1
on page 83). As previously discussed in Section 3.ii.a.5, this case generates a significant
amount o f third harmonic output power for large input signals and generates no second
harmonic content. Although it does not generate second harmonic on the output, the
idealized model does generate a significant amount o f reflected second harmonic power.
This reflected power was previously shown in Figure 3.13 on page
8 8
. Perusal o f Figure
3.13 shows that even in a highly idealized FET model, very significant amounts o f
reflected power exist. This figure shows that a maximum o f +2 dBm o f 2fo power is
created at the input for a 10 dBm input power. Similarly, a maximum o f -ISdBm o f 3fo
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149
power is created for 5dBm o f input power. This 2fo and 3fo reflected power is caused by
the clipping at the gate due to the gate-source diode (Dgs). This effect can be seen in
Figure 3.13, where only fundamental power is reflected until the input power level
reaches - 6 dBm, the point where Dgs turns on. It follows that the use o f a 2fo reflector
will only be significant for input power levels greater than - 6 dBm for case A l
(VGO=Vmid). In this idealized analysis, all o f the 2fo reflected power is reflected back
towards the gate with the 2fo reflector network. By simultaneously sweeping* the input
power level and 2 fo input reflector length Lin2 fo, the effects o f the 2 fo input reflector
were fully characterized.
CM
-15
•
*. '■
I w!
-25
-3 0 .
Tt
10
20
30
Pin = -5dBm
Pin = OdBm
Pln = 5dBm
P ln = lO dBm
w IM o h m , Pin—5dBm
40
-i_
50
\iV
60
70
80
90
Linjfo (deg)
Figure 3 .5 5 .2fo Conversion Gain vs.
2fo Reflector Phase Length:
M odel A, Case A l.
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\ii Harm_Gen_via_Input_Cond\d Harmonic
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_03.fig
S e e d escrip tion o f a sim u ltan eou s sw ee p o n page 101
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150
Figure 3.55 shows the second harmonic conversion gain versus 2fo reflector phase
length for case A l (VGO = -0.3V) at several different input power levels. Note that the
solid trace on the figure (for the Pin=-5dBm curve) shows a re-simulation o f the circuit
using a 10 mega ohm resistor in parallel with the 2fo reflector network. This was
necessary for simulator convergence when the reflector network created a large
impedance value at the gate o f the transistor and is discussed in more detail on page 160.
As Figure 3.55 shows, the 2fo reflector has a profound effect on the second harmonic
conversion gain for case A l. This is exhibited in the figure at an input power o f -5 dBm,
where the second harmonic conversion gain ranges from -20 dB (at Lin2 fo = 0 degrees) to
-3 dB (at Linafo = 45 degrees). The impact o f the reflector is made even more significant
considering that this case shows very little 2fo output power when no reflector is used
(as previously shown in Section 3.ii.a.5 in Figure 3.11, page
8 6
). A qualitative
demonstration o f the improvement in 2fo conversion gain will be shown later in Figure
3.57.
The 2fo input reflector length giving the maximum 2fo output conversion gain (Lin2 fo
= 45 degrees*) was obtained through this characterization. Additionally, the length
giving the maximum 3fo output conversion gain (Lin2 fo = 0 degrees^) was characterized.
The third harmonic conversion gain versus 2fo input reflector length response is shown in
Figure 3.56. Note again the solid trace representing areas o f re-simulation using a 10
mega ohm parallel resistor for convergence. Figure 3.56 shows that the 2fo reflector has
less o f an impact on the third harmonic conversion gain, although it still shows some
variation with the reflector length.
A d isc u ssio n o f the v a lu e s o f th e optim um reflector len gths fo llo w s b elo w .
^ A d isc u ssio n o f the v a lu e s o f the optim um reflector len gths fo llo w s b elo w .
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151
Using the lengths for optimum 2fo conversion gain (denoted Refl. Opt 2fo in Figure
3.57, to be shown) and 3fo conversion gain (denoted Refl. Opt 3fo in Figure 3.57, to be
shown on page 152) an input power versus conversion gain profile was plotted and
compared to the response when no reflector was used. This comparison is shown in
Figure 3.57.
•
CO
Pin = -5dBm
Pin = OdBm
Pin = 5dBm
Pin = lO dBm
wlO M ohm , Pin=-5dBm
-10
-14
-16
-18
-20
Figure 3 .5 6 .3fo Conversion Gain vs. 2fo Reflector Phase Length: M odel A, Case A l
C:\R esearch\l_B _I Undrstndng NL M ech\B Stdy Idlzd Mdls\ii Harm_Gen_via_Input_Cond\d Harmonic
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Figure 3.57 shows that, as expected, the 2fo harmonic reflector has no effect for input
power less than - 6 dBm. However, for larger input power levels, the reflector makes a
huge impact. For the design which has been optimized for 2fo conversion gain (Refl.
Opt. 2fo in Figure 3.57), a maximum o f around - 2 dB is obtained for a model which
contains no 2fo output power without the use o f a reflector network. Thus the reflector
network exhibits a very significant improvement in the generation o f 2 fo output.
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152
Additionally, this same 2fo reflector, with Lin2 fo chosen to give optimum 2fo CG, has
significantly less (about 4dB on average) third harmonic output.
0
-2
;
;
1
1
:
1
'
T / 'V
-4 ------ f
—
A1 \ 41
No Refl.
Refl. Opt 2fo
Refl. Opt 3fo
■
-6
1
-8
—
^ -10
0 -1 2
O
-14
1
\
1
___ 1
____ &___
.•r
1\
......X X '1 ;/ '1
'' \ X\ '
------- 1
—
h -/---1
1
-10
-5
0
5
Pin (dBm)
10
-20
-10
-8
M- 1 0
0-12
O
-14
-16
-16
-18
S
-18
No|Refl.|i
! < -20 dB'T
-5
0
5
Fin (dBm)
10
0
-5
0
5
10
Pin (dBm)
Figure 3.57. Pin vs. Conversion Gain for M odel A, Case A l - Comparison o f Response with: No Input
Reflector (solid); 2fo Reflector Optimized for 2fo Output (dashed); 2fo Reflector O ptim ized for 3fo
Output (dotted)
C:\M y D ocum ents\R esearch\l_B _l Understanding NL Mech\B Study o f Idealized Models\ii Harm_Gen_via_Input_Cond\d Harmonic Reflection\model
A PinPout w_2fo refl 2_10_03\modelA_CaseA CG_comp_plot_2_10_03.flg
The figure also shows the response for a design where the 2fo reflector has been used
in an attempt to optimize the third harmonic conversion gain (Refl. Opt. 3fo in Figure
3.57). However, the figure shows that the 3fo output conversion gain is lower for the
design with the 2fo reflector than for the design which uses no reflector at all. Although
nonlinear mixing between the re-reflected second harmonic and other harmonics
(primarily the fundamental) has the possibility o f causing increased third harmonic levels,
as discussed in Section 3.ii.d.l, no improvement in the third harmonic conversion gain is
shown in this case.
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153
Case B l (Bias VGO = Vp)
The use o f a 2fo input reflector was also studied for case B l (VGO = -0.6V). Figure
3.18, previously shown in Section 3.ii.a.5, shows that for this case reflected power at the
higher order harmonics (2fo and 3fo) also exists at the gate. It takes a larger input power
to create reflected (2fo and 3fo) harmonics at this lower bias level. As a result, the 2fo
input reflector only causes variation in the output conversion gain for larger input power
levels (greater than 0 dBm). This trend is exhibited on the second harmonic conversion
gain versus reflector length (Lin2 fo) response for case B l, shown in Figure 3.58.
P'in=iO 5dBm
-1 0
-20
-25
Pih=-10dBm
Pin =
Pin =
Pln =
Pin =
P in =
-10d B m
-5dBm
OdBm
5dBm
lO dBm
-30
Figure 3 .5 8 .2fo Conversion Gain vs. 2fo Reflector Phase Length: M odel A, C ase B l
C:\R esearch\l_B_l Undrstndng NL MechVB Stdy Idlzd Mdls\ii Harm_Gen_via_Input_Cond\d Harmonic
Reflection\Rflctr_Ntwk_Swps_8_6_03\modelA_fixed_9_12_03\Opt2fo_Refl_ModelA_CaseB_Rdc_50_CG2foplot_9_12_03.fig
The figure shows that the reflector length Lin2 fo has little effect for lower input power
levels. Large variation is shown for the larger input power levels (Pin = 5, 10 dBm),
however, this variation occurs in regions o f significantly lower conversion gain. The
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154
maximum conversion gain (which occurs between Pin = -10 to -1 dBm, as will be shown
in Figure 3.59), is constant with the input reflector length and the optimum value is
therefore set arbitrarily to 90 degrees.
As conducted for case A l, the third harmonic conversion gain versus 2fo input
reflector length was also tested, it is shown in Appendix B.i.d.4 (page 483). The input
reflector length for maximum third harmonic conversion gain was 45 degrees (Lin2 fo = 45
degrees).
Utilizing the optimum 2fo input reflector lengths giving the maximum 2fo and 3fo
conversion gain, the conversion gain versus input power response was plotted for case
B l, and is shown in Figure 3.59.
7
—
—
6
5
No Refl.
Refl, O pt 2fo
Refl. O pt 3fo
4
3
^
2
(D
1
-10
m -10
0
-14
1
-16
-16
-2
-18
-18
-^ 1 0
0
Pin (dBm)
10
-20
■-10
10
Pin (dBm)
-20
Pin (dBm)
Figure 3.59. Pin vs. Conversion Gain for Mode! A, Case B l - Comparison o f Response with: No Input
R eflector (solid); 2fo Reflector Optimized for 2fo Output (dashed) 2fo R eflector O ptim ized for 3fo
Output (dotted)
C:\My D ocum ents\Research\l_B_l Understanding NL Mech\B Study of Idealized Models\ii Harm_Gen_via_lnput_Cond\d Harmonic
Reflection\model A PinPout w_2fo refl 2_10_03\modelA_CaseA_CG_comp_plot_2_10_03.fig
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155
Figure 3.59 shows the simulated best conversion gain response when the second
harmonic input reflector is used to maximize, through optimization o f the input reflector
length Linifo, the second harmonic conversion gain and the third harmonic conversion
gain. This is compared to the response when no input reflector is used. Figure 3.59
shows that the second harmonic reflector does not improve the maximum 2 fo conversion
gain for case B1 (VGO=Vp). Although the 2fo CG is larger with the reflector in place for
input power levels from +1 to +10 dBm, the overall maximum 2fo CG (occurring for
Pin=-10 to -1 dBm) shows no improvement due to the reflector. This is somewhat to be
expected since, with no reflector present, the maximum second harmonic conversion gain
occurs for an input power range from -10 to -1 dBm. The second harmonic reflected
power, shown in Figure 3.18, does not begin to rise until an input power o f around 0 dBm
(when the gate-source diode begins to conduct). Thus at the point o f maximum second
harmonic conversion gain where no reflector is used, no 2 fo reflected power exists to
provide improvement through use o f the 2fo input reflector. However, for an input power
level greater than 0 dBm, it does allow a significant amount of 3fo power to be generated
as compared to the case where no reflector is used. Note again that the effects o f the
network cannot be seen until an input power level is reached that generates reflected 2 fo
power at the gate.
Case Cl (Bias VGO = Vfwd = OV)
Finally the use o f a 2fo input reflector was studied for case Cl (VGO=Vfwd =-0.01 V).
Figure 3.23, previously shown in Section 3.ii.a.5, shows why Case Cl may be the most
interesting. Since this case is at a bias level which is equal to the tum-on voltage o f the
gate-source diode (Vfwd), very large amounts o f higher-harmonic, reflected power exists.
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156
This large amount o f reflected power is exhibited by the significantly clipped gate-source
waveform previously shown in Figure 3.19(b). As a result o f this clipping, larger gatesource voltage levels exist at the higher order harmonics. In this case, larger second
harmonic levels exist. These higher harmonic levels cause a significant increase in the
reflected power level, as related by Equation ( 3.31 ). Specifically, the reflected 2fo
power here is significantly larger than for cases A1 and B 1. This suggests that the effects
o f the 2fo input reflector are going to be more significant. Observing the response o f the
second harmonic conversion gain versus the input reflector length, shown in Figure 3.60,
the second harmonic conversion gain can vary from around 4 dB (at Lin2 fo= 4 5 degrees)
down to much less than -30 dB (at Lin2 fo= 0 degrees) for an input power o f -10 dBm.
CD
-10
CM
-1 5
CD
O
-20
-2 5
Pin
Pin
Pin
Pin
Pin
= -10dBm
= -5dBm
= OdBm
= 5dBm
= lOdBm
-30.
Lin2 fo (d e g )
Figure 3 .6 0 .2fo Conversion Gain vs. 2fo Reflector Phase Length: M odel A, Case C l
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\ii Harm_Gen_via_Input_Cond\d Harmonic
Reflection\Rflctr_Ntwk_Swps_8_6_03\modelA_fixed_9_12_03\Opt2fo_Refl_ModelA_CaseC_Rdc_50_CG2foplot_9_12_03.fig
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
157
The third harmonic conversion gain also exhibits large variation with changes in
Lin2 fo. The response, shown in Appendix B.i.d.4 (page 483), gives a maximum 3fo
conversion gain occurring at a length Lin2 fo o f 0 degrees. The conversion gain versus
input power responses utilizing the maximum 2 fo reflector lengths for case C l are shown
in Figure 3.61. Figure 3.61 repeats the input power versus conversion gain response o f
Figure 3.57 and Figure 3.59 for case C l. Figure 3.61 shows the effects o f the 2fo
reflector to be very significant for this case. As the figure shows, the optimum obtainable
2fo and 3fo conversion gains improve by around 5dB. This significant improvement is
due to the large amount o f 2 fo gate reflected power available for re-reflection for this
case (case C l). As previously discussed the improvement in the second harmonic
conversion gain is attributed directly to the effects o f re-reflected second harmonic signal
at the input. The fact that re-reflecting 2fo power back into the transistor can create extra
3fo harmonic power suggests that a significant amount o f nonlinear mixing between fo
and 2fo is taking place. Since this mixing cannot be happening at the output, or due to
feedback, it must be due to nonlinear mixing at the input diode Dgs. Note also that the
reflector for optimum 2fo CG also significantly increases the CG (gain) at the
fundamental frequency. This also must be attributed to nonlinear mixing within the Dgs
diode.
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158
10
------------1
8
6
— ■ NoRefl.
- — Refl. Opt 2fo
Refl. Opt 3fo
\
\\
ca
;o,
£CM -5.
' v
%
\
V
\
V
2
- - - -
--------■
\ \
o
\ \
0
O
O
,'
\
V
1■
'
x
l
\\
' ' '\
■10
\
^
\ \
l\
\\
\
-2
-1 0
i
\
-------------- -------------- ----------------------------------
'V.
4
>2
@
---------------1----------------»--------------- f---------------
A
S'
B
10
------------
-5
0
5
Pin (dBm)
10
-15
-1 0
-5
1
t
0
5
Pin (dBm)
10
-5
0
5
Pin (dBm)
Figure 3.61. Pin vs. Conversion Gain for M odel A , Case C l - Comparison o f Response with: No Input
Reflector (solid); 2fo Reflector Optimized for 2fo Output (dashed) 2fo R eflector O ptim ized for 3fo
Output (dotted)
C:\My D ocum ents\Research\l_B_l Understanding NL Mech\B Study o f Idealized Models\ii Harm_Gen_via_Input_Cond\d Harmonic
Reflection\model A PinPout w_2fo refl 2_10_03\modelA_CaseC_CG_comp_plot_2_10_03.fig
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
159
Table 3.4. Sum mary o f Idealized Designs USING 2fo INPUT REFLEC TO R
Optimum 2fo Conversion Gain Results:
C a se A1
(VG O =Vm id)
M ax C G 2fo (no Refl)*
C a se B1
(VGO=Vp)
C a se C l
(V G 0= V fw d)
-CO
-1.1
Not
A p p lica b le
-2.2
-1
-1
-1.1
3.7
P ava il @ M ax C G (O pt)**
-2
-1
-10
Im provem ent (dB)
Lin,^^ (D e g W R T fo )
CO
0
4.8
45
90
45
P a va il @ M ax C G (no R efl)t
M ax C G 2fo (Opt)*
-1.1
Optimum 3fo Conversion Gain Results:
M ax C G 3fo (no Refl)*
-5
-10.9
-1 0 .9
P ava il @ M ax C G (no R efl)t
0
6
6
-5.2
-6
-5.5
-1
3
-10
-0.2
4.9
5.4
0
45
0
M ax C G 3fo (O pt)*
P ava il @ M ax C G (Opt)**
Im provem ent (dB)
Lin^^^ ( D e g W R T fo )
* C G M a x i m i z e d W ith R e s p e c t to Pavail
t C o r r e s p o n d i n g Pavail V a l u e
t C G M a x i m i z e d W ith R e s p e c t to b o th Pavail a n d Lin2fo
** C o r r e s p o n d i n g Pavail V a lu e
C :\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\ii Harm_Gen_via_Input_Cond\d Harmonic Reflection\modelA PinPout
w_2fo refl 2_10_03\comparison_table_2_10_03.sxc
Table 3.4 shows a summary o f the results o f using the 2fo reflector on the transistor’s
input. The table compares the optimum conversion gain response o f the model at the
second and third harmonic with and without the use o f the 2fo reflector. It is interesting
to note that in the designs that show improvement (Cases A1 and C l for 2fo output and
Cases B1 and C l for 3fo output) the electrical length is either 0 or 45 degrees with
respect to the fundamental frequency. This represents either a short or an open circuit
for the second harmonic frequency. The magnitude o f the impedance o f the input
network at the second harmonic frequency (ZMijfo) versus transmission line length
(Lin2 fo) is shown in Figure 3.62, as previously noted the transmission line length Lin2 fo is
expressed in degrees with respect to the fundamental frequency.
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160
The reasons behind, and implications o f the optimum reflector offset lengths being
either 0 or 45 degrees (and the corresponding optimum impedance points being either
short or open) are several and are discussed below.
1400
1200
1000
(/)
E
800
^
600
N
400
200
Figure 3.62. Input im pedance o f 2fo Input Reflector Network vs. Phase Length in Degrees
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\ii Harm_Gen_via_Input_Cond\d Harmonic Reflection\Optimum
Reflector Networks (New)\Zin_vs_freq_2fo_refl_2_l 0_03.fig
Discussion of Optimum Reflector Offset Lengths
One implication o f the optimum 2fo reflector offset lengths being either 0 or 45
degrees (causing a short or open circuit at the gate, respectively) is that when the reflector
causes an open circuit at the transistor gate, some simulation difficulty can result. This
occurs because the impedance o f the input network M l (Figure 3.52) is driven up
towards infinity for a 2fo reflector length o f 45 degrees (Lin2 fo = 45 degrees), as shown in
Figure 3.62, between 44 and 46 degrees. The simulation problems can be remedied using
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161
a known technique [61] o f utilizing a large parallel resistance at the problematic node. In
this case a 10 mega ohm resistor was utilized at the transistor gate. As previously shown
in Figure 3.55 and Figure 3.56, this technique allows simulation o f a full range o f 0 to 90
degrees. In a more practical device model, such as that o f the actual PHEMT model
described in Chapter 2 (see Figure 2.14, page 40), finite input impedance allows for a
result which is more realistic and less problematic.
Optimum Reflector Length Considerations for Case C l, Optimized for 2fo CG
The clear benefit o f open circuiting the second harmonic is exemplified by case Cl
(VGO=Vfwd), where the reflector is optimized for 2fo CG. The maximum second
harmonic conversion gain occurs for a 2fo reflector length o f 45 degrees (corresponding
to an open circuit) at an input power o f -10 dBm*, as previously shown in Figure 3.60.
The corresponding second harmonic gate voltage magnitude (|Vgs|2 fo) response versus
Lin2 fo is shown in Figure 3.63. The 2fo gate voltage with no reflector present is also
shown in the figure. Figure 3.63 shows that the effect o f the optimum 2fo reflector
(Lin2 fo = 45 degrees) is to maximize the second harmonic voltage appearing at the gate.
At its maximum point, the 2fo reflector almost doubles the amount o f second harmonic
voltage content appearing at the gate o f the transistor compared to when no reflector is
used (dotted curve). As reflected in Equation ( 3.15 ) on page 95, this approximate
doubling o f the second harmonic gate voltage magnitude (VgS2 fo_withreflector =
2
* V g S 2 fo_without reflector)
leads to a propoitional increase in the 2 fo drain-source output
current, corresponding to an increase in the second harmonic conversion gain o f around
N ote from Figure 3.60, that the 2fo CG response is fairly constant between -10 and -3 dBm and that -10
dBm is utilized as the optimum point here since it provides a good illustration o f the effect o f the 2 fo input
reflector.
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162
6
dB (this is shown as the 4.8 dB improvement for case Cl in Table 3.4, page 159).
Considering the transistor is providing 2fo conversion gain via amplification o f the gate
voltage for case C l (as discussed in Section B.ii.a.S), the fact that maximizing the second
harmonic voltage at the gate gives the optimum conversion gain ( 2 fo) is reasonable.
0.08
— With Refl
■— No Refl
0.07
0.06
g
0.05
0.04
«
^ 0.03
0.02
0.01
30
90
Figure 3 .6 3 .2fo Reflector Phase Length vs. Second Harmonic Gate V oltage M agnitude: M odel A,
Case C l (VGO=Vfwd, Pin=-10dBm )
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\ii Harm_Gen_via_Input_Cond\d Harmonic Reflection\Optimum
Reflector Networks (New)\Opt2fo_Refl_ModeIA_CaseC_Rdc_50_vgin2foplot_pin-! 0_2_6_03.fig
Cases Studied in Further Detail:
Table 3.5. Cases Examined in Further Detail
C ase
A1
B1
Cl
O p tim iz e d for:
45
45
0
Infinite
Infinite
0
2 fo C G
3 fo C G
3 fo C G
C :\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd MdlsMi Harm_Gen_via_Input_Cond\d Harmonic Reflection\modelA PinPout
w_2fo refl 2_10_03\comparison_table_2_10_03.sxc
Several o f the other cases shown in Table 3.4 also exhibited significant amounts o f
conversion gain, warranting further study. This subset of cases from Table 3.4 is
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163
summarized in Table 3.5. For the other cases where an optimum conversion gain is
obtained at a 2fo reflector length of 45 degrees (case A1 for 2fo CG and case B1 for 3fo
CG, as shown in Table 3.5), the benefits o f the gate 2fo open circuit are less
straightforward than previously shown for case Cl (for 2fo CG). In these cases the
conversion gain mechanism is not directly related to amplification o f the gate-source
waveform (at the desired harmonic), and is dependent on both gate-source voltage
clipping across Dgs and the pinchoff mechanism o f the drain-source current generator.
For both cases some insight into the improvement provided by the 2fo input reflector is
obtained by observing the gate-source voltage and drain-source current waveforms.
Optimum Reflector Length Considerations for Case A l, Optimized for 2fo CG
Figure 3.64 shows the voltage and current waveforms for case A l for an input power
level close to that giving the optimum 2fo conversion gain (Pin=-ldBm).* Figure 3.64(a)
gives a comparison o f the gate-source voltage waveform when the optimum (Linafo = 45
deg.) 2fo reflector network is utilized compared to when no reflector is present. As
shown in Figure 3.64(a), the open-circuiting of the second harmonic distorts the
gate-source voltage waveform so that the clipping (occurring at Vgs = Vfwd = 0 V)
duration is significantly increased (i.e. the gate waveform now is driven up to the
forward conduction voltage for a longer period of time).
N o te that the true optim um occurred at an input p ow er o f 3 dB m (T able 3 .4 ), h o w ev e r, for e a se o f
sim u lation data p ro cessin g an approxim ate input p ow er lev e l w a s used.
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164
0.03
0.5
0.02
f 0.01
5 - 0 .5
D)
>
~a
N o R efl
O pt R efl
-
T im e ( s e c )
x l O ' ’’°
0.01
T im e ( s e c )
x 1 0 '^ °
Figure 3.64. Comparison o f Gate-Source Voltage and Drain-Source Current W aveform s for Case A l,
Pin=-1 dBm, Optimized for 2fo CG
C :\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\ii Harm_Gen_via_Input_Cond\d Harmonic Reflection\modelA PinPout
w_2fo refl 2_10_03\modelA_CaseA_wf_comp_plot_opt2foCG_9_19_03.fig
This change in the input Vgs waveform has the effect of distorting the output Ids
current from a trapezoidal-type waveform to a waveform which more resembles a
rectangular wave, as shown in Figure 3.64(b). This rectangular wave, as discussed
in Section 3.ii.a.5.v (page 102) and in [5] contains large second harmonic content as
it approaches a duty cycle of 25%. Thus the distortion described above accounts for
the increased 2fo conversion gain seen due to the 2fo input reflector providing a
second harmonic open circuit at the gate.
Optimum Reflector Length Considerations for Case A l, Optimized for 3fo CG
Interestingly, for case B 1 the 2fo open circuit at the gate provides improvement in the
third harmonic conversion gain. Figure 3.65 shows the gate voltage and drain current
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165
waveforms for case B 1 for an input power level close to that giving the optimum 3fo
conversion gain (Pin=5dBm).’
0.5
0.03
4
0.02
-0.5
<
w
•a
fr
O)
N o R efl
O pt R efl
-2.5
-
T im e (s e c )
x lo '^ °
0.01
T im e ( s e c )
x 1 0 ’^°
Figure 3.65. Comparison o f Gate-Source Voltage and Drain-Source Current W aveform s for C ase B l,
Fin=5 dBm, Optimized for 3fo CG
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\ii Harm_Gen_via_Input_Cond\d Harmonic Reflection\modelA PinPout
w_2fo refl 2_10_03\modelA_CaseB_wf_comp_plot_opt3foCG_9_20_03.fig
As shown in Figure 3.65(a), the second harmonic open circuit has a similar effect as
shown for case A l above, in that the clipping duration occurring at the forward
conduction voltage (Vgs=Vfwd=OV) is significantly increased. In this instance, however,
the effect seen on the output is to distort the drain-source current (Figure 3.65(b)) from a
rectangular-type waveform into more o f a square-wave type waveform. Thus, for case
B l, the 2fo input reflector is shown at a length Lin2 fo o f 45 degrees to significantly
increase the third harmonic conversion gain. In comparison with the previous case (case
A l, optimized for 2fo CG) opposite effects can be seen. In the previous case (case A l),
N o te that the true optim um occurred at an input p ow er o f -2 dB m (T able 3 .4 ), h o w ev e r, for e a se o f
sim u lation data p ro cessin g an approxim ate input p ow er le v e l w a s used .
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166
the trapezoidal drain current waveform became rectangular (Figure 3.64(b)) and the 2fo
CG was increased. In this case (case B l, optimized for 3fo CG) the rectangular
waveform became more square (Figure 3.65(b)) and the 3fo CG was increased.
Optimum Reflector Length Considerations for Case C l, Optimized for 3fo CG
The other result given in Table 3.4 showing significant improvement is the third
harmonic conversion gain for case Cl (VGO=Vfwd=OV). In this instance the optimized
2fo reflector length is 0 degrees (Lin2 fo=0 deg.) and provides a 2fo short circuit at the gate.
Figure 3.66 shows the gate-source voltage and drain-source current waveforms at the
input power level near the point o f optimum 3fo conversion gain (Pin=-7dBm).* As
shown in Figure 3.66(a) the short-circuiting o f the second harmonic at the gate causes the
gate-source voltage waveform to be distorted from a half-wave rectified sinusoid into a
wave resembling a square-wave (containing strong third harmonic content). This
distortion is also translated to the output drain-source current, which also becomes a
square-type waveform with strong third harmonic content, as shown in Figure 3.66(b).
Thus for case C l, shorting the second harmonic at the gate provides a significant
improvement in the third harmonic conversion gain.
N o te that the true optim um occurred at an input p ow er o f -1 0 dB m (T able 3 .4 ), h o w ev e r, for ea se o f
sim u lation data p ro cessin g an approxim ate input p o w er lev e l w a s used.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
167
0.1
0.025
0
S
(A
-
■D
0.1
(A
0.02
0.015
O)
>
-
0.2
-0.3.
0
—
—
2
4
T im e ( s e c )
6
x 1 0 ^°
0.005
N o R efl
O pt R efl
2
4
T im e ( s e c )
6
x 1 0 ’^°
Figure 3.66. Comparison o f Gate-Source Voltage and Drain-Source Current W aveform s for C ase C l,
Pin=-7 dBm, Optimized for 3fo CG
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\ii Harm_Gen_via_Input_Cond\d Harmonic Reflection\modelA PinPout
w_2fo refl 2_10_03\modelA_CaseC_wf_comp_plot_opt3foCG_9_20_03.fig
3.ii.d.3. Study of 3fo Input Reflection Using Idealized Model
A second harmonic reflector was shown in the previous section to be useful,
especially in enhancing the second harmonic output power. As previously shown in
Figure 3.13 and Figure 3.18, a significant amount o f third harmonic reflected power may
also exist at the gate. It follows that a third harmonic reflector may be useful in
increasing third (and possibly second) harmonic output. The circuit configuration for
using a third harmonic input reflector is shown in Figure 3.53 when n is set equal to 3.
Figure 3.67 shows a plot o f the 3fo conversion gain vs. 3fo input reflector phase
length (Linsfo) for case A l (VGO = -0.3V). Note that the phase length Linsfo is shown in
degrees with respect to the fundamental frequency fo and that the response for lengths
between 28 and 32 degrees were obtained using a 10 mega ohm parallel resistance as
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168
previously discussed. The figure shows that 3fo output can be greatly affected by the use
o f a 3fo input reflector.
------- 1----------------- 1----------------- 1----------------- -----------------
1
.
00
■■
.->"7V'"'
. X.
•
1
_ ...
.
.1 .
O
O
.
•
*
_________
•
;
•
•
_________
1
•
« •
( ► • • • *
• •
:
----------------- 1------------
0
•
Pin = -5dBm
Pin = OdBm
10
—
Pin = lOdBm
wlOMohm, Pin=-5dBm
.
20
30
40
..
50
60
Lin3,„ (deg)
Figure 3.67. 3fo Conversion Gain vs. 3fo Input Reflector Phase; M odel A, C ase A l
C:\Research\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\ii Harm_Gen_via_Input_Cond\d Harmonic
Reflection\Rflctr_Ntwk_Swps_8_6_03\modelA_fixed_9_12_03\
Opt3fo_Refl_ModelA_wl0Mohm_CaseA_Rdc_50_CG3foplot_9_15_03.fig
The effects o f the 3fo input reflector were fully characterized by performing a
simultaneous simulated sweep* o f the input power and the 3fo input reflector length
(L in 3 fo)
for cases A l, B l and C l. For each case (A l, B l, C l) the optimum length Linsfo
giving maximum second and third harmonic output conversion gain were obtained. The
resulting conversion gain response was compared to the equivalent case when no
reflector was used. The results are summarized in Table 3.6. For a detailed plot o f each
simulation for cases A l, B l and Cl refer to Appendix B.i.d.5 (page 485).
S e e d escrip tion o f a sim ultaneous sw ee p o n page 101
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169
Table 3.6 shows conversion gain data and utilizing a 3fo reflector at the gate. The
upper part o f the table shows the 2fo CG (even though the reflector is a 3fo reflector).
For case A l, the upper portion o f the table shows that, when compared with the case
where there is no reflector at all the conversion gain improvement is from negative
infinity (no 2fo CG) to -46.2 dB (when the 3fo reflector is optimized to provide a
maximum 2fo CG). The optimum location o f the 3fo reflector in this case is 30 degrees
and the available power for the result is 9 dBm (recall that a simultaneous sweep o f
Pavail and Lin3fo has been undertaken to give this result). Similar interpretations can be
obtained from the other entries in the upper portion o f the table.
Table 3.6. Optimum Conversion Gain Designs Utilizing a 3fo INPUT REFLECTOR
Optimum 2fo Conversion Ga n Results:
C a s e A1
(V G O = V m id )
M a x C G 2 fo (no R efl)*
P a v a il @ M a x C G (no Refl)'!
C ase B l
C ase C l
(V G O = V p) (V G O = V fw d )
-OO
Not
A p p lic a b le
-1.1
-1.1
-1
-1
-4 6 .2
-1.1
- 0 .8
P a v a il @ M a x C G (O pt)**
9
-1
- 1 0
Im p ro v e m e n t (d B )
CO
0
0 .3
30
0
60
-1 0 .9
-1 0 .9
M a x C G 2 fo (O pt)*
L in 3^^ ( D e g W R T fo )
Optimum 3fo Conversion Ga n Results:
M a x C G 3 fo (no R efl)*
P a v a il @ M a x C G (no R efl)*
-5
0
6
6
- 1 .6
-7 .6
-1 0 .6
P a v a il @ M a x C G (O pt)**
-3
3
5
Im p ro v e m e n t (d B )
3.4
3.3
0.3
Li n3^^ ( D e g W R T fo )
30
30
26
M a x C G 3 fo (O pt)*
* C G M a x i m i z e d W i t h R e s p e c t t o P a v a il
t C o r r e s p o n d i n g P a v a il V a l u e
C G M a x i m i z e d W i t h R e s p e c t t o b o t h P a v a il a n d Lin2fo
t
** C o r r e s p o n d i n g P a v a il V a l u e
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\ii Harm_Gen_via_Input_Cond\d Harmonic Reflection\modelA PinPout
w_2fo refl 2_10_03\comparison_table_2_10_03,sxc
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
170
In the case o f the conversion gain at 3fo given a 3fo reflector, as shown in the lower
portion o f Table 3.6, it is seen that the maximum improvement in conversion gain is 3.4
dB. The results presented in Table 3.6 are discussed below.
Case A l
With reference to Table 3.6, for case A l (VG0=Vmid=Vp/2), the third harmonic input
reflector gives a negligible improvement on the second harmonic conversion gain. As
previously shown in Figure 3.11 on page
8 6
, for case A l there is no 2fo output power
shown whatsoever. Therefore, although the optimum 3fo reflector brings the maximum
2fo conversion gain up to -46.2 dB from nothing (less than -300 dB), it is not expected
that much 2 fo conversion gain is obtainable for this case.
When optimized for maximum third harmonic conversion gain however, case A l
shows the largest amount o f third harmonic conversion gain (-1.6 dB) o f all the cases
tested. This design shows a 3.4 dB improvement over the optimum response using no
input reflector. The input reflector length Linafo giving this improvement occurs at 30
degrees (with respect to fo), which represents an open circuit to the third harmonic at the
transistor gate.
In order to understand why a 3.4 dB improvement is seen in 3fo, the gate-source
voltage and drain-source current waveforms can be examined as was done in the case of
the 2fo input reflector. Figure 3.68 shows the gate-source voltage and drain-source
current waveforms for an available power near to that giving the optimum 3fo conversion
gain (Pin=-ldBm).*
N o te this is su ffic ien tly c lo s e to the -3d B optim um valu e for c o n v e n ien ce o f com putation.
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171
0.03
(b)
“T i
it
ft
I
0.02 \11i
fr
1*
V
\i
ft
1
It
<n 0.01
\
i
I J
T3
If
1
\i
I
11 i t1
1__ u .
0
---- N o R efl
---- O pt Refl
—1
i .1
0.01
>-0.5
-
0
T im e (s e c )
2
4
T im e (s e c )
xIO
■10
Figure 3.68. Comparison o f Gate-Source Voltage and Drain-Source Current W aveform s for Case A l,
Pin=-1 dBm, Optimized for 3fo CG
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\ii Harm_Gen_via_Input_Cond\d Harmonic ReflectioMmodelA PinPout
w_3fo refl 2_1 l_03\modeIA_CaseA_wf_comp_plot_opt3foCG_9_20_03.fig
The figure shows the waveforms where the 3fo refleetor has been used to maximize
the 3fo conversion gain compared to where no reflector is used (note however that -IdBm
has been used instead o f -3dBm for Pin). Figure 3.68(a) shows that the effect of
reflecting the third harmonic with a 3fo open circuit at the gate is to create a gatesource waveform which is more rectangular in shape then when no reflector is
present. The resulting output current, shown in Figure 3.68(b), is distorted from a
trapezoidal to a squarer waveform. As discussed in Section 3.ii.a.5 (see Figure 3.26,
page 105), a square waveform has stronger third harmonic content than a
trapezoidal signal. Thus the open circuiting o f the third harmonic at the gate results
in an improved 3fo conversion gain.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
172
Case B l
For case B l, shown in Table 3.6, the third harmonic input reflector also gives
negligible improvement on the second harmonic conversion gain. As discussed in the
previous section (Section 3.ii.d.2, on page 155), for case B l the optimum second
harmonic conversion gain occurs between -10 and -1 dBm with no reflector present.
Since the 3fo reflected gate power does not begin to rise until an input power o f 0 dBm
for this case (as shown in Figure 3.18 on page 93), the 3fo input reflector provides no
improvement.
When case B l is optimized for 3fo conversion gain, the reflector does give an
improvement from -10.9 to -7.6 dB, although this third harmonic level is much smaller
than for case A l. Once again, the improvement shown can be seen in the gate-source
voltage and drain-source current waveforms. Figure 3.69 shows a waveform
comparison for case B l, at an input power near that giving the maximum 3fo conversion
gain (Pin=5dBm).
Figure 3.69(a) shows that the optimized 3fo reflector, which once again provides a 3fo
open circuit at the gate, causes the rectified sine wave (with no reflector present) to more
closely resemble a square wave. The resulting output drain-source current (Figure
3.69(b)) is changed into a more square shape where the waveform had been rectangular
without the input reflector present. As previously discussed for this case (case B l,
optimized for 3fo CG) when the 2fo input reflector was used (see Figure 3.65, page 165),
the square waveform gives a larger 3fo output than the rectangular waveform, resulting in
a larger third harmonic conversion gain.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
173
0.5
0.03
0.02
- 0 .5
f
O)
001
n
— N oR efl
—■ Opt Refl
-
T im e ( s e c )
x 1 0 ‘^°
0.01
T im e ( s e c )
x 1 0 ‘''°
Figure 3.69. Comparison o f Gate-Source Voltage and Drain-Source Current W aveform s for C ase B l,
Pin=5 dBm, Optimized for 3fo CG
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\ii Harm_Gen_via_Input_Cond\d Harmonic Ref1ection\modelA PinPout
w_3fo refl 2_1 l_03\modelA_CaseB_wf_comp_plot_opt3foCG_9_20_03.fig
Case C l
Finally, case Cl shows little improvement for optimum second or third harmonic
conversion gain. Perusal o f Figure 3.23 (page 98) in Section 3.ii.a.5 shows that there is
no 3fo reflected power for case C l, whieh explains why a 3fo input reflector would have
no effect.
The results of Table 3.6 show a result that is very similar to the previous section in
that the optimum 3fo conversion gain designs occur for a phase length o f around 30
degrees with respect to the fundamental (which corresponds to an open circuit for the
third harmonic).
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
174
0.12 " -------- 1............. 1------------1
1
1
f
0.08 ---------£
CO
;
------ With Refl
------ N oR efl
0.1
/ 1
/
-----
0.06
w
o
>
— 0.04 - ---------i ----------- u --------- --------- ----------
/
1
1 --------- 1
--------- . ........ ......^-----
0.02
10
20
30
L.
J_
40
50
Lin3 fo(Deg)
60
---------- 1,.
70
80
Figure 3.7 0 .3 rd harm onic Gate Voltage M agnitude vs. 3fo Input Reflector Phase Length: M odel A,
Case A l (VGO=Vmid, Pin = OdBm)
C:\Research\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\ii Harm_Gen_via_Input_Cond\d Harmonic Reflection\Optimum
Reflector Networks (New)\Opt3fo_Refl_ModelA_CaseA_Rdc_50_vgin3foplot_pinO_2_l l_03.fig
Figure 3.70, a plot o f the 3fo gate-source voltage magnitude |VgS3 fo|* versus the 3fo
input reflector length, shows a vital relationship similar to that shown in the previous
section (case C l, shown in Figure 3.63). For case A l, the optimum 3fo input reflector
length for maximum 3fo conversion gain corresponds to the length that gives the
maximum 3fo gate voltage magnitude. Although the 3fo conversion gain is not attributed
directly to amplification o f the 3fo gate voltage signal (as was the case with the 2fo
conversion gain and the 2fo gate voltage magnitude for case C l), the maximization o f the
3fo gate voltage clearly gives rise to the significant 3fo conversion gain increase shown.
In this instance the 3fo reflector network more than doubles the third harmonic gate
voltage magnitude compared to when no reflector is used.
T h e 3 fo co m p o n en t o f the F ourier Series representation for the gate-sou rce v o lta g e w a v efo rm .
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
175
In fact, all o f the cases in Table 3.6 that showed conversion gain improvement with
the use o f the 3fo input reflector did so for a reflector length of 30 degrees, and
correspondingly where the 3fo gate voltage magnitude was maximized. These
improvements are attributed to the way the 3fo input reflector manipulates the gatesource waveform, as was shown in Figure 3.68(a) and Figure 3.69(a). This manipulation
at the gate causes distortion o f the drain-source output current waveform (Figure 3.68(b)
and Figure 3.69(b)) such that the desired harmonic component o f Ids is maximized.
3.ii.d.4. Higher Harmonic Reflected Power Generated Via Input
Reflectors
In the previous sections the effects o f a 2fo and 3fo input reflector on the output
conversion gain was explored. A possible additional benefit o f these reflectors is that
nonlinear mixing between the re-reflected signal at the input and other harmonic signals
occurring in the gate-source diode may cause additional reflected power at other
harmonics. This additional harmonic power may be utilized by a “secondary” input
reflector. For example, a 2fo input reflector may be used on the input to increase the
output second harmonic conversion gain. This reflector may also, however, create
increased reflected power levels at the third harmonic which may subsequently be
utilized by a secondary input reflector at the third harmonic.
Figure 3.71 shows the reflected power levels at the relevant harmonics for case A l,
B l and Cl when the relevant reflectors are employed. For example, the solid curve in
Figure 3.71 shows the reflected 2fo power for case A l when a 3fo reflector is employed.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
176
I
Pref^fQ, ca seM , wi
f''ef3foi ca seB I, with 2fb Ref
t PrefjfQ,
I
IIII ^211fo Ref
c a s e dIf,W
with
Q
Pref^jg,
Pref^jg,caseA
caseAt,t, no/Ref
Q
Prefgjg. caseB t, no/Ref
0
Prefgfg, c a s e d , no/Ref
Prefjjg, C a s e d
' no/Ref (<-35 dBm)
Pin (dBm)
Figure 3.71. Illustrated Effects o f Input Reflector on the Reflected Power Levels at O ther Harmonics
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd MdlsMi Harm_Gen_via_Input_Cond\d Harmonic
Reflection\HigerHarmRefPwr_7_l_03\modeIA_caseABC_Pref_higerharm_vs_Pin_7_l_03.fig
For case A l (VGO=Vmid), Figure 3.71 shows a comparison o f the 2fo reflected gate
power when no input reflector is used (shown as the circles) to the 2 fo reflected power
when the optimum* 3fo input reflector is used (shown as the solid line). As shown in the
figure, when the 3fo input reflector is used for case A l, the reflected 2fo power level is
slightly reduced. For example, at an input power o f 0 dBm, the 2fo reflected power is -11
dBm without an input reflector compared to -13.5 dBm when the reflector is introduced.
However, even though the input reflector reduces the 2fo reflected power, significant
amounts o f 2fo power still exist (up to around IdBm for an input power o f 10 dBm) and
this 2fo power may now be utilized to further improve 3fo output via a secondary, 2fo
input reflector.
W here Lirisfo has b e e n op tim ized for 3 fo C G (se e T able 3.6 , p age 169).
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Ill
For case B l (VGO=Vp), Figure 3.71 shows a comparison o f the 3fo reflected gate
power when no input reflector is used (shown as the squares) to the 3fo reflected power
when the optimum* 2fo input reflector is used (shown as the dashed line). Comparing the
3fo reflected power levels for case B l when a reflector is used or not shows that the
addition o f the 2fo input reflector significantly increases the 3fo reflected power. An
improvement o f up to 7dB for an input power level o f 10 dBm is shown.
For case C l (VGO=Vfwd), Figure 3.71 shows a comparison o f the 3fo reflected gate
power when no input reflector is used (not shown because the power is less than -35
dBm) to the 3fo reflected power when the optimum^ 2fo input reflector is used (shown as
the dotted line). When no 2fo reflector is used for Case C l, no 3fo reflected power exists
whatsoever. The presence o f the 2fo reflector, however, causes large amounts o f 3fo
reflected power at the gate.
Figure 3.71 shows that the effect that the input reflector networks (at a harmonic nfo)
have on the reflected power levels at the other harmonics is significant. The utilization of
this reflected power at the other harmonics via a secondary input reflector network will
be explored in detail in Section 3.iv.c.
* W here Lin 2 fo has been optim ized for 2fo CG (see Table 3.4, page 159).
^ W here Lin 2 fo has been optim ized for 2fo CG (see Table 3.4, page 159).
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
178
3.in. Harmonic Generation via Various Output Conditions
Section 3.ii gave an analysis o f the considerations for multiplier design consisting o f
conditions on the input. As discussed in Section 3.i, several design considerations also
exist on the output, consisting of: the choice o f drain bias and load resistance; the
response o f the output network M2 at the desired output frequency; the choice o f DC bias
network at the drain; and the response o f M2 at the unwanted frequencies.
S.iii.a. Output Load and Bias
Much like the fact that the AC signal and DC bias level are o f primary consideration
on the input o f the device, the AC load and DC bias level are typically o f primary
consideration on the output. In the most basic sense, the choice o f a certain load
resistance and drain bias level will determine what regions of operation the output signal
will fall into. A standard practice is to prevent a device from entering the linear or
breakdown region, which may or may not be desirable. This section explores the use o f a
resistive output load and drain bias level in the manipulation o f harmonics on the output
o f an idealized device.
The idealized model, model A, was given a simplified drain-source current generator
response which was not a function o f the output voltage Vds. As a result, the choice o f
output load and bias is trivial. The amount o f output power at each harmonic is simply
scaled by the choice o f load resistance R l , as will be shown. Due to this consideration,
several models with different Ids(Vds) relationships were studied. These are shown in
Table 3.7 (note that column 2 shows the Ids versus Vgs relationship and column 3 shows
the Ids versus Vds relationship).
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179
Table 3.7. Models Tested in Output Load and Bias Study*
Model
Ids vs. Vgs Relationship
A
L in e a r
B
L in e a r
C _2*
L in e a r
Ids vs. Vds Relationship
Constant (all v o lta g e s )
Linear (b e lo w kn e e v o lta g e V k i),
Constant (a b o v e k n e e v o lta g e V k i)
Linear (b e lo w kn e e v o lta g e V k i),
Constant (a b o ve kn e e v o lta g e V k i,
b e lo w re v e rs e -b re a k d o w n v o lta g e V rb d ),
Breakdown (a b o v e re v e rs e -b re a k d o w n
v o lta o e V rb d )
Bias\tableofmodels_output_a.sxc
0.03
Saturation Region
Vgs = 0
0.025
:
—■ ■■
X
□
Idss
0.02
•
O
0.015
^
<]
\/g s = Vp/2
"D
A
0
#
0.01
V
ModelA, VGO=Vp
ModelA, VG0=Vp/2
ModelA, VG0=0
Case A l Bias Point
Case A2 Bias Point
Case A3 Bias Point
Case Bl Bias Point
Case B2 Bias Point
Case B3 Bias Point
Case Cl Bias Point
Case C2 Bias Point
Case C3 Bias Point
0.005
Vgs = Vp
Vki
Vds (V)
Figure 3.72. DC IV Curves o f M odel A, W ith Cases Tested
C :\R esearch\l_B_l Undrstndng NL MechVB Stdy Idlzd Mdls\i Dev Idealized Models\Comparisons_w_Meas_data\
modelA_IV_wcases_7_2_03 .fig
Model A was previously described in Section 3.ii.a.3, on page 78, by Equation (3.13
). The DC Ids versus Vds response o f model A is shown in Figure 3.72, for Vgs values
equal to;
M o d e l C _ 2 is a r ev isio n o f an original m od el called m o d el C w h ic h n eed ed a slig h t r ev isio n in order to
appropriately estim ate th e resp on se o f the actual P H E M T transistor.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
180
•
Pinchoff (Vp)
•
Midway (Vmid=Vp/2)
•
Forward conduction (Vfwd=0).
The figure also shows nine bias points (case A1 through case C3, listed in the legend
in Figure 3.72) which are utilized in this study and will be described in more detail in
Table 3.8. Note that, as shown in the figure, model A only has a saturation region of
operation.
Model B (Figure 3.73) has a linear/saturation transition region which is described by:
I DSS 1
Ids(Vgs,Vds) =
'-DSS
Vds > Vki; Vgs > Vp
-
Vp
1Vp
Vds
Vki
0< V ds< V ki ; Vgs>Vp
( 3 .3 2 )
Vds > 0 ; Vgs < Vp
Where Vki is the “knee voltage” which describes the point where Vds transitions from
the linear to the saturation region. The ADS schematic o f model B is shown in Appendix
B.ii.a.l (page 490). Figure 3.73 shows the DC Ids versus Vds response for model B. As
shown in the figure, model B is comprised o f both a linear and saturation region o f
operation. Note that the nine bias points (case A1 - case C3) are also shown in the
figure.
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181
0.03
J. Saturatior —
Region
Linear
0 .0 2 5
1/
Idss
m
0.02
0)
X
■
•
•
«
□
O
^
0 .0 1 5
Vgs = V p /i
T3
A
—_ _ _.
Q —
0
♦
V
1
:7
0 .0 0 5 ■S
0.01 i• /
M odelB, VG O =Vp
M odelB, V G 0 = V p /2
M odeiB, V G 0 = 0
C a s e A1 Bias Point
C a s e A 2 Bias Point
C a s e A 3 Bias Point
C a s e B1 Bias Point
C a s e B2 Bias Point
C a s e B 3 B ias Point
C a s e C l Bias Point
C a s e C 2 B ias Point
C a s e C 3 Bias Point
i
'J
1
l> — '
Vgs = Vp
-----
'— A
Vds (V)
Figure 3.73. DC IV Curves o f M odel B, W ith Cases Tested
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\i Dev Idealized Models\Comparisons_w_Meas_data\
modelB_IV_wcases_7_2_03.fig
Model C_2 has the same Ids current equation as model B. The gate-drain diode (Dgd,
as shown in Figure 3.2, page 65 and described in Appendix B.ii.a.2, page 491) is added
on to this model, which introduces the reverse-breakdown region o f operation. The gatedrain diode follows the equation:
G {Vgd-VJwd)
7 g rf =
Gj {Vgd - VaoM )
0
V gd> Vfivd
Vgd <
^ Vgd < Vfivd
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( 3 .3 3 )
182
Where Vfwd is the forward conduction voltage (as previously shown in Section
3.ii.a.3), Vcorbd is the reverse-breakdown voltage (where Dgd conducts current in the
reverse direction), G is the conductance when this diode is on, and Gb is the conductance
when the diode is in reverse-breakdown. Note the difference between the reversebreakdown voltage o f the gate drain diode VoDrbd, and the voltage where the transistor
enters the reverse breakdown region Vrbd. Since the gate-drain voltage is equal to the
gate voltage subtracted from the drain voltage, the drain-source voltage required to drive
the transistor into the reverse breakdown region varies. The reverse breakdown voltage
Vrbd is defined as the drain-source voltage required to drive the transistor into reverse
breakdown when Ids is equal to zero (or when Vgs is equal to the pinchoff voltage). The
reverse breakdown voltage o f the gate-drain diode Voorbd is the constant, overall voltage
drop across Dgd required to drive it into reverse-breakdown. For model C_2 Vrbd is
equal to 4.5V and Vcorbd is equal to 5.1V.
The ADS schematic o f model C_2 is shown in Appendix B.ii.a.2 (page 491). Figure
3.74 shows the DC Ids versus Vds response for model C_2.
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183
0.03
0.025
Saturation
RIegion
Linear
Rev B D I I •
Vgs = 0
X
□
0.015
O
JVgs = Vp/2
^
^
1
A
^
♦
V
M od elC 2, V G O =Vp
M od elC 2, V G 0 = V p /2
M odelG 2, V G 0 = 0
C a s e A1 Bias Point
C a s e A 2 Bias Point
C a s e A 3 B ias Point
C a s e B1 B ias Point
C a s e B2 B ias Point
C a s e B3 B ias Point
C a s e C l Bias Point
C a s e C 2 Bias Point
C a s e C 3 B ias Point
0.005
Vgs = Vp
4
Vrbd
5
Vds (V)
Figure 3.74. DC IV Curves o f M odel C_2, W ith Cases Tested
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\i Dev Idealized Modeis\Comparisons_w_Meas_data\
modelC_2_I V_wcases_7_2_03.fig
As shown in the figure, model C_2 is comprised o f the linear, saturation, and reversebreakdown regions o f operation.
As shown by Figure 3.73 and Figure 3.74, Models B and C_2 have nonlinear
transition regions which can effect the generation o f harmonics on the output. As the
figures also show, cases A l, B1 and Cl were those previously studied where the drain
bias Vdd is set midway between the knee voltage (Vki) and the reverse breakdown
voltage (Vrbd). Cases A2, B2 and C2 represent new bias cases where the drain voltage
bias is set equal to the knee voltage. Cases A3, B3 and C3 represent bias cases where the
drain voltage bias is set equal to the reverse breakdown voltage.
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184
Table 3.8. Cases Tested in Output Load and Bias Study
Case
A1
A2
A3
B1
B2
B3
C1
C2
C3
Load
nout Signal
B ia s
Pin (dBm) |V g|(V )
VGO(V)
V d d (V )
A1.1
-7
IVd I/2
V p /2
A1.2
-1
IVpl
Vp /2
A1.3
5
2 1 V dI
Vp /2
A2.1
-7
IVd I/2
Vp /2
A2.2
-1
Vp /2
Vp / 2
Vrbd
A2.3
5
IVd I
2*|V d I
A3.1
-7
iVpj/2
A 3 .2
-1
iVpj
(ohms)
(Vrbd+VkiV2 5 0 , R , „ , , = 1 6 0 , 2 5 0
(Vrbd+Vki)/2 5 0 . R , „ „ ^ = 1 6 0 , 2 5 0
(Vrbd+Vki)/2 5 0 . R , „ „ , = 1 6 0 , 2 5 0
5 0 ,R ^ ,;,= 1 6 0 ,2 5 0
Vki
Vki
5 0 ,R ,.„ ,= 1 6 0 ,2 5 0
Vp /2
Vki
5 0 ,R ^ « ^ = 1 6 0 ,2 5 0
Vp /2
Vrbd
5 0 ,R ^ « ;,= 1 6 0 ,2 5 0
5 0 ,R ^ ,^ = 1 6 0 ,2 5 0
5 0 ,R ^ ,^ = 1 6 0 ,2 5 0
A 3 .3
5
2*IVp|
Vp /2
B1.1
-7
IVp I/2
Vp
Vrbd
(Vrbd+VkiV2 5 0 , R ^ , ^ = 1 6 0 , 2 5 0
(Vrbd+VkiV2 5 0 , R ^ , , - 1 6 0 . 2 5 0
B 1 .2
-1
IVd !
Vp
B 1 .3
5
2*|Vpl
Vp
82.1
-7
IVp I/2
Vp
B 2 .2
-1
IVp I
Vp
Vki
5 0 ,R ^ ,^ = 1 6 0 ,2 5 0
B 2 .3
5
2*IVp I
Vp
Vki
5 0 ,R ^ « ^ = 1 6 0 ,2 5 0
B3.1
-7
IVp I/2
Vp
Vrbd
B 3 .2
-1
IVp !
Vp
Vrbd
5 0 ,R u, . a=1 60 ,2 50
5 0 ,R l„„^=160,250
B 3 .3
5
21Vp I
Vp
C1.1
-7
IVol/2
Vfwd=0
C 1 .2
-1
IVpj
Vfwd=0
C 1 .3
5
2*IVp|
VlVvd^O
C2.1
-7
IVpl/2
Vfwd=0
C 2 .2
-1
IVp !
Vfrtd=0
Vki
C 2 .3
5
2*|Vp|
Vfwd=0
Vki
5 0 ,R ^ „ ^ = 1 6 0 ,2 5 0
(Vrbd+VkiV2 5 0 , R ^ « ^ = 1 6 0 , 2 5 0
5 0 .R ,.„ ^ = 1 6 0 ,2 5 0
Vki
50 ,R ^ ,^ = 1 6 0 ,2 5 0
Vrbd
fVrbd+VkiV2 5 0 , R ^ „ ; , = 1 6 0 , 2 5 0
(Vrbd+Vki)/2 5 0 . R , „ „ , = 1 6 0 , 2 5 0
(Vrbd+Vki)/2 5 0 , R ^ « ^ = 1 6 0 , 2 5 0
5 0 ,R ,„ ,= 1 6 0 ,2 5 0
Vki
5 0 ,R ,.„ ;,= 1 6 0 ,2 5 0
03 .1
-7
IVp I/2
Vfwd=0
Vrbd
5 0 ,R ^ « ^ = 1 6 0 ,2 5 0
C 3 .2
-1
IVp !
Vfwd=0
Vrbd
5 0 ,R ^ „ ;,= 1 6 0 ,2 5 0
C 3 .3
5
2*lVpl
Vfwd=0
Vrbd
5 0 ,R ^ „ ^ = 1 6 0 ,2 5 0
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\ii Harm_Gen_via_Input_Cond\a Input Sig and Bias\table o f cases.sxc
The cases are summarized in Table 3.8, as follows: The two columns, labeled “Case,”
show the name o f each case tested. The third column “Pin” shows the available generator
power level used for each case (note that for Pin versus Pout simulations the eases are
generically referred to as case A l, case B2, etc. since Pin is a swept value). The
available input power levels were chosen to give an AC input gate voltage
magnitude |Vg| equal to 14 pinchoff, pinchoff, and twice the pinchoff voltage. These
AC input voltage magnitudes are shown in the fourth column. The fifth column “VGO”
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
185
shows the gate bias level. Note that VGO and Vg represent the input voltage signal and
were previously shown in Equation ( 3.1 ) on page 72, repeated below:
Vgs ( ) = VGO + Vg»cos(c()j)
(3.1)
7
The sixth column “Vdd” shows the various drain bias levels tested in this study. The
final column
“R l”
shows the various loads tested. The load R l o p i ^ is an optimum load
which will be explained in section S.iii.a.l. Note that the case names also follow the
convention previously presented in Table 3.1 on page 83. In order to characterize the
effects o f variation in the DC drain bias and load resistance, the cases o f Table 3.8 were
analyzed in ADS using the circuit configuration o f Figure 3.75.
M1
M2
Ids
Vds
rl=
Swept
Vgs
Rdc=50Q
VGO
Vdd = Swept
Figure 3.75. Circuit Schem atic for Output Load and Bias Study
C;\research\figures\jj m l m2 outload_a BD.ai
The cases in Table 3 . 8 were analyzed from two perspectives. First, the effects of
varying the load resistance ( R l , shown in Figure 3 . 7 5 ) were studied. Second, the
effects of varying the drain-bias voltage (Vdd, shown in Figure 3 . 7 5 ) were analyzed.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
186
A schematic o f the ADS simulation for this study is shown in Appendix B.ii.a.3, page
493.
3.iii.a.l. Variation in Load Resistance.
The output load resistance may be varied while trying to optimize the response o f a
frequency multiplier.
Preliminary Consideration
•
Power Amplifier Perspective
In the area o f power amplifier design, techniques exist to determine optimum load
conditions for a given gate bias and set o f transistor parameters. By utilizing the
idealized models (A, B, and C_2, Table 3.7), the effects o f varying Rl can be studied,
definitions for optimum load for power amplifiers can be verified, and several
conclusions regarding the choice o f load in frequency multiplier design can be drawn.
In power amplifier designs, the load resistance is typically chosen to give maximum
output swing constrained to the saturation region. As shown in Kushner [44], values for
optimum load resistance can be chosen assuming an output circuit utilizing a load
resistance with a parallel, tuned LC filter centered at the fundamental frequency or
assuming a simple resistive load. In this section the simple resistive load is utilized as
shown in Figure 3.75.
For case A TI (VGO=Vmid, Vg=|Vp|/2), shown in Table 3.8, maximized output power
occurs when the maximum drain current and voltage swing is obtained. The gate voltage
is set to swing between Vp and 0. This maximizes the corresponding drain current swing
to be from zero to the saturation current ( I d s s » 25mA). The boundaries o f the
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
187
corresponding drain voltage swing are set utilizing the finite saturation region given by
the response o f model C_2 and are from the knee voltage, Vki » .5 V, to the reverse
breakdown voltage, Vrbd « 4.5 V. To obtain the above voltage swing, the drain bias
(Vdd) is set halfway between Vki and Vrbd (Vddmid) and the load resistance
(R
l)
is
adjusted to allow the drain-source voltage to reach the boundaries defined above. The
resultant optimum load resistance RLopt for case A l (Rlopi^) is calculated as:
Vdd —Vki
Vrbd - Vki
" ~
1 ^DSS
------------
Where the transistor parameters give a value o f RLopt^ = 160 ohms.
Although the above calculation for this “optimum” load resistance for a power
amplifier is useful, it should be taken in stride. A frequency multiplier design will
have a different load for each harmonic frequency and the actnal load R l will
usually only be presented to the desired output harmonic. Although not
representative of an actual multiplier circuit, studying variation in R l for case A l.l
helps verify that the optimum load choice is that which maximizes the drain-source
voltage swing, constrained to the saturation region. This optimnm definition can
also be applied to frequency multipliers when a parallel LC filter is utilized on the
output, as will be shown in Section 3.iv.a. Furthermore, the effects of the choice of
R
l
provide insight into what happens when the device is driven into different
regions of operation. For case A l.l, each model (Table 3.7) has been simulated to study
the effects o f varying the load resistance
(R
l)
and the results are presented below in
Section B.iii.a.l.i. For the other cases (case B l, case C l, etc.) the choice for optimum
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
188
load is dependent on the choice o f termination for the other harmonics [6 ]. Since feeding
all o f the output harmonics into R l is not a practical situation for these cases, they were
not studied. In Section 3.iv, variation in R l is studied utilizing these other cases in a
more practical multiplier configuration.
5. iii. a. 1. L CaseA 1.1 R esu lts:
The effects o f varying the load resistance are characterized by examining the output
conversion gain response with changes in the load resistance value. Figure 3.76 shows
the conversion gain response versus load resistance for case A l.l (see Table 3.8), where
R l is swept from 50 to 300 ohms. This case (A l.l) corresponds to an input voltage
swing from pinchoff to forward conduction (Vfwd=OV).
21
20
19
18
OQ
TJ
T3
T3
17
a
@
C O -10
16
(!)
O 15
O -15
0 -1 5
-20
-20
—
ModelA
— — ModelB
ModelC-2
f s Calc w / R,
-25
-25
100 150 2 00 2 50 300
-30
50
14
13
lo p t
12
50
(oh m s)
100 150 200 2 50 300
(oh m s)
-30
50
100 150 200 2 5 0 300
R^ (o h m s)
Figure 3.76. Conversion Gain Response vs. Load Resistance for Case A l . l (VGO=Vmid, Vdd=Vdd„,id,
Vg=|Vp|/2), Comparison o f Models A, B and C_2
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd MdlsMii Harm Gen via Output Conditions\a Output Load and
Bias\modeI_A_B_C_2_rlswp_9_22_03\comp_caseAl_l pin_m6_5dbm_rIswp_plotB_9_22_03.fig
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
189
The figure gives a comparison o f the response o f models A, B and C_2 , for the
fundamental, second and third harmonics. Figure 3.76(a) shows the conversion gain at
the fundamental frequency, and includes the calculated (refer to Section B.ii.a for the
calculation methods) conversion gain when the load is set to the theoretical optimum
(calculated by Equation ( 3.34 ) above to be 160 ohms). For model A, for which Ids has
no Vds dependence, the output power and conversion gain is directly proportional to Rl.
As the value o f R l gets larger the output power level is raised accordingly, as described
by Equations ( 3.9 ) and ( 3.10 ) and shown in Figure 3.76(a). Since the model (A)
contains only a saturation region, the output remains sinusoidal and no 2 fo or 3fo
conversion gain is shown as R l is varied.
The model B response o f Figure 3.76(a) is identical to model A for load resistances
below the optimum value (RLopt^=160 ohms). For these lower resistances the model is
constrained to the saturation region where models A and B are equivalent. When the
resistance is raised past the theoretical optimum (RLopt^=160 ohms), however, the
response o f model B diverges from that o f model A. The larger resistance values cause
model B to enter the linear region when the drain source voltage is driven down to the
knee voltage. This effect o f model B making a nonlinear transition between the linear
and saturation region causes the fundamental frequency conversion gain to deviate from
the response o f model A, as exhibited in Figure 3.76 (a). As shown in Figure 3.76(b) and
(c), when model B begins making these nonlinear transitions, 2fo and 3fo output power
arises.
Model C_2 shows a similar response to model B. When the load resistance is smaller
than, or equal to the theoretical optimum, the response o f model C_2 matches model A.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
190
As the load resistance becomes larger, the conversion gain at the fundamental frequency
begins to drop, as shown in Figure 3.76(a). At the same time, the fo conversion gain
begins dropping, the conversion gain at 3fo begins to rise (Figure 3.76(c)) as the
transistor begins to make transitions between the saturation, linear, and reversebreakdown regions.
The lower fundamental frequency output level due to a load resistance larger than the
calculated optimum is also discussed in Kushner [44]. As described in the work by
Kushner, when the linear (and/or reverse-breakdown) region is breached, then choosing a
load greater than the optimum results in an output voltage swing which is the same as
when the load is set to the optimum, but a smaller output current swing occurs. Note that
this principle becomes much more evident when observing the waveform plots for each
case. These waveforms will be shown below. As a result o f this reduction in output
current swing, the overall output power level at the fundamental frequency is reduced. In
model A, which has no linear or reverse breakdown region, the drain-source voltage
swing is unconstrained, and there are no limits on the maximum load power obtainable
by increasing Rl.
It is interesting to observe that for the more complex models (model B and C_2),
significant amounts o f 2fo and 3fo conversion gain exist when R l is greater than Rlopi^For model B, a significant 2fo and 3fo conversion gain is found, where there is none for
model A. Similarly, model C_2 shows strong 3fo conversion gain when R l is greater
than Rlopi^- These higher order harmonics are seen because the transistor, previously
operating only in the saturation region, is now making transitions between the saturation
region, the linear region and reverse breakdown region. These nonlinear transitions can
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191
be represented as a nonlinear output conductance, Gds, which is capable o f generating
harmonics o f the fundamental frequency on the output. The presence o f these higher
order harmonics for larger load resistance values raises the possibility o f utilizing the
nonlinearity o f the “knee” and “reverse breakdown” regions o f operation for the
generation o f beneficial harmonics.
The nonlinear transitions described above can be clearly observed by comparing the
time-domain waveforms o f models A, B and C_2. Figure 3.77 shows the waveform plot
o f case A l.l (VGO=Vmid, Vdd=Vddmid, Vg=|Vp|/2, Pin=-7dBm) for model A, where the
load R l is varied to values of less than, equal to, and greater than the optimum value
Rropt^ (these values are Rl =50, Rl = RLopt^=160, and Rl =250 ohms respectively).
Figure 3.77(a) is a plot o f the DC Ids versus Vgs relationship. Part (b) shows the
voltage waveform at the gate. Part (c) is the corresponding drain current waveform. Part
(d) is the DC Ids versus Vds relationship, with the load-line super-imposed on it (shown
as the solid line with dots). The load-line plot, shown in part (d) (and also to be shown in
Figure 3.79(d) and Figure 3.82(d)), refers to “a plot o f the instantaneous drain-source
current versus drain-source voltage,” [44]. By super-imposing it on the device model IV
curves, the regions o f operation can be determined and further insight into the effects o f
the choice o f load can be obtained. As shown in figure, as the load resistance Rl is
increased, the slope (lAIl/jAVl) of the corresponding load-line is decreased. Part (e)
shows the drain-source voltage waveform.
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192
“
0.03
0.03
0.03
0.02
0.02
0.02
0.01
0.01
(flJ
T
0.01
time (sec) ^ ., q -10
V g s (V )
x IO
'^L'l’^LopfA
Vds (V)
-10
x IO
-10
0
0
o(U2
<0
—
R, <R.
—
R.L =R.L o p tA
L
2
L o p tA
R, >R,
L
4
L o p tA
4
6
6
■0.6
-0.4
-0.2
■1
0
0
Vgs (V)
1
2 3 4
Vds (V)
5
6
Figure 3.77. W aveform Plot for M odel A, Case A l.l (VGO=Vmid, Pin=-7dBm , Vg=0.3 V)
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\iii Harm Gen via Output Conditions\a Output Load and
Bias\comp_model_plots_9_25_03\modeIA_caseAl_waveforms_pin_m_7_loadswp_9_25_03.fig
0.35
t
0.014
j (a) G ^ te-S oilrce
I
V oltage
0 .3 ||
13)
(b) Drain C urrent
3.5
^
^
0.012
3
0.25
0.01
2.51 k
0.2
^ 0 .0 0 8
TO
g,0.15
10
'
D>
O)
(D
;o
(c) b r a in -S o u r c e
V()ltage
03
0.006
0.1
0.004
0.05
0.002
♦
R^=50
▲
R|^=160
■
R^=250
^ 1 .5
>
1
0.5
-----0
0
0
Freq (GHz^.,o9
■ f-4
Freq (GHz^ . , q9
Figure 3.78. Fourier Series Plot for M odel A, Case A l . l (VGO=Vmid, Pin=-7dBm , V g=0.3 V)
C :\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd MdlsNiii Harm Gen via Output Conditions\a Output Load and
Bias\comp_model_p!ots_II_26_03\modeIA_caseAl_l_FSPlot_l l_26_03.fig
R e p r o d u c e d with p e r m is s io n of t h e cop y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e r m is s io n .
193
As seen by observing Figure 3.77(d) and Figure 3.77(e), the drain-source voltage
swing increases linearly with the increase in Rl. The drain voltage swing is simply a
function o f the drain current times the load resistance. This basic model has no limiting
function as Vds changes and the drain-source voltage can even swing negatively as
shown in part (e) of the figure, where the voltage minimum is seen to decrease to
approximately -0.5 V.
The Fourier harmonic components o f the waveforms in Figure 3.77(b), (c) and (e) are
shown in Figure 3.78. Figure 3.78 shows the effect o f varying the load resistance on the
generation o f harmonics at the input and output o f the transistor for model A. As
previously shown in Figure 3.77(b), the gate-source voltage signal is the same sinusoidal
signal for each choice o f load resistance because model A is unilateral and has no
feedback mechanism. This is observed in the harmonic components o f the gate-source
voltage, shown in Figure 3.78(a) to contain only a DC and fundamental frequency
component. Figure 3.77(c) showed that the drain current signal was also sinusoidal and
independent o f changes in the load resistance. Figure 3.78(b), which shows the harmonic
components o f the drain current, confirms that only DC and fo components are present in
the drain current and that the same drain current level is obtained for each load resistance.
Figure 3.78(c) shows the drain-source voltage harmonics. The figure shows that as the
load resistance is increased, the fundamental frequency component o f the drain-source
voltage is raised accordingly. The figure also shows that, as expected, no higher order
harmonics are present in the drain-source voltage.
Figure 3.79 is a figure showing the same representations as Figure 3.77, but now for
model B.
R e p r o d u c e d with p e r m is s io n of t h e cop y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohib ited w ith o u t p e r m is s io n .
194
0.03
0.03
L03
l i ■'LoptA
0.02
0.02
1.02
0.01
0.01
1,01
O _ L 0 p tA
T3
~
V g s (V )
time (sec)
Vds (V)
-10
x10
x IO
-10
0
6
■0.6
-0.4
-0.2
V g s (V )
0
0
1
2
3
4
5
Vds (V)
Figure 3.79. W aveform Plot for M odel B, Case A l . l (VGO=Vmid, Pin=-7dBm , Vg=0.3 V)
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd MdlsMii Harm Gen via Output Conditions\a Output Load and
Bias\comp_model_plots_9_25_03\modelB_caseAl_waveforms_pin_m_7_loadswp_9_25_03.fig
This figure shows what happens when the knee voltage transition is added in. Here,
the response o f model B exactly matches that o f model A when the load resistance is less
than or equal to RLopt^- When R l becomes greater than RLopt^, however, the response
becomes quite different. The drain-source voltage is limited approximately to the knee
voltage (Vds ~ Vki) and a clipping effect is produced when the load resistance causes the
drain-source voltage to hit the linear region. The output voltage (Vds), during the time
period which it falls into the linear region, is constrained to a value close to the knee
voltage (Vds<Vki). This is exhibited in Figure 3.79(d) and Equation ( 3.32 ) which show
that, when the device hits the linear region, the output current can vary significantly, but
the drain-source voltage is constrained between zero volts and the knee voltage Vki (ie
0<Vds<Vki once Vds becomes less than or equal to Vki). The resulting drain current,
which must obey the resistive current and voltage relationship in Equation ( 3.9 ),
R e p r o d u c e d with p e r m i s s io n of t h e cop y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e rm is s io n .
195
subsequently undergoes clipping, due to the fact that the drain-source voltage is clipped
beginning at the knee voltage (Vki).
0 .0 3
R.L<R.LoptA
R =R
L
LoptA
RL>R,LoptA
0 .0 2 5
0.02
C lipping S e e n I)
w hI e n R,L>R,LoptA
'
0.01
0 .0 0 5
time (sec)
xIO
-1 0
Figure 3.80. Enlarged Plot o f Figure 3.79(c): Ids W aveforms for Mode! B, Case A l.l
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd MdlsMii Harm Gen via Output Conditions\a Output Load and
Bias\comp_modeIj3lots_9_25_03\modelB_caseAl_waveforms_pin_m_7_loadswp_partc_zoom_9_25_03.fig
This clipped drain current can be clearly seen in Figure 3.80, which is an enlarged plot
o f Figure 3.79(c). The output waveforms (both voltage and current) are single-sided,
clipped sinusoids which contain significant amounts o f second harmonic content as
evident from a perusal o f Figure 3.76(b).
The Fourier harmonic components o f the waveforms in Figure 3.79(b), (c) and (e) are
shown in Figure 3.81. Figure 3.81 shows the effect o f varying the load resistance on the
generation o f harmonics at the input and output o f the transistor for model B.
Figure 3.81(a) shows the gate-source voltage harmonics corresponding to the
waveforms previously shown in Figure 3.79(b). Figure 3.81(a) confirms that Vgs is a
R e p r o d u c e d with p e r m i s s io n of t h e co p y rig h t o w n e r. F u r th e r r e p ro d u c tio n prohibited w ith o u t p e rm is s io n .
196
simple sinusoid and is independent o f the load resistance, which is to be expected from
model B since (like model A) it has no feedback mechanism.
] (a) G 'ate-Soiirce
f
1--------- 1------- --------- r
(c) D rain-So u rce
V o lta g e
3 . 5
0 . 0 1 4 p - - - - - - - - - - - - 1- - - - - - - - - - - - ! - - - - - - - - - - - - r
^
(b) Drain C urrent
V ojtage
0.012t-
0 . 3 1 1
%■
0.01
0 . 2 5
1
I
*
t
O)
^ 0 . 0 0 8
0 .2
D)
TO
O)
OJ
CO
4
"w D 0
S , 0 . 1 5
>
R|^=160
0
0
0
Freq (GHz^ . | 0 9
-------- \
T3
H Rl=250
— .-1 ►
0.002
0 . 0 5
A k
(/>
>
. 0 0 6
0 . 0 0 4
0 .1
R|^=50
--------- L
l-l
!I _ J
Freq (GHz^ .iq®
Freq (GHz^ .jq®
Figure 3.81. Fourier Series Plot for M odel B, Case A l . l (VGO=Vmid, Pin=-7dBui, V g=0.3 V )
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\iii Harm Gen via Output Conditions\a Output Load and
Bias\comp_model_plots_ll_26_03\m odelB_caseAl_l_FSPlot_ll_26_03.fig
Figure 3.81(b) shows the drain current harmonics corresponding to the waveforms
previously shown in Figure 3.79(c). The harmonic content o f the drain current is linear
(with DC and fo content only) when the load resistance is smaller than
to
(R
l
(R
l=
or equal
50)
=160) the optimum load resistance. When the load resistance becomes larger ( R l
=250), drain current waveform is distorted (Figure 3.79(c)), causing 2fo and 3fo
harmonics to arise. Figure 3.81(c) shows the drain-source voltage harmonics
corresponding to the waveforms previously shown in Figure 3.79(e). Similar to the drain
current, the harmonic content o f the drain-source voltage is linear (with DC and fo
content only) when the load resistance is smaller than
(R
l
=50) or equal to
(R
R e p r o d u c e d with p e r m i s s io n of t h e co p y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e rm is s io n .
l
=160) the
197
optimum load resistance. When the load resistance becomes larger (Rl =250), the drainsource voltage waveform is distorted (Figure 3.79(e)), causing 2fo and 3fo harmonics to
arise.
0.03
0.03
0.03
(d) 1 Rl^Rlo^ia
(C)
■o
A
0.02
0.02
1
/
\
/
0.01
0.01
-0.6
-0.4
-0.2
0
Vgs (V)
s A \ RL''AoptA_ _
0.02
'^l='Rl; pw
1
1
"(0O
<0
TJ
j
— ^y
”
2
4
time (sec)
RL <RL o p tA
RL =RL o p tA
R. >R,
L
L o p tA
”
0.01
Oi
0
6
0
1
2
3
Vds (V)
0
5
(6)
j
o0 )
-----
1
1
.....
> (
2
-0.4 -0.2
Vgs (V)
4
x 1 0 '^“
^ 2
i4
-0.6
;
D
1
2
3
4
£
Vds (V)
Figure 3.82. W aveform Plot for M odel C-2, Case A l . l (VGO=Vmid, Pin=-7dBm , Vg=0.3 V)
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\iii Harm Gen via Output Conditions\a Output Load and
Bias\comp_model_plots_9_25_03\modeIC_2_caseAl_waveforms_pin_m_7_loadswp_9_25_03.fig
Figure 3.82 shows what happens when the reverse-breakdown transition is added in
(this constitutes model C_2). Once again, when the load resistance is below or equal to
RLoptA> the transistor remains in the saturation region and the response exhibited in the
output waveforms matches that o f model A. When the load becomes greater than RlcpLa!
it causes the device to enter the linear and reverse-breakdown regions o f operations.
Now, the drain-source voltage is limited approximately to the knee voltage (0<Vds<Vki)
on the low end and the reverse breakdown voltage (Vds « Vrbd) on the high side (see
Figure 3.82(e)). This causes clipping on both the low and high end o f the output voltage
R e p r o d u c e d with p e r m is s io n of t h e cop y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e r m is s io n .
198
wavefomi, and subsequent distortion o f output current. This distortion in the output
current can be clearly seen in Figure 3.83, which is an enlarged plot o f Figure 3.82(c).
0.03
C lipping w h en
0.025
V d s < Vki
0.02
r o .o i5
C lipping w fien
R,L > R ,LoptA
. . Iand
V d s > Vrbdl
0.01
R. <R.
L
0.005
LoptA
R,L=R,LoptA
R. >R.
L
LoptA
time (sec)
x 10
-1 0
Figure 3.83. Enlarged Plot o f Figure 3.82(c): Ids W aveform s for M odel C_2, Case A l . l
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\iii Harm Gen via Output Conditions\a Output Load and
Bias\comp_model_pIots_9_25_03\modeIC_2_caseAl_waveforms_pin_m_7_loadswp_partc_zDom_9_25_03.fig
This clipping reduces the amount of fundamental output power, but still creates a
significant amount o f third harmonic output as evident in Figure 3.76(c). Note in Figure
3.82(b), the gate-source voltage (V gs)plot, that an unusual distortion/clipping effect is
also exhibited in the gate-source voltage waveform and this will be discussed in Section
3.iii.a.l.ii below. This distortion in the gate-source voltage can be clearly seen in Figure
3.84, which is an enlarged plot o f Figure 3.82(b).
The Fourier harmonic components o f the waveforms in Figure 3.82(b), (c) and (e) are
shown in Figure 3.85. Figure 3.85 shows the effect o f varying the load resistance on the
generation o f harmonics at the input and output o f the transistor for model C_2.
R e p r o d u c e d with p e r m i s s io n of t h e cop y rig h t o w n e r. F u r th e r r e p ro d u c tio n prohibited w ith o u t p e rm is s io n .
199
x10
-10
D istortion d u e to R e v e r se B reak d ow n
wh^nRL>R|^p^
'
R. <R,
L
LoptA
R,=R,
L
LoptA
R|L^R|LoptA
.A
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0 . 1
0
0 .1
Vgs (V)
Figure 3.84. Enlarged Plot o f Figure 3.82(b): Vgs W aveform s for M odel C_2, Case A l . l
C:\Researcti\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\iii Harm Gen via Output Conditions\a Output Load and
Bias\comp_model_plots_9_25_03\modelC_2_caseAl_waveforms_pin_m_7_loadswp_partb_zoom_9_25_03.fig
Figure 3.85(a) shows the gate-source voltage harmonics corresponding to the
waveforms previously shown in Figure 3.82(b). Figure 3.85(a) confirms that when the
load resistance is greater than the optimum (R l> RLopt^)> feedback to the gate causes
distortion in Vgs. The figure shows that when Rl is greater than RLopt^! that the
fundamental component o f Vgs drops slightly and 2fo and 3fo components begin to rise.
Figure 3.85(b) shows the drain current harmonics corresponding to the waveforms
previously shown in Figure 3.82(c). The harmonic content of the drain current is linear
(with DC and fo content only) when the load resistance is smaller than ( R l = 5 0 ) or equal
to ( R l =160) the optimum load resistance. When the load resistance becomes larger ( R l
=250), drain current waveform is distorted (Figure 3.82(c)), causing the fo component to
drop and the 3fo component to arise. Figure 3.85(c) shows the drain-source voltage
harmonics corresponding to the waveforms previously shown in Figure 3.82(e). Similar
R e p r o d u c e d with p e r m i s s io n of t h e cop y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e rm is s io n .
200
to the drain current, the harmonic content o f the drain-source voltage is linear (with DC
and fo content only) when the load resistance is smaller than (Rl =50) or equal to (Rl
=160) the optimum load resistance. When the load resistance becomes larger ( R l =250),
drain-souree voltage waveform is distorted (Figure 3.82(e)), causing the third harmonic
to arise.
0 .3 5
I (a) d a te -S o iir c e
I
V d ltage
-----
0.3^^
^
0 .2 5
O)
TO
0 .0 1 4 r r
0
£
.0 1 2 '
I
t
0.01
__ - J.
11
2 ^ -0 .0 0 8
O)
ro
0 .2
g ,0 ,1 5
>
w 0 .0 0 6
0 .1
0 .0 0 4
0 .0 5
1---------- 1---------!
(c) Drain-Sc )u rce 1
I
V tiltage
(b) Drain C urrent
u>
♦
R^=50
A
R|^=160
■
R^=250
i k.
(/>
■D
>
<►
0.002
0
.
0
0
0
Freq(GHz^10®
1
0
Freq (GHz^ .,0 ®
Freq (GHz^ .,q9
Figure 3.85. Fourier Series Plot for M odel C-2, Case A l . l (VGO=Vmid, Pin=-7dBui, Vg=0.3 V)
C;\R esearch\l_B_l Undrstndng NL MechVB Stdy Idlzd MdlsMii Harm Gen via Output Conditions\a Output Load and
Bias\comp_model_plots_l l_26_03\modelC_2_caseA l_l_F S Plot_l l_26_03.fig
3. Hi. a. 1. it Summary o f the Effects o f the Load Resistance R l:
In an actual multiplier design, the impedance o f the output network (Zut) at each
harmonic can differ. The above results suggest that the optimum load for the desired
output harmonic would constrain the output voltage signal (at the desired output
harmonic) to the saturation region. However, the load for the unwanted harmonics (i.e.
the fundamental) may be utilized to cause the device to enter the linear and reverse-
R e p r o d u c e d with p e r m i s s io n of t h e co p y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e rm is s io n .
201
breakdown regions to create additional power at the desired harmonic. This possibility is
exemplified by the generation o f harmonics at the output when the load is raised above
RLopt;^ (Figure 3.76(b) and (c)). Although these clipping mechanisms in the Vds
waveform may be useful in generating extra output power, some caution must be taken.
When causing the drain voltage to hit reverse-breakdown, current is allowed to flow
through the gate-drain diode towards the gate. This feedback effect causes distortion in
the gate waveform (as shown on the gate waveform plot in Figure 3.82(b), and may prove
to be very problematic in terms o f circuit stability [3;50] (see page 412 in [50]).
Furthermore, as already stated, the use o f a single load resistance for all harmonics is not
representative o f an actual multiplier design. Extended studies o f variation in the load
resistance in combination with realistic output networks will be conducted in Section
3.iv.
3.iii.a.2. Variation in Drain Bias Level
Model A has a constant drain-source current (Ids) versus drain-source voltage (Vds)
relationship, and consequently is insensitive to variations in the drain-source bias voltage
(as shown in Figure 3.7). Flowever, the more complex models B and C_2, which exhibit
variation in the Ids(Vds) relationship, merit a study o f the effects o f changing the drain
bias level (Vdd). To facilitate such a study the following bias points were utilized as
outlined in Table 3.8:
•
Bias points near the knee voltage
o
Case A2 (VGO=Vmid, Vdd=Vki)
o
Case B2 (VGO=Vp, Vdd=Vki)
o
Case A2 (VGO=Vfwd, Vdd=Vki)
R e p r o d u c e d with p e r m i s s io n of t h e c o p y rig h t o w n e r . F u r th e r re p r o d u c tio n p rohib ited w ith o u t p e r m is s io n .
202
•
•
Bias points near the reverse-breakdown voltage
o
Case A3 (VGO=Vmid, Vdd=Vrbd)
o
Case B3 (VGO=Vp, Vdd=Vrbd)
o
Case C3 (VGO=Vfwd, Vdd=Vrbd)
Bias points midway
o
Case A l (VGO=Vmid, Vdd=Vddm,d)
o
Case B 1 (VGO=Vp, Vdd=Vddmid)
o
Case Cl (VGO=Vfwd, Vdd=Vddmid)
The study was conducted by simulating the conversion gain versus input power for all
9 bias cases (caseAl through C3 in Table 3.8), with a constant load of 50 ohms, for
models A, B and C_2.
As previously stated, the response o f model A is insensitive to variations in Vds. As a
result, for model A the value o f the drain bias (Vdd) cannot affect the device’s response.
Therefore the conversion gain response for cases A l, A2 and A3 are all equivalent and
correspond to the response previously shown in Figure 3.12 on page 87. This is true
because among all three cases (A l, A2 and A3) only the drain bias is changed and the
cases have the same gate bias value. Likewise, the responses for cases B l, B2 and B3 are
equivalent and were shown in Figure 3.17 on page 93. Finally, cases C l, C2 and C3 are
equivalent and were shown in Figure 3.22 on page 98.
The response for model B is not shown in the body o f this work. This is due to the
following reasons:
(1)
The response o f model A and B is exactly the same for cases A l, A3, B l, B3, Cl
and C3, since for each o f these cases the model is in the saturation region o f operation.
R e p r o d u c e d with p e r m i s s io n of t h e cop y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e rm is s io n .
203
The model remains in saturation because a small load (Rl =50 ohms) is utilized and the
drain-source voltage swing is relatively small.
(2)
The response o f model B and model C_2 (to be shown) are exactly the same for
cases A2, B2 and C2, since fo r each o f these cases the model operates in the linear or
saturation region only.
Due to the reasons described above, the effects o f varying the drain bias can be
characterized by comparison o f models A and C_2 only. For conversion gain plots o f
model B for these 9 cases (A l through C3), refer to Appendix B.ii.a.4 (page 494), Figure
B.27, Figure B.28 and Figure B.29.
The conversion gain responses o f cases A l through C3 for model C_2 are shown in
Figure 3.86, Figure 3.88 and Figure 3.90. Figure 3.86 is a comparison o f the conversion
gain response o f model C_2 for cases A l (where VGO=Vmid, Vdd=Vddmid, Rl ==50
ohms, and Pin is swept from -10 to 10 dBm), A2 (where VGO=Vmid, Vdd=Vki, Rl =50
ohms, and Pin is swept from -10 to 10 dBm) and A3 (where VGO=Vmid, Vdd=Vrbd, R l
=50 ohms, and Pin is swept from -10 to 10 dBm). Note that the response o f model A
(equivalent for all 3 cases), is included in the figure to facilitate comparison.
In Figure 3.86, the model A plot is denoted by the squares (■), and all the remaining
plots are for model C_2. The figure shows that for case A l, model C_2 has an equivalent
response to model A. This occurs since the device is constrained to the saturation region
by the small 50 ohm load.
R e p r o d u c e d with p e r m is s io n of t h e cop y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e r m is s io n .
204
20
20
(c)
(b)
15
15
1 0
1 0
—
pasefS
5
M o d e lC -2 '
I *S
0-10
I
0
^
-5
M o d e lC -^
M
I
i
N •
__L_\
0 - 1 0
O
C aseA 3
y
•
-2 0
\ \
’
CaseA2 '
+ ••••'
._MoldeLC-3_Vj___
I
!
I CaseAl '
-5
0
i ---------
-15 '
W)odel0 -2 ^
-10
5
5
Pin (dBm)
10
\!
\
-25 rM b ld e IA iiC -2 lV "
I <r30d^
-30
-10 -5
0
5 10
Pin (dBm)
M odelC -2, C a s e A l
M odelC -2, C a s e A 2
M od elC -2, C a s e A 3
M odelA , C a s e A l ,2,3
•
■
0
« -5
@)
O -1 0 ,
O
-15
-2 0
-25
-30.
-10
-5
0
5
10
Pin (dBm)
Figure 3.86. Conversion Gain vs Pin Response o f Models C_2 and Model A, for Cases A l, A2 and A3
C :\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\iii Harm Gen via Output Conditions\a Output Load and
Bias\comp_modeI_plots_9_25_03\modelC_2_caseAl_2_3_cgplot_wmdlA_9_29_03.fig
However, when model C_2 is biased at the knee voltage (case A2) the device
transitions between the linear and saturation regions. This response is shown in Figure
3.86 by the dashed curve (— ). A perusal o f this curve shows that with Pin increasing
from -10 dBm, the fundamental conversion gain decreases (Figure 3.86(a)) as well as the
3fo conversion gain (Figure 3.86(c)). As well as the reduction in the fundamental and
third harmonic output CG (Figure 3.86(a) and (c)), biasing at the knee (case A2) created
second harmonic conversion gain (Figure 3.86(b)) in comparison with model A.
When model C_2 is biased at the reverse-breakdown voltage (case A3) the device
transitions between the saturation and reverse-breakdown regions. This is shown also to
reduce the fundamental and third harmonic output CG (Figure 3.86(a) and (c)) while
creating second harmonic output CG (Figure 3.86(b)) where none was previously present.
R e p r o d u c e d with p e r m i s s io n of t h e co p y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e rm is s io n .
205
As shown in Figure 3.86(b), the maximum 2fo conversion gain points for case A2 and A3
occur for an input power o f about -7 dBm.
The waveform plots for cases A2.1 (VGO=Vmid, Vdd=Vki, Vg=|Vp|/2, Pin = -7dBm)
and A3.1 (VGO=Vmid, Vdd=Vrbd, Vg=]Vpl/2, Pin = -7dBm) are shown in Figure 3.87.
0.03
(a)
^ 0 .0 2
<
W
)
-
-----
0.01
-
5 -0.3 -0.1
xIO
0.1
.ioVgs (V)
0
)
—
^
t?me (sec)
X
0
1 2 3 4
_ioVds (V)
x IO
10
0
CaseA2.1
Case A3.1
— T"
' o 2
0.01
—
(e);
I
0 -2
1
5
(U
^ 4
VI
^4
I
-0.7 -0.5 -0.3 -0.1
Vgs (V)
0.1
0
1
2 3 4
Vds (V)
5
Figure 3.87. W aveform Plot for M odel C_2, Cases A2.1 and A3.1 (R l = 50 ohm s, Pin = -7dBm)
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\iii Harm Gen via Output Conditions\a Output Load and
Bias\comp_model_plots_2_25_03\caseA2_A3_modelC_2_CGplot_2_28_03.fig
As before. Figure 3.87(a) shows the DC Ids versus Vgs, Figure 3.87(b) shows the
input gate-source voltage waveforms, and Figure 3.87(c) shows the corresponding drainsource current waveforms. Figure 3.87(d) now illustrates the load-lines for the 2 biases
(Case A2.1 and A3.1) superimposed on the DC Ids versus Vds curves. Finally, Figure
3.87(e) shows the drain-source voltage waveforms. Figure 3.87(e) shows the output
waveforms for both cases have a relatively small voltage swing. However, the
waveforms do resemble half-wave rectified sinusoidal waves, which have been shown in
Section 3.ii.a.5 to contain significant second harmonic output levels. These two cases
R e p r o d u c e d with p e r m i s s io n of t h e cop y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e rm is s io n .
206
represent interesting possibilities as potential bias points for frequency doublers.
Unfortunately, case A3 may not be practical since it requires a bias near reversebreakdown. The use o f these bias points in a more advaneed multiplier eonfiguration
using an output reflector network will be explored in Section B.iii.c.
20
2 0
(c)
(b)
15
15
10
10
““
5
5
•
■
-10
-5
M od elC -2, C a s e A l
M odelC -2, C a s e A 2
M odelC -2, C a s e A 3
M odelA, All C as e s
I 0
^
CD- 1 0
-5
CD-10
O
-15
'A
-20
i \
■
1
\
-25
s
.
\
\
-10
-5
0
5
Pin (dBm)
10
-30
-10
-5
0
5
Pin (dBm)
i
10
0
5
10
Pin (dBm)
Figure 3.88. Conversion Gain vs Pin Response o f M odel C_2 and Model A, for Cases B l, B2 and B3
C'.\Research\l_B_l Undrstndng NL Mech\B Stdy Idlzd MdlsMii Harm Gen via Output Conditions\a Output Load and
Bias\comp_model_plots_9_25_03\ modelC_2_caseBl_2_3_cgplot_wmdlA_9_29_03.fig
Figure 3.88 is a comparison o f the response o f model C_2 for cases B l (where
VGO=Vp, Vdd=Vddmid, Rl =50 ohms, and Pin is swept from -10 to 10 dBm), B2 (where
VGO=Vp, Vdd=Vki, Rl =50 ohms, and Pin is swept from -10 to 10 dBm) and B3 (where
VGO=Vp, Vdd=Vrbd, Rl =50 ohms, and Pin is swept from -10 to 10 dBm). Again, the
response o f model A (equivalent for all three cases) is included in the figure.
The response o f model C_2 closely matches the response o f model A for case B 1.
Notice for this case, however, that for larger input power levels (Pin>7dBm) the 2fo and
R e p r o d u c e d with p e r m i s s io n of t h e cop y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e rm is s io n .
207
3fo conversion gain o f model C_2 deviates from the response o f model A. This fact is
initially disconcerting since for case A l, the small load resistance kept model C_2
operating only in the saturation region. For this case, however, the large input power
level and large (negative) gate bias causes a large gate voltage minimum to be reached.
This negative gate voltage causes a negative enough gate-drain voltage for the device to
enter the reverse-breakdown region. This can be seen by Equation ( 3.35 ) which
describes the gate-drain voltage.
Vgd{t)^Vgs{t)-Vds{t)
( . )
3
3 5
Figure 3.89 shows a comparison waveform plot o f models C_2 and A for case B l and
an input power o f 10 dBm. Figure 3.89(a) shows the DC Ids versus Vgs response o f the
models at a Vds value o f 2.5V. As the figure shows, when the overall gate drain voltage
reaches the point o f reverse breakdown (VoDrbd—S.lV, corresponding to Vds=2.5V and
Vgs=-2.6V) the drain current (for model C_2) begins quickly increasing. As shown in
Figure 3.89(b), when the input power level is brought up to 10 dBm, the gate voltage is
driven down to the point o f reverse breakdown and model C_2 enters the reverse
breakdown region. The effects o f this are exhibited in Figure 3.89(c) and (e) which show
the drain current and voltage waveforms respectively. As the figures show, when the
gate-source voltage signal drives the device into the reverse-breakdown region (shown
from time a to b in the figure) the drain current is driven up from zero to a local
maximum and back down again. This distortion in the response of model C_2 changes
the output harmonic content as compared to model A as exhibited in Figure 3.88.
R e p r o d u c e d with p e r m i s s io n of t h e co p y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e rm is s io n .
208
0.03
0.03
(a)
-
/
0.02
■(0U
0.01
9
-
2
-
1
0.02
/
/
u
0
U
T
3)
/
2
4
time (sec)
\
0.01
0
6
0
1
u
------ ModelA
....... ModelC-2
1
^
-1
Vgs (V)
4
5
(e)
,|4
1
^
-2
3
x 1 0 ’’'°
1____ __
o2
<D
6
2
Vds (V)
[
-2.9
:
\
1
x 1 0 '^°
(b)
(d):
0.02
0.01
Vgs (V)
0
0.03
(c)
j
-I
0
o2
(U
—
\
i
m
S> A
t '
6
---
- - - - i
0
1
2
3
Vds (V)
4
5
Figure 3.89. W aveform Comparison o f M odel C_2 and M odel A for Case B l (VGO=Vp,
Vdd=Vddmid), Pin=10dBm
Returning to the other cases (B2 and B3) exhibited in Figure 3.88, these cases show
significant deviation in the response o f model A. As shown in Figure 3.88(a) and (b),
both cases show reduced fo and 2 fo conversion gain levels over most o f the input power
range. The 3fo conversion gain shows an improved 3fo level for an input power range o f
-10 to 0 dBm for case B3. Ftowever, although the improvement is significant the 3fo
conversion gain is still fairly low (<-lGdB).
Figure 3.90 is a comparison o f the conversion gain versus input power response o f
model C_ 2 and model A for cases Cl (where VGO=Vfwd, Vdd=Vddmid, R l =50 ohms,
and Pin is swept from -10 to 10 dBm), C2 (where VGO=Vfwd, Vdd=Vki, R l =50 ohms,
and Pin is swept from -10 to 10 dBm) and C3 (where VGO=Vfwd, Vdd=Vrbd, R l =50
ohms, and Pin is swept from -10 to 10 dBm).
R e p r o d u c e d with p e r m i s s io n of t h e cop y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e rm is s io n .
209
20
20
(a)
20
(c) ;
(b)
15
«—
——
•
■
10
5•
CQ
T3
0
sHv
M od elC -2, C a s e C I
M od elC -2, C a s e C 2
M od elC -2, C a s e C S
M odelA, C a s e C I ,2,3
mmmm^
V‘ •V'
*
%^
1 «\
■2 -5
0-10
;
• s
1• • \ <
1 ^
; •
'
1
1
1
’
i
0
5
1
O
-15
'
-20
-25
-1 0
-5
Pin (dBm)
10
-10
-5
0
5
10
Pin (dBm)
-10
-5
0
5
Pin (dBm)
Figure 3.90. Conversion Gain vs Pin Response o f Models C_2 and M odel A, for Cases C l, C2 and C3
C:\Research\l _B _l Undrstndng NL Mech\B Stdy Idlzd Mdls\iii Harm Gen via Output Conditions\a Output Load and
Bias\comp_modelj)lots_9_25_03\modelC_2_caseCl_2_3_cgplot_wmdlA_9_29_03.fig
The figure shows that for case Cl model C_2 operates in the saturation region and has
an equivalent response to model A. When the drain bias is set to the knee voltage (case
C2), however, the fo, 2fo and 3fo conversion gain is reduced significantly as seen in
Figure 3.90(a), (b) and (c) respectively. Biasing near reverse-breakdown (case C3) also
leads to reduced fo and 2fo conversion gain (Figure 3.90(a) and (b)), but shows 3fo
conversion gain comparable to model A (Figure 3.90(c)).
3.iii.a.3. Summary of Output Load and Bias Study
Varying the load resistance on the output can create significant effects in models
containing the knee and reverse-breakdown regions. The use of a load larger than the
standard optimum tends to reduce the amount o f fundamental output power, but shows
significant second and third harmonic output power levels (Figure 3.76).
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210
Although a typical “optimum” drain bias occurs midway between the knee and
reverse-breakdown transition regions, bias points around the knee and reverse-breakdown
regions have shown to produce significant amounts o f 2 fo output power.
By sweeping the drain bias and load values for several models, some important
possible output load and bias combinations have been identified. These are specifieally;
o
An optimum load resistance (Rl = RLopt^=160ohms) for conversion gain at the
fundamental frequency,
o
A bias point at the knee voltage (Vdd=Vki) exhibiting significant 2fo CG (case
A2.1).
o
A bias point at the reverse breakdown voltage (Vdd=Vrbd) exhibiting significant
2foC G (case A3.1).
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5.111.b. Output Bias Network
3.111.b.l. Basic Considerations
Similarly to the input case (Section S.ii.c), the choice o f network used in the drain
biasing o f the transistor can have unforeseen consequences. As was the case for the gate
circuit, unexpected shifts will occur in the drain output waveforms unless Rdd and R
l,
shown in M2 in Figure 3.91 below, are equal. This phenomenon can be explained in
more detail through use o f the idealized model (model A), utilizing the circuit
configuration shown in Figure 3.91.
M2
M1
Vds
R dc=
V gs
50Q
R l=
R d d = S w ep t
50Q
VGO
Figure 3.91. Circuit Configuration for Output Bias N etw ork Study
C:\Research\Figures\jj m lm 2 output_bias_c BD ai
The figure shows the same basic circuit schematic o f Figure 3.4 (used for the study o f
the gate bias network) with a variable resistance in the DC output path (Rdd=swept).
This section presents an analysis o f the effects o f changing the value o f this DC output
bias resistance.
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212
3.iii.b.2. Theoretical Calculations
The ideal model (model A) operates only in the saturation region where Ids is a
function o f Vgs only (as explained in Section 3.ii.a). Therefore the signal fed into this
output circuit can be viewed as a current source (Ids) that is completely independent o f
the output circuit. In other words, Ids is not a function o f Vds and therefore an output
voltage Vds generated by the output circuit will not change the operation o f Ids. The
output current waveform will consist o f an AC part (IdsAc) and a DC part (Idsoc) as
shown on in the example waveform in Figure 3.92.
x10
Ids
Ids
Ids,
'DC
Ids,DC
^>*^<><KM<KXK>iOOOOm>
-Ids,DC
180
270
360
theta (deg)
450
540
630
720
Figure 3.92. Exam ple Ids W aveform
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd MdlsMii Harm Gen via Output ConditionsVc Output Bias Network\output
(old)\exampleidswaveform.fig
Due to the action o f the choke and DC block on the output o f the circuit, the AC
component o f the current (IdsAc) will flow through the AC path and cause a voltage drop
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213
across the AC load resistance Rl- Note that Wsac will have a zero DC value. This is
shown on the detail view (from Figure 3.91) o f the output network shown in Figure 3.93.
Ids AC
Ids
iL
Vds
Ids
R dd=
Sw ept
Vdd
Figure 3.93. Detail V iew o f Output Circuit from Figure 3.91
C:\Research\Figures\jj m !m 2 output_bias_c BDzoomed.ai
The corresponding output voltage across R l is the AC component o f the drain-source
output voltage (VdsAc)- It was previously described in Section 3.ii.a.2 as part o f
Equation ( 3.9 ), but is rewritten here in a different form as Equation ( 3.36 ):
V d s ^ c = -I d S A C * R L
( 3 .3 6 )
The DC component o f the current (Idsoc) will flow through the DC path and cause a
voltage drop across the DC path resistance Rdd. This voltage drop plus the value o f the
DC bias voltage Vdd is the DC component o f the drain-source output voltage (Vdsoc)- It
is written as:
Vds^^ = Vdd - Idsly, * Rdd
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( 3 .3 7 )
214
Due to the action of the bias-T circuit, the overall drain-source voltage can be obtained
by combining the voltage occurring across the DC path (VdsDc) and the voltage occurring
across the AC path (VdsAc) gives the total drain source voltage;
Vds = V ds^ + Vds^^ = Vdd - Idsj^. * R dd - Ids^^ *
( 3.38 )
Figure 3.94 shows the “calculated” Vds waveform (using Equation ( 3.38 ))
corresponding to the input Ids waveform of Figure 3.92.
Vds.
Vds,
DC
Vds ,
- e - Vds
Vds^^
0.5
Vds
A C m ax
Vds
A C m in
-0.5
180
270
360
450
theta (deg)
540
630
720
Figure 3.94. Exam ple Calculated VAs W aveform Using (Eq ( 3.38 ))
C :\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\iii Harm Gen via Output Conditions\c Output Bias Network\output
(oId)\ examplevdswaveform.fig
If Ids is a waveform such as the one in Figure 3.92, with peak current Ip, minimum
current 0, and known DC level Idsoc, then the maximum AC current component is:
Ids AC^ —I p - Ids D C
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( 3.39 )
215
And the minimum AC current component is:
These values are indicated in the plots o f Figure 3.92. Given these extrema, the
extrema o f the AC voltage VdsAc can be calculated (note that a maximum current
corresponds to a minimum voltage due to the negative sign in Equation ( 3.37 )):
= -Ids^c^
Vds^r
- ( - I p + Ids^c )
= -Ids^r^^ •R^ = Ids^c
( 3.41)
( 3.42 )
From Equations (3.41) and ( 3.42 ) the extrema o f the overall voltage Vds can be
calculated;
^ds^^ = VdSjjf^ + V d s
=
Vdd + IdSj^Q (R^ — Rdd^
( 3.43 >
= ^ ‘ls ^ + VdSjc^ = Ydd-Ip -R ^ +Id s^ (R i^-R dd )
= ^ d ^ ^ -Ip -R L
It is clear from Equations ( 3.43 ) and ( 3.44 ) that the extrema of the Vds
waveform will be a function of the AC load resistance R l and the resistance in the
DC path Rdd. These equations also show that the extrema will also vary with the DC
current level Idsoc- The implication o f this is that as Wsdc is increased (which can
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216
increase with increases in the DC or AC gate input voltage), the DC voltage level, and
resulting extrema can shift significantly. For this simple transistor model it is o f little
concern, since the transistor only has one region o f operation (saturation). However,
when considering more complex regions o f operation such as the linear region or the
breakdown region, the amount o f DC drain voltage shifting can be quite significant. If,
for example, the transistor made a transition between the linear and saturation regions at
the knee voltage (Vds = Vki) an unaccounted for DC voltage shift could change the point
in the waveform cycle where the transition was made.
A typical microwave circuit design configuration utilizes a 50 ohm AC load resistance
(R l = 50 ohms) and a very small resistance in the DC path (Rdd = 0). This simplifies the
equation for the extrema to:
Vds„„ = Vdd + Ids„c ' A
= y d s„ „ , - I p - R ,
<
( 3 .4 6 )
For the case when the resistance in the output DC bias path is zero (Rdd = 0), the DC
voltage level is constant. Looking at Equation ( 3.37 ) shows that Ydsoc = Vdd, which is
independent o f the DC current level. However, although the DC voltage is independent
o f the DC current level. Equations ( 3.45 ) and ( 3.46 ) show that the extrema o f the
overall output voltage waveform (Vds) are not. Thus, for varying levels o f Idsoc, the
extrema o f the output voltage waveform will vary.
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>
217
A possible solution to negate the effect o f varying extrema would be to set the
resistance in the output DC bias path equal to the AC load resistance (Rdd = R l). Then
the equation for the extrema would simplify to:
Vds^=Vdd
F<iSmin ”
^
^
For this case, the extrema o f the voltage waveform are independent o f Idsoc, even
though the DC voltage level is not. Note that the impact o f variation in the extrema and
the practicality o f utilizing a DC drain bias resistance equal to R l (Rdd= R l) will be
discussed in Section S.iii.b.5.
3.iii.b.3. Analysis of Theoretical Calculations
To demonstrate the phenomenon described in the previous section, a theoretical
calculation o f two Vds waveforms corresponding to the Ids waveforms shown in case
B l.l (VGO=Vp, Vdd=Vddmid, Pin=-7dBm, Vg=|Vp|/2) and case B1.2 (VGO=Vp,
Vdd=Vddmid, Pin=-ldBm, Vg=|Vp|) was conducted. The calculation utilized Equations (
3.36 ) and ( 3.37 ) to calculate the Vds waveform given an arbitrary Ids waveform using
Matlab, and is shown in Appendix B.ii.b.l (page 496). The circuit was also implemented
in ADS, using the ideal transistor in the multiplier configuration given in Figure 3.91 to
find the simulated Vds waveforms for the cases (B l.l and B 1.2). A schematic o f the
ADS simulation, which for this study was the same as the ADS setup in Section 3.ii.a, is
shown in Appendix B.i.a.4 (page 463).
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218
The Ids and Vds waveforms for cases B l.l and B1.2 were calculated and simulated
for different DC drain bias resistance values. Figure 3.95 shows the Ids and Vds
waveforms resulting when the drain bias resistance is equal to approximately zero
(Rdd=0.1).
0.025
0.02
0.015
CO
■D
0.01
•
0.005 •
o
□
T im e ( s e c )
^ . | q-
CaseB1.1
Sim C aseB 1.2
Calc, CaseB1.1
Calc, C a s e B I .2
T im e ( s e c )
^ . , q-
Figure 3.95. Ids and Vds W aveforms for Case B l .l (VGO=Vp, Pin=-7 dBm, Vg=lVp|/2) and Case B1.2
(VGO=Vp, P in=-ldB m , Vg=|Vp|), when R l = 50 ohms and Rdd = 0.1 ohms
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The figure shows an interesting result which illustrates the implications o f the
relationships defined by Equations ( 3.45 ) and ( 3.46 ). At first glance, the expected
maximum drain-source voltage would be equal to Vdd=Vddmid=2.5 V, where the drain
current was equal to zero (shown between times t=a and t=b in Figure 3.95(a)). Then as
the drain-source current turned on and drove up to Ip (shown at time t=c in Figure 3.95
(a)), the drain-source voltage would be expected to drop to a minimum which
corresponded to the DC drain bias voltage minus the voltage drop across the load resistor
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219
(Vdd-Ip*
R
l
).
However, based on Equation ( 3.45 ) the maximum drain voltage is larger
than Vdd by an amount equal to
M
sd c
*
Rl, and as seen in Figure 3.95(b) this is shown to
agree with simulation, reaching 2.7V for case B l.l and 2.9V for case B1.2. This occurs
because the small drain bias resistance (Rdd~0) forces the DC level o f the drain voltage
to be equal to the bias voltage Vdd (Vdd=2.5V). This is shown in Equation ( 3.37 ) when
Rdd is set equal to zero.
Figure 3.96 shows the Ids and Vds waveforms resulting for cases B l.l and B1.2 when
Rdd is equal to the load resistance (Rdd= Rl =50 ohms).
0.025
3
1
(b )
I
o
o
0.02
-
S im ,C a s e B I.1
Sim, C a s e B I .2
Calc, C a s e B I.1
Calc, C a s e B I.2
2 .5
Jl
0.015
•1
a/ i»
>
.
in
■D
0.01
T3
>
2 f 1
1 1
f
1
1 .5
0.005
-------
ft P
1r
2
4
T im e ( s e c )
6
xlO'^°
1 ----------- 1
0
T im e ( s e c )
^ . jq-10
Figure 3.96. Ids and Vds W aveform s for R l = Rdd = SOohms, Pin—10, -5 and 0 dBm (Corresponding
to Idsj, Ids 2 and Idss)
C :\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\iii Harm Gen via Output ConditionsVc Output Bias
Network\modelA_Rdd_swps_9_29_03\modeIA_caseBl_Rdd_50_IdVd_plot_9_30_03.fig
The figure shows that when the drain bias resistor is set equal to the load resistance,
the “expected” drain-source voltage waveform with a maximum occurring at the bias
voltage Vdd equal to 2.5V is achieved. As previously demonstrated by Equations ( 3.47 )
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220
and ( 3.48 ), these “expected” maximum and minimum drain-source voltages are only
achieved when Rdd is set equal to the load Rl. This occurs because the 50 ohm drain
bias resistance allows the DC drain bias level to shift according to Equation (3 .3 7 ), and
causes the drain-source voltage maximum to be independent o f the drain current level
according to Equation ( 3.47 ).
3.iii.b.4. Compensation Technique
Although it is clear from the above analysis that the “expected” drain-source voltage
extrema are obtained when Rdd is equal to the load resistance Rl, the phenomenon brings
up some problems. A drain bias resistance o f 50 ohms can easily be implemented in a
multiplier circuit. However, when Rdd is equal to 50 ohms it will have a large DC
voltage drop across it, requiring a large bias voltage Vdd to achieve a given drain bias
level. For example, if the gate is biased such that the DC drain current Idsoc is 12.5mA,
Equation ( 3.37 ) shows that the bias voltage Vdd will have to be set to 3.125 volts to
achieve a DC drain voltage o f 2.5V. This results in a disastrous effect on the DC to RF
efficiency o f the transistor. Similar to the case for the gate bias resistance, the
“expected” waveforms which occur when Rdd is equal to Rl (50 ohms) can be
achieved by setting Rdd equal to zero and adjusting the DC bias level. Figure 3.97
shows the simulated drain-source voltage level versus input power utilizing several
values o f drain bias resistance Rdd with a 50 ohm load Rl. Note that at each Rdd value,
the same DC bias voltage (Vdd=2.5V) is used in the ADS simulation. As the figure
shows, when Rdd is equal to 50 ohms, the DC drain-source voltage varies from 2.35V at
an input power o f -10 dBm to 2.1V at an input power o f -IdBm. This shift is expected as
shown by Equation ( 3.37 ). When Rdd is changed, the DC drain-source voltage level
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221
shifts by different amounts. As Rdd is reduced to almost zero (Rdd=0.1), the DC drainsource voltage level remains at the input drain-source bias level Vdd. Utilizing the same
technique as that presented for the gate bias, Rdd can be set to a practical value o f around
0.1 ohms and the drain bias level (Vdd) can be shifted {for each input pow er level)
according to the amount o f shift shown when Rdd was equal to 50 ohms (as shown in
Figure 3.97).
2.7
2 .5
Compensation
needed
when
Rdd=0.1
o
Q
CO
> 2.1
•
-
R d d = 0.1
Rdd=10
Rdd = 50
R d d = 100
-10
Pin (d B m )
Figure 3.97. Shift in DC Drain Voltage Level W ith Increasing Inpnt Power, Case B l (VGO=Vp,
Vdd=Vdd„id)
C :\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\iii Harm Gen via Output Conditions\c Output Bias
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Figure 3.98 shows the waveforms resulting from a re-simulation o f case B1.2
(VGO=Vp,Vdd=Vddmid, Pin=-ldBm, Vg=|Vp|) where Rdd has been set to
0.1
ohms and
the above bias adjustment was conducted. The figure also shows the original waveforms
when Rdd was equal to 50 ohms. As shown, the responses correspond well. This
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222
shows that, rather than utilizing a 50 ohm DC drain bias resistance, a practical
(Rdd=0.1ohms) resistance can be utilized and the drain bias level Vdd can be
adjusted to achieve drain-source waveforms with the “expected” minimum and
maximum values.
o
Rdd=50
R d d = 0 . 1 w /b ias adjustment
2 .5
T3
T im e ( s e c )
x10
-10
Figure 3.98. Drain Source W aveform s for C aseB l.2 (VGO=Vp, Vdd=Vddmi<n P in=-ldB m ,V g=|V p|),
Showing Bias Compensation Technique
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3.iii.b.5. Summary of Output Bias Network Considerations
The implications o f the phenomenon shown in Section 3.iii.b.3 are several. First,
using a common microwave biasing configuration with a small DC drain bias resistance
(Rdd - 0) warrants caution. A small resistance in the DC path forces a constant DC
voltage level at the drain, which can cause the extrema o f the output voltage waveform to
shift to an unexpected level. This shift, which in the example o f Figure 3.95 is up to
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223
around 0.35 V, can force the device out o f the saturation region in an actual device,
causing unexpected harmonic output. Second, the shifts can be counter-acted by
inserting a resistance in the DC path which is equal to the load resistance, as shown in
Figure 3.96. Flowever, there is a huge drawback to this procedure because the voltage
drop across the resistance Rdd requires a much larger DC voltage level. This has a
ruinous effect on the devices DC-RF efficiency. Another option does exist however, and
that is to use the standard configuration (Rdd~0), and give slight adjustments to the DC
bias to keep the drain voltage swing within the desired limits. This will allow the desired
swing limits to be maintained without causing a huge voltage drop in the DC drain bias
path. In a practical sense, the output current waveform may be sinusoidal on the overall
output. In this situation, the extrema o f the output voltage waveform are still dependent
on Idsoc, but the DC current level will show little change as the magnitude o f the output
current is varied. Thus, in a full multiplier design, the choice o f Rdd will be much less o f
a concern.
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224
3.111.c. n*fo Harmonic Output Reflection
3.111.c.l. Basic Considerations
Similar to the use o f a reflector network on the input o f the transistor (as discussed in
Section 3.ii.d) a network (M2), which reflects the drain output power at a harmonic n*fo
back into the transistor, may also be utilized to manipulate conversion gain. As shown in
Figure 3.11, Figure 3.16 and Figure 3.21 in Section 3.ii.d, the transistor outputs large
amounts o f power at the first three harmonic frequencies. The unwanted output
frequencies (such as fo and 3fo in a frequency doubler) are commonly filtered out with a
bandpass filter [6 ]. However, it has been shown that the use o f a “reflector network” at
an unwanted frequency n*fo could be used to enhance the output power at a desired
frequency m*fo [23;35;47;58]. Figure 3.99 shows the circuit configuration utilizing a
“reflector network” to reflect n*fo output power back into the transistor.
M1
M2
^^Loutpfo
Vds
Vgs
Rdc=50Q
zo=
i
Rgen
—-
3 —
^
n*fo
Reflctr
Elemnt
VGO
_i
Vdd
Figure 3.99. Circuit Configuration for nfo Output Reflection
C:\research\figures\jj m lm 2 output_refl_d BD.ai
As shown in Figure 3.99, a n*fo reflector element which reflects power at a chosen
harmonic n*fo is placed on the output o f the transistor. A 50 ohm transmission line (ZO
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225
= R-gen = 50 ohms) is inserted between the nfo reflector element and the output o f the
transistor. Figure 3.100 shows a detailed view o f the output circuit shown in Figure 3.99
as well as a detailed view o f the transistor’s output components.
Figure 3.100 illustrates how the network (M2 in Figure 3.99) is used to generate
desirable harmonic output.
ZM 2
M2
Feedback
to input
nfo
Drain
m*fo generation
V ds(
R |_ = 5 0 Q
n*fo
Reflctr
Elemnt
Ids
S o u r ce
=
- Vdd
Figure 3.100. Detail V iew o f Output Circuit from Figure 3.99
C:\research\figures\jj m l m2 o u tp u tr e f ld BDzoomed3.ai
It should be noted that the output current generator for the FET/HEMT device used in
Figure 3.99 is represented as a current generator - shunt nonlinear conductance
combination [3;50] (see page 35 in [50]). Following[3;50], the output current function is
separated into a (small-signal) gate-source voltage dependent drain-source current
generator and a (small-signal) drain-source voltage dependent output conductance (gd).
This is done by conducting a Taylor Series expansion on the output current function
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226
around a specific bias point, and dropping the higher order terms*. The calculated output
conductance will vary non-linearly with changes in the bias point. An example o f such
nonlinear variation is exhibited in Figure 2.19 (on page 49), which shows the measured
output conductance o f an actual PHEMT, as well as the simulated response o f the
practical device model (of Figure 2.14, page 40). Figure 2.19 shows that the output
conductance (ga) varies non-linearly with changes in the gate bias (VGO=Vgs) and drain
bias (Vdd=Vds).
The n*fo reflector element is used to exploit the nonlinearity at the transistor’s output
by reflecting the n*fo power generated by the transistor back into the device. The
interaction o f this reflected n*fo power with the nonlinear output conductance can
directly generate additional power at a desired output harmonic m*fo. The reflected n*fo
power may also mix with another harmonic present in the output to create additional
m*fo generation. Furthermore, the reflected n*fo signal may also provide beneficial
feedback to the input o f the transistor which can be manipulated to generate additional
output power at m*fo. This feedback typically occurs when the reflected n*fo signal
causes reverse-breakdown o f the gate-drain diode o f the transistor.
By varying the length o f the transmission line Loutnfo, the phase o f the reflected
signal at n*fo is varied. Variation in the phase o f this reflected signal at n*fo can then be
used to vary the way the n*fo power interacts with the nonlinear output conductance o f
the transistor. The variation in phase can also determine the magnitude and phase o f
feedback power, if any, provided back to the transistor gate. These changes, in turn, can
change the amount o f overall output power at the desired harmonic m*fo. The effects
* N o te that this m eth od is h ig h ly approxim ate. It a ssu m es a sm a ll-sig n a l input v o lta g e and a w e a k ly
n on lin ear outp ut current fu n ction (as d escrib ed in [3]). H o w ev er, it p rovides a b a sic illustration o f the fact
that there are sig n ifica n t n on lin ear m ech an ism s occurring at the output o f a transistor.
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Ill
caused by varying Loutnfo can thus he used to maximize the output conversion gain or
output pow er level at the desired harmonic m*fo at the drain.
From another perspective, the n*fo output reflector maximizes the CG or output
power by presenting a specific load at the transistor output
Varying the offset
length Loutnfo causes variation in the load and the corresponding load-line trajectory.
LFtilizing this load-line variation, output waveforms which give a maximum CG or output
power can be obtained.
The use o f a reflector at the fundamental frequency (represented by a reflector element
with n = 1 in Figure 3.99) is o f primary concern since the largest amount o f power in the
drain output occurs at the fundamental frequency. An fo reflector element was
implemented by using a series LC short circuit, as shown in Figure 3.99. The circuit was
designed using the same methods described in Section 3.ii.d to give a high-Q short at the
fundamental frequency. Figure 3.101 shows the 821 magnitude response o f the LC short
circuit.
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228
CD
T3
W
2 .8 5
2 .9
3 .0 5
2 .9 5
3 .1 5
Freq (GHz)
3.2
x10'
9
Figure 3.101. Frequency Response o f Fundamental Frequency (fo = 3 G H z) LC Short Circuit
C :\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd MdlsMii Harm Gen via Output Conditions\d Output nfo Harm Refl\3GHz Refl
Des 3_4_03\ 3GHz_harm_refl_plot_7_4_03.fig
As the figure shows, the LC circuit provides a high-Q short circuit at the fundamental
frequency (3 GHz). By providing an fo short circuit, the circuit will reflect all o f the
transistor output power at the fundamental frequency. A section o f transmission line was
then inserted in-between the fundamental short and the drain o f the transistor, as shown
in Figure 3.99. The effects o f variation in the length o f transmission line Loutfo on the
conversion gain response were characterized using ADS simulation o f model A and
model C_2. The ADS schematic for the simulations is shown in Appendix B.ii.c.l (page
497).
The effects o f varying the phase o f the reflected signal (by varying Loutfo) were
studied for several input signal and bias levels corresponding to cases A l, B l, C l, A2,
and A3 o f Section 3.iii.a. These cases were defined in Table 3.8 on page 184 and in the
ensuing paragraphs below. The results o f these simulations are presented below.
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229
3.iii.c.2. Case A l (VGO=Vmid, Vdd=Vdd„id)
Basic Considerations
Model A
The first case tested for transistor model A was case A l, which as previously
described represents a gate bias midway between pinchoff and the forward conduction
voltage (VG0=Vmid=-0.3V) and a drain bias midway between the linear (Vki) and
reverse-breakdown (Vrbd) regions (Vdd=Vddmid= 2.5V). Using an output reflector
element at the fundamental frequency, the conversion gain at the first three harmonics
was simulated versus the transmission line length Loutnfo (where n = l) for several
different input power levels. Figure 3.102 shows the third harmonic conversion gain
versus transmission line length (Loutfo), for model A.
-4
1--
"'
1
1
1
1
1
1
-5
-6
-----------
-7 ------m
■O
-8
£
CO
(§) -9
O
-10
------ Pin = -5dBm
"" — Pin = OdBm
....... Pin = 5dBm
---
-11
-12
------- —^------- ...........
-13 ______ 1...... ....
20
100
0
40
60
80
Lout^^ (Deg)
---------... — 1
120
140
160
180
Figure 3 .1 0 2 .3fo Conversion Gain vs. fo Output Reflector Phase Length for M odel A, Case A l
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\iii Harm Gen via Output Conditions\d Output nfo Harm
Refl\comparison_plots_3_5_03\modelA_caseA_CG3fo_vs_Lfo_3_5_03.fig
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230
As discussed in Section 3.ii.a.3, the most basic model (model A) has a constant Ids
versus Vds relationship. Since Ids is independent o f Vds, the use o f the fo reflector does
not contribute to the output power levels at other harmonics. This is evident by Figure
3.102.
More Complex Models
The more complex models (model B and C_2), previously shown in Section 3.iii.a,
have a nonlinear Ids versus Vds response as previously shown in Figure 3.73 and Figure
3.74. O f particular interest is model C_2, which includes both the linear region and the
reverse-breakdown region (Figure 3.74). Model C_2 is a device model which has a more
realistic drain-current response which is a nonlinear function o f the drain-source voltage.
Specifically, the device becomes nonlinear as the drain-source voltage reaches the knee
voltage and reverse breakdown voltage, thereby leaving the saturation region o f
operation. Therefore, extra nonlinear output power at a desired harmonic (m*fo) can be
created by utilizing the fo reflector network. As discussed above, the extra harmonic
power can occur through interaction o f the reflected fo power with the nonlinear output
conductance as well as by feedback o f the fo power to the gate. For model C_2 this
nonlinear output conductance consists o f sharp transitions between the linear, saturation
and reverse-breakdown regions. This nonlinear output conductance is shown in Figure
3.103.
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231
0.09
0.08
R e v e r s e B b R e g io n
0.07
0.06
E
O 0.05
Llm lar R e g io n
S atu ration R eg io n
0.02
0.01
0.5
2.5
3
Vds (V)
3.5
4.5
5.5
Figure 3.103. Output Conductance vs Drain Source Voltage o f M odel C_2: V G 0—0.3V
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\iii Harm Gen via Output Conditions\d Output nfo Harm
Refl\modetC_2_newlook_10_8_03\modelC_2_DC_gd_vds_plot_ll_16_03.fig
The figure shows that, within each region o f operation (linear, saturation, reversebreakdown) the conductance is constant. However, if the load presented at the output
causes the device to make transitions between the regions, the response can become
highly nonlinear. As such, model C_2 exhibits variations in output CG as the output
reflector offset length (Loutfo) and correspondingly the load seen at the output, is varied.
Figure 3.104 shows the same response as Figure 3.102 where model A has been
replaced with model C_2. From the figure it is seen that, at an input power o f -5 dBm, an
18 dB improvement in the 3fo conversion gain is achieved when Loutfo is varied from 0
to 90 degrees.
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232
— Pin = -5dBm
■— Pin = OdBm
Pin = 5dBm
in
T3
,_ r
O
O
-15
-20
-25
20
40
60
80
100
Loutj^ (Deg)
1 2 0
140
160
180
Figure 3 .1 0 4 .3fo Conversion Gain vs. fo Output Reflector Phase Length for M odel C_2, C aseA l
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\iii Harm Gen via Output Conditions\d Output nfo Harm
Refl\comparison_plots_3_5_03\modelC-2_caseA_CG3fo_vs_Lfo_3_5_03.fig
Clearly, the use o f an fo output reflector can provide a significant contribution to the
third harmonic conversion gain*. Based on the output conductance o f Figure 3.103, this
contribution can only occur when the output load causes the device to transition between
regions o f operation (linear, saturation, reverse-breakdown). This concept will be
explored further below (beginning on page 237).To examine the effects o f the
fundamental frequency reflector in further detail, the conversion gain response of
modelC_2 was simulated over variations in Loutfo from 0 to 180 degrees for input power
levels from -10 to +10 dBm. From the simulation, regions of maximum conversion gain
at 2fo and 3fo can be determined.
* B e lo w in th is se c tio n b egin n in g o n p age 2 5 0 , this result is rev iew ed in th e ligh t o f optim al c o n v e rsio n
gain A N D p o w er ou t consideration s.
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233
Design fo r Maximum 2fo and 3fo Conversion Gain
The conversion gain response o f modeIC_2 versus the output reflector length (Loutfo)
is shown in Figure 3.105 and Figure 3.106 for case A l. Figure 3.105 shows the second
harmonic conversion gain for this case.
Pin
Pin
——■ Pin
Pin
Pin
=
=
=
=
=
-lOdBm
-5dBm
OdBm
5dBm
lOdBm
CQ -15
-20
0
20
40
60
80
100
Loutjo (deg)
120
140
160
180
Figure 3 .1 0 5 .2fo CG versus Output Reflector Length: M odel A, C aseA l (VGG=Vmid,Vdd=Vddmid)
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\iii Harm Gen via Output ConditionsVd Output nfo Harm
Refl\modelC_2_newlook_10_8_03\modelC_2_caseA_Loutfoswp_CG2fo_plot_10_9_03.fig
As shown in Figure 3.105, the output fo reflector clearly has a drastic effect on the 2fo
conversion gain for caseAl. The figure shows a maximum conversion gain o f -7.1 dB at
the second harmonic for an input power of -lOdBm and an output reflector length o f 81
degrees. Referring back to Figure 3.86 on page 204, it is seen that there is no 2fo
conversion gain (less than -30 dBm) for case A l when no reflector is used. Thus,
through the use of the output reflector a significant amount of 2 fo conversion gain can be
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234
attained even where none was present when no output reflector was present. Here, the
2fo CG achieved is attributed completely to the fact that the output reflector drives the
transistor in such a way that it makes transitions between the linear, saturation and
reverse-breakdown regions. Although a significant amount of 2fo conversion gain is
achievable for this bias level (caseAl: VGO=Vmid, Vdd=Vddmid) other bias cases exhibit
a much larger amount, as will be shown. Therefore the 2fo conversion gain response for
this case (A l) is not o f primary interest. As previously studied in Section S.ii.a where
there was no reflector present on the output network, caseAl with model C_2 is expected
to exhibit a much better 3fo conversion gain response than 2fo conversion gain.
Figure 3.106 shows the “3fo” conversion gain versus the output reflector length for
case A l at several different input power levels. The figure shows that the output reflector
length (Loutfo) also has a drastic effect on the 3fo conversion gain. For an input power
level o f -lOdBm, the 3fo conversion gain is shown to vary from less than -25dB all the
way up to a maximum o f 7.1dB (at Loutfo=87 degrees).
Another important conclusion to draw from Figure 3.106 is that the 3fo conversion
gain is maximized for an output reflector length approaching 90 degrees. This holds true
for all five power levels from -10 to +10 dBm.
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235
■
■
■
-
Pin
Pin
Pin
Pin
Pin
= -10dBm
= -5dBm
= OdBm
= 5dBm
= lOdBm
m
■D
■ T "-
co
O
O
-1 0
-15
-20
-25
20
40
60
80
100
Lout, (deg)
120
140
160
180
Figure 3.106. 3fo CG versus Output R eflector Length: M odel A, C aseA l (VGO=Vmid,Vdd=Vddmid)
C :\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\iii Harm Gen via Output ConditionsVd Output nfo Harm
Refl\modelC_2_newlook_10_8_03\modelC_2_caseA_Loutfoswp_CG3fo_plot_10_9_03.fig
CO
CD
o
- Original
■ Zoomed
95
1 0 0
Lout, (deg)
Figure 3.107. 3fo CG versus Output Reflector Length Showing True 90 degree Optim um Length:
M odel A, C aseA l (VGO=Vmid,Vdd=Vdd„id)
C :\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd MdlsMii Harm Gen via Output ConditionsVd Output nfo Harm
Refl\modelC_2_newlook_10_8_03\modelC_2_caseAl_pin_ml0_Loutfo_zoomswp_plot_10_15_03.fig
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236
Note that the maximum is not shown at exactly 90 degrees (it occurs at 87 degrees) due
to difficulty in obtaining computer convergence as the fundamental frequency impedance
o f the output network (Zmi^.^) approaches an open circuit (as will be shown below). At a
fixed input power level, the simulation can be zoomed in to obtain convergence closer to
90 degrees
Figure 3.107 shows the 3fo conversion gain versus fo output reflector length at an
input power o f -lOdBm and compares the original response (shown in Figure 3.106) with
a zoomed in simulation using a smaller step size. Figure 3.107 shows that 90 degrees
represents a true optimum value for the fo output reflector length (Loutfo).
Further insight into the 90 degree optimum length (Loutfo=90deg) is gained by
observing the magnitude o f the impedance o f the output network (M2) at the
fundamental, this is shown in Figure 3.108. As the figure shows, the impedance o f M2 at
fo becomes infinite (representing an open circuit) as the length Loutfo approaches 90
degrees. This large impedance causes a large drain-source voltage swing which forces
the transistor (modelC_2) into the linear and reverse-breakdown regions o f operation.
The mechanisms for the significant improvement shown in the 3fo conversion gain
can be studied by looking at the waveform plots for this case.
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237
25 00
2000
1500
N
1000
500
80
100
120
140
160
180
Lout (Deg)
Figure 3.108. M agnitude o f the Im pedance o f the fo Reflector Network at the Fundam ental
Frequency (|ZM2 |fo)» vs. Reflector Phase Length
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\iii Harm Gen via Output Conditions\d Output nfo Harm
Refl\comparison__plots_3_5_03\output_refl_fo_zinmag_plot_3_6_03.fig
•o
“
0.03
0.03
0.03
0.02
0.02
0.02
73
0.01
“
.10
0
' 5 0 o h m LL
\
0.01
time (sec)
V g s (V )
x10
LL w / r e f i'
.10
V d s (V )
x IO
—
N oRefI
Wi t h Refi
6
■0.7 -0.5
-0.3
Vgs (V)
-0.1
0.1
0
2
4
Vds (V)
Figure 3.109. Comparison W aveform Plot for Model C_2, Case A l . l
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Refl\comparison_plots_3_5_03\modelC-2_caseA_\vfcomp_pin_m7_opt3fo_3_6_03.fig
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238
The waveforms for modelC_2, case A l.l (VGO = Midway = -0.3V, Vdd = Midway =
2.5 V, Vg == 0.3 V, Pin = -7 dBm), with an input power o f -7dBm are shown in Figure
3.109. The figure gives a comparison o f the response with no output reflector at fo and
with the output reflector inserted and set to give maximum 3fo conversion gain (at an
output reflector length (Loutfo) o f 87 degrees).* Enlarged versions o f the waveforms
shown in Figure 3.109(b), (c), (d) and (e) are shown below in Figure 3.110, Figure 3.111,
Figure 3.112, and Figure 3.113.
0 .0 3
50 (bhm Lojad-Line
(No;Output'Reflector)
0 .0 2 5
fo Output Reftector
Load-Line
0.02
f
■o
0 .0 1 5
0.01
=.25nsel:
0 .0 0 5
a^.2nsec ,
e=.55nsec
0 .5
2 .5
3.5
4 .5
Vds(V)
Figure 3.110. IV Curves and Load-Line Plot (Zoomed in Plot o f Figure 3.109(d))
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\iii Harm Gen via Output Conditions\d Output nfo Harm
Refl\comparison_plots_3_5_03\modelC-2_caseA_wfcomp_partd_pin_m7_opt3fo_3_6_03.fig
* T he p recise optim um ca se (at L outfo= 90degrees) w ill also be sh o w n b e lo w (b eg in n in g o n p a g e 2 4 6 ),
h o w ev e r it is instructive to illustrate the e ffe c ts in v o lv ed by dem onstrating th e case for L outfo=87 d egrees
first.
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239
0
x10
1
2
a=.2 n s e c
O
o
0) -J
</>
0
E
4
-►
d= .45 n s e c
5
6
-0.7
-0.5
-0.3
-
0.1
0.1
Vgs (V)
Figure 3.111, Gate-Source Voltage W aveform (Zoomed in Plot o f Figure 3.109(b))
C :\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\iii Harm Gen via Output Conditions\d Output nfo Harm
Refl\comparison_plots_3_5_03\modelC-2_caseA_\vfcomp_partb_pin_m7_opt3fo_3_6_03.fig
0.03
0.025
b = .2 5 n se c
Effect of l^everseBreakdown
0.02
<
0.015
0.01
0.005
Eftpct of Knee
a = .2 n s e c
time (sec)
x IO
-10
Figure 3.112. Drain Current W aveform (Zoomed in Plot o f Figure 3.109(c))
C;\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd MdlsMii Harm Gen via Output Conditions\d Output nfo Harm
Refl\comparison_plots_3_5_03\modelC-2_caseA_wfcomp_partc_pin_m7_opt3fo_3_6_03.fig
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240
x10
0
-10
1
2
a = .2 n s e c
O o
<
Do
(0
<D
d = .4 5 n se c
E
5
6
0
0.5
1
1.5
2
2.5
Vds (V)
L inear
Saturation
3
3.5
4
. 4.5
5
V /
R e v e r se BD
Figure 3.113. Drain-Source Voltage W aveform (Zoomed in Plot o f Figure 3.109(e))
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\iii Harm Gen via Output Conditions\d Output nfo Harm
Refl\comparison_plots_3_5_03\modelC-2_caseA_wfcomp_parte_pin_m7_opt3fo_3_6_03.fig
With reference to Figure 3.110, Figure 3.111, Figure 3.112, and Figure 3.113, perusal
o f the waveforms is very informative. With no the reflector network and only a 50 ohm
load at the drain. Figure 3.86 presented earlier shows that for this case (caseA l.1, where
Pin=-7dBm) no harmonics are generated at the drain. As shown in Figure 3.110
(enlarged plot o f Figure 3.109(d)), the resistive 50 ohm load, as demonstrated by the 50
ohm load-line, keeps the output current and voltage within the saturation region. As a
result the output signal is a pure sinusoid at the fundamental frequency. This condition
has been overlaid with the result when the reflector is inserted at the drain as also shown
in Figure 3.110. As the figure shows, the use o f the output reflector causes dramatic
changes. The output reflector, with a length o f approximately 90 degrees (Loutfo=87)*,
presents close to an open circuit to the transistor output at the fundamental frequency.
P le a se refer to th e fo otn ote on p age 2 3 2 , in regards to the c h o ic e o f Loutfo presented here.
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241
This causes the output voltage waveform swing to become quite large, going from
approximately 0.2 to 4.8V. This leads from the linear region below the knee (Vki=0.5) of
the IV curve to the reverse breakdown region (Vrbd=4.5). The effects o f this on the
output current are dramatic. They are best explored by examining the signal path o f the
gate-source voltage (Vgs, Figure 3.109(b) and Figure 3.111), drain current (Ids, Figure
3.109(c) and Figure 3.112), and drain-source voltage (Vds, Figure 3.109(e) and Figure
3.113) waveforms. These are explored at several points in time, denoted as times a, b, c, d
and e in all the enlarged figures. Between time a (.2 ns) and time b (.25 ns) the gatesource input voltage (Figure 3.111) follows a normal sinusoidal path. The corresponding
drain output current (Figure 3.112) during these times also follows a normal sinusoidal
path, the same as the path as would occur without the reflector network. The
corresponding drain-source output voltage (Figure 3.113) falls within the saturation
region (Vki=0.5, Vrbd-4.5V) between time a and time b. At time b (.25 ns) when
Vds=0.5V, the drain voltage is driven into the linear region due to the load presented by
the fo reflector (the impedance presented by the reflector network, Zm2 , will be explained
in more detail below). This causes a dramatic decrease in the output current as the drain
voltage is driven down to almost OV (see Figure 3.113). Between time b (.25 ns) and
time c (.35 ns) the gate-source voltage remains on a normal sinusoidal path comparable to
when no output reflector is used. However, from Figure 3.112 the drain current diverges
from the normal sinusoidal trajectory and instead decreases, reaches a local minimum,
and begins to rise again between these times. This response in the drain current (Figure
3.112) corresponds exactly with the drain-source voltage being driven into the linear
region, reaching a minimum at 0.2V, and then rising back up towards the saturation
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242
region (at time e). Note that this effeet is also exhibited in Cripps [62] (in Figure 3. 1 0 on
page 62 o f this reference). When the drain voltage reaches the saturation region at time c
(.35ns), the output drain-source current (Figure 3.112) begins a normal sinusoidal path
again. Between time c (.35 ns) and time d (.45 ns), the gate-source voltage (Figure
3.111) continues on its sinusoidal trajectory. The drain current (Figure 3.112)
corresponds to the waveform when no reflector is present. Here, the drain-source voltage
has left the linear region and again falls within the saturation region. At time d (.45ns)
the drain voltage begins to be driven up to the reverse-breakdown region. Here the
output current begins a dramatic increase. This is due to reverse-breakdown o f the gatedrain diode, and the large amount o f current which flows from the drain o f the transistor
back towards the gate. Subsequently, this feedback current towards the gate changes the
gate voltage as it flows through Dgd, Dgs and back towards the generator through RgenHowever all o f the current flows through Rgen since Dgs is turned off at this time. This
feedback is illustrated by the distortion in the gate-source voltage waveform, which is
shown to begin at time d (.45ns) and continue from time d (.45ns) to time e (.55ns). The
reverse breakdown o f the gate-drain diode Dgd between time d and time e is shown in
Figure 3.114 below. The figure shows a peak o f -5.4mA current flowing back into the
gate, causing the distortion o f the gate-source waveform. This is seen when the voltage
drop across Rgen (due to Igd) and the input voltage signal (Vg*sin(cOot), shown in the
circuit diagram o f Figure 3.99) add up to exactly -0.3V. Between these times d and e the
output drain current increases, reaches a local maximum, and begins to decrease again.
This response in the current corresponds exactly with the drain voltage being driven into
R e p r o d u c e d with p e r m is s io n of t h e cop y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e r m is s io n .
243
the reverse breakdown region, reaching a maximum o f approximately 4.7V, and then
dropping back into the saturation region. At time e (.55ns) the process begins to repeat.
As previously discussed. Figure 3.110 shows the load-line trajectory superimposed on
the DC IV curves. The figure shows how the Ids current versus Vds voltage relationship
varies over time. Between time a and b the load-line varies in a straight line, with the
current increasing from 3mA to 17mA and the voltages decreasing from 4.5V to 0.5V.
At time b, the transistor transitions into the linear region. Between times b and c, the
load-line flows down into the linear region. During this time, the drain-source current
begins to quickly decrease dropping to a minimum of 7mA and then rises to 2ImA at
time c. The corresponding drain-source voltage (between times b and c) is constrained
close to the knee voltage (0<Vds<0.5V). From time c to time d, the load-line follows a
straight line through the saturation region. The load-line between these times (times c
and d) is parallel to the load-line between times a and b. The output current drops from
2ImA at time c to 8 mA at time d. The corresponding voltage rises from the knee (0.5V)
at time c to reverse-breakdown (4.5V) at time d. At time d the devise enters reversebreakdown. Between time d and e the load-line travels into the reverse-breakdown
region and back out again. During this time the output current rises up to a maximum o f
18mA and then falls down to 3mA at time e. The corresponding voltage during these
times (times d and e) is constrained close to the reverse-breakdown voltage
(4.5<Vds<4.8V).
R e p r o d u c e d with p e r m is s io n o f t h e cop y rig h t o w n e r. F u r th e r r e p r o d u c tio n p rohib ited w ith o u t p e r m is s io n .
244
1
x10'
KMMyi-
0
-1
! \
t=a
t
I
1
1
1
T3
•
I
-4
f
I
V fI
f
-6
f
f
N o Refi
With Refi
I
f
V
-5
I
t
f
f
VI
f
*
1
I
i
I
*
I
1
I
I
I
1
I
1
I
*-
f
1
I
I
t=e
3
4
T im e (s e c )
x 10
- 10
Figure 3.114. Gate-Drain Current W aveform for M odelC_2, C a seA l.1 (VGO=Vmid, Vdd=Vddmid5
Pin=-7dBm)
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\iii Harm Gen via Output Conditions\d Output nfo Harm
Refl\comparison_plots_3_5_03\modelC_2_CaseAl_l_Probed_Igdwf_plot_10_05_03.fig
0.35
0.014
■(a) G. ate Vc titage
C
^
D
ra)
0.2
ain C jrrenti
f
t'l
1
W
2.51
1
0.01
X
No Refi
•
With Refi
• 0.008
i
D
)
<0
2 0.006
0.1
0.004
i
—
{----- 5
F req(G H z) ^.,^9
#
D>
"(0D
>
i
i
L
§ 1.5
| ) 0.15
0.05
^ ‘ !(c) ofain v ilta g e
^-----
0.012
0.3
0.25
■(b)
0.5
0.002
—
i1
1
^
Freq(G H z) ^.,o9
F re q (G H z)
^^.,^9
Figure 3.115. Comparison Frequency Domain Response for M odel C_2, Case A l.l
C :\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd MdlsMii Harm Gen via Output Conditions\d Output nfo Harm
Refl\comparisonj3lots_3_5_03\ modelC-2_caseA_FScomp_pin_m7_opt3fo_3_6_03.fig
R e p r o d u c e d with p e r m i s s io n o f th e cop y rig h t o w n e r. F u r th e r re p ro d u c tio n p rohib ited w itho ut p e r m is s io n .
245
The frequency domain representation o f the waveforms in Figure 3.109(b), (c) and (e)
is shown in Figure 3.115. This figure shows the frequency domain representation with
(x) and without ( • ) the reflector network. Figure 3.115(a) shows the gate-source voltage,
Figure 3.115(b) shows the drain current, and Figure 3.115(c) shows the drain-source
voltage. The distortion in the output current and voltage waveforms provided by the
reflector network results in a large amount o f 3fo content, where none (zero) is present
without the network. A large increase in fundamental frequency level in the drain
voltage is also shown as a result o f the inclusion o f the fo reflector network.
Referring back to the 3fo conversion gain versus output reflector length (Loutfo)
response in Figure 3.106, another trend is seen. For output reflector lengths o f less than
60 degrees and greater than 120 degrees the conversion gain remains constant. This
relates to the magnitude o f the impedance o f M2 at the fundamental (Figure 3.108). It is
seen in Figure 3.108 that below an Loutfo o f 60 degrees and above 120 degrees the
impedance becomes much smaller (less than 90 ohms) compared to the maximum values
seen around 90 degrees o f greater than 2500 ohms. As this impedance becomes smaller,
the drain-source voltage swing at fo is reduced until the transistor operates solely in the
saturation region (This phenomenon is further illustrated in the following discussion).
When the impedance is smaller, the output fo reflector does not contribute to harmonic
generation on the output.
Effect of Reflector Network on Load-Line
By observing the load line trajectory for several different output reflector lengths
(Loutfo), the transistor is shown to go from making significant transitions between the
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
246
linear, saturation, and reverse-breakdown regions to operating only within the saturation
region. This principle is shown in Figure 3.116.
0.03
0.025
QurveB
0.02
« 0.015
T3
CurveB
Curve A
DC IV, VGO=Vp
__ DC IV, VGO=Vmid
DC IV, VG0=V1wd
CuneA, Loutjjj=89.9deg
CurveC
CuneB, Loutjjj=80deg
CurvfeA
0.01
CurveD
0.005
I
CuneC, Loutj^=40deg
CuneD, Loutf^=Odeg
Vds (V)
Figure 3.116. Load-line Trajectory Comparison for Various Output Reflector Lengths (Loutf„)
C :\R esearch\l_B_l Undrstndng NL MechVB Stdy Idlzd MdlsViii Harm Gen via Output Conditions\d Output nfo Harm
Refl\modelC_2_newIook_10_8_03\modelC_2_caseAl_l_Loutfoswp_LLplot_10_l 1 0 3 .fig
This figure shows the load-line trajectory o f case A l.l (VGO=Vmid, Vdd=Vddmid,
Pin=-7dBm) for differing Loutfo values of 89.9, 80, 40 and 0 degrees. When the output
length Loutfo is 89.9 degrees (very close to an open circuit), the transistor is shown to
operate in the linear and reverse-breakdown regions over a large portion o f the trajectory
(Curve A). Note that in the saturation region o f operation, this trajectory is itself a
straight line. As the length is reduced, the impedance |ZM2 |fo drops (as shown in Figure
3.108) and the drain-source voltage swing is decreased. The reduced drain-source
voltage swing results in the transistor spending less time in the linear and reversebreakdown regions o f operation, and more time operating in the saturation region. This is
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
247
reflected in the load-line trajectory when Loutfo is equal to 80 degrees (Curve B). When
Loutfo is reduced further, the drain-source voltage swing decreases so much that the
device operates purely in the saturation (shown in Figure 3.116 when Loutfo = 40deg,
Curve C). When this occurs, the transistor is no longer making nonlinear transitions into
the linear and reverse-breakdown regions, and the output reflector no longer contributes
to the higher order harmonic output. When Loutfo is equal to 0 degrees (Curve D), the
fundamental frequency impedance is
0
(a short circuit) and the load-line becomes
completely vertical and is again a straight line.
Effect of Reflector Network on Conversion Gain
The following discussion shows the improvement o f the “optimum” reflector network
on conversion gain. Figure 3.117 shows the 2fo and 3fo conversion gain versus the input
power at the optimized reflector lengths (Loutfo=81 degrees for maximum 2fo conversion
gain and Loutfo=87degrees for maximum 3fo conversion gain*, as previously shown in
Figure 3.105 and Figure 3.106 respectively), compared to the response when no reflector
is used. The figure also shows the output power response which corresponds exactly
with the conversion gain shown when the reflector is used. The output power will be
used in the ensuing discussion to show that a new design parameter must be used to
determine an optimum practical design.
As shown in Figure 3.117, the output reflector allows for a large improvement in both
the 2fo and 3fo conversion gain. Figure 3.117(a) shows that the 2fo conversion gain
reaches a maximum o f -7.1 dB (at Pin=-10dBm) where no 2fo conversion gain is
* T he op tim u m is actually 9 0 d egrees, but due to the sim u lation issu es d iscu ssed earlier, 8 7 d eg rees is
actu ally u sed here.
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248
achieved without the input reflector. Note that in this instance, the 2fo conversion gain
occurs entirely due to the use of the output reflector.
10
10
(a) Loutj^ = Optfo(2fo CG = 81deg
5■ —
5
0
0
CG w/ Ref!
——■ Pout w / Refi
4
-5
/
2- 10
/
/
/
-15
-20
\
\
\
\
\
\
-15
y
y
/ y
/
\
V
/
-20
^
C G w /R e fI
——■ Pout w /R e fi
CG no Refi
-25
-25
-30
-10
-5
^-■'0
>
CM
(b) Lout,^ = Opt for; 3fo C G = 87deg
CG no Refi < -30dB
10
Pin (dBm)
10
-1 0
Pin (dBm)
Figure 3.117. Conversion Gain Comparison for Model C_2, Case A l
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd MdlsMii Harm Gen via Output Conditions\d Output nfo Harm
Refl\modelC_2_newlook_10_8_03\modelC_2_caseA_Pinswp_2fo3fo_plot_l0_9_03.fig
For the third harmonic, Figure 3.117(b) shows a maximum 7.1 dB conversion gain (at
Pin=-10dBm) with the reflector compared to only a maximum o f -5 dB with no reflector.
Note that in this instance, the 3fo conversion gain occurs entirely due to the use o f the
output reflector when the input power is less than -7dBm. However, when the input
power is greater than -7dBm 3fo conversion gain occurs without the reflector, but when
the reflector is used it significantly increases the 3fo conversion gain. The improvement
in this case occurs due to additional 3fo power being generated at the drain, mixing
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
249
occurring in the drain, and feedback to the gate provided when the transistor is
driven into reverse-breakdown.
Also o f note in Figure 3.117(b) is that the input power level at which the 3fo
conversion gain is maximum is significantly different when the reflector is utilized. The
maximum 3fo conversion gain occurred at -1 dBm input power with no reflector, but
with the optimized reflector (Loutfo=90deg) the maximum occurred at an input power o f 10 dBm. This difference is seen because, with no reflector present the mechanisms for
harmonic generation are clipping o f the Ids current as the gate source voltage swings
below pinchoff and above forward conduction (as previously discussed in Section 3.ii.a).
When the fundamental frequency output reflector is used, harmonics can be generated by
causing the transistor to transition between the linear, saturation and reverse-breakdown
regions. As the input power level is intentionally lowered, and correspondingly the
drain-source current swing becomes smaller, the large impedance at fo still allows a large
drain-source voltage swing. Thus, the transistor can still transition into the linear and
reverse-breakdown regions and cause the device to generate significant harmonic output
power. The lowering of the input power while retaining a significant output power
level at the desired harmonic is what causes a larger conversion gain.
Another vital relationship shown in Figure 3.117 is between the conversion gain and
the corresponding output power. As shown in Figure 3.117(b), (for the case o f the
reflector included) the maximum 3fo conversion gain occurs when the 3fo output power
is a minimum (the input power has been restricted from - 1 0 to
+ 1 0
in this section).
Likewise, the maximum 3fo output power occurs near the point o f minimum 3fo
conversion gain. This presents a serious problem in the design o f frequency multipliers.
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250
Although the focus o f the design techniques presented so far was on maximizing the
conversion gain, great care must also be taken to ensure that a reasonable output power
level can be reached as well. The next section presents a new design technique which
accounts for an optimal design based on both conversion gain and output power response.
D esigning f o r M aximum M ultiplier Power (MP)
In order to design a multiplier with large conversion gain and simultaneously ensure
sufficient output power at a given harmonic, a new characterization is necessary. This
measurement, called multiplier power (MP) is given by Equation ( 3.49 ) below:
Pout^
MPnfo {^ atts) = CG„^„ {mag) * Pout„^„ {watts) = - ^ ^ { w a t t s )
^
^
By taking the product o f the conversion gain and output power, the multiplier power
(MP) provides a means to design for large conversion gain and output power at a desired
harmonic. If the conversion gain becomes unreasonably large for a very small input
power level, the multiplier power will remain low due to the Pout squared term. Thus the
multiplier power allows the multiplier designer to design for a large conversion gain
while ensuring sufficient output power. With these principles in mind, the sweep o f input
power level and output reflector length (Loutfo) from the previous section was repeated to
find the maximum multiplier power for case A l (VGO=Vmid, Vdd=Vddmid)- Examples
o f the MP for 2fo versus the output reflector length for case AI at several different input
power levels are shown in Figure 3.118.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
251
—
—
60
80
100
Loutfo (deg)
Pin = -1 OdBm
Pi n = -5dBm
Pin = OdBm
Pin = 5dBm
Pin = lOdBm
120
180
Figure 3 .1 1 8 .2fo M ultiplier Power (M P) versus Output Reflector Length: M odel A, C aseA l
(VGO=Vmid,Vdd=Vdd„id)
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd MdlsMii Harm Gen via Output Conditions\d Output nfo Harm
Refl\modelC_2_newlook_10_8_03\modeIC_2_caseA_Loutfoswp_MG2fo_plot_10_9_03.fig
Note that, Figure 3.118 shows the same relative relationship between the multiplier
power and Loutfo as between the conversion gain and Loutfo (previously shown in Figure
3.105). This occurs since at any given input power, the multiplier power and conversion
gain are related to each other by a simple scaling factor (Poutnfo), regardless o f the value
chosen for Loutfo. However, the optimum combination o f input power and Loutfo can be
very different for the multiplier power. As shown in Figure 3.118, the optimum
multiplier power (for an input power range o f -10 to +lGdBm) occurs for an input power
o f around 10 dBm and an output reflector length o f 95 degrees. The optimum
conversion gain, previously shown in Figure 3.105 occurred at an input power o f -10
dBm and an output reflector length o f 81 degrees.
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252
Figure 3.118 also shows a low value o f multiplier power (as can be seen by observing
the large multiplier power in Figure 3.119, to be shown), which hints that this design
gives a relatively poor 2 fo conversion gain and output power.
Figure 3.119 shows the 3fo multiplier power (MP) versus the output reflector length
for case A l (ie biased midway) at several different input power levels.
Pin
Pin
Pin
Pin
Pin
= -lOdBm
= -5dBm
= OdBm
= 5dBm
= lOdBm
Q. -15
60
60
100
Loutfo (deg)
120
140
160
180
Figure 3.119. 3fo M ultiplier Power (M P) versus Output Reflector Length: M odel A, C aseA l
(VGO=Vmid,Vdd=Vdd,„id)
C :\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd MdlsMii Harm Gen via Output Conditions\d Output nfo Harm
Refl\modelC_2_newlook_10_8_03\modelC_2_caseA_Loutfoswp_MG3fo_plot_10_9_03.fig
Here, the maximum multiplier power is seen at an input power level o f -5 dBm and an
output reflector length o f 87 degrees*. The multiplier power reaches a maximum of
around 6 dBm, which will be shown below to suggest a significant 3fo conversion gain
and simultaneous output power level.
The true maximum occurs at 90 degrees as previously discussed.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
253
In order to examine the results o f maximizing the multiplier power, the multiplier
power (MP) versus input power response with the optimized output reflector length is
compared with the MP response when no reflector is used. This comparison is shown in
Figure 3.120, which shows the following*.
•
MP with the reflector
•
MP with no reflector
•
CG with the reflector
•
CG with no reflector
•
Pout with the reflector
10
(a)
L ou(^ = O p t fon2fo M P
95 deg
(b) Lout I = O p t fo rS fo M P =; 8 7 d e g
C G w / Refi
P o u t w /R e fi
M P w / Refi
C G no Refi
M P no Refi
00
-1 5
-20
-25
-30
-5
0
Pin (dBm)
5
10
C G w / Refi
P o u t w / Refi
MP w / Refi
C G no Refi
M P n o Refi
-35
-10
Pin (dBm)
Figure 3.120. M ultiplier Power (MP) Comparison for M odel C_2, Case A l
C :\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd MdlsMii Harm Gen via Output Conditions\d Output nfo Harm
Refl\modeIC_2_newlook_10_8_03\modelC_2_caseA_Pinswp_2fo3fo_wMG_plot_10_9_03.fig
T he resp o n ses w ith the reflector are sh o w n for a reflector len gth Loutfo set to m a x im iz e th e M P.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
254
Figure 3.120(a) shows the result for the 2fo output. As the figure shows, the
maximum multiplier power is -16dBm and occurs at an input power o f lOdBm. The
corresponding 2fo conversion gain is -13dB with an output power o f -3dBm. As
expected from the low overall multiplier power (-16dBm), the 2fo conversion gain and
output power to not reach a very large level. Figure 3.120(b) shows the result for the 3fo
output. It is shown in the figure that by utilizing the optimum output reflector length
(Loutfo~90deg), the maximum multiplier power (MP) is improved from -9dBm (at
Pin=2dBm) with no reflector to 6 dBm (at Pin=-3dBm) with the reflector. The
corresponding 3fo conversion gain (at the point o f maximum MP, Pin=-3dBm) is around
4.5dB with an output power level o f 1.5dBm when the reflector is used. When the fo
output reflector was utilized to maximize the 3fo CG (Figure 3.117, page 248) a 7.17 dB
CG was achieved at an input power o f -10 dBm, giving a corresponding -3.83 dBm 3fo
output power level. In comparing the maximum MP design with the maximum CG
design, it is seen that by utilizing the maximum multiplier power, the conversion gain is
reduced by 2.67dB (7.17-4.5) but the output power level is raised by 5.33dB (1.5-(3.83)). This shows the practicality o f using the multiplier power method in multiplier
design to ensure an ample amount o f output power is achieved while still achieving a
large conversion gain.
3.iii.c.3. Case B1 Pinchoff Bias (VGO=Vp, Vdd=Vddmid)
The design methods explored for case A l above were repeated for case B 1. For the
present case (B l), the conversion gain response (at 2fo and 3fo) versus the output
reflector length (Loutfo) was studied for several input power levels. Figure 3.121 shows
the 2 fo conversion gain versus output reflector length for input powers ranging from
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
- 1 0
255
to +10 dBm. The figure shows that, generally, as the input power is increased, the
conversion gain decreases.
2r
0 ■
-2 ■
—
-4 ■
s
~o
-6 ■
^ —
CsJ -8
@)
o -1U ■
o
-12
•»*»
*/
Pin = -10dBm
Pin = -5dBm
Pin = OdBm
Pin = 5dBm
Kin
ua
Pi n = 1lOdBm
__
y
i
-14 -16
------- - '4
20
40
60
80
100
Lout^^ (deg)
120
140
160
180
Figure 3.121. 2fo Conversion Gain vs. Output Reflector Length (Loutf„), C ase B1 (VGO=Vp,
Vdd=Vdd„.i<,)
C;\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\iii Harm Gen via Output Conditions\d Output nfo Harm
Refl\modelC_2_newlook_10_8_03\modelC_2_caseB_Loutfoswp_CG2fo_plot_10_9_03.fig
Also, the conversion gain typically peaks for Loutfo ~ 90degrees in each case, except
for input powers o f 0 and -5dBm when the maximum conversion gain occurs at 23
degrees.
Another phenomenon shown in the figure is that the local maxima o f each trace shown
(representing different input power levels) are different. The local maximum for an input
power level o f -lOdBm occurs at 91 degrees as do the maxima for input power levels o f 5
and lOdBm. At an input power o f 0 and -5dBm however, the local maximum occurs at a
reflector length o f 23 degrees. The conclusion to be drawn from this example is that the
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
256
maximum multiplier power (MP), which may occur at a different input power, may also
occur at a different output reflector length.
For the third harmonic, Figure 3.122 shows the 3fo conversion gain versus the output
reflector length for several input power levels.
Pin
Pin
——• Pin
Pin
Pin
= -lO dBm
= -5dBm
= OdBm
= 5dBm
= lOdBm
I
180
Lout^^ (deg)
Figure 3.122. 3fo Conversion Gain vs. Output Reflector Length (Loutf„), Case B1 (VGO=Vp,
Vdd=Vdd„id)
C :\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd MdlsMii Harm Gen via Output Conditions\d Output nfo Harm
Refl\modelC_2_newlook_I0_8_03\modelC_2_caseB_Loutfoswp_CG3fo_plot_10_9_03.fig
As was the case with the second harmonic conversion gain, this figure (Figure 3.122)
also shows a maximum conversion gain occurring near 90 degrees (Loutfo=89deg) for
3fo, at an input power o f -lOdBm. As previously discussed, the approximate 90 degree
output reflector length provides a large impedance at the fundamental frequency. This
results in a very large drain-source voltage swing which drives the transistor into the
linear and reverse-breakdown regions, creating desirable harmonics. The waveform plot*
S e e p a g e 81 for a d escrip tion o f w h at a w aveform p lot c o n sists of.
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257
for case B l.l (VGO=Vp, Vdd=Vddmid5 Pin=-7dBm) where the optimum output reflector
(Loutfo optimized for 2fo conversion gain) has been used is shown in Appendix B.ii.c.2
(page 498).
In order to show the improvement provided by the output reflector, the conversion
gain versus input power with the optimized reflector (Loutfo~90*) is compared with the
response when no output reflector is used. This comparison is shown in Figure 3.123
Note that the figure also shows the output power with the same optimized output
reflector.
(a) L o u (j = Opt forlzfo C G =! 91 deg
(b) Lou(^ = Opt for,3fo C G =; 89 deg
£ -10
CM
CO- 1 0
-15
-20
-15
— CG w/RefI
—■ Pout w/ Ref!
■■■ CG no Ref!
-20
-2 5
-2 5
-3 0
10
-1 0
Pin (dBm)
— GGw/RefI
-■ Poutw/RefI
. . . CG no Ref!
-3 0
-1 0
Pin (dBm)
Figure 3.123. Conversion Gain vs Input Power Comparison for Case B1 (VGO=Vp, Vdd=Vddmid)
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\iii Harm Gen via Output Conditions\d Output nfo Harm
Refl\modelC_2_newlook_10_8_03\modeIC_2_caseB_Pins\vp_2fo3fo_pIot_10_9_03.fig
Figure 3.123(a) shows the response at the second harmonic. The figure shows an
improvement in the maximum 2fo conversion gain from -IdB (without the reflector) to
l.SdB (with the optimized reflector) which occurs at an input power o f -lOdBm. This
T he len gth is sim u lated as c lo se to 90 d egrees as p o ssib le w ith ou t sim ulation error.
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258
figure also shows that the conversion gain response (with reflector) is significantly
different from the output power response for 2fo. Similar to case A 1, when the output
reflector is used to maximize the conversion gain, the conversion gain and output power
are shown to have an inverse relationship versus the input power. At the point o f
maximum 2fo conversion gain (Pin=-10dBm) a -8.5dBm second harmonic output power
is shown. As Pin changes to +10dBm, while the conversion gain decreases, Pout
increases to the point where at Pin=+10dBm, the conversion gain is -8.5dB and the
output power is +ldBm.
Figure 3.123(b) compares the 3fo conversion gain versus the input power when the
optimum output reflector is used to when no reflector is used. For the third harmonic, the
optimum output reflector (at Loutfo~90deg) results in a maximum 2.5dB conversion gain
which occurs at an input power o f -lOdBm compared to a maximum o f -1 IdB with no
reflector which occurs at an input power o f 5dBm. Once again the 3fo conversion gain
and corresponding 3fo output power show an inverse relationship when the output
reflector is used. At the point o f maximum 3fo conversion gain (Pin=-10dBm) a 7.5dBm second harmonic output power is shown.
In order to compensate for the difference between the locations o f optimum output
power and optimum conversion gain, the multiplier power (MP) is once again employed.
Figure 3.124 shows the MP versus the input power when the output reflector length
Loutfo has been set to optimize the MP, compared to the response when no reflector is
used. The figure also includes the corresponding conversion gain response (when the
reflector has been used to optimize the multiplier power and when no reflector is used).
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259
as well as the output power response (when the reflector has been used to optimize the
multiplier power).
Figure 3.124(a) shows that a maximum 2fo MP o f -2 dBm is reached for an input
power o f OdBm and an output reflector length o f 23 degrees. At this point o f maximum
2fo MP, a 2fo conversion gain o f -IdB is achieved with a corresponding -1 dBm output
power. The design optimized for 2fo conversion gain, previously shown in Figure
3.123(a) gave 1.5dB second harmonic conversion gain but only -8.5dBm o f 2fo output
power. This shows once again the advantage o f designing for maximum multiplier
power, rather than conversion gain.
10
(a) LoutJ = Opt fof2fo M P =! 23 deg
(b) Lou(^i = Opt fori3fo M P =i 89 deg
5
0
-5
-1 0
£
CM
-20
----- C G w /R efi
——• Poutw/RefI
----- M Pw/RefI
—
-1 0
1
^
MP no RefI
-5
0
Pin (dBm)
-35 •-
—
->
—
•
*-
C G w /R efi
Poutw/RefI
MPw/RefI
CG no Ref!
MP no Ref!
-40
-10
-5
0
Pin (dBm)
-25
5
10
-30
!
5
10
Figure 3.124. M ultiplier Power vs Input Power Comparison for Case B1 (VGO=Vp, Vdd=Vddn,id)
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd MdlsMii Harm Gen via Output Conditions\d Output nfo Harm
Refl\modelC_2_newlook_10_8_03\modelC_2_caseB_Pinswp_2fo3fo_wMG_plot_10_9_03.fig
Figure 3.124(b) shows a similar result to that o f Figure 3.124(a), for the third
harmonic. Flere a maximum -O.SdBm third harmonic multiplier power is achieved at an
input power o f IdBm and output reflector length o f 89 degrees. At this point o f
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260
maximum 3fo MP, a 3fo conversion gain o f -IdB is achieved with a corresponding 0
dBm 3fo output power. The design optimized for 3fo conversion gain, previously shown
in Figure 3.123(b) gave a 3fo conversion gain o f 2.5dB but only a -7.5dBm o f output
power. Once again the advantage o f using the multiplier power is shown.
In summary, it was shown that an fo output reflector can be utilized on a transistor’s
output to improve the 2fo and 3fo CG. Furthermore, the MP can be optimized rather than
the CG, allowing a significant CG to be achieved while ensuring a reasonable
corresponding output power level.
3.iii.c.4. Other Cases Studied
The use o f the fo reflector was repeated for C l, A2 and A3 (as shown in Table 3.8)
using modelC_2. For convenience, the case definitions are repeated here:
CaseCl: VG0=Vfwd-0, Vdd=Vddmid=2.5V
CaseA2: VG0=Vmid=-0.3, Vdd=Vki=0.5V
CaseAB: VG0=Vmid=-0.3, Vdd=Vrbd=4.5V
For each case, the study conducted above for cases A1 and B1 was repeated. This
entailed the following:
(a) The input power and output reflector length (Loutfo) were swept and the points o f
maximum 2fo and 3fo conversion gain were found.
(b) The waveform plots showing the gate and drain waveforms and the load-line
trajectory when the optimized output reflector is utilized were examined.
(c)The optimum points from the sweep o f part (a) were compared to the response
when no output reflector was used by looking at the conversion gain versus input power
response.
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261
(d)
Finally, the points o f maximum 2fo and 3fo multiplier power were identified and
the response utilizing the optimum output reflectors was compared to the response when
no output reflector was used by looking at the multiplier power versus input power
response.
These results are shown in Appendix B.ii.c.3, B.ii.c.4 and B.ii.c.5 (beginning on page
499) and they show a very significant result. Just as in the previous cases (case A1 and
B l), for each design with significant output conversion gain (at the desired harmonic),
the maximum conversion gain occurs for output phase lengths o f Loutfo close to 90
degrees. As already shown in Figure 3.108, this length corresponds to a maximum
impedance o f Zm2 at fo (ZM2 g,)- For each case the conversion gain is maximized at least
in part due to distortion o f the drain current waveform resulting from the device
entering the reverse-breakdown region. Using a large impedance to drive the device
into reverse-breakdown presents some concerns. The device is being driven up to a large
drain voltage, with potentially harmful results in an actual device. Although several
practical devices have been designed, tested and run for reasonable lengths o f time
without detrimental effects.
Another concern is that, since the device is operating partially in the reversebreakdown region, a significant amount of feedback is present which gives the potential
for stability problems. Thus, as stated in Maas [3], using an open-circuit drain
termination at the fundamental frequency may have unpredictable results. Although
Mima [34] has been able to develop multiplier designs based on stability.
The problems in terms o f stability and device operating limits expected from utilizing
this region o f operation warrant great care when considering a final multiplier design.
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262
However, it is certain that the use o f the fo output reflector network can provide a very
significant improvement in output conversion gain.
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263
3.iv Harmonic Generation via input and Output Conditions
In Section 3.ii, the effects o f varying the input conditions on harmonic generation
were studied. These input conditions consisted o f VGO, Pin and the impedance o f the
input network (Zmi) at DC (variation in Rdc) and the first three harmonics (variation o f
quarter-wavelength “matching” network at fo, and variation of input m*fo reflector). In
Section 3.iii, the effects o f varying the output conditions on harmonic generation were
studied. These output conditions consisted o f Vdd and the impedance o f the output
network (Z mi) at DC (variation in Rdd) and the first three harmonics (variation in R l, and
variation in an output n*fo reflector). In order to fully characterize basic harmonic
generation, simultaneous variations o f input and output conditions are explored in this
section.
Sections 3.iv.a through 3.iv.d below utilize simultaneous variation o f the variables
described above in development o f design techniques for optimum 2fo and 3fo
conversion gain. Section 3.iv.a explores a typically utilized procedure o f shorting out the
unwanted harmonics with a parallel LC load and finding the optimum load resistance Rl
to increase output conversion gain and output power [3;6]. Section 3.iv.b examines the
use o f a fundamental frequency output reflector and an input reflector at the desired
output harmonic (m*fo). Section 3.iv.c builds on the design o f section 3.iv.b, adding on
an input and output reflector at the higher-order, unwanted harmonic (n*fo). The designs
o f Sections 3.iv.a through 3.iv.c are numbered I through 3, respectively. Section 3.iv.d
shows a comparison o f designs 1, 2 and 3. The characterization o f the above designs was
conducted with ADS and utilized the idealized model containing the linear and reversebreakdown regions o f operation (modelC_2).
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264
3.iv.a. Idealized Design #1, Parallel Output LC Circuit with Load
Resistance Variation
3.iv.a.l. Introduction
A common frequency multiplier design method is to:
•
adjust the input signal and bias level to generate a large amount o f output power
at a desired harmonic (as presented in Section 3.ii.a)
•
filter out the unwanted harmonics with a parallel LC filter tuned to the desired
output harmonic
•
adjust the load resistance Rl for maximum output power at the desired harmonic
[3;6],
The topology for such a design is shown in Figure 3.125 below.
M2
Ids
Vds
Vgs
R d c= 50n
^
VGO
Figure 3.125. M ultiplier Topology Utilizing Parallel LC Circuit
C:\research\figures\jj m lm 2 ideal_designl BD.ai
In order to verify and explore the above design method, an ADS simulation was
performed using the circuit configuration o f Figure 3.125 with transistor model C_2
(containing the linear and reverse-breakdown regions o f operation). By utilizing an ADS
simulation, the theoretical calculation for the optimum load Rl will be verified, the
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265
effects o f terminating the unwanted output harmonics with the LC filter will be explored,
and the improvement in harmonic generation will be shown below.
3.iv.a.2. Theoretical Design
Many multiplier design techniques utilize a topology similar to that shown in Figure
3.125 and use the following procedure [3;6]:
•
Initially, variation in the input signal and bias level are utilized to create large
amounts o f output current at the desired output harmonic. In Section 3.ii.a this
process was discussed in-depth and optimum bias points for: (a) second harmonic
conversion gain (case B I, VGO=Vp=pinchoff) (b) second harmonic conversion
gain (case C l, VGO=Vfwd=forward conduction voltage) and (c) third harmonic
conversion gain (case A I, VGO=Vmid=midway between Vp and Vfwd) were
shown.
•
After adjusting the input power and bias levels in accordance with (a), (b) and (c)
above, the resulting output current is fed into a parallel LC filter centered on the
desired output harmonic (nfo), followed by a load resistor R l, as shown in Figure
3.125. The LC filter provides a short circuit for all frequencies other than the
desired output harmonic. In Section 3.iii.c the use of shorts for the unwanted
harmonics were studied as part o f the study o f nfo output reflector networks.
•
Finally, the resistance R l is adjusted to give a maximum Vds swing while keeping
the device in the saturation region (Rl = Riopt^^-J-
Given the idealized transistor parameters, (such as those for the idealized modelC_2,
which includes the linear and reverse-breakdown regions as discussed in Section 3.iii.a),
the optimum load (RLopt^fo) can be calculated for a given amount o f output current at the
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266
desired harmonic (m*fo). The calculation fo r the optimum load at the desired harmonic
m*fo (Riopt^j-J, as presented by [3;6] determines the optimum load to be that which
gives the maximum Vds swing (at a desired output harmonic m*fo) in the saturation
region of the transistor. To accomplish this, the optimum load is calculated by
determining the load required to cause the drain-source voltage to swing from the
reverse-breakdown voltage (Vrbd) to the knee voltage (Vki) when the drain is biased
midway between the two points (Vdd=Vddmid=(Vrbd+Vki)/2). This optimum load is
described by Equation ( 3.50 ) below.
Vdd-Vki
Loptmfo
( 3 .5 0 )
mfo
Where Vddmid is the drain bias (set midway between reverse breakdown and pinchoff;
Vdd=Vddmid=(Vrbd+Vki)/2), Vki is the knee voltage, and Idsmfo is the “peak” output
drain current at the desired harmonic m*fo. Note that this optimum load definition
differs somewhat from that given by Equation ( 3.34 ) on page 187 in Section 3.iii.a,
which was the load giving maximum CG at the fundamental frequency. Equation ( 3.50 )
is used to calculate the optimum load for an output current level at a desired harmonic
(m*fo), determined by manipulation at the transistor’s input. Using this optimum load,
no matter what the output current level (IdSmfo) is, the drain-source voltage will have a
maximum swing from the knee (Vki) to the reverse-breakdown (Vrbd) voltage. Note
also that when Idsfo for case A 1.1 is utilized as the desired output harmonic current (as
explored in Section 3.iii.a), Equation ( 3.34 ) is equivalent to Equation ( 3.50 ).
Based on the optimum load resistance given by Equation ( 3.50 ) and the calculated
harmonic output current (as shown on equations ( 3.3 ) and (3 .8 )), the second and third
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267
harmonic conversion gain from the circuit configuration o f Figure 3.125 can be
calculated.
Using the above calculations, the maximum second and third harmonic conversion
gain levels will be calculated and compared to simulated results using the idealized
transistor model C_2. Cases B l (VGO=Vp, Vdd=Vddm,d) and C l (VGO=Vfwd,
Vdd=Vddmid), shown in Section S.ii.ato provide large second harmonic conversion gain,
were studied for optimum second harmonic output. Case A l (VGO=Vmid, Vdd=Vddmid),
shown in Section B.ii.a to provide large third harmonic conversion gain, was used for an
optimum third harmonic output design.
3.iv.a.3. Designs for Optimum Second Harmonic Output*
Case B l (VGO=Vp, Vdd^Vdd^d)
For case B l the drain output current is a half-wave rectified sinusoid, shown in
Section 3.ii.a.5 to have large second harmonic output. The magnitude o f the second
harmonic output drain current can be calculated by utilizing Equations ( 3.2 ) and ( 3.3 )
where the gate bias (VGO) is set equal to pinchoff (Vp). The resulting output current at
2fo is given by Equation (3.51 ) below^:
__ 2 Ip
( 3 .5 1 )
D 71
S e e T ab le 3 .2 for determ ination o f th ese optim um bias eonditions.
^Note that a derivation o f equations ( 3.51 ) through ( 3 .5 6 ) is g iv e n in A p p en d ix
B.iii.a. 1.
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268
Where it is assumed the device has not been driven up to forward conduction at the
gate, and the output drain current remains a single-sided, clipped waveform. Ip is the
peak drain current and can also be calculated as a function of the gate input signal and
bias level. If the forward conduction voltage o f the Dgs diode is equal to zero, the peak
drain current becomes (Appendix B.iii.a. 1):
Vp
Where
Id ss
is the saturation current and Vg is the magnitude o f the AC input voltage
generator signal (shown in Figure 3.125). The resulting second harmonic drain current
magnitude is:
S ttVp
Using Equation ( 3.50 ), the optimum load is given by Equation ( 3.54 ) below:
n
Vdd-Vki
Given that the optimum load RLopt2fo gives a drain-source voltage swing o f (VddmidVki), the output power level can be calculated by Equation ( 3.10 ) as:
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269
Using Equation ( 3.55 ) and the equation for the available power previously shown on
Equation ( 3.12 ), the conversion gain at the second harmonic can be calculated by:
P a va il.
fo
-3 V fV g
As Equation ( 3.56 ) above shows, for a gate bias at the pinchoff voltage (case B l), the
output second harmonic conversion gain is inversely proportional to the gate input
voltage magnitude (Vg). As a result, the conversion gain can reach an infinite maximum
as Vg is decreased. However, a constraint on the conversion gain is imposed by the load
resistor Rlopi- As shown by Equations ( 3.53 ) and ( 3.54 ), as the AC gate input voltage
magnitude (Vg) is decreased, the second harmonic output current is decreased,
necessitating an increasingly large Rlopi value. Awareness of the fact that a potentially
infinite maximum exists was a significant consideration when creating optimum designs.
A Mathcad spreadsheet utilizing Equations (3.51 ) through ( 3.56 ) was used to
calculate the second harmonic conversion gain and optimum load for the ideal transistor
model, model C_2 defined in Table 3.7 on page 179. Using the parameters o f model C_2
(Vki = 0.5V, Vrbd = 4.5V, Vp = -0.6V, Vfwd = OV, loss = 0.025A), the second harmonic
conversion gain for an AC gate input voltage (Vg) o f 0.6V (corresponding to an available
power o f -0.458 dBm) was calculated by Equation ( 3.56 ) as 7.7 dB (CG2fo = 7.7dB).
This corresponded to an optimum load o f 377 ohms (R l = Rtopt = 377 ohms). The details
o f the calculation are shown in Appendix B.iii.a.2 (page 516).
In order to verify Equations ( 3.51 ) through ( 3.56 ) and the optimum choice o f load
resistance (R l) as defined by [3;6], the ideal model C_2 was utilized in an ADS
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270
simulation. A schematic o f the ADS simulation is shown in Appendix B.iii.a.3 (page
518). For a given input power level o f -0.46 dBm (giving a gate AC input voltage
magnitude o f 0.6V), the load Rl was swept through a range o f values to obtain the one
giving the maximum second harmonic conversion gain.
a
CM
—
X
o
O
Sim ulated
C alculated Optimum
R|^ (O hm s)
Figure 3.126. Second Harmonic Conversion Gain vs. Load R l for Case B l
C:\Research\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\iv Harm Gen via Input and
Output\jj_ideal_doub_l\caseBl_modelC2_doubI_finalswpl jlo t_ 6 _ 7 _ 0 3 .fig
Figure 3.126 shows the simulated second harmonic conversion gain versus the load
resistance R l for an AC gate input voltage o f 0.6V (Vg=|Vp|=0.6, Pin=-0.46 dBm) as
well as the calculated response as explained above. As the figure shows, the simulation o f
the idealized model verifies the theoretical choice o f optimum load (Rl = Riopt=377ohms)
fo r this multiplier design. Additionally, the increase in the load from 50 ohms to the
optimum is shown to increase the 2fo conversion gain from -1 to 7.75dB, an 8.75 dB
improvement.
R e p r o d u c e d with p e r m i s s io n of t h e cop y rig h t o w n e r. F u r th e r re p ro d u c tio n p roh ibited w ith o u t p e r m is s io n .
271
Note that the AC gate input signal (Vg=|Vp|) for this design was chosen to cause the
gate-source voltage to swing up to the point o f forward conduction, resulting in a
maximum peak drain-source current Ip. As shown on Equation ( 3 . 5 6 ) the AC input
signal could be reduced indefinitely, resulting in a very large conversion gain
(approaching infinity). However, this would require an increasingly large and impractical
optimum load resistance RLopijfo^s shown by Equation ( 3.54 ). Furthermore, reducing
Vg will reduce the output pow er level to an undesirable low value. In order to ensure a
design with large 2 fo conversion gain while achieving a reasonable output power level
the principle o f multiplier power (MP), previously discussed in Section B.iii.c, can be
utilized.
Figure 3.127 shows a plot o f the output power, conversion gain, and multiplier power
versus the input power when R l is set to the optimum (Rl = RLopt2 fo=3 7 7 ohms). The
figure shows that, although the maximum 2 fo conversion gain occurs over a range o f
input powers from -10 to -I dBm, the output power is maximum only around IdBm and
drops off quickly as the input power is decreased. The multiplier power (MP), previously
defined in Equation ( 3.49 ) on page 250, reaches a maximum at an input power o f
around 0 dBm where the 2fo conversion gain and output power are both large (2fo CG =
7.3 dB, 2fo Pout = 7.3 dBm). By utilizing the MP, the input power level can be
constrained to a reasonable value while still achieving a large 2 fo conversion gain.
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272
—
Pout (dBm)
C G (dB )
MP(dBm)
3
Q .
3
o
-10
-10
Pin (dBm)
Figure 3.127. Comparison of Output Power, Conversion Gain and M ultiplier Pow er R esponse, R l
=377ohms: Case B l (VGO=Vp, Vdd=Vdd„id)
C:\Research\I_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\iv Harm Gen via Input and
Output\jj_ideal_doub_I\modeIC_2_caseB_Desl_SwpA_MP_plot_10_13_03.fig
The other consideration for this design is the contribution o f the LC circuit to the
overall conversion gain. In Section S.iii.c, an fo output reflector element was used to
reflect fo power back into the drain o f the transistor, with beneficial effects. The LC load
o f this multiplier configuration also reflects the fundamental (as well as 3fo and higher
order harmonics) back into the drain by providing a short circuit. However, this load was
not shown to modify the conversion gain response as exhibited by the agreement between
the simulation and theoretical calculation (which did not account for any extra
contributions from the LC network). This non-contribution o f the LC circuit to the
second harmonic conversion gain is explained by looking at the impedance o f the output
network (Zm2 ), as shown in Figure 3.125. The impedance is described by:
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273
Kpt
0
n = m= 2
n^2
\
( 3 .5 7 )
In Section B.iii.c, it was shown that an fo output reflector could enhance the 2fo
conversion gain only when the reflector offset length (Loutfo) was adjusted so that the
impedance o f the output network at fo
became very large. For small values o f
Z]vi2 fo, the reflector gave a small drain-source voltage swing which kept the transistor
operating in the saturation region. When the parallel LC circuit (Figure 3.125) is utilized
on the output, a short circuit is seen at all o f the unwanted harmonic frequencies. This
results in a drain-source voltage swing o f zero at each o f the unwanted harmonics. At the
second harmonic, the impedance o f the output network
is equal to the optimum
load resistance (Rropijfo)- By definition, this optimum resistance causes Vds to swing
from the knee voltage (Vki) to the reverse-breakdown voltage (Vrbd), leaving the
transistor in the saturation region. The overall drain-source voltage contains 2fo content
only, and remains in the saturation region o f operation. Therefore, no harmonics are
generated from the nonlinear properties o f the Ids versus Vds response. Consequently,
the parallel LC output circuit is shown to suppress the unwanted harmonics, but not to
enhance the conversion gain.
Case C l (VGO=Vfwd, Vdd=Vdd^^
The other gate bias point showing optimal second harmonic output is Case Cl
(VGO=Vfwd, Vdd=Vddmid)- This case was shown to give the equivalent harmonic output
as case BI when a simple 50 ohm input and output network are used, and the device
R e p r o d u c e d with p e r m is s io n of t h e cop y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e r m is s io n .
274
remains in the saturation region (as shown in Section 3.ii.a.5). The only difference
between the two cases (shown in Section 3.ii.a.5) is in the gate input harmonic content.
Therefore, in the absence o f manipulation o f the gate voltage signal (by changing the
impedance o f the input network to something other than 50 ohms) the two cases remain
equivalent. For this design (utilizing the circuit configuration o f Figure 3.125) a 50 ohm
impedance is used for the input network ( Z m i ) and the device is constrained to the
saturation region. Therefore the response for case Cl is equivalent to case B l shown
above, and the conversion gain relationship o f Equation ( 3.56 ) is also valid for case C l.
Consequently, the resulting calculated and simulated second harmonic conversion gain
and optimum load resistance values are the same for case Cl as for case B l.
3.iv.a.4. Designs for Optimum Third Harmonic Output
C a s e A l (VGO=Vmid, Vdd=Vdd^^
To explore optimum third harmonic generation, a gate bias midway between the
pinchoff and forward conduction voltages was chosen (Case A l, VGO = Vmid). This
bias was chosen since it was the gate bias for third harmonic generation for the input
network (M l) o f Figure 3.125 as shown earlier in Figure 3.4 in Section 3.ii.a.
Similarly to case B l in the previous section (3.iv.a.3.on page 267), the conversion
gain for this input signal and bias level can be calculated as a function o f the device
parameters. In this case, the output current waveform is a double-sided, clipped sinusoid
described by Equation ( 3.8 ) when n is equal to 3 (calculation o f the third harmonic
current). The optimum load for this output current follows Equation ( 3.50 ), where m is
set equal to three. As a result, the optimum load and corresponding third harmonic
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275
conversion gain can be calculated. A MathCAD spreadsheet showing the above
calculation is presented in Appendix B.iii.a.4 (page 519).
Although the above calculation exists, a question exists as to what input power level
(and corresponding input voltage magnitude) should be utilized for maximum 3fo
conversion gain. In the previous section (3.iv.a.3), it was shown that the output
conversion gain could be increased indefinitely by lowering the input power level. The
drawbacks from doing so were a highly increased optimum load resistance and an
unrealistically low output power level. For case A l, and the third harmonic output, a
slightly different phenomenon takes place. Due to the complexity o f the output harmonic
current equation for this case (shown in Equation ( 3.8 ), page 75), no closed form
equation for the 3fo CG in terms o f the gate input voltage magnitude (Vg) exists.
However, the MathCAD calculation shown in Appendix B.iii.a.4 can be utilized to
calculate the 3fo CG for various input power levels while keeping the load resistance set
to the optimum (RLoptj^,)- This calculation was conducted for an input power range from
-6
to 2 dBm and the results are shown in Table 3.9.
Table 3.9. Calculation o f R lopi and Resulting 3fo CG for Several Input Power Levels
P in (d B m )
2
V q ( V)
0 .7 9 6 2
R Io o tfo h m )
474
P o u t (d B m )
6 .2 5
C G 3 fo (d B )
1
0 .7 0 9 6
0 .6 3 2 5
506
552
5 .9 7
5 .5 9
4 .9 7
5 .5 9
0 .5 6 3 7
0 .5 0 2 4
622
5 .0 7
731
4 .3 7
6 .0 7
6 .3 7
0 .4 4 7 7
0.3 9 9 1
920
1315
3 .3 7
1.82
6 .3 7
5 .8 2
1 0 .7 4
9 .7 4
7 .6 4
-5
0 .3 5 5 7
2416
-0 .8 2
4 .1 8
3 .3 6
-6
0 .3 1 7 0
11180
-7 .4 7
-1 .4 7
-8 .9 4
b e lo w .3
Not Applicable
-e o
-»
-C O
0
-1
-2
-3
-4
b e lo w -6
4 .2 5
M P 3 fo (d B m )
10.5
1 0 .9 4
1 1 .1 8
1 1 .1 4
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276
The table shows that, unlike case B l (Section 3.iv.a.3), the input power level cannot
be lowered indefinitely to result in an infinite conversion gain. In fact, for case A l,
which represents a gate bias midway between pinchoff and forward conduction, if the
input voltage drops low enough (below - 6 dBm, shown in Table 3.9) then the transistor
does not swing below pinchoff or up to forward conduction. Correspondingly, no
clipping o f the output current occurs and no harmonics are generated whatsoever.
Although the input power cannot be increased indefinitely. Table 3.9 does show that,
as the input power is dropped from 2dBm to -2dBm, the 3fo CG rises from 4.25 to 6.37
dB. A t this point (Pin=-2dBm), the conversion gain is maximized.
CO
@
o
o
—
X
-1 0
100
200
300
400
500
600
Simulated
Calculated Optimum
700
800
900
1000
R|_ (ohms)
Figure 3.128. Third Harmonic Conversion Gain vs. Load R l for Case A l, VGO=Vmid, Vdd=Vddmid,
Pin=-2dBm
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modeiC_2_caseA 1Jij idealtrip_des 1_rlswp_pl ot_ 10_26_03 .fig
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Ill
In order to verify the above calculations, model C_2 was utilized in an ADS
simulation. The third harmonic conversion gain versus load resistance Rl response was
simulated for an input power o f -2 dBm, as shown in Figure 3.128.
As shown in the figure. Equation ( 3.50 ) shows the correct calculation for the
optimum load for this multiplier topology. The figure also shows that the optimum load
increases the 3fo conversion gain to 6.37 dB where only -5 dB was obtained with a 50
ohm load. This represents an 11.37 dB improvement in the 3fo conversion gain.
Although the calculation summarized in Table 3.9 was successfully utilized to
determine the input power and load for maximum conversion gain, a disturbing trend can
be seen. As shown in Table 3.9, when the input power varies from 2 to -2dBm, the
required optimum load resistance rises from 474 to 731 ohms. Furthermore, the drop in
input power (from 2 to -2dBm) causes the output power to decrease from 6.25 to 4.37
dBm. Thus, similar drawbacks in dropping the input power to increase the conversion
gain can be seen for case A l (VGO=Vmid, Vdd=Vddmid) as were seen in case B l
(VGO=Vp, Vdd=Vddmid)- Due to these drawbacks, the M P (also shown in Table 3.9) was
employed. The table shows a maximum 3fo MP o f 11.18 dBm occurring at an input
pow er o f 0 dBm, and corresponds to a 5.59 dB CG. The resulting output power level is
5.59 dBm and the optimum load resistance is 552 ohms. In comparison, the design
optimized for CG gave a 4.37 dBm output power and a 731 ohm load resistance. As
such, utilizing the optimum M P design allowed a larger output power level, and a lower
load resistance value.
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278
3.iv.a.5. Summary of Results
The results o f the designs for cases A l, B l and Cl are summarized in Table 3.10.
Table 3.10. Summary o f M ultiplier Designs Using Configuration o f Figure 3.125
(a) D esigns for Optimum 2fo Output:
C aseB I
(VGO=Vp, Vdd=Vdd^.j)
C ase C l
(VGO=Vfwd, Vdd=Vdd^|^)
D esigned
for:
Maximum
2foCG
Maximum
2foM P
Maximum
2foC G
Maximum
2foM P
Output R esp o n se
Pout2fo
(dBm)
Zm2 (maq/deq)
Zm1 (m aa/deg)
C ass
Pin (dBm) CG2fo (dB)
MP2fo
(dBm)
fo
2fo
3fo
fO
2fo
3fO
50/0
50/0
50/0
0/0
380/0
0/0
-1
7.74
6.74
1448
50/0
50/0
50/0
0/0
380/0
0/0
0
7,3
7.3
14.6
50/0
50/0
50/0
0/0
380/0
0/0
-1
7.74
6.74
14.48
50/0
50/0
50/0
0/0
380/0
0/0
0
7.3
7.3
14.6
[bl D esipns for Optimum 3fo Output:
C a s e Al
(VGO=Vmid, Vdd=Vdd^.j)
D esigned
for:
Maximum
3foC G
Maximum
3foM P
Output R esp o n se
PoutSfo
(dBm)
Zm2 (maq/deq)
Zm i (m aq/dea)
C ase
Pin (dBm) CG3fo (dB)
MP3fo
(dBm)
fo
2fo
3fo
fO
2fo
3fo
50/0
50/0
50/0
0/0
0/0
626/0
-1
6.08
5.08
11.16
50/0
50/0
50/0
0/0
0/0
552/0
0
5.59
5.59
11.18
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279
3.iv.b. Idealized Design #2, m*fo Input Reflector and fo Output
Reflector.
3.iv.b.l. Introduction
As discussed in the previous section (S.iv.a), the use o f a simple parallel LC circuit on
the output shorts out the unwanted output harmonics, but does not contribute to any
additional conversion gain. More recent multiplier designs utilize an m*fo reflector on
the transistor input (as discussed in Section S.ii.d) and a fundamental frequency reflector
on the transistor output (as discussed in Section 3.iii.c). Thomas [11] and Huang [63]
utilized a second harmonic input reflector and fundamental output reflector to create
frequency doublers with significant amounts o f conversion gain. The general topology
for this design is shown in Figure 3.129.
M1
Zm
i
Zm2
Lirimfo
Z0 =
m*fo —
Reflctr
R d c= 50O < Elemnt
I—
f^ g e n
—
i
Reflctr
Eem nt
f U ) V n * S in ( c » o t )
::^ V G O
= Vdd
Figure 3.129. M ultiplier Topology Utilizing m*fo Input and fo Output R eflector Networks
C:\Research\Figures\jj m lm 2 ideal_design2 BD_fix.ai
The design process for the above multiplier configuration combines the principles
discussed in Section 3.ii.d and 3.iii.c. A “reflector” at the desired output frequency m*fo
is inserted at the input o f the transistor with a variable length o f transmission line o f
length Linmfo. Similarly, a fundamental frequency reflector is inserted at the transistor
output with a transmission line o f length Loutfo, as shown in Figure 3.129.
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280
The lengths Linmfo and Loutfo, and the input power are simultaneously swept* in an
ADS simulation to determine an optimum conversion gain design. For the simulation,
model C_2 was used in order to take the linear and reverse-breakdown regions into
account. The lengths Linmfo and Loutfo were swept through 180 degrees o f phase for an
input power range o f -10 to +10 dBm for cases B1 and Cl (both o f which are optimum
for 2fo output) and case A1 (which is optimum for 3fo output). Note that for this study
the output load Rl was set to 50 ohms and was not adjusted. The results o f the study are
presented below.
3.iv.b.2. Designs for Maximum 2fo Output
CaseBl(VGO=Vp, Vdd=Vdd„uci)
The first case studied for optimum second harmonic conversion gain was case B1
(VGO=Vp=pinchoff). For second harmonic output a second harmonic input reflector was
utilized with an input transmission line length Lin2 fo as shown in network M l o f Figure
3.129. The input transmission line length Linifo, the output transmission line length
Loutfo, and the input power Pin were simultaneously swept^ to determine the point o f
optimum second harmonic conversion gain. The simultaneous sweep consisted o f a
sweep o f the variables Pin, Linafo, and Loutfo where Pin was varied from -10 to +10 dBm,
Lin2 fo was varied from 2 to
8 8
degrees (with respect to fo), and Loutfo was varied from 10
to 170 degrees so that all combinations o f Pin, Lin2 fo and Loutfo were tested. Out o f this
large dataset o f results the maximum 2 fo conversion gain was obtained from a simple
searching function to find the maximum CG in the dataset. This maximum CG was also
T he id ea o f a sim u ltan eou s sw ee p w a s d efin ed on p age 101. H ere the len gths Linmfo and Loutfo, and the
input p o w er are sw ep t o v e r a certain range such that all com b in ation s o f the three variab les are tested .
^ T he id ea o f a sim u ltan eou s sw ee p w a s defin ed on page 101.
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281
verified by inspection. The resulting optimum values were: Lin2fo=50 degrees; Loutfo= 8 8
degrees; and Pin=-10 dBm, and these values gave a maximum 2fo CG o f 6.7dB (with a
corresponding 2fo output power o f -3.3 dBm). Figure 3.130 shows the second harmonic
conversion gain versus the fundamental output reflector transmission line length Loutfo,
for the optimum value o f Linifo and Pin (note that the responses versus Lin2 fo and Pin will
also be shown in Figure 3.132 and Figure 3.140).
8
6
Lin 2 fjj = 5 0 d e g , Pin = -1 0 d B m
4
£
2
CM
0
(3
O
2
-4
6 ' ------------10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170
■
Loutfo (d e g )
Figure 3.130. Second Harmonic Conversion Gain vs. fo Output Reflector Transm ission Line Length
for Case B l: VGO=Vp, Vdd=Vdd„,i<„ Lin2f„=50deg, Pin=-10dBm
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\iv Harm Gen via Input and Output\jj_ideal_doub_2\
caseBl_modelC2_doub2_ref_swp_zoomed2_CGvsLoutfo_6_7_03.fig
The figure shows a similar 2fo CG versus Loutfo response to the same response when
only an fo output reflector is used (with no input reflector, as presented in Section 3.iii.c,
in Figure 3.121). For output reflector lengths o f less than 83 and greater than 97 degrees,
the fundamental frequency impedance o f the output network
is low. When the
output reflector lengths fall between 83 and 97 degrees, the fundamental frequency
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282
impedance is higher, causing the drain-source voltage to have a large swing. With this
large swing, the transistor begins to transition from saturation into the linear region
(where Yds is less than the knee voltage, Vki) and into the reverse-breakdown region
(where Yds is greater than Yrbd). At this point the fo output reflector begins to have a
drastic effect on the 2fo CG*.
Figure 3.131 shows a zoomed in version o f the response o f Figure 3.130, where the
output reflector length is swept from 80 to 100 degrees. For comparison, the dashed
curve (— ) shows the 2fo CG response versus the output reflector length Loutfo when no
input reflector is used. Note that this dashed curve represents a zoomed in plot o f Figure
3.121 (forPin=-10dBm).
-------------- 1
10
--------- 1------------------------- 1
------ Linzfo = 50 deg
8
I
’ “ ■"'N L
6
------ No 2fo Input Ref!
1
4
I
^
@
CD
O
2
0
-2
___________ - V
/
i
\
■4
I
i
-6
\
V
\
tt
ui7
tf
If
1/
\ ^ //
!
-8
80
/
-/
L
-IQ-
f
..
1
85
90
95
1 0 0
Lout^^ (deg)
Figure 3.131. Second Harmonic Conversion Gain vs. fo Ontput Reflector Transm ission Line Length
for Case B l: Zoom ed in Plot o f Figure 3.130
C:\R esearch\I_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\iv Harm Gen via Input and
Output\jj_ideal_doub_2\zoomed_I0_23_03\modelC_2_caseBI_Loutfo_swp_zoomed2_plot_10_27_03.fig
T he relation sh ip b e tw e en the C G and the output reflector length is explored in m ore detail o n p age 2 9 6
b e lo w .
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283
Observing Figure 3.131 it is clear that the presence o f the input reflector changes the
2fo CG response versus Loutfo. With no 2fo input reflector, the maximum 2fo CG
occurred at an output reflector length (Loutfo) o f 90 degrees. However, with the 2fo input
reflector the maximum 2fo CG is shifted to an output reflector length o f 88.5 degrees.
Furthermore, the overall maximum 2fo conversion gain increases from 1.8 dB (without
the 2fo input reflector) to 7.8 dB (with the optimized 2fo input reflector).
If the transistor input and output were isolated from each other (for example, without
the presence o f Dgd), the relative 2fo CG versus Loutfo response would be expected to be
independent o f the presence o f an input 2fo reflector. Note that this independence is
demonstrated in Appendix B.iii.b.l on page 522. However, since the fo reflector causes
feedback to the transistor gate, the effect the 2fo input reflector has on the 2fo CG versus
Loutfo response is not surprising. Note that the differences between the response with
and without the input reflector are relatively small. The output reflector length giving
maximum 2fo CG only differs by 1.5 degrees between the response with the input
reflector (where Loutfo is 88.5 degrees) and without the input reflector (where Loutfo is 90
degrees). Also, the 2fo CG minimums are shown for both responses at Loutfo values o f
around 84 and 96 degrees. Figure 3.131 shows therefore, that whether or not an input
reflector is used, the optimum Loutfo length occurs at approximately 90 degrees.
Once again, the 90 degree optimum value is that which gives an impedance close to
an open circuit for the output network (M2) at the fundamental frequency. This is
counter to the common belief that this output network should be a short circuit at the
fundamental frequency for optimum output power. For example, Camargo [6 ] states that
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284
“The proper drain termination... is obtained by a short-circuit at the fundamental
frequency...” (on page 67 o f this reference).
Variation o f the input second harmonic reflector length Linafo was shown in Section
S.ii.d to give very little improvement in the second harmonic conversion gain for case B l
(YGO=Vp, Vdd=Vddmid)- This was due to the fact that the maximum 2fo CG occurred
for a range o f smaller input power levels (Pin = -10 to -1 dBm) where there was no
reflected second harmonic content at the gate to work with. However, using the second
harmonic input reflector in conjunction with the fundamental frequency output
reflector results in a significantly different response. A comparison o f the effects o f
Linafo with an optimized Loutfo reflector and with no Loutfo reflector is shown in Figure
3.132.
No Output Reflector
7dB
T3
CN
N o O utput R eflector
CD-2
40
50
Lin,2f„ (d eg)
Lin
Figure 3.132. Second Harmonic Conversion Gain vs. 2fo Input Reflector Transm ission Line Length
for Case B l: VGO=Vp, Vdd=Vddmid, Loutfo=88.5 deg, Pin=-10dBm
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\caseBI_modelC2_doub2_ref_swp_CGvsLin2fo_6_8_03.fig
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285
Figure 3.132 shows that for this design the length Linifo has a very significant effect
on the second harmonic conversion gain. Without the presence o f a fundamental output
reflector, no second harmonic power exists at the gate o f the transistor for a bias at
pinchoff (case B l) and an input power o f -10 dBm. However, the fundamental output
reflector presents a large impedance (approaching an open circuit) which drives the
device into the reverse-breakdown region. As previously shown in Section 3.iii.c, driving
the transistor into the reverse-breakdown region causes feedback into the gate. In this
case, the feedback causes second harmonic content to appear at the gate. This feedback
effect is exhibited in the waveform plot, shown in Figure 3.133. Note that the gate
voltage plot o f Figure 3.133(b) includes the gate voltage response if the reversebreakdown region is not included in the transistor.
0.03
0.03
(a)
^ 0 .0 2
(c)
^
<
to
0.02
to
-
0.01
0.01
-1
0
-0.5
Vgs (V)
0.03
1
0
A/
2
4
6
time (sec)^.jQ-io
-
(d)
'
'
1
t
0 .0 2
0.01
7
0
1
2 3 4
Vds (V)
5
0
1
2 3 4
Vds (V)
5
,x 1 0
With RBD
No RBD
-1
-0.5
Vgs (V)
0
Figure 3.133. W aveform Plot for Design #2, Case B l (Linf„=88.5deg, Lout2fo=50deg, Pin=-10dBm )
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Output\jj_ideal_doub_2\zoomed_10_23_03\modelC_2_caseBl_Pout_ml0_comp_wfplot_10_27_03.fig
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286
As shown in Figure 3.133(d) and (e), the large fundamental frequency load presented
at the output causes a large drain-source voltage swing since the drain voltage goes from
approximately OV to reverse-breakdown. This large swing causes the device to enter the
reverse breakdown region, causing feedback current to flow through the gate-drain diode
(Dgd). This feedback results in the presence o f second harmonic content at the gate which
can be utilized by the second harmonic input reflector. As seen in Figure 3.133(b), when
the reverse-breakdown region is disabled, no distortion o f the gate-source voltage occurs.
Therefore no harmonic power exists at the gate to be utilized by the 2fo reflector.
More insight into the operation o f this optimum design is gained by observing
enlarged versions o f the waveforms shown in Figure 3.133(b), (c), (d) and (e), these are
shown in Figure 3.134, Figure 3.135, Figure 3.137 and Figure 3.136, respectively.
-10
2.25
2.5
2.75
3.25
3.5
_ 3 .7 5
t=b
1
t= c
t=d
4.75
t= e
5.25
5.5
5.75
6.25
6.5
Vgs (V)
Figure 3.134. Enlarged Version o f Figure 3.130(b), Gate-Source Voltage W aveform for D esign!,
C aseB l
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287
0.03
0.025
0.02
t=d
<
0.015
t=h
t=g
0.01
t=a
t=b
t=c
t=e
t=i
t=f
0.005
xIO
time (sec)
-10
Figure 3.135. Enlarged Version o f Figure 3.130(c), Drain Current W aveform for D esign!, C aseB l
C:\Research\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\iv Harm Gen via Input and
Output\ii_ideal_doub_2\zoomed_I0_23_03\modelC_2_caseBl_Pout_ml0_comp_wfplot_partc_10_27_03.fig
xIO
-10
2 .2 5
2.5
2 .7 5
t=b
3 .2 5
3.5
3 .7 5
o
(U
(O
4 .2 5
0)
E
t=d '
t=e
tfg
5 .2 5
5.5
5 .7 5
t=h
6 .2 5
6 .5
0 .5
2 .5
V d s (V)
3 .5
4 .5
Figure 3.136. Enlarged Version o f Figure 3.130(e), Drain-Source Voltage W aveform for D esign!,
C aseB l
C:\R esearch\l_B_I Undrstndng NL Mech\B Stdy Idlzd MdlsMv Harm Gen via Input and
Output\jj_ideal_doub_2\zoomed_10_23_03\modelC_2_caseBl_Pout_ml0_comp_wfplot_parte_10_27_03.fig
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288
0.03
0 . 0 2 5
0.02
t=d
t=h
0.01
t=f
t= c
t=a,i
0 . 0 0 5
t=b
t= e
t=g
Vds (V)
Figure 3.137. Enlarged Version o f Figure 3.130(d), Load-Line Plot for D esign2, C aseB l
C:\Research\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\iv Harm Gen via Input and
Output\jj_ideal_doub_2\zoomed_l 0_23_03\modelC_2_caseB l_Pout_m 10_comp_wfplot_partd_l 0_27_03 .fig
From time a (.275ns) to time b (.35ns) the gate-source voltage (Figure 3.134) is below
the pinchoff voltage (Vp=-0.6V). The corresponding drain current (Ids, Figure 3.135) is
zero between times a and b, which occurs due to the transistor being turned off. The
corresponding drain-source output voltage (Figure 3.137) falls within the saturation
region between times a and b. At time b, the device remains in the saturation region and
remains in saturation from time b to time c. The drain-source voltage during these times
(time b and c) varies from 0.8 to 0.2V. The corresponding gate-source voltage swings
from pinchoff (Vp=-0.6V, at time b) up to -0.5V (at time c), and the transistor begins
conducting again. The drain current begins to rise up from zero at time b, reaching 4mA
at time c. At time c, several things happen. At time c, the drain-source voltage is driven
down to the linear region o f operation (Vds=0.2V<Vki) due to the large load presented
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289
by the fo output reflector. Also at this time (time e), the gate-souree voltage continues to
be driven up. From time c to time d, the gate-source voltage (Figure 3.134) is driven up
to a local maximum o f -O.IV. Also during times c and d, the drain-source voltage
(Figure 3.137) is driven below the knee (Vki=0.5V) and the transistor operates in the
linear region during these times. The corresponding drain current swings sharply upward
from 4mA (at time c) reaching a peak o f 14mA (at time d). During these times (c and d),
the drain current waveform shape is a function o f the Vgs dependence and Vds
dependence, because the transistor is operating in the linear region. Just after time d,
however, the drain-source voltage rises well above 0.5V, and the transistor goes back to
the saturation region o f operation. From time d to time e, the drain-source voltage lays in
the saturation region. The corresponding gate-source voltage swings from -0.2V to the
pinchoff voltage (-0.6V). Here, the corresponding drain current (time d to time e) is
related directly to the gate-source voltage, by Equation (3.13 ) on page 79, repeated here
for convenience as Equation ( 3.58 ):
Vgs < Vp
Ids = ^DSS 1
Vgs
-
Vp < Vgs < 0
( 3 .5 8 )
Vp.
^DSS
Vgs > 0
Equation ( 3.58 ) holds true because the transistor is in the saturation region, where the
drain current is not a function o f the drain-source voltage. To show that the equation
holds true, the calculated drain current can be compared to the simulated result. For
example, at a time midway between time d and e (time=.437ns) the gate-source voltage is
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290
-0.35V. For this voltage, Equation ( 3.58 ) gives a drain current o f 10.4mA, which agrees
exactly with the simulated result shown in Figure 3.135.
At time e, the gate-source voltage is at the pinchoff voltage. From time e to f, the
gate-source voltage swings below pinchoff (-0.6V) and reaches a minimum o f -1.05 V.
Between these times (times e and f), the drain current is zero which corresponds with the
gate-source voltage being below pinchoff. The corresponding drain-source voltage
between times e and f remains within saturation, swinging from 2 to 4 volts.
At time f, the gate-source voltage is -1.05V and the drain-source voltage is 4V.
Utilizing Equation ( 3.35 ) on page 207, the gate-drain voltage at this point is -5.05V.
This gate-drain voltage is large enough so that, if the drain-source voltage is driven
higher, the transistor will enter the reverse-breakdown region o f operation*. Between
times f and g it is seen that the drain-source voltage is driven up from 4V to 4.5V and
during these times the transistor is in the reverse-breakdown region. As a result o f the
transistor being in reverse-breakdown, the output drain current is driven upwards from
0mA (at time f) to 6 mA (at time g). During these times (times f to g) the gate-source
voltage is still below the pinchoff voltage. It is apparent, therefore, that the output
current observed in Figure 3.135 (from time f to g) is due entirely to the reversebreakdown o f the gate-drain diode.
At time g, the gate-source voltage has once again been raised up to the pinchoff
voltage (Vp=-0.6V). From time g to time h the gate-source voltage rises from pinchoff to
a local maximum o f -0.45V. During these times (time g to h), the drain-source voltage
reaches a maximum o f 4.65V and begins to drop, reaching 4.4V at time h. With this
* S e e E qu ation ( 3 .33 ) and the d isc u ssio n on p age 181 regarding reverse-b reakd ow n o f the gate-d rain
d iod e.
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291
large drain-source voltage level, the transistor remains in reverse-breakdown during these
times (time g to h). From time g to time h, the corresponding drain current shows a
significant amount o f distortion. The drain current rises, reaches a local maximum o f
7.5mA (at time = .54ns), drops to a local minimum o f 6 mA (at time=.57ns) and begins to
rise again, reaching 7mA (at time h).
At time h, the drain-source voltage has reached 4.4V. From time h to time i, the drainsource voltage drops out o f the reverse-breakdown region and goes back into saturation.
The corresponding gate-source voltage (from times h to i) drops from -0.45V to pinchoff
(-0.6V). The corresponding drain current (from times h to i) also drops, from 7mA down
to zero. At time i, the process begins to repeat.
Figure 3.136 shows the load-line trajectory superimposed on the DC IV curves. The
figure shows how the Ids current versus Vds voltage relationship varies over time.
Between time a and b the load-line varies in a horizontal line. The drain current is
clipped at zero and the drain voltage increases from 3.5 to 0.5V. At time b, the transistor
remains in the saturation region, but the drain current is driven up from zero (at time b) to
4mA at time c. This is represented by the diagonal, straight load-line shown between
times b and c. At time c, the transistor transitions into the linear region. Between times c
and d, the load-line flows upward into the linear region. During this time, the drainsource current begins to quickly increase rising to a maximum o f 14mA at time d. The
corresponding drain-source voltage (between times c and d) is constrained close to the
knee voltage (0<Vds<0.5V). From time d to time e, the load-line follows a diagonal
through the saturation region. The load-line between these times (times d and e) is
parallel to the load-line between times b and c. The output current drops from 14mA at
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
292
time d to zero at time e. The corresponding voltage rises from the knee (0.5V) at time d
to 2.4V at time e. Between times e and f, the drain current is zero, but the drain-source
voltage continues to rise from 2.4V (time e) to 4V (time f). This section o f the load-line
(from times e to f) is again a horizontal line. At time f the device enters reversebreakdown. Between times f and g the load-line travels into the reverse-breakdown
region and the drain current shows an increase from zero to 6 mA. From time g to time h,
the device remains in reverse-breakdown. The load line between these two times is very
distorted, corresponding with the large amount o f distortion shown in the drain current
waveform shown in Figure 3.135. While in the reverse-breakdown region, the drainsource current is limited to a voltage range between 4 and 4.6V. At time h, the transistor
leaves the reverse-breakdown region as the drain-source voltage decreases. From time h
to time i, the drain-source voltage drops from 4.5V to 3.5V. During this time the output
current drops down from 7mA (time h) to zero (time i).
Perusal o f the waveforms in Figure 3.134, Figure 3.135, and Figure 3.136 above gives
a greater understanding o f the distortion caused by the input 2 fo and output fo reflector.
However, the resulting waveform shapes are very complex and it is not immediately
apparent how the distortion o f the waveforms changes the harmonic output. By
observing the Fourier Series representation o f the Vgs waveform (Figure 3.134), the Ids
waveform (Figure 3.135), and the Vds waveform (Figure 3.136), the effect o f utilizing
the input and output reflector networks on harmonic generation can be understood more
thoroughly. Figure 3.138 shows the Fourier Series representations of: (a) the gate-source
voltage waveform (of Figure 3.134); (b) the drain current waveform (o f Figure 3.135); (c)
the drain-source voltage waveform (of Figure 3.136). These are shown as the diamond
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293
(♦) values in Figure 3.138. Figure 3.138 also includes the harmonic content o f Vgs, Ids,
and Vds when:
•
No input or output reflectors are used at all. Shown as the triangular ( A ) values
in the figure.
•
Only the 2fo input reflector is utilized, and the output network (M2) provides a
simple 50 ohm load at the transistor output. Shown as the square (■) values in the
figure.
•
Only the fo output reflector is utilized, and the input network (M l) provides a
simple 50 ohm load at the transistor input. Shown as the circular ( • ) values in the
figure.
i
.x 1 0
0.7
I-------------------------1----------------------- 1 .....................
0.5
i(c ) Drair -S o u r c e V o lta g e
(b) Drain C urrent
(a) G a te -S o u r c e V o lta g e
♦ Both Rflctrs
A No Reflctrs
■ Input Refl Only
• Output Refl Only
i
r
♦
i>
> 0 .4
D)
0.2
0.1
I
I
;;
I
3
u
6
Freq (GHz)
---------- --------
.
9
xIO®
3
6
Freq (GHz)
9
x10®
--------------1 .
^‘ i1 1
3
6
Freq (GHz)
9
x IO
9
Figure 3.138. Harmonic Plots for Ideal Doubler Design#2, Case B l, Various Reflector C om binations
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\iv Harm Gen via Input and
Output\jj_ideal_doub_2\wf_fs_comp_l l_2I_03\caseBI_doub2_fscomp_plot_I l_24_03.fig
Table 3.11 below shows a summary o f the results from Figure 3.138.
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294
Table 3.11. Sum mary o f Results for Harmonic Plot for Ideal Doubler Design#2, C aseB l
(a) G a te - S o u rc e V o lta a e IVasI (VI
3fo
2fo
fo
N o R efle cto rs
( A)
Botfi R e fle c to rs
(♦)
Input R e fle c to r
Onlv (■)
O u tp u t R e fle c to r
O n lv f* )
(b) D rain C u rre n t lldsl (mA)
2fo
fo
3fo
(c) D ra ln -S o u rc e V o lta a e IVdsI (V)
2fo
3fo
fo
0 .2 0 0
0 .0 0 0
0 .0 0 0
4 .1 6 0
1 .7 6 0
0 .0 0 0
0 .2 1 0
0 .0 8 8
0 .0 0 0
0 .1 4 0
0 .3 3 0
0 .0 4 6
1 .6 4 0
4 .3 2 0
1 .9 8 0
2 .3 4 0
0 .2 2 0
0 .0 9 9
0 .2 0 0
0 .0 0 0
0 .0 0 0
4 .1 6 0
1 .7 6 0
0 .0 0 0
0 .2 1 0
0 .0 8 8
0 .0 0 0
0 .1 2 0
0 .0 7 1
0 .0 4 9
1.2 5 0
2 .3 7 0
2 .5 4 0
2 .3 9 0
0 .1 2 0
0 .1 3 0
C :\R esearch\l_B _l Undrstndng NL Mech\B Stdy Idlzd M dls\iv Harm Gen via Input and
O utput\jj_ideal_doub_2\w f_fs_com p_Il_2I_03\caseB l_C l_doub2_fscom p_table_i I_24_03.sxc
Figure 3.138(a) and Table 3.11(a) show the Fourier Series representation o f the gatesource voltage waveforms previously shown in Figure 3.134, where a 2fo input and fo
output reflector has been used to optimize the 2fo CG. The figure (and table) also
includes the Fourier harmonic signals when: no reflectors are used; only the input
reflector is used; only the output reflector is used.
Figure 3.138(a) shows that when no reflectors are used (shown as the ( A ) values), the
gate-source voltage is a simple sinusoid which contains fundamental frequency content.
The addition o f the input reflector (shown as the (■) values) does not change the gatesource voltage harmonic levels. As previously discussed above, this occurs because there
is no 2 fo power present at the gate o f the transistor to be manipulated by the 2 fo input
reflector. However, when the output reflector is utilized by itself (with no input reflector,
shown as the ( • ) values), the gate-source voltage harmonic content changes significantly
(compared to the case when no reflectors are used). As previously shown in Section
3.iii.c.3 (page 254) this change occurs because o f the large fo impedance at the output
which causes the transistor to enter reverse breakdown, and the subsequent feedback to
the gate. As Figure 3.138(a) and Table 3.11(a) show, the output Vgs drops from 0.2V
(with no reflectors) to 0.12V (with the fo output reflector). The figure (and table) also
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295
shows the presence o f 2fo and 3fo content in Vgs when the output reflector is used,
compared to none with no reflectors present.
When both the input 2fo and output fo reflectors are utilized, the gate-source voltage
shows very significant harmonic content. The output fo reflector provides 2fo power to
the gate through feedback. The input 2fo reflector then provides a large 2fo impedance at
the transistor gate, which causes a large 2fo gate-source voltage magnitude o f 0.33V.
Figure 3.138(b) and Table 3.11(b) show the drain current output signals corresponding
to the gate-source voltage signals o f Figure 3.138(a). When no reflectors are used
(shown as the ( A ) values), the drain current exhibits significant fo and 2fo content
(|Idsfol=4.16mA, |Ids2fo|=1.76mA). As previously stated, the input reflector by itself (the
(■) values in Figure 3.138(b)) does not change the circuit response. The response with
the input reflector input reflector only is equivalent to the response when no input
reflector is utilized. The output reflector by itself (the ( • ) values) causes the fo drain
current to drop from 4.16mA (without reflectors) to 1.25mA (with the output reflector).
This drop in the fundamental frequency output current is consistent with the fo output
impedance being an open circuit. As discussed in Section 3.iii.c.3 (page 254), the open
circuiting o f the fundamental frequency at the output also causes the device to make
transitions between the linear, saturation and reverse-breakdown regions. This causes a
significant change in the 2fo and 3fo drain current harmonic content. In particular, the
2fo drain current increases from l.'76m A (without reflectors) to 2.37mA (with the output
reflector). With both the input and output reflectors (shown as the (♦) values), this 2fo
drain current is increased even further (4.32mA). The increase in the 2fo drain current
level from 2.37mA (with only the output reflector) to 4.32mA (with both reflectors)
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296
corresponds with the significant increase in the 2 fo gate-source voltage magnitude from
0.071V (with only the output reflector) to 0.33V (with both reflectors).
Figure 3.138(c) and Table 3.11(e) show the drain-source voltage output signals
corresponding to the gate-source voltage signals o f Figure 3.138(a) and the drain current
signals o f Figure 3.138(b). With no reflectors ( A) , the drain-source voltage levels are
low at all three harmonics (|Vdsfo|=0.21V, |Vds2fo|=0.088V, |Vds3 fol=0 V). For reasons
previously discussed above, the input reflector (■) does not change the circuit response
and the same drain-source voltage levels occur with the input reflector as when no
reflectors are used. When utilizing only the output reflector (•), the drain-source
harmonics are significantly different from the case when no reflectors are used. The
large fo impedance from the output reflector causes a very large fo drain-source voltage
level (|Vdsfo|=2.39V). The output reflector also causes significant changes in the 2fo and
3fo drain-source voltage level. In particular, the 2fo drain-source voltage increases from
0.088V with no reflectors, to 0.12V when the output reflector is used. When both
reflectors are used (♦), the change in the 2 fo drain-source voltage level is even more
pronounced, reaching 0.22V. Overall Figure 3.138(c) shows that the use o f a 2fo input
and an fo output reflector causes a large increase in the 2 fo drain current and 2 fo drain
voltage level. As a result, the 2fo CG (and corresponding output power level) is greatly
improved.
Relationship Between Load-Line and Variation in 2fo CG
In Figure 3.130, it was shown that variation in the output reflector length Loutfo has a
significant effect on the 2fo CG. It was previously stated that this output reflector causes
changes in the CG only when it causes the device to make transitions between the linear.
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297
saturation, and reverse-breakdown regions o f operation. By observing the load line
trajectory for several different output reflector lengths (Loutfo), the transistor is shown to
go from making significant transitions between the linear, saturation, and reversebreakdown regions to operating only within the saturation region. This principle is
shown in Figure 3.139.
0.025
D C IV, VG O =Vp
D C IV, VGO=Vm id
D C IV, VGO=Vfwd
CurveA, Loutf^=88.5deg
0.02
Curves, Lout^jj=84deg
C u rveA
CurveC, Loutjjj=40deg
CurveD, Lou^jj=Odeg
0.015
M
-a
^ u rveB
0.01
C u rveA
-
0.005 C u rveD
C u rv e B
O'l a ' O 'OB
Vds (V)
Figure 3.139. Load-line Trajectory Comparison for Various Output R eflector Lengths (Loutf„)
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\iv Harm Gen via Input and
Output\jj_ideal_doub_2\caseB l_LLsw p_l 1_18_03\modelC_2_caseBI_ideal_doub2_LLswp_comp_pIot_l I_18_03.fig
This figure shows the load-line trajectory o f case B l (VGO=Vp, Vdd=Vddmid,
Pin=-10dBm) for differing Loutfo values o f 88.5, 84, 40 and 0 degrees. When the output
length Loutfo is 88.5 degrees (very close to an open circuit), the transistor is shown to
operate in the linear and reverse-breakdown regions over a large portion o f the trajectory
(Curve A). As the length is reduced, the impedance o f the output network at the
fundamental frequency |ZM2 |fo drops (note that this was previously shown in Figure 3.108
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298
on page 237) and the drain-source voltage swing is decreased. The reduced drain-source
voltage swing results in the transistor spending less time in the linear and reversebreakdown regions o f operation. When Loutfo is equal to 84 degrees (Curve B), the
device operates almost entirely in the saturation region (0.5V<Vds<4.5V). When Loutfo
is reduced further, the drain-source voltage swing decreases so much that the device
operates purely in the saturation (shown in Figure 3.139 when Loutfo = 40deg, Curve C).
When this occurs, the transistor is no longer making nonlinear transitions into the linear
and reverse-breakdown regions, and the output reflector no longer contributes to the
higher order harmonic output. When Loutfo is equal to 0 degrees (Curve D), the
fundamental frequency impedance is
0
(a short circuit) and the load-line becomes
approximately vertical.
Conversion Gain Response Versus Input Power
The second harmonic conversion gain versus input power response o f the optimized
case B l design (VGO=Vp, Vdd=Vddmid, Loutfo=88.5 deg, Lin2fo=50 deg) is shown in
Figure 3.140. The figure also includes the corresponding output power response.
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299
— C G 2 fo
— P out2fo
(D
O
-10
-1 0
Pin (dBm)
Figure 3.140. Conversion Gain vs. Input Power Plot for Design #2, Case B l (Loutfo=88.5 deg,
Lin2f„=50deg)
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Output\jj_ideal_doub_2\maxMP_10_27_03\caseBl_modelC2_doub2_opt_CG2fopiot_I0_27_03.fig
The figure shows a similar trend as seen in Section 3.iii.c. Once again it can bee seen
that in maximizing the conversion gain, the output power has been driven down to an
unreasonable value (Poutafo = -3.7dBm at Pin = -lOdBm). The solution to this problem is
to redesign the doubler for maximum multiplier power (MP).
To create a doubler with maximum 2fo MP, the simultaneous sweep described on
page 280 was repeated. This time, the point o f maximum MP was determined. The
maximum MP was 6.12 dBm, which occurred for: Pin = -4dBm; Loutfo = 94deg; Linafo =
46deg. Figure 3.141 shows the 2fo MP versus input power response for the optimum
reflector lengths described above. The figure also includes the 2fo CG and output power.
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300
MP2fo
C G 2fo
Pout2fo
-10
-10
Pin (dBm)
Figure 3.141. M P vs. Input Power Plot for Design #2, Case B l (Loutf„=94deg, Lin2f„=46deg)
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modelC_2_caseB_Loutfo_Lin2fo_Mx_MG2fo_Pout_vs_Pin_I0_28_03.fig
At the point o f maximum 2fo MP, a 5.1 dB 2fo conversion gain and 1.1 dBm 2fo
output power is shown. In comparison with the optimum conversion gain design, which
gave a 6.7 dB 2fo CG and a -3.3 dBm 2fo output power, the optimum MP design results
in an improved output power while retaining a large 2fo CG.
Case C l (VGO=Vfwd, Vdd=Vdd„ad)
For case C l, the effects o f variation in the input second harmonic reflector length
(Lin2 fo) and output fundamental reflector length (Loutfo) were also studied. The input
transmission line length Linifo, the output transmission line length Loutfo, and the input
power Pin were simultaneously swept to determine the point o f optimum second
harmonic conversion gain. Figure 3.142 shows the second harmonic conversion gain
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301
versus the output fundamental reflector length for the optimum value o f second harmonic
input reflector length (Linafo = 47 degrees) and input power (Pin=-10dBm, Vg=0.2V).
T3
CM
100
70
110
120
130
Loutfo (deg)
Figure 3.142. Second Harmonic Conversion Gain vs. fo Output Reflector Transm ission Line Length
for Case C l for Pin = -lOdBm, L in lfo = 47deg
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caseCl_modelC2_doub2_ref_swp_zoomed3_CGvsLoutfo_6_9_03.fig
Similar to case B l, the optimum fundamental output reflector length occurs at around
90 degrees, which corresponds to an open circuit for the output network M2. The
optimum point is also close to that shown in Section B.iii.c, where the optimum Loutfo
was calculated using no reflector on the input. This suggests that the optimum output
Loutfo value is independent o f the choice o f input second harmonic reflector length. The
second harmonic conversion gain response as a function o f the input second harmonic
reflector length (Lin2 fo) is shown in Figure 3.143.
As Figure 3.143 shows, the input second harmonic reflector length has a significant
effect on the second harmonic conversion gain. The optimum value occurs for a value
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302
close to 45 degrees (with respect to the fundamental frequency), representing an open
circuit at the second harmonic for the input network M l. This corresponds closely to the
optimum value when no reflector is used on the output, as presented in Section B.ii.d. As
a result, the optimum choice o f second harmonic reflector is also independent o f the
output reflector length for this case.
5.5
4.5
■a
2.5
Figure 3.143. Second Harmonic Conversion Gain vs. 2fo Input Reflector Transm ission Line Length
for Case C l for Pin = -lOdBm, Loutf„ = 92deg
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caseC l_modelC2_doub2_ref_swp_zoomed4_CGvsLin2fo_6_9_03 .fig
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303
0.03
0.03
^
0 .0 2
«
-
0.01
(C)
0.03
I
M
m
^ 0.01
(d);
. 0.02
tr
w
-
0.01
1
..1
0 .6 -0 .4 -0 .2
loVgs (V)
0
0
'
, x10
(b)
o2
(U
CO
1
time (sec) ^„-io
2
3
4
5
4
5
y d s (V)
^xIO
<
1^4
1
- —'
With RBD
NoRBD
<
- 0 .6 -0 .4 -0 .2
0
Vgs (V)
0
1
2
3
Vds (V)
Figure 3.144. W aveform Plot for Design #2, Case C l (Linfo=92deg, Lin2fo=47deg, Pin=-10dBm )
C:\R esearch\I_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\iv Harm Gen via Input and
Output\jj_ideal_doub_2\zoomed_10_23_03\modelC_2_caseCl_Pout_ml0_comp_wfplot_10_28_03.fig
Figure 3.144 shows the waveform plot corresponding to the optimum second
harmonic conversion gain described above. As the figure shows, the optimum
conversion gain occurs for an output stub length which results in the device entering the
reverse breakdown region. In comparison, Figure 3.144(b) also shows the gate-source
waveform response when the reverse-breakdown region o f the transistor is disabled. As
shown in the figure, when the device enters reverse-breakdown significant gate-source
voltage occurs. This occurs as current flows into the gate through the gate-drain diode
(as previously described in detail on page 242). Once again, more insight into the
operation o f this optimum design is gained by observing enlarged versions o f the
waveforms shown in Figure 3.144(b), (c), (d) and (e), these are shown in Figure 3.145,
Figure 3.146, Figure 3.148, and Figure 3.147 , respectively.
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304
-10
0 . 5
— With RBD
— No RBD
2 . 5
t=a—
t=b
oj 3 . 5
4 . 5
5 . 5
t=f
- 0 . 6
- 0 . 5
- 0 . 4
t=g
- 0 . 3
- 0 . 2
0.1
- 0 . 1
Vgs (V)
Figure 3.145. Enlarged Plot o f the Gate-Source Voltage W aveform for Design2, C aseC l
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m odelC_2_caseCI_Pout_ml0_comp_wfpIot_partb_10_28_03.fig
0 . 0 3
t=a
f=b
t=c
t=d
t=g
0 . 0 2 5
0.02
<
0 . 0 1 5
t=e
0.01
0 . 0 0 5
time (sec)
xIO
-10
Figure 3.146. Enlarged Plot o f the Drain Current W aveform for D esign!, C aseC l
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m odelC_2_caseCl_Pout_ml0_comp_w fylot_partc_10_28_03.fig
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305
x10
- 10
0.5
t=a
2.5
0
t=b
) 3.5
4.5
t=e
t=d
t=c
5.5
t=g
t=f
6.5
0.5
0
1.5
1
2.5
2
3
3.5
4
4.5
5
5.5
Vds (V)
Figure 3.147. Enlarged Plot o f the Drain-Source Voltage W aveform for D esign!, C a s e d
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m odelC_2_caseCl_Pout_ml0_comp_wIplot_parte_10_28_03.fig
0.03
t=a,g
t=b
0.025
t=f
t=c
0.02
CO
t=d
0.015
T3
t=e
0.01
0.005
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Vds (V)
Figure 3.148. Enlarged Plot o f the Load-Line Trajectory for D esign!, C aseC l
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modelC_2_caseCI_Pout_ml0_comp_wfplot_partd_I0_28_03.fig
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306
With reference to Figure 3.145, Figure 3.146, and Figure 3.147, perusal o f the
waveforms is very informative. As previously conducted for case B1 above, the input
gate-source voltage, output drain current, and output drain-source voltage are explored
for case C l at several points in time, denoted as times a, b, c, d, e, f and g in all the
enlarged figures. Between time a (.29 ns) and time b (.35 ns) the gate-source input
voltage (Figure 3.145) is clipped at zero volts due to forward conduction o f the gatesource diode. Note that this is also the gate-source voltage seen in the absence o f
reverse-breakdown. The drain output current (Figure 3.146) during these times follows
the gate-source voltage and is therefore clipped at 25mA. The corresponding drainsource output voltage (Figure 3.147) falls within the saturation region (Vki=0.5,
Vrbd=4.5V) between time a and time b. At time b (.35 ns) when Vds=0.5V, the drain
voltage is driven into the linear region due to the load presented by the fo reflector. This
causes a dramatic decrease in the output current as the drain voltage is driven down to
almost OV (see Figure 3.146). Between time b (.35 ns) and time c (.45 ns) the gatesource voltage is still clipped and equal to the gate-source voltage when no reversebreakdown region is present. However, from Figure 3.146 the drain current diverges
from the clipped trajectory and instead decreases, reaches a local minimum, and begins to
rise again between these times. This response in the drain current corresponds exactly
with the drain-source voltage being driven into the linear region, reaching a minimum at
0.3V, and then rising back up towards the saturation region (at time c). When the drain
voltage reaches the saturation region at time c (.45ns), the output drain current (Figure
3.146) begins to be clipped at 25mA again. Between time c (.45 ns) and time d (.47 ns),
the gate-source voltage (Figure 3.145) continues to be clipped at 0 V. The drain current
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
307
is clipped at 25mA corresponding to the gate-source voltage clipping at zero volts. Here,
the drain-source voltage has left the linear region and again falls within the saturation
region. At time d (.47ns) the gate source voltage is driven down by the AC input
generator, now the voltage begins a sinusoidal path between times d (.47ns) and e (.53ns).
The drain current during these times (times d and e) continues to follow the gate-source
voltage and also begins to follow a sinusoidal path. The corresponding drain-source
voltage during these times (times d and e) remains in the saturation region. However, at
time e (.53ns) the drain voltage reaches the reverse-breakdown region. Here the output
current begins a dramatic increase. This is due to reverse-breakdown o f the gate-drain
diode, and the large amount o f current which flows from the drain o f the transistor back
towards the gate. This feedback is illustrated by the distortion in the gate-source voltage
waveform, which is shown to begin at time e (.53ns) and continue from time e (.53ns) to
time f (.58ns). Between these times e and f the output drain current increases, reaches a
local maximum, and begins to decrease again. This response in the current corresponds
exactly with the drain voltage being driven into the reverse breakdown region, reaching a
maximum o f approximately 5V, and then dropping back into the saturation region. At
time f (.58ns), the drain-source voltage has dropped to 4.3V, leaving the reversebreakdown region. From time f (.58ns) to time g (.62ns) the gate-source voltage no
longer shows distortion, and once again corresponds to the voltage with no reversebreakdown region present. The drain-current between these times again becomes
sinusoidal, corresponding to the gate-source voltage. At time g (.62ns) the process begins
to repeat.
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308
As previously discussed, Figure 3.137 shows the load-line trajectory superimposed on
the DC IV curves. The figure shows how the Ids current (Figure 3.146) versus Vds
voltage (Figure 3.147) relationship varies over time. Between time a and b the load-line
varies in a horizontal line, with the current being clipped at a constant value o f 25mA and
the voltage decreasing from 3.5V to 0.5V. At time b, the transistor transitions into the
linear region. Between times b and c, the load-line flows down into the linear region.
During this time, the drain-source current begins to quickly decrease dropping to a
minimum o f 15mA and then rising back up to 25mA at time c. The corresponding drainsource voltage (between times b and c) is constrained close to the knee voltage
(0<Vds<0.5V). From time c to time d, the load-line again follows a horizontal path, as
the drain current is once again clipped at 25mA and the drain-source voltage increases
from 0.5 to 1.5V. From time d to time e, the load-line begins following a straight line
diagonally through the saturation region. The output current drops from 25mA at time d
to 15mA at time e. The corresponding voltage rises from the I.5V at time d to reversebreakdown (4.5V) at time e. At time e the devise enters reverse-breakdown. Between
time e and f the load-line travels into the reverse-breakdown region and back out again.
During this time the output current rises up to a maximum o f 22mA and then falls down
to 19mA at time f. The corresponding voltage during these times (times e and I) is
constrained close to the reverse-breakdown voltage (4.5<Vds<5V). At time f, the device
has left the reverse-breakdown region. The load-line follows on a straight line diagonally
through the saturation region from time f to time g. The load-line between these times
(times d and e) is parallel to the load-line between times d and e. As previously stated
above, at time g, the process begins to repeat.
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309
As was conducted for case B l, for case C l the Fourier Series representation o f the
waveforms o f Figure 3.145, Figure 3.146, and Figure 3.147 are analyzed to gain a better
understanding o f the effects o f the input and output reflector networks. This
representation is shown in Figure 3.149 below. In Figure 3.149, part (a) shows the gatesource voltage harmonics, part (b) shows the drain current harmonics, and part (c) shows
the drain-source voltage harmonics. For each part (a, b and c) o f the figure, the
harmonics are shown when:
•
Both the 2fo input and fo output reflectors are used. Shown as the (♦) values.
•
No input or output reflectors are used. Shown as the triangular ( A ) values.
•
Only the 2fo input reflector is utilized. Shown as the square (■) values in the
figure.
•
Only the fo output reflector is utilized. Shown as the circular ( • ) values in the
figure.
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310
0.2
0 .0 2 5 p —
(a) G a te ■Source / o l t a g e |
(b) Dl-ain C u rren t
1(c) Dralr -S o u r c e V o lta g e
. j ^
0.02
^
t
Both Rflctrs
‘
No Reflctrs
11
-0 .0 1 5
O)
I
(0
------------ L
0.1
O) .
D)
CD
............ 1 1
I
Input Ref! Only
^
Output Refl Only
>
U)
w
-
0.01
1
'IF
--------------
---------
I
‘
------------- r
0 .0 0 5
1
i
-
i
m
1
3
6
Freq (GHz)
9
x IO
3
g
6
'
9
i ^
3
Freq (GHz)
I
6
9
Freq (G Hz)
x IO
Figure 3.149. Harm onic Plots for Ideal Doubler Design#2, Case C l, Various R eflector C om binations
C:\Research\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\iv Harm Gen via Input and
Output\jj_ideal_doub_2\wf_fs_comp_l 1_2 l_03\caseCl_doub2_fscom p_plot_l l_24_03.fig
Table 3.12 is a summary o f the results from Figure 3.149.
Table 3.12. Sum mary o f Results for H armonic Plot for Ideal Doubler Design#2, C aseC l
(a) G a te - S o u rc e V o lta a e IVasI (V)
3fo
2fo
fo
No R eflecto re
(A )
B o th R e fle c to rs
(♦ )
Input R e fle c to r
Onlv (■)
O utp u t R e fle c to r
Onlv ( • )
(b) D rain C u rre n t IldsI (mA)
2fo
fo
3fo
(c) D ra ln -S o u rc e V o lta a e iV dsi (V)
2fo
3fo
fo
0 .1 0 6
0 .0 4 2
0 ,0 0 2
4 ,4 3 0
1 ,7 6 0
0 ,0 8 7
0 ,2 2 0
0 ,0 8 8
0 ,0 0 4
0 .0 9 5
0 .0 4 8
0 .0 1 4
1 ,7 6 0
3 ,6 1 0
2 ,7 1 0
2 ,5 2 0
0 .1 8 0
0 ,1 4 0
0 .1 2 0
0 .0 7 3
0 ,0 2 5
5 ,1 0 0
3 ,0 6 0
1,0 3 0
0 ,2 5 5
0 ,1 5 0
0 ,0 5 1
0 .0 9 3
0 .0 3 3
0 ,0 1 3
1,7 6 0
3 ,2 6 0
2 ,6 4 0
2 ,5 2 0
0 ,1 6 0
0 ,1 3 0
C:\Research\l_B_I Undrstndng NL Mech\B Stdy Idlzd Mdls\iv Harm Gen via Input and
Qutput\jj_ideal_doub_2\wf_fs_comp_l l_21_03\caseBl_Cl_doub2_fscomp_table_l l_24_03.sxc
Figure 3.149(a) and Table 3.12(a) show the harmonic content o f the gate-source
voltage. When no reflectors are used ( A ) a significant fo and 2fo harmonic voltage level
is present at the gate. In particular, the 2fo gate-source voltage is 0.042V. As previously
shown in Section 3.ii.a.5 (page 82), when the transistor is biased at forward conduction
(as in this case, case C l) the gate-source voltage is a half-wave rectified sinusoid,
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9
311
containing large second harmonic content. When the input reflector is introduced (shown
as the (■) values) the second harmonic content is significantly increased (from 0.042V
without reflectors to 0.073V with the input reflector). This increase occurs when the 2fo
input reflector provides a large 2 fo input impedance at the gate o f the transistor.
Interestingly, when only the output reflector is used ( • ) the 2fo gate-source voltage level
drops from 0.042V (with no reflectors) to 0.033V (with the output reflector). This occurs
because the fo output reflector causes nonlinear feedback to the gate. The feedback
signal distorts the gate-source waveform (an example o f this distortion for case C l is
shown in Figure B.34 in Appendix B.ii.c.3, page 499) and this distortion reduces the 2fo
content o f the gate-source voltage signal. The feedback also causes the 3fo gate-source
voltage level to rise from 0.002V (with no reflectors) to 0.013V (with the output
reflector). When both the input and output reflectors are used (♦), the 2fo gate-source
voltage level is only slightly larger then when no reflectors are used (0.048V with the
reflectors compared to 0.042V without them).
The harmonic content o f the drain output current is shown in Figure 3.149(b).
Focusing again on the second harmonic content, the 2fo drain current is 1.76mA when no
reflectors are used (A) . With the input reflector only (■), the 2fo drain current level rises
up to 3.06mA. As discussed in Section 3.ii.d.3 (page 147), this rise corresponds with the
increased 2 fo gate-source voltage level seen when the 2 fo input reflector is used.
When the output reflector is used (•), the 2fo drain current also shows a significant
increase compared to the case when no reflectors are used. Here, |Ids2 fo| is equal to
3.26mA (with the output reflector), compared to 1.76mA (with no reflectors). In this
case, the increased 2 fo drain current level is not attributed to an increased 2 fo gate-source
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312
voltage level. In fact, the 2fo gate-source voltage level drops (Figure 3.149(a)) when
only the output reflector is used. In this case, the increased 2fo drain current occurs
because o f the distortion o f the drain current waveform as it transitions between the
linear, saturation, and reverse-breakdown regions.
When both the input and output reflectors are used (♦) the drain current shows its
largest second harmonic level o f 3.61mA. Here, the 2fo input and fo output reflectors
combine to produce several effects:
1. The output reflector distorts the drain current by causing the transistor to
transition between the linear, saturation, and reverse-breakdown regions.
2. By causing the transistor to enter reverse-breakdown, the output reflector also
causes feedback which distorts the gate-source voltage waveform.
3. The input reflector manipulates the 2fo gate-source voltage, causing an increase in
the 2fo gate-source voltage from 0.033V (with only the output reflector in place)
to 0.048V (with both reflectors in place). This change in the gate-source voltage
level also manipulates the drain output current.
As a result o f these effects, a large 2fo drain current level is achieved.
Figure 3.149(c) shows the drain-source voltage harmonic signals for case C l. As
shown in the figure, with no reflectors ( A ) the drain-source voltage level is quite low
(|Vdsfo|=0.22V, |Vds2fo|=0.088V, |Vds3fo|=0.004V). The addition o f the input reflector (■)
gives a slight inerease in the drain-source voltage harmonic levels (|Vdsfo|=0.255V,
|Vds2fo|=0.15V, |Vds3fo|=0.051V). When the output reflector is introduced (•), however,
a great change in the fundamental frequency drain-source voltage level is seen. The
drain-source voltage level at fo is 2.52V with the output reflector, compared to only
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313
0.22V with no reflectors. As previously discussed, this arises from the open circuiting o f
the fundamental frequency by the output reflector. This large fo drain-source voltage
allows the transistor to enter the linear and reverse-breakdown regions, which causes
distortion o f the drain current. When both reflectors are used (♦), the drain-source
voltage levels are approximately the same as when only the output reflector is used (as
shown in Table 3.12). The 2fo drain-source voltage component is 0.18V when both
reflectors are used, compared to 0.16V with only the output reflector. However, as
previously shown in Figure 3.149(b), the use o f both the input and output reflectors
causes an inerease in the 2fo drain current component. As a result, the 2fo CG is greatly
enhanced by the use o f the 2 fo input and fo output reflectors.
Conversion Gain Response Versus Input Power
The 2fo CG versus input power response for case Cl with the optimum input and
output reflector lengths (Loutfo=92deg, Lin2fo=48 deg) is shown in Figure 3.150. The 2fo
output power response is also shown in the figure. As also noticed in case B l, the
optimum 2fo conversion gain for case Cl also occurs for a very small input power (Pin =
-lOdBm). The resulting 2fo output power is -4.9 dBm. In order to improve this design
by increasing the 2fo output power, the MP is employed.
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314
10
----- CG2fo
----- Pout2fo
i.
0
£CM
0
O
-5
- - - - X
-10
. .
■^-?o
-5
0
\
10
Pin (dBm)
Figure 3.150. Conversion Gain vs. Input Power Plot for Design #2, Case C l (Loutfo=92 deg,
Lin2f„=48deg)
C:\R esearch\l_B _l Undrstndng NL M ech\B Stdy Idlzd Mdls\iv Harm Gen via Input and
O utput\jj_ideal_doub_2\maxM P_I0_27_03\caseCl_modeIC2_doub2_opt_CG2foplot_10_28_03.fig
The simultaneous sweep o f Pin, Loutfo, and Lin2 fo (the sweep process is described in
detail on page 280) was repeated to find the maximum 2fo MP for case C l. This
maximum 2fo MP was 4 dBm for the following optimum parameter values: Pin =
-3dBm; Loutfo = 1 1 0 deg; Lin2 fo= 4 4 deg. Figure 3.151 shows the 2fo MP versus input
power using the above optimum reflector lengths. The figure includes the corresponding
2fo CG and output power.
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315
10
----- M P2fo
8
...... Pout2fo
6
4
E
CD
2
£ 0
CN
@ -2
Q.
-4
-6
-8
----1 0
-5
x
\
0
10
Pin (dBm)
Figure 3.151. M P vs. Input Power Plot for Design #2, Case C l (Loutfo=110deg, Lin2fo=44deg)
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\iv Harm Gen via Input and Output\jj jdcal_doub_2\m axM P_l ()_27_03\
modelC_2caseC_Loutfo_Lin2fo_Mx_M G2fo_Pout_vs_Pin_10_28_03.fig
Figure 3.151 shows that the maximum MP design results in a maximum 2fo CG o f 3.5
dB (at Pin = -3dBm) with a corresponding 0.5 dBm 2fo output power. This design
compares favorably over the maximum CG design, which gave 5.1 dB 2fo CG but only
-4.9 dBm output power.
3.iv.b.3. Designs for Maximum 3fo Output
C a se A l
To test the simultaneous use of a desired harmonic (m*fo) input and fundamental
frequency (fo) output reflector for third harmonic output, a bias midway between
pinchoff and forward conduction was utilized (case A l). The input reflector was chosen
to reflect the third harmonic and its input transmission line length was Linsfo (represented
by Figure 3.129 when m = 3). Just as for the second harmonic case, the input and output
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316
transmission line lengths (Linafo and Loutfo) were simultaneously swept to determine the
point o f maximum third harmonic conversion gain. Figure 3.152 shows the third
harmonic conversion gain versus the output fundamental frequency reflector transmission
line length (Loutfo) at the optimum input power and third harmonic reflector transmission
line length (Pin = -10 dBm, Linsfo = 30.5 deg). As the figure shows, the optimum output
transmission line length once again occurs close to 90 degrees. This was also the case for
the optimum second harmonic conversion gain designs previously shown above.
Furthermore, this optimum point was also obtained in Section 3.iii.c, when an output
fundamental frequency reflector was used independently o f an input reflector. This
suggests that the optimum choice o f fundamental frequency reflector transmission line
length (Loutfo) is independent o f the second harmonic reflector length (Lin2 fo).
-15
-20
-25
-30
80
90
1 0 0
110
120
Loutfo (deg)
Figure 3.152. Third Harmonic Conversion Gain vs. fo Output Reflector Transm ission Line Length
for Case A l for Pin = -lOdBm, Lin3fo = 30.5 deg
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\iv Harm Gen via Input and Output\jj_ideal_trip_2\
caseAl_modelC2_trip2_ref_swp_zoomed2_CGvsLoutfopIot_6_12_03.fig
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317
12.5
CO
7.5
60
Figure 3.153. Third Harmonic Conversion Gain vs. 3fo Input Reflector Transm ission Line Length
for Case A l for Pin = -lOdBm, Loutfo = 89 deg
C :\R esearch\l_B _l Undrstndng NL M ech\B Stdy Idlzd Mdls\iv Harm Gen via Input and Output\jj_ideal_trip_2\
caseA l_m odelC2_trip2_ref_swp_zoomed3_CGvsLin2foplot_6_12_03.fig
Figure 3.153 shows the third harmonic conversion gain versus the input third
harmonic reflector transmission line length at the optimum input power and fundamental
frequency output reflector length (Pin = -lOdBm, Loutfo=89deg).
The optimum choice o f the third harmonic reflector length is also shown to occur at a
point close to the independently obtained optimum (shown in Section 3.ii.d). The
maximum third harmonic conversion gain occurs for a transmission line length close to
30 degrees (Linsfo = 30 deg). As previously discussed, the optimum input and output
networks result in an open circuit. The input network M l gives a very large impedance
at the third harmonic. The output network M2 presents a very large impedance to the
output at the fundamental frequency. Figure 3.154 shows the waveform plot at the point
o f optimum conversion gain (Pin = -lOdBm, Loutfo = 89deg, Linsfo = 30.5deg).
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
318
0.03
0.03
0.03
0.02
0.02
(d)
(a)
0.02
—
__
1
cn
T3
0.01
-----
-0.7
-----
-0.5
1
>
-0.3 -0.1
Vgs (V)
0.01
0.01
-
r i \
0.1
2
4
time (sec)
6
0
2
4
.10 Vds (V)
x IO
(e)
o0
i4
-0.7
-0.5
-0.3 -0.1
V g s (V )
0.1
~ 4 —
2
4
Vds (V)
Figure 3.154. W aveform Plot for Design #2, Case A l (Linfo=89deg, Lin3fo=30.5deg, Pin=-10dBm )
C;\Research\l_B_l Undrstndng NL MechVB Stdy Idlzd MdlsMv Harm Gen via Input and
Output\jj_ideal_trip_2\caseAl_modelC2_trip2_optsngI2_wfplot_6_12_03.fig
As a result o f the large impedance presented to the fundamental frequency at the
output, the device is driven into the reverse breakdown region as exhibited in Figure
3.154 (d) and (e). Figure 3.154 (c) reveals an important feature o f the optimum third
harmonic design using the bias o f case A l . The gate voltage waveform for this case does
not swing very far below the pinchoff region or above the forward conduction region. As
a result, the drain output current does not constitute a double-sided, clipped sinusoid, as
the optimum third harmonic design in Section 3.ii.a did. Thus this design relies on the
input and output reflectors to provide the mechanism for significant conversion gain.
More insight into the improvements provided by the reflectors can be gained by
observing enlarged versions o f Figure 3.154(b), (c), (d) and (e), these are shown in Figure
3.155, Figure 3.156, Figure 3.158 and Figure 3.157, respectively.
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319
x1 0
-10
0.5
t=b,
t=c
2,5
o0 ) >
o3
t=d
t= e
® 3.5
t=f
4 .5
5.5
6 .5
-
0.6
-0.5
-0.4
-0.3
-
0.2
-
0.1
0.1
0
V g s (V )
Figure 3.155. Enlarged Plot o f the Gate-Source Voltage W aveform for D esign!, C aseA l
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caseAI_modelC2_trip2_optsngI2_wfplot_partb_6_I2_03.fig
0.03
t=e
0.025
t=c
0.02
<
0.015
■U
a)
0.01
0.005
t=d,
t=f
0.5
2.5
3
3.5
time (sec)
4.5
5.5
6.5
x IO
-10
Figure 3.156. Enlarged Plot o f the Drain Current W aveform for D esign!, C aseA l
C:\R esearch\l_B_l Undrstndng N L Mech\B Stdy Idlzd MdlsMv Harm Gen via Input and Output\jj_ideal_trip_2\
caseAI_modelC2_trip2_optsngl2_wfplot_partc_6_I2_03.fig
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320
x10
-10
0.5
t=b
t=e
2.5
t=c
t=d
gj 3.5
4.5
t=f
5.5
6.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Vds (V)
Figure 3.157. Enlarged Plot o f the Drain-Source Voltage W aveform for D esign!, C aseA l
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\iv Harm Gen via Input and Output\jj_idea!_trip_2\
caseA l_modelC2_trip2_optsngl2_wfplot_parte_6_l 2_03 .fig
0 .0 3
t=a,g
0 .0 2 5
0.02
t= c
t= e
V 0 .0 1 5
T3
0.01
t=b
0 .0 0 5
t=f
0.5
2.5
3.5
4 .5
Vds (V)
Figure 3.158. Enlarged Plot o f the Load-Line Trajectory for D esign!, C aseA l
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caseAl_modelC2_trip2_optsngl2_wfplot_partd_6_12_03.fig
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321
As previously conducted for case B l and Cl above, perusal o f the waveforms for case
A l is very informative. The waveforms are explored at several points in time, denoted as
times a, b, c, d, e, f and g in all the enlarged figures. Between time a (.08 ns) and time b
(.13 ns) the gate-source input voltage (Figure 3.155) travels from zero to the pinchoff
voltage. Note that for case A l, the gate-source waveform is very distorted on account o f
the input 3fo reflector as well as feedback from the output fo reflector. Also note, as
previously stated above, that the gate-source voltage varies between the pinchoff voltage
(Vp=-0.6V) and forward conduction (Vfwd=OV) without swinging above or below these
values. The drain output current (Figure 3.156) during times a and b swings from the
saturation current (Ids=lDss=25mA) to zero. This current corresponds with the gatesource voltage swinging from zero (where Ids is equal to the saturation current) to
pinchoff (where the transistor is turned off and Ids is zero). The corresponding drainsource output voltage (Figure 3.157) falls within the saturation region (Vki=0.5,
Vrbd=4.5V) between time a and time b. At time b (.13 ns) when Vds=4.5V, the drain
voltage is driven into the reverse-breakdown region due to the load presented by the fo
reflector. This causes a dramatic increase in the output current as the drain voltage is
driven up to a maximum o f around 4.8V (see Figure 3.156) at time c (.18ns). Between
time b (.13 ns) and time c (.18 ns) the drain current increases from 0 up to 18mA. During
these times (times b and c) gate-source voltage begins a sharp increase, going from
pinchoff (-0.6V) up to -0.2V. Similar to previous cases (B l and C l) the sharp changes in
the drain current and gate-source voltage seen for this case are attributed to the device
entering reverse-breakdown, causing large feedback current the gate. At time c, the drain
voltage has reached a maximum o f 4.8V. Between times c (.18ns) and d (.25ns) the drain
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322
voltage begins to decrease, going from the maximum o f 4.8V down to 4.5V. During
these times, the transistor is still in the reverse-breakdown region o f operation. The drain
current begins decreasing from its local maximum o f 18mA at time c and decreases all
the way back down to zero at time d. The corresponding gate-source voltage (from time
c to d) also decreases from its local maximum o f -0.2V at time c and decreases back
down to the pinchoff voltage at time d. At time d, the drain-source voltage is 4.5 V, and
the transistor leaves the reverse-breakdown region o f operation. From time d (.25ns) to e
(.3ns) the drain-source voltage drops from 4.5V to 0.5V and the device operates in the
saturation region. During these times (times d and e) the drain current increases from
zero (time d) all the way back up to the saturation current (Ioss=25mA, at time e). The
corresponding gate-source voltage (time d to e) increases from pinchoff (Vp=-0.6V) up to
zero. At time e, the drain-source voltage has reached the knee voltage (Vki=0.5V). From
time e (.3ns) to time f (.36ns), the drain-source voltage enters the linear region of
operation, dropping from the knee voltage (Vki=0.5V) at time e to a minimum o f 0.2V at
time f. During these times (times e and f), the drain current makes a dramatic decrease,
traveling from 25mA down to a local minimum o f 4mA. The gate-source voltage also
makes a dramatic decrease, going from OV down to -0.3V between times e and f. At
time f, the drain-source voltage has reached a minimum o f 0.2V. From time f (.36ns) to g
(.42ns) the drain-source voltage begins to increase from 0.2V (time f) to the knee voltage
(Vki=0.5V, at time g). The corresponding drain current begins increasing from 4mA
(time f) back up to the saturation current (lDss=25mA, at time g). The corresponding
gate-source voltage also increases, traveling from -0.3V at time f back up to zero volts at
time g. At time g (.42ns) the process begins to repeat.
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323
Figure 3.158 shows the load-line trajectory superimposed on the DC IV curves. The
figure shows how the Ids current (Figure 3.156) versus Vds voltage (Figure 3.157)
relationship varies over time. Between time a and b the load-line varies in a diagonal line
through the saturation region, with the drain current decreasing from 25mA to zero and
the drain voltage increasing from 0.5V to 4.5V. At time b, the transistor transitions into
the reverse-breakdown region. Between times b and d, the load-line flows up into the
reverse-breakdown region. During this time, the drain-source current begins to quickly
increase, rising to a maximum o f 18mA (at time c) and then dropping back down to 0mA
at time d. The corresponding drain-source voltage (between times b and d) is constrained
close to the knee voltage (4.5<Vds<4.8V). From time d to time e, the load-line again
follows a diagonal path, as the drain current is once again clipped at 25mA and the drainsource voltage increases from 0.5 to 1.5V. From time d to time e, the load-line begins
following a straight line diagonally through the saturation region. The output current
increases from 0mA at time d to 25mA at time e. The corresponding voltage drops from
the reverse-breakdown voltage (4.5V) at time d to the knee voltage (0.5V) at time e. At
time e the device enters the linear region. Between time e and g the load-line travels into
the linear region and back out again. During this time the output current drops down to a
minimum o f 4mA at time f and then rises back up to 25mA at time g. The corresponding
voltage during these times (time e to g) is constrained close to the knee voltage
(0.2<Vds<0.5V). At time g, the process begins to repeat.
As previously conducted for the optimum 2fo CG designs (for case B l and case C l),
the Fourier Series components o f the gate-source and drain-source waveforms are
examined for the optimum 3fo CG design (for case A l). Figure 3.159 shows the Fourier
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324
Series representations of: (a) the gate-source voltage waveform (of Figure 3.155); (b) the
drain current waveform (of Figure 3.156); (c) the drain-source voltage waveform (of
Figure 3.157). These are shown as the diamond (♦) values in Figure 3.159. Figure 3.159
also includes the harmonic content o f Vgs, Ids, and Vds when:
•
No input or output reflectors are used at all. Shown as the triangular ( A ) values
in the figure.
•
Only the 3fo input reflector is utilized, and the output network (M2) provides a
simple 50 ohm load at the transistor output. Shown as the square (■) values in the
figure.
•
Only the fo output reflector is utilized, and the input network (M l) provides a
simple 50 ohm load at the transistor input. Shown as the circular ( • ) values in the
figure.
0.02
0 .3 5
(a) G ate i-Source V o lta g e
::
0 .0 1 8
1
^
(c) Drain -S o u r c e V o lta g e
Both Rflctrs
0 .0 1 6
Akk No Reflctrs
0 .0 1 4
H
Input Refl Only
^
Output Refl Only
1
-
1
O
)
(0
D)
™
U
)
CD
>
(b) Drain C u rrent
0 .0121
>
O)
0.01
■<an
(0
-
i>
>
0 .0 0 8
0 .0 0 6
1:
Freq (GHz)
x IO
0 .0 0 4
0.002
u u
0
Freq (GHz)
6
Freq (G Hz)
9
- .9g
x IO
Figure 3.159. Harm onic Plots for Ideal Tripler D esign#!, Case A l, Various Reflector C om binations
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325
Table 3.13 is a summary o f the results from Figure 3.159.
Table 3.13. Sum mary o f Results for H armonic Plot for Ideal Tripler D esign#2, C aseA l
(a ) G a te - S o u r c e V o lta q e |V q s| (V)
No
R e f le c to r s
(A )
B o th
R e f le c to r s
(♦ )
Input
R e fle c to r
O n lv fa )
O u tp u t
R e fle c to r
O n lv f* )
(b ) D ra in C u rre n t jldsi (m A )
(c) D r a ln - S o u r c e V o lta q e jV dsj (V)
fo
2 fo
3 fo
fo
2fo
3fo
fo
2fo
3 fo
0 .2 0 0
0 .0 0 0
0 .0 0 0
8 .3 3 0
0 .0 0 0
0 .0 0 0
0 .4 2 0
0 .0 0 0
0 .0 0 0
0 .1 4 0
0 .0 3 4
0 .2 1 0
0 .9 6 0
0 .7 4 0
9 .5 3 0
2 .7 4 0
0 .0 3 7
0 .4 7 0
0 .2 0 0
0 .0 0 0
0 .0 0 0
8 .3 3 0
0 .0 0 0
0 .0 0 0
0 .4 2 0
0 .0 0 0
0 .0 0 0
0 .1 4 0
0 .0 5 0
0 .0 3 7
0 .9 0 0
0 .4 6 0
4 .7 0 0
2 .5 8 0
0 .0 2 3
0 .2 3 4
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Figure 3.159(a) shows the harmonic content o f the gate-source voltage signal. When
no reflectors are used ( A ) the gate-source voltage is not driven up to forward conduction
and no feedback occurs. As such, when the gate-source voltage signal is purely
sinusoidal and only the fundamental frequency voltage is present. When the 3fo input
reflector is utilized (■), the response is equivalent to when no reflectors are used and the
gate-source voltage signal occurs only at the fundamental frequency (|VgSfo|=0.2V). The
3fo input reflector is ineffective by itself since there is no 3fo signal present at the gate to
be manipulated. When the fo output reflector is used by itself (•), the harmonic levels
change significantly. As shown in Table 3.13, with the output reflector present, the 2fo
gate-source voltage is 0.05V and the 3fo gate-source voltage is 0.037V. This is a
significant amount compared to the case when no reflectors are used, which shows only
fundamental (and no 2fo or 3fo) gate-source voltage. As discussed in Section 3.iii.c.2
(page 229), the optimum output fo reflector causes feedback to the input which distorts
the Vgs waveform. This distortion accounts for the 2fo and 3fo harmonic levels seen in
the gate-source voltage
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326
When both the 3fo input and fo output reflectors are used (♦) the 3fo gate-source
voltage level becomes much larger (|V gS3fo|=0.21V ) then when only the output reflector
is used (|V gS3fo|=0.037V ). This occurs since the input 3fo reflector presents a large 3fo
impedance at the gate.
Figure 3.159(b) shows the drain current harmonic levels corresponding to the gatesource voltage signals shown in Figure 3.159(a). With no reflectors (A) , the drain
current contains only fundamental frequency harmonic content. This occurs for two
reasons:
1. With no manipulation at the transistor output, the drain-source voltage remains in
the saturation region.
2. The gate-source voltage remains above pinchoff and below the forward
conduction voltage.
Due to these reasons, the drain current remains in a region o f operation which is
proportional to the gate source voltage, related by Equation ( 3.13 ) on page 79.
Therefore, since only fundamental frequency gate-source voltage is seen when no
reflectors are used, the corresponding drain current contains only fundamental frequency
current.
The use o f the 3fo input reflector by itself (■) results in the same drain current
harmonic levels as the case without the reflectors. As previously discussed, no 3fo
harmonic voltage exists at the gate for the 3fo input reflector to manipulate. Therefore,
the 3fo input reflector by itself cannot affect the input or output harmonic content.
When the output fo reflector is used by itself ( • ) the transistor is driven into the linear
and reverse-breakdown regions o f operation. The subsequent distortion in the drain
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327
current causes the 2fo (|Ids2fo|=0.46mA) and 3fo (|Ids3 fo|=4 .7 mA) harmonic levels to rise.
The fundamental frequency drain current level is greatly reduced by the fo output
reflector (|Idsfol=0.9mA, compared to 8.33mA with no reflectors) which causes an fo
open circuit at the transistor drain.
With both the 3fo input and fo output reflectors (♦), the 3fo drain current reaches a
large level (|Ids3 fo|=9 .3 mA). This represents an approximate 50% improvement over
when the output reflector is used by itself (where |Ids3 fo|=4 .7 mA). This improvement is a
result o f several effects:
1. The fo output reflector presents a large fo impedance at the drain, eausing the
transistor to make nonlinear transitions between the linear, saturation and reversebreakdown regions. This causes distortion in the drain current which significantly
increases its 3fo harmonic content.
2. In addition to the distortion o f the drain current, the fo output reflector causes
feedback to the gate. As a result, 3fo gate-source voltage is seen where none was
present (with no reflectors)
3. The 3fo input reflector utilizes the 3fo harmonic voltage at the gate provided by
the output fo reflector. The input reflector greatly increases the 3fo level o f the
gate-source voltage, which also provides a further increase in the 3fo drain current
level.
As a result o f these effects, a large 3fo drain current level is achieved.
Figure 3.159(c) shows the harmonic content o f the drain-source voltage signal. With
no reflectors ( A) , only fundamental frequency drain-source voltage exists. The same is
true when only the 3fo input reflector is used (■). When the output reflector is used (•),
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328
the output impedance at the fundamental frequency is approximately an open circuit.
Therefore, the use o f the output reflector greatly increases the drain-source voltage level
at the fundamental frequency (|VdSfo|=2.58V, compared to 0.42V with no reflectors).
This inerease also occurs when both the input and output reflectors are used (♦), where
the fo drain-source voltage level reaches 2.74V. Note that the 3fo drain-source voltage
level also rises, up to 0.47V with both reflectors (where no 3fo is shown without the
reflectors). As a result o f the significant increase in the 3fo drain-source voltage and
current levels, the 3fo CG is greatly improved when both the 3fo input and fo output
reflectors are used.
Conversion Gain Response Versus Input Power
The 3fo CG versus input power response with the optimized reflector lengths (Loutfo
= 89deg, Lin3 fo = 30.5deg) is shown in Figure 3.160. The figure also shows the
corresponding 3fo output power.
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329
— 3 fo C G
— 3fo Pout
CQ
T3
CO
CD
O
-10
-10
Pin (dBm)
Figure 3.160. Conversion Gain vs. Input Power Plot for Design #2, Case A l (Loutf„=89 deg,
Lin3f„=30.5deg)
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Output\jj_ideal_trip_2\maxMP_I0_27_03\caseCl_modelC2_trip2_opt2_CG3foplot_I0_28_03.fig
In the figure, 13.6 dB 3fo CG is achieved at an input power o f -10 dBm. The
corresponding 3fo output power is 3.6 dBm. An interesting trend which did not occur in
previous designs is seen in Figure 3.160. As the input power level drops, the 3fo CG
increases significantly. However, as the Pin is decreased, the 3fo output power remains
relatively constant. This is contrary to previous results (for example the response shown
in Figure 3.140 for the optimum 2fo CG design o f case B l) where as the CG rises (with
decreasing Pin), the corresponding output power quickly decreases. The implications of
the response o f Figure 3.160 is that a maximum 3fo MP, which takes both CG and Pout
into account, may be achieved at an input power less than -10 dBm. Previously the input
power had been constrained to a minimum input power o f -10 dBm, since at this point the
output power would typically become unreasonably low. To examine the response at
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330
lower input power levels, the response o f the optimum 3fo CG design (Loutfo = 89deg,
Lin3 fo = 30.5deg) was re-simulated for an input power range o f -25 to +10 dBm. Figure
3.161 shows the 3fo CG response versus the input power, and includes the 3fo MP and
output power.
MP 3fo
CG 3fo
Pout 3fo
20
m
■D
CO
o
o
-10_
-25
-20
-10
Pin (dBm)
Figure 3.161. Conversion Gain vs. Inpnt Power Plot for Design #2, Extended to Low er Input Power
Levels, Case A1 (Loutf„=89 deg, Lin3f„=30.5deg)
C:\Researoh\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdis\iv Harm Gen via Input and 0utput\jj_ideal_trip_2\m axM P_l 0_27_03\
caseC l_modelC2_trip2_opt2_MP3foplot_EXT_l 0_28_03 .fig
The figure shows that for this design the 3fo CG and MP is significantly increased
when the input power drops below -10 dBm. The design reaches a maximum 3fo CG o f
21.7 dB at an input power o f -22 dBm, with a corresponding -0.3 dBm output power. If
the point o f maximum MP is utilized rather than the maximum CG, the 3fo output power
level becomes more reasonable. A maximum 3fo MP o f 22 dBm occurs at an input
power o f -20 dBm with a corresponding 21 dB CG and 1 dBm output power.
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33 1
The fact that the CG and MP reaches a maximum at such a small input power level is
attributed to the very large impedances at the gate and drain provided by the input and
output reflectors. As discussed in Section 3.iii.c, the fo output reflector (with an
optimized offset length Loutfo=89 deg in this case) provides a nearly open circuit (|ZM2 |fo
=2864 ohms) on the transistor output at the fundamental frequency. Even when a small
input voltage (and correspondingly a small input power) is utilized, this very large
impedance creates a very large drain-source voltage swing. This large swing forces the
device to make transitions from the saturation region into the linear and reversebreakdown regions. As a result large harmonic output power can be generated by a very
small input power signal. Furthermore, as discussed in Section 3.ii.d, the 3fo reflector
provides a near open circuit (IZMibfo =1909 ohms in this case) on the transistor’s input at
the third harmonic. This causes a large increase in the 3fo gate-source voltage magnitude
which can significantly increase the 3fo output current level. The effect o f the very large
impedances provided on the input and output allows a significant 3fo output power level
to be reached, even as the input power level is decreased. It is not surprising, therefore,
that a very large CG and MP can be obtained from a very small input power level.
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3.iv.b.4. Summary of Results
Table 3.14 shows a summary o f the results obtained for case A l, B l, and C l above.
Table 3.14. Sum m ary o f Designs Utilizing Circuit Configuration o f Figure 3.129
(a) D eslans for Optimum 2fo Output:
Zm1 (m a q /d e a )
C ase
C a s e B1
(V G O =V p )
(V d d = V d d „J
C ase C l
(V G O =V fw d )
(V d d = V d d „J
D e s ig n e d
for:
M a x im u m
2 fo C G
M a x im u m
2 fo M P
M a x im u m
2 fo C G
Ma>dmum
2 fo M P
Z m 2 (m aa /d e q )
O u tp u t R e s p o n s e
P o u t2 fo
C G 2 fo (d B )
(d B m )
L in , ,J d e g ’ )
Lout^^ (d e g )
fo
2fo
3 fo
fO
2 fo
3 fo
P in
(d B m )
M P 2 fo
(d B m )
50
88
5 0 /0
2 8 4 /-9 0
5 0 /0
1 4 3 2 /9 0
5 0 /0
5 0 /0
-1 0
6 .7
-3 ,3
3.4
46
94
5 0 /0
1 4 3 2 /-9 0
5 0 /0
7 1 5 /-9 0
5 0 /0
5 0 /0
-4
5,1
1.1
6 ,2
4 6 .7
89
5 0 /0
8 4 2 /-9 0
5 0 /0
2 8 6 4 /9 0
5 0 /0
5 0 /0
-1 0
5.1
-4 .9
0 .2
44
1 10
5 0 /0
1 4 3 2 /9 0
5 0 /0
1 3 7 /-9 0
5 0 /0
5 0 /0
-3
3 .5
0 .5
4
3fo
2 fo
3 fo
P in
(d B m )
[b) D esigns for Optimum 3fo Output;
Z m 2 (m aa /d e g )
Z m l (m a g /d e q )
C ase
C ase A l
(V G O = V m id )
(V d d = V d d „J
D e s ig n e d
for:
M a x im u m
3 fo C G
M a x im u m
3 fo M P
O u tp u t R e s p o n s e
P o u t3 fo
C G 3 fo (d B )
(d B m )
M P 3 fo
(d B m )
L in 3 ,.(d e g ’ )
L o ut,„ (d e g )
fo
2fo
3 0 .5
89
5 0 /0
5 0 /0
1 9 0 9 /-9 0 2 8 6 4 /9 0
5 0 /0
5 0 /0
-2 2
2 1 ,7
-0 .3
2 1,4
3 0 ,5
89
5 0 /0
5 0 /0
1 9 0 9 /-9 0 2 8 6 4 /9 0
5 0 /0
5 0 /0
-2 0
21
1
22
fO
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3.iv.c. Idealized Design #3, m*fo input Refiector and fo Output
Reflector with Secondary n*fo Input and Output Reflectors.
3.iv.c.l. Introduction
In addition to the use o f a fundamental frequency output reflector and an input
reflector at the desired harmonic (m*fo), input and output reflectors at the unwanted,
higher order harmonics may be utilized to further improve conversion gain and output
power. For example, the frequency doubler o f Section 3.iv.b, which contains an output
reflector at the fundamental frequency (fo) and an input reflector at the second harmonic
(2*fo), can be improved by adding third harmonic (3*fo) reflectors at the input and
output as will be shown below. This principle is shown in Figure 3.162, where the
desired output harmonic is m*fo and the higher order, unwanted harmonic is n*fo.
M1
ZMI ZM2
M2
n*fo
R e f l c tr ,
n*fo
^ R e flc tr
E le m n t
E le m n t
Id s
V ds
m *fo
V gs
I
R e flc tr
E le m n t
,Z 0 =
^gen
E le m n t
,
^gen
Figure 3.162. M ultiplier Topology Utilizing Extra n*fo Input and Output R eflector Networks
C:\Research\Figures\jj m lm 2 ideal_design3 BD2.ai
Just as in the previous section, a length o f transmission line is inserted between these
extra n*fo reflectors, with lengths Linnfo and Loutnfo. Note that the overall distance o f the
n*fo reflector from the transistor itself is denoted by Lin’nfo and Lout’nfo- Variation in
these lengths (Lin’nfo and Lout’nfo) changes the phase o f the reflected n*fo signal on the
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334
input and output respectively, causing variation in the way the n*fo signal interacts with
those signals at the other harmonics. In this way, the output power level at the desired
output harmonic, m*fo, can be manipulated. As previously discussed in Section 3.ii.d,
the phenomenon is attributed to nonlinear mixing between the n*fo signal and the other
harmonics. The mixing provides a larger m*fo output when:
•
n*fo power mixes with fo power at the output to provide more m*fo output
power.
•
n*fo power mixes with fo power within the gate-source diode (when the diode is
conducting) to create more m*fo power at the input.
•
the n*fo power on the input reacts with nonlinear feedback being provided by the
output reflectors.
Using this method o f mixing described above, the previous design o f Section 3.iv.b
can be improved. The use o f the n*fo harmonic reflectors has been verified in this
section through a simulation o f the circuit configuration shown in Figure 3.162. First, all
o f the reflector elements were implemented as LC series resonators (as shown in Figure
3.162). These reflector elements were the same as those developed in Seetion 3.ii.d (the
responses are shown in Figure 3.54, on page 146) and Section 3.iii.c (the response is
shown in Figure 3.101, on page 228) for a high-Q response. Second, to study the effects
o f changing the phase o f the reflected n*fo signal at the input and output, the lengths
Linnfo and Loutnfo were simultaneously swept. The simultaneous sweep, similar to that
discussed in Section 3.iv.b on page 280, consisted o f a large simulation where Pin was
varied from -10 to +10 dBm, Linnfo varied through 180 degrees o f electrical length, and
Loutnfo was varied through 180 degrees o f electrical length so that all combinations o f
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335
Pin, Linnfo and Loutnfo were tested. Out of this large dataset o f results the maximum 2fo
and 3fo conversion gain was obtained from a simple searching function and verified by
inspection. The results o f this study are presented below.
3.iv.c.2. Designs for Optimum Second Harmonic Output
C aseB l
The first design studied utilized the circuit configuration o f Figure 3.162 at a pinchoff
bias (Case B l, VGO = Vp). The line lengths o f the input second harmonic and output
fundamental signal frequency reflector lines (Lin2 fo and Loutfo, Figure 3.129) were given
by the previous design in Section 3.iv.b.2 (beginning on page 280). The values o f these
lengths were: Loutfo = 88 degrees; and Linifo = 50 degrees. Third harmonic reflector
elements in the form o f shunt LC series resonators were added to the input and output and
the lengths o f their locations from the gate and drain, Lin’sfo and Lout’sfo were
simultaneously varied. The output length Lout’afo was swept from 120 to 180 degrees
(with respect to fo) and the input length Lin’sfo was swept from 60 to 120 degrees (with
respect to fo). The corresponding sweep o f the output offset length Loutsfo was from 32
to 92 degrees and the input Linsfo was from 10 to 70 degrees. The input power was also
swept from -10 to +10 dBm. The simulation showed how the overall second harmonic
conversion gain changed with variations in the input power and in the third harmonic
reflector offset lengths. The conditions for maximum 2fo conversion gain were: Pin=-10
dBm; Lout’3fo=147.5 degrees; and Lin’3fo=77 degrees. Figure 3.163 shows the second
harmonic conversion gain versus the output third harmonic refiector length Lout’sfo for
the optimum 3fo input harmonic reflector length (Lin’sfo) and input power value (Pin).
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336
Note that both the overall lengths (Lout’sfo and Lin’sfo) and relative lengths (Loutsfo and
Linsfo) are shown. The overall lengths (Lout’sfo and Lin’sfo) give a better idea o f how the
3fo reflector phase relates to the impedance (2 (4 2 3 ^ and 2 1 4 1 3 ^,) seen by the drain and gate
o f the transistor.
Lout3f^(deg)
32
42
52
130
140
62
72
82
92
150
160
170
180
Lout'gf^ (d e g )
Figure 3.163, Second Harmonic Conversion Gain vs. 3fo Output Reflector Length, C ase B l
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As shown in Figure 3.163, the output third harmonic reflector has a drastic effect on
the second harmonic conversion gain. The optimum 2fo conversion gain reaches around
12.5 dB for a length Lout’sfo o f 147 degrees and quickly drops down to around 2 dB at
150 degrees.
The 2fo conversion gain versus the input third harmonic reflector length is shown in
Figure 3.164 for the optimum 3fo output reflector length and input power value. As the
figure shows, the input third harmonic reflector has a substantial impact on the second
R e p r o d u c e d with p e r m is s io n of t h e cop y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e r m is s io n .
337
harmonic conversion gain. The reflector causes variation in the second harmonic
conversion gain from around 1 to 12.5 dB.
Linsfo (deg)
10
20
30
40
50
60
70
100
110
120
Figure 3.164, Second Harm onic Conversion Gain vs. 3fo Inpnt R eflector Length, C ase B l
C;\Research\l_B_l Undrstndng NL Mech\B Stdy Idlzd MdlsViv Harm Gen via Input and
Output\jj_ideal_doub_3\caseBI_modelC2_doub3_ref_swp3_CGvsLin3foplot_6_16_03.fig
More insight into the improvement mechanism provided by the 3fo input and output
reflectors can be gained by observing the voltage and current waveforms and
corresponding harmonic content. Figure 3.165, Figure 3.166, Figure 3.167, and Figure
3.168 show the drain-source voltage (Vds), gate-drain current (Igd), gate-source voltage
(Vgs), and drain-source current (Ids), respectively. In each figure the optimum 2fo CG
design utilizing the 3fo reflectors (with the following optimum values: Loutfo=88 deg;
Lin2fo=50 deg; Lout3fo=59.5 deg (Lout’3fo=147.5); Lin3fo=27 deg (Lin’3fo=77), Pin=-10
dBm) is compared to the same design with the 3fo reflectors disabled (with the values:
R e p r o d u c e d with p e r m is s io n of t h e cop y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e r m is s io n .
338
Loutfo=88 deg; Lin2fo=50 deg; Pin=-10 dBm). Note that the response when no 3fo
reflectors are used corresponds to design #2 (in Section 3.iv.b.2, on page 280). Part (a) o f
each figure shows the time-domain waveforms o f each signal and part (b) shows the
corresponding harmonic content. Utilizing the plot configuration described above, the
contributions from the 3fo reflectors can be analyzed.
Figure 3.165 shows the drain-source voltage both with and without the 3fo reflectors
present.
2.6
t=d
4.5
2.4
t=«
V
/ V
2.2
“■r
3.5
t=a
> 1.4
2.5
^ 1.2
0.8
iPwthsFRflctrs'
X
No 3fo Rflctrs
0.6
0.5
- W ith 3fo Rflctrs
- No 3fo Rflctrs
Time (sec)
x10'^°
0.4
0.2
N
/
/V
Freq (GHz)
xIO
9
Figure 3.165. Drain-Source Voltage W aveforms and Corresponding Harmonics: Case B l (VGO=Vp,
Vdd=Vdd„ia)
C:\R esearch\l_B_l Undrstndng NL MechVB Stdy Idlzd Mdls\iv Harm Gen via Input and
Output\jj_ideal_doub_3\newlook_10_30_03\caseBl_modelC2_doub3_opt2_Vds_wffs_compp!ot_l l__02__03.fig
Figure 3.165(a) shows that, with no 3fo reflectors, the drain-source voltage was nearly
sinusoidal. When the 3fo reflectors are added, this almost sinusoidal waveform is
severely distorted. This distortion is observed in the change in the harmonic levels
R e p r o d u c e d with p e r m is s io n of t h e cop y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e r m is s io n .
339
shown In Figure 3.165(b). With no 3fo reflectors, the fundamental frequency is very
large (|Vdsfo|=2.35V) compared with the second and third harmonic (|Vds2fo|=0.2V,
|Vds3fo|=0.1V). As studied earlier, the large drain-source voltage at the fo is seen since
the fo reflector provides a very large impedance at the transistor’s output. When the 3fo
reflectors are added on, the 3fo drain-source voltage rises significantly (from 0.1 to 0.9
V). This rise in the 3fo voltage can be attributed to the presence o f a large 3fo output
network impedance, provided by the optimum 3fo output reflector (at Lout’3 fo= 147.5
deg). Corresponding to the rise in the 3fo drain-source voltage, the Vds at the
fundamental frequency shows a significant drop (from 2.35 to 1.8 V). Also, the 2fo Vds
shows a 50% increase when the 3fo reflectors are added, from 0.2 to 0.4V. The rise in
the 3fo content, coupled with the increase in the 2fo content suggests that mixing
between the fo and 3fo is occurring. Based on the drop in the fo drain-source voltage
content, it is shown that some o f the fo harmonic signal is mixed up to the second
harmonic.
Another effect exhibited in the distortion o f the drain-source voltage (when the 3fo
reflectors are added on) is a change in the feedback provided to the input o f the transistor.
As shown in Figure 3.165(a), the peak o f the Vds waveform (occurring between times a
and e in the figure) becomes distorted when the 3fo reflectors are introduced. Between
times a and b the drain-source voltage follows a nearly sinusoidal path, with a single peak
at 4.7V, when no 3fo reflectors are used (shown on the dashed trace). When the 3fo
reflectors are introduced (shown on the solid trace) however, the drain-source voltage is
altered. The drain-source voltage now reaches a peak o f 4.3 V at time b, drops to a local
minimum o f 3.5V at time c, and then peaks again to 4.7V at time d. This distortion at the
R e p r o d u c e d with p e r m is s io n of t h e cop y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e r m is s io n .
340
high-end o f the drain-source voltage, which reaches reverse breakdown at 4.5 V (and at
less than 4.5V when the gate-source voltage swings below pinchoff)* changes the
feedback provided to the transistor’s input.
The change in the feedback discussed above can be observed by examining the gatedrain current, shown in Figure 3.166. Figure 3.166 compares the gate-drain signals
which occur with and without the presence o f the input and output 3fo reflectors.
1
xIO"
(a)
1.8
A.
0
1 . 4
-2
1.2
< 1
■o
O) 0.8j^
-a
^ -4
ri
- 5
-6
-8
(b)
1.6
-1
- 7
x10'
0.6
0 . 4
W ith 3fo Rflctrs
No 3fo Rflctrs
9
W ith 3fo Rflctrs
X
No 3fo Rflctrs
0.2
I
0
3
Time (sec)
^ ^ q-10
6
Freq (GHz)
xIO
Figure 3.166. Gate-Drain Current W aveforms and Corresponding Harmonics: Case B l (VGO=Vp,
Vdd=Vdd„i<,)
C;\R esearch\l_B_! Undrstndng NL MechVB Stdy Idlzd MdlsViv Harm Gen via Input and
Output\jj_ideaI_doub_3\newlook_10_30_03\caseBl_modelC2_doub3_opt2_Igd_wffs_compplot_ll_02_03.fig
Figure 3.166(a) shows the gate-drain current waveforms with and without the 3fo
reflectors. The figure shows that the presence o f the reflectors significantly increases the
amount o f gate-drain current flow. The corresponding change in harmonic content is
exhibited in Figure 3.166(b). Here, it can be seen that the addition o f the 3fo reflectors
* A s sh o w n in E quation ( 3 . 3 5 ) on p age 2 0 7 , breakdow n o f the gate-drain ju n ctio n is dep en d en t o n both the
drain-sou ree and gate-sou rce vo lta g e.
R e p r o d u c e d with p e r m is s io n of t h e cop y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e r m is s io n .
341
increased the magnitude o f the feedback current at fo, 2fo and 3fo. The implications o f
these increases are several.
First, an increase in the 2fo feedback provides more 2fo power to be reflected back
into the gate by the 2fo input reflector.
Second, an increase in the 3fo feedbaek provides more 3fo power to be utilized by the
3fo input reflector. This extra 3fo power can mix with the fo power already present at the
gate to increase the 2fo gate signal.
Third, an increase in the fo feedback provides extra fo power for mixing o f fo and 3fo
at the gate.
0.7
0.2
W ith 3fo Rflctrs
No 3fo Rflctrs
(b)
0.6
i
0.2
0.5
-0.4
-0.4
- 0.6
(/>
O)
> 0.3
0.8
0.2
-
O)
>
-
0.1
-
0
Time (sec)
x 1 0 ’^°
#
With 3fo Rflctrs
X
No 3fo Rflctrs
11
___________ .
)
C
i
ii
3
6
Freq (GHz)
1
x IO
Figure 3.167. Gate-Source Voltage W aveforms and Corresponding Harmonics: Case B l (VGO=Vp,
Vdd=Vdd„id)
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd MdlsMv Harm Gen via Input and
Output\jj_ideal_doub_3\newlook_I0_30_03\caseBI_modeIC2_doub3_opt2_Vgs_wffs_compplot_l l_02_03.fig
R e p r o d u c e d with p e r m is s io n of t h e cop y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e r m is s io n .
342
Based on the effects exhibited in Figure 3.166 it is clear that significant harmonic
distortion occurs at the transistor gate. This distortion is observed in Figure 3.167, which
compares the gate-source voltages with and without the 3fo reflectors present.
Figure 3.167(a) shows that the presence o f the 3fo reflectors causes an increase in the
gate-source voltage swing. The gate-source voltage swings from -1.05 to -O.IV with no
3fo reflectors, and this increases to a swing from -1.1 to OV when the reflectors are used.
Also notable about the gate-source voltage waveform (with the 3fo reflectors present) is
that it does not exhibit clipping at the forward conduction voltage. This is because the
gate-source voltage is not driven past OV. As a result, the gate-source diode does not
conduct and remains an open circuit. The implications o f this are that the gate-source
diode does not contribute to any harmonic mixing at the gate. Therefore, the only
possible mixing occurring at the gate must be among the fundamental frequency input
signal and the harmonics provided by feedback through the gate-drain diode. Figure
3.167(b) shows the harmonic content corresponding to the waveforms shown in Figure
3.167(a). The figure shows that when the 3fo reflectors are utilized, the magnitude o f the
second harmonic gate-source voltage is increased from 0.32 to 0.42V. As discussed
above, this increased 2fo level is attributed to: mixing o f the fo and 3fo feedback signals;
mixing o f the fo input signal and the 3fo feedback signal; and the increase in the 2fo
feedback power provided to be utilized by the 2fo input reflector.
Figure 3.168 shows the drain-source current occurring with and without the 3fo
reflectors present.
R e p r o d u c e d with p e r m is s io n of t h e cop y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e r m is s io n .
343
0.014
0.03
(a)
W ith 3fo Rflctrs
No 3fo Rflctrs
p)
#
W ith 3fo Rflctrs
X
No 3fo Rflctrs
0.012
0.025
0.01
0.02
.0.008
to 0.015
■o
CO
- 0.006
i►
------- ;•
i
0.01
0.004
0.005
0.002
0
Time (sec)
-10
)
*K
c
i
•
\ /
7s
1r
3
6
Freq (GHz)
xIO
Figure 3.168. Drain-Source Current W aveforms and Corresponding Harmonics: Case B l (VGO=Vp,
Vdd=Vdd™id)
C:\Research\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\iv Harm Gen via Input and
Output\jj_ideal_doub_3\newlook_10_30_03\caseBl_modeIC2_doub3_opt2_Ids_wffs_comppIot_l l_02_03.fig
Figure 3.168(a) shows the drain-source current waveforms. The peak drain-source
current increases from 14mA (without the 3fo reflectors) to 25mA (with the 3fo
reflectors). Interestingly, when the 3fo reflectors are used, the waveform shape remains
very similar, with the main change being in the overall magnitude o f the waveform.
Figure 3.168(b) shows the harmonic content of the waveforms shown in Figure 3.168(a).
The figure shows that the 2fo content is greatly increased (from 4 to 8 mA) when the 3fo
reflectors are used. This increase in the 2fo harmonic content corresponds with: (a) the
increase in the 2fo harmonic content exhibited at the gate and (b) the change in the
nonlinear interactions seen in the linear and reverse-breakdown regions when the 3fo
reflectors are introduced. The increases seen in the 2fo drain-source current and drain-
R e p r o d u c e d with p e r m is s io n of t h e cop y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e r m is s io n .
344
source voltage levels result in a much improved 2fo conversion gain when the 3fo
reflectors are used.
In order to ensure that the design presented above (which utilized the 3fo reflectors to
further improve the 2fo CG) gave an adequate output power response, the 2fo CG, Pout
and MP response versus the input power was tested. Figure 3.169 shows the 2fo CG,
Pout, and MP for the optimum 2fo CG design over an input power range o f -10 to +10
dBm.
—
—
M P 2 fo
C G 2 fo
P out2fo
E
m
T3
CL
-10
-15.
-10
Pin (dBm)
Figure 3.169. Second Harmonic CG, Pont, and M P vs. Input Power, Case B l, Design 3
C:\Research\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\iv Harm Gen via Input and
Output\jj_ideaI_doub_3\newlook_10_30_03\caseBl_modelC2_doub3_opt2_MP_Pin_plot_l l_0I_03.fig
The figure shows an interesting phenomenon. In this case, the maximum conversion
gain appears to occur for an input power less than -10 dBm. The output power also
shows a maximum occurring at a -10 dBm input power level. As a result, the 2fo MP
also appears to occur at an input power below -10 dBm. In order to determine the true
R e p r o d u c e d with p e r m is s io n of t h e cop y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e r m is s io n .
345
optimum 2fo CG and MP for this doubler design the input power was re-swept over a
range o f -18 to -8 dBm. This response is shown in Figure 3.170 below.
20
— • M P 2fo
— C G 2 fo
Pout2fo
-16
-14
-12
-10
Pin (dBm)
Figure 3.170. Second Harmonic CG, Pout, and MP vs. Input Power (Extended to Low er Pin), Case
B l, Design 3
C :\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd MdlsMv Harm Gen via Input and 0utput\jj_ideal_doub_3\newlook_10_30_03\
caseBI_modelC2_doub3_opt2_reswp_MPplot_l I_02_03.fig
A maximum 2fo CG o f 13.98 dB at an input power o f -16.7 dBm is shown in the
figure. The corresponding 2fo output power is -2.72 dBm at Pin=-16.7 dBm. When the
maximum MP is utilized*, the optimum input power becomes -10.1 dBm, giving: a 2fo
MP o f 15.3 dBm; a 2fo CG o f 12.7 dB; and a 2fo Pout o f 2.6 dBm. As previously shown,
using a maximum MP design is preferable in providing a large CG with a reasonable
output power level.
* N ote that the maximum M P occurred for the same input and output reflector lengths (Lin 2 fo, Linsfo, Loutfo,
Loutsfo) as w hich m axim ized the CG.
R e p r o d u c e d with p e r m is s io n of t h e cop y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e r m is s io n .
346
Case C l
The next design studied consisted o f adding input and output reflectors on to the
design o f Section B.iv.b (Figure 3.129) at a forward conduction bias (Case C l:
VGO=Vfwd; Vdd=Vddmid )• The optimum values o f Loutfo and Lin2 fo from Section 3.iv.b
were utilized and the third harmonic reflector offset lengths Loutsfo (Lout’sfo) and Linsfo
(Lin’sfo) were simultaneously swept as previously described for case B l. The resulting
optimum lengths were; Lout3fo=63 deg (Lout’3fo=152); and Lin3fo=53.3 deg (Lin’3fo=100)
at an input power o f -10 dBm.
Figure 3.171 shows the second harmonic conversion gain response versus the third
harmonic output reflector length Lout’3 fo.
31
41
Lout3fo(deg)
51
61
120
130
140
71
81
91
160
170
180
6.5
GQ
B 5.5
v2
CM
@)
O
o
4.5
Figure 3.171. Second Harmonic Conversion Gain vs. 3fo Output Reflector Length, C ase C l
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\iv Harm Gen via Input and Output\jj_ideal_doub_3\
caseC l_modeIC2_doub3_ref7_swp_CGvsLout3fopIot_6_l 6 03 .fig
R e p r o d u c e d with p e r m is s io n of t h e cop y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e r m is s io n .
347
The optimum second harmonic conversion gain is around 6.2 dB for a reflector length
Lout’sfo o f 152 degrees. Although less effective than shown for the previous case (Case
B l) the 3fo output reflector causes around 2 dB o f variation in the 2fo conversion gain.
The input 3fo reflector is also less effective than for the previous case, its response is
shown in Figure 3.172.
3fo
19.3
29.3
39.3
(deg)
49.3
59.3
69.3
79.3
97
107
117
127
89.3
6.4
6.2
5.4
5.2
137
Lin'sfo (deg)
Figure 3.172. Second Harmonic Conversion Gain vs. 3fo Input R eflector Length, Case C l
C;\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\iv Harm Gen via Input and Output\jj_ideaI_doub_3\
caseCI_modeIC2_doub3_ref6_swp_CGvsLin3foplot_6_16_03.fig
As Figure 3.172 shows, the input third harmonic reflector only causes variation in the
2fo conversion gain o f around 1 dB.
Figure 3.171 and Figure 3.172 clearly show that, in comparison to case B l (Figure
3.163 and Figure 3.164), the 3fo input and output reflectors have much less o f an effect
on the 2fo conversion gain for case C l. This lack o f effectiveness o f the 3fo reflectors is
also illustrated by observing the input and output voltage and current signals. Figure
R e p r o d u c e d with p e r m is s io n of t h e cop y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e r m is s io n .
348
3.173, Figure 3.174, Figure 3.175, and Figure 3.176 show the drain-source voltage, gatedrain current, gate-source voltage, and the drain-source current respectively. Also, for
each figure the waveform is shown in part (a) o f the figure and the corresponding
harmonic content is shown in part (b). As conducted for case B l above, each figure
shows a comparison o f the design o f this section (design 3) with the design o f the
previous section (design 2, Section 3.iv.b.2) where no 3fo reflectors are used.
Figure 3.173 shows the drain-source voltage both with and without the 3fo reflectors
present.
5.5
t=b
4.5
t=a
- -f-
---
3.5
CO
■o
>
2.5
#
W ith 3fo Rflctrs
X
No 3fo Rflctrs
W ith 3fo Rflctrs
No 3fo Rflctrs
0.5
0.5
N/
/
Time (sec)
x10'^°
Freq (GHz)
x10
S
9
Figure 3.173. Drain-Source Voltage W aveforms and Corresponding Harmonics: Case C l
(VGO=Vfwd, Vdd=Vdd„id)
C:\Research\l_B_l Undrstndng NL Mech\B Stdy IdJzd Mdls\iv Harm Gen via Input and
Output\jj_ideal_doub_3\newlook_10_30_03\caseCl_modelC2_doub3_opt2_Vds_wffs_compplot_ll_03_03.fig
Figure 3.173(a) shows that, with no 3fo reflectors the drain-source voltage is nearly
sinusoidal. As shown between times a and b in the figure, when the 3fo reflectors are
R e p r o d u c e d with p e r m is s io n of t h e cop y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e r m is s io n .
349
used the waveform shape is distorted in the reverse-breakdown region. A similar effect is
exhibited at the lower voltage levels below the knee voltage (Vki=0.5V). However, the
distortion provided by the 3fo reflectors for case Cl is much less than for that previously
shown in case B l (Figure 3.165(a), page 338). As a result, the change in the harmonic
levels for case Cl is much less significant. Although the 3fo drain-source voltage is
increased from 0.2 to 0.5V for case C l, the 2fo drain-source voltage shows no change
when the 3fo reflectors are used. The lack o f improvement from the 3fo reflectors
suggests that although the 3fo output reflector reflects the 3fo transistor output power
back into the drain, no beneficial mixing between 3fo and fo is taking place on the output.
Another result seen from utilizing the 3fo reflectors is that the amount o f nonlinear
feedback is reduced. This is exhibited in the gate-drain current response, shown in Figure
3.174.
0.5
x10
—
—
(b)
With 3fo Rflctrs
No 3fo Rflctrs
s/ /
1
1
-0.5
?\
i
■a
D)
-2.5
t
i\
41
9
With 3fo Rflctrs
X
No 3fo Rflctrs
3
Time (sec)
^
9
6
Freq (GHz)
x10®
Figure 3.174. Gate-Drain Current W aveforms and Corresponding Harmonics; Case C l (VGO=Vfwd,
V dd=Vdd„i,)
C :\R esearch\I_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\iv Harm Gen via Input and
O utput\jj_ideal_doub_3\newIook_I0_30_03\caseCI_modelC2_doub3_opt2_Igd_wffs_com pplot_I l_03_03.fig
R e p r o d u c e d with p e r m is s io n of t h e cop y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e r m is s io n .
350
Figure 3.174(a) shows that when the 3fo reflectors are utilized, the peak gate-drain
current actually decreases. Without the 3fo reflectors a negative peak gate-drain current
o f -2.25mA is reached compared to a negative peak of-1m A with the reflectors. In
Figure 3.174(b), the magnitude o f the gate-drain current is shown to decrease by
approximately 50% for fo, 2fo and 3fo.
0.12
(b)
0.05 •
—
—
With 3fo Rflctrs
No 3fo Rflctrs
0.1
0.08
(/) 0.06
D)
>
O)
0.04
-0.15
-
0.2
0
W ith 3fo Rflctrs
X
No 3fo Rflctrs
0.02
_t=a
t=c
-0.25
3
Time (sec)
x10'^°
6
Freq (GHz)
1
x IO
Figure 3.175. Gate-Source Voltage W aveforms and Corresponding Harmonics: Case C l
(VGO=Vfwd, Vdd=Vdd„,id)
C:\Research\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\iv Harm Gen via Input and
Output\jj_ideal_doub_3\newlook_10_30_03\caseCl_modelC2_doub3_opt2_Vgs_wffs_compplot_ll_03_03.fig
The reduced amount o f feedback when the 3fo reflectors are used is apparent in the
gate-source voltage waveform, shown in Figure 3.175(a). With no 3fo reflectors, the
gate-source voltage is distorted at its negative peak. It reaches a local minimum o f 0.16V at time a, then begins to rise up to a local maximum at time b, and finally reaches
R e p r o d u c e d with p e r m i s s io n of t h e co p y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e rm is s io n .
351
its negative peak at time c*. However, when the 3fo reflectors are used this distortion is
reduced and the gate-source waveform resembles a simple half-wave rectified sinusoid^
The result o f this change in the gate-source waveform is actually an increase in the
harmonic content at fo, 2fo, and 3fo.
Figure 3.176 shows the drain-source current response. As shown in Figure 3.176(a),
the addition o f the 3fo reflectors changes the waveform shape o f the drain-source current.
0.03
0.025
(b)
0.028
0.026
0.02
“ "I
0.024
0.022
r
0.015
0.02
OT
■O
0.018
W ith 3fo Rflctrs
0.01
No 3fo Rflctrs
0.016
0.014
0.012
0.005
—
—
With 3fo Rflctrs
No 3fo Rflctrs
0.01
3
Time (sec)
x10'^°
6
Freq (GHz)
J
x IO
Figure 3.176. Drain-Source Current W aveforms and Corresponding Harmonics: Case C l
(VGO=Vfwd, Vdd=Vdd„,id)
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However, the resulting second harmonic content (Figure 3.176(b)) is relatively
unchanged, showing a slight increase from 3.6 to 4.1 mA. The fact that an increase in the
2fo gate-source voltage (Figure 3.175(b)) did not lead to a significant increase in the
This waveform distortion w as previously shown on Figure B .34 in Appendix B .ii.c.3 (page 4 9 9 ) to occur
due to the output fo reflector driving the transistor into reverse breakdown.
^ A s expected with no feedback present as previously shown on Figure 3.19, page 95.
R e p r o d u c e d with p e r m i s s io n of t h e c o p y rig h t o w n e r . F u r th e r re p r o d u c tio n p rohib ited w ith o u t p e r m is s io n .
352
corresponding 2fo current (Figure 3.176(b)) is at first counter-intuitive. However, as
previously shown in Figure 3.144(b) (where only the output fo and input 2fo reflectors
are used, as in design 2 on page 303) the large 2fo CG obtained for the response without
the 3fo reflectors was attributed in part due to the distortion o f the gate-source voltage
waveform provided by nonlinear feedback. When the 3fo reflectors are added, the
amount o f feedback is reduced (Figure 3.174(b)), the resulting distortion o f the gatesource waveform is much less (Figure 3.175(a)), and no significant improvement to the
2fo drain-source current is shown (Figure 3.176(b)). As a result o f this lack o f significant
improvement to either the 2fo drain-source current or voltage magnitude, no significant
improvement to the 2fo conversion gain is obtained through the use o f the input and
output 3fo reflectors. In fact, for a -10 dBm input power a 2fo CG o f 5.1 dB is achieved
without the 3fo reflectors (see design 2, Figure 3.150 on page 314) compared to around
6.2 dB with the 3fo reflectors in place. Thus only a 1.1 dB improvement is achieved with
the use o f the 3fo reflectors.
In comparison o f case B l and C l, it is seen that the 3fo reflectors provide much more
improvement for case B l. The differences shown in the efficiency o f the 3fo reflector
networks between Case B l and Case Cl can be attributed to the amount o f 3fo power
available for the networks to reflect. Figure 3.177 shows the third harmonic output and
reflected power response for Case B l and Cl where the third harmonic reflectors are not
present (this represents the output and reflected power response for the previous design
number 2, shown in Section 3.iv.b). At the point o f optimum second harmonic
conversion gain (Pin = -10 dBm) case Cl exhibits around -27 dBm o f 3fo reflected gate
power compared to -17 dBm for case B l. Although the output power levels between the
R e p r o d u c e d with p e r m is s io n of t h e cop y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e r m is s io n .
353
two cases are comparable (-7.5 dBm for case Cl and -10 for ease B l), the very low 3fo
gate reflected power level for case Cl causes the third harmonic reflectors to be less
effective.
T3
ji
-10
c-15
—
-—
o
n
-20
-2 5
P o u t@ 3 fo , c a s e B I
P r e f@ 3 fo , c a s e B I
P o u t@ 3 fo , c a s e C I
P r e f@ 3 fo , c a s e C I
-3 0
-10
Pin (dBm )
Figure 3.177. Third Harmonic Output and Reflected Power Levels Before Use o f Extra Third
Harmonic Reflector Networks
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Output\jj_ideal_doub_2\caseBl_Cl_modelC2_doub2_3foPoutPref_comp_6_17_03.fig
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354
MP 2fo
CG 2fo
Pout 2fo
CM
■20
-25
-30
-10
Pin (dBm)
Figure 3.178. Second Harmonic CG, Pout, and M P vs. Input Power, Case C l, Design 3
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The 2fo conversion gain response versus the input power for case Cl (with the 3fo
reflectors back in place) is shown in Figure 3.178. Note that the figure also includes the
2fo output power and MP response. The figure shows the same trend seen in case B l .
As the input power level drops down to -10 dBm, the output 2fo CG and MP appears to
be continuing to increase. Thus, an optimum input power of less than -10 dBm must be
searched for. In order to find the true optimum 2fo CG response, as well as the true 2fo
MP, the doubler design (design 3) for case Cl was re-simulated over an input power
range o f -18 to -8 dBm. This extended simulation o f the 2fo CG, Pout and MP response
versus the input power is shown in Figure 3.179.
R e p r o d u c e d with p e r m is s io n of t h e cop y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e r m is s io n .
355
12
M P 2fo
C G 2 fo
P out2fo
10
8
6
4
CM
2
0
•2
■4
■6
-1 6
-14
-12
-10
■8
Pin (dBm)
Figure 3.179. Second Harmonic CG, Pout, and MP vs. Input Power (Extended to Lower Pin), Case
C l, Design 3
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Output\jj_ideal_doub_3\newlook_10_30_03\caseCl_modelC2_doub3_opt2_reswp_MPplot_l l_03_03.fig
As the figure shows, a maximum 2fo CG o f 10.19 dB is reached for an input power o f
-16.1 dBm. The corresponding 2fo Pout at this input power level is -5.91 dBm. When
utilizing the maximum MP, an input power level o f -13.9 dBm is optimum, giving a
maximum MP o f 5.14 dBm. The corresponding 2fo CG and Pout values are 9.53 dB and
-4.38 dBm respectively. Here, the MP results in a slightly better output power level.
3.iv.c.3. Designs for Optimum Third Harmonic Output
C aseA l
The above principle o f utilizing reflector networks at the higher order, unwanted
harmonics was also extended to the use o f an optimum third harmonic output conversion
gain design. This design utilizes the previously optimized design (design 2) o f Section
R e p r o d u c e d with p e r m is s io n of t h e cop y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e r m is s io n .
356
3.iv.b.3 (page 315), with extra second harmonic reflectors inserted at the input and output
with lengths Lin2 fo and Lout2 fo, respectively. This circuit configuration is represented by
Figure 3.162 where “m” is equal to 3 and “n” is equal to 2 (m=3, n=2). The transistor is
biased midway between pinchoff and the forward conduction voltage (Case A 1:
VGO=Vmid; Vdd=Vddmid).
Using ADS simulation, the effects o f variation in the second harmonic input and
output reflector lengths, Lin2 fo and Lout2 fo (Figure 3.162), were studied. The results are
presented below.
Figure 3.180 shows the third harmonic conversion gain versus the output second
harmonic reflector length Louf 2 fo at the input power level (Pin) and input 2fo reflector
length (L in ’2fo) giving optimum third harmonic conversion gain. Note that the lengths
Lout2 fo and Linifo are also included on the plot. The figure shows that variation in the
output second harmonic reflector length causes around 0.5 dB o f variation in the third
harmonic conversion gain. A maximum 3fo conversion gain level o f around 13.95 dB is
obtained for an output length Louf 2 fo o f around 130 degrees.
R e p r o d u c e d with p e r m is s io n of t h e cop y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e r m is s io n .
357
Lout^^^ (deg)
11
21
31
100
110
120
41
51
61
71
81
91
150
160
170
180
13.9
13.8
CO
13.6
CD
O
13.5
13.4
13.3
90
130
140
Lout'2 f^ (deg)
Figure 3.180. Third Harmonic Conversion Gain vs. 2fo Output Reflector Length, Case A1
C:\Research\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\iv Harm Gen via Input and
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Variation in the input 2fo reflector length Lin’ifo is shown in Figure 3.181, at the
optimum input power level (Pin = -10 dBm) and output 2fo reflector length (Lout’2 fo 130 degrees).
As Figure 3.181 shows, variation o f the input second harmonic reflector causes a more
significant change in the third harmonic conversion gain, causing almost 3.3 dB o f
variation. The optimum 3fo conversion gain occurs for an input length Lin’afo o f 105
degrees.
Note that the 3fo CG exhibited in Figure 3.180 and Figure 3.181 reaches a maximum
o f 13.95 dB at an input power o f -10 dBm.
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358
Lin2 fo (deg)
49.5
59.5
69.5
100
120
79.5
89.5
99.5
109.5
119.5
160
(deg)
180
200
220
13.5
m
— 12.5
CO
CD
O
10.5_
Figure 3.181. Third Harmonic Conversion Gain vs. 3fo Input Reflector Length, Case A1
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Output\jj_ideaI_trip_3\newlook_ll_03_03\caseAl_modelC2_trip3_ref4_REswp_CGvsLin2foplot_l l_03_03.fig
Pout @ 3fo
Pout @ 2fo
Pref @ 2fo
Q- - 1 0
■a
-15
-20
-25
-30
-10
Pin (dBm)
Figure 3.182. Output and Reflected Power Response with 3fo Reflectors Disabled (Tripler Design 2)
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359
The 3fo CG when no 2fo input and output reflectors were used (tripler design 2, case
A l, page 315) was 13.6 dB at an input power o f -10 dBm. Thus, the addition o f the 2fo
input and output reflectors results in a negligible 0.35 dB improvement in the maximum
3foC G (at Pin = -10 dBm).
The reason for the ineffectiveness o f the 2fo input and output reflectors for ease A l is
clearly exhibited by observing the 2fo output and reflected power response for the
previous design (tripler design 2), where no 2fo reflectors (and only the optimum fo
output and 3fo input reflectors) are used. The 2fo Pout and Pref, as well as the 3fo Pout
response versus the input power is shown in Figure 3.182.
As the figure shows, at an input power o f -10 dBm the 2fo output and reflected power
level is around -20 dBm. Compared to the 3 dBm 3fo output power at the same input
power level (Pin = -lOdBm), these 2fo power levels are very small. In fact, the 2fo
output and reflected power is about 23 dB lower than the corresponding 3fo output power
for tripler design 2. As a result, the addition o f the 2fo reflectors on the input and output
cannot provide significant improvement o f the 3fo CG since there is minimal 2fo power
to reflect. This is observed in the fact that a negligible 0.35 dB improvement in the 3fo
CG is obtained when the 2fo reflectors are utilized.
In Section 3.iv.b.3 (page 315) it was shown that for case A l, tripler design 2, the
maximum 3fo CG and MP occurred for an input power level o f less than -10 dBm. The
same proves true for the design o f this section. Figure 3.183 shows the 3fo CG, MP and
Pout response versus the input power with the optimized input and output reflector
lengths (Loutfo=89 deg, Linsfo = 30.5 deg, Lout2 fo = 40.5 deg (Lout’2 fo = 129.5), Lin2 fo =
72 (Lin’2 fo= 102.5).
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360
— M P 3fo
— C G 3 fo
P out3fo
25
20
E
CD
TJ
-10
-25
-20
-15
-10
Pin (dBm)
Figure 3.183. Third Harmonic CG, MP, and Pout vs Pin for Tripler Design 3, Case A l
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caseAI_modelC2_trip3_opt2_reswp_MPpIot_ll_03_03.frg
As the figure shows, when the input power level drops below -10 dBm the 3fo CG and
MP continues to increase. The 3fo CG reaches a maximum o f 26 dB at an input power o f
-24 dBm. The maximum 3fo MP reaches 28 dBm, also at an input power o f -24 dBm.
The output power level at this input power is 2 dBm.
3.iv.c.4. Summary of Results
A summary o f the results for the optimum second harmonic and third harmonic CG
and MP designs in this section is shown in Table 3.15.
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361
Table 3.15. Summary of Results for Section 3.iv.c
(a) Designs for Optimum 2fo Output:
Zm 2 (maq /deq)
& n 1 (m aq /deq)
C ase
C ase B1
(VGO =Vp)
(V d d = V d d ,J
C ased
(VGO=VIVvd)
(V d d = V d d ^ J
D es ig n e d
for.
M axim um
2fo C G
M axim um
2fo M P
M axim um
2fo C G
M axim um
2fo M P
(deg*)
(dec*)
Lout.
L o u l,^ / Lout' 3,^
(deg)
(dea*)
fo
2fo
3fo
fO
O utput R esponse
2fo
3fo
Pin
(dB m )
C G 2fo
(dB)
P out2fo
(dB m )
M P 2fo
(dB m )
50
2 7 /7 7
88
5 9 .5 /1 4 7 ,5
50/0
284/-90
60/90
1432/90
50/0
380 /9 0
-16.7
13.98
-2 .7 2
11.26
50
2 7 /7 7
88
5 9 .5 /1 4 7 .5
50/0
284/-90
60/90
1432/90
50/0
380/90
- 10.1
12.7
2.6
15.3
46.7
5 3 .3 /1 0 0
89
6 3 /1 5 2
50/0
842/-90
87/-90
2864/90
50/0
476/-90
-16.1
10.19
-5.91
4 .2 8
9 ,52
-4 .3 8
5,14
46J
5 3 .3 /1 0 0
89
6 3 /1 5 2
Loutj^
L o u t,,,/ Lout'3,,
(deg*)
L in ,,,/ Lin'^,^
(dea*l
(deg)
(dea*)
30.5
7 2 /1 0 2 .5
89
30.5
7 2 /1 0 2 .5
89
50/0
842/-90
87/-90
2864/90
47 6 /-9 0
-1 3.9
2fo
3fo
Pin
(dB m )
C G 3fo
(dB )
PoutSfo
(dB m )
M P 3fo
(dB m )
50/0
(b) Designs for Optimum 3fo Output:
C ase A l
(VGO =Vm id)
(V d d = V d d ,J
D esigned
fo r
M axim um
3fo C G
M axim um
3 fo M P
O utput R esponse
Zm 2 (maq /dea)
Zm 1 (m aqi/deg)
C ase
3fo
fO
fo
2fo
4 0 .5 /1 2 9 .5
50/0
23/90
1909/-90 2864/90
2 49 /9 0
50/0
-24
26
2
28
4 0 .5 /1 2 9 .5
50/0
23/90
1909/-90 2864/90
249/90
50/0
-24
26
2
28
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362
3.iv.d. Comparison of Designs 1 Through 3
Table 3.16, Table 3.17, Table 3.18 and Table 3.19 below show a summary o f the
results from designs 1 through 3. Table 3.16 and Table 3.17 present the results o f the
designs giving maximum 2fo eonversion gain and 2fo multiplier power (MP),
respectively. Table 3.18 and Table 3.19 present the results o f the designs giving
maximum 3fo conversion gain and 3fo multiplier power (MP), respectively.
Sum m ary o f Optimum 2fo Conversion Gain Designs
Table 3.16 shows a summary o f the designs which were maximized for second
harmonic CG. For each design the optimum impedance value at the input (Zmi) and
output (Zm2 ) at each harmonic (fo, 2fo, 3fo) is shown, as well as the optimum 2fo
conversion gain obtained and the corresponding input power level, output power level,
and MP. Note that the optimum conversion gain obtained with when only the input
signal was adjusted with no external reflectors and a simple 50 ohm input and output
resistance (as presented in Section 3.ii.a.5, page 82) is included in the table for
comparison.
Table 3.16. Summary of Optimum 2fo Couversiou Gain Designs
Zm2 (mag/deq)
Zmi (mag/dea)
C ase
C aseB I
(VGO=Vp.Vdd=Vdd^,;
D esig n #
3fO
fO
50/0
50/0
50/0
50/0
284/-90
284/-90
50/0
50/0
fo
2fo
Basic Case*
50/0
1
50/0
2
50/0
3
B asic C ase ’
1
50/0
50/0
2
50/0
MP2fo
(dBm)
-3.14
14.48
3fo
50/0
50/0
0/0
380/0
50/0
0/0
50/0
1432/90
50/0
50/0
-10
6.7
-3,3
3.4
60/90
50/0
1432/90
50/0
0/0
50/0
50/0
380/90
50/0
-16.7
-1
-2.72
-2.07
11.26
-3.14
14.48
0/0
50/0
380/0
50/0
842/-90
50/0
2864/90
50/0
50/0
476/-90
50/0
842/-90
87/-90
2864/90
50/0
3
•B asic c a s e consists of a simple 50 ohm im pedance on the input and output, as shown in Section 3.ii.a.5
C ase C1
(VGD=Vfwd, V d d W d d ^ .;
Output R esponse
Pin
CG2fo Pout2fo
(dBm)
(dB)
(dBm)
-1
-2.07
-1.07
-1
7.74
6.74
2fo
-1
13.98
-1.07
7.74
-10
5.1
-4.9
0.2
-16.1
10.19
-5.91
4.28
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363
CaseBI (VGO=Vp, Vdd=Vdd,^^
Referring to Table 3.16, the results for case B1 are very interesting. For the basic
case, (with a simple 50 ohm impedance on the input and output), the maximum
conversion gain is -1.07 dB. Design 1 (Section 3.iv.a) increases this conversion gain by
simply shorting out the unwanted output harmonics and adjusting the load for maximum
swing in the saturation region. This simple procedure increases the conversion gain from
-1.07 to 7.74 dB. As shown in Section 3.iv.a, however, the maximum 2fo CG for design
1 may be increased to an arbitrarily large amount. Therefore a more realistic
characterization o f design 1 utilizes the MP, and this will be discussed below (Table
3.17). The conversion gain is also significantly increased by utilizing design procedure 2
(Section 3.iv.b), where a second harmonic input, and fundamental output reflector is
used. This increases the second harmonic conversion gain from -1.07 to 6.7 dB. The
optimum impedances for this design consist o f a large magnitude (approaching an open
circuit) for both the fundamental output and second harmonic input impedance as
presented by the output and input harmonic reflector networks. When secondary, higherorder, unwanted harmonic reflectors are added to design 2, which makes up design 3
(Section 3.iv.c), the conversion gain can be increased even further. A maximum
conversion gain o f 13.98 dB is reached for design 3 compared to 6.7 for design 2. This
significant improvement is attributed to nonlinear mixing between the higher order,
unwanted harmonics and the fundamental and desired harmonic as discussed in Section
3.iv.c. Improvement was also seen since for design 3, the input power level was lowered
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364
below -10 dB, to find a true maximum at an input power o f -16.7 dBm*. For design 1, 2
and 3 a primary concern is the fact that designing for maximum 2fo CG tends to give
poor output power response. As previously discussed above, this concern was addressed
by designing for maximum 2fo MP for all three designs. The maximum 2fo MP designs
will be summarized below (Table 3.17).
Case C l (VGO=Vfwd, Vdd=Vdd„u<i)
Referring once more to Table 3.16, the designs o f case Cl also show interesting
results. Design 1 gives the same improvement over the initial case as case B1 giving 7.74
dB output 2fo conversion gain compared to -1.07 when only a 50 ohm input and output
impedance is presented. For the same reasons discussed for case B1 above, however, the
maximum 2fo CG for case Cl is largely arbitrary. Designs 2 and 3 give much less
conversion gain improvement for case C l then they do for case B l.
The optimum networks for case Cl and B l show some striking similarities. As
previously discussed in Section 3.iv.a above, the two cases are equivalent for design 1.
For designs 2 and 3 the optimum fundamental output impedance for both cases is that
which approaches an open circuit and causes the transistor to hit the linear and the
reverse-breakdown region. The use o f this fundamental impedance is one o f the major
mechanisms to provide the large second harmonic output conversion gain, and depends
on the use o f the reverse-breakdown region.
In com p arison , d esig n 2 w a s constrained to a m inim um input p ow er o f -1 0 dB m .
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365
Sum m ary o f Optimum 2fo M ultiplier Power (MP) Designs
Table 3.17 shows a summary o f the designs which were maximized for second
harmonic MP. In Table 3.17 the optimum impedance value at the input ( Z m i ) and output
(Zm2 ) at each harmonic (fo, 2fo, 3fo) is shown, as well as the optimum 2fo MP obtained
and the corresponding input power level, output power level, and CG.
Table 3.17. Summary of Optimum 2fo Multiplier Power (MP) Designs
Zm2 (maq/deq)
Zm1 (mag/deq)
2fo
3fo
50/0
50/0
50/0
1432/-90
50/0
284/-90
C ase
D esig n #
fo
C aseB I
(VGO=Vp,Vdd=Vdd^.;
1
2
3
C ased
(VGO^Vfwd, Vdd=Vdd^.J
3fo
Pin
(dBm)
0
Output R esponse
CG2fo PoutZfo
(dB)
(dBm)
7.3
7.3
MP2fo
(dBm)
14.6
fO
2fo
50/0
0/0
380/0
0/0
50/0
715/-90
50/0
50/0
-4
5.1
1.1
6.2
60/90
1432/90
50/0
380/90
-10.1
12.7
2.6
15.3
14.6
1
50/0
50/0
50/0
0/0
380/0
0/0
0
7.3
7.3
2
50/0
1432/90
50/0
137/-90
50/0
50/0
-3
3.5
0.5
4
3
50/0
842/-90
87/-90
2864/90
50/0
476/-90
-13.9
9.52
-4.38
5.14
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CaseBI (VGO=Vp, Vdd=Vdd„aa}
Table 3.17 shows some interesting conclusions about designs 1, 2 and 3 utilizing a
gate pinchoff bias (case B l). The table shows that the design utilizing only an LC filter
on the output (design 1) has a comparable 2fo MP (14.6 dBm) to design 3 (MP2 fo = 15.3
dBm). Although these two designs exhibit comparable maximum MP values, there are
some significant differences. Design 3 exhibits a 12.7 dB 2fo CG which is much larger
than the maximum 7.3 dB conversion gain achieved for design 1. However, in terms o f
the 2fo output power, design 1 gives a superior performance. This is exhibited in the 7.3
dBm 2fo output power obtained for design 1, compared to only 2.6 dBm 2fo output
power for design 3.
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366
Case C l (VGO=Vfwd, Vdd=Vdd,^^
Table 3.17 shows that design 1 shows a superior 2fo MP performance for case C l.
The MP is 14.6 dBm for design 1, compared to 4 dBm for design 2 and 5.4 dBm for
design 3. Design 1 also exhibits a significant 7.3 dB 2fo conversion gain. However,
design 3 exhibits the largest 2fo CG, which is 9.52 dB. This design (design 3) exhibits a
poor 2fo output power level (Pout2fo=-4.38) compared to design 1 (Pout2fo=7.3dBm).
Sum m ary o f Optimum 3fo Conversion Gain Designs
Table 3.18 shows a summary o f the designs which were maximized for third harmonic
CG. For each design the optimum impedance value at the input ( Z m i ) and output ( Z m i ) at
each harmonic (fo, 2fo, 3fo) is shown, as well as the optimum 3fo conversion gain
obtained and the corresponding input power level, output power level, and MP. Note that
the optimum conversion gain obtained with when only the input signal was adjusted with
no external reflectors and a simple 50 ohm input and output resistance (as presented in
Section 3.ii.a.5, page 82) is included in the table for comparison.
Table 3.18. Summary of Optimum 3fo Conversion Gain Designs
Zm1 (maq/deq)
C ase
D esig n #
Output R esponse
Zm2 (mag/deq)
fo
2fo
3fo
fO
2fo
3fo
Pin
(dBm)
-0 4
CG3fo
(dB)
-4.83
Pout3fc
(dBm)
-5.23
MP3fo
(dBm)
-10.06
Basic C ase’
50/0
50/0
50/0
50/0
50/0
50/0
C aseA l
1
50/0
50/0
50/0
0/0
0/0
626/0
-1
6.08
5.08
11.16
(VGO=Vmid,Vdd=Vdd^.J
2
50/0
50/0
1909/-90
2864/90
50/0
50/0
-22
21.7
-0.3
21.4
3
50/0
23/90
1909/-90
2864/90
249/90
50/0
-24
26
2
28
•B asic c a s e consists of a simple 50 ohm im pedance on the input and output, as shown in Section 3.ii.a,5
C;\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd MdlsMv Harm Gen via Input and Output\summaryC_desl-5.sxc
As Table 3.18 shows, utilizing a parallel LC output network and optimizing the load
resistance (design 1) increases the 3fo conversion gain from -4.83 dB (for the basic case)
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261
to 6.08 dB (for design 1). When the fo output and 3fo input reflectors are used (design 2)
the conversion gain is increased from -4.83 dB (for the basic case) to 21.7 dB (for design
2), showing a very significant increase in conversion gain when only the fundamental
output and third harmonic input impedances are adjusted. Design 3, which adds second
harmonic input and output reflectors, increases the conversion gain o f 21.7 dB (design 2)
to 26 dB. For the optimum third harmonic conversion gain designs, the design giving the
highest conversion gain is design 3, which utilizes the reverse breakdown region. Note
that, just as in the 2fo conversion gain designs, design 3 (maximized for 3fo CG) consists
o f a very large fundamental frequency output impedance.
Similar to the designs optimized for 2fo CG, the 3fo CG designs utilizing input and
output reflectors (design 2 and design 3) exhibit a sub-par corresponding output power
level. In terms o f the 3fo output power, design 2 (with Pout3fo=-0.3 dBm) and design 3
(with Pout3fo=2 dBm) exhibit significantly less power in comparison to design 1, which
exhibits 5.08 dBm 3fo output power. The 3fo output power for all three designs was
improved upon by designing for maximum 3fo MP, as will be shown below.
Sum m ary o f Optimum 3fo M ultiplier Power (MP) Designs
Table 3.19 shows a summary o f the designs which were maximized for second
harmonic MP. The optimum impedance value at the input (Z m i) and output (Z m 2 ) at each
harmonic (fo, 2fo, 3fo) is shown in the table, as well as the optimum 3fo MP obtained
and the corresponding input power level, output power level, and CG.
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368
Table 3.19. Summary of Optimum 3fo Multiplier Power (MP) Designs
Zm2 (mag/deg)
Zmi (mag/deg)
Case
D esign#
to
2fo
C ase A1
(VGO=Vmid,Vdd=Vcld^._)
1
2
3
50/0
50/0
50/0
50/0
50/0
23/90
3fo
fO
50/0
0/0
1909/-90 2864/90
1909/-90 2864/90
2fo
3fo
0/0
50/0
249/90
552/0
50/0
50/0
Output Response
Pin CG3fo Pout3fo MP3fo
(dBm) (dB) (dBm) (dBm)
0
5.59
5.59 11.18
-20
21
1
22
-24
28
26
2
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\iv Harm Gen via Input and Output\summaryC_desI-5.sxc
Table 3.19 shows that design 3, has the largest 3fo MP by a significant amount. The
design (design 3) shows 28 dBm o f 3fo MP compared to 22 dBm for design 2 and 11.18
dBm for design 1. Design 3 exhibits a very large 26 dB 3fo CG with a corresponding 2
dBm 3fo output power. In comparison, design 2 shows a 21 dB 3fo CG with 1 dBm 3fo
output power. Design 1 exhibits the lowest 3fo CG (5.59 dB), however, this design gives
the best 3fo output power (5.59 dBm).
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369
3.V. Sum maty of Chapter 3
In this chapter principal frequency multiplier design techniques have been developed
and explored. These fundamental design principals were developed through theoretical
calculation as well as comprehensive simulation in ADS utilizing idealized transistor
models.
In section 3.ii, design techniques utilizing conditions at the input o f the transistor were
developed. Section 3.ii.a explored nonlinear signal generation by varying the input signal
and bias level. From the analysis in Section 3.ii.a, AC input signals and gate bias voltage
levels for optimum 2fo and 3fo CG were shown. Section 3.ii.b explored the use o f a
quarter-wave, input “matching” network at the fundamental frequency. Variation in the
impedance presented to the gate o f the transistor at the fundamental frequency was
utilized to increase the output conversion gain. In Section 3.ii.c, the effects o f the
resistance in the path o f the gate bias voltage were explored. It was shown that the use of
bias-T networks in a frequency multiplier design can greatly affect the expected harmonic
output. A compensation technique to utilize a practical DC bias resistance while still
achieving the calculated harmonic output was developed. Section 3.ii.d explored the use
o f an input reflector at the second and third harmonics. A 2fo (and 3fo) reflector element,
offset by a varied length o f transmission line, was shown to significantly affect the output
conversion gain. Offset lengths giving maximum 2fo and 3fo CG were discovered and
analyzed.
In section 3.iii, design techniques utilizing conditions at the output o f the transistor
were developed. Section 3.iii.a explored variation in the load resistance and drain bias
level. Variation in the load in a power amplifier configuration was shown to greatly
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370
affect the conversion gain at the fundamental frequency, as well as cause harmonics to
rise at 2fo and 3fo. The effects o f biasing the transistor near the linear and reversebreakdown regions o f operation were also studied. In Section 3.ii.b, the effects o f the
resistance in the path o f the drain bias voltage were explored. Similar to the gate bias
(Section 3.ii.c), it was shown that the use o f a bias-T network at the drain can also affect
the expected harmonic output. Finally, Section 3.ii.c provided an in-depth analysis o f the
use o f an output reflector network at the fundamental frequency. Section 3.iii.c also
presented a novel characterization method, the multiplier power (MP). It was shown that
the MP can be utilized to create large CG designs while also ensuring a large
corresponding output power level. Optimum offset lengths for the output reflector,
giving maximum 2fo and 3fo CG and MP were shown.
Section 3.iv presented multiplier design techniques utilizing combinations o f input and
output conditions for maximum CG and MP. In Section 3.iv.a, a multiplier design was
developed which utilized a basic network (with a 50 ohm generator impedance and DC
bias resistance) at the input and a parallel LC filter with a varied load resistance (R l) on
the output. By varying the load resistance, gate bias and input power level, the CG and
MP was maximized both for 2fo and for 3fo. Section 3.iv.b presented a multiplier design
which had an input reflector operating at the desired output harmonic frequency mfo (2fo
for a doubler design and 3fo for a tripler design). The design also had an output reflector
at the fundamental frequency. The offset lengths o f the input and output reflectors and
the input power level were varied to create optimum CG and MP designs. Finally,
Section 3.iv.c added secondary input and output reflectors to the design o f Section 3.iv.b,
to further improve the CG and MP.
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371
Overall, Chapter 3 presented fundamental, universal principals o f frequency multiplier
design. These principals were thoroughly analyzed by examination o f the large-signal
response, the time domain input and output waveforms, and the harmonic content o f the
gate and drain voltages and currents. Since the design techniques utilized an idealized
representation o f a FET/HEMT transistor, they are applicable to a wide-range of
situations and can be used as a baseline for the design o f practical frequency multipliers.
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372
Chapter 4.
Practical Frequency Multiplier Design
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373
4.1. Practical Frequency Doubler Design
4.1.a. Choice of Bias Point
In Section 3.ii.a.5, gate bias points providing a maximum 2fo conversion gain were
discovered via simulation o f the idealized model (model A). To determine these points
the gate bias and input power were simultaneously swept* and points o f optimum
conversion gain were identified. Utilizing the extensive large-signal measurements
conducted in Section 2.ii.c, gate bias points o f maximum 2fo conversion gain were
identified for the actual device. Figure 4.1 shows the measured 2fo conversion gain
versus gate bias response for several input power levels.
Pin = OdBm
Pin = 2dBm
Pin = 4dBm
—
Pi n = 6dBm
-■ Pin = 8dBm
Pin = lOdBm
-
0.2
0
Vgo (V)
Figure 4.1. Measured 2fo Conversion Gain vs Gate Bias Voltage (VGO) for Several Input Power
Levels
C:\R esearch\l_B_l Undrstndng NL Mech\C Practical Designs\jjsimpledoublerl_writeup_10_13_03\
Xtr36a_maxCG2fosearch_neat_fo_3G_ 10_ 13 03. fig
T h e id ea o f a sim u ltan eou s sw ee p w a s d efin ed on page 101
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374
As shown in the figure, the maximum 2fo conversion gain occurs at a 6dBm input
power, for a gate-source bias voltage o f -0.6V . This gate bias corresponds with the
optimum gate bias for the ideal, simulated case shown in Section 3.ii.a.5.ii (case B l).
Note also that the 2fo conversion gain begins increasing sharply as the gate-source
approaches 0.4V. This occurs since the bias level is approaching the forward conduction
voltage o f the transistor (Vfwd ~ 0.8V for this device). A gate-source bias at forward
conduction (VGO=Vfwd) corresponds with the other optimum bias for maximum second
harmonic conversion gain discovered with the idealized model (case C l, Section
3.ii.a.5.iii). Unfortunately, the actual device ran into burn-out problems when it was
operated for long periods o f time above a gate-source voltage o f 0.4V, therefore a
forward conduction bias could not be utilized.
The drain bias for the practical design was chosen based on the results obtained from
the idealized analysis (Section 3.iii.a and 3.iii.c). The ideal analysis showed that a drain
bias midway between the knee (Vki) and reverse-breakdown voltage (Vrbd) gave an
optimum response. Thus, for the practical design, the midway drain-source bias
(Vdd=Vddmid=(Vrbd+Vki)/2) was used.
4.1.b. Input and Output Network Configuration
After choosing a bias point, the configuration o f the input (M l) and output (M2)
networks were chosen. The design corresponding to design #2, conducted with the
idealized model (as shown in Section 3.iv.b.2) was utilized. This consisted o f an output
fundamental fo “reflector network” and an input second harmonic “reflector network.”
Unlike the idealized design, however, the reflector elements (fo output reflector and 2fo
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375
input reflector) were implemented as microstrip lines o f a quarter-wavelength. These
reflectors are described in more detail in Section 4.i.c below. A schematic o f the circuit
configuration is shown in Figure 4.2.
M icrostrip Circuit Board
W s tu b t
W stu b 2
Lstubt
L s tu b 2
son
son
ATF 36163
PHEM T f
son
2*fo
Reflctr
Eiem nt
son
Reflctr
Eiem nt
V dd
JLz .
Figure 4.2. Circuit Configuration for Practical Frequency Doubler Design
C:\Research\Figures\practical_doub_design2 BD.ai
As done in the idealized design, the design o f the practical doubler consisted o f
varying the output fo reflector length (Loutfo), the input 2fo reflector length (Lin2 fo), and
the input power level (Pin) to achieve maximum conversion gain.
4.i.c. Implementation of Reflector Elements
The idealized design procedure (Section B.iv.b) utilized high-Q, lumped LC elements
to reflect the fo output signal and the 2fo input signal (as previously shown in Figure
3.129 on page 279). In order to facilitate fabrication o f a practical design, these reflector
elements were designed as lengths o f microstrip transmission line. These microstrip lines
were designed as quarter wavelength, open circuit stubs to reflect the desired harmonic
on the input and output. Utilizing the properties o f the circuit board used for fabrication
o f the multiplier, a length o f 50 ohm, quarter wavelength microstrip line was calculated
for the fundamental frequency (fo=3GHz) and second harmonic (2fo=6GHz). The
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376
specifications o f the circuit board and resulting quarter-wavelength microstrip stubs are
shown in Table 4.1.
Table 4.1. Circuit Board Properties and Quarter-Wavelength Stub Dimensions
D e scrip tio n
P a ra m e te r
Value
D ie le c tric C onstant
£r
2.2
Lo ss T angent
tanD
9 .0 E -4
C o n d u c to r T h ickn e ss (m ils)
T
1.4
H eight (m ils)
H
20
C onductivity
W id th of >JA S ection @
fo = 3 G H z (mils): 50 Ohms
Length o f k/4 S ection @
fo = 3 G H z (m ils )
W id th of A/4 S ection @
2fo= 6 G H z (mils): 50 Ohms
Length of A/4 S e ctio n @
2fo= 6 G H z (m ils)
G
3 .8 E + 7
W stub2
60
Lstub2
718
W s tu b i
60
L s tu b i
35 9
C:\Research\I_B_l UndrstndngNL Mech\C Practical Designs\test_multiplier_param_val_summary_10_21_03.sxc
These microstrip reflector elements were implemented in ADS. The response o f 821
versus frequency o f the networks is shown in Figure 4.3 below.
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377
(a) Output Network (M2) Response
(b) Input Network (M1) Response
(■
-10
-10
-30
-30
-35
-35
-40
10
Freq (GHz)
^0
,9
xIO
Freq(GHz)
Figure 4.3. Initial |S21| Response of Input and Output Quarter-Wavelength Stubs
C:\Research\l_B_l UndrstndngNL Mech\C Practical
Designs\jjsimpledoubIerl_writeup_10_13_03\jjsimpledoublerl_initial_M lM2_S21resp_10_14_03.fig
Note that, the output fo reflector (shown in Figure 4.3(a), where |S21| drops to zero at
3GHz) also reflects the third harmonic. This is a consequence o f using a transmission
line implementation for the output reflector element.
In order to improve the response o f the reflector elements, the ADS optimizer was
used. The widths and lengths o f the quarter-wavelength stubs were optimized to improve
the Q o f the reflector elements and create resonance exactly at the desired frequencies.
The initial and optimized dimensions o f the quarter-wavelength stubs are shown in Table
4.2 below.
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378
Table 4.2. Initial and Optimized Quarter-Wavelength Stnb Dimensions
D e s c rip tio n
P a ra m e te r Initial V a lu e
W id th o f W4 S e c tio n @
fo = 3 G H z (m ils )
L e n g th o f >JA S e c tio n
( 5 )fo = 3 G H z (n iils )
W id th o f W4 S e c tio n ( g
2 fo = 6 G H z (m ils )
L e n g th o f >/4 S e c tio n
2 fo = 6 G H z (m ils )
O p tim iz e d
V a lu e
% C hange
W s tu b 2
60
37
3 8 .3 3
L s tu b 2
718
720
0 .2 8
W s tu b i
60
27
55
L s tu b i
359
359
0
C:\R esearch\l_B_l UndrstndngN L Mech\C Practical Designs\test_multiplier_param_val_summary_10_21_03.sxc
As a result o f the optimization, the 1S21| response o f the input and output reflector
elements became more accurate and gained a higher Q. Figure 4.4 shows a comparison
o f the initial and optimized |S21| response o f the input and output networks. As the
figure shows, the response o f the networks was significantly improved by the
optimization.
(b) Input Network (M1) Response
(a) Output Network (M2) Response
-10
-10
-15
.-.-15
CQ
73
-20
—
— -25
-30
— Initial
•— Optimized
-30
-35
-35
-40.
10
Freq (GHz)
xIO®
^0
Freq (GHz)
xIO®
Figure 4.4. Initial and Optimized |S21| Response of Quarter-Wavelength Stnbs
C:\Research\l_B_l UndrstndngNL Mech\C Practical
Designs\jjsimpledoublerl_writeup_10_13_03\jjsimpledoublerl_opt_MlM 2_S21resp_10_14_03.fig
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379
4.i.d. Conversion Gain Response versus Refiector Lengths
The next step in the design process was to implement the full doubler configuration of
Figure 4.2 in ADS. The circuit consisted of: the optimized reflector elements presented
in Section 4.i.c; input and output reflector offset microstrip lines o f length Linifo and
Loutfo; and the generalized PHEMT model previously presented in Section
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380
2.iii on page 39. Utilizing this circuit, a simultaneous sweep* o f the input power, the
input 2fo reflector length (Lin2fo=L2), and the output reflector length (Loutfo=L3).
Similar to the idealized case presented in Section 3.iv.b.2 on page 280, by utilizing a
simultaneous sweep o f the above parameters a point o f maximum second harmonic
conversion gain was found. The maximum 2fo conversion gain was 3.5 dB and occurred
for an input power level o f 2dBm, an input reflector length (Lin2fo=L2) o f 900 mils, and
an output reflector length (Loutfo=L3) o f 1300 mils. In order to further improve this
maximum 2fo conversion gain, the ADS optimizer was once again employed. Utilizing
the optimizer, the input reflector length Lin2 fo (L2) and output reflector length Loutfo (L3)
were adjusted to achieve further improvement in the 2fo conversion gain. This resulted
in a maximum 2fo conversion gain o f 3.54 dB, representing a very slight, 0.04 dB
improvement.
Table 4.3. Initial and Optimized Reflector Oflset Lengths
D escription
P aram eter
Initial V a lu e - F r o m
Sim ultaneous Sw eep
O ptim ized
Value
% C hange
Fundam ental Frequency (to)
Output R eflector Lenqth (mils)
S econd Flarm onic (2fo) Input
R eflector Lenqth (mils)
Lout,io=L3
1300
1325
1.92
L in ,o = L 2
900
911.5
1.28
C:\R esearch\l_B_l Undrstndng NL Mech\C Practical Designs\test_multiplier_param_val_summary_10_21_03.sxc
The initial and optimized values o f the input and output reflector lengths are shown in
Table 4.3. As shown in the table, using the ADS optimizer to optimize the reflector
offset lengths (Loutfo and Lin2 fo), did not result in a significant change. The resulting
improvement in conversion gain (from 3.5 to 3.54 dB), was not significant.
The idealized analysis o f Section 3.iv.b.2 (page 280) showed that the 2fo CG varied
drastically with variation in the input and output reflector lengths. In order to examine
T he id ea o f a sim u ltan eou s sw ee p w a s defin ed on page 101
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381
this variation in more detail for a practical case, the 2fo CG was analyzed with changes in
Loutfo and Lout2 fo. Figure 4.5 shows the simulated 2fo CG versus the output reflector
length (Loutfo). at the optimum input reflector length (Linifo = L3 = 911.5 mil) and input
power level (Pin = 2dBm).
Loutfo (deg)
4
25
50
75
100
125
150
175
200
225
200
400
600
800
1000
1200
1400
1600
1800
3
CQ
2
£
CN
CD
1
O
0
1
Loutj^ (mils)
Figure 4.5. Second Harmonic Conversion Gain vs fo Output Reflector Offset Length (Loutfo)
C:\Research\l_B_l Undrstndng NL Mech\C Practical
Designs\jjsimpIedoublerI_writeup_10_13_03\jjsimpIedoublerl_CG2fo_vs_Loutfo_p!ot_10_14_03.fig
The figure shows that the fo output reflector has a very significant effect on the
second harmonic conversion gain. A minimum 2fo CG o f -1 dB occurs for an output
reflector length o f 650 mil compared to a maximum o f 3.54 dB occurring for an output
reflector length o f 1325 mil (165.7 deg).
The 2fo CG response versus the input 2fo reflector length Lin2 fo, at the optimum input
power (Pin = 2dBm) and output reflector length (Loutfo = 1325 mil), is shown in Figure
4.6. The figure shows that the 2fo input reflector length also causes drastic variation in
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382
the 2fo CG. Here a very low minimum 2fo CG o f -23 dB is reached for an input reflector
length o f 250 mil. The maximum 2fo CG o f 3.5 dB occurs at a length o f 911.5 mil (114
deg).
Liri2f„(deg*
25
50
75
100
125
150
175
200
200
400
600
800
1000
1200
1400
1600
-15
-20
-2 5
-3 0
Lin,
Lin 2 f^ (mils)
* D e g re e s with r e s p e c t to the fundam ental frequency fo
Figure 4.6. Second Harmonic Conversion Gain vs 2fo Input Reflector Offset Length (Linxfo)
C:\Research\l_B_l Undrstndng NL Mech\C Practical
Designs\jjsimpledoublerl_writeup_10__13_03\jjsimpledoublerl_CG2fo_vs_Lin2foj3lot_10_14_03.fig
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383
-10
-15
-20
-10
m
- -15
£
@
O -20
O
CM
O
-30
-10
-25
-35
-15
-30
-40
3.2
.2
Freq (GHz)
Freq (GHz)
Freq (GHz)
Figure 4.7. Simulated Conversion Gain Response vs Fundamental Frequency
C:\R esearch\l_B_l Undrstndng NL Mech\C Practical Designs\jjsimpledoublerl_plots_11_05_03\
jjsimpledoublerl_CG_fo_plot_simonly_zoomed_vgo_mO_6_pin_2dbm_l l_05_03.fig
The 2fo CG versus fundamental frequency response o f the optimum doubler
configuration (Pin = 2dBm, Loutfo = 1325 mil, Linifo = 911.5 mil) is shown in Figure 4.7.
Figure 4.7(b) shows the 2fo CG level reaches a maximum of 3.54 dB (at fo=2.98 GHz)
and that the 3dB fractional bandwidth o f the doubler is 10.5%. At the frequency o f
maximum 2fo CG (fo=2.98GHz), Figure 4.7(a) shows a harmonic rejection o f -21.5 dB at
the fundamental frequency and Figure 4.7(c) shows a harmonic rejection o f -34 dB at 3fo.
As previously studied in depth in Chapter 3, ensuring that a large conversion gain does
not come at the expense o f the output power is an important aspect o f doubler design. In
order to verify that the doubler design had a reasonable output power response, the 2fo
CG, Pout and MP o f the circuit was simulated. This response is shown in Figure 4.8.
Figure 4.8 shows that at the point o f maximum 2fo CG (CGifo = 3.54 dB at Pin = 2
dBm), a reasonably large 2fo output power o f 5.54 dBm is aehieved. In an alternative
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384
design, the point o f maximum multiplier power (MP = 10 at Pin = 4 dBm) can be utilized
to result in a 2fo CG o f 3 dB and an output power o f 7 dBm. This alternative design
results in a 1.46 dB improvement in the 2fo Pout while only dropping the 2fo CG by .54
dB. Although this alternative design gives a good result, the maximum CG design also
gave an adequate output power response, and is the design presented in the remainder o f
this section (Section 4.i).
MP 2f<>
9.08 dBpi
CM
CG 2fo
3.54
Pout 2fo
5.54 dB ^
CG2fo
_3 d_^_ ^
MP2fo
10 dBm
P outifo
7dBrh
-10
- M P 2fo
■ C G 2 fo
■ Pout2fo
-15
-20
Pin (dBm)
Figure 4.8. Simulated 2fo CG, MP and Pout vs Pin Response of Doubler
C:\Research\l_B_l Undrstndng NL Mech\C Practical
Designs\jjsimpledoublerl j(lots_ll_05_03\jjsim pledoublerl_M P_CG_pIot_sim only_vgo_m 0_6_l l_05_03.fig
4.i.e. Fabrication
The optimized frequency doubler design shown in Section 4.i.d was fabricated on
microstrip circuit board. The circuit board layout was implemented utilizing a
photolithographic process. Figure 4.9 shows the layout o f the doubler design.
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385
W s tu b 2
W s tu b t
1“
1
1^
^
L1
1
j^
f—
x t r F ix t u r e
5
1
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€
(JJ
11
L3=Lou^o
j1
L 2 = L irfe fo
2fo Input
Reflector
Element
c
cr
NJ
^
^
'-4
fo Output
Reflector
Element
Figure 4.9. Layout of Frequency Doubler
C :\users\default\ads\fixtures_prj\jj sim pledoublerjay out_B.ai
The designed and realized dimensions o f the doubler circuit (shown in Figure 4.9) are
summarized in Table 4.4 below.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
386
Table 4.4. Designed (Simulated) and Actual Fabricated Dimensions of Frequency Doubler Circuit
P a ra m e te r
F in a l S im u la te d
V a lu e
A ctual
F a b ric a te d
V a lu e
% Change
L1 (m il)
500
5 0 2 .5
0.5
W 1 (m il)
60
6 9 .5
13.7
9 1 1 .5
9 0 9 .5
0 .2
60
6 8 .5
12.4
13 2 5
1 3 2 2 .5
0.2
W 3 (m il)
60
6 9 .5
13.7
L4 (m il)
500
4 9 1 .5
1.7
W 4 (m il)
60
6 6 .5
9.8
Input 2 fo R e fle c to r
S tub L in e L e n q th
L s tu b i (m il)
359
3 6 4 .5
1.5
Input 2 fo R e fle c to r
S tu b L in e W id th
W s tu b i (m il)
27
3 5 .5
2 3 .9
O u tp u t fo R e fle c to r
S tub L in e L e n q th
L s tu b 2 (m il)
720
7 2 8 .5
1.2
O u tp u t fo R e fle c to r
W s tu b 2 (m il)
S tu b L in e W id th
37
44
15.9
D ie le c tric C o n s ta n t
2.2
2 .2 8
3.5
D e s c rip tio n
Input 5 0 Q Lin e
L e n a th
Input 5 0 Q L in e
W id th
Input 2 fo R e fle c to r
O ffs e t L in e Le ng th
Input 2 fo R e fle c to r
O ffs e t Line W id th
O u tp u t fo R e fle c to r
O ffs e t L in e L e n g th
O u tp u t fo R e fle c to r
O ffs e t Line W id th
O u tpu t 5 0 Q Line
L en a th
O u tp u t 5 0 Q Line
W id th
L in ,,.= L 2
(m il)
W 2 (m il)
Lout, = L 3
(mil)
C:\R esearch\l_B_l Undrstndng NL Mech\C Practical Designs\test_multiplier_param_val_summary_10_21_03.sxc
As shown in Table 4.4, the fabricated dimensions varied by up to 23.9%. The
implications o f this variation in dimensions are analyzed by conducting a simulated back
analysis, to be discussed in Section
4.i.f below. Figure 4.10 shows an image o f the actual doubler.
R e p r o d u c e d with p e r m is s io n of t h e cop y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e r m is s io n .
387
Figure 4.10. Im age o f Practical Frequency Doubler
C:\Research\lab_pics\prac_doubler_image2.JPG
Measured Response of Doubler
The fabricated frequency doubler circuit was characterized using the large-signal
measurement system previously shown in Figure 2.6 on page 28. The doubler was
measured over the following input conditions:
•
A gate bias voltage range (VGO) o f -0.7 to -0.5 V.
•
A drain bias voltage (Vdd) o f 2.5 V.
•
An input power range (Pin) o f 0 to 7 dBm.
•
A fundamental frequency range (fo) o f 2.5 to 3.5 GHz.
Figure 4.11 shows the measured CG versus frequency response o f the fabricated
doubler for an input power o f 2 dBm. It also shows the initial simulated result
(previously shown in Figure 4.8) as well as the simulated “hack analysis” (where the
actual circuit dimensions from Table 4.4 were utilized in a re-simulation o f the doubler in
ADS). A small change in the dielectric constant (from 2.2 to 2.28, Table 4.4) was also
R e p r o d u c e d with p e r m is s io n of t h e cop y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e r m is s io n .
388
included in the back analysis, which showed a slightly better prediction o f the doubler’s
response.
-15
-10
-20
XI
-25
CO
O
O
-30
-20
O -35
O -10
-25
■40
-15
-30
-45
Freq (GHz)
Freq (GHz)
—
—
S im
M eas
B ack
Freq (GHz)
Figure 4.11. Conversion Gain vs Fundam ental Freqnency o f Doubler Design: M easured, Sim ulated
and Back Analysis
C:\Research\l_B_l Undrstndng NL Mech\C Practical
DesignsVysimpIedoubIerlj3lots_ll_05_03\jjsimpledoublerl_CG_fojjlot_sim_meas_backanaladj2_zoomed_vgo_m0_6_pin_2dbm_l
l_06_03.fig
Figure 4.11 shows a fairly close correspondence between the measured and initial
simulated response for fo and 3fo. By conducting the back analysis, the agreement with
the measured response becomes much closer. However, even with the back analysis, the
2fo CG response shows some error. This error is attributed to inaccuracy in the model,
and occurs since the input power utilized for this design (Pin=2dBm) is slightly below the
minimum o f the range the model was optimized for (4dBm < Pin < 1 0 dBm). Although
some error is shown, the match between the measured and simulated 2 fo conversion gain
is very reasonable.
R e p r o d u c e d with p e r m is s io n of t h e cop y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e r m is s io n .
389
The pertinent results exhibited in Figure 4.11 are summarized in Table 4.5 below.
Table 4.5. Sum m ary o f Pertinent Results for Simulated, M easured, and Back Analysis o f Frequency
Doubler
D iffe r e n c e
IM eas-BackI
D escription
P a r a m e te r
Sim u lated
M e a su r e d
B a c k A nalysis
M aximum 2fo
C o n v e r sio n Gain
F re q u en cy of Maximum
2fo C on v e rsion Gain
Fractional Bandwidth
Fundam ental F re q u en cy
R ejection atfo^^^
C G ,,, (dB)
3 .5 4
7
3.7
3 .3
fo m a x ’•(GHz)■'
2 .9 8
2 .8 4
2 .9 2
0 .0 8
F B W (%)
10.5
6 .4 5
9 .8 6
3.41
C G ,J d B )
- 2 1 .5
- 1 5 .8 3
-24
8 .1 7
C G 3 „ (d B )
-34
- 1 8 .1 7
-30
1 1 .8 3
Third Flarmonic
R ejection atfo^^^
C:\R esearch\l_B_l Undrstndng NL Mech\C Practical Designs\test_multiplier_result_summary_l I_06_03.sxc
Referring to Table 4.5 and Figure 4.11, the measured 2fo CG was slightly higher than
expected from simulation, reaching a maximum o f 7 dB at a frequency o f 2.84 GHz. The
figure also shows that the back analysis gave a 3.7 dB maximum 2fo CG at an input
frequency o f 2.92 GHz. There was a 3.3 dB difference in the value o f the maximum 2fo
CG between the measurement and the back analysis and the frequencies at which the
maxima occurred were different by 0.08 GHz. The fractional bandwidth o f the measured
doubler was 6.45%, which was smaller than the 9.86% percent fractional bandwidth
predicted by the back analysis. Also, the measured response had less harmonic rejection
(-15.83 dB at fo and -18.17 dB at 3fo) than predicted by the back analysis (-24 dB at fo
and -30 dB at 3fo).
Overall, as Figure 4.11 shows, the simulated (back-analysis) and measured doubler
responses are in reasonable agreement. This agreement shows the efficacy o f the
generalized model presented in Chapter 2 in predicting the response o f a practical
nonlinear circuit design. The large conversion gain exhibited by the doubler shows that
R e p r o d u c e d with p e r m i s s io n o f t h e cop y rig h t o w n e r. F u r th e r re p ro d u c tio n p rohib ited w itho ut p e r m is s io n .
390
the idealized multiplier configuration presented in Chapter 3 (Idealized Design 2, Case
B 1 : in Section 3.iv.b.2, page 280) can also be utilized to create practical designs.
R e p r o d u c e d with p e r m is s io n of t h e cop y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e r m is s io n .
391
4.U. Practical Frequency Tripler Design
4.11.a. Introduction
In addition to the frequency doubler presented in the previous section, a high CG
frequency tripler was also designed. The design process followed a similar procedure as
the doubler, and is presented in Sections 4.ii.b through 4.ii.g below.
4.11.b. Choice of Bias Point
Just as in the case o f the doubler, the first step in the tripler design was choosing the
bias point. This was done by observing the measured 3fo CG o f the PHEMT as a
function o f the gate bias (VGO). Figure 4.12 shows the 3fo CG versus the gate bias for
several input power levels. This measured data utilized the measurement setup shown
previously in Figure 2.6 on page 28. This data was taken for 4 transistors and the data
shown is the average o f these measurements. Note that, although this design is similar to
the tripler design previously presented by Mima [34], for this design the bias point was
chosen utilizing the actual measured response o f the transistor. In [34], the bias point
was chosen based on simulation o f the transistor model.
The response in Figure 4.12 shows that the transistor has a large 3fo CG for gate bias
voltages ranging from -0.3 to 0.2 V. A gate bias o f 0.1 V was selected because it gives a
large 3fo CG and represents the midway point between pinchoff (Vp=-0.6V) and forward
conduction (Vfwd=0.8V). As previously shown in Section 3.ii.a.5.v, this gate bias is that
which gives an optimum 3fo CG (case A l, as shown in Table 3.3, page 104).
R e p r o d u c e d with p e r m is s io n of t h e cop y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e r m is s io n .
392
The drain bias (Vdd) was set midway between the knee (Vki) and reverse-breakdown
(Vrbd) voltages, the optimum point given from analysis o f the idealized model (as
presented in Section B.iii.a, page 178 and Section B.iii.c, page 224).
y
-10
Pin = 0
Pin = 2
Pin = 4
Pin = 6
- - Pin = 8
Pin = 10
Vgo (V)
Figure 4.12. Measured 3fo Conversion Gain vs Gate Bias for Several Input Power Levels
C:\R esearch\l_B_l Undrstndng NL Mech\C Practical Designs\jjsimpletriplerl_b_writeup_10_21_03\
Xtr36a_maxCG3fosearch_neat_fo_3G_10_21_03.fig
4.ii.c. input and Output Network Configuration
The input and output configuration for the tripler design was chosen based on the
idealized design (design B) in Section B.iv.c.B, on page B55. This design consists o f a fo
and 2fo output reflector network and a 2fo and Bfo input reflector network. For this
practical design, the reflector elements were implemented as microstrip transmission
lines with the exception o f the fo reflector on the output. Due to the repeating nature o f
transmission line responses, the fo reflector element could not be implemented as a
transmission line stub because it would also reflect the third harmonic. This problem was
R e p r o d u c e d with p e r m is s io n of t h e cop y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e r m is s io n .
393
circumvented by using a lumped, parallel LC circuit to reflect the fundamental frequency
at the output, a method previously utilized by Mima [34]. The circuit configuration is
shown in Figure 4.13.
M icrostrip Circuit B oard
W stub2
W stu b i
U t u b l o n ; W s tu b lo u t
L stubi
fo
Elem nt ^ 3 g re so
PHEMT
R n e n -5 0 il
,
^
3
Reflctr
Elem nt
2
Reflctr
Elem nt
=Lout3fo
— 2fo
Reflctr
Elemnt
Vg*sln((oot)
R d d = 1 .in
Vdd
Figure 4.13. Circuit Configuration for Practical Frequency Tripler Design
C:\Research\Figures\practical_trip_design3 BD.ai
As previously discussed for the idealized case in Section 3.iv.c.3 (page 355), the
networks providing maximum 3fo CG are obtained by optimizing the reflector offset
lengths Linifo, Linsfo, Loutfo, and Loutafo. For this realistic case, a similar method was
used. However, instead o f a simultaneous sweep* o f the offset lengths (as done for the
idealized case), the lengths were optimized using the ADS optimizer. The optimization
procedure for the practical tripler design is discussed in Section 4.ii.e below.
4.ii.d. Implementation of Reflector Networks
As in the case o f the doubler, the reflector networks for the tripler were designed in
ADS to give a high-Q and resonate exactly at the frequencies o f interest. The initial
lengths o f the quarter-wavelength stubs were:
•
359 mil (Lstubl=359 mil) for the quarter-wavelength input stub at 2fo ( 6 GHz)
•
239.3 mil (Lstub2=239.3 mil) for the quarter-wavelength input stub at 3fo (9GHz)
T he id ea o f a sim u ltan eou s sw ee p w a s d efin ed on page 101
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394
•
359 mil (Lstublout=359 mil) for the quarter-wavelength output stub at 2fo
( 6 GHz)
The initial widths o f the stubs were all set to the optimum value obtained for the
practical doubler design (presented in Section 4.i in Table 4.2, page 378). These widths
were:
•
27 mil (Wstubi =27 mil) for the quarter-wavelength input stub at 2fo (6 GHz)
•
27 mil (Wstub2=27 mil) for the quarter-wavelength input stub at 3fo (9GHz)
•
27 mil (Wstubiout=27 mil) for the quarter-wavelength output stub at 2fo ( 6 GHz)
For the parallel LC fundamental frequency open circuit, the capacitance (Csgreso) and
inductance (Lsgreso) values had to be chosen. A 0.6 pF capacitance was selected for the
capacitor based on lab component availability. The actual capacitor utilized in the
fabrieated design (to be shown in Section 4.ii.f) was a surface mount, chip type, which
was mountable on microstrip line. For simulation purposes, the built in ADS model for
the chip capacitor was used. Given the capacitance value, the corresponding inductance
(L 3 greso) was set to give resonance at the fundamental frequency (fo = 3GHz). The initial
value for the reflector elements are summarized in Table 4.6.
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395
Table 4.6. Initial Param eter Values for Input and Output R eflector Elem ents
D e s c rip tio n
P a ra m e te r
Initial V a lu e
W s tu b 2
27
L stu b 2
2 3 9 .3 3
W s tu b i
27
L s tu b i
359
W id th o f Input A/4
S e c tio n @ 3 fo = 9 G H z
(m ils)
L e n g th o f Input A/4
S e c tio n @ 3 fo = 9 G H z
(m ils)
W id t h o f Input A/4
S e c tio n @ 2 fo = 6 G H z
(m ils)
L e n g th o f Input A/4
S e c tio n @ 2 fo = 6 G H z
(m ils)
W id th o f Output A/4
S e c tio n @ fo = 6 G H z
(m ils)
W s tu b i
,
27
.
359
out
L e n g th o f A/4 Output
S e c tio n @ 2 fo = 6 G H z
(m ils)
C a p a c ita n c e value
f o r L C C irc u it ( d F)
In d u cta n ce value fo r
L C C irc u it (nH)
L s tu b i
out
c
S greso
^S greso
0.6
4 .6 9
C:\R esearch\l_B_l Undrstndng NL Mech\C Practical Designs\test_multiplier_param_val_summary_10_2 l_03.sxc
The parameters in Table 4.6 were used to implement the reflector elements on the
input and output. The rest o f the interconnecting microstrip lines were simply 50 ohm
lines (as shown in Figure 4.2). As such, the lengths o f the interconnecting lines did not
effect the |S21| response, and were simply set to 500 mil (i.e. Lin, L9g, L 6 g, L6 gout,
L3gout, Lout were all set to 500 mil). The resulting computed |S211 response o f the
output and input networks versus frequency is shown in Figure 4.14.
R e p r o d u c e d with p e r m is s io n of t h e cop y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e r m is s io n .
396
(b) Input Network (M1) Response
(a) O utput Network (M2) Response
-10
-10
-30
-30
-35
-35
-40
10
Freq (GHz)
x IO
9
-40
Freq (GHz)
xIO
9
Figure 4.14. |S21| vs Freq of: (a)Output Reflector Network; (b) Input R eflector Network
C:\Research\l_B_l Undrstndng NL Mech\C Practical
Designs\jjsimpletripIerl_b_writeup_10_2I_03\jjsimpletriplerl_b_init_MlM 2_S21resp_10_21_03.fig
Figure 4.14(a) shows the response o f the output network. The 2fo reflector shows
sharp resonance exactly at 6 GHz (2fo). However, the fo reflector is slightly off its
designed resonant frequency o f 3GHz.
Figure 4.14(b) shows the |S211 response o f the input network. Like the output 2fo
reflector, the 2 fo input reflector shows resonance exactly at the designed frequency
(6GHz=2fo). The 3fo input reflector is slightly off its designed resonant frequency o f 9
GHz.
In order to improve the response o f the reflector networks, the ADS optimizer was
once again utilized. The lengths and widths o f the stubs, and the value o f the inductance
Lsgreso were optimized so that the reflector elements gave resonance exactly at the desired
frequency. The initial and optimized dimensions are compared in Table 4.7 below.
R e p r o d u c e d with p e r m i s s io n o f t h e cop y rig h t o w n e r. F u r th e r re p ro d u c tio n p rohib ited w itho ut p e r m is s io n .
397
Table 4.7. Initial and Optimized Param eter Values for Input and Output Reflector Elem ents
D e s c rip tio n
W id th o f Input >v/4 S e c tio n
@ 3 fo = 9 G H z (m ils /o h m s )
P a ra m e te r
Initial V a lu e
O p tim iz e d
V a lu e
% C hange
W s tu b 2
2 7 /7 9 .1
3 7 /6 6 .9
3 7 .0 4
L stu b 2
2 3 9 .3 3
2 3 2 .7
2 .7 7
W s tu b i
2 7 /7 9 .1
2 7 .5 /7 8 .4
1.85
L s tu b i
359
3 5 8 .5
0 .1 4
,
2 7 /7 9 .1
2 7 .5 /7 8 .4
1.85
,
359
3 5 8 .5
0 .1 4
0.6
0.6
0
4 .6 9
4 .3 8
6 .7 2
L e n g th o f Input >J4
S e c tio n @ 3 fo = 9 G H z
(m ils)
W id th o f Input W 4 S e c tio n
@ 2 fo = 6 G H z (m ils /o h m s )
L e n g th o f Input X/4
S e c tio n @ 2 fo = 6 G H z
(m ils)
W id th o f Output }J 4
S e c tio n @ fo = 6 G H z
(m ils /o h m s )
W s tu b i
out
L e n g th o f >J4 Output
S e c tio n @ 2 fo = 6 G H z
(m ils)
C a p a c ita n c e v a lu e fo r L C
C irc u it (p F )
In d u cta n ce va lu e fo r L C
C irc u it (nH)
L s tu b i
out
c
Sgreso
^S greso
C:\R esearch\l_B_l Undrstndng NL Mech\C Practical Designs\test_multiplier_param_val_summary_10_21_03.sxc
The input and output networks utilizing the optimized parameter values in Table 4.7
were re-simulated in ADS. Figure 4.15 compares the initial and optimized |S211 versus
frequency response.
R e p r o d u c e d with p e r m is s io n of t h e cop y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e r m is s io n .
398
(b) Input Network (M1) Response
(a) O utput Network (M2) Response
-10
-10
-15
-30
—
—
Initial
O ptim ized
-30
-35
-35
-40
0
Freq (GHz)
xIO
9
^0
Freq (GHz)
xIO
9
Figure 4.15. |S21| vs Freq of: (a)Output Reflector Network; (b) Input R eflector Network:
Comparison o f Initial and Optimized Response
C;\Research\l_B_l Undrstndng NL Mech\C Practical
Designs\jjsimpletripIerl_b_writeup_10_21_03\jjsimpletriplerl_b_opt_M lM2_S21resp_10_21_03.fig
As Figure 4.15(a) shows, optimization resulted in the resonant frequency o f the 3GHz
(fo) reflector becoming more accurate. The resonance o f the 9GHz (3fo) input reflector
was also improved as shown in Figure 4.15(b).
4.ii.e. Optimizing Refiector Offset Lengths for Maximum 3fo
Conversion Gain
The next step in the design process was to optimize the reflector offset lengths
(Lin2 fo=L6 g, Lin3 fo=L9 g, Loutfo=L3gout, Lout2 fo=L6 gout, as shown in Figure 4.13, page
393) for maximum third harmonic conversion gain as was discussed earlier for the ideal
case (Section 3.iv.c.3, page 355). Due to the fact that there were four lengths to adjust.
R e p r o d u c e d with p e r m is s io n of t h e cop y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e r m is s io n .
399
which meant a very large Harmonic Balance parameter sweep*, this step was bypassed
for the tripler design. The values o f the four reflector offset lengths (Lin2 fo=L6 g,
Lin3 fo=L9 g, Loutfo=L3gout, Lout2 fo=L6 gout) were instead set to a median value o f 500 mil^
and then optimized directly using the ADS optimizer. Using this method the
maximum 3fo conversion gain was found. The optimization was conducted for several
different input power levels between 4 and 10 dBm, where the measured conversion gain
response o f the transistor itself (with no reflectors present, as shown in Figure 4.12, page
392) exhibited a large 3fo CG. The results o f the optimization are summarized in Table
4.8, which shows the initial and optimized reflector offset lengths. Note that the
maximum COMPUTED 3fo CG occurred at an input power level o f 6 dBm.
Table 4.8. Initial and Optimized Reflector OfTset Lengths
O p tim iz e d
% Change
P a ra m e te r
Initial V a lu e
Input R e fle c to r L e n g th
L i"3 ,.= L 9 g
500
1 9 8 .7
6 0 .2 6
(m ils)
S e c o n d H a rm o n ic (2 fo )
Input R e fle c to r Le n g th
L in „ „ = L 6 g
500
782.1
5 6 .4 2
(m ils)
S e c o n d H a rm o n ic
F re q u e n c y (2 fo ) Output
L o u t,,.= L 6 g ..,
500
6 5 8 .2
3 1 .6 4
L o u t,„= L 3 g ,„
500
6 3 4 .2
2 6 .8 4
D e s c rip tio n
V a lu e
T h ird H a rm o n ic (3fo)
R e fle c to r L e n a th (m ils)
F u n d a m e n ta l F re q u e n c y
(fo) Output R e fle c to r
L e n a th (m ils )
C:\R esearch\l_B_l Undrstndng NL Mech\C Practical Designs\test_m ultiplierjaram _val_summ ary_10_21_03.sxc
* This refers to the concept o f a simultaneous sw eep as previously defined on page 101. In this case the
sw eep w ould in volve simulation o f all com binations o f Lin 2 fo, Linsfo, Loutfo, and Lout 2 fo over a w ide range
o f values.
^ This length w as chosen arbitrarily near the middle (500m il=62.5 degrees) o f the full range o f f possible
offset lengths (from 0 to 180 degrees).
R e p r o d u c e d with p e r m is s io n of t h e cop y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e r m is s io n .
400
The conversion gain versus fundamental frequency response, resulting from
simulation o f the tripler circuit utilizing the optimized values in Table 4.8, is shown in
Figure 4.16.
-10
-10
-15
m
■o
-20
-20
-25
CO
-25
-30
-35
-30
-40
-35
^ -1 0
O
2
Freq (GHz)
Freq (GHz)
Freq (GHz)
Figure 4.16. Simulated Conversion Gain vs Frequency Response o f Practical Tripler Design;
(Pin=6dBm)
C:\Research\l_B_l Undrstndng NL Mech\C Practical
Designs\jjsimpletriplerl_b_writeup_l0_21_03\jjsimpletriplerl_b_CG_vs_freq_sim_pin_6dbm_l l_07_03.fig
Figure 4.16(c) shows the 3fo CG reaches a maximum of 2.9 dB at a frequency of
2.98 GHz (fomax = 2.98 GHz), with a 3dB fractional bandwidth of 8.75%. At the
frequency o f maximum Bfo CG (fomax=2.98 GHz), Figure 4.16(a) shows a harmonic
rejection o f -28.2 dB at the fundamental frequency and Figure 4.16(b) shows a harmonic
rejection o f -26.5 dB at 2fo.
As previously studied in depth in Chapter 3 (and examined in Section 4.i.d, page 379),
ensuring that a large conversion gain does not come at the expense of the output
power is an important aspect of multiplier design. In order to verify that the tripler
R e p r o d u c e d with p e r m is s io n of t h e cop y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e r m is s io n .
401
design had a reasonable output power response, the 3fo CG, Pout and MP o f the circuit
was simulated. This response is shown in Figure 4.17.
MP 3fo
CG 3fo
Pout 3fo
CO
-10
Pin (dBm)
Figure 4.17. Simulated 3fo CG, M P and Pout vs Pin Response o f Tripler
C:\R esearch\l_B_l Undrstndng NL Mech\C Practical Designs\jjsimpletriplerl_b_writeup_10_21_03\
jj simpletripler l_b_CG_MP_Pout_sim_ 11_07_03.fig
Figure 4.17 shows that at the point o f maximum 3fo CG (CGsfo = 2.9 dB at Pin = 6
dBm), a reasonably large 3fo output power o f 8.7 dBm is achieved. The point of
maximum multiplier power (MP = 11.5) also occurs at the same input power level (Pin =
6 dBm). The fact that the maximum 3fo CG and MP occur at the same input power level
gives assurance that the design gives a reasonable 3fo output power level.
R e p r o d u c e d with p e r m i s s io n o f t h e cop y rig h t o w n e r. F u r th e r re p ro d u c tio n p rohib ited w itho ut p e r m is s io n .
402
Fabrication of Frequency Tripler
The optimized tripler design presented in the previous section was fabricated utilized
the same techniques previously presented for the frequency doubler. The circuit board
layout is shown in Figure 4.18.
Parallel LC Fixtur(
Wstublo^jt
Xtr Fixture
Wstub2
For fo Output
Rflctr Element
\
W stubi
ON
IQ
O
c
L6gbut=Lout2fo \ L3gbut=Loutfo
3fo Input
Rflctr Element L9g=Liri3fo
2fo Input
RActr Element
2fo Input
Rflctr Element
Figure 4.18. Circuit Board Layout for Fabricated Tripler
C:\users\default\ads\fixtures_prj\jjsimpletripler_b_layout.ai
For the frequency tripler design, a lumped, parallel LC fundamental frequency
reflector element was utilized. This element was fabricated on the “Parallel LC Fixture”
area o f the layout shown in Figure 4.18 as follows. First, the chip capacitor was soldered
across the gap in the microstrip shown on the layout. Second, an inductor was realized
using a half-turn o f copper wire soldered in parallel with the chip capacitor. The value o f
inductance was adjusted by varying the tilt o f the inductor coil relative to the circuit
board. This technique for implementing an fo reflector element on the tripler output
follows that o f Mima [34].
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403
Table 4.9 shows the designed (optimum) circuit dimensions along with the actual
fabricated dimensions.
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404
Table 4.9. Designed and Fabricated Dim ensions o f Frequency Tripler
P a r a m e te r
Final S im ulated
Value
Actual
F ab ricated
Value
% Change
Length
Lin (mil)
500
4 9 2 .5
1.5
Input 5 0 Q Line Width
Win (mil)
60
6 9 .5
13 .7
Input 3fo R efiector Offset
Line Length
L9g=Lin3f„
1 9 8 .7
1 9 4 .5
2 .2
60
6 9 .5
1 3.7
782 .1
775
0 .9
60
6 9 .5
13 .7
6 5 8 .2
657.5
0.1
W 6 g ,^ (mil)
60
69.5
1 3 .7
L3g„^ (mil)
634 .2
6 2 9 .5
0 .7
W3g„^ (mil)
60
71
15 .5
Output 5 0 Q Line Length
Lout (mil)
500
493
1.4
Output 5 0 Q Line Width
W out (mil)
60
70
14 .3
Input 2fo R eflector Stub
Line Length
Lstubi (mil)
3 5 8 .5
3 6 4 .5
1.6
Input 2fo Reflector Stub
Line Width
W s t u b i (mil)
2 7 .5
3 6 .5
2 4 .7
Input 3fo R eflector Stub
Line Length
Lstub2 (mil)
2 3 2 .7
238.5
2.4
Input 3fo R eflector Stub
Line Width
W stub 2 (mil)
3 6 .3
47
2 2 .8
D escription
Input 5 0
Q Line
Input 3fo R eflector Offset
Line Width (5 0 Q )
Input 2fo R eflector Offset
Line Length
Input 2fo R eflector Offset
Line Width (5 0 Q )
(mil)
W 9 g (mil)
L6g=Lin^„
(mil)
W 6 g (mil)
Output 2fo R eflector Offset L 6g^,=Lou^„
Line Length
(mil)
Output 2fo Reflector Offset
Line Width (5 0 Q )
Output fo Reflector Offset
Line Lenath
Output fo R eflector Offset
Line Width (5 0 Q )
Output fo Reflector Stub
Line Lenath
Output fo Reflector Stub
Line Width
Output Parallel LC
Inductance Value
Lstubi
(mil)
3 5 8 .5
368
2 .6
W stubi
(mil)
2 7 .5
3 7 .5
2 6 .7
4 .3 8
Not Available
Not A vailable
(nH)
C:\R esearch\l_B_l Undrstndng NL Mech\C Practical Designs\test_m ultiplierjaram _vai_summ ary_10_21_03.sxc
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405
As the table shows, tolerance limits o f the fabrication process can result in up to
26.7% difference between the designed and fabricated dimensions. As already discussed
in the case o f the frequency doubler, this variation in the dimensions was a source o f
error between the measured and designed response. This error was examined by
conducting a simulated back analysis, shown in the next section. Figure 4.19 shows an
image o f the practical frequency tripler.
Figure 4.19. Image o f Practical Frequency Tripler
C;\Research\lab_pics\prac_tripler_image2.jpg
4.ii.g. Tripler Conversion Gain Response
The response o f the fabricated tripler circuit was measured on the large-signal
measurement system previously used to measure the device itself (as previously shown in
Figure 2.6 on page 28). Figure 4.20 shows the measured conversion gain response versus
the fundamental frequency for an input power o f 6 dBm. The figure includes the
simulated (designed) response and a back analysis o f the tripler using the actual realized
dimensions (from Table 4.9).
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406
-10
a
-10
-15
-15
-25
v\- f
^
CO-2 0
■o
£ -2 5
CN
@-30
-30
- -M-
-35
-20
’#J- -
CO
O
III
-35
-40
-40
-45
Freq (GHz)
-10
Freq (GHz)
— Sim
■— Meas
Back
Freq (GHz)
Figure 4.20. Conversion Gain Response o f Practical Frequency Tripler at Pin=6dBm
C:\R esearch\l_B_l UndrstndngNL Mech\C Practical Designs\jjsimpletriplerl_b_writeup_10_21_03\
jjsim pletriplerl_b_CG_vs_freq_sim_meas_back_pin_6dbm_ll_07_03.fig
As shown in Figure 4.20, very close correspondence between the measured and
simulated response is shown, and the back-analysis brings the simulated response even
closer to the measurement. The pertinent results exhibited in Figure 4.20 are summarized
in Table 4.10 below.
Table 4.10. Sum mary o f Pertinent Results for Simulated, M easured, and Back Analysis o f Frequency
Tripler: Pin=6dBm
D escription
P a ram eter
Sim ulated
M easu red
B a c k Analysis
D ifference
IM eas-Backj
Maximum Sfo
C o n v e rsio n Gain
F re q u en cy of Maximum
Sfo C onversion Gain
Fractional Bandwidth
Fundam ental F requ en cy
R ejection at fo^^^
C G 3jdB )
2.9
3 .1 7
2 .6 6
0.51
fo^^^ (GHz)
2 .9 8
2 .9 4
2 .9 4
0
F B W (%)
8 .7 5
9 .5 9
1 1 .0 3
1.4 4
CG^^(dB)
-2 8 .2
- 2 5 .5
-20.1
5.4
C G ,J d B )
- 2 6 .5
- 2 3 .7
- 1 9 .5
4.2
S e c o n d Harmonic
Rejection
a t f o m ax
••
C:\R esearch\l_B_l UndrstndngN L Mech\C Practical Designs\test_multiplier_result_summary_l l_06_03.sxc
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407
Referring to Table 4.10 and Figure 4.20, the measured Sfo CG was slightly higher
than expected from simulation, reaching a maximum o f 3.17 dB at a frequency o f 2.94
GHz (fOmax=2.94). Table 4.10 also shows that the back analysis gave a 2.66 dB
maximum Sfo CG at an input frequency o f 2.94 GHz. There was only a 0.51 dB
difference in the value o f the maximum Sfo CG between the measurement and the back
analysis. The frequencies at which the maxima occurred (fomax) were in exact agreement
between the measured response and the back analysis. The fractional bandwidth o f the
measured doubler was 9.59%, which was only 1.4% smaller than the 11.03% fractional
bandwidth predicted by the back analysis. The measured response had more harmonic
rejection (-25.5 dB at fo and -23.7 dB at Sfo) than predicted by the back analysis (-20.1
dB at fo and -19.5 dB at Sfo).
Overall, as Figure 4.20 shows, the simulated (back-analysis) and measured tripler
responses are in close agreement. In Section 4.i, it was shown that the generalized model
presented in Chapter 2 is very accurate in predicting the response in a frequency doubler
design. The close agreement between the measured response and the back analysis
shows that the device model provides great accuracy in tripler design as well. The large
conversion gain exhibited by the doubler shows that the idealized multiplier
configuration presented in Chapter S (Idealized Design S, Case AI: in Section S.iv.c.S,
page 355) can also be utilized to create practical designs.
In conducting the measured sweep o f the tripler, an input power o f 4dBm was shown
to exhibit a slightly larger Sfo CG than for the 6dBm input power. The Sfo CG response
versus fundamental frequency for a 4dBm input power is shown in Figure 4.21 below.
The figure includes the initial simulation, the measured response and the back analysis.
R e p r o d u c e d with p e r m is s io n of t h e cop y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e r m is s io n .
408
-10
- 1 5
V
-10
^ -2 0
m
•o
CO
CM
@
- 3 0
-10
— Sim
— Meas
Back
- 4 0
^0
- 4 5
Freq (GHz)
Freq (GHz)
Freq (GHz)
Figure 4.21. Conversion Gain Response o f Practical Frequency Tripler at Pin=4dBm
C:\R esearch\l_B_l UndrstndngNL Mech\C Practical Designs\jjsimpletriplerl_b_writeup_10_21_03\
jjsimpletriplerl_b_CG_vs_freq_sim_meas_back_pin_4dbm_n_07_03.fig
The pertinent results shown in Figure 4.21 are summarized in Table 4.11.
Table 4.11. Sum mary o f Pertinent Resnlts for Simnlated, Measured, and Back Analysis o f Frequency
Tripler: Pin=4dBm
D escrip tion
Maximum Sfo
C o n v e r s io n Gain
F r e q u e n c y of Maximum
Sfo C o n v e rsio n Gain
Fractional Bandwidth
F un dam ental F r e q u e n c y
R ejection atfo^^^
S e c o n d Harmonic
R ejection at fo^^^
Param eter
Sim u lated
M e a su re d
B a c k A nalysis
D iffe re n c e
IM eas-B ackj
CGatc (dB)
2.19
3.67
1 .1 7
2 .5
fo^^^ (GHz)
S .0 4
2 .9 4
2.98
0.04
F B W (%)
8.11
8 .1 6
1 2.5
4.S 4
C G ,,(clB )
- 2 0 .5
- 2 S .1 7
-2 8 .1 4
4 .97
C G ,,,(d B )
- 2 1 .4
-2S.5
-2 0 .1
S.4
C:\R esearch\t_B_l UndrstndngN L Mech\C Practical Designs\test_multiplier_result_summary_l l_06_03.sxc
Referring to Table 4.11 and Figure 4.21, the measured response and simulated back
analysis are again in very close agreement. Here, the maximum measured 3fo CG
reaches up to 3.67 dB at a fundamental frequency o f 2.94 GHz. In perusal o f available
R e p r o d u c e d with p e r m i s s io n o f t h e cop y rig h t o w n e r. F u r th e r re p ro d u c tio n p rohib ited w itho ut p e r m is s io n .
409
literature, this amount o f Sfo CG is the largest ever reported fo r a practical frequency
tripler.
R e p ro d u c e d with permission of the copyright owner. Further reproduction prohibited without perm ission.
410
Chapter 5.
Conclusion
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411
This work has presented a comprehensive theory for the fundamental design o f
frequency multipliers. In Chapter 2, a generalized modeling technique was presented. The
technique was utilized to create a PHEMT model with the ability to predict the measured
large single response over large variations in fundamental frequency, bias, and input
power.
In Chapter 3 the full model o f Chapter 2 was simplified. This simplified, idealized
model was utilized in a concise study o f fundamental principles o f harmonic generation.
Effects o f variation in the AC input single level, gate and drain bias point, input network
configuration, and output network configuration on the output power and conversion gain
were studied. From this study, conditions on the input and output o f the transistor giving
a maximum 2fo and 3fo conversion gain were identified. Chapter 3 also introduced a
novel design characterization, the multiplier power (MP). The MP was utilized in the
design o f frequency multipliers to give a large conversion gain response while ensuring
an adequate corresponding output power level.
Finally, Chapter 4 presented some practical multiplier designs which utilized design
principles in Chapter 3 with the realistic PHEMT model o f Chapter 2. Chapter 4 showed
the simulated and measured results o f a very large conversion gain frequency doubler and
frequency tripler. The agreement between the simulation and the measurement showed
the high level o f accuracy o f the realistic device model in a practical circuit design.
Additionally, this chapter presented a frequency tripler with an unprecedented 3.67 dB
conversion gain.
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412
Appendices
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413
Appendix A. Generalized Nonlinear FET/HEMT
Modeling Appendix Data
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414
Appendix A.I. Device Measurements on Improved System
A.i.a. DC Measurement Details
By applying the correction on the gate-source and drain-voltages described in Chapter
2, a measured dataset was obtained for the Ids current source as a function o f only the
internal voltages VgSint and Vdsjnt. The values for Rg, Rd, and Rg were taken to be the
values determined by the manufacturer [11] and the voltage combinations tested were
those in which the gate-source and gate-drain diodes did not conduct. This allowed the
correct measured result for the drain-source current to be calculated. Table A .l shows an
example o f applying this correction to measured data (note that this calculation shows a
correction for Rg, Rj and Rg only).
Table A .I. Internal vs. Term inal Voltages o f PHEM T Transistor
C o rre c tio n s in D ra ln -S o u rc e V oltage:
Vds,
Vgs, = -0.6
Vgs, = 4).4
Vds.n,
VdSir^
1
2
3
C o rre c tio n s in
%Diff
0.021
1 .0 0 0
0 .9 9 6
0 .0 3 8
1 .9 9 9
1.993
2 .9 9 8
0 .0 7 7
2 .9 9 0
G a te -S o u rc e V oltage:
Vds, = 0
Vgs,
-0 .6 0 0
-0 .4
-0 .2
-0 .4 0 0
-0 .2 0 0
%
D
\ff
0 .3 7 8
0 .3 3 3
0 .3 3 9
Vds, = 1
%Dlff
-0 .6
Vgs, = -0.2
0 .0 0 0
0.001
0 .0 0 4
Vds.r^
Vds.^
%Dlff
0 .9 8 7
1.9 8 3
2 .9 7 7
1.2 8 7
0 .8 5 2
0 .7 6 2
Vds, = 2
“/oDiff
-0 .6 0 0
-0 .4 0 2
-0 .2 0 6
Vgs, = 0.0
-0 .0 1 8
-0 4 6 8
-3 .0 8 0
%Diff
Vds, = 3
“/oDiff
-0 .6 0 0
-0 .4 0 3
-0 .2 0 8
2 .4 5 7
1 .4 4 8
1 .1 1 6
0 .9 7 6
1.971
2 .9 6 7
%Dlff
-0 .0 6 4
-0 .8 2 4
-4 .0 5 3
-0.601
-0 .4 0 5
-0.211
-0 .1 9 1
-1 .2 5 1
-5 .3 6 4
C:\Research\DC (old)\Measured data and Templates\IV_Donald_Uncorr vs Corr 5_17_02.sxc
As Table A .l shows, the parasitic resistances in some cases can cause significant
deviation, greater than 5%, between the applied terminal voltages and the actual internal
voltages applied to the transistor.
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415
A.i.b. Characterization of Dgs and Dad
'gd Diodes
Figure A .l shows the setup used to measure Dgs and Dgd using the HP4155.
Vd(
^biasT
^
V W ” "AAA/“
V g -w v ^ -V W
^d
^9
Vd = 0
^biasT
lds = 0
Vs,
Vs,
biasT
Vs = 0
Figure A .l. M easurem ent o f Dg* and Dgd Using a Sem iconductor Param eter A nalyzer
C:\Research\Figures\ 4155 Dgs Dgd Measurement Setup B.ai
The HP4155 can apply voltages at the gate (Vg 4 i 55 ), drain (Vd 4 i 5 5 ) and source
(VS4 1 5 5 ), and measure the resulting currents Id and Ig. Both Vd 4 i 5 s and VS4 1 5 5 are set
equal to zero volts. This causes the voltage across the drain-source current generator to
be very small (close to zero), which results in a very small current flow from drain to
source (close to zero).
Assuming Ids is zero, the current through, and the corresponding voltage across each
diode can be determined as shown in Equations ( A .l ) through ( A .4 );
Ij,
= - I d
gd
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
( A .1 )
416
( A .2 )
h
gs
= l g
+
I d
V g d -m , = F g4i55 - I g [ R g +
) + / J (i? ^ +
V g S ; ,, = Fg4i55 - I g [2 R ,^ ^ ^ J + R g + R ^ ) - I d
)
( A .3 )
+ R^)
( A .4 )
Thus if the values o f the gate parasitics (Rg, Rd and Rs) and the extra resistance in the
measurement setup Rbiasi (due to external cabling and the use o f a bias-T) are known,
then the IV characteristics o f the Dgs and Dgd diodes can be extracted. Goolio [64]
mentions a similar technique to characterize the response o f the diodes.
Figure A .2 shows the IV response o f Dgd in the forward conduction region and Figure
A.3 shows the IV response o f Dgd in the reverse-breakdown region.
0 .0 1
<
0 .0 0 8
x tr 3 6 a -1
x tr 3 6 a -2
0 .0 0 6
x tr 3 6 a -3
x tr 3 6 a -4
x tr 3 6 a -a v g
0 .0 0 4
0 .0 0 2
0 .5
0 .6
0 .8
Figure A.2. Measured IV Response o f Dgd in Forward Conduction Region
C:\R esearch\l_B_l Undrstndng NL Mech\A ActI Dvce Charti Dvce Meas\DC\36163a xtr
8_21_02\Diode_M easurements\xtr36a_Dgd_measfwd.fig
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
0 .9
417
,x10
-4
□
-7 .6
xtr36a-1
xtr36a-2
xtr36a-3
xtr36a-4
xtr36a-avg
-7 .4
V gd ,^ ^ (V )
Figure A.3. Measured IV Response o f Dgd in Reverse Breakdown Region
C:\Research\l_B_l Undrstndng NL Mech\A Actl Dvce Char\i Dvce Meas\DC\36163a xtr
8_21_02\Diode_Measurements\xtr36a_Dgd_meas_rev.fig
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
418
A.i.c. S-Parameter Measurement Setup
Figure A .4 shows the setup for making S-Parameter measurements on the HP 8510
network analyzer. Note that both an 8510 B and 8510 C were utilized in the
measurement process.
S-Parameter Measurement Block Diagram
H P8510C
Vector Network
Analyzer
Fixture
Input
XTR
Fixture
Output
Figure A.4. S-Param eter M easurement Setup
C:\Research\Figures\SParamBlockDiagram.ai
Reproduced with permission o f the copyright owner. Further reproduction prohibited without permission.
419
A.i.d. Measured S-Parameter Data
mag(S11)
mag(S21)
■ xtr36a-1
■ xtr36a-2
■■ xtr36a-3
■ xtr36a-4
0.8
0.6
0.5
0.8
0.6
0.4
0.4
0.2
mag(S22)
0.2
25
phase(S21)
phase(S11)
phase(S22)
200
200
200
100
100
100
-100
-100
-100
-200
-200
-200
Freq (GHz)
Freq (GHz)
Freq (GHz)
Figure A.5. S-Param eter M easurement Results for VGO = -0.6V, Vdd = 2.5V
C :\R esearch\l_B_l Undrstndng NL Mech\A Actl Dvce Char\i Dvce Meas\S_Parameters\Wan 8_20_02 Xtr36a
Meas\xtr36a_Vgo_m0_6_Vdd_2_5_noS12_noavg.fig
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
420
mag(S22)
mag(S21)
mag(S11)
0.8
4
1.4
1.2
xtr36a-1
xtr36a-2
xtr36a-3
xtr36a-4
3
0.6
2
0 .4
1
0.2
0.8
0.6
0
0 .4
p h a s e (S 2 2 )
p h a s e (S 21 )
p h a s e ( S II)
200
200
200
100
100
100
0
-100
-
I- h -
-200
-100
-100
-200
-200
Freq (GHz)
Freq (G Hz)
F req (G H z)
Figure A.6. S-Param eter M easurement Results for VGO = -0.4V , V dd = 2.5V
C :\R esearch\l_B _l Undrstndng NL MechVA Actl Dvce Char\i Dvce M eas\S_Paraineters\W an 8_20_02 Xtr36a
Meas\xtr36a_Vgo_m0_4_Vdd_2_5_noS12_noavg.fig
m a g ( S II )
m a g (S 2 2 )
m a g (S 2 1 )
0.8
1
0.8
-
0.6
xtr36a-1
xtr36a-2
xtr36a-3
xtr36a-4
" rj:
0.6
0 .4
0.2
0 .4
5
10
15
20
5
25
10
15
20
p h a s e (S 2 2 )
p h a s e (S 2 1 )
p h a s e ( S II)
200
200
200
100
100
100
-100
-100
-100
-200
-200
-200
Freq (G Hz)
Freq (G Hz)
Freq (G Hz)
Figure A .7. S-Param eter M easurement Results for VGO = -0.2V, Vdd = 2.5V
C :\R esearch\l_B _l Undrstndng NL Mech\A Actl Dvce Char\i D vce M eas\S_Parameters\W an 8_20_02 Xtr36a
Meas\xtr36a_Vgo_m0_2_Vdd_2_5_noS12_noavg.fig
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421
mag(S11)
mag(S22)
mag(S21)
0.8
6
0.8
4
0.6
2
0.4
0
- xtr36a-1
- xtr36a-2
" xtr36a-3
■ xtr36a-4
0.6
0.4
0.2
phase(S22)
phase(S21)
phase(S11)
200
200
200
100
100
100
-100
-100
-100
-200
-200
25
Freq (GHz)
-200
Freq (GHz)
Freq (GHz)
Figure A.8. S-Param eter M easurement Results for VGO = OV, Vdd = 2.5V
C ;\R esearch\l_B _I Undrstndng NL Mech\A Actl Dvce Char\i Dvce Meas\S_Parameters\W an 8_20_02 X tr36a
Meas\xtr36a_Vgo_p0_0_Vdd_2_5_noS12_noavg.fig
mag(S22)
mag(S21)
mag(SII)
0.8
—
—
0.8
—
xtr36a-1
xtr36a-2
xtr36a-3
xtr36a-4
0.6
0.6
0.4
0.2
0.4
5
10 15 20
25
phase(S22)
phase(S21)
phase(SII)
200
200
200
100
100
100
0
-100
-100
-100
-200
-200
-200
Freq (GHz)
Freq (GHz)
5
10 15 20
Freq (GHz)
Figure A.9. S-Param eter M easurem ent R esults for VGO = 0.2V, V dd = 2.5V
C :\R esearch\l_B _l Undrstndng NL MechVA Actl D vce CharVi Dvce MeasVS ParametersVWan 8_20_02 Xtr36a
MeasVxtrS 6a_V go_pO_2_V dd_2_5_noS 12_noavg.fig
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25
422
mag(S22)
mag(S21)
mag(S11)
0.9
5
0.8
4
0 .7
3
0.6
2
0 .5
1
0 .4
0
0.8
xtr36a-1
xtr36a-2
xtr36a-3
xtr36a-4
0.6
0 .4
0.2
p h a s e (S 2 2 )
p h a s e (S 21 )
p h a s e (S 11 )
200
200
100
100
-100
-100
-100
-200
-200
200
100
r-
Freq (GHz)
25
Freq (G Hz)
-200
Freq (G H z)
Figure A.IO. S-Param eter M easurement Results for VGO = 0.4V, Vdd = 2.5V
C :\R esearch\l_B _l Undrstndng NL Mech\A Actl Dvce Char\i Dvce M eas\S_Parameters\W an 8_20_02 Xtr36a
Meas\xtr36a_Vgo_p0_4_Vdd_2_5_noS12_noavg.fig
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423
A.i.e. MATLAB Program to Average S-Parameter Data
C :\R esearch \m atlab files\s2p _averager.m
®/os2p_averager.m Last Revision 9/3/2002 Jessi Johnson
%Program to take the average o f s-parameter files
“/otnakes special adjustment for the phase data
clear;
clf;
axis on;
datal_styl =
data2_styl = '
data3_styl =
data4_styl = 'y';
dataavg_styl = 'b';
datasets = 4; %Number o f Datasets
%Matlab program to average two (or more?) input datasets and spit out
%the average o f all points
%function s2p_no_phaseshifl takes the +-180 phase shifts out o f the data
load xtr36a_I_Vgo_mO_6_Vdd_2_5.s2p;
setl = s2p_no_phaseshift(xtr36a_l_Vgo_m0_6_Vdd_2_5);
loadxtr36a_2_Vgo_m0_6_Vdd_2_5.s2p;
set2 = s2p_no_phaseshift(xtr36a_2_Vgo_mO_6_Vdd_2_5);
load xtr36a_3_Vgo_m0_6_Vdd_2_5.s2p;
set3 = s2p_no_phaseshift(xtr36a_3 _Vgo_mO_6_Vdd_2_5);
load xtr3 6a_4_V go_mO_6_V dd_2_5.s2p;
set4 = s2p_no_phaseshift(xtr36a_4_Vgo_m0_6_Vdd_2_5);
%Needed variables
Ix = length(setl(:,l));
numcols = length(setl(l,:));
if length(setl) ~ length(set2)
'warning!! datasets are o f unequal length'
end
‘lt)for loop loops through all o f the dataset values and averages them
%for j = 1:4;
“/oloop once for each s-parameter
«/oforr=l:lx
% if (set2(r, l+2*j) - setl (r, l+2*j)) >= 200
%
set2(r,l+2'*j) = set2(r,l+2'^j) - 360;
% end
% if (set3(r,l+2*j) - setl(r,l+2*j)) >= 200
%
set3(r,l+2*j) = set3(r,l+2*j) - 360;
% end
% if (set4(r,l+2*j) - setl(r,l+2*j)) >= 200
%
set4(r,l+2*j) = set4(r,l+2*j) - 360;
% end
%end
%end
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424
%for loop loops through all o f the dataset values and averages them
for j = 1:4;
%loop once for each s-parameter
fo rr= l:lx
if (set2(r,l+2*j) - setl(r,l+2*j)) <= -200
set2(r,l+2*j) = set2(r,l+2*j) + 360;
end
if (set3(r,l+2*j) - setl(r,l+2*j)) <= -200
set3(r,l+2*j) = set3(r,l+2*j) + 360;
end
if (set4(r,l+2*j) - setl(r,l+2*j)) <= -200
set4(r,l+2*j) = set4(r,l+2*j) + 360;
end
end
end
avgset = (setl + set2 + set3 + set4)/datasets;
%Plot phases
subplot(2,4,5)
hold on
plot(setl(:,l),setl(;,3),datal_styl);
hold on
plot(set2(;,l),set2(:,3),data2_styl);
hold on
plot(set3(:,l),set3(:,3),data3_styl);
hold on
plot(set4(:,l),set4(;,3),data4_styl);
hold on
plot(avgset(:,l),avgset(:,3),dataavg_styl);
title('phase(Sll)'), axis tight, grid on
subplot(2,4,6)
hold on
plot(setl(:,l),setl(:,5),datal_styl);
hold on
plot(set2(:,l),set2(:,5),data2_styl);
hold on
plot(set3(:,l),set3(:,5),data3_styl);
hold on
plot(set4(:,l),set4(:,5),data4_styl);
hold on
plot(avgset(:,l),avgset(:,5),dataavg_styl);
title('phase(S21)'), axis tight, grid on
subplot(2,4,7)
hold on
plot(setl(:,l),setl(;,7),datal_styl);
hold on
plot(set2(:,l),set2(:,7),data2_styl);
hold on
plot(set3(;,l),set3(:,7),data3_styl);
hold on
plot(set4(:,l),set4(:,7),data4_styl);
hold on
plot(avgset(;,l),avgset(:,7),dataavg_styl);
title('phase(S12)'), axis tight, grid on
subplot(2,4,8)
hold on
plot(setl (;, l),setl (:,9),datal_styl);
hold on
plot(set2(:,l),set2(:,9),data2_styl);
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425
hold on
plot(set3(:,l),set3(:,9),data3_styl);
hold on
plot(set4(;, I),set4(:,9),data4_sty 1);
hold on
plot(avgset(:,l),avgset(:,9),dataavg_styl);
title('phase(S22)'), axis tight, grid on
%Plot Magnitudes
subplot(2,4,l)
hold on
plot(setl(:,l),setl(:,2),datal_styl);
hold on
plot(set2(:,l),set2(:,2),data2_styl);
hold on
plot(set3 (:, 1), set3 (: ,2),data3_sty 1);
hold on
plot(set4(:,l),set4(:,2),data4_styl);
hold on
plot(avgset(:,l),avgset(:,2),dataavg_styl);
title('mag(Sl 1)'), axis tight, grid on
subplot(2,4,2)
hold on
plot(setl(:,l),setl(;,4),datal_styl);
hold on
plot(set2(:,l),set2(:,4),data2_styl);
hold on
plot(set3(:,l),set3(:,4),data3_styl);
hold on
plot(set4(:,l),set4(:,4),data4_styl);
hold on
plot(avgset(:,l),avgset(;,4),dataavg_styl);
title('mag(S21)'), axis tight, grid on
subplot(2,4,3)
hold on
plot(setl(;,l),setl(:,6),datal_styl);
hold on
plot(set2(:, 1),set2(:,6),data2_sty 1);
hold on
plot(set3 (:, 1), set3 (: ,6),data3_sty 1);
hold on
plot(set4(;,l),set4(:,6),data4_styl);
hold on
plot(avgset(:,l),avgset(:,6),dataavg_styl);
title('mag(S12y), axis tight, grid on
subplot(2,4,4)
hold on
plot(setl(:,l),setl(:,8),datal_styl);
hold on
plot(set2(;,l),set2(:,8),data2_styl);
hold on
plot(set3(:,l),set3(:,8),data3_styl);
hold on
plot(set4(:,l),set4(:,8),data4_styl);
hold on
plot(avgset(:,l),avgset(:,8),dataavg_styl);
title('mag(S22)'), axis tight, grid on
%function s2p_phaseshift puts the +-180 phase shifts back into the data
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
426
avgset = s2p_phaseshift(avgset);
%Plot phases
%subplot(2,4,5)
%hold on
%plot(avgset(;,l),avgset(:,3),':');
%title('phase(S 11)')
%subplot(2,4,6)
%bold on
%plot(avgset(:,l),avgset(:,5),':');
%title('pbase(S21)’)
%subplot(2,4,7)
%bold on
%plot(avgset(:,l),avgset(:,7),':');
%title('pbase(S 12)')
%subpIot(2,4,8)
%bold on
%plot(avgset(:,l),avgset(;,9),':');
%title('pbase(S22)')
legend('xtr36a-r, 'xtr36a-2','xtr36a-3','xtr36a-4','xtr36a-avg')
save xtr36a_avg_Vgo_m0_6_Vdd_2_5.s2p avgset /ascii
function[spout] = s2p_no_phaseshift(spfile)
%This function takes the -180 to +180 degree phase shifts out o f an s2p file
"/oUseage: s2p_no_phaseshift(spfile)
%spfile = a standard 2-port sparameter file
%s2p_no_phaseshift.m Last Revision 9/3/2002 Jessi Johnson
%Needed variables
Ix = Iength(spfile(:,l));
maxphsshfts = zeros(4,l);
%Number o f frequency points in s2p file
%Array to input number o f phase shifts in s2p phase data
%Loop to calculate the number o f phaseshifts from -180 to +180 for all four s-params
for j = 1:4;
%loop once for each s-parameter
for k = l;(lx -l);
%loop through each frequency
ifabs(spfile(k,l+2*j) - spfile(k+l,l+2*j)) >= 200
maxphsshfts(j) = maxphsshfts(j) + I;
end
end
end
%Loop to remove the -180 to +180 degree phaseshifts
for j = 1:4;
%loop once for each s-parameter
for k = l:(lx -l);
%loop through each freq
for 1 = 1:maxphsshfts(j);
%perform correction for each phaseshift in dataset
if abs(spfile(k,l+2*j) - spfile(k+l,l+2*j)) >= 200
spfile(k+l,l+2*j) = spfile(k+l,l+2*j) - 360;
end
end
end
end
spout = spfile;
function [spout] = s2p_phaseshift(spfile)
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427
%This function puts the -180 to +180 degree phase shifts into an s2p file
%Useage: s2p_phaseshift(spfile)
%spfile = a standard 2-port sparameter file
%s2p_phaseshift.m Last Revision 9/3/2002 Jessi Johnson
%Needed variables
Ix = length(spfile(:,l));
maxps = zeros(4,l);
%Number o f frequency points in s2p file
%Array to input number o f phase shifts in s2p phase data
%Loop to calculate the number o f phaseshifts from -180 to +180 for all four s-params
for j = 1:4;
maxpsfj) = round((max(spfile(:,l+2*j))-min(spfile(:,l+2*j)))/360);
end
%Loop to introduce the -180 to +180 degree phaseshifts
for j = 1:4;
%loop once for each sparameter
for 1= l:maxps(j)
%perform correction for each phaseshift in dataset
for k = 1:(lx);
%loop through each frequency
ifspfile(k,l+ 2*j)< -180
spfile(k,l+2*j) = spfile(k,l+2*j) + 360;
end
end
end
end
spout = spfile;
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428
A.i.f. Large-Signal Measurements
Figure A .l l . Im age o f Large-Signal M easurement System
C:\Research\lab_pics\ls_meas_setup 1jp g
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429
—
*
♦
xtr36a-2
xtr36a-3
xtr36a-5
xtr36a-6
-10
73
S--10
CO
-20
-25
-lOit
-25,
-15
-30
-20,
-35,
-30
-40,
-10
-10
Pin (dBm)
-10
Pin (dBm)
Pin (dBm)
Figure A .l l . Pin vs. Pout Measurements for VGO—0.6V, Vdd=2.5V, fo=3G Hz
C:\R esearch\I_B_l UndrstndngNL Mech\A Actl Dvce Char\i Dvce Meas\Power\Pwr meas xtr36a
Il_23_02\xtr36a_comp_vgo_m0_6_vdd_2_5_fo_3G_noAVG_ll_24_02.fig
-10
X
-10
-15
♦
xtr36a-2
xtr36a-3
xtr36a-5
xtr36a-6
-15
-20
E-20
^ -2 5
CO
-30
-30
-35
-35
-40
-15,
-10
-45,
- 45,
-10
Pin (dBm)
-10
Pin (dBm)
Pin (dBm)
Figure A.13. Pin vs. P ref Measurements for VG0—0.6V, Vdd=2.5V , fo=3G Hz
C:\Research\l_B_l Undrstndng NL Mech\A Actl Dvce Char\i Dvce Meas\Power\Pwr meas xtr36a
ll_23_02\xtr36a_Pref_comp_vgo_m0_6_vdd_2_5_fo_3G_noAVG_ll_24_02.fig
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
430
-20
-25
«
-30
♦
xtr36a-2
xtr36a-3
xtr36a-5
xtr36a-6
-35
X/j
CQ-40
'S-IO
CN
-15
1 -50
0.
-55
-20'
-60
-10
-25
-65
-15
-70,
-30*Pin (dBm)
Pin (dBm)
Pin (dBm)
Figure A.14. Pin vs. Pout M easurements for VG0—0.6V, Vdd=2.5V, fo=6G Hz
C:\Research\l_B_l UndrstndngNL Mech\A Actl Dvce Char\i Dvce Meas\Power\Pvvr meas xtr36a
1 l_23_02\xtr36a_comp_vgo_m0_6_vdd_2_5_fo_6G_no AV G_ 11_24_02 .fig
-40
—
X
-45
*
-10
xtr36a-2
xtr36a-3
xtr36a-5
xtr36a-6
-50
E -1 5
•o
■D
-25
X.',
-60
.X X
r
-30H?
-10
-12
-14
-40
Pin (dBm)
-70,
Pin (dBm)
Pin (dBm)
Figure A.15. Pin vs. P ref M easurements for VG0—0.6V, Vdd=2.5V , fo=6G Hz
File: C:\Research\l_B_l Undrstndng NL Mech\A Actl Dvce Char\i Dvce Meas\Power\Pwr meas xtr36a
ll_23_02\xtr36a_Pref_comp_vgo_m0_6_vdd_2_5_fo_6G_noAVG_ll_24_02.fig
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
431
-25
-30
-35
-10
-40
m-15
T3
5 -2 5
-55
-30
—
X
-60
-35
♦
-65
-45
Pin (dBm)
xtr36a-2
xtr36a-3
xtr36a-5
xtr36a-6
-70.
Pin (dBm)
Pin (dBm)
Figure A.16. Pin vs. Pout M easurements for VG0=0.1V, Vdd=2.5V , fo=6GHz
File; C:\Research\l_B_l Undrstndng NL Mech\A Actl Dvce Char\i Dvce Meas\Power\Pwr meas xtr36a
I l_23_02\xtr36a_comp_vgo_p0_l_vdd_2_5_fo_6G_noAVG_l l_24_02.fig
-45
—
X
.y*'
-50
-10
♦
xtr36a-2
xtr36a-3
xtr36a-5
xtr36a-6
-15
CO
--X
-12
aj -60
-14
-30
-16
-35
-20.
-10
10
Pin (dBm)
-45.
-70.
-10
-10
Pin (dBm)
Pin (dBm)
Figure A.17. Pin vs. Pref Measurements for VG0=0.1V, Vdd=2.5V , fo=6G Hz
File: C:\Research\l_B_l Undrstndng NL Mech\A Actl Dvce Char\i Dvce Meas\Power\Pwr meas xtr36a
1 l_23_02\xtr36a_Pref_comp_vgo_p0_l_vdd_2_5_fo_6G_noAVG_ll_24_02.fig
Reproduced with permission o f the copyright owner. Further reproduction prohibited without permission.
432
18
I
10
1
1
ai
5
16
0
14
-5
j
------------
E12
ca
T)
-------
'-10
MO
------m-20
o
55-25
------------
i)-15 —
------
-------
o
---------- - E -------- 1-----------J:
1
Q.
r
^
r
'
------------
X
r
♦
¥
11/
1
1
/ — H— 1—
1
1
Jt
-10
1
1
-5
0
5
10
-35
-10
-5
0
5
-50
10
-10
-5
0
5
Pin (dBm)
Pin (dBm)
Pin (dBm)
xtr36a-2
xtr36a-3
xtr36a-5
xtr36a-6
Figure A.18. Pin vs. Pout M easurem ents for VG0=0.4V, Vdd=2.5V , fo=3GHz
File: C:\R esearch\l_B_l Undrstndng NL Mech\A Actl Dvce Char\i Dvce Meas\Power\Pwr meas xtr36a
1 l_23_02\xtr36a_comp_vgo_p0_4_vdd_2_5_fo_3G_noAVG_l l_24_02.fig
-15
-20
-10
-25
m -1 5
CQ ^
T3
^ -2 0
-35
-30
—
a
-35
♦
-10
-12.
-10
10
Pin (dBm)
xtr36a-2
xtr36a-3
xtr36a-5
xtr36a-6
-45^
-10
-45,
-10
Pin (dBm)
Pin (dBm)
Figure A.19. Pin vs. P ref Measurements for VG0=0.4V, Vdd=2.5V , fo=3G Hz
File: C:\Research\l_B_l Undrstndng NL Mech\A Actl Dvce Char\i Dvce Meas\Power\Pwr meas xtr36a
ll_23_02\xtr36a_Pref_comp_vgo_p0_4_vdd_2_5_fo_3G_noAVG_ll_24_02.fig
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
433
-35
-40
-45
E -5 0
0-60
xtrS6a-2
xtr36a-3
xtr36a-5
xtr36a-6
X
-20
♦
-25
-30
-70
-35
-75,
Pin (dBm)
Pin (dBm)
X
Pin (dBm)
Figure A.20. Pin vs. Pout M easurements for VG0=0.4V, Vdd=2.5V, fo=6G Hz
File: C:\Research\l_B_I Undrstndng NL Mech\A Actl Dvce Char\i Dvce Meas\Power\Pwr meas xtr36a
1 l_23_02\xtr36a_comp_vgo_p0_4_vdd_2_5_fo_6G_noAVG_l l_24_02.fig
-45
-50
-10
-15
T3
B -20
^5 -10
-12
-X - -
-55
-25
■g-eo
-14
-30
-16
-35 -
-18’
-40
-20,
-45,
—
X
-65
♦
Pin (dBm)
xtr36a-2
xtr36a-3
xtr36a-5
xtr36a-6
-70,
Pin (dBm)
10
Pin (dBm)
Figure A.21. Pin vs. P ref Measurements for VG0=0.4V, Vdd=2.5V, fo=6G Hz
File: C:\Research\l_B_l Undrstndng NL Mech\A Actl Dvce Char\i Dvce Meas\Power\Pwr meas xtr36a
11_23_02\xtr36a_Pref_comp_vgo_p0_4_vdd_2_5_fo_6G_no A V G_ 11_24_02 .fig
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
434
Appendix A.ii. Generalized Modeling Based on Measured
Results
A.ii.a. ADS Schematic (SDD) of Generalized Device Model
C=Cpgd
R =R d
N um =
C=Cpg
C=Cpg1
N um =2
C=( ;ds
so m p
SDD4P1
l[1,0]=lgs
l[1.1]=Qg
l[2,0]=lds
l[3,0]=lgd
l[3,1]=Qgd
l[4,0]=ldsrf
em
R=Rc
C=Cpd1
C=Crf;
R=Rs
L= L S
Num=3
[^ V A R
Dgd_Parameters
DgdN=1.93504
DgdNr=26.1951
Dgdisat=5.31842e-010
Dgdvt=0.026
Dgdvbr=3.51502
Dgdre=426.299
I VAR
Dgs_Parameters
DgsN=1.9
DgsNr=13.1948
Dgsisat=.5e-010
Dgsvt=0.026
Dgsvbr=1
Dgsre=6868.04
e g VAR
Capacitor_Equations
Qgs=cgsp*Vgsi+cgso*(Vgsi+Lc1 +Vgsi*Th2+Lc1 *Th2)
Qgd=cgdp*Vgdi+cgdo*(Vgdi+Lc4+Vgdi*Th3+Lc4*Th3)
Lc1 =log(cosh(P10+P11*Vgsi))/P11
Lc4=log(cosh(P40+P41*Vgdi))/P41
Th2=tanh(P20+P21 *Vdsi)
Th3=tanh(P30+P31*Vdsi)
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
435
Dgs_Equations
lgs=ifV gsi> -10*DgsN*Dgsvtthenlgsonelselgsaendif
lgsa=if Vgsi > -Dgsvbr + 50*Dgs\<then Igsoffelselgsrbdenclif
lgsoncurr=Dgsisat*(exp{Vgsi/(DgsN*Dgs\<))-1)
lgson=if Igsoncurr < .1 then Igsoncurr else ,1 endif
lgsoff=Dgslsat*(exp(-10.0)-1)+Dgsggs*(Vgsl-10*DgsN*Dgs\^)
Dgsggs=Dgsisat*((e)qD(-10))/{DgsN*Dgsvt))
lgsrbclcurr=-Dgsisat*Dgsre*e)(p{-(Dgsvbr+Vgsi)/(DgsNr*Dgs\*))+Dgsisat*(e)ip(-10)-1)+Dgsggs*{Vgsi-10*DgsN*Dgs\<)
lgsrbd=if Igsrbdcurr > -.1 then Igsrtidcurr else-.1 endif
Dgd_Equatlons
lgd=ifVgdi > -10*DgdN*Dgd\< then Igdon else Igdaendif
igda=if Vgdi > -Dgd\fcr + 50*DgcMthen igdoff else igdrbd endif
lgdoncurr=Dgdisat*(exp(Vgdi/(DgdN*Dgclvt))-1)
igdon=if igdoncurr < .1 then igdoncurr else .1 endif
lgdoff=Dgdisat*(exp(-10.0)-1)+Dgdggs*(Vgdi-10*DgdN*Dgdvt)
Dgdggs=Dgdisat*((e)ip{-10))/(DgdN*Dgdvt))
igdrtxicurr=-Dgdisat*Dgdre*exp{-(Dgd\tor+Vgdi)/(DgdNr*Dgdvt))+Dgdisat*{exp(-10)-1)+Dgdggs*(Vgdi-10*DgdN*Dgd\*)
igdrbd=if igdrbdcurr > -.1 then igdrtxJcurr e ls e -.1 endif
1 3 VAR
DC_Parameters
lpk=0.05
apsi=file{DAC1, "apsi"}
alambda=file{DAC2, "alambda"}
alpha=file{DAC3, "alpha"}
1 3 VAR
DrainSource_Current_Equation
lds=lpk*(1+tanh(apsi))*(exp(alambda*Vdsi))*(tanh(alpha*Vdsi))
1 3 VAR
VAR2
Rc=file{DAC4, "Rc"}
Crf2=10e-3F
Cpgd=flie{DAC4, "Cpgd"}
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
436
VAR
Parasitic_Elements1
Rd=0.5 Ohm
Rg=1 Ohm
Rs=0.5 Ohm
Ri=10hm
Gpg=file{DAC4, "Cpg"}
Cpg1=file{DAC4, "Cpg1"}
Gpd=file{DAG4, "Gpd"}
Gpd1=file{DAG4, "Gpdl"}
Lg=file{DAG4, "Lg"}
Ls=file{DAG4, "Ls"}
Ld=file{DAG4, "Ld"}
IVAR
Displacement_Parameters1
Grf=10e-3 F
Rcw=file{DAG4, "Rcw"}
I VAR
Gapacitor_Parameters2
cgso=file{DAG4, "cgso"}
cgsp=file{DAG4, "cgsp"}
cgdo=file{DAG4, "cgdo"}
cgdp=file{DAG4, "cgdp"}
P10=file{DAG4, "P10"}
P11=file{DAG4, "P11"}
P20=file{DAG4, "P20"}
P21=file{DAG4, "P21"}
P30=fiie{DAG4, "P30"}
P31=file{DAG4, "P31"}
P40=file{DAG4, "P40"}
P41=file{DAG4, "P41"}
Gds=file{DAG4, "Gds"}
^SafaAccessComponent
DAC4
F ile="m od e l36 a J m p _ w P re fj3 S tc _ tb ljD 0 _1 _ 1 2 _ 8 _0 2 .m d f
Type=G eneralized Multi-dimensional Data
lnterpMode= Linear
lnterpDom=Rectangular
iVar1="RFfreq"
iVal1=RFfreq
StaA ccessC om ponent
DAC3
File="ctialm 99_DC_optnew _alpha_corr_10_15_02.m df'
Type=G eneralized Multi-dimensional Data
lnterpMode=Cubic
lnterpDom =Rectangular
iVar1="Vgsi"
iVal1=Vgsi
iVar2="Vdsi"
iVal2=Vdsi
M a A c c e s s Com ponent
DAG 2
File="chalm 99_D C _optnew Jam bda_corr_10_15_02.m df''
DAC1
F ile="chalm 99_D G _optnew _psi_corr_10_15_02.m df’Type=Generalized Multl-dlmensional Data
Ty pe=Generalized Multi-dimensional D ata
lnterpMode=Cubic
InterpMode=Cubic
interpDom=Reotanguiar
interpDom =Rectanguiar
iVar1="Vgsi"
iVar1="Vdsi''
iVai1=Vgsi
iVai1=Vdsi
iVar2="Vdsi"
iVai2=Vdsi
jataA ccesrsC om ponent
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
437
VAR
Disp lacement_Eq u ations
ldsrf=(1 +tanh(apsi))*Vdsi/Rcw
I S VAR
Port_Voltage_Defin itions
Vgsi=_v1
Vdsi=_v2
Vgdi=_v3
File: C:\users\default\ads\optimizing_prj\networks\
model36a_chalm99_imp_optboth_wPref_fo_tbI_pO_l.dsn
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
438
A.ii.b. Response of Optimized Dgd Diode Model
0.01
-0 .2
0.0 0 9
xIO
-0.4
0.008
-0 .6
S-0.8
S 0.004
TO
-0 .0 0 3
-1.4
0.002
-1 .6
0.001
Measured
Modeled
0 .8
Figure A.22. Measured vs. Simulated DC IV Response o f the Gate-Drain D iode (Dgd)
C:\R esearch\l_B_l Undrstndng NL Mech\A Actl Dvce Char\ii Dvce Mod\DgsandDgdopt\xtr36a_DiodeOpt_8_21_02\
modeI36a_Dgd_final_sim_vs_meas_both_7_10_03.fig
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
439
A.ii.c. ADS Diode Optimization Schematics
Diode Ontimization Schematic
File: C :\users\default\ads\optimizing_prj\networks\dgsopt.dsn
Dc Sweep Settings
VAR
DC
DC1
SweepVar="vgs"
Start=vgsstart
Stop=vgsstop
Step=0.01
ConvMode=0
VAR1
vgs=-0.5
vgsstart=-8
vgsstop=2
Diode Model
f t
l_Probe
■’ V_DC
model36a_Dgs_diode
X1
Igssim
SRC2
Vdc=vgs V
Import M easured DC Data
SRC1
I ldc=flle{DAC1. "lgsm eas'}A
DataAccessComponent
DAC1
File= "C:\Research\1_B_1 Undrstndng NL Mech\A Actl Dvce Char\i Dvce M ea s\X \3 6 1 6 3 a xtr 8_21_02\DI{
Type=Generarized Multi-dBnenslonal Data
lnterpMode= Linear
InterpDom= Rectangular
iVar1=''vgsimeas"
iVal1=vgs
rfeijRe^\diode36a_avgLDg$_ci rr.m d f
Igsm
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
440
O p tim iz e r B o x e s
OPTIM
GOAL
GOAL
C^)ai
O p tin ft
/
I
0|3tim T ’^ e = G r a d ie n t U se A ll^ tV a rs= y e K
E r r o r F o m i^ 2
OptY^fl1J=
\
M a x lte r s = 1 0 \
U ^ A llG o a ls = y e s
P=2
\
I
D e s ir e d E r r o r = 0 .d \
*
S ta tu s L e v e l= 4
*
F in a tA n a !y s is = 'J ^ o n e \
»
S e tB e s tV a lu ^ = y e s
\
‘
S eed=
y
\
I
S av eS o lQ S = y es
j
S a v e G fy l!s= n o
\
»
S aveO ptim V ars= :yes
'
U p d a te D a ta s e t= y e s
\
\
S a v e N o m in a l= y e s
\
\
1
O p tiM p o a ll
/
Expr="6urTBnjerr"
«
S (m ln s ta i^ f e N a m e = 'D ( tl"
M n=0.1 / \
i
O ptim G oal2
E xpr= "currenterr'
S im ln s ta n c e N a m e -D C r'
Min=0.1
W e i# it= 1
\
R afig e V art1 ]= 'V g ^ \
X a n g e M n [1 ]= -3 .5 '
W eight= 1
R angeV ar[11='V gs’’
R angeM ln[1]= 0.65
R angeM a)<1]=0.82
IfejaEqn
...
Ma>?s0.1
M eas1
m e a sd c c u rre n t= D C .Ig s m .i
sim d c cu rren t= D C .Ig ssim .i
cuirenterTs(m easdccurrent-sim dccuiTent)/m easdccurrent
flS5J«AUJj®M.Qn.^=m................... y .
SDD o f Dgs Diode fmodel36a Dgs diode.dsn')
File: C:\users\default\ads\optimizing_prj\networks\model36a_Dgs_diode.dsn
T h is is th e ig s D io d e M od el for th e A T 3 6
s r o
Num=1
S
Num=2
SDD1P1
l[1,0]=lgs
C[1]=
E ]V A R
Diode_Equations
lgs=if Vgs > -10*N*vt then Igson else Igsa endif
lgsa=if Vgs > -vbr + SOM then Igsoff else Igsrbd endif
lgson=isat*(exp(Vgs/(NM))-1)
lgsoff=isat*(exp(-10.0)-1)+ggs*(Vgs-10*NM)
ggs=isat*((exp(-10))/(NM))
lgsrbd=-isat*re*exp(-(vbr+Vgs)/(NrM))+isat*(exp(-10)-1)+ggs*(Vgs-1C*NM)
VAR
VAR
Diode_Param eters
N=1.89969
Nr=13.1948
isat=5.020040-010
vt=0.026
vbr=1
re=6868.04
Port_Voltage_Definitions
Vgs=_v1
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
441
SDD o f Dgd Diode (model36a Dad diode.dsn)
File; C:\users\default\ads\optimizing_prj\networks\model36a_Dgd_diode.dsn
T h is is th e ig d D io d e M od el for th e A T 3 6
Nunn=1
SDD1P1
l[1,0]=lgd
C[1]=
D
Num=2
I VAR
Diode_Equations
lgd=if Vgd > -10*N*vt then Igdon else Igda endif
lgda=lf Vgd > -vbr + SOM then Igdoff else Igdrbd endif
lgdon=isat*(exp(Vgd/(NM))-1)
lgdoff=lsat*(exp(-10.0)-1)+ggs*(Vgd-10*NM)
ggs=isat*((exp(-10))/(NM))
lgdrbd=-isat*re*exp(-(vbr+Vgd)/(NrM))+isat*(exp(-10)-1)+ggs*(Vgd-10*NM)
VAR
VAR
D iode_P aram eters
N= 1 .9 3 5 0 4
Nr=26.1951
Port_V oltage_D ef Initi on s
Vgd=_v1
lsa t= 5 .3 1 8 4 2 e-0 1 0
vt= 0.026
vb r= 3.51502
re = 4 2 6 .2 9 9
Reproduced with permission o f the copyright owner. Further reproduction prohibited without permission.
442
A.ii.d. ADS Schematic of DC Optimization Scheme
Optimization Schematic
File: C:\users\default\ads\optimizing__prj\networks\DCoptimizer_chalm99.dsn
D c S w e e p S e ttin g s
O p tim iz e r S e ttin g s
§
IfSB I parameter SWEEP 1
0
P a ra m S w e e p
DC1
SweepVar=
Start=
Stop=
Step=
Pt=0
Convftibde^O
SWEEPPl^
S w e e p P ia n
VdsSweep
SweepVap"vds"
SimlnstariceNarne[1]-Vgsoptsweep"
SiminstanceName[2]=
SimlnstanceName[3]=
SimlnstanceName[4]=
SimlnstanceName[5J=
SimlnstanceName[6]=
Start=0,5
Stop=2
Step=0.1
Pt=
SwpPlanI
Start=0.1 Stop=l1 Step^.t Lin=
UseSweepPlan=yes
SweepPlan-'SwpPlan3"
'em^p p lan t
S w a e jM p n
SwpPlan2
Start=.6_^§j0|5=2''SteR=.1 Lin=
Us 5&ifeepPlan=yes
pcSfepPJaosSMjeiaQi"..''.SW EEP PLAN
SwpPlanS
Start=1.5 Stop=4.5 Step=,5 Lin=
UseSweepP!an=
SweepPlan=
Opt1
OptimType=Gradieiit
ErrorForm=L2
Wbxlters^lO
P=2
DesiredEnoi^O.O
StatusLevel=4
FinalAnalysis-None"
SetBestValues=yes
Seed=
Sa\eSolns=yes
SaveGoals=yes
SavBOptimVars=yes
UpdateDataset=no
SaveNominal=yes
Sa\eAlllterations=no
PARAMETER SWEEP
Ids G oals
‘aram Sw gep
Vgsoptsweep
GOAL
Goal
G o a IJ d s e rr
Expr="vdserr"
S im lnsta n c e N a m e -'D C 1 "
Min=0
Max=0
W elght=1
R ang eV ar[1]=
RangeM !n[1]=
I VAR
SweepVar="vgs2"
DCVars
vgs2=0
Slm lnstanceName[1 ]= " 0 p t1 "
Sim lnstanceNam e[2]=
vds=2
Sim lnstanceNam e[3]=
Sim lnstanceNam e[4]=
vgs2start=-0.6
vdsstart=2
vgs2stop=0,6
Sim lnstanceNam e[5]=
vdssfop=2
Start— 1
Stop=1
Slm lnstanceNam e[6]=
Step=0,1
RangeM ax[1]=
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
UseAIIOptVars=yes
UseAIIGoals=yes
443
Model Simulation
R3
R=RDbiasT Q
Si
Ri
y_DC R=RGbiasT Ohm
lr S R C 2
i_Probe
Idss
h
me id el3 6 a _ D C _ ch a lm 9 9 j bi^_i_DC
X2
Vdc=vgs2
■ is R c a
Vdc=vds
R2
R=RSbiasT Ohm
VAR
M e a s u r e m e n t E q u a tio n s
M easE q n
C u rren tD ata
R B ia sT
R G b ia s T = 0 .9
R S b ia s T = 0 .2
R D b ia s T = 1 .1
M e a sd c l= ld sm .i
S im d c l= ld ss .i
M easE q n
V dsE rr
v d s e r r = (M e a s d c l-S im d c l)/M e a s d c l
Import M e a su re d DC D ata
ataAccessComponent
DAG1
File="avglDS_08_22_2002.mdf
Type=Generalized Multi-dimensional Data
lnterpMode=Linear
lnterpDom=Rectangular
LOG
SRG1
ldc=file{DAC1, "lds_meas"}
p n LProbe
^
Idsm
iVar1="vgs2"
iVal1=\/gs2
iVar2="vds_meas"
iVal2=vds
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
444
Schematic of DC Model for Optimization
File: C:\users\default\ads\optim izing_prj\networks\m odel36a_DC_chalm 99_psitbl.dsn
m o a e l 36a _ D g d _ d io d e
X2
HV
NArR
■J—W r -
R
R2
G
RI
N um =1 R=Rg
R=Rd
I
D
N um =2
m o d e l 36a D gs d io d e SU U dP
X1
"
SD D 3P1
l[1,0]=0
l[2,0]= lds
l[3,0]=0
C[1]=
-RR6
R=R s
i
Port
S
N um =3
( S I VAR
(W |V A R
(w jV A R
P a ra sitic E le m e n ts
D rain S ource_C urrent_E quation
D C _ P a ra m e te rs
lds=lpk*(1+
tanh(apsi))*(exp(alam
bda*V
ds))*(tanh(alpha*V
ds))
R d= 0.5 O hm
lpk=0.05
Rg=1 O hm
apsi=fiie{D A C1, "apsi"}
[WJR®S5).5 Ohm
a ia m b d a= 0 .0 5 opt{ 0,01 to 1.2 }
P ort_V oitage_D ef initions
aip h a = 3 .5 opt{ .01 to 1 2 }
V g s= _ v 1
V d s= _ v 2
V gd=_v 3
Ja ta A c c e s sC o m poneiit
DAC1
F iie= "p sio p ttab le _ 9 _ ll_ 0 2 .m d f"
T ype= G eneralized M uiti-dim ensional D ata
interpM ode=C ubic Spline
I nte rp D o m = R e c tan g u la r
iV ar1="vgs2"
iV ai1=vgs2
R e p r o d u c e d with p e r m i s s io n o f t h e cop y rig h t o w n e r. F u r th e r re p ro d u c tio n p rohib ited w itho ut p e r m is s io n .
445
A .ii.e. A D S S c h em atic o f A C O p tim izatio n S chem e
File: C:\users\default\ads\optimizing_prj\networks\xtrACopt_Pinswp_dbm _wPref.dsn
S im u la te T ra n sisto r M odel
p g ] M ea sE q n
-FT'
M eas2
PfC
Pfc2
Psim fo=wtodbm(pfc(vdsout,0,ldsout.i,{1}))
spsim =S(5::6,5::6)
Psim 2fo=wtodbm (pfc(vdsout,0,ldsout.i,{2}))
Psim 3fo=wtodbm (pfc(vdsout,0,ldsout.i,{3}))
Prefsfo=w todbm (pfc(vgsref,0,lgsref.i,{1}))+cplng
Prefs2fo=wtodbm (pfc(vgsref,0,lgsref.i,{2}))+cping
Prefs3fo=w todbm (pfc(vgsref,0,lgsref.i,{3}))+cplng
R4
i t-TOl:
R =50O hm
ro o e
G o u p te r S in g
Id so u t
C 0U P1
C o u p lin g = o p in g dB
M V SW R 1=1
C V SW R 1=1.
P^ITofie
i-TODe
PO RTS
N um =5
F re q = R F fre q G H z
V dc=
L o ssl^ O . dB
4
f
R3
R=RddO hm
!erm
lle rm e
1 j N u m =6
» ■ Z =R I O hm
D lre c t1 = 1 0 0 d B
Z R e f= 5 0 . O h m
Z = R g O hm
P = d b m to w (R F p o w e r)
Im m
xk)!3t-)a c h a ln i9 9 im p odl:K)th 'A ^kef f
V DC
SRC1
V DC
pSRC 2
V dc=V dd V
V dc=V G O V
Read Measured Pin Pout Data
Jata A c c e ssC o m p o n e n t
DAC1
File="C:\Reseanch\1_B_1 U ndtstndng NL Mech\A Actl Dvce Char\i Dvce MeasVPowertPwr m e a s xtr36a 11_23_02\xtr36a_avg_sw eep_fnritd_11_23_0:
Type=G eneralized M ultl-dlmensional Data
lnterpM ode=Linear
lnterpD om =Rectangu|a lfe~ |
iVar1=’VG0"
PfC
iVal1=VG0
P fcl
iVat2="RFfreq''
Pm easfo=w todbm (pfc(vpoutm eas,0,l_Poutm eas.i,{1}))
IVal2=RFfreq
Piiefmfo=wtodbm(pfc(vprefmeas,0,l_Prefmeas,i,{1}))
iVar3="Pln"
Pmeas2fo=w todbm(pfc{vpoutmeas,0,l_Poutmeas.i,{2}))
IVal3=RFpower
PrBfm2fo=wtodbm(pfc(vprefmeas,0,l_Prefmeas.i,{2}))
P m e a s 3 f o = w to d b m ( p f c ( v p o u tm e a s ,0 ,l_ P o u tm e a s .i,{ 3 } ) )
Prefm3fo=wtodbm(pfc{vprefmeas,0,l_Prefmeas.i,{3}))
R e p r o d u c e d with p e r m is s io n of t h e cop y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e r m is s io n .
446
<0?
vpoutmeas
X I
ProBe
Pou tm eas
P_nHarm
P0RT1
Num=1
Z=50 Ohm
Freq=RFfreq GHz
”
P[1]=file{DAC1, "Pout1"}
P[2]=file{DAC1, "Pout2"}
P[3]=file{DAC1, "PoutS"}
T erm
Term2
Num=2
Z=50 Ohm
vprefmeas
f t
P__nHarm
rP r o b e
1 Pref m ea s
PORT?
Num=7
Z=50 Ohm
Freq=RFfreq GHz
P[1]=file{DAC1, "Pref1"}
P[2]=file{DAC1, "Pref2"}
P[3]=file{DAC1, "Pref3"}
T erm
Terms
Num=8
Z=50 Ohm
Read in M easured S-Param eter Data
Term
j g MeasEqn
T e rm 4
M eas1
T e rm S
Num =4
s p m e a s = S (3 ;;4 ,3 ::4 )
Num =3
Z = 5 0 Ohm
Z = 50O h tS N P 1
F ile = " C :\R e s e a r c h \1 _ B _ 1 U n d r s tn d n g N L M ec h \A A c 1 ) D v c e C h a r \i D v c e M e a s \S _ P a ra m e te i
R e p r o d u c e d with p e r m is s io n of t h e cop y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e r m is s io n .
447
Optimization Goals
S-Parameter Goals
J
\ magS245oai
1 E x p r= " m a ^ 2 1 _ e ir"
« S im l n s t a n c e ^ t e i m e f ^ P I "
I
M n=0
^
T Sai
)* \
\
fVbx=0
I
W e ig h t= ^ 2 'lm a g W F
I
R a n g ^ a r t1 ] = 'T r e q "
1 R ^ g e M n [ 1 ] = 2 ‘ R F fre q G H z
icfcuwJStoilJf3*BFteja.ette..
I
Goal
\
phsS H goal
\
E x p r= " p h s S 1 1 _ e rr"
S l m l n s t a n c e ^ ^ m e ^ 'S P I "
\
S im l n s t a n c e N a m e = " S P 1 "
I
M n =0
I
M n=0
\
I
!
Ma)FO
phsS 21goai
j
m a g s 't l ^ o a l
X
E x p r= " p h s S 2 1 _ e rr"
\
E x p r= ''m a g S 1 1 _ e rr "
S im (n s ta n c e N a m e = " S P 1 "
I
M n -0
l\/bx=0
/
W e ig h t= S 2 1 p h s W F
I
Max =0
W e ig h t= ^ 1 1 m a g W F
R an g eV ail1 ]= ''freq "
I
R a n g eV a[t1 ]= 'T re q '‘
|
R a n g e V a r[1 ]= ’Treq''
R a n g e M n [1 ]= s ta rtfre q
I
R a n g e M n [1 ]= 2 * R F fre q G H z
\
R a n g e M n [ 1 ]= s ta r tfre q
UisDflsteLUsSlBEtregJSdz___
R ange!V bx[1]= stopfreq
W G ig h t= S 1 1 p h s W F
R an g eM a x [1 ]= s to p fre q
A'k g
s g
Gi)ei
I E>9r="rT^S22_err V '
phsS 22goal
E > p r= " i:^ S 2 2 _ e rr"
Si ml nstanceN am e= "S P 1"
M in=0
Ma>FO
V\teight=S22phsV\F
R angeV ar[1]="freq"
R ang eM in[1 ]=startfreq
R angeM ^o^^]=stopfreq
I Sim lnstanceN^m p»^‘'S P1"
! M in=0
I M ax=0
I V\^ght7-3^magV\F
’» R arpeV ar(1]= "freq"
I R a h g e M iril]= s ta rtfre q
I'-'SsnasMatilJsJQBftM...
I
I B p -= " p h S § 1 2 _ e rr"
E )p r= " iT ^ S 1 2 _ e rr V '
» Simlnstar)ceNli§mpftf''SP1"
I
M in=0
I Ma>FO
/
S "
'x
I S im fn s ta n c e H ^ m ^ ‘'S P1"
I M in=0
* M ax=0
/*
I V\feightjS^12phs\AF
\ V\feight7-3''l2magV\F\
t
t R a r p ^ a r [ 1 ] = ''f r e q ”
5 R afigeM ir(1l= startfreq
R a rjg ^ a r[1 ]= " fre q "
I RafigeM ln[1]=start!Teq
S/.'saHsMatUrJJQBlea— >.4'i*3sMatU?^la#e9_
Output Power Goals
_
GOAL
GOAL
I Goal
j p o u tfo g o a l
! E x p r= "p & u tfo err" y '
1 Simlnstanc©^laJ3n'e="HB1"
: IWin=0
• M ax= 0
> V\feighJ?^’o u t_ fo V \/F x
• R a n ^ V a r[1 ]=
; R a’n g eM in [1 ]=
.......
Ut^naeM32Hl=
GOAL
GOAL
J
! p o u t2 fg g o a l
i E xpr="p'c> yt2foerr'',/''
I S im ln stan c'eN arp ^= "H B 1 "
j M in=0
j M ax= 0
/ '
I V\feight?Pout_2fotAlF»^
I Rang^Vart1]=”RFpow^i;i
1 F ^'hgeM ln[1]= 0
U'JanaeMJi>tIji=lfl..........
nS Sf
i pout3fp9°3l
I E x p r= "p W 3 fo e rr
I S im ln sta n c & ^ a jii'e = "H B 1 ’'
1 M in = 0
j
M ax=0
I \Afeight?1^out_3foV5F^^
I RanaeVart1]=
I [Ja tig e M ln [l]=
U'i?anaaMa><ll]=..................
1
C 5oS(
!
p re ffb g p a l
E x p r= " p rfe t,f o e r r "
1 p re fi^ p g o a l
/
!
G o si
G o*<
/
E x p r= " p f f e t2 f o e r r " /
p re fsra g o al
E x p r= " p re t5 f o e r r "
S im I n s t a n c ^ a t p « = " H 8 1 "
> S i m ) n s t a n c f e l! ^ a n j e = " H B l "
M ln =0
I
M in = 0
M in =0
I
M ax= 0
M a x =0
4" \
M ax= 0
Weight7pref_foWF
R a n g e v a r[1 1 =
R a fi* g e M ln [1 ]=
...........
Sim In s t a n c & t ^ a n j e - 'H
81"
i W e i g h t ? P 'r e f _ 2 f o W F '\
W e ig h t;# rr e f_ 3 f o W F \
1 R a n g e V a r [ 1 ] = " R F p o w e r ‘'\ ^
R a n g ^ V a r [ 1] = " R F p o w e F X ,
I R a f i g e M i n [ i] = 5
F ^ h g e M ln [1 ]= 5
kfenggMaxLlblQ............
R a D f lS M 9 « L U d a
.........
R e p r o d u c e d with p e r m i s s io n o f t h e cop y rig h t o w n e r. F u r th e r re p ro d u c tio n p rohib ited w itho ut p e r m is s io n .
448
Optimizer Specifications
E
g
l VAR
VAR4
S11m agW F=10
S11phsWF=1
S21m agW F=10
S 2 1 p h sW F = 1
S12m agW F=10
S 1 2 p h sW F = 1
S22m agW F=10
S 2 2 p h sW F = 1
P o u t_ f o W F = 1 0 0
P o u t_ 2 f o W F = 1 0 0
P o u t_ 3 f o W F = 1 0 0
P re f_ fo W F = 8 0
P re f_ 2 fo W F = 8 0
P re f
3 fo W F = 8 0
MeasEqn
e rro r_ e q u a tio n s
m a g S I 1 _ e r r = ( m a g ( s p m e a s ( 1 , 1 ) ) - m a g ( s p s i m ( 1 , 1 ) ) ) / m a g ( s p m e a s ( 1 ,1 ))
m a g S 2 1 _ e r r = (m a g { s p n n e a s ( 2 ,1 ) ) - m a g ( s p s im ( 2 ,1 ) ) ) /m a g ( s p m e a s ( 2 ,1 ) )
m a g S 2 2 _ e r r = ( m a g ( s p m e a s ( 2 ,2 ) ) - m a g { s p s im ( 2 ,2 ) ) ) /m a g { s p m e a s ( 2 ,2 ) )
m a g S t 2 _ e r r = ( m a g ( s p m e a s ( 1 , 2 ) ) - m a g ( s p s i m ( 1 , 2 ) ) ) / m a g ( s p m e a s ( 1 ,2 ))
p h s S I 1 _ e r r = { p h a s e ( s p m e a s ( 1 , 1 ) ) - p h a s e ( s p s i m ( 1 , 1 ) ) ) / p h a s e ( s p m e a s ( 1 ,1 ))
p h s S 2 1 _ e r r = (p h a s e { s p m e a s ( 2 ,1 ) ) - p h a s e ( s p s lm ( 2 ,1 ) ) ) /p h a s e ( s p m e a s ( 2 ,1 ) )
p h s S 2 2 _ e r r = { p h a s e ( s p m e a s ( 2 ,2 ) ) - p h a s e ( s p s im ( 2 ,2 ) ) ) /p h a s e ( s p m e a s ( 2 ,2 ) )
p h s S t 2 _ e r r = ( p h a s e { s p m e a s ( 1 , 2 ) ) - p h a s e ( s p s l m ( 1 , 2 ) ) ) / p h a s e ( s p m e a s ( 1 ,2 ))
p o u tfo e rr = (P m e a s f o -P s im fo ) /P m 6 a s fo
p o u t2 fo e rr = (P m e a s 2 f o -P s im 2 fo ) /P m e a s 2 fo
p o u t3 f o e r r = ( P m e a s 3 f o -P s im 3 f o ) /P m e a s 3 f o
p re ffo e rr = (P re fm fo -P re fs fo )/P re fm fo
p re f 2f o e r r = (P re f m 2 fo - P r e f s 2 f o ) /P r e f m 2 f o
p re f3 f o e rr = (P re fm 3 fo -P re fs 3 fo )/P re f m 3 fo
PARAW ETER SW EEI
XAR2
stW .;^eq= 2*R F freq
OpRI
O ptim 't\^
Opti mT
andom
E rro rF o rm = L ^ ^
U seA IIO ptV ^'^=yes
U s e A IIG (^ s= y es
M axlters= O ptrun§'^
P=2
pinstgp^e
Si m ln sta n ce^ a m e[1 ] = "
Si m l n s ta n c e N a r ti|[ ^ " S P 1 "
Sim lnstanceN am eJ§||^
Si ml nstanceN ^rtie[4]^v^
Slm lnstancef^am e[5]=: \
' \
pinsfop=8
F inal Ana! ysi s - " N one"
S etB e slV alu es= )es
Sw eepl^an="S w pPlan2"
S w ee p V arV R F freq "
/'
foicwFi
fohigh= 6
fostep= i y
D e sired E rro r= 0 .0
StatusL evei= 4
GH^''
stopfreq= 2*R F freq p t4 z
freq s t e p s ^ F f r e q ^ ^ z
\
Si m tnstapdeN am^6]=:
,pi(nstep=2
.
S eed =
S a v e S d n s ^ v e s ," '’
SaveGcals^i^^
Start=^^'
S to p ^4
^t^.5
S aveO ptia1V ars=yes
........
Sa<feNominal=yes
i=DQ>
S im u la tio n S p e c ific a tio n s
VAR
jw iV A R
VAR3
VAR1
startfreq=f^freq GHz
RFpower=5
stopfreq=3*RFfreq GHz
RFfreq=4
freqstep=RFfreq GHz
Rl=50
folow=1
Rg=50
fotilgti=6
Rdc=1.1
fostep=1
Rdd=1.1
plnstart=-10
VG0=0.1
plnstop=10
Vdd=2.5
cplng=100
plnstep=1
S-P A R A M E T E R S
l i iParam
I
SF-1
Start=startfreq
Stop=sfopfreq
Step=freqstep
H AR M ONIC BALANCE
HarmonicBalance
HB1
MaxOrder=4
Freq[1]=RFfreq GHz
Order[1]=25
Start=plnstart
Stop=p Instop
Step=pinstep
R=
lnFlle="guess2"
UselnFile=no
OutFlle="guess2"
UseOutFile=no
J| l^njoPTION^
Options
Options 1
Temp=25
Topology Check=7 es
V_RelTol=1e-2
V_AbsTol=1e-4 V
l_Rerrol=1e-2
l_AbsTol=1e-8 A
GiveAliWarnlngs=yes
MaxWarnlngs=10
S W E E P PLAN
Sw pRan_F1n
R=5
R=8
R=10
UseSweepRan=
Sw eepRan=
] [ Sw eepRan
Sw eepHan
Sw pRan1
R=-2
R=2
R=4
UseSweepRan=
SweepRan=
S W E E P P LAN
1
Sw pRan2
R=4
UseSw eepRan=
Sw eepRan=
R e p r o d u c e d with p e r m i s s io n of t h e co p y rig h t o w n e r. F u r th e r r e p ro d u c tio n prohibited w ith o u t p e rm is s io n .
449
A .ii.f. S -P a ra m e te r R esp onse o f G en eralized M odel a t V G 0 = -0 .6 V
S11
j1
f= 1 2 G H z
/
§
■
♦
0
/
M eas 2-12GHz
fo = 2GHz
fo = 3GHz
fo = 4GHz
f= 2 G H z
-jO.5
Figure A.23. Measured vs. Simulated S ll Response for VGO = -0.6V, Vdd = 2.5V, fo=2-4GHz
C:\AC_Opt_12_12_02_wPref_m0_6\sp_plot_Sll_vgo_m0_6_on_10_18_03.ai
R e p r o d u c e d with p e r m is s io n of t h e cop y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e r m is s io n .
450
S22
•
■
♦
0
/•v
Meas 2-12GHz
fo = 2GHz
fo = 3GHz
fo = 4GHz
/
/ - y f= 2 G H z
I
^
-jO.5
Figure A.24. Measured vs. Simulated S22 Response for VGO = -0.6V, Vdd = 2.5V, fo-2-4G H z
C:\AC_Opt_12_12_02_wPref_m0_6\sp_plot_S22_vgo_m0_6_on_10_18_03.ai
S21
90
120
150
X .— r - . . /
Meas 2-12GHZ
Sim,fo = 2GHz
Sim,fo = 3GHz
Sim,fo = 4GHz
f= 2 G H z •
180
f= 1 2 G H z
210
240
330
300
270
Figure A.25. Measured vs. Simulated S21 Response for VGO = -0.6V, Vdd = 2.5V, fo=2-4GHz
C:\AC_Opt_12_12_02_wPref_m0_6\sp__plot_S21_vgo_m0_6_on_10_18_03.ai
R e p r o d u c e d with p e r m i s s io n of t h e cop y rig h t o w n e r. F u r th e r r e p ro d u c tio n prohibited w ith o u t p e rm is s io n .
451
Appendix B. Fundamentals of Active Frequency
Multiplier Design Utilizing Idealized Model - Appendix
Data
R e p r o d u c e d with p e r m i s s io n of t h e co p y rig h t o w n e r. F u r th e r r e p ro d u c tio n prohibited w ith o u t p e rm is s io n .
452
B A . H a r m o n ic G e n e r a tio n v ia V a r io u s I n p u t C o n d i t io n s A p p e n d i x D a ta
B .i.a. In p u t S ignal and Bias - A p p e n d ix Data
B.i.a.l. Derivation of Harmonic Generation in double-sided, clipped
waveform including the DC level.
(File: C:\Research\Figures\Equations\ociardha_deriv_5_4_03.w m f and
part2.wmf)
This derivation results in the theoretical equations for the harmonic currents in a double­
sided, clipped sinusoid as presented by O’Ciardha et al [5], with additional calculation of
the DC levels.
Derivation for Harmonics o f Double-Sided, Clipped, Sinusoidal Waveform (OCiardha):
1. Calculation o f Clipping Durations (Eqtns 7 and 8 in Ref):
Utilizing Figure 3 in R ef.
When t = a,
FAcC0s(ru„a) + f)3c =1
FAcCOs(ro„fl) = l-F ^ c
1
a = — cos
^
V
DC
VAC
When t = b.
V ac c o s
roj
2
b
N
cos
—2-
V 2
= C 0S7T
= COS
y
= -1
[ 2J
Vac cos{7i-(O^b) + V ^ = 0
Vac [cos(;7)cos(<u„6)-sin(;T)sin(ro„6)]-l-FQ(, = 0
-V ac cos(^y«^) +
F z jc = 0
Vac cos(ro„6) = V^
DC
V ^
bA - —1 cos -1 'DC
VV
'^Ac y
R e p r o d u c e d with p e r m is s io n o f t h e cop y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e r m is s io n .
453
2. Normalized Current Waveform is:
0
vb<t<-a
Vdc +V jc cos{coj)
2
-a<t<a
i(t) = 1
Vdc +
a<t <
cos(rOgt)
2
T
T
--b < t< 2
2
0
b
3. Find Fourier Coefficients:
1
cos(ro/)]cos(i7<y/) Jt
+ I" c,os{ncoj)dt
13
+ f X ^ dc +'^ac c o s{o )j)]c o s{n c a j)d t
f
" C+ft ^DC co s{n o )j)d i + f
co s{n o )j)d t
71
+ £:
COSTCOj)cos{no}j)dt + + ^
V^^cosi^coj:)cos{ncoj)dt
12
+ £ COS[na>j)dt
73
R e p r o d u c e d with p e r m i s s io n of t h e cop y rig h t o w n e r. F u r th e r r e p ro d u c tio n prohibited w ith o u t p e rm is s io n .
454
3 .a - S o lv e fo r I I:
71=
[F r ,c C O s (n < y /)(i/ = ^ ^ r s i n ( « ® / ) " |
•’
nct)„
71 =
+ - ^ [ s i n { n c o j) f ; ‘’
no)^
71 _Vnc
no),
- sin [nco„a)
+ sin nco,, —+ b
V
U
77
K ^ [sin ( - / 7 <«„a) - sin (-«;r + nco„b) + sin («;r - nco„b) - sin («ty„a)]
71 = -^
nco,
l
71 = K
-^r-2sin(nro„o)-2sin(?7ry„Z))(-l)"
nm L
^
J
nco.
( - l ) ”""sin(n®„&)-sin(n(y„a)
nco L
J
3.b - Solve for 12:
7 2 = |F'^(,cos(<u„/)cos(n®„^)«7;= | - ^ [ c o s ( ( « + l)ft>„?) + c o s((n -l)« „ < )]rf?
72 =- ^
2
sin ((« + l)£y^/)
sin ((«-l)ffii„/)
(n + l)w„
(« -l)« „
sin ((« + l)co„;)
sin((«-l)<»„?)
72
V
72 = ----- ^
2 (n + l)(B„
sin ((n + l ) « 7 )
s in ((« -l)« /)
[n + \)o)„
{n~l)ci}„
sin(-(« +l)«„a)-sin|^-(« +l)®„^+(« +l)ca„6j +sin|^(n+l)£y„^-(« + l)ffl„6j-sin((« + l)(y„a)
2{n~l)a}„
s in ^ -(« + l)<»„-y + (« + l)®„ 6 j = s i n ( - ( « + l);T )cos((n + l)(»„ 6 ) + sin ((« + l)(»„6 ) c o s ( - ( « + l);!r)
= 0+(-l)”*' sin((« +l)fl;„i)
12 =
[ - sin ((« + 1 ) co„a) -
72 = 7 - % — r ( - 1 ) ” sin ( (« + 1)
3 .C
sin ((« + 1) cw„6 ) ]
[ - s i n ( ( n - 1)
- sin ((« + 1) <»„a)1 +
— [ ( - 1 ) ” sin (( « - 1 )
- ( - 1)”"' s in ( ( « - 1) « > ) ]
- sin ((n - 1)
- Calculate 1 3 :
73 =
1
noj„
r sin (ncoj)]
a
1
= ----- 2 sin (nru^o) =
2
sin (nco^^a)
nco„
R e p r o d u c e d with p e r m i s s io n of t h e co p y rig h t o w n e r. F u r th e r r e p ro d u c tio n prohibited w ith o u t p e rm is s io n .
)1
455
Multiply by ^ to get for A „ :
A = Y [n + n + B ]
A
2V
= ^
riTZ
sin ((^ + 1) cojj^ - sin ((« + 1) <5>oa)
+
(n + 1) K
+
KAC
(-1)" sin ((« - 1) (O^b^- sin ((n - \)co^a^
( n - 1 ) TV
• ^
t
+ —2 sin(«<y^a)
riTV
4. But, for n=l (n-1 = 0), so recalculate 12 term:
Assumes integral same throughbothintervals
12=
2
cos' (o3^t)dt
^1
1
= IV^c J - + -cos(2n;„t) d t
^Ac
^Ac Jcos
dt
Calc for one interval mult, by2
■Ub
= v.A C
-a + T
2
f
r
u
bu + ■ AC sin(-2ru^a)-sin 2co^ —T + b
2
2co„
V
V
j)
1 2 = V A C ^ - [ a + b)
V,
+ ■ A C [ - sin (2n;^a) - sin (2cy^6)]
2m
To get A, Plug n=l into II and 13 and use the above 12 to get:
4 = - ( 2 1 + / 2 + / 3)
'jy
A = - ^ [ s i n ( r y „ 6 ) - s i n ( n 2 , a ) ] + 2T;,c
1
2
[a + b)
T ~
2
V
+ ■ AC [ -s in (2<y^«) - sin (2<y„Z?)] h— sin [m^a)
2k
R e p r o d u c e d with p e r m i s s io n of t h e cop y rig h t o w n e r. F u r th e r r e p ro d u c tio n prohibited w ith o u t p e rm is s io n .
456
5. For n=0, — terms go infinate, so re-calc II and 13 terms:
n
n = v .DC
T
T
2
2
-a -\------- b + ----- b - a
73= £ dt = [tY^=2a
To get Ag Plug n=0 into 12 and use the above II and 13 to get:
A = - ( / 1 + / 2 + /3)
DC
1 -2
a+b
2a
V.
+ ■ AC [ - sin (co^a) + sin(<u„6)] +
Y
7t
R e p r o d u c e d with p e r m i s s io n of t h e co pyright o w n er. F u r th e r re p ro d u c tio n p rohib ited w itho ut p e r m is s io n .
457
B.i.a.2. MATLAB Program for Idealized Calculation of Output
Harmonic Levels
Program Calculates output harmonic voltages, currents, and power levels as a function o f
the input signal, bias, and device parameters.
(File: C:\Research\matlabfiles\pavail_pout.m)
%File pavail pout.m
1/28/2002
Jessi Johnson
%Matlab Calculation o f Pavail vs. Pout in Ideal Case
%for unclipped, single-clipped, or double-clipped waveform s
%using method o f O'Ciardha, and Lindholm paper, with backup equations from
%Clark and H ess hook. A lso utilizes som e o f Jessi's calculations for the
%Case where V gs is clipped at V fwd.
% Note, there are still som e bugs in this program. C ases for V fw d w ith a cond
%angle less than 180 deg, aren't working correctly. A lso a logic switch for
% regions where V gs < Vp and V gs > V fw d need to be added in.
clear
c lf
% Input Variables
%Transistor Parameters
Idss = .025;
V p = -0.6;
V fw d = 0;
%Saturation current (Ids when V gs = V fw d)
%Transistor pinchoff voltage
%Forward conduction voltage o f D gs
%Circuit Parameters
VGO = -0.31;
Vdd = 2.5;
R g = 50;
R1 = 50;
Rdd = 0.1;
harm = 3;
fo = 3e9;
P in d B m = [-10:1:10];
%Gate bias voltage
%Drain bias voltage
%Generator Impedance
%Load Impedance
% Resistance in DC output bias path
%number o f harmonics to solve
%Fundamental input frequency
% Availahle input power sw eep range in dBm
% Basic initial calculations
T = 1/fo;
w = 2*pi*fo;
Vm id = (V p + V fw d)/2;
PinW = (l/1000)*(10.^ (P in d B m /10));
V g = sqrt(PinW .*8*Rg);
Idsn = zeros(harm,length(Vg));
%Period o f fundamental frequency
%Fundamental frequency in radians
%Midpoint between forward conduction and p in ch off
%Convert available pow er from dBm to Watts
%Convert available pow er into gate input voltage
%Initialize an array for current harmonic content
% Calculation to normalize D ouble-Sided, clipped waveform from Ciardha paper
% Normalized DC V oltage
V D C = (VGO - V p)/(V fw d - Vp);
% Normalized AC V oltage
V A C = V g /(V fw d - Vp);
%Time w hen normalized w aveform is equal to 1
a = (l/w )* a c o s((l-V D C )./V A C );
%Time w hen normalized waveform is equal to 0
b = (l/w )* a co s(V D C ./V A C );
R e p r o d u c e d with p e r m is s io n of t h e cop y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e r m is s io n .
458
%This for loop iterates for all values o f V g and does a calculation for the
% corresponding output current o f the transistor, it contains four i f switches
% which check whether the w aveform is undipped, single, or double clipped
fo r k = l;len gth (V g)
% Chooses condition for a double-clipped w aveform
i f (V g(k )+ VGO > V fw d) & (-Vg(k)+VGO <= V p)
Ipeak(k) = Idss;
%Calculation o f peak drain current
%CaIculation o f Current waveform harmonics using Fourier C oefficients as
%Calculated in Ciardtha paper
for n=l:harm
Idsna = (2*V D C /(n ’^pi))*((((-l).^(n+l)).*sin(n.*w .*b))-sin(n.*w .*a));
Idsnb = (V A C ./((n -l)*p i)).* (((-l).^ n ).* sin ((n -l).* w .* b )-sin ((n -l).* w .* a ));
Idsnc = (V A C ./((n + l)*p i)).*(((-l)." 'n ).*sin ((n+ l).*w .*b )-sin ((n + l).*w .*a));
Idsnd = (2/(n*pi)).*sin(n.*w .*a);
Idsn(n,k) = (Idsna(k) + Idsnb(k) + Idsnc(k) + Idsnd(k));
end
%Calculate fundamental current content
Id s la = (2*V D C /pi).*(sin(w .*b)-sin(w .*a));
Id slb = 2.*V A C .*(0.5-((a+b)/T));
%The term on this line is incorrect in Ciardtha
%paper (see m y correction lab book2 page 119)
Id s lc = (V A C ./(2*pi)).*(-sin(2.*w .*b)-sin(2.*w .*a));
Id sld = (2/pi).*sin(w .*a);
Id sn (l,k ) = Id sla (k ) + Id slb (k ) + Id slc(k ) + Idsld(k);
% Idsn(l,k) = -2./pi;
(This is an approximation for the square w ave current content)
Idsn(;,k) = Idsn(:,k)*Ipeak(k);
% Unnormalize the harmonic current content
% Calculate D C Current components (not done in Ciardtha paper, calc by m e see lab book2 page 117)
Id sD C l(k ) = V D C *(l-2*(a(k)+ b(k))/T );
%Calculated by Jessi
IdsD C 2(k) = (V A C (k)/pi)*(sin(w *b(k))-sin(w *a(k)));
ld sD C 3(k ) = 2*a(k)/T;
IdsDC(k) = Id sD C l(k ) + ldsD C 2(k) + ldsDC3(k);
IdsDC (k) = ldsDC (k)*lpeak(k);
end
% Chooses condition for single-sided, clipped waveform (Clipped at Vp)
i f (V g(k) + VGO <= V fw d) & (-Vg(k)+VGO <= Vp)
aprt = (l/2*pi)*acos((V p-V G 0)A ^g(k));
phi = acos((Vp-VG O)/Vg(k));
%Calculation o f aperture time
%Calculation o f conduction angle
%Calculation o f peak drain current. Calc by Jessi - See lab book #3 page 76
Ipeak(k) = ldss*((VG O +V g(k))/(V fw d-V p)+abs(V p)/(abs(V fw d)+abs(V p)));
%Calculate current w aveform harmonics
for n=T.harm
R e p r o d u c e d with p e r m i s s io n of t h e co p y rig h t o w n e r. F u r th e r r e p ro d u c tio n prohibited w ith o u t p e rm is s io n .
459
% Calculation using the Ciardha Paper (seem s less accurate)
%Idsna = sin ((n -l)*p i*ap rt)/(n -l);
%Idsnb = sin((n+l)*pi*aprt)/(n+l);
%Idsnc = -(2/n)*cos(pi*aprt)*sin(2*pi*aprt);
%Idsn(n,k) = (Ipeak(k)/pi)*(Idsna + Idsnb + Idsnc);
%CalcuIation using Clarke and H ess B ook (more aceurate)
Id sn (n,k ) = (2 * Ip e a k (k )/p i)* (c o s(p h i)* sin (n * p h i)-n * sin (p h i)* c o s(n * p h i))/(n * (n ^ 2 -l)* (l-c o s(p h i)));
end
“/oCalculation o f fundamental current content using
%Ciardha Paper (there must be som e error in this because it gives inaecuracy)
% Idsla = pi*aprt;
% Idslb = -sin(2*pi*aprt)/2;
% Idsn(I,k) = (Ipeak(k)/pi)*(Idsla+IdsIb);
% Calculation o f fundamental using Clark and H ess B ook
Id sn (l,k ) = (Ipeak(k)/pi)*(phi-cos(phi)*sin(phi))/(l-cos(phi));
%Calculation o f D C current component
IdsDC(k) = (Ipeak(k)/pi)*(sin(phi)-phi*cos(phi))/(l-cos(phi));
end
% Chooses condition for single-sided, clipped waveform (clipped at V fwd)
%This case worked by Jessi - see lab book #2 page 76
% Note that this case still does not work for V fw d case, need to fix this
%It giv es incorrect phase
i f ((V g(k) + VGO > = V fw d) & (-Vg(k)+VGO > = V p))
phi = acos((Vfwd-V G O )/-V g(k));
%Calculation o f conduction angle
% Calculation o f min drain current
Imin = Idss*((V G O -V g(k))/(V fw d-Vp)+abs(V p)/(abs(V p)+abs(Vfwd)));
Ipeak(k) = Idss - Imin;
% Calculate current w aveform harmonics
forn=I:harm
% Calculation using Clarke and H ess B ook (more accurate)
Idsn(n,k) = -(2*Ipeak(k)/pi)*(cos(phi)*sin(n*phi)-n*sin(phi)*cos(n*phi))/(n*(n^2-I)*(l-cos(phi)));
end
% C alculation o f fundam ental u sin g Clark and H ess B o o k
I d s n (l,k ) = -(Ip e a k (k )/p i)* (p h i-c o s(p h i)* sin (p h i))/(l-co s(p h i));
% C alculation o f D C current com p on en t
Id sD C (k ) = Id ss - (Ip ea k (k )/p i)* (sin (p h i)-p h i* c o s(p h i))/(I-c o s(p h i));
end
R e p r o d u c e d with p e r m i s s io n of t h e co p y rig h t o w n e r. F u r th e r r e p ro d u c tio n prohibited w ith o u t p e rm is s io n .
460
% Chooses condition for undipped waveform
i f (V g(k) + VGO < = V fw d) & (-Vg(k)+VGO > Vp)
%Set all harmonics except fundamental equal to zero
for n=l:harm
Idsn(n,k) = 0;
end
% Calculate fundamental com ponent based on a linear transistor response
% (m odelA but M odified for arbitrary V fw d, see lab book #2 page 120)
ld sn (l,k ) = Idss*(V g(k)/(V fw d-V p));
% Calculate D C com ponent based on linear tranistor response
IdsDC(k) = ldss*(V G O /(V fw d-V p)+abs(Vp)/(abs(Vfwd)+abs(V p)));
end
end
%End o f current w aveform harmonic calculations
V dsn = -Idsn.*Rl;
V dsD C = Vdd - IdsDC*Rdd;
P o u tlW = 0.5.*real(conj(Vdsn).*Idsn);
P o u tld B m = 10*lo g l0 (P o u tlW * 1 0 0 0 );
plot(PindBm ,Pout 1dBm)
%Calculate harmonic output voltage
%Calculate DC output voltage
%Calculate output power in watts
%Convert output power to dBm
%Plot Pavailable vs. Pout
%Output Pin vs. Pout data into an ascii file
%Setup Pin and Pout vectors
indat = transpose(PindBm);
outdat = real(transpose(PoutldBm ));
output = [in d a t, outdat];
%This is the header for the pow er data, arranged in columns
pwrtitle = '%Pin(dbm) Pout @ fo Pout @ 2fo Pout @ 3fo'; %Power out file
%Convert pow er data to text format
outputtext = num2str(output);
% initialize output file array
matrix=[];
matrix = strvcat(pwrtitle, outputtext);
%Convert sw eep range to text for formatting
pinstarttext = num2str(min(PindBm));
pinstoptext = num2str(max(PindBm));
pinsteptext = num 2str(abs(PindBm (l)-PindBm (2)));
fotext = num2str(fo);
vddtext = num2str(Vdd);
vgotext = num2str(VG0);
datetext = num2str(date);
%Title to input on T ext file
title = '%Theoretical Pin vs. Pout Data for M odelA , B iased for Optimum 3fo CG:';
title2 = cat(2,'% B ias Voltage: V go = ', vgotext, 'V, Vdd = ', vddtext, 'V');
R e p r o d u c e d with p e r m i s s io n of t h e co p y rig h t o w n e r. F u r th e r r e p ro d u c tio n p rohibited w ith o u t p e r m is s io n .
461
titles = cat(2,'% Freq: fo = fotext, ’GHz');
title4 = cat(2,'% Pow er Range: Pin = pinstarttext, 'dBm to ', pinstoptext, 'dBm, (', pinsteptext, 'd B m ...
step)');
titles = cat(2,'%Calculated o n : ', datetext,' - Jessi Johnson');
%Input title information
output = strvcat(title,title2,titles, title4, titleS, matrix);
%Enter output filenam e inbetween single quote marks 'filename'
dlm write('m odelA_tripler_opt_CG _Calc_l_27_03.txf,output,')');
R e p r o d u c e d with p e r m i s s io n of t h e cop y rig h t o w n e r. F u r th e r r e p ro d u c tio n prohibited w ith o u t p e r m is s io n .
462
B.i.a.3. Derivation of Harmonic Generation in an undipped waveform
with arbitrary Vfwd.
H a r m o n ic s i n
a n U n d i p p e d W a v e fo r m ( a r b i t r a r y
V fw d )
Define loss andloss^as:
lo s s = Id s{V g s = V Jw d)
Idss„ = Id s{V g s = 0)
Use equation for a straight line to find Ids waveform equation:
Id s
= m Vgs + b
IDSS
m =■
V fw d -V p
^DSSo
■-DSSn
\Vp\
^
•-DSS
\V ^ + \V jw d \
Id s = I DSS
Vgs
■+
Y fiv d -V p
\Vfivd\+ \VF\
Split into DC and AC Components:
n>l
Ids„ =
Vg
DSS
VGO
•■DSS
n=l
V fw d -V p
V fw d -V p
n=0
■+
\Vfw d\ + \Vp\
R e p r o d u c e d with p e r m i s s io n of t h e co p y rig h t o w n e r. F u r th e r r e p ro d u c tio n p rohibited w ith o u t p e r m is s io n .
463
B.i.a.4. SDD of Model A
Model:
[w ]VA R
Constants
ldss=.025
Vp=-.6
A
Ids vs. Vds:
Constant
Ids vs. Vgs:
Linear
Dgs:
Resistiw
Dgd:
X
Cgs:
X
Ggd:
X
o il
G
Nutn=1
□
I VAR
Port_Voltages
Vgs=_v1
Vds=_v2
Vgd=_v3
EjVAR
Port_Gurrents
lds(x,y) = if x>=Vp ttien kJsa else 0 endif
ldsa=ldss*(1-(VgsA/p))
Diode_res
X2
D
Num=2
sCrap
SDD3P1
l[1,0]=0
l(2,0]=lds(Vgs,Vd
l[3,0]=0
!)
Num=3
Figure B .l. Symbolically Defined Device Representation of Model A
Diode_res
This is a diode model which uses a logic switch
to turn current on and off. When Vd<0 the currer
is 0, When Vd>=0 the current increases linearly
(ie the "ON" diode is a very small resistor, equal
to Rd)
o
Oft
A
Num=1
P
SDD1P1
l[1,0]=ld
C[1]=
E ! VAR
Port_Voltage_Definitions
Vd= v1
Port
C
Num=2
®VAR
Constants
lss=1e-13
V1=.01
Rd=0.01
G=1/Rd
I VAR
Port_Currents
ld=if Vd >= 0 then G*Vd else 0 endif
Figure B .l. Symbolically Defined Device Representation of Idealized Diodes
R e p r o d u c e d with p e r m i s s io n of t h e co pyright o w n er. F u r th e r re p ro d u c tio n p rohib ited w itho ut p e r m is s io n .
464
B.i.a.5. ADS Schematic of Input Signal and Bias Study.
QVAR
mHannorucBaiance
. HARMONIC BALANCE
T o p o l ogy C h eck = y es
V _ R e(T o l= 1 e-2
V _ A b s T o l= 1 e -4 V
l_ R e lT o l= 1 e-2
R d c= 5 0
Rdd=0.1
VG0=-0.01
V d d= 2,5
pin sta rt= -1 0
p in s to p = 1 0
pin ste p = 1
S te p = p in s te p
Pt=
ln F iie= " g u ess2 "
U s e ln R le = n o
Optiottft
O p tio n s i
T em p= 25
R Ffreq=3
R l=50
R g= 50
freq step = 1 GHz
folow=1
fohigh= 6
fo step = 1
Freq[1]=R Ffreq GHz
Ortierf1]=25
S ta rt= p in s ta rt
S to p = p in sto p
O u tF ile = "g u ess2 "
U se O u tF ile= n o
VAR2
R F pow et^ S
VAR3
startfreq = 3 GHz
sto p fre q = 9 GHz
HB2
MaxOrder=4
C p ln g = 1 0 0
l_ A b s T o l= 1 e -8 A
G iv eA llW am in g s= y es
M a)A/Vamings=10
Pfc
P fc2
P sim fo= w todbm (pfc(vout,0,ldsout.i,{1}))
P s im 2 fo = w to d b m (p fc (v o u t,0 ,ld so u t.i,p } ))
P slm 3fo= w todbm (pfc(vout,0,ldsout.i,{3}))
CGfo = P s im fo - R F p o w er
C G 2fo = P s im 2 fo - R F pow er
CGSfo = P sim S fo - R F pow er
Pspec
Pm eas
P o u t= p s p e c (w d s o u t,0 ,-Id s o u t.i)
P refg= p s p e c (v re fg , 0,1 re fg .i)
P fc3
Prefsfo=w todbm (pfc(vrefg,0,lrB fg,i.{1}))+C plng
Prefs2fo=w todbm (pfc(vrefg,0,lrefg.i,{2}))+ C plng
Prefs3fo=w todbm (pfc(vrefg,0,irefg.i,{3}))+ C plng
R =50 Ohm
CouoTerSsnqie
C 0U P 1
C o u p lin g = C p ln g d B jg
M VSW R1=1.
C V S W R 1= 1.
'R
P.JTone
I
L o s s 1=0. dB
R2
D ire ct1 = 1 0 0 dB
R = R dc Ohm!
ZR ef= 50. Ohm
po rti
id s o u t
R
R3
R =R dd Ohm
v',„OC
" z = 5 0 O hm
P = d bm tow (R FpowefT
F req= R F freq GHz
V dc=
SR C 1
Vdc=VGO V
V_DC
|S R C 2
‘V dc=V dd V
Figure B.3. ADS Schematic for Characterization of Idealized Models
R e p r o d u c e d with p e r m is s io n of t h e cop y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e r m is s io n .
, ;R1
’ 'R =R I Ohm
465
B.i.a.6. Optimum 2fo Output Design Using Optimum Conduction Angle
Method.
(file: C:\Research\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\ii
Harm_Gen_via_Input_Cond\a Input Sig and Bias\2 Study using Idealized Model\caseE
optimum designs\modelA_maas_doub_design_2_03_03 .mcd)
This design method uses the current versus conduction angle calculation as presented in
Maas [3] and Clarke and Hess [43].
Design of Frequency Doubler Using Optimum Conduction Angle (Maas)
1. Input transistor parameters, pinchoff voltage (Vp) and generator resistance (Rg):
Vp := -0.6
Rg := 50
2. Choose optimum conduction angle ( 2
2(|) := 120
(|) ) for maximum normalized Ids @ 2fo:
^:= 60
3. Set Vg and VGO to maximize the peak output current Ip:
VGO + Vg = Vlwd = 0
VGO = -Vg
4. Calculate Vg and VGO using the conduction angle equation:
/ X V -V qo
COS((b) :=---------Vg
cos
- V g o - c o s (< |)) : = V p -
V -V qo
:=-----------Vgo
V go
1 - cos (f deg)
Vg:-VGO
5.
Vg=1.2
Calculate Pavail (into an open circuit), required to give Vg:
1 V
^avair=2'TR
^avail =
^ a v a i l d Bm( ^ a v a i l )
wtodbm(x) := lOlog(x-lOOO)
^availdBm 5.563 dBm
R e p r o d u c e d with p e r m i s s io n of t h e cop y rig h t o w n e r. F u r th e r r e p ro d u c tio n prohibited w ith o u t p e rm is s io n .
466
B.i.a.7. Optimum 2fo Output Design Using Rectangular Waveform
Method.
(file: C:\Research\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\ii
Harm_Gen_via_Input_Cond\a Input Sig and Bias\2 Study using Idealized ModeAcaseE
optimum designs\modelA_ciardha_doub_design_2_03_03 .mod)
This calculation utilizes the method o f O’Ciardha et al [5].
Design of Frequency Doubler using Rectangular Waveform (O'Ciardha)
1. Input transistor parameters, pinchoff voltage (Vp), forward conduction voltage (Vfwd), angenerator resistance (Rg):
V p := -0 .6
R g:= 50
2. Choose near optimum, normalized AC and DC gate voltage levels for maximum second
harmonic output Ids @ 2fo (approaches a 0.25 duty cycle, dipped rectangular wave). See
O'Ciardha paper, tablet
3.
Unnormalize to find Vg and VGO
'^GO-Vp
^
''.DC-
V fw d -V p
VGO:=MVfwd-Vp) + Vp
Vgo=-1. 56
V„
V.AC^
'^fwd
V, := V A c (V iV d -V p )
4.
Vg = 1.86
Calcuiate Pavail (into an open circuit), required to give Vg:
Pavail'=
2 4 Rg
Pavail =
PavaildBm' "^°‘^^™{Pavail)
^
wtodbm(x) := iaiog(x-1000)
PavaildBm
R e p r o d u c e d with p e r m is s io n of t h e cop y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e r m is s io n .
467
B.i.a.8. Optimum 3fo Output Design Using Optimum Conduction Angle.
(file; C:\Research\l_B_l Undrstndng NL Mech\B Stdy Idlzd MdlsMi
Harm_Gen_via_Input_Cond\a Input Sig and Bias\2 Study using Idealized Model\caseE
optimum designs\modelA_maas_trip_design_2_03_03 .mcd)
This design method uses the current versus conduction angle calculation as presented in
Maas [3] and Clarke and Hess [43],
Design of Frequency Tripler Using Optimum Conduction Angle (M aas)
1. Input transistor parameters, pinchoff voitage (Vp) and generator resistance (Rg):
Vp
:=-0.6
Rg := 50
2. Choose optimum conduction angle ( 2i^ ) for maximum normalized Ids @ 3fo:
2(t):=80
(t):=40
3. S et Vg and VGO to maxim ize the peak output current Ip:
VGO + Vg = Vfwd = 0
VGO = -Vg
4. Calculate V g and VGO using the conduction angle equation:
Vg
-Vgo
-VQgcos((()) := Vp - Vqo
Vqo :=------- :----- T
1- cos((j)-deg)
Vg:=-Voo
5.
Vf-;n= -2.565
V =2.565
Calculate Pavail (into an open circuit), required to give Vg:
^avail ■=
1
^
2 4 Rg
^avail = 0 016
^availdBm - "^°‘^'’”'('^avail)
W
wtodbm(x) := 101og(x-1000)
^availdBm 12.16 dBm
R e p r o d u c e d with p e r m is s io n o f t h e cop y rig h t o w n e r. F u r th e r r e p r o d u c tio n p rohib ited w ith o u t p e r m is s io n .
468
B.i.a.9. Optimum 3fo Output Design Using Rectangular Waveform
Method.
(file: C:\Research\l_B_l Undrstndng NL Mech\B Stdy Idlzd MdlsMi
Harm_Gen_via_Input_Cond\a Input Sig and Bias\2 Study using Idealized Model\caseE
optimum designs\modelA_ociardha_trip_design_2_03_03 .mcd)
This calculation utilizes the method o f O’Ciardha et al [5].
D esign of F requ ency Tripler using R ectan gu lar W avefo rm (O 'C iard ha)
1.
Input transistor p aram eters, pinchoff voltage (Vp), forward conduction voltage (Vfw d), an'
g en erator resistance (Rg):
Vp-=-0.6
2.
Rg.= 50
Vj^d:=0
C h o o s e n ea r optimum, norm alized A C and D C gate voltage levels for m axim um third
harm onic output Ids @ 3fo (approaches a (1 /6 ) duty cycle, clipped rectangular w a v e ). S e e
O 'C iardh a paper, ta b le t
^DC •3.
X\C
U n n o rm alize to find V g and VGO
V
TDC .
V fw d -V p
'^GO'- ’^Dc(^fwd "■'p) +
%jO-
V
V g := V A c (V f^ d -V p )
4.
V„ = 4.2
C alcu late Pavail (into an open circuit), required to give Vg:
1
2 4 Rg
Pavail :=-----
Pavail"
PavaildBm ■“ "^®‘^^™(Pavail)
wtodbm(x) := 101og(x-1000)
PavaildBm
16.444 dBm
R e p r o d u c e d with p e r m i s s io n of t h e cop y rig h t o w n e r. F u r th e r r e p ro d u c tio n prohibited w ith o u t p e rm is s io n .
469
B .i.b. In p u t Im p ed an ce M atch ing @ the Fu ndam en tal - A p p e n d ix
Data:
B.i.b.l - ADS Schematic for Fundamental Frequency Input Impedance
Study:
mVAR
HARMONIC BALANCE
VARS
startfreq*3GHz
stopfreq=9GHz
freqstep=1 GHz
:«rrmr«c8alanc«
HB2
MaxOrcter=4
Freq[1]=RFfreq GHz
Order[1l=25
SweepVar=''Zm1"
Start=10
Stops 350
Step=2
fohigh=6
ft»tep=1
pinstart=-10
pinstop=10
pinstep=1
Pts
VAR2
RFpower=-10
RFfreq=3
Rl=50
R gs50
Rdc=50
Rdd=0.1
VG0=-0,6
Vdd=2.5
Cplng=100
Zm1=10
0|!^ons1
Temps 25
Topol ogvChecks yes
V_RelTol=1e-2
V_AbsTol=l6-4V
)_RelTol=le-2
l_AbsTol=1e-8A
GiveAIIVV^rningssyes
Max\Ahrnln 9 SslO
Pouts p6pec(vds out,O,*l<lsout>)
Pre^sp5pec{vre^.0,lref
Pfc2
,ir^.i.{l)))+
C plng
Prefsfb=wloclbrn(p^vr^.O,irefi
'
Prefs2fbswtodbm(pfc(vre^ ,0,lre^ i.{2}))+C|^ng
Prefs3f6swtodbm(pfc(vre^ ,0,lre^ ,i,{3}))+Cp(ng
Psimfoswtodbm(pfc(voijt,0,idsout.i,{1}))
Psirr0o=vvtodbr^pfc(vout,O,ldsout.i,{2}))
Pslm3foswtodbm(pfc(v(xit,0,ldsout.i ,{3}))
C G fos Psimfo - RFpower
C G 2fos PsirrCfo- RFpower
CGSfo = PsimSfo - RFpower
50 Ohm
ouf^erS!
C 0UP2
C ouplingsCplng||B
MVSV\R1=1,
CVS\W1=1
LoSSlsQ
R6
Direct1=100dB
R sR dcO h
Ref=50. Ohm
R
, PUons;
Z=Zm1
F=3GHz
P2
X
Files"2fo&3fo block >2p“
R3
R sRdd Ohm
1 p 6 r T2
“ Z=50Ohm
P s dbcTtcw( R Fpowef
FreqsR Ffreq GHz
Vdcs
RIOhm
VDC
SRC3
Vdc=VGOV
SRC4
Vdc=VddV
S-PARAMETERS
RspOOhm
C 0U P3
Coupling sC plng|ip
MVSVVR1=1.
CVSWR1=1.
Loss1=0. dB
Kr.
,^ 1. Direct1=100dB
R sR dc O h n ^ p g ^ 5Q_
Z=50Ohm
Zin1=zln(S11,PortZ1)
Zin2szin(S33,PortZ3)
GHz
StepsI.OGHz
Sweepi
SNI
Files "2fo 4
SweepVars"^r
3 fo blocks2j
SimlnstanceName[1]="SPr
SimlnstanceName|2]s
SlmlnstanceName(3]=
SimlnstanceName|4is
ZsSOOhm SimlnstanceName[5]s
SimlnstanceNarTB[6]=
Starts 10
Stops 350
Step=2
Figure B.4. ADS Schematic for Fundamental Frequency Input Impedance Study
F ile: C :\u sers\d e fa u lt\a d s\id e a lx tr m o d e lin g _ p r j\n etw o rk s\m o d e lA _ w lk o h m _ H B _ w M l_ m a tch sw p j j . d s n
R e p r o d u c e d with p e r m is s io n o f t h e cop y rig h t o w n e r. F u r th e r r e p r o d u c tio n p rohib ited w ith o u t p e r m is s io n .
470
B .i.c. In p u t Bias N etw o rk - A p p e n d ix Data:
B.i.c.l. ADS Simulation Schematic for Input Bias Network Study
PARAMETER SWEEP
Psi|amS‘jveer-
Sv^^pl
/
/
S w eepp!an= "Sw pP |^n1"
Sweep'J^r="Rdcy^
,
S tm ln sta)> ce N afn e [1 ]= "H si'
S im ln s ta n C ^ a m e [ 2 ]=
S ifnlnstantret^am e[31=
S im ln s t^ c e N a h 3 e [ 4 ]=
S im ln s ta n c e N a rrr^ 5 ]=
S im tK stanceN am e[6^=
Stj(ft=
^op=
___
El VAR
VARS
s ta rtfre q = 3 G H z
sto p fre q = 9 G H z
freq s(e p = 1 G H z
f olow=1
fohigh=6
fo step = 1
pinstart= -10
pinstop= 10
pinstep=1
SWEEP PLAN
HARMONIC BALANCE
H anrionicB alance
C-^^epPian /
HB2
M axO rder=4
F req [1 ]= R F fre q GHz
O rder[1]=25
S ta rt= p in start
S to p = p in sto p
S te p = p in step
Pt=
lnFile= "guess2"
U selnF ile= no
O utF lle='’g u e s s 2 "
U seO utF ile= no
S w |iftan 1 /
C a VAR
VAR2
R Fpow er=5
R F freq= 3
Rl=50
R g=50
Rdc=1
Rdd=1.1
VG0=file{DAC5, ’Vgo"}
Vdd=2.5
C ping=100
a
T^sAccessCoriipor.ent
p t= i6 o /
P t= 5 0 ,X
Pt=J.0
Pti^l
\
\
l/seSw eepP l^q=
DAC5
Fi(e=”m o d elA _ c aseA _ R d c 5 0 _ V g sD C _ v als_ 5 _ 1 5 _ 0 3 .m d f"
T yp esG en eratized M ulti-dim ensional D a ta
lnterpM ode=Linear
In terp D o m ^ R e ctan g u lar
iVar1s"R Fpower"
iV allsR F p o w e r
<5pttons^^
O ptional
T em p= 25
Topology C h e c k = y e s
V_RelTol=1e-2
V_AbsTol=1e-4 V
l_RelTol=1e-2
l_AbsTol=1e-8 A
Giv eA llW am ings=y e s
M axW am ings=10
K’rooe
R=50 Ohm
P fc 2
P m eas
P o u t= p s p e c (v d s o u t,0 ,-Id s o u t,i)
Pf c 3
g = p sp e c (v re f g,0 , Iref g, i)
P refsfo = w to d b m (p fc(v refg ,0 ,lre fg .i,{ 1 )))+ C p ln g
P refs2 fo = w to d b m (p fc(v refg ,0 ,lre fg .i,{ 2 } ))+ C p ln g
P refs3 fo = w to d b m (p fc{v ref g ,0 , Iref g.i,{3}))+Cplng
P sim fo= w todbm (pfc(v out, 0, Idsout,
P sim 2fo= w todbm (pfc(v out, 0, Id so u t. i,{2}))
P sim 3 fo= w lodbm (pfc(vout,0,ldsout.i,{3}))
C G fo = P s im fo - R F pow er
G G 2fo = P s im 2 fo - R F pow er
C G 3 fo = P sim S fo - R F pow er
O oupie
C0U P1
C oupling=Cplng d B |g
MVSWR1=1
CVSW R1=1
L oss1=0. dB
D irect1= 100 dB
R - R d c O f i'^ R e f = 5 0 . Ohm
„.1Tony
PORT1
Num=1
SRC1
Z=50 Ohm
Vdc=VGO V
P=dbm tow (R F powel^
F re q = R F fre q GH z
Vdc=
1
H ie::'
R
R3
R =R dd Ohm
R
^R1
; •R = R i O hm
\/_D C
^S R C 2
W dc= V dd V
Figure B.5. ADS Simulation Schematic for Input Bias Network Study
File: C:\users\default\ads\ideaIxtrm odeling_prj\networks\HBtest3_Inputsim_BiasshftTbl.dsn
R e p r o d u c e d with p e r m is s io n of t h e cop y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e r m is s io n .
471
B.i.c.l. Gate waveforms for various values of Rdc using realistic Model
(Model36a_Vgo_pO_l), Case C1.3 (VGO = 0.8V, Pin = 5 dBm)
Rdc
R dc
Rdc
Rdc
= 1 ohm
= 1 0 ohm s
= 50 ohm s
= 100 ohm s
0.5
-0.5
V.
V -..
/
1V. • • . r . '*/ // -
V***.
T im e (s e c )
-
x10
-10
Figure B.6. Gate waveforms for various values of Rdc using realistic Mode! (Model36a_Vgo_pO_l),
Case C1.3 (VGO = 0.8V, Pin = 5 dBm)
File; C:\Research\l_B_l UndrstndngNLMech\BStdy IdlzdMdlsMiHarm_Gen_via_Input_Cond\c Input Bias
Network\model36a_vgo_p0_l_2_14_03\ model36a_vs_meas_CaseCI_3_vgswf_rdcswp_6_26_03.fig
The above figure is the simulated response o f the realistic PHEMT model (presented
in Chapter 2 in Figure 2.14 on page 40) for various Rdc values, at an input power level o f
5 dBm and a gate bias at forward conduction. Note that the gate bias o f 0.8V is much
larger than the bias o f case Cl (VGO=OV) because the more realistic model has a forward
conduction voltage approximating that o f the actual device. The response in the realistic
model shows the minimum waveform point decreasing as the value o f Rdc becomes
larger, the same trend exhibited in the idealized model.
R e p r o d u c e d with p e r m is s io n of t h e cop y rig h t o w n e r. F u r th e r r e p r o d u c tio n prohibited w ith o u t p e r m is s io n .
472
B.i.c.3. Study of Input Bias Network with Realistic Device Models
In order to study the implications o f the study shown in Section S.ii.c, several more
realistic models were tested for the case o f a bias midway between pinchoff and forward
conduction. This case, in a more realistic design, is case Al_adj rather than case A l.
Case A l adj represents a bias exactly midway between pinchoff and forward conduction
when the forward conduction voltage (Vfwd) is set to a realistic value (Vfwd = 0.8V).
For the actual device this midway bias occurs at +0.1 V.
M o d e lA jf b :
The idealized model, model A, was adjusted to have a Vfwd value which matched that
o f the actual PHEMT used in this study (Vfwd = 0.8V). This model (model A_4_b) was
tested under the varying Rdc condition for case A l adj. Figure B.7 shows the input vs.
output power response for varying Rdc values.
R e p r o d u c e d with p e r m i s s io n of t h e co p y rig h t o w n e r. F u r th e r r e p ro d u c tio n prohibited w ith o u t p e rm is s io n .
473
20
19
18
17
E
m 16
CO
>2 15
(O
T3
@
3
o
Q.
I
Q.
13
-10
-10
12
- - Rdc =1
Rdc = 10
— Rdc = 50
— Rdc= 100
11
10
'4
5
6
7
8
Pin (dBm)
10
9 10
Pin (dBm)
-15
Pin (dBm)
Figure B.7. Pin vs. Pout o f M odelA-4-b, Case A l adj, varying Rdc values
C :\R ese arch \l_ B _ l U ndrstndng N L M ech\B Stdy Idlzd MdlsMi H arm _G en_via_Input_C ond\c Input B ias
N etw ork\m odelA _ 4_b _ rd csw p_ 2_ 14_ 03\ m odelA _ 4_b_caseA _adj_rdcsw p_zoom ed_pw r_ 2_ 18_ 03.fig
Figure B.7 shows a response that is equivalent to the idealized model (model A),
presented in Section S.ii.c, the choice o f Rdc has a very significant effect on the output
harmonics. The response o f model A_4_b can be compared to the actual device. The
measured and simulated response o f the actual device is shown in Figure B . 8 .
Reproduced with permission o f the copyright owner. Further reproduction prohibited without permission.
474
20
1
19
;
18
17
1 ^
m 16,
i t
r
f
1
^ 7 - ____
>2 15
1
M eas Rdc = 1
M eas Rdc = 10
M eas Rdc = 50
M eas Rdc = 100
Sim Rdc = 1
Sim Rdc = 10
Sim Rdc = 50
Sim R d c = 100
3 14
o
Q.
13
--
--
;
11
____ i
1
i
5 6 7 8 9 10
Pin (dBm)
4
5 6 7 8 9 10
Pin (dBm)
4
5 6 7 8 9 10
Pin (dBm)
Figure B.8. Pout vs. Fin Response o f Actual Device and Device M odel, Case A l adj, V arying R dc
C :\R e se arch \l_ B _ l U ndrstndng N L M ech\B Stdy Idlzd MdlsMi H arm _G en_via_Input_C ond\c Input B ias
N etw o rk \m o d el 36a_vgo_p 0_ l _ 2_ 14_ 03\ m odel 36a_vs_m eas_C aseA _adj_pw r_rdcsw p_ 2_ I 7_ 03.fig
Comparison o f Figure B.7 and Figure B . 8 are quite interesting. The figures clearly show
that the choice o f a small Rdc value leads to a larger second harmonic output power.
Similarly, the choice o f Rdc which is not equal to 50 ohms leads to a smaller amount o f
third harmonic output power. It is also clear, however, that Rdc has less o f an effect on
the realistic device. This can be attributed to the presence o f parasitic elements at the
gate [55], which distort the clipped waveform across Dgs. This effect is shown in Figure
B.9.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
475
0.5
D)
-0.5
Ideal Rdc = 0.1
Ideal Rdc = 50
Sim Rdc = 0.1
Sim Rdc = 50
-1.5
Time (sec)
xIO
-10
Figure B.9. Gate Voltage W aveform s for Idealized (M odel A_4_b) and Realistic PHEM T M odel,
Case A l adj, Pin = +5dBm
C :\R ese a rc h \l_ B _ l U ndrstndng N L M ech\B Stdy Idlzd MdlsMi H arm _G en_via_Input_C ond\c In p u t B ias
N etw o rk \m o d el 36a_ vgo_p 0_ l _ 2_ 14_ 03\ m odel 36a_vs_m odelA - 4-b_C aseA _adj_vgsw f_rdcsw p_ 2_ I 8_ 03.fig
Figure B.9 shows that the presence o f parasitics (Rg, Rs, Lg, Cpg, Cpgi and Ls - as
shown in the realistic model in Chapter 2 in Figure 2.14, page 40) distorts the clipped
waveform appearing at the gate. As a result, the effects o f varying Rdc are less severe.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
476
B.i.c.4. Compensation Technique Using Realistic Models
In order to verify the compensation technique developed in Section 3.ii.c.3 it was
conducted on the realistic PHEMT model presented in Chapter 2 (Figure 2.14, page 40).
Figure B.IO shows the measured and simulated values o f the DC voltage levels at the
gate with varying input power.
0.1
0.05
0
----- Meas Rdc = 1
Meas Rdc = 10
----- Meas Rdc = 50
----- Meas Rdc = 100
o Sim Rdc = 1
X Sim Rdc = 10
□ Sim Rdc = 50
* Sim Rdc = 100
S-0.05
o
o
tn
^
-0.1
-0.15
-0.2
-0.25
0
2
4
6
Pin (dBm)
Figure B.IO. M easured and Simulated Shift in the DC Bias Level vs. Input Power, C ase A l adj
C :\R e se a rc h \l_ B _ l U ndrstndng N L M ech\B Stdy Idlzd MdlsMi H arm _G en_via_Input_C ond\c Input B ias
N etw o rk \m o d el 36a_vgo_p 0_ l _ 2_ 14_ 03\m o d el 36a_vs_m eas_C aseA _adj_vgsD C _rdcsw p_ 2_ 17_ 03.fig
The figure verifies the effect shown in Section 3.ii.c.2. For small Rdc values, the DC
gate voltage level is insensitive to the AC input level. As Rdc is increased, the DC
voltage drops with increasing AC input. The “expected” result occurring at Rdc = 50
shows a shift in bias from 0.1 V to around -0.1 V for a 10 dBm input power. N ote that the
Reproduced with permission o f the copyright owner. Further reproduction prohibited without permission.
477
figure shows that the realistic device model and the measured response show the same
trend, and have very close agreement.
Figure B .l 1 shows a comparison o f Pin vs. Pout o f the realistic model for Rdc = 50
ohms compared to Rdc = 1 ohm, where the bias level has been adjusted exactly
corresponding to the shift o f Rdc = 50 ohms (as shown in Figure B.IO). This repeats the
compensation technique explored in Section 3.ii.c.2 with the realistic device model.
Similarly to the previous results, the technique demonstrates the equivalency o f using
Rdc = 50 ohms and using an adjusted Rdc = 1 ohm.
-10
-10
-15
S^-15
TJ
T3
-20
?0 -20
-25
-25
-30
Rdc = 50
Rdc = 1 w/bias adj
-35
-30
-40
-45
-10
-35
-10
-10
Pin (dBm)
Pin (dBm)
Pin (dBm)
Figure B . l l . Pout vs. Pin Response o f Realistic M odel (M odel36a-vgo-p0-l) for Rdc = 50 Ohm s, and
Rdc = 1 Ohm W ith Bias Adjustm ent
C :\R ese arch \l_ B _ l U ndrstndng N L M ech\B Stdy Idlzd MdlsNii H arm _G en_via_Input_C ond\c Input B ias
N etw ork\m odei 36a_vgo_p 0_ l _ 2_ 14_ 03\m odel 36_a_vgo_p 0_l_caseA _adj_biasT bl_pvw _ 2_ 18_ 03.fig
Reproduced with permission o f the copyright owner. Further reproduction prohibited without permission.
478
B.i.d. nfo Input Reflector Networks - Appendix Data:
B.i.d.l. Derivation of Available and Reflected Power
See Lab Book #7 - Page 113
The incident and reflected power waves are given by:
n+R j,
2 ^ ^
2
^
It follow s that:
P „ ^ .= R e { 6 ,- A ; }
First, Solve for Available Power:
.
L
+
v
.
r
+
v
:
1
%R
g
1
r
v , v : + R ] h i : + R / j > R , h v :
g
Re
} = ^ [ R e {k. k;} +
{V ,•} + « , . Re {r./; + / . k; }'
+ ^ M L f + 2 R ,-R e {L L ‘ }
n f
P
avail/^
, R ,\h
=
g
8
The reflected power follows directly by calculating:
R e p ro d u c e d with p e rm issio n o f th e co p y rig h t o w n er. F u rth e r re p ro d u c tio n p ro h ib ite d w ith o u t p e rm is sio n .
479
Resulting in:
^ ref, %R
8
g
A D S Verification o f Above Equations:
COVAj%
\\4m-
¥m'j
mm
^m
mdmi
mui^-as.
•CjsimHsttail
Stwtis
Pv^its
snF^^'^wii4i2‘
8
m
RtS
R«f«»vvldit
mt^
CHVdJR
F fe a » se^ iy ^ c^ v » « l0 ,M ie ii
ii
\
iSlfi
El
ht()|i (Dl'i‘C^r^:
P»irfB"MA'tedfern|>^rew itKU ■,!} *Cii^r9
:m
m
C^i:4iri^0i£^>;^
WV^ViR1»1..
>!•
«a
t2i(rn
| m a o V s m a g ( v g l( i)
|n n a g ! * : m a g ( l g . |
■
l> lg .l
J c o r i j V » c o n K v g ln )
10,000
|R S > 5 0
|v » V 8 i n
R£Rt^Ot»i
^ in d o
1 0 .0 0 0
P ^ 2 fo
-S7.7Sa
P in c ^
-1 1 4 ...
Pr«ffo
M .402
P reiofo
“' f M
2 60
- I .d
■ c ( H iil« o o n j( lg .l)
ilW » (inagV 'fnagV W 'R g) •*■feal(l*conjM^(4>♦ (Rg'm agi'm agli/S
^ |p f e f 3 W « ( m a g V * m a g V V ( 4 * R g ) + ( R g 'i m a g t * m a g l ) / 4
[Pavail« Brtodl)tn(PavaiWl
mpavail2>wlodbm(reat(a'‘conJ(a'))>
PfefW a^m agym agW fB flg) - fe3ll(!»ooniV)f(41 «■<Hg*fflagl‘mag(lf8
^^Pie!2^odbm(raaKb*GOf^(b)))
| P r e f « w t a d b r r j( P w ( ¥ iO
|a = {V+RgWsqi1(«g»
P r»!3to
- l « .l d S
l b = ( y . R g ‘ l )/(2 * s q rt(2 * R g ))
H
P re f3 > n v to (fl} m < P re l3 W )
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
480
Reflected Power
Calculated Utilizing
Gate-Source Harmonic
Voltage and Current Levels
Reflected Power
Simulated in ADS
P a v a il
a.booaK2
3 ,O £ 0 S » !
e iff ix a H ii!
\
I BD.aOD
Pwt
W pff»/er»1D .O D O
R fip o w erslO .D D O
e .ie s
ia,SKo«.tido
2 ,2 ? 5
1 0 ,0 ®
-0 1 0 ,1 :2 2
- I S .B K )
-S 33.1:T 4
sa eo sw
iRIfpow arislO .G O O
O.OM KJKZ
aoxxS H z
s .a o o D tB !
ooG om !
1 2 .0 O S H Z
o m a iD x m
D .016 / - 3 . 0 3 3 8 - 1 4
0 ,1808/ - S .S S 4 8 - 1 8
O .i m 1 6 ,1 8 5 8 - 1 3
0 . 8 0 1 1 - 1 8 0 ,0 0 0
v e in
R P jsaw 4 f» 1 Q ,0 E »
0 .3 9 3 /1 8 0 ,0 0 0
1 .1 S 1 /2 .8 T O E -1 4
0 .4 1 1 / i s o . o a a
8 .0 8 2 / - m a o a
0 , 0 2 2 / S ,0 8 a E -1 3
fm q
0 .tX M 0 H z
3 ,0 0 0 l3 H z
S.OOOQH z
f t ,0 0 8 G « z
1 2 ,® & S Z
P te t2
P te ia
RP(3O!(y*#»fO,0a0
R B p4W 4< «10jD 00
O iB »
- 4 .4 0 2
2 ,2 2 6
- 1 4 .1 8 5
-1 2 .S 8 0
m aeV
...p o w e r s 1 0 .0 8 0
e .3 s e
1D .1 S S
2 .2 ? 8
- 1 4 .1 8 8
- 1 2 .8 8 8
« r^ l
.„ p o w « !» 1 0 ,0 B a
o .r®
1 .1 9 1
0 ,4 1 1
0 .8 B 2
0 .8 ? 2
0 .0 1 0
0 ,0 1 8
oooe
0 .8 0 1
0 .0 0 1
C :\R esearch\sanity checks\pow er_voltage_relationship\pw rsanchk_pavail_ 10dbm _plotsection_l l _ 10_ 03.ai
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
c o n jV
...p o w e r « 1 0 .0 0 0
0 .7 a } /-1 8 0 .0 ! X
1 ,1 9 1 / - 2 ,0 7 & .,
0 4 1 1 / - 1 0 O .D K
0 , 0 6 2 / tS O .IK E
0 ,0 7 2 / - 5 .0 S 9 ...
481
B.i.d.2. Gate-Source Current Waveforms for Case C l (VGO=Vfwd)
0.025
V g = lV p |/2 (C a s e C 1 .1 )
V g = |V p |(C a s e C 1 .2 )
V g = 2 |V p l(C a s e C 1 .3 )
0 .0 2
0.015
<
OT
O)
0 .0 1
0.005
Time (sec)
x IO
-10
Figure B.12. Gate-Source Current W aveforms for Case C l (VGO=Vfwd), at Pin=-7, - 1 ,5 dBm
C :\ 2_ S td y _ Id lz d _ M d l\m o d e lA _ c a se C _ ig sw f_ ll_ 10_ 03.fig
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
482
B.i.d.3. ADS Schematic of 2fo Input Reflector Network Simulation
PARAMETER SWEEP |
1
SWEEP PLAN
1
P ara m S w e ep
Svv,v<3pFian
S w ee p i
Sw pPlanI
S w eepV ar=”L2fo"
S ta rt= 0 S to p = 2 7 S te p = 2 Lln=
S im lnstanceN am e[1]= "H B 1"
U s e S w e e p P la n = y e s
S im ln stan ce N am e [2 ]= ''S P 1 "
S w eep Plana"S w pPlan2"
S im ln stan ce N am e [3 ]=
S lm ln stan ce N am e [4 ]=
S im ln stan ce N am e [5 ]=
— VAR
■ SWEEP PLAN |
Sim 1n s t an c e N am e[6]=
VAR1
SvAiepPlan
Star1=0
R F freq = 3 G H z
Sv»pPlan2
Stop= 90
R Fpow er= 10
S ta rt= 3 3 S to p = 8 7 S te p = 2 Lin=
S tep= 2
R i=50
U se S w e ep P ian =
R dc= 50
S w eepP lan=
R efle cto rs
Rdd=0.1
L6GH z=1.3 2 6 2 9 119243246 H
VG0=-0.3
C 6G H z= 5.30516476972985e-22 F
Vdd=2.5
L 9G H z=8.84194128288307e-7 H
L2fo=53
C 9G H z= 3.53677651315323e-16 F
Ordr=15
O ptions
O p tio n s i
T em p= 25
Topology C heck= y e s
V_RelTol=1e-2
V_AbsTol=1e-4 V
l_RelTol=1e-2
l_A bsTol=1e-8 A
Giv 6AIIW arnings=y e s
M axW arnings=10
HB1
F req [1 ]= R F fre q
O rdert1]= O rdr
M axS hrinkage= 1. Oe-20
ArcM inV alue=-1000000
ArcM axV alue=1000000
U seK ry lov=no
Sw eepV ar="R Fpow er"
S ta rt =-10
S top= 10
S tep=1
Pt=
Ps
Pout
P o u t= p sp ec(v dsout, ),-ldsout.l)
i Probe
i Probs
Z = 50.0 0 h m
1 prcoe
R
R
R3
R =R dd O hm
R =R dc Ohm
“1
50 O hm
P=dbm tow(R F powdT)
F req = R F freq
V DC
SRC1
Vdc=VGO V
y_DC
SRC2
Vdc=Vdd V
Vdc=
lAI
R4
R=5C Ohm
TL2
Z = 50.0 Ohm
Term 2
Num =2
Z=50 Ohm
S-PARAMETERS
S ..P a fam
SP1
S ta rt= 0 GH z
S to p = 7 3 GH z
S te p = 3 GH z
j
C
Hn||
PPI
"-fir
Zin1
Zm 1=i
L=L9GHz
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
R1
R=RI O hm
483
B.i.d.4. Simulations of Idealized Model (ModelA) Using 2fo Input
Reflector
■
"
-
Pin
Pin
Pin
Pin
Pin
=
=
=
=
=
-lO d B m < -35d B
-5d B m < -35d B
OdBm
5dBm
lO dB m
-10
S .-1 5
CO
-20
-25
-30
-35
90
Figure B.13. 3fo CG versus L in lfo for M odelA, Case B1
C :\R ese arch \l_ B _ l U n d rstn d n g N L M ech\B Stdy Idlzd M dls\ii H arm _G en_via_Input_C ond\d H arm onic
R eflection\R flctr_N tw k_S\vps_ 8_ 6_ 03\m odelA _fixed_ 9_ 12_ 03\O pt 2fo_R efl_M odelA _C aseB _R dc_ 50_ C G 3foplot_ 9_ 12_ 03.fig
Reproduced with permission o f the copyright owner. Further reproduction prohibited without permission.
484
a
00
-15
@)
O
-2 0
-25
■
■
-
Pin = -10dBm
Pin = -5dBm
Pin = OdBm
Pin = 5dBm
Pin = lOdBm
-30,
Lin2fQ (deg)
Figure B.14.3fo CG versus Lin2fo for M odelA, Case C l
C ;\R ese a rc h \l_ B _ l U ndrstndng N L M ech\B Stdy Idlzd M dls\ii H arm _G en_via_Input_C ond\d H arm onic
R eflectton\R flctr_N tw k_S w ps_ 8_ 6_ 03\m odelA _fixed_ 9_ 12_ 03\O pt 2fo_R efl_M odelA _C aseC _R dc_ 50_ C G 3foplot_ 9_ 12_ 03.fig
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
485
B.i.d.5. Simulations of Idealized Model (ModelA) Using 3fo Input
Reflector
Case A l:
-40
-50
S'
-60
T3
o
-80
-90
- Pin = -10dBm (< -1 0 0 d B )
- Pin = -5dBm
■■ Pin = OdBm
Pin = 5dBm
- Pin = lOdBm
-1 0 0 ,
Figure B .15.2fo Conversion Gain versus 3fo Input Reflector Length for M odel A, C ase A l
C :\R ese arch \l_ B _ l U ndrstndng N L M ech\B Stdy Idlzd M dls\ii H arm _G en_via_Input_C ond\d H arm onic
R eflection\R flctr_N tw k_S w ps_ 8_ 6_ 03\m o d e lA fix e d _ 9_ 12_ 03\O pt 3fo_R efl_M odelA _C aseA _R dc_ 50_C G 2foplot_ 9_ 12_ 03.fig
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
486
-50
-55
-60
-1 0
-65
S '-15
-75
-80
-25
-85
-30
— No Refl.
■— Refl. Opt 2fo
Refl. Opt 3fo
-90
-35
-95
-1 0 0
-10
-10
Pin (dBm)
10
Pin (dBm)
-1 0
Pin (dBm)
Figure B.16. Pin vs. Conversion Gain for M odel A, Case A l - Comparison o f Response with: No
Input R eflector (solid); 3fo Reflector Optimized for 2fo Output (dashed) 3fo Reflector O ptim ized for
3fo Output (dotted)
C :\R e se a rc h \l_ B _ l U n d rstn d n g N L M ech\B Stdy Idlzd MdlsMi H arm _G en_via_Input_C ond\d H arm onic R eflection\m odeIA P inP out
w _ 3fo refl 2_1 l_ 03\m odelA _C aseA _PinPout_com p_plot_ 2_ l l_ 03.tig
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
487
Case B l:
00
S
Pin = -10dBm
-Hi-- Pin = -5dBm
Pin = OdBm
Pin = 5dBm
Pin = lOdBm
-1 0
^ -1 5
CD
O
•fN ..
<
-2 0
-25,
L 'n sfo ( d e g )
Figure B .1 7 .2 fo Conversion Gain versus 3fo Input Reflector Length for M odel A, C ase B l
C :\R e se arch \l_ B _ l U ndrstndng N L M ech\B Stdy Idlzd MdlsMi H arm _G en_via_Input_C ond\d H arm onic
R eflection\R flctr_N tw k_S w ps_ 8_ 6_ 03\ m odelA _fixed_ 9_ 12_ 03\O p t 3fo_R efl_M odelA _C aseB _R dc_ 50_ C G 2foplot_ 9_ 12_ 03.fig
•
Pin = OdBm
Pin = 5dBm
Pin = lOdBm
wlOMohm, Pin=OdBm
(§)
-25
-30
Figure B .1 8 .3 fo Conversion Gain versus 3fo Input Reflector Length for M odel A, Case B l
C :\R e se arch \l_ B _ l U n d rstn d n g N L M ech\B Stdy Idlzd M dls\ii H arm _G en_via_Input_C ond\d H arm onic
R eflection\R flctr_N tw k_Sw ps_ 8_ 6_ 03\
m od elA _ fix ed _ 9_ 12_ 03\O p t 3fo_ R efl_ M o d elA _ w l 0M ohm _C aseB _R dc_ 50_ C G 3foplot_ 9_ 15_ 03.fig
Reproduced with permission o f the copyright owner. Further reproduction prohibited without permission.
488
-10
£
@
(3
O
No Refl.
Refl. Opt 2fo
Refl. Opt 3fo
-30
-20
-35
-40
-25
-10
-10
■-10
Pin (dBm)
Pin (dBm)
Pin (dBm)
Figure B.19. Pin vs. Conversion Gain for M odel A, Case B l - Comparison o f R esponse with: No
Input R eflector (solid); 3fo R eflector Optimized for 2fo Output (dashed) 3fo R eflector O ptim ized for
3fo Output (dotted)
C :\R e se a rc h \l_ B _ l U ndrstndng N L M ech\B Stdy Idlzd M dls\ii H arm _G en_via_Input_C ond\d H arm onic R eflection\m odelA PinP out
w _ 3fo refl 2_1 l_ 03\m o d e lA _ C ase B _ P in P o u t_ c o m p j 5lot_ 2_ l l _ 03.fig
CaseCl:
GO
a
CM
-1 0
Pin = -1 OdBm
Pin = -5dBm
Pin = OdBm
Pin = 5dBm
Pin = lOdBm
CD
O
-15
-2 0 .
10
20
30
40
50
60
Lingfo (deg)
Figure B.20. 2fo Conversion Gain versus 3fo Input Reflector Length for M odel A, C ase C l
C :\R e se arch \l_ B _ l U n d rstn d n g N L MechVB Stdy Idlzd M dls\ii H arm _G en_via_Input_C ond\d H arm onic
R eflection\R flctr_N tw k_S w ps_ 8_ 6_ 03\ m odelA _fixed_ 9_ 12_ 03\O p t 3fo_R efl_M odelA _C aseC _R dc_ 50_ C G 2foplot_ 9_ 12_ 03.fig
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
489
-1 0
GO
2 . -2 0
■B
CO
-30
O
O
— Pin = -1 OdBm
■— Pin = -5dBm
Pin = OdBm
—• Pin = 5dBm
• - Pin = lOdBm
-40
-50,
Figure B .21.3fo Conversion Gain versus 3fo Input Reflector Length for M odel A, Case C l
C :\R e se arch \l_ B _ l U ndrstndng N L M ech\B Stdy Idlzd MdlsMi H arm _G en_via_Input_C ond\d H arm onic
R eflection\R flctr_N tw k_S w ps_ 8_ 6_ 03\ m odelA _fixed_ 9_ 12_ 03\O p t 3fo_R efl_M odelA _C aseC _R dc_ 50_ C G 3foplot_ 9_ 12_ 03.fig
No Refl.
Refl. Opt 2fo
Refl. Opt 3fo
-10
m -15
■o
?o -20
-14
-30
-16
-35
-18
-20
■-10
-10
Pin (dBm)
10
Pin (dBm)
-40
-10
Pin (dBm)
Figure B.22. Pin vs. Conversion Gain for M odel A, Case C l - Comparison o f Response with: No
Input R eflector (solid); 3fo Reflector Optimized for 2fo Output (dashed) 3fo R eflector O ptim ized for
3fo Output (dotted)
C :\R e se a rc h \l_ B _ l U ndrstndng N L M ech\B Stdy Idlzd MdlsMi H arm _G en_via_Input_C ond\d H arm onic R eflection\m odelA PinP out
w _ 3fo refl 21 l _ 03\m odelA _C aseC _P inPout_com p_plot_ 2_ l 103.fig
Reproduced with permission o f the copyright owner. Further reproduction prohibited without permission.
490
B.ii. Harmonic Generation via Various Output Conditions
B.ii.a. Output Load and Bias - Appendix Data:
B.ii.a.l. ADS Schematic of Model B
Model:
B
Ids vs. Vds:
Knee
Ids vs, Vgs:
Linear
Dgs:
Resistive
Dgd:
Resistive
Ggs:
X
Cgd:
X
[ 3 VA R
Constants
ldss=.025
V p = -.6
Vki=0.5
[ 3 VA R
Port_Voltages
Vgs=_v1
Vds=_v2
Vgd=_v3
Vov=Vki
Port_Currents
Ids =if Vds > 0 ttien if Vds>Vki then Idsa else Idsb end if else 0 endlf
ldsa=if (Vgs>=Vp) then Idslin else 0 endif
ldsb=if (Vgs>=Vp) then ldslin*VdsA/ki else 0 endif
ldslin=ldss*( 1-(V gsA /p))
D
Num=2
Num=
^0D 3P
SDD3P1
l[1,0]=0
l[2,0]=lds
l[3,0]=0
"cnF
.
1 Port
Num=3
Figure B.23. ADS Schem atic o f M odel B
Reproduced with permission o f the copyright owner. Further reproduction prohibited without permission.
491
B.ii.a.2. ADS Schematic of Model C 2
]VAR
0 3 VAR
C „2
Model:
Ids vs. Vds: K nee and BD
Linear
Ids vs. Vgs:
Dgs:
Resistive
Dgd:
Resistive
Ggs:
X
Cgd:
X
Port_Voltages
Vgs=_v1
Vds=_v2
Vgd=_v3
Vov=Vki
Constants
ldss=.025
Vp=-.6
Vki=0,5
g ]V A R
Port_Currents
Ids =lf Vds > 0 ttien If Vds>Vki ttien Idsa else Idsb endlf else 0 endlf
ldsa=lf (Vgs>=Vp) ttien Idslln else 0 endlf
ldsb=lf (Vgs>=Vp) then ldslln*VdsA/kl else 0 endlf
ldslln=ldss*(1-(VgsA/p))
es_B D 5
Num=2
Num=1
'w m r ~
SDD3P1
l[1,0]=0
l[2,0]=lds
l[3,0]=0
Num=3
Figure B.24. ADS Schem atic o f M odel C_2
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
492
Diode_res_BD5
This is a diode model which uses a logic switch
to turn current on and off. It includes reverse break
down voltage, Vrbd.
EJVAR
B
VAR
Constants
Port_Voltage_Definitions
Vd= v1
lss=1e-13
Vrbd=-5,1
Vfwd=0
Rd=0.01
E l VAR
Rdb=10
Gb=1/Rdb
G=1/Rd
o Port
A
Num=1
■<I>
O T lP
SDD1P1
l[1,0]=ld
Port
C
Num=2
C[1]=
Port Currents
ld=if Vd > Vfwd then G*(Vd-Vfwd) else (if Vd < Vrbd then Gb*(Vd-Vrbd) else 0 endif) endif
Figure B.25. ADS Schematic o f Dgj Diode M odel Used in M odelC_2
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
493
B.ii.a.3. ADS Simulation Schematic for Output Load and Bias Study
PW?AMCTER SWEEP
’8rBmt>'»veep
\
»
\ \
li
—----
HB2
M axO rdei^4
Freq[1]=R Ffreq GHz
O rder[1l= 25
S ta rt= p in s ta rt
S to p = p in sto p
S te p = p in s te p
Pt=
ln F ile= " g u ess2 "
U se !n F ile= n o
O u tF ile = " g u ess2 "
U se O u tF ile= n o
S V r'e e p P la n /
SwliPlany^
P t= 2 ^ p /
Pt=16{^{
V AR2
R Fpow er^S
R Ffreq=3
R l=50
R g=50
R d c= 5 0
R dd=0.1
VG0=-O.O1
V dd= 2.5
C pln g = 1 0 0
V AR3
startfreq = 3 QHz
sto p fre q = 9 GHz
freq step = 1 GHz
folow=1
fohigh= 6
fo step = 1
pin sta rt= -1 0
p in s to p = 1 0
pin ste p = 1
^HHarm
arm oonscBaia^
n ic B a ia n c J s
Sw SepI
/
I
S w ee tiV a r= "R r'
\
S im ln s\^ n c e N |tffie [1 l= "H 6 2 '
S im ln s ta f^ e N 'a m e [ 2 ]=
\
S im ln stan ch b N am e[3 ]=
|
S im in s t^ c e h J a m e [ 4 ] =
\
S im ln § ^ n ce N a'tT ie[5 ]=
t
S im |H s t a n c e N a m ^ ] =
\
^9ft=
^op=
LSteKL
I VAR
Iffll V AR
1^1
O p tio n s i
T em p= 25
T Opel ogy C h eck = y es
V _ R e lT o l= 1 e -2
V _ A b s T o l= 1 e -4 V
L R e lT o l= 1 e -2
l_ A b s T o l= 1 e -8 A
Q v e A IIW a m in g s = y e s
M axW am ings= 10
P fc
P fc2
P slm fo = w to d b m (p fc (\o u t,0 ,ld so u t.i,{1 }»
P sim 2 fo = w to d b m (p fc (v o u t,0 ,ld 8 o u t.i,^ }))
P sim 3fo= w todbm (pfc(vout.0.ldsout.i,{3}))
CGfo = P s im fo - R F pow er
C G 2fo = P s im 2 fo - R F p o w er
C G 3fo = P s im 3 fo - R F p o w er
-p 7^
HSpSC
P m eas
P o u t= p s p e c ( v d s o u t,0 ,4 d s o u t.i)
P refg = p sp ec (v re fg ,0 ,lrefg .i)
P fc3
Prefsfo=w todbm (pfc(vrefg,0,lrefg.l,{1}))+ C plng
P refs2 fo * w to d b m (p fc (v re fg ,0 ,lrefg .i,p }))+ C p ln g
P refs3fo=w todbm (pfc(vrefg,0.lrefg.i,{3}))+ C plng
Pt=§6 \
PJ??50 '%
lt1seSweepPf^<
R
R4
R =50 Ohm
('oupiCfSmpi
P,
R =R dc
I
C 0U P 1
C o u p lin g = C p ln g d ^ g
M VSW R1=1.
C V S W R 1= 1.
L o s s 1 = 0 .d B
D ire c t1 = 1 0 0 d B
P0RT1
V DC
Num=1
i ►SR C 1
'Z =50 Ohm
^V dc=V G O V
P =dbm tow (R Fpow ffl
P ro b e
Id s o u t
I lout
dolA w ikoi'trnoui
R3
R =R dd Ohm
V [)(;
►
SRC2
V dcaV dd V
F req= R F freq GHz
V dc=
Figure B.26. ADS Simulation Schem atic for Output Load and Bias Study
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
R
R1
R=RI Ohm
494
B.ii.a.4. Conversion Gain Responses of Model B, Cases A l through C3.
20
20
—
•
CaseA!
CaseA2
CaseA3
V
-a
V
(3 -10
0 -1 0
o
-15
-1 5
\
-2 0
-2 0
-2 0
-25
-25
-25
-30
-1 0
10
Pin (dBm)
V
-30
-30
-1 0
10
Pin (dBm)
-1 0
Pin (dBm)
Figure B.27. Pin vs. Conversion Gain for M odel B, Cases A l, A2 and A3
C :\R ese a rc h \l_ B _ l U ndrstndng N L M ech\B Stdy Idlzd MdlsMii H arm G en v ia O utput C onditions\a O utp u t L oad and
B ias\com p_m odel_plots_ 9_ 25_ 03\m o d e lB _ c a s e A l_ 2_ 3_cgplot_ 9_ 25_ 03.fig
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
495
—
o
\ - --
m
-5
■o
T3
V
-1 0
CaseBI
CaseB2
CaseBS
S -1 0
o -15
-2 0
-2 0
-2 0
-25
-25
-25
-30
-30
-30
Pin (dBm)
Pin (dBm)
Pin (dBm)
Figure B.28. Pin vs. Conversion Gain for M odel B, Cases B l, B2 and B3
C :\R e se arch \l_ B _ l U ndrstndng N L M ech\B Stdy Idlzd M dls\iii H arm G en v ia O utput C onditions\a O utp u t L oad and
B ias\com p_m odel_plots_ 9_ 25_ 03\ m o d elB _ caseB l_ 2_ 3_cgplot_ 9_ 25_ 03.fig
—
o
■a
CaseCI
CaseC2
CaseCS
■a
-1 0
c5 -1 0
6 -15
-2 0
-2 0
-2 0
-25
-25
-25
-30
-30
Pin (dBm)
10
Pin (dBm)
-30
Pin (dBm)
Figure B.29. Pin vs. Conversion Gain for M odel B, Cases C l, C2 and C3
C :\R ese a rc h \l_ B _ l U ndrstndng N L M ech\B Stdy Idlzd MdlsMii H arm G en v ia O utput C onditions\a O u tp u t L oad and
B ias\com p_m odel_plots_ 9_ 25_ 03\m o d e lB _ ca seC l_ 2_ 3_ c gplot_ 9_ 25_ 03.fig
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
496
B.ii.b. Output Bias Network - Appendix Data:
B.ii.b.l. Theoretical Calculation of Vds Waveforms Using Matlab
The following program text is an add-on to the Matlab program shown in Appendix
B.i.a.2 (page 457). It uses the Ids harmonic data to calculate the Vds harmonics and then
plugs both the Ids and Vds harmonic data into the Fourier Series to extract the Ids and
Vds waveforms.
%Matlab Program “pavailjout_tim e_output.m ”
Vdsn = -Idsn.*Rl;
VdsDC = Vdd - IdsDC*Rdd;
%Calculate harmonic output voltages
%Calculate DC output voltage level
%Calculate Time Domain Waveforms
tm = [0:.le-10:7e-10];
V g s t m = zeros(length(Vg),length(tm));
I d s t m = zeros(length(Vg),length(tm));
Vds_tm = zeros(length(Vg),length(tm));
for k=l :length(Vg)
forn=l;harm
Ids_tm(k,:) = Ids_tm(k,:) + Idsn(n,k)*cos(w*n*tm);
Vds_tm(k,:) = Vds_tm(k,:) + Vdsn(n,k)*cos(w*n*tm);
end
Vgs_tm(k,:) = Vg(k).*eos(w*tm);
Ids_tm(k,:) = Ids_tm(k,;)+IdsDC(k);
Vds_tm(k,:) = Vds_tm(k,;)+VdsDC(k);
end
V g s t m = VGO+Vgs_tm;
%Output Pin vs. Pout data into an ascii file
%Setup Pin and Pout vectors
indat = transpose(tm);
outdatl = transpose(V gstm );
outdat2 = transpose(Idstm );
outdatS = transpose(V dstm );
output = [indat, outdatl, outdat2, outdatS];
%This is the header for the power data, arranged in columns
pwrtitle = '%Time Vgs@Pinl Vgs@Pin2 Vgs@Pin3 Ids@Pinl Ids@Pin2 Ids@Pin3 Vds@ Pinl Yds@Pin2
Vds@Pin3'; %Power out file
%Convert power data to text format
outputtext = num2str(output);
%initialize output file array
matrix=[];
matrix = strvcat(pwrtitle, outputtext);
title = '%Theoretical Time Waveforms for ModelA, CaseBI, with Rdd equal to 0.1 ohms';
%Input title information
output = strveat(title,title2,title3, titled, titleS, matrix);
%Enter output filename inbetween single quote marks 'filename'
dlmwrite('modelA_caseBl_Rdd_50_calc_wfdata_zoom_9_30_03.txf,output,')');
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
497
B.ii.c. nfo Output Reflector - Appendix Data:
B.ii.c.l. ADS Schematic of nfo Output Reflector Simulations
m :
HARMONIC BALANCE
1
I
IEoptions
HB1
SwpPlanY'.,^,..''''
I
iec
Optionsi
Start=1 5t®^='f3'^tep=2 Lin^
Temp=25
Pout
|
Topology 0 heok=y e s Pout=pspec(v dsout, 0, -Idsout. Usg&jfeepPlan=ye^'».^
rSvskecPJsuH'lSiKReiaDZ^.'-vi
V_RelTol=1e-2
V_AbsTol=1e-4 V
-•S.WEEPPLAN
l_RelTol=1e-2
PARAMETERSWEEP |
sw eep tjan
i
l_AbsTol=1e-8 A
SwpPlan2''-.j,-'''"
i
Giv eAIIWarnings=y e s Sweepi
Start=57,S«p='87,Step=2 Lir^
MaxWarnlngs=10
SweepVar="Lfo"
U seSw^epPlan=yes‘-'-._
I
Sim InstanceN am e[1 ]="H B l"
mVAR
,iS5©epEto:§ys!cPJ8i-na'l!;:iU
Sim
I
nstanceName[2]="SP1"
*^AR1
Sim InstanceNam e[3]=
RFfreq=3 GHz
VAR
Sim InstanceName[4]=
aw ee p K ia n
1
RFpower=10
Reflectors
SimlnstanceNam e[5]=
S w p P la n i'''-...,-'''
I
Rl=50
L6GHz=1.32629119243246e-7 H Rdc=50
Sim InstanceN am e[ 6]=
Start=93,Sto'p='l7a^Step=2 Lir|=
C6GHz=5.30516476972985e-15 F n^-n 1
Start=1
U seSw 6epPlan=
!
L9GHz=8.84194128288307e-7 H
„
Stop=179
«S^.eBPJSJl=-..................
C9GHz=3.53877651315323e-16 F ^ . . .
Step=2
L3GHz=2.65258238486492e-8 H . f 53
C3GHz=1.06103295394597e-13 F
Freq[1]=RFf req
Order! 1]=0rdr
MaxShrinkage=
ArcMinValue=
ArcMaxValue=
UseKry lov=no
SweepVar="RFpower"
Start=-10
Stop=10
Step=1
Pt=
Other=
Idsout
R2
PORT1
Num=1
Z=50 Ohm
R=RI Ohm
I 9GHzrefl
jL=L3G H z
Ohm
lc = C 3 G H z ^ R=Rdd
” -'
R=Rdc Ohm
1Tone
LIN
TL1
Z=50.0 Ohti
E=Lfo
b ta s i
'■obeF=3 GHz
b iasT
X2
T
V DC
V DC
USRCI
P=dbmtow(RFpo^')^‘*‘^"''°°
!^10 MOtirh
Vdc=Vdd V
Freq=RFfreq
- ^ = ..............
S-PARAMETERS
R
:R4
R=50 Ohm
TL2
Z=50.0 Ohm
A fcLfo
IS f e §
GHz
pL=L3GHz
Lc =C3GH z
Term
|Term2
Num=2
Z=50 Ohm
P afarfi
SP1
Start=0 GHz
S top=73 GHz
Step=3 GHz
in
ZInl
Zm1=zin(S22,PortZ2)
Figure B.30. ADS Schematic o f nfo Output Reflector Simulations
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
498
B.ii.c.2. Case B l, Simulations Utilizing Output fo Reflector
0.03
0.03
0.03
0.02
0.02
0.02
“ 0.01
TD
~ 0.01
-0.8 -0.6 -0.4 -0.2
- -ill
~ 0.01
0
time (sec)
V g s (V )
,-10
V d s (V)
x IO '
x IO
—
-0.8 -0.6 -0.4 -0.2
Vgs (V)
0
No Refl
Wi t h Refl
0
2
4
V ds (V)
Figure B.31. W aveform s for M odel C_2, Case B l, Comparison o f Response W ith fo R eflector for
Optim um 2fo CG and W ithout Reflector. Pin = -7dBm
C :\R e s e a rc h \l_ B _ l U ndrstndng N L M ech\B Stdy Idlzd MdlsMii H arm G en v ia O utput C onditions\d O utput nfo H arm
R efl\com parison_plots_ 3_ 5_ 03\m odelC - 2_caseB _w fcom p_pin_m 7_o p t 2fo _ 3_ 6_ 03.fig
Figure B.31 shows the waveform plot for case B l and an input power o f -7 dBm, and
compares the response when no reflector is used and when the fo reflector is optimized
for 2 fo conversion gain.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
499
B.ii.c.3. Case C l, Simulations Utilizing Output fo Reflector
5
* * * * W N n m n n n iN H n
U W U W i m ilW U U M M H Ii
_
-5
^ -1 0
o
o
—
15
Pin
Pin
Pin
Pin
Pin
=
=
=
=
=
-lO d B m
-SdBm
OdBm
SdBm
lO dB m
-2 0
I
-25
i
20
40
60
/ ;
:
100
80
Lout^^ (deg)
120
140
160
180
Figure B .3 2 .2 fo Conversion Gain vs. Output Reflector Length (Loutfo), Case C l (VGO=Vfwd,
Vdd=Vdd„id)
C :\R ese a rc h \l_ B _ l U n d rstn d n g N L M ech\B Stdy Idlzd MdlsMii H arm G en v ia O utput C onditions\d O utput nfo H arm
R efl\m odeIC _ 2_ n e w lo o k _ 10_ 8_ 03\m odelC _ 2_caseC _L outfosw p_C G 2fo _ p Io t_ 10_ 9_ 03.fig
Figure B .32 shows the 2fo conversion gain versus Loutfo response for Case C l
(VGO=Vfwd, Vdd=Vddmid), for several input power levels. A maximum o f around 4.5dB
is reached for an output fo reflector length Loutfo o f 91 degrees at an input power o f lOdBm.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
500
5
—
—^
0
------------------- -------------------
.. i
-5
m
S -1 0
CO
_______
/
#;
i;
i\
\ w -------
*.» ;
® -1 5
•
O
O
-2 0
■!
1H
-✓
___________
20
40
f
1-
_________
60
-------------------
i V
• i
V '
F
i
-25
Pin = lOdBm
................... -
------------------
-30
Pin = -1 OdBm
Pin = -SdBm
Pin = OdBm
1
1
:
-
■—“ —“
L
i.
100
80
Lout^^ (deg)
120
140
160
180
Figure B .3 3 .3 fo Conversion Gain vs. Output Reflector Length (Loutfo), Case C l (VGO=Vfwd,
Vdd=Vdd„id)
C :\R ese a rc h \l_ B _ l U ndrstndng N L M ech\B Stdy Idlzd M dls\iii H arm G en v ia O utput C onditions\d O u tp u t n fo H arm
R efl\m odelC _ 2_ n e w lo o k _ 10_ 8_ 03\m odelC _ 2_caseC _L outfosw p_C G 3fo _ p lo t_ 10_ 9_ 03.fig
Figure B.33 shows the 3fo conversion gain versus Loutfo response for Case C l
(VGO=Vfwd, Vdd=Vddmid), for several input power levels. A maximum o f around 3dB
is reached for an output fo reflector length Loutfo o f 89 degrees at an input power o f lOdBm.
Reproduced with permission o f the copyright owner. Further reproduction prohibited without permission.
501
0.03
0.03
0.03
0.02
0.02
0.02
“ 0.01
■o
“ 0.01
■■ 0.01
time (sec)
,-10
xIO'
-10
xIO'
Vds (V)
No Refl
— With Refl
■0.6
-0.4
-0.2
Vgs (V)
0
0
2
Vds (V)
4
Figure B.34, W aveform s for M odel C_2, Case C l, comparison of response with fo reflector for
optimum 2fo CG and without reflector. Pin = -7dBm
C :\R e se a rc h \l_ B _ l U ndrstndng N L M ech\B Stdy Idlzd MdlsMii H arm G en v ia O utput C onditions\d O utput nfo H arm
R efl\com parison_plots_ 3_ 5_ 03\m odelC - 2_caseC _w fcom p_pin_m 7_opt 2fo_ 3_ 8_ 03.fig
Figure B.34 shows the waveform plot for case C l and an input power o f -7 dBm, and
compares the response when no reflector is used and when the fo reflector is optimized
for 2fo conversion gain.
R e p ro d u c e d with perm ission of th e copyright owner. Further reproduction prohibited without permission.
502
(a) Lout.
= O ptfor 2fo CG n 91deg
10
(b) Loul^^i = Opt fon2fo C G
89deg
5
0
-5
£CO-10
-15
CG w / Refl
Pout w /R e fl
CG no Refl
-20
G G w /R e fI
——• Pout w /R e fl
. . . . . CG no R efl
-25
-5
0
Pin (dBm)
5
-30
-10
-5
0
5
10
Pin (dBm )
Figure B.35. Conversion Gain vs Input Power Comparison for Case C l (VGO=Vfwd, Vdd=Vddmid)
C;\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\iii Harm Gen via Output Conditions\d Output nfo Harm
Refl\modelC_2_newlook_10_8_03\modelC_2_caseC_Pinswp_2fo3fo_plot_10_9_03.fig
Figure B.35(a) shows the response at the second harmonic. The figure shows an
improvement in the maximum 2fo conversion gain from -IdB (without the reflector) to
4.5dB (with the optimized reflector at Loutfo=91deg). Figure B.35 (b) compares the 3fo
conversion gain versus the input power when the optimum output reflector is used to
when no reflector is used. For the third harmonic, the optimum output reflector (at
Loutfo=89deg) results in a maximum 3dB conversion gain compared to a maximum o f 11 dB with no reflector.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
503
O ptfot|2fo M P =^91 deg
(a) Lout
CG w / Refl
-■ Pout w /R e fl
M P w /R e fI
CG no R efl
MP no Refl
-5
0
Pin (dBm )
(b) Lout ' = Opt fori 3fo M P ^ 89 deg
—
5
-5
CG w / Refl
P out w /R e fl
MR w /R e fl
CG no R efl
MP no Refl
0
Pin (dBm )
5
Figure B.36. M ultiplier Power vs Input Power Comparison for Case C l (VGO=Vfwd, Vdd=Vddmid)
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd MdlsMii Harm Gen via Output Conditions\d Output nfo Harm
Refl\modelC_2_newlook_10_8_03\modelC_2_caseC_Pinswp_2fo3fo_wMG_plot_10_9_03.fig
Figure B.36 shows the multiplier power versus the input power when the output
reflector length Loutfo has been set to optimize the multiplier power, compared to the
response when no reflector is used. Figure B.36(a) shows that a maximum 2fo multiplier
power o f -IdBm is reached for an input power o f -lOdBm and an output reflector length
o f 91 degrees. At this point o f maximum 2fo multiplier power, a 2fo conversion gain o f
4.5dB is achieved with a corresponding -5.5 dBm output power.
Figure B.36(b) shows that a maximum 3fo multiplier power o f IdBm is reached for an
input power o f 2dBm and an output reflector length o f 89 degrees. At this point o f
maximum 3fo multiplier power, a 3fo conversion gain o f -0.5dB is achieved with a
corresponding l.SdBm output power.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
504
B.ii.c.4. Case A2, Simulations Utilizing Output nfo Reflector
Pin = -1 OdBm
Pin = -SdBm
Pin = OdBm
Pin = SdBm
Pin = lOdBm
-10
©)
20
40
60
80
100
120
140
160
180
Lout^^ (deg)
Figure B .37.2fo Conversion Gain vs. Output Reflector Length (Loutfo), C ase A2 (VGO=Vmid,
Vdd=Vki)
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd MdlsMii Harm Gen via Output Conditions\d Output nfo Harm
Refl\modelC_2_ne wlook_ 10_8_03\modelC_2_case A2_Loutfoswp_CG2fo_plot_ 10_9_03.fig
Figure B.37 shows the 2fo conversion gain versus Loutfo response for Case A2
(VGO=Vmid, Vdd=Vki), for several input power levels. A maximum o f around 2 .IdB is
reached for an output fo reflector length Loutfo o f 91 degrees at an input power o f lOdBm.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
505
lOdBm
5dBm
OdBm
5dBm
lOdBm
60
80
100
Lout^^ (deg)
120
140
180
Figure B.38. 3fo Conversion Gain vs. Output Reflector Length (Loutfo), Case A2 (VGO=Vmid,
Vdd=Vki)
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\iii Harm Gen via Output Conditions\d Output nfo Harm
Refl\modelC_2_newlook_10_8_03\modelC_2_caseA2_Loutfoswp_CG3fo_plot_10_9_03.fig
Figure B.38 shows the 3fo conversion gain versus Loutfo response for Case A2
(VGO=Vmid, Vdd=Vki), for several input power levels. A maximum o f around -8.2dB is
reached for an output fo reflector length Loutfo o f 1 degree at an input power o f -1 dBm.
Reproduced with permission o f the copyright owner. Further reproduction prohibited without permission.
506
U)
73
0.03
0.03
0.02
0.02
0.01
0.01
-0.6
-0.4
-0.2
0
0.03
2
4
time (sec)
Vgs (V)
6
0
0.5
1
V d s (V)
No RefI
With RefI
-0.6
-0.4
-0.2
V g s (V)
0
0 .5
1
Vds (V)
Figure B,39. W aveform s for M odel C_2, Case A2, comparison o f response with fo reflector for
optimum 2fo CG and without reflector. Pin = -7dBm
File: C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\iii Harm Gen via Output Conditions\d Output nfo Harm
Refl\comparison_plots_3_5_03\modelC-2_caseA2_wfcomp_pin_ra7_opt2fo_3_6_03.fig
Figure B.39 shows the waveform plot for case Cl and an input power o f -7 dBm, and
compares the response when no reflector is used and when the fo reflector is optimized
for 2fo conversion gain.
Reproduced with permission o f the copyright owner. Further reproduction prohibited without permission.
507
10
10
(a) Loutj^ = Optfoi 2fo CG = 91 deg
(b) L o u t' = Opt fo( 3fo C G =f 1deg
5
5
.
CG w / RefI
P o u tw / RefI
CG no RefI
0
0
-5
-5
---K
>2 -10 ---------- V
CN
-15
-15
% -------\
-20
-25
-20
------ C G w /R e fi
P o u tw /R e fi
. . . . . C G no Refi
---1----------- 1---------30
1 0 - 5
0
5
Pin (dBm )
-25
10
-3 0
-5
0
5
Pin (dBm )
Figure B.40. Conversion Gain vs Input Power Comparison for Case A2 (VGO=Vmid, V dd=Vki)
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd MdlsNiii Harm Gen via Output Conditions\d Output nfo Harm
Refl\modelC_2_newlook_10_8_03\modelC_2_caseA2_Pmswp_2fc3fo_plot_10_9_03.fig
Figure B.40(a) shows the response at the second harmonic. The figure shows an
improvement in the maximum 2fo conversion gain from -4.3dB (without the reflector) to
2.1dB (with the optimized reflector at Loutfo=91deg). Figure B.40(b) compares the 3fo
conversion gain versus the input power when the optimum output reflector is used to
when no reflector is used. For the third harmonic, the optimum output reflector (at
Loutfo=ldeg) results in a maximum -8.2dB conversion gain compared to a maximum o f 12dB with no reflector.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
508
(b) Lout^ = Opt for 3fo M P
(a) Loutj = Opt for 2fo MP =i 91 deg
—— CG w/ Refi
P o u tw /R e fi
—
M P w /R e fI
■•■•I CG no Refi
MP no Refi
-4 0
-1 0
-5
0
Pin (dBm)
f
1 deg
—
CG w / R efi
——■ P o u tw /R e fi
r ^
MP w / R efi
•
CG no R efi
MP no R efi
5
10
-5(
-10
JL
-5
0
Pin (dBm )
5
10
Figure B.41. M ultiplier Power vs Input Power Comparison for Case A2 (VGO=Vmid, Vdd=Vki)
C :\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd MdlsMii Harm Gen via Output Conditions\d Output nfo Harm
Refl\modelC_2_newlook_10_8_03\modelC_2_caseA2_Pinswp_2fo3fo_wMG_pIot_l0_9_03.fig
Figure B.41 shows the multiplier power versus the input power when the output
reflector length Loutfo has been set to optimize the multiplier power, compared to the
response when no reflector is used. Figure B.41 (a) shows that a maximum 2fo multiplier
power o f -2.4dBm is reached for an input power o f -6dBm and an output reflector length
o f 91 degrees. At this point o f maximum 2fo multiplier power, a 2fo conversion gain o f
1.8dB is achieved with a corresponding -4.2 dBm output power.
Figure B.41(b) shows that a maximum 3fo multiplier power of-16.2dBm is reached
for an input power o f IdBm and an output reflector length o f 1 degree. At this point o f
maximum 3fo multiplier power, a 3fo conversion gain o f -8.6dB is achieved with a
corresponding -7.6dBm output power.
Reproduced with permission o f the copyright owner. Further reproduction prohibited without permission.
509
B.ii.c.5. Case A3, Simulations Utilizing Output nfo Reflector
Pin
Pin
Pin
Pin
Pin
120
140
=
=
=
=
=
-1 OdBm
-5d B m
OdBm
5dBm
lO dB m
160
180
Lout^^ (deg)
Figure B .4 2 .2 fo Conversion Gain vs. Output Reflector Length (Loutfo), Case A3 (VGO=Vmid,
Vdd=Vrbd)
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\iii Harm Gen via Output Conditions\d Output nfo Harm
Refl\modelC_2_newlook_10_8_03\modelC_2_caseA3_Loutfos\vp_CG2fo_plot_10_9_03.fig
Figure B.42 shows the 2fo conversion gain versus Loutfo response for Case A3
(VGO=Vmid, Vdd=Vrbd), for several input power levels. A maximum o f around 5.4dB
is reached for an output fo reflector length Loutfo o f 91 degrees at an input power o f 1OdBm.
Reproduced with permission o f the copyright owner. Further reproduction prohibited without permission.
510
—
100
120
Pin
Pin
Pin
Pin
Pi n
=
=
=
=
=
-lO d B m
-5 d B m
OdBm
5dBm
lO d B m
160
180
Loutj^ (deg)
Figure B .43.3fo Conversion Gain vs. Output Reflector Length (Loutfo), Case A3 (VGO=Vuiid,
Vdd=Vrbd)
C:\Research\I_B_l Undrstndng NL Mech\B Stdy Idlzd Mdlsliii Harm Gen via Output Conditionstd Output nfo Harm
Refl\modelC_2_newlook_10_8_03\modelC_2_caseA3_Loutfoswp_CG3fo_plot_10_9_03.fig
Figure B.43 shows the 3fo conversion gain versus Loutfo response for Case A3
(VG0=Vmid, Vdd=Vrbd), for several input power levels. A maximum o f around -7dB is
reached for an output fo reflector length Loutfo o f 1 degree at an input power of-2dBm .
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
511
0.03
0.02
in
•o
0.01
1
1
1
1
1
1
y
1
1
1/
1
1
1
1
y
!
-0.6 -0.4 -0.2
Vgs(V)
xIO
1
0
1
0.03
0.03
_ 0 .0 2
0.02
“ 0.01
0.01
1
1
-------- 1—
—t
2
4
6
time (sec)
0
—
-0.6 -0.4 -0.2
Vgs (V)
Vds (V)
No Refi
With Refi
0
Vds (V)
Figure B.44. W aveform s for M odel C_2, Case A3, comparison of response with fo reflector for
optimum 2fo CG and without reflector. Pin = -7dBm
C :\R e se arch \l_ B _ l U n d rstn d n g N L M ech\B Stdy Idlzd M dls\iii H arm G en v ia O utput C onditions\d O utput nfo H arm
R efl\com parison_plots_3_5_03\m odelC -2_caseA 3_\vfcom p_pin_m 7_opt2fo_3_6_03.fig
Figure B.44 shows the waveform plot for case A3 at an input power o f -7 dBm, and
compares the response when no reflector is used and when the fo reflector is optimized
for 2fo conversion gain.
Reproduced with permission o f the copyright owner. Further reproduction prohibited without permission.
512
(a) Loutjj = Opt for 2fo C G
(a) Lout I = Opt foil 3fo C G 4 1deg
91 deg
C G w /R e fI
P o u tw /R e fi
. . . . . CG no Refi
-10
CO
-15
-15
-20
-25
-10
-20
— C G w /R e fi
-■ P o u tw /R e fi
. . . CG no Refi
-3 0
-2 5
10
-10
Pin (dBm)
-3 0
-10
Pin (dBm )
Figure B.45. Conversion Gain vs Input Power Comparison for Case A3 (VGO=Vmid, Vdd=Vrbd)
C:\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\iii Harm Gen via Output Conditions\d Output nfo Harm
Refl\modelC_2_newlook_10_8_03\modelC_2_caseA3_Pinswp_2fo3fo_plot_10_9_03.fig
Figure B.45(a) shows the response at the second harmonic. The figure shows an
improvement in the maximum 2fo conversion gain from -0.9dB (without the reflector) to
5.4dB (with the optimized reflector at Loutfo=91deg). Figure B.45(b) compares the 3fo
conversion gain versus the input power when the optimum output reflector is used to
when no reflector is used. For the third harmonic, the optimum output reflector (at
Loutfo=ldeg) results in a maximum -7dB conversion gain compared to a maximum o f 10.4dB with no reflector.
Reproduced with permission o f the copyright owner. Further reproduction prohibited without permission.
513
(a) L o u t' = O p tfo (2 fo M P ^ 91 deg
(b) Lout,l = Opt fof 3fo M P r 1 deg
C G w /R e fI
P o u tw /R e fi
M P w /R e fI
■■■■■ CG no R efi
MP no R efi
-1 0
-5
0
Pin (dBm )
——
^
5
10
-5
C G w / R efi
P o u tw /R e fi
M P w /R e fI
CG no R efi
MP no R efi
0
Pin (dBm )
5
10
Figure B.46. M ultiplier Power vs Input Pow er Comparison for C ase A3 (VGO=Vmid, V dd=Vrbd)
C :\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd MdlsMii Harm Gen via Output Conditions\d Output nfo Harm
Refl\modelC_2_newlook_10_8_03\modelC_2_caseA3_Pinswp_2fo3fo_wMG_plot_10_9_03.fig
Figure B.46 shows the multiplier power versus the input power when the output
reflector length Loutfo has been set to optimize the multiplier power, compared to the
response when no reflector is used. Figure B.46(a) shows that a maximum 2fo multiplier
power o f -2.2dBm is reached for an input power o f -6dBm and an output reflector length
o f 91 degrees. At this point o f maximum 2fo multiplier power, a 2fo conversion gain o f
4.1dB is achieved with a corresponding -1.9dBm output power.
Figure B.46(b) shows that a maximum 3fo multiplier power o f -16.IdBm is reached
for an input power o f -2dBm and an output reflector length of 1 degree. At this point o f
maximum 3fo multiplier power, a 3fo conversion gain o f -V.ldB is achieved with a
corresponding -9.IdBm output power.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
514
B.iii. Harmonic Generation via Various input and Output
Conditions - Appendix Data
B.iii.a. Idealized Design #1 - Appendix Data
B.iii.a.l. Derivation of Equation for 2fo Conversion Gain for Case B1
Calculation o f the Conversion Gain as a Function o f the AC Gate Input Voltage
Magnitude (Vg):
1. Device is Biased at Pinchoff Voltage (CaseBl)
V
= -V
2. Calculate Conduction Angle
(j) = cos“'
F
(j) - cos ' ( 0 ) = = 90 deg
3. Calculate Second Harmonic Output Current Component:
21 p cos((2))sin(n(zJ)-nsin(jzJ)cos(/t^z))
n=2
n
7t
6
5 K
4. Now, based on the a piece-wise linear xtr response, we can calculate Ip versus Vg. See
MATLAB program pavail_pout.m in Appendix B.i.a.2, page 457.
F
^ p
L et
^ dss
+F
Ffw d - Fp
L^jwd +
= 0 , F^o =
5. Plug Ip into Equation for Ids(2):
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
515
T
=
'
=
'^ ^ dss^ g
3 ;r
3;z-F
o _ V d d ^ n id z lK
6. Rl is Calculated Using the Load-Line:
And it gives a second harmonic drain voltage swing (Vd(2)) o f (Vdd-Vki).
7. Calculate Pout and Pavail
-F „
1
Pavail/o = -----^
2 4i?„
8. Finally, we can calculate the second harmonic conversion gain:
{ y d d „ ^ - V ^ ) I j,/^
-3 F ,
g
=■
-3 Fp F"
g
IJ I
2 4P
SRg (V dd^jj
C G .2fo
^ki)^dss
- 3 VpVg
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
516
B.iii.a.2. MathCAD 2fo CG Calculation for Case B1
File: C:\Research\l_B_l Undrstndng NL Mech\B Stdy Idlzd Mdls\iv Harm Gen via Input
and Output\jj_ideal_doub_l\ jj_ideal_doub_l_design_5_24_03.mcd
Calculation of 2fo CG and Optimum Load RIopt:
Input transistor parameters, pinchoff voltage (Vp) and generator resistance (Rg)
R g := 5 0
V p := -0 .6
^fwd ■ ®
Idss := 0.025
Vk:=0.5
Vrbd^=4.5
Choose pinchoff bias, and gate voltage required to reach peak drain current:
Vgq:=-0.6
V„ := 0.6
%-bd +
Vdd='
Vdd:=-
Calcuiate aperture time and re-calc conduction angie using my calculations
(See pavaii_pout.m, and Ciark and Hess book:
^on:=—
2-n
0 := acos
ton = '
,
)
„ 180
v„
0
I
=1
Calculate peak output current from transistor Ids equation (Jessis caic - pavail_pout.m):
"^G0+
■ ^dss
I^p I^
Ip = *
^’^fwd“ ’^p
I’^fwdl + I’^p Ij
Reproduced with permission o f the copyright owner. Further reproduction prohibited without permission.
517
Calculate output harmonic current (Clark and Hess)
, ^
c o s ( 0 ) - s in ( n - 0 ) - n s in ( 0 ) c o s ( n '0 )
Id(n) :=
/■ o
\
for n > 1
n-(n^ - l ) - ( l - c o s ( 0 ) )
Id (2) = .
Id(3) = >
Id(4) = '
^^(2)—
=■
P
Calculate Pavail (into an open circuit), required to give Vg;
1
2 4 Rg
P a v a il-- —
Pavail = •
PavaildB tn-
^
'^^°^'^” ^(Pavail)
w tod bin(x) := lOlog(x-lOOO)
PavaildB m
'
Calculate Rl
Vdd-Vk
R, :=
’
Rl = 1
Id(2)
Calculate Pout:
Pout2 •
2
d d (2 )
Pout2
'
Pout2dB m — ''4odbm (PQyi.2)
P out2dB m “ '
Conversion Gain of Design (Assuming no addition by networks at other harmonics)
— Pout2dB m ~ P availdB m
“ '
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
518
B.iii.a.3. ADS Schematic for 2fo CG Simulation
File: Jj ideal doub l.dsn
CQ
HB1
FreqI1)*RFfreq
0rder(11*0rdr
SweepVar= "RF power"
SweepPlan=
Start*
Stop*
Step*
R *-.4 5 8
Pfc2
Psimfo=wtodbm(pfc(vout,0,lout,i,{1}))
Psitn2f0 * wt odbm(pfc(vout, 0,1out.i, {2}))
Pfc3
Prefsfo“ Wtodbm(pfc(vrefg,0,lrefg.i,{1}))+Cplng
Prefs2fo»wtodbm(pfc(vrefg,0,lrefg.i,{2}))+Cplng
Prefs3fo*wtodbm(pfc(vrefg,0,!refg.i,{3}))+Cplng
Psim3fo*wtoctom(pfc(vout,0,loijt.i,{3}))
CGfo = Psimfo - RFpower
CG2fo * Psim2fo - RFpower
CG3fo = PsimSfo - RFpower
AR
aV
VAR2
RFfrecpS GHz
Reflect ore
L6GH z= 1.326291192432466-7 H
C6GHz*5,30516476972985e-15 F
L9GHZ*8.841941282883070-7 H
C9GHZ*3,536776513153238-16 F
L3GHz*2.65258238486492e-7 H
C3GHz=1.061032953945976-14 F
L12GHz=6.63145596216231e-7 F
C12GHZ* 2.^2582384864926-16 F
y
Swe^l
RN50
Rdc=50
Rdd=0.1
Ordr*25
RFpowera-1
V G 0= -0,6
Vdd * 2.5
CpIng^lOO
Sv^iPlanl /
S w e e ^ b n * "Sw pPlyfl"
Sweep\Ar= "RFpos*^’
SimI nstaiKV^agw( 1]=“FB I
Sknl retancei^i^el23 •=
SimI nstanc^9 ^W ^ e (^ *
Pt=-^s /
P ty t
P^fe-10
\
^#dseSweepPlan*
SimI n s ta ^ e N a m ^ *
Sknt n|tanceName(5^
SimU%tarKeN3me[€|*
Sjert=450
\
vStO|^:2000
'
pttl'
L»Z-09ei*933084S6 pH
R*50 Ohm
----
Ids out
[ Pfoly,
COUPI
Couping=Cplng dB
MVSWR1=1.
C V S W R 1 *!
Loss1=0. dB
^
R2
mm
R=RdcOhnP'«*'-''“''B
P-jTom
3Bi-^l
|9^rlfl
jr - -
R
R3
R=RddOhm
t^CQQ
ZRef=50. Ohm
^but
Ip o r t i
Num*1
I pSRC1
'z» 5 0 O h m
P * dbmtow(RF pcwerf
FrecpRFfreq
Vdc»
m
S-PARAMETERS
SP1
S tart*O G H z
Stop=21 GHz
R=RIOhm
Vi
SRG2
Vdc«Vdd V
s
Z ini
Zm1*zln<S22,PortZ9
Zm2=zin(S33,PortZ^
Step*.1 GHz
' L5^.4>3glSte«14^ pH
ITorai
R tsisiT
R7
X8
R=50 Ohm
R4
R=Rdc Ohm
tcscaafl*:
Term2
Num=2
Z *5 0 Ohm
Num=3
Z *5 0 O h m
0
pLytSOHz
t^C3s£li:
itenfre
R*RI Ohm
lcC»C ■
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
519
B.iii.a.4. MathCAD 3fo CG Calculation for Case A1
C :\R esearch\l_B_l Undrstndng NL Mech\B Stdy Idlzd MdlsMv Harm Gen via Input and Output\jj_ideal_trip_l\
jj_ideal_trip_5_25_03,mcd
Calculation of Third Harmonic Conversion Gain and Optimum Load for Ideal Tripler Design # '
input transistor parameters, pinchoff voitage (Vp) and generator resistance (Rg):
V p := -0 .6
R g := 5 0
Vrbd:=4-5
Vk:=0.5
W
^=0-025
fo-310^
Choose pinchoff bias, and gate voitage required to reach peak drain current:
V „ := .563
\b d + \
^dd •=----- ;
V.
oc
^GO-Vp
^
Y
Y
'^ fw d
'^p
^dd - •
V.„ = i
ac
V
V„„:=------ 2
ac Y^ . _ V
fw d
v„- = i
'^p
Reproduced with permission o f the copyright owner. Further reproduction prohibited without permission.
520
a :=
l-V d c ^
acos
^ac
b :=
acos
"o
J
V ac
Ip = '
Ip •- Idss
2-V,
Idsa(") •=
n-7t
(-l)"'^'-sin(n-cOo-b) - sin(n coQ-a)
\
\
V,
Idsb(i') :=-----—— (-l)"sin[(n - l)-coQ-b] - sin[(n - l)-coQ-a]
(n - l)-7t
ac
Idsc*-”^■ (n + l)-7t •j^(-l)"sin[(n + l)-C0 Q-bJ - sin[^(n + l)-coQ-aJ
Idsd('i) ■=
Ids(a)
2
sinfn-coo-a)
n-7i
^
^
Ip (ldsal-’^^ Idsbl-*^^ Idsc^^^
Idsdl^^^)
Ids(2) = '
Ids^2) = ■
Ids(4) = '
Calculate Pavail (into an open circuit), required to give Vg;
avail'
1
I*avail '
2 4 R„
I’a v a i l d B m " ^ ° ‘II”^ ( l ’avail)
wtodbm(x) := lO log(x lOOO)
W
I*availdBm
'
Calculate Rl
^dd Rl-
ds (3 )
R, = i
I
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
521
Calculate Pout:
^out3
^dd~^k
~2
I
I
^out3dB m ■“ "^°*^^™(^out3)
_
^out3 “ '
^out3dB m “ '
Conversion Gain of Design (Assuming no addition by networks at other harmonics)
^out3dB m “ ^ availdB m
^ 9 3 fo “ '
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
522
B.iii.b. Idealized Design #2 - Appendix Data
B.iii.b.l. Comparison of 2fo Conversion Gain Responses for Case B1
LiHafo = 50 deg
No 2 fo Input R efi
■a
-10
-15.
95
100
Loutfo (deg)
Figure B .4 7 .2 fo CG vs Loutfo Response for Design 2, Case B l: (-) with 2fo Input R eflector, (— ) w/o
2fo Input Reflector
C :\R esearch\l_B _l Undrstndng NL M ech\B Stdy Idlzd Mdls\iv Harm Gen via Input and
O utput\jj_ideaI_doub_2\m odelB _sim _li_14_03\caseBl_m odeIB_doub2_Loutfosw p_com pplot_ll_I4_03.fig
Figure B.47 shows the simulated 2fo CG versus output fo reflector offset length Loutfo
for an input power o f -10 dBm utilizing model B (which has a linear and saturation region
o f operation, but no reverse breakdown region). The solid curve shows the 2fo CG
versus Loutfo response when the optimum 2fo input reflector (with optimum offset length
from the idealized design 2, case B l, presented in Section 3.iv.b.2 on page 280) is used.
The dashed curve shows the same response with the 2fo input reflector disabled. As the
figure shows, the responses are identical. This occurs because when there is no feedback
in the transistor (which is the case for model B, which has no feedback mechanism, i.e.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
523
no gate-drain diode) the 2fo input and fo output reflector lengths are independent o f each
other.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
524
R e fe r e n c e s
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