close

Вход

Забыли?

вход по аккаунту

?

Additive manufacturing and analysis of highfrequency interconnects for microwave devices

код для вставкиСкачать
ADDITIVE MANUFACTURING AND ANALYSIS OF HIGH
FREQUENCY INTERCONNECTS FOR MICROWAVE DEVICES
BY
ELICIA K. HARPER
A.A. PHYSICS: BUNKER HILL COMMUNITY COLLEGE (2012)
A.A. MATHEMATICS: BUNKER HILL COMMUNITY COLLEGE (2012)
B.S. ELECTRICAL ENGINEERING: UNIVERSITY OF MASSACHUSETTS
LOWELL (2015)
SUBMITTED IN PARTIAL FULFULLMENT OF THE
REQUIREMENTS FOR THE DEGREE OF MASTER OF SCIENCE
DEPARTMENT OF ELECTRICAL AND COMPUTER
ENGINEERINOING
UNIVERSITY OF MASSACHUSETTS LOWELL
Signature of
Author:
Signature of Thesis Co-Supervisor:
Name Typed: Craig Armiento
Signature of Thesis Co-Supervisor:
Name Typed: Alkim Akyurtlu
Signatures of Other Thesis Committe^Membj
Committee Member Signature:
Name Typed: Chris Laighton
-
9f :
5/s/ / ?..
ProQuest Number: 10633346
All rights reserved
INFORMATION TO ALL USERS
The quality of this reproduction is dependent upon the quality of the copy submitted.
In the unlikely event that the author did not send a complete manuscript
and there are missing pages, these will be noted. Also, if material had to be removed,
a note will indicate the deletion.
ProQuest
Que
ProQuest 10633346
Published by ProQuest LLC(2017). Copyright of the Dissertation is held by the Author.
All rights reserved.
This work is protected against unauthorized copying under Title 17, United States Code.
Microform Edition © ProQuest LLC.
ProQuest LLC
789 East Eisenhower Parkway
P.O. Box 1346
Ann Arbor, Ml 48106-1346
ADDITIVE MANUFACTURING AND ANALYSIS OF HIGH
FREQUENCY INTERCONNECTS FOR MICROWAVE DEVICES
BY
ELICIA K. HARPER
ABSTRACT OF A THESIS SUBMITTED TO THE FACULTY OF THE
ELECTRICAL AND COMPUTER ENGINEERING IN PARTIAL
FULFULLMENT OF THE REQUIREMENTS
FOR THE DEGREE OF MASTER OF SCIENCE
UNIVERSITY OF MASSACHUSETTS LOWELL
2017
Thesis Supervisor: Alkim Akyurtlu, Ph.D.
Professor, ECE Department
Thesis Supervisor: Craig Armiento, Ph.D.
Professor, ECE Department
ABSTRACT
Wire bond interconnects have been the main approach to interconnecting
microelectronic devices within a package. Conventional wirebonding however offers
little control o f the impedance o f the interconnect and also introduces parasitic inductance
that can degrade performance at microwave frequencies. The size and compactness o f
microchips is often an issue when it comes to attaching wirebonds to the microchip or
other components within a microwave module. This work demonstrates the use o f
additive manufacturing for printing interconnects directly between bare die microchips
and other components within a microwave module.
A test structure was developed consisting o f a GaAs microchip sandwiched
between two alumina blocks patterned with coplanar waveguides (CPW). A printed
dielectric ink is used to fill the gap between the alumina CPW blocks and the GaAs chip.
Conductive interconnects are printed on top o f the dielectric bridge material to connect
the CPW traces to the bonding pads on the GaAs microchip. Simulations o f these
structures were modeled in the electromagnetics simulation tool by ANSYS, high
frequency structure simulation (HFSS), to optimize the printed interconnects at 1-40 GHz
(ANSYS Inc., Canonsburg, PA). The dielectric constant and loss tangent o f the simulated
dielectric was varied along with the dimensions o f the conductive interconnects. The best
combination o f dielectric properties and interconnect dimensions was chosen for
impedance matching by analyzing the insertion losses and return losses. A dielectric ink,
which was chosen based on the simulated results, was experimentally printed between the
two CPW blocks and the GaAs chip and subsequently cured. The conductive
interconnects were then printed with an aerosol jet printer, connecting the CPW traces to
the bonding pads on the GaAs microchip.
The experimental prototype was then measured with a network analyzer and the
measured data were compared to simulations. Results show good agreement between the
simulated and measured S-parameters. This work demonstrates the potential for using
additive manufacturing technology to create impedance- matched interconnects between
high frequency ICs and other module components such as high frequency CPW
transmission lines.
ACKNOWLEDGEMENTS
I would like to thank my parents for their love and support; I wouldn’t be who I am today
with you.
I would like to thank my fiancee, Darin, for always believing in me. Thank you for all of
your love and support over the past 8 years.
I would like to my brother, Tyler, for inspiring me to be a worthy role model.
I would like to thank my advisors, Professor Alkim Akyurtlu and Professor Craig
Armiento. I am truly lucky to have had the opportunity to work with you both.
I would like to thank my ‘Raytheon advisors,’ Chris Laighton and Sue Trulli. Thank you
for all o f your guidance over the past year. It has been a very rewarding experience.
I would like to thank Mary Herndon from Raytheon Co. for all o f her help and support o f
this work.
I would finally like to thank my colleagues at the Raytheon UMass Lowell Research
Institute (RURI) for all o f your help, advice and friendship. Thank you Mahdi
Haghzadeh, Ehsan Hajisaeid, Kyle Homan, Carolyn Reistad, Arcan Dericioglu, Nolan
Grant, Dima Volkov, Jarrod Vaillancourt, Brian Morrison, James Wigglesworth, James
Benedict, Ed Kingsley, Denise Radkowski, Kristin Bourgault and all others I had the
pleasure o f working with.
Elicia Harper
May 5,2017
TABLE OF CONTENTS
L IS T O F F IG U R E S ...................................................................................................................................................vii
I. IN T R O D U C T IO N .................................................................................................................................................. 1
II. B A C K G R O U N D T H E O R Y A N D IN F O R M A T IO N ...............................................................................3
II. 1 C o n v e n t i o n a l M e t h o d s o f F o r m i n g M i c r o c h i p In t e r c o n n e c t s ........................................... 3
II. 1.1 C o n v en tio n al In terco n n ect M e th o d s.................................................................................................4
II. 1.2 P ro b lem s w ith C o n v en tional W ire b o n d s........................................................................................ 6
II.2 P r i n t e d E l e c t r o n i c s a n d A d d i t i v e M a n u f a c t u r i n g T e c h n i q u e s ........................................ 8
11.2.1 T w o D im en sio n al P rin tin g T e c h n o lo g ie s .......................................................................................9
II. 1.2 P rin ted a n d A d d itiv ely M an u factu red In te rc o n n e cts................................................................ 11
III. A N A L Y S IS .......................................................................................................................................................... 13
I I I .l E l e c t r i c a l A n a l y s i s ............................................................................................................................................. 14
III. 1.1 M o d el F a m ilia rity ................................................................................................................................15
III. 1.2 P rin ted In terco n n ect O p tim iz a tio n ................................................................................................ 17
III. 1.3 P illow M a te ria l.................................................................................................................................... 22
III. 1.4 V ariab le G ro u n d H e ig h t................................................................................................................... 24
III.2 M u l t i p h y s i c s S i m u l a t i o n A p p r o a c h ............................................................................................26
111.2.1 T h erm al M ech an ical A n a ly sis........................................................................................................ 27
111.2.2 S tructural M ech an ical A n a ly s is .....................................................................................................31
IV . E X P E R IM E N T A L S E T U P ...............................................................
34
IV . 1 M a t e r i a l C h a r a c t e r i z a t i o n o f P r i n t e d M a t e r i a l s ................................................................. 3 4
IV . 1.1 D ielectric C h a ra c te riz a tio n ....................
35
IV . 1.2 C o n d u ctiv e In k C h a ra c te riz a tio n ..................................................................................................43
IV. 1.3 T herm al C o n d u ctiv ity C h aracterizatio n o f D ielectric I n k ................................................... 45
IV . 1.4 T h erm al E x p an sio n M easu rem e n t o f D ielectric I n k .............................................................. 46
IV .
1.5 E lasticity M e asu rem en t o f P rin ted I n k s .................................................................................. 50
IV .2 P r i n t i n g
and
M e a s u r e m e n t E q u i p m e n t a n d T e c h n i q u e ....................................................52
IV .2.1 T w o A lu m in a C o p la n a r W a v eg u id e s...........................................................................................52
IV .2.2 C o p la n a r W av eg u id e to G aA s M ic ro strip .................................................................................. 54
V. R E S U L T S ............................................................................................................................................................... 58
V . l M a t e r i a l C h a r a c t e r i z a t i o n R e s u l t s .....................................................................................................5 9
V .1.1 E lectrical C h aracterizatio n R e s u lts ................................................................................................59
V .1.2 M ech an ical S im u latio n R esu lts w ith M easu red D ielectric T herm al an d S tructural
P ro p e rtie s.............................................................................................................................................................64
V .2 M e a s u r e d R e s u l t s o f P r i n t e d In t e r c o n n e c t s ................................................................................. 6 8
V .2.1 T w o A lu m in a C o p la n a r W a v e g u id e s ............................................................................................68
V .2.2 C o p la n a r W av eg u id e to G aA s M ic ro strip ................................................................................... 73
VI. C O N C L U S IO N ...................................................................................................................................................77
V II. F U T U R E W O R K .............................................................................................................................................78
V III. L IT E R A T U R E C I T E D .................................................................................................................................79
IX . B IO G R A P H IC A L S K E T C H O F A U T H O R ............................................................................................84
LIST OF FIGURES
F ig u re 1: S im p lified p ro cess o f ball b o n d in g pro cess (left) and w edge b o n d in g pro cess (right),
tak en from [16]. A u to b all b o n d in g u ses T C , T S o r U S energy to bond ball fo r bond to bond
pad. W edge b o n d in g u ses U S en ergy and co m p ressio n to bond w ire to su rfa c e .......................... 5
F ig u re 2: O p to m ec A ero so l Je t system set-up and process. T ak en from [2 1 ]........................................11
F ig u re 3: 3 D In terco n n ect stru ctu re m eth o d co n sists o f an IC die atop a su b strate w h ere a
d ielectric ram p is p rin ted on the side o f a die, upon w hich the co n d u ctiv e tra ce is printed.
From [3 0 ]............................................................................................................................................................. 12
F ig u re 4: M o d el im ag e o f c o p lan ar w av eg u id e co n n ectin g to a m icro ch ip w ith standard w ire bond
in terco n n ects (left), an d c o p lan ar w av eg u id e co n n ectin g to a m icro ch ip w ith printed
in te rc o n n e c ts.......................................................................................................................................................14
F ig u re 5: H F S S M odel o f tw o c o p lan ar w av eg u id es attached w ith w ire-bonds fo r m odel
v e rific a tio n .......................................................................................................................................................... 15
F ig u re 6: Im age o f th e rib b o n b o n d interco n n ects b etw een the tw o co p la n ar w av eg u id es used for
m odel v erificatio n . T ak en w ith K ey en ce V H X -5 0 0 0 series digital m icro sco p e (Itasca, IL,
U S A )..................................................................................................................................................................... 16
F ig u re 7: R etu rn losses ( S n ) o f c o p lan ar w av eg u id es co n n ected w ith w ire-b o n d s: m easu red data
an d sim u lated re su lts........................................................................................................................................16
F ig u re 8: S ix skin d ep th s o f silv er nan o -p article ink versus freq u en c y ....................................................18
F ig u re 9: R etu rn and in sertio n losses fo r m odel o f G aA s m icrochip co n n ected to tw o c o p lan a r
w av eg u id es w ith w ire -b o n d s.........................................................................................................................19
F ig u re 10: R etu rn losses fo r perm ittivity sw eep o f dielectric o f m aterial in m odel w ith G aA s
m icro ch ip co n n ected to tw o c o p lan ar w av eg u id es w ith p rin ted in terconnects. R etu rn losses
sh o w n fo r d ielectric co n stan t o f 2, 3, 4, 11, 12, 20, 30 and 4 0 . .....................................................21
F ig u re 11: R etu rn losses for perm ittivity sw eep o f dielectric o f m aterial in m odel w ith G aA s
m icro ch ip co n n ected to tw o co p la n ar w av eg u id es w ith p rinted in terconnects. D ielectric
c o n stan t v alues o f 2, 3, and 4 (sh o w n in blue, red and green, resp ectiv ely ) co m p ared to
baselin e case w ith rib b o n bond in terconnects (sh o w n in p in k ).........................................................21
F ig u re 12: H F S S m o d el o f C P W -G aA s-C P W w ith silicon pillow m aterial u n d ern eath the p rinted
d ielectric m aterial an d cross section o f bu ild -u p o f pillow m aterial, d ielectric m aterial and
p rin ted co n d u ctiv e tra c e s............................................................................................................................... 23
F ig u re 13: M odel o f cross section o f p rinted in terco n n ect section w ith ground (re d ) printed on
p illo w m a te ria l.........................
24
F igure 14: H FS S m odel o f C P W -G aA s-C P W w ith silicon pillow m aterial, th en a co n d u ctiv e
g ro u n d plane, th en co n tro lled d ielectric, th en signal and m ore d ielectric (left). C ross section
o f b u ild -u p o f pillow m aterial, co n d u ctiv e ground, d ielectric m aterial and p rin ted signal line
w ith m o re d ielectric printed on top (rig h t)...............................................................................................25
F ig u re 15: M o d elled S n p aram eters o f the stru ctu re show n in F igure 14 co m p arin g rib b o n bonds
an d printed, em b ed d ed m ic ro strip -in terc o n n ects...................................................................................26
F igure 16: Im p o rted h eat g en eratio n boundary co n d itio n ap plied to the n o n -electrically
co n d u ctiv e bod ies in the m odel (left), and im ported h eat flux boundary co n d itio n s ap plied to
th e e lectrically co n d u ctiv e faces in the m odel (rig h t).......................................................................... 28
F ig u re 17: H e a t m ap o f S tead -S tate T herm al sim u latio n w ith bottom face o f m odel heated to
150°C .....................................................................................................................................................................29
F ig u re 18: T o tal h eat flu x m ag n itu d e from S teady-S tate th erm al w ith b ottom face o f m odel h eated
to 150°C ............................................................................................................................................................... 29
F ig u re 19: H eat m ap o f S tead -S tate T h erm al sim u latio n w ith o u tp u t o f G aA s m icro ch ip h eated to
150°C .................................................................................................................................................................... 30
F ig u re 20: T o tal h eat flux m ag n itu d e from S teady-S tate th erm al w ith o u tp u t o f G aA s m icro ch ip
h eated to 150°C..................................................................................................................................................31
F ig u re 21: T o tal d efo rm atio n m axim um 0 .14m m w ith tem p eratu re o f bo tto m o f en tire stru ctu re
se t to 150°C .........................................................................................................................................................32
F ig u re 22: S tress intensity o ccu rs at boundary betw een dielectric and C P W and G aA s w ith
B o tto m S urface H eated
to 150°C ................................................................................................................33
F ig u re 23: T o tal d efo rm atio n m axim um o f 0 .04m m w ith o u tp u t side te m p eratu re boundary
co n d itio n set to 150°C ..................................................................................................................................... 33
F igure 24: Stress in ten sity resu lts w ith G aA s m icrochip o u tp u t side tem p e ra tu re boundary
c o n d itio n set to 150°C..................................................................................................................................... 34
F ig u re 25: E tch ed cy lin d rical c a p a cito r (left) and H F S S im age o f cy lin d rical c a p a c ito r (rig h t)
w h ere R|„ = 2 20 ii m an d RoU, = 600 u m ................................................................................................ 36
F ig u re 26: E q u iv alen t circu it m o d el o f the device u n der te st (D U T ) filled w ith a d ielectric
m aterial, i.e., air o r m aterial u n d er te st (M U T ).......................................................................................38
F ig u re 27: E x tracted c o m p lex d ielectric p ro p erties from sim u lated results o f D U T filled w ith a
M U T v ersus in p u t d ielectric profiles p red efin ed fo r the M U T : (left) perm ittiv ity , (rig h t) loss
ta n g e n t.................................................................................................................................................................. 41
F ig u re 28: W av eg u id e set-u p fo r dielectric m easu rem en t (left) and thin film sam p le o f cured
dielectric ink (rig h t)......................................................................................................................................... 43
F ig u re 29: P rin ted sam p le o f silv er n ano-particle ink used fo r te st (left) and p ro filo m ete r
m ea su re m e n t im age o f h eig h t o f printed sam p le (right). T he sam p le abo v e w as p rin ted w ith
10 p asses o f th e prin ter, m e asu rin g 18.4 m icro n s in h e ig h t............................................................... 44
F ig u re 30: F o u r p o in t p ro b e used fo r cond u ctiv ity m e a su re m e n ts............................................................ 44
F ig u re 31: H e a te r line fo r 3 -o m eg a th erm al conductivity m ea su rem en t w ith o u t dielectric m aterial.
...............................................................................................................
45
F ig u re 32: H e a te r line fo r 3 -o m eg a th erm al con d u ctiv ity m easu rem en t w ith d ielectric m aterial. 46
F ig u re 33: T A In stru m en ts T G A . A sm all am o u n t o f uncu red sam p le gets loaded into th e sm all
pans an d is h eated. T h e T G A m easures the chan g es in w eig h t in th e pan as a fu n ctio n o f
te m p e ra tu re ......................................................................................................................................................... 47
F ig u re 34: T G A resu lts o f u n cu red C reative M aterials d ielectric. R esu lts show th e p erce n t w eig h t
left o f th e original w eig h t o f th e m aterial across th e te m p eratu re p ro file .....................................48
F ig u re 35: D ielectric sam p le in D M A fixture fo r m easu rin g C T E ............................................................50
F ig u re 36: C reativ e M aterials cu red d ielectric sam ple in Q 800 D M A by T A In stru m en ts fo r
ten sile te s t...........................................................................................................................................................51
F igure 37: L octite E C I1 0 1 1 sam p le in Q 800 D M A by T A In stru m en ts for ten sile te s t.................... 52
F ig u re 38: T h ree sets o f tw o a lu m in a C P W s end to end m o u n ted in co p p er-m o ly su b strate 10 m ils
apart. V iscous D ow 3145 silicone pillow m aterial dep o sited betw een C P W s w ith syringe.
P o ly im id e K ap to n tap e used to prev en t silicone from cu rin g onto co n d u ctiv e p a d s .................53
F ig u re 39: P a ru n an o -p article silv er ink in terco n n ects p rinted on C reativ e M aterial d ielectric ink
w ith O p to m ec A ero so l Je t Printer. E ach set o f in terconnects p rin ted w ith sev en passes o f
c o n d u ctiv e in k ....................................................................................................................................................54
F ig u re 40: A lu m in a C o p la n a r w av eg u id e and G aA s th ru m icro ch ip m o u n ted on co p p er-m o ly heat
sp re a d e r su b strate, 15 m il apart. L ay ers o f K apton tape stack ed used as dam m a te ria l
55
F ig u re 41: D ow 3 1 4 0 P illo w m aterial d ep o sited in gap, th en C reativ e M aterials d ielectric
d ep o sited ato p it an d c u re d ............................................................................................................................ 56
F ig u re 42: S n p aram eters o f G aA s m icro ch ip b etw een tw o co p la n ar w av eg u id es 15 m il apart.
T w o p rin ted b onds sh o w n in b lue, one p rinted bond show n in re d ................................................. 57
F ig u re 43: C u red silv er n an o -p article ink p rin ted on d ielectric, co n n ec tin g G aA s an d C PW . S ingle
sig n al line p rin ted ra th e r th an tw o ...............................................................................................................58
F ig u re 44: M easu red d ielectric co n stan t (left) and loss ta n g en t (rig h t) o f C reativ e M aterials ink,
av erag ed o v er results from th ree p rinted sa m p le s................................................................................. 60
F ig u re 45: M easu red d ielectric co n stan t w ith N IS T m eth o d versus p resen ted m eth o d (left) and
m easu red loss tan g en t w ith N IS T m eth o d versus presen ted m ethod (rig h t) o f C reativ e
M aterials M U T .................................................................................................................................................. 62
F ig u re 46: W eig h ted av erag es o f cond u ctiv ity results fo r v arious c u rin g m eth o d o f th e P aru silv er
nan o -p article in k ............................................................................................................................................... 63
F ig u re 47: In sertio n losses (S 12 and S21) and return losses (S I 1 an d S22) fo r m odel o f G aA s
m icro ch ip c o n n ected to tw o c o p lan ar w av eg u id es w ith p rinted in terconnects on top o f
d ielectric w ith c o n sta n t d ielectric co n stan t (red ) and m easured dielectric co n sta n t (b lu e).... 64
F ig u re 48: 3 -O m eg a v o ltag e v ersus fre q u e n c y .................................................................................................65
F ig u re 49: D isp lacem en t v ersu s T em p eratu re curve fo r C T E m easu re m e n t......................................... 66
F ig u re 50: S tress-S train C u rv e for C reativ e M aterials d ie le c tric ............................................................... 67
F ig u re 51: S tress-S train C u rv e fo r L o ctite E C I 1011 silv er in k ................................................................. 68
F igure 52: C o p la n a r w av eg u id es w ith p rinted in terconnects (to p ) an d H F S S m odel o f th e co p la n ar
w av eg u id es w ith p rin ted in terco n n ects..................................................................................................... 69
F ig u re 53: M easu red and sim u lated S n results w ith a co n stan t dielectric co n sta n t o f four, and
sim u lated resu lts w ith th e m easu red d ielectric co n stan t results fo r th e tw o c o p lan ar
w av eg u id es en d to e n d ....................................................................................................................................69
Figure 54: P ro file o f d ielectric ink as v iew ed from th e side. T his im age show s how th e dielectric
ink is n o t flat, but is like tw o peaks w ith a valley betw een the p e a k s.............................................70
F ig u re 55: C ro ss sectional view o f the tw o alu m in a C P W sam ples w ith a p rin ted in te rc o n n e c t.
T h e d ielectric w as red raw n to b etter m atch m easu rem en t taken w ith p ro filo m e te r.................. 70
F ig u re 56: Im ag e o f p ro to ty p e, w hich show s the dielectric ink co v erin g p art o f th e ed ges o f the
g o ld traces o n C P W . T h is is sig n ifican t b ecau se the length o f the p rin ted traces atop the
d ielectric affects th e in d u ctance o f the in terc o n n e cts..........................................................-................ 71
F ig u re 57: Im ag e o f p ro to ty p e, w hich show s the p rin ted in terco n n ect n o t co n n ected to gold trace
on C P W (left). M odel o f second in terco n n ect taken o u t to a c co u n t fo r the d isco n n ec t o f one
o f th e printed in te rc o n n e c ts...........................................................................................................................72
F ig u re 58: M easu red and sim u lated S n results w ith a nom inal dielectric co n stan t o f four, and
sim u lated resu lts w ith the m easured dielectric co n stan t results used in m od ified m o d e l
72
F ig u re 59: In terco n n ects printed b etw een a C P W and G aA s m icro ch ip ................................................. 73
F ig u re 60: C P W to G aA s m icro ch ip w ith rib b o n bond in te rc o n n ec ts......................................................74
F ig u re 61: S n and S 21 resu lts o f C P W to G aA s m icrochip. S im ulated vs. m easu red w ith p rin ted
in terco n n ects vs. m easu red
w ith
ribbon b o n d s.......................................................................74
F ig u re 62: S 22 and S 12 resu lts o f C P W to G aA s m icro ch ip . S im ulated vs. m easu red w ith p rin ted
in terco n n ects vs. m easu red
w ith
rib b o n b o n d s.......................................................................75
F ig u re 63: M o d ified m o d el o f C P W to G aA s w ith co n cav e dielectric m aterial an d in terco n n ects..
.............................................................................................................................................................................. .7 5
F igure 64: S n and S2i resu lts o f C P W to G aA s m icrochip. S im ulated w ith m od ified m odel to
re fle c t printed ap p earan ce vs. m easured w ith p rin ted interconnects vs. m easu red w ith rib b o n
b o n d s.....................................................................................................................................................................76
F igure 65: S 22 and S 12 resu lts o f C P W to G aA s m icrochip. S im ulated w ith m o d ified m odel to
re fle c t p rin ted ap p earan ce vs. m easu red w ith p rin ted in terconnects vs. m easu red w ith ribbon
b o n d s............................................................................
77
1
I. INTRODUCTION
The method o f creating interconnects between microelectronic chips has not
changed very much since the introduction o f microelectronics. Wirebonds and ribbon
bond interconnects have provided a simple and effective way to electrically connect
microchips, but they can also lead to unwanted inductance attributed to the long, loopy
wirebonds and don’t allow for a controlled impedance across the interconnect. Until
recent years, there has been no other practical means o f creating reliable, easy to
implement interconnects, but with the recent progress in printed electronics and additive
manufacturing, this is no longer the case. With the use o f additive manufacturing,
interconnects can be printed directly between microchips, coplanar waveguides and other
radio frequency transmission lines. This thesis presents the design and fabrication o f
additively manufactured conductive interconnects to be used to electrically connect
microelectronic devices and transmission lines in electronic packaging. The ability to
design and print conductive interconnects allows for a more optimized and controlled
impedance, which leads to a better overall performance o f the devices in the
microelectronic packaging.
The second chapter o f this thesis provides a background on conventional methods
for interconnects within microelectronic packaging, introducing the issues with
traditional wirebonds, which have been problematic for engineers and technicians for
years. The background section o f this thesis also provides a background o f techniques
and progress in printed electronics and additive manufacturing. The development o f
printed electronics and the recent improvements in the technology used in this area
enable the ability to additively create structures whose performance is on par with similar
subtractively manufactured structures will be demonstrated.
The third chapter o f this thesis presents the simulation analysis. The design
presented involves a microchip and coplanar waveguide on a substrate separated by a
gap. The printed conductive interconnects includes dielectric material printed within the
gap on which the conductive interconnects are printed upon. A model o f the structure is
made in HFSS and the electrical properties o f the dielectric material are optimized
through simulations. The electrical performance o f the dielectric material printed on a
supportive ‘pillow’ material, whose purpose is to build height, is also analyzed through
simulations. Thermal and structural analysis are also presented in this chapter to simulate
the effects o f any thermal expansion o f the dielectric materials, printed between the chip
and the coplanar waveguide structures. For conventional wire bonding methods, only air
exists between these structures.
In the fourth chapter, the material characterization,, printing, and measurement
methods are discussed. The types o f equipment used and the considerations for printing
methods are discussed in detail. The dielectric material is characterized for electric,
thermal, and structural properties. Then, the material properties are entered into the
simulations and compared to the measured results. Two prototypes are manufactured with
printed interconnects: one with two coplanar waveguides, end to end, and another with a
coplanar waveguide to GaAs Microchip.
In the last chapter, the thesis concludes with a summary o f the work
encompassing this project. An additively manufactured interconnect that can be used
between microchips in high frequency devices is designed and created using printed
electronics technology. Future work for improving the printing methods and suggestions
for improving materials available is included.
II. BACKGROUND THEORY AND INFORMATION
In this chapter, we explore the background that contributes to this thesis. First,
conventional methods o f interconnecting microelectronic devices (wirebonding, and
ribbon bonding, Flip Chip technology and Tape-Automated bonding) and each method’s
benefits and problems are discussed. The next section introduces printed electronics and
its benefits over traditional subtractively-manufactured electronics and then delves into
different types o f printing technologies and how these different technologies operate.
This section also discusses the capabilities o f printed electronics by exploring different
types o f radio frequency (RF) and microelectronic devices that are manufactured with
printed electronics technology. Prior work on different types o f printed microchip
interconnects is also discussed in this section.
I I . l C o n v e n t io n a l M e t h o d s o f F o r m in g M ic r o c h ip I n t e r c o n n e c t s
With the reduction o f size and the improved performance o f microelectronics, it
has become increasingly important to form interconnects between bare die microchips to
increase the compactness o f integrated circuits (ICs). There are several types o f
interconnect technologies that have been used for connecting bare die microelectronic
chips. Chip on board (COB) is where bare die chips are placed on the substrate with bond
pads facing up. COB is convenient for manufacturers because most ICs are available in
bare die format, so the manufacturer only needs to invest in bonding equipment for
forming wirebonds to connect bare die chips to the substrate or bond pad. Another option
for connecting bare die chips to a substrate is flip chip (also called controlled collapse
chip connection, C4, or FC). Flip chip uses the same types o f bare die ICs as COB except
the bond pads are on the bottom o f the chip. The direct attachment o f the die to the
substrate eliminates the extra capacitance and inductance caused by bondwires in COB
packaging. This and the compactness makes flip chip packaging a popular interconnect
technique. While flip chip and wirebond interconnects in microelectronic packaging are
viable methods, they both still have their drawbacks. In wirebonding, uncontrolled
impedances are undesirable, especially in high frequency applications. Flip chip
packaging can be costly, particularly if the ICs are not low cost or high volume.
II.l.l Conventional Interconnect Methods
Wire bonds are the primary type o f interconnects used in chip on board (COB)
packages where the bare die chip is placed on the substrate with the bond pads facing up.
Wire bonding in electronic devices was first used by Bell Labs in 1947 on the first
transistor ever built. The wire bonds were hand mounted and quite large. Since then the
technology has progressed, but for the last 30 years or so, there have been two main types
o f wire bonds: wedge bonding and autoball bonding [1]. Figure 1 shows an image o f how
wedge and autoball bonds are formed. The wedge-bonding tool uses ultrasonic (US)
energy and compression to weld the wire to the bond surface where the wire takes on the
form o f the wedge at the joint. The autoball bonding tool feeds the wire through a
capillary where a spark melts the end o f the wire into a ball. The ball is bonded to the
surface with thermocompression (TC) energy, where heat and compression forms the
bond to the bond pad, or with thermosonic (TS) energy, where US energy, heat and
compression bond the ball to the bond pad. Ball bonding is a faster method o f forming
wirebonds than wedge bonding due to the fact that ball bonds can be moved in any
direction once the first bond is formed. This allows for the microchip or substrate to
which the second bond will be attached to have more placement flexibility than that of
the wedge bond. In wedge bonding, the components being bonded must be aligned in a
straight line in one dimension to avoid structural stress on the bonds. Other types o f chip
interconnect options include flip chip, (also called controlled collapse chip connection,
C4, or FC), where solder bumps are deposited on the top side o f a chip and the chip is
flipped over so the solder bumps connect the chip to the bond pads, attaching it to
external circuitry and solder bumps are welded to the pad using TS energy. Another
alternate chip interconnection method used is Tape-Automated Bonding (TAB). In TAB,
interconnects are etched onto multilayer polyimide tape and the tape is overlaid on top o f
the bare die chip so the interconnects attach to the bond pads and bonded through TS,
converted wire autobonders or laser bonding [1].
y -U S c n a iB K
'jwm.
A
mm,
„
“nd
i
mm.
Figure 1: Simplified process o f ball bonding process (left) and wedge bonding process (right), taken
from [161. Autoball bonding uses TC, TS or US energy to bond ball for bond to bond pad. Wedge
bonding uses US energy and compression to bond wire to surface.
6
II.1.2 Problems with Conventional Wirebonds
When comparing wirebonding in COB packaging to FC and TAB, FC
interconnects provide the best performance because o f the limited inductance caused by
the bonds being directly attached to the chip. This also causes FC packages to be more
compact because the need for space consuming wire bonds is eliminated. However, with
both FC and TAB bonding, any modifications to the microchip in size or design require
the redesign o f the bonding package pattern. In FC, the substrate to which the the chip is
being bonded also needs to be redesigned to accommodate the alignment o f the bond
pads and solder bumps on the chip. In TAB, the etch design o f the interconnects on the
polyimide tape also needs to be updated to ensure alignment with the microchip being
altered. FC and TAB are also costlier than wirebonding, which means that for either to be
cost-effective, they need to be used in high volume or high cost microchips. Wirebonds
provide the flexibility to alter the size, or positioning o f the wirebond interconnects in the
package by simply reprogramming the bonding tool [1], The flexibility and costeffectiveness o f wirebonding is the reason they have been the predominant method o f
chip interconnects for over 50 years. However, there are problems with wirebonding that
have plagued microelectronic packaging. One o f these problems is the increased
inductance introduced by wire bonds. The longer the wirebond, the more inductance
introduced
into the
interconnect.
This increased
inductance causes
impedance
mismatches at the interconnect transition, which leads to unwanted reflections in high
frequency (HF) circuits. Wirebonding also requires that there is enough space for the
large bonding tool to be able to physically attach to the bonds. Wire bonding also requires
a strict set o f considerations on the part o f the assembler according to IPC guideline IPC-
7
CM-770 [2]. These considerations include the bond pads and substrate being within a
very narrow height range o f each other, a level substrate, among other spatial constraints.
With the growing demand for higher frequency and higher density ICs, this is becoming
increasingly difficult.
To alleviate some o f the issues caused by higher inductances, high frequency IC
manufacturers often opt for ribbon bonds over wire bonds. The ribbon bonds are flat
wires with a rectangular cross section and depending on the width to thickness ratio o f
the rectangular cross section, yield less inductance losses, leading to lower impedances at
high frequencies [1,2]. The inductance o f a flat ribbon wire is given in nH by [3]:
( 1)
As the w/t ratio increases, the impedance decreases. This is desirable at higher
frequencies, but the larger w/t ratio can make it difficult to weld the bond to the substrate.
As the w/t ratio increases, it becomes increasingly important to maintain a parallel
distance between the welding tool and the substrate, otherwise one side of, the ribbon
bond will be poorly welded to the substrate. Additionally, the IPC-CM-770 restrictions
apply to all printed board component mounting, including both wire bond and ribbon
bonding processes.
The use o f ribbon bonds decreases the unwanted inductance, but often additional
measures are needed to reduce inductance. Another method manufacturers often
implement to reduce the inductance o f ribbon or wire bonds is to use two bonds, rather
than one. Based on Equation 2, the equivalent inductance o f inductors in parallel is less
than the smallest inductance.
The use o f two bonds decreases the inductance, but this often requires that more space is
added to a bond pad, which can cause unwanted capacitance and alter the impedance o f a
transmission line. Larger bond pads also take up valuable space on a microchip.
Not only do wirebonds cause unwanted inductances, they also simply provide
very uncontrolled impedance since every wirebond is slightly different (positioning on
the bond pad, shape o f wirebond bend). Wire bonds can also be subject to sagging,
especially in three dimensional circuitry [4,5]. The wire sagging can cause short circuits
and other types o f chip malfunctioning.
I I .2 P r i n t e d E l e c t r o n i c s a n d A d d i t i v e M a n u f a c t u r i n g T e c h n i q u e s
Printed electronics, a subset o f additive manufacturing, is a quickly developing
technology and is currently estimated to be a 19 billion USD industry by 2025 [6]. Due to
its cost effective nature, rapid prototyping and minimal waste, printed electronics is a
viable competitor to traditional subtractive manufacturing. Subtractive manufacturing
uses expensive and time consuming multi-step photolithographic processes in which a
mask is developed and a chemical treatment removes unwanted parts o f the substrate to
result in the desired pattern. This process can take months and, by its nature, yields a lot a
material waste, so not only is the process itself costly, but the wasted materials that are
chemically removed cannot be recovered. Conversely, additive manufacturing uses only
the material needed for the process, which can be conductive, resistive and/or dielectric,
and patterns are made by the subsequent printing o f these materials on top o f each other.
9
In printed electronics, a pattern is developed and printed onto a substrate rather than
going through the photolithographic and etching process. The cycle for additive
manufacturing begins with a design (sometimes built in a simple computer aided design
(CAD) program), the design being printed (and cured, depending on the material), and
finally tested. This cycle time can happen in as little as a day versus months for a
subtractively-manufactured product. Furthermore, if a modification is needed in a design
of a product being fabricated with subtractive manufacturing, this could cost the
manufacturer time and money. Because o f the short cycle time and rapid prototyping
associated with additive manufacturing, any design modifications can be applied and
tested within days allows designers more freedom with their designs because products
can be redesigned in days rather than months for a fraction o f the cost. Rapid prototyping,
low cost manufacturing and the recent technology developments in printed electronics
have led to the emergence of printed solar cells [7], multilayer, flexible circuit boards [8],
RFID tags and antennas [9,10], transistors [11], and other RF circuitry [12-17].
II.2.1 Two Dimensional Printing Technologies
Two dimensional printing technologies include inkjet, direct contact micro­
dispensing, and Aerosol Jet printing. Inkjet printing can be dispensed through piezo,
thermal, electrostatic or acoustic printing. Piezo dispensing is the most common, in which
a piezoelectric crystal causes a droplet o f ink to be dispensed when the voltage is applied
to it. Inkjet printing systems require very low viscosity inks (5-50 cp) and can produce
line widths from 20-50 pm [18]. Direct contact micro-dispensing is a term that can be
applied to several different print systems, one o f which being the nScrypt Micro-
Dispense system. This system dispenses ink through the Smartpump and the volume o f
material dispensed is controlled by a valve rod opening and pressure applied to the pump.
This system can deposit a wide variety o f materials, with viscosities ranging from that o f
water (around one centipoise) to that o f a thick paste (around 1,000,000 centipoise) [19].
Another type o f micro-dispense system is the Sonoplot Microplotter. This system uses
capillary action to load micro tubes with the material being printed. The material is
dispensed by applying a voltage that vibrates a piezoelectric crystal, which forces out the
material. In both the nScrypt micro-dispensing system and the Sonoplot microplotter, the
print head is in direct contact with the print substrate. An image o f the Optomec Aerosol
Jet system depositing ink is shown in Figure 2. In the Optomec Aerosol Jet system (200
Series Systems, Optomec Co., USA), the print head is offset from the print surface.
Aerosol Jet printing is an automated, direct-write deposition method that can deposit
materials from 1-1000 cp viscosity with the ability to print fine features (down to 10 pm
line widths and 20 pm pitch sizes). The three main components o f an Aerosol Jet system
are the Pneumatic Atomizer, the Virtual Impactor exhaust (VI), and the Deposition Head.
The Pneumatic Atomizer creates an aerosol mist from a liquid well o f ink with an input
o f N 2 gas. The mist is drawn from the atomizer nozzle and formed into a high velocity
stream. The aerosol stream goes through the VI where the excess atomization gas is
removed and the aerosol mist is concentrated. An input o f sheath gas into the Deposition
Head focuses the mist before being deposited [20].
Figure 2: Optomec Aerosol Jet system set-up and process. Taken from [21].
The focused beam o f aerosol mist gives the Optomec Aerosol Jet printing system the
ability to print very fine feature pitch sizes. This thesis primarily uses the Optomec
Aerosol Jet system to print conductive interconnects between bare die RF devices atop a
dielectric ink.
II. 1.2 Printed and Additively Manufactured Interconnects
Developments in recent years in additive manufacturing make printed threedimensional (3D) interconnects a practical alternative to conventional wire bonding or
flip chip packaging techniques used to interface ICs and other high frequency electronic
components. The ability to directly write interconnects directly in electronic packaging
reduces alignment issues with traditional wire bonding and helps mitigate issues with
parasitic inductances attributed to wire bonds [2]. Printed interconnects offers a versatile
solution for interconnecting multilayer system-in-package (SiP) electronic packaging and
12
has been shown to have great promise in high-speed digital device packaging [22].
Printing the conductive trace up the side o f a chip from the substrate can often lead to
cracks in the printed conductor, particularly at the 90° angle comers between the chip and
the substrate and at the comer o f the chip. To mitigate this problem, an insulating
dielectric material is often time printed first, acting as a ramp for the conductive ink [2230]. The conductive material is printed onto the ramp using Aerosol Jet printing-in
[22,25,30]. Current progress in millimeter wave technologies is leading to the
development o f low cost, compact microelectronic packaging with large bandwidth data
transmission. Printed electronics technology offers the capability o f producing a more
controlled impedance at the interconnects enabled by the ability to design and print
engineered transitions in high frequency devices. However, all o f the work discussed uses
printed electronics to print interconnects between DC devices except for [23]. In [23], the
3D interconnect structure consists o f a substrate with a 50 micron thick silicon IC die
which are connected by coplanar waveguide transmission lines printed on a dielectric
ramp structure using inkjet printing. All o f the methods, whether for digital or high
frequency applications, use similar structures. An example is shown in Figure 3.
Dielectric ram ps
Interconnect Lines
Figure 3: 3D Interconnect structure method consists o f an IC die atop a substrate where a dielectric
ramp is printed on the side o f a die, upon which the conductive trace is printed.
13
In this thesis, a similar method is used to create 3D printed interconnects, except rather
than an IC die being electrically connected to a signal line on a substrate, the IC die is
electrically connected to a radio frequency transmission line which is at the same level as
the die. So rather than a dielectric material acting as a ramp, it acts a bridge for the
conductive trace to be printed upon. The use o f the dielectric as a bridge can also be used
as a means o f interconnecting two radio frequency transmission line or two bare die ICs.
Additionally, the work in this thesis uses the Optomec Aerosol Jet printing system to
form the conductive interconnects rather than inkjet printing, which is beneficial because
o f the finer pitch capabilities o f the Optomec.
III. ANALYSIS
This chapter presents a novel way o f connecting 3D structures in high frequency
microelectronic devices. The test structure is a grounded coplanar waveguide that will be
connected to a GaAs microchip separated by a gap. The GaAs microchip is mounted on a
copper-molybdenum heat spreader to bring it to the same height as the coplanar
waveguides. Normally, the coplanar waveguide would be connected to the microchip
with wire bonds or ribbon connectors, but this work explores the process o f replacing the
wire bonds with printed interconnects printed on a dielectric material connecting the two
structures as shown in Figure 4.
14
Figure 4: Model image o f coplanar waveguide connecting to a microchip with standard wire bond
interconnects (left), and coplanar waveguide connecting to a microchip with printed interconnects.
The dielectric filled in the gap between the coplanar waveguide and the microchip will
affect the impedance o f the interconnect as well as the mechanical properties o f the
interconnects due to coefficient o f thermal expansion (CTE) mismatches. This chapter
first looks at the electrical effect o f the dielectric by modeling the printed interconnects
atop the dielectric. The process o f optimizing the impedance o f the printed interconnects
in HFSS is outlined. The cross section o f the ribbon bonds is maintained in the
conductive interconnects first and the dielectric constant o f the dielectric material is
optimized. Next, the impedance optimization o f the printed interconnects with the
controlled dielectric material printed atop a pillow material with a low Young’s modulus,
whose purpose is to build height for the dielectric. This chapter then looks at the
multiphysics approach o f analyzing the effects o f the 3D printed interconnects. The
electrical and mechanical properties o f the printed materials are characterized and entered
into HFSS and the Mechanical simulator by ANSYS. The different simulation tools are
linked together in ANSYS workbench and a full, multiphysics analysis o f the test
structure is achieved.
I I I . l E l e c t r ic a l A n a l y s is
High frequency electronics are very sensitive to changes in design, so the design
and analysis of the interconnects is important to ensure electrical performance doesn’t
suffer. Electrical analysis o f two coplanar waveguides connected with traditional ribbon
bonds is simulated to first gain familiarity with the test structure. Subsequent analysis
will insert a GaAs microchip between the two coplanar waveguides.
III.l.1 Model Familiarity
To gain confidence in electromagnetic model simulations, a model o f two
grounded coplanar waveguides made o f alumina and attached with wire bonds was
simulated in ANSYS HFSS. An image o f this model is shown in Figure 5.
Figure 5: HFSS Model o f two coplanar waveguides attached with wire-bonds for model verification.
The model was simulated in HFSS with a waveport excitation o f lW att from 1-30 GHz
with 201 equally spaced frequency points. The return and insertion losses were analyzed
by looking at the scattering parameters (S-parameters). In order to verify the simulated
results, two alumina coplanar waveguides were mounted atop a copper-molybdenum
ground substrate and gold ribbon bond interconnects were bonded to the waveguides to
connect the signal and grounds o f the coplanar waveguides. The structure was measured
using an Agilent PNA microwave network analyzer and ground-signal-ground (GSG)
350 pm pitch probes from GGB Industries Inc. (Naples, FL, USA). The losses attributed
16
to the coaxial cables and probes were calibrated out using a short-open-load-thru (SOLT)
calibration substrate. The measurement was performed over a range o f l-18GHz due to
the limitations o f the G-S-G probes. An image o f the fabricated structure for verification
is shown in Figure 6.
Figure 6: Image o f the ribbon bond interconnects between the two coplanar waveguides used for
model verification. Taken with Keyence VHX-5000 series digital microscope (Itasca, IL, USA).
The simulated and measured results were compared and found to be in agreement with
each other. Graphs o f the reflection losses for the measured and simulated results are
shown in Figure 7.
-10
-20
-40
-50
-60
-70
Frequency GHz
Figure 7: Return losses (Sn) of coplanar waveguides connected with wire-bonds: measured data and
simulated results.
17
The variations between the simulated and measured results are likely due to slight
differences in the model and the real device (such as the shape o f the ribbon bonds and
the probe placements). Because o f the reflections and resonances that can happen at
higher frequencies [39-42], the deviation between the simulated and measured results is
expected to increase as the frequency increases.
III. 1.2 Printed Interconnect Optimization
When modeling the printed interconnects, there are many design parameters to
optimize. One important design parameter is the thickness o f the printed conductive
traces. In order to avoid losses due to skin effects, the conductivity o f the material needs
to be taken into account. Another important design parameter is the dielectric properties
o f the dielectric material on which the conductive traces will be printed. The relative
permittivity o f the material is a primary contributor to the impedance o f the interconnects
and needs to be optimized for minimal reflections. This section looks into these factors
more in depth.
III. 1.2.1 Conductive Traces
Silver nano-particle inks used in additive manufacturing print systems have a
much lower conductivity than bulk silver. Measurements that will be discussed in section
IV. 1 show that the Paru silver nano-particle ink has a conductivity o f 1.18xl07 S/m,
whereas bulk silver has a conductivity o f 6.30x107 S/m at room temperature. At high
frequencies, the current density is mainly on the top surface, or skin, o f the conductor and
18
follows a negative exponential distribution. One skin depth is the depth at which the
current density has fallen to 37% (1/e) and is defined as [31]:
(3 )
where a is the bulk conductivity o f the material, p is the permeability, and co is the
angular operating frequency. The negative exponential distribution o f the current density
tells us that when a conductor is six skin-depths thick, 99.75% o f the AC current will be
captured. Figure 8 is a graph o f the frequency dependency o f minimum thickness needed
for the printed silver nano-particle ink in order to capture 99.75% o f the current. This
chart shows that in order to avoid skin depth losses at frequencies above 7.5 GHz, the
printed conductive traces need to be at least 10 microns thick.
30
''o
5
10
15
20
25
30
F re q u e n c y (GHz)
Figure 8: Six skin depths o f silver nano-particle ink versus frequency.
III. 1.2.2 Dielectric Optimization
Once the simulation method was verified by comparing to measured results, the
model was updated to include the GaAs chip between the coplanar waveguides. This
model was simulated to have a baseline model for future comparisons. The Sn and S 12
parameters for this model are shown in Figure 9.
-10
■5 -2 0
I -30
-40
-50
-60.
25
30
Figure 9: Return and insertion losses for model o f GaAs microchip connected to two coplanar
waveguides with wire-bonds.
Once the baseline model above was established, a model for the printed interconnects
was created. Due to the gap between bare die microchips, a dielectric material needs to be
inserted between the structures to support the printed interconnects. The wire-bonds in
the model were removed and a dielectric material was inserted in the gap. Printed
interconnects are patterned on the dielectric in the model creating the connections
between the signal on the coplanar waveguide and the GaAs microchip and between the
grounds on the coplanar waveguide and the GaAs microchip. The thickness o f the printed
interconnects was set to 10 microns to avoid losses due to skin effects. The dielectric
20
material being deposited between the components will serve as a bridge for the
conductive traces to be printed. In high frequency transmission lines, the dielectric
properties o f the substrate have an enormous effect on the impedance o f the transmission
line. For example, the formulas for the characteristic impedance o f a microstrip
transmission line is shown in Equation 4 [31]:
120 tt
where W is the width o f the conductive strip, d is the thickness o f the dielectric substrate
and £e is the effective dielectric constant o f the dielectric material.
Since the thickness o f the dielectric is fixed to the height o f the coplanar
waveguides and the width o f the conductive traces have very little flexibility due to the
size o f the bond pads, the main component that can be controlled is the dielectric material
properties. To optimize the performance o f the interconnect, a parametric sweep o f the
dielectric constant o f the material was performed from 1-40. A plot o f the return losses
for some o f the dielectric constant values in the sweep are shown in Figure 10.
21
-10
U
-20
-
'II
tn -30
-40
-50
EpsR = 2
— EpsR =3
- — EpsR = 4
EpsR = 11
EpsR = 12
EpsR = 20
EpsR = 30
EpsR = 40
-60,
20
Frequency GHz
Figure 10: Return losses for permittivity sweep o f dielectric o f material in model with GaAs
microchip connected to two coplanar waveguides with printed interconnects. Return losses shown for
dielectric constant o f 2 ,3 ,4 ,1 1 ,1 2 ,2 0 ,3 0 and 40.
Based on the parameter sweep o f the dielectric constant, the best results (i.e. the lowest
return losses) occur when the dielectric constant is as close to that o f air as possible
(lowest possible). A comparison o f the lowest permittivity values in the sweep to the case
o f using ribbon bond interconnects is shown in Figure 11.
-10
-20
cn -30
CD
*o
-40
EpsR = 2
EpsR = 3
JL
EpsR = 4
ribbon bonds
-50
-60
20
25
Frequency GHz
Figure 11: Return losses for permittivity sweep o f dielectric o f material in model with GaAs
microchip connected to two coplanar waveguides with printed interconnects. Dielectric constant
values o f 2, 3, and 4 (shown in blue, red and green, respectively) compared to baseline case with
ribbon bond interconnects (shown in pink).
22
Based on this, the useful temperature range and the available materials, epoxy based
dielectric ink, 118-12, from Creative Materials with a dielectric constant o f 4 at 50 Hz
was chosen (Creative Materials, Ayer, MA, USA) [32].
III.1.3 Pillow Material
The previous section explores the option o f filling in the gap between the coplanar
waveguides and the GaAs microchip with a single dielectric material. That method would
include filling the gap with a dielectric ink and fully curing the ink without any voids.
Since the coplanar waveguides are 20 mil thick, this could be problematic. Additionally,
the chosen dielectric material may not be suitable for thermal and mechanical purposes.
To remedy this potential problem, the use o f a pillow material is analyzed. The pillow
material is a material that will be deposited in the gap between the coplanar waveguide
and GaAs microchip before the dielectric. The pillow material will not completely fill the
depth o f the gap, but instead will leave space (on top) for the controlled dielectric to
finish filling the gap. The purpose o f the pillow material is to build height for the
controlled dielectric to be printed, as well as to provide a cushion to absorb any CTE
mismatches so the pillow material must have a low Young’s modulus. For these reasons,
3140 RTV silicone (Dow Coming, Midland, MI, USA) [33] was chosen.
The Dow Corning 3140 silicone has a relative dielectric constant o f 2.52 and
dielectric loss tangent o f 0.001 at 100 kHz, which will alter the impedance o f the
interconnects. The silicone under the dielectric was modeled in HFSS to analyze the
effects o f the silicone on the impedance. The height o f the silicone was chosen such that
the majority o f the gap is filled with the pillow material and a thin layer o f the Creative
23
Materials dielectric would sit on top o f the pillow. A model image o f the GaAs microchip
between two CPWs with the controlled dielectric material printed on the pillow material
in the gap with the printed interconnects is shown in Figure 12.
Figure 12: HFSS model o f CPW -GaAs-CPW with silicon pillow material underneath the printed
dielectric material and cross section o f build-up o f pillow material, dielectric material and printed
conductive traces.
The total height o f the alumina coplanar waveguides is 20 mil, so the model was made
with a 16mil thick layer of pillow and 4mil thick layer o f dielectric. The equivalent
relative dielectric constant o f the 4mil thick controlled dielectric and the 16 mil silicone
pillow material can be calculated from Equation 5 [34]:
Where N is the number o f layers (two in this case), sn is the dielectric constant o f the nth
layer and tn is the thickness o f the nth layer. Using Equation 5, the equivalent dielectric
constant o f the two materials comes out to be 2.72.
24
III. 1.4 Variable Ground Height
As a result o f the work in the previous section, the concept o f a variable ground
height was explored with the use o f the pillow material. The height o f the coplanar
waveguide is a limiting factor in the thickness o f the dielectric which, as pointed out in
the previous section in Equation 4, is crucial for optimal impedance matching. However,
if there was a conductive ground layer printed onto the pillow layer before depositing the
controlled dielectric, then the dielectric material beneath the ground (i.e. the pillow
material), would not matter electrically. In Equation 4, d would only be the height o f the
dielectric above the ground layer, which is the height o f the Creative Materials 118-12 in
Figure 13.
Signal
Conductive Ground
layer (red)
Controlled dielectric (Creative
Materials 118-12)
Pillow Material
Figure 13: Model o f cross section o f printed interconnect section with ground (red) printed on pillow
material.
Adding the conductive ground layer above the pillow material electrically isolates the
pillow from the top dielectric material. This allows for more customizable impedance
25
matching o f the conductive traces, since the height o f the dielectric material is no longer a
limiting factor.
To test this concept, simulations were conducted with a GaAs microchip being
connected to a coplanar waveguide with this type o f structure, as shown in Figure 14.
Figure 14: HFSS model of CPW -GaAs-CPW with silicon pillow material, then a conductive ground
plane, then controlled dielectric, then signal and more dielectric (left)- Cross section o f build-up of
pillow material, conductive ground, dielectric material and printed signal line with more dielectric
printed on top (right).
Comparing the S-parameter results from the set-up in Figure 14 to the typical ribbon
bond interconnects, there is a reduction in reflection losses, especially in the higher
frequency ranges, as shown in Figure 15.
26
Embedded Microstrip
Ribbon Bonds
-10
CO - 2 0
■o
-3 0
-4 0
-5 0
10
20
30
40
50
60
Frequency (GHz)
Figure 15: Modelled Sn parameters of the structure shown in Figure 14 comparing ribbon bonds and
printed, embedded microstrip-interconnects.
Additionally, since the pillow material is isolated electrically from the other dielectric
material, the dielectric properties of the pillow material no longer matter. This opens up
more possibilities for types o f materials that can be used for the pillow, including ones
that have better thermal and structural properties.
I I I .2 M u l t i p h y s i c s S i m u l a t i o n A p p r o a c h
A unique artifact o f this research is filling the gap between the high frequency
components to create an even surface on which the interconnects could be printed. By
doing this, however, potential problems with thermal expansion o f materials are
introduced. In order to fully analyze the effects o f the printed dielectric and conductive
interconnects, a full multiphysics simulation o f the model is required. ANSYS’s
27
workbench enables a united, interactive solution in which electrical, thermal and
structural analysis o f a model can be assessed.
III.2.1 Thermal Mechanical Analysis
Once the electrical analysis is completed, the results and model are imported into
ANSYS Mechanical through the Workbench. To set up the thermal model, boundary
conditions need to be applied to the model. In ANSYS Mechanical Steady-State Thermal
either a convection or a temperature boundary condition needs to be applied for a unique
solution. Since we want to look at the heat leaving the surface, a convection boundary
condition was applied. A temperature boundary condition was also applied to the bottom
faces o f the structure and set to 150°C, which represents the heat spreader substrate to
which the components would be mounted in an actual package (not shown). Imported
heat generation load from the HFSS model was applied to body o f all non-conducting
objects; the imported heat flux load from the HFSS model was applied to all o f the
electrically conducting surfaces. An image o f the imported heat generation boundary
condition and the imported heat flux boundary condition being applied to the structure is
shown in Figure 16.
28
Figure 16: Imported heat generation boundary condition applied to the non-electrically conductive
bodies in the model (left), and imported heat flux boundary conditions applied to the electrically
conductive faces in the model (right).
When applying the convection boundary condition, a heat transfer coefficient, as
well as an ambient temperature, must be entered. The film coefficient (aka heat transfer
coefficient or convection coefficient) can be viewed as a proportionality constant
between the surface temperature and the ambient temperature. A small film coefficient
(convection coefficient) of 7 W/m2*°C was chosen, since there is little heat generation in
this system and the ambient temperature is chosen to 25° C. The ANSYS workbench has
a library of materials that can be imported into the mechanical model and these materials
have the required material properties to run the simulation o f the model. Since the
dielectric is not included in the material library, it is necessary to measure the required
material properties to run the model. The characterization o f the mechanical material
properties is discussed in section IV. 1.3. The material properties o f the dielectric material
and conductive ink material used in the thermal and structural analysis are those
measured and discussed in future sections. In the case o f the Steady-State Thermal
simulations, the thermal conductivity is required. The thermal conductivity o f the
Creative Materials dielectric was measured to be 0.25 W/(m*pK). One interesting
simulation result to look at in thermal analysis is the temperature o f the object, which
29
shows how the surrounding objects heat up under certain thermal conditions. The
simulation of the model shows a maximum temperature o f 151.08°C at the interconnects,
as shown in Figure 17.
i it-cj.J' c t o t iCPDcyS
Figure 17: Heat map of Stead-State Thermal simulation with bottom face of model heated to 150°C.
Another informative simulation result in the thermal analysis is the heat flux, which is
defined as the rate o f heat energy going through a given surface. The total heat flux
showed a maximum at the interconnects o f 1.9659e6 W/m , as shown in Figure 18.
Figure 18: Total heat flux magnitude from Steady-State thermal with bottom face o f model heated to
150°C.
It can be seen in these simulations that thermal conductivity o f the dielectric material is
much less than that o f the surrounding materials because o f the rise in temperature at the
interconnects. To get a more realistic depiction o f how a device similar to this would
actually heat up, a second thermal simulation was conducted. Typically, a GaAs
microchip would have an active device on it, causing the chip to heat up at the output. To
mimic this scenario, a thermal boundary condition o f 150°C was applied to the output
side o f the GaAs microchip. The temperature results o f this simulation are shown in
Figure 19.
ESI!8g3IMiSl
Figure 19: Heat map of Stead-State Thermal simulation with output of GaAs microchip heated to
150°C.
One notable artifact o f the temperature results is how the heat propagates through
the dielectric ink more than it does through any other materials next to the output side o f
the GaAs microchip. Also, even though the temperature boundary condition is 150°C, the
maximum temperature o f the device reaches 161.89°C. The total heat flux o f this thermal
simulation is shown in Figure 20.
Figure 20: Total heat flux magnitude from Steady-State thermal with output o f GaAs microchip
heated to 150°C.
'y
The maximum heat flux in this simulation is shown to be 3.7576e8 W/m . Results in
Figure 20 indicate that this happens at the place where the GaAs chip was split in half
into the input and output sides (at the location o f the red tag). Ordinarily, a microchip
would not be split in half, so the heat flux at this location is an artifact o f the simulation,
which can be ignored. The other main place where there is a heat flux is at the
interconnects on the output side o f the chip, which is 1.4e6 W/m .
III.2.2 Structural Mechanical Analysis
The main purpose of the thermal analysis is to observe how the structure behaves
under a heat load. Once the thermal analysis was completed, the results were sent to the
set-up for the Static Structural model in ANSYS Workbench. The material properties
needed for the structural model are the Young’s modulus and thermal expansion
coefficient. These properties were measured and the process and results are discussed in
section IV. 1.3. To set up the Static Structural model, boundary conditions must again be
32
applied. In this model the only boundary condition needed for a unique solution is a fixed
support. In this case the fixed support was applied to the bottom faces o f the alumina
coplanar waveguides, the dielectric and the heat spreader. The body temperature load
from Steady-State Thermal was also imported and applied to the model. The two most
important results to analyze in the Static Structural model are the total deformation o f the
model, which indicates how much the materials in the model have expanded due to heat
and CTE mismatches, and the stress intensity, which indicates which areas will have the
most stress applied to them under expansion. The simulation results from the first Steady
State Thermal analysis with the bottom face o f the structure heating to 150°C were
applied to the first static structural analysis. The model was simulated and the total
deformation o f the model was 0.14 mm, as shown in Figure 21.
.
vy«r.>-?
Figure 21: Total deformation maximum 0.14mm with temperature o f bottom o f entire structure set
to 150°C.
The stress intensity results for this simulation are shown in Figure 22.
33
Figure 22: Stress intensity occurs at boundary between dielectric and CPW and GaAs with Bottom
Surface Heated to 150°C.
The Static Structural model was simulated again with the results o f the thermal
simulation with the output side o f the microchip being heated to 150°. Figure 23 shows an
image o f the total deformation in the model, which is 0.04mm.
Figure 23: Total deformation maximum of 0.04mm with output side temperature boundary condition
set to 150°C.
The stress intensity results o f the simulation are shown in Figure 24.
Figure 24: Stress intensity results with GaAs microchip output side temperature boundary condition
set to 150°C.
These results indicate that the expansion and CTE mismatches could cause problems with
the interconnects as the temperature increases. As the dielectric material expands, so do
the conductive printed interconnects. This is a potential problem, electrically, because it
could cause the interconnects to crack and become an open circuit. Further analysis o f the
device under more realistic conditions should be conducted with an actual active device
on the GaAs microchip. This would help to determine whether the Creative Materials
dielectric material is suitable for uses in this application.
IV. EXPERIMENTAL SETUP
This chapter discusses the experimental methodology for printing and material
characterization.
IV.l
M a t e r ia l C h a r a c t e r iz a t io n o f P r in t e d M a t e r ia l s
As the field o f additive manufacturing and printed electronics grows the available
materials to work with also expands. Materials are being developed for a variety o f
printing applications and printers. The types o f materials range from inks used in Aerosol
Jet printing, inkjet printing, and other types o f microdispensing, to filaments used in 3D
printing systems. A crucial factor with the printable materials is the ability to accurately
characterize them, both electrically and mechanically because without reliable material
properties to use in model simulations, an accurate depiction o f how the device will
perform with the chosen material is unrealizable. It is often found that manufacturers
provide minimal material characteristics, which increases the necessity for reliable and
repeatable electrical and mechanical characterization methods. For the application in this
thesis, the materials for both the controlled dielectric the interconnects are printed on and
the conductive interconnects need to be characterized. The next several sections discuss
the electrical and mechanical characterization methods used in this work, with a main
focus on the dielectric characterization method.
IV.1.1 Dielectric Characterization
The dielectric characterization method used was developed at RURI [40,42].
Many material manufacturers simply avoid characterizing their dielectrics at high
frequencies, for example, the Creative Materials dielectric being used in this work has a
dielectric constant o f 4 at 50Hz. Since many dielectric inks that are used in inkjet and
aerosol systems are in liquid form, they are printed and cured in thin layers. Conventional
means o f characterizing dielectric properties o f a material under test (MUT) require a
thick slab or 3D piece o f the material that must be machined to fit in a waveguide or
cavity [35-39] and require several different size resonators to characterize the MUT over
a large frequency range. Whereas these methods provide accurate results, they are time
consuming due to the need to create multiple samples o f a specific size and thickness.
36
The method used in [41] can characterize the complex dielectric properties o f a material
over a very wide frequency range, but requires expensive and time-consuming
photolithography technique and a large thin film o f the MUT to be fabricated. The
method we developed in [40] only requires a small amount o f ink and accurately
characterized the real part o f the dielectric constant up to 20 GHz, but also yields a low
dielectric loss tangent, which can often be inaccurate. Our method in [40,42] requires no
photolithography, like in [41], and is shown to accurately characterize the dielectric
properties of a material up to 20 GHz, but uses printed cylindrical capacitors whose
dimensions can vary from print to print and can lead to inaccuracies in the measurements.
The method used also utilizes cylindrical capacitors filled with the MUT, but rather than
printing the cylindrical capacitors, like in [40,42], or using expensive photolithography
with a large sheet o f the MUT, like in [41], cylindrical capacitors are etched out o f a
copper plated substrate using standard PCB techniques.
This characterization method uses a 14 ounce copper cladded Rogers 5870
substrate. The cylindrical capacitors were etched out o f the substrate leaving a 35 pm
deep well to fill the ink with. Figure 25 shows an image o f the etched copper cylindrical
capacitor.
Substrate
Figure 25: Etched cylindrical capacitor (left) and HFSS image o f cylindrical capacitor (right) where
Rin = 220 pm and Rout = 600 pm.
37
The cylindrical capacitors were measured with one 850 pm pitch GSG probe (GGB
Industries Inc., Naples, FL.) using an HP8510C Vector Network Analyzer (VNA)
(Keysight Technologies Inc., Santa Rosa, CA). The MUT printed in the opening space of
capacitors for characterization was Creative Materials 118-12, an epoxy based dielectric
ink (Creative Materials, Inc. Ayer, MA).
The MUT was deposited onto the capacitors
using an ultrasonic controlled micro-dispensing printer (Microplotter II, Sonoplot Co.,
USA). Dimensions were measured using a digital microscope (VHX-5000 Series,
Keyence Co., USA) and height measurements were performed by a stylus profilometer
(Alpha-Step D-500, KLA-Tencor Co., USA). To verify the accuracy o f the measured
results, the dielectric properties o f the MUT were measured using a Transmission Line
method utilizing waveguides. These measurements were taken using an X-band (WR-92)
waveguide with a FieldFox VNA (Keysight Technologies Inc., Santa Rosa, CA).
IV.1.1.1 Dielectric Characterization Method
The characterization method is based on one-probe RF measurements, and utilizes
a cylindrical capacitor as the Device Under Test (DUT). The capacitor consists o f a
conductive cylinder separated by a gap from an outer conductive cylinder as shown in
Figure 25. The capacitor is made by etching away the copper coating o f a copper cladded
substrate. The parallel plate capacitance o f the cylindrical capacitor, ignoring fringing
effects, is given as:
C = 2.7l£r€n --- 5——----,
0 In(
/Rin)
(6)
where eo = 8.85E-12 F/m is the permittivity o f free space, er is the relative permittivity o f
the MUT, h is the height o f cylinders, R0m is the inner radius o f the outer cylinder, and Rin
38
is the outer radius o f the inner cylinder. The proposed method uses the reflection Sparameter (Si i) to extract the dielectric constant and loss tangent. The complex Su
parameters can be converted to the complex impedance o f the DUT:
1 4* S-ii
z =zn1 -
Su '
(7)
where Zq = 50 Q is the impedance o f the measurement port. The equivalent circuit o f the
DUT can be represented as a resistor in series with two complex capacitors in parallel, as
shown in Figure 26.
Figure 26: Equivalent circuit model o f the device under test (DUT) filled with a dielectric material,
i.e., air or material under test (MUT).
The impedance o f the equivalent circuit o f the DUT can be given as:
Z — Rn +
— -------^7T'
joi(CP + CD)
(8)
where Ro represents the ohmic losses from the metallic plates, Cb represents the
capacitance from the dielectric in the gap (whether the air or MUT), and Cp represents
any parasitic capacitance present (mainly due to the substrate). We arrange the real and
imaginary parts of the complex capacitances, Cd and Cp, as:
a = CD + CP,
/? = CDtanSD + CptanSp,
(9)
(10)
39
where a is the sum o f the real part o f each capacitance and [i is the sum o f the imaginary
part o f each, and tan8o represents the losses from the dielectric in the gap and tan8p
represents the parasitic losses. We can rewrite (7) as:
Z
R °
w(a2 +
(11)
Equation (11) can be separated into real and imaginary parts:
w
(12)
(13)
We define Zref to be the impedance o f the capacitor with air (in absence o f MUT), and
Ztest to be the impedance o f the capacitor with the MUT. For Zref, a = Ca + Cp and /? =
Cp tan^p. For Ztest, a = C + Cp and
= Ctan<5 + Cp tan<5p. Since loss tangent values are
usually very small, we assume that
terms are negligibly small and can be removed to
simplify the equations. Moreover, tan<Sp is known from the data sheet for each substrate
used. By taking the real and imaginary parts o f Zref and Ztest using (12) and (13), a set o f
four equations are obtained that can be solved to extract the dielectric loss tangent and
dielectric constant o f M UT:
tanS =
Re{Z test}
Re{Zref }
-------------- t----- z---------------- y -------------- r -
(14)
I t y i (Zfgyf)
1
1
//TX(Z^eS()
( ojCa) ( l + tan28) ’
^ }
40
where Ca is calculated by using er = 1 in (1). These equations were used in MATLAB to
analyze the simulated and measured results.
IV. 1.1.2 Dielectric Characterization Simulation
The equations used for the extraction o f dielectric properties were initially
validated by HFSS simulations 17.0. The following simulation method involves
predefining dielectric properties o f a MUT in HFSS model and extracting the dielectric
properties o f the MUT using (14-15) and the simulated reflection parameters. This
method allows for comparison o f the known or predefined dielectric properties and the
extracted dielectric properties, much like the method used in [42].
A cylindrical capacitor was created in HFSS, as shown in Fig. 25. The inner
radius
(7 ? jn )
was set to 220 pm and the outer radius o f the capacitor was set to 600 pm.
The metallic plates were modeled as lossy copper. For the first part o f the simulations,
the dielectric material in the gap was defined as air for the reference DUT. The model
was simulated from 1-35 GHz and the Sy i-parameters were stored. For the second part,
the dielectric material in the gap was modeled as a material with predefined dielectric
constant and loss tangent profiles, which are shown respectively with dashed and solid
blue curves in Fig. 4.1.1.2.1. The frequency-dependent relative permittivity o f the MUT
in the simulation was defined to have a set profile, as shown in Equation 16:
Er = 40 • exp (sin (x )),
(16)
where x is a vector from 1 to 35 with 200 equally spaced points, which represents the
frequency axis (in GHz). This fictional dielectric material was used to provide a known
41
dielectric constant profile which is frequency dependent. The dielectric loss tangent was
set to 0.05 with a constant profile over frequency range. The test DUT was also simulated
from 1-35 GHz and the Su -parameters were stored.
Once the 5) i-parameters from the simulations o f reference and test DUTs were
recorded, reference and test impedances were obtained using (7). Equations (14) and (15)
were finally used to extract the permittivity and dielectric loss tangent o f the MUT. The
extracted relative permittivity and dielectric loss tangent values are shown with solid red
curves in Figure 27. It can be seen that they are in agreement with the pre-assigned
permittivity profile and loss tangent values.
— Extracted cf
0.06
.
— Input <r profile
a 0.05
100
m0.04
2 0.02
30
Frequency (GHz)
35
0.01
5
10
15
20
25
30
35
Frequency (GHz)
Figure 27: Extracted complex dielectric properties from simulated results o f DUT filled with a MUT
versus input dielectric profiles predefined for the MUT: (left) permittivity, (right) loss tangent.
The simulations show that the complex dielectric characterization method works quite
accurately up to 30 GHz. Extracted dielectric constant and loss tangent values at
frequencies above 30 GHz show a divergence from the input dielectric properties, which
could be due to resonances in the cylindrical capacitors at high frequencies. The
simulated results also show that this method is a much more reliable method for
calculating the dielectric constant and loss tangent values than the method used in [40],
which results in a loss tangent o f more than an order o f magnitude lower than the actual
42
value. The discrepancies between simulated and extracted loss tangent values could be
due to unaccounted losses in HFSS model arising from higher mode propagations or
radiation losses.
To verify the accuracy o f the method presented, the Creative Materials dielectric
was formed into and cured in a film, and cut to fit into an X-Band TE-mode waveguide
fixture for measurements. A Thru-Reflect-Line (TRL) calibration was performed on the
waveguide fixtures with a VNA. The thickness o f the sample was measured with a micro­
caliper and entered into the software for accurate dielectric calculations. Return and
insertion losses from 8.2 - 12.4 GHz were measured with 200 evenly spaced frequency
data points.
IV. 1.1.3 Waveguide Method Setup
To verify the accuracy o f the method presented, the Creative Materials dielectric
was formed into and cured in a thin film o f approximately 400 pm thick and cut to fit into
an X-Band TE-mode waveguide fixture for measurements. A Thru-Reflect-Line (TRL)
calibration was performed on the waveguide fixtures with a VNA. The thickness o f the
sample was measured with a micro-caliper and entered into the software for accurate
dielectric calculations. Return and insertion losses from 8.2 - 12.4 GHz were measured
with 200 evenly spaced frequency data points. An image o f the waveguide fixture set-up
and measured sample are shown in Figure 28.
43
Figure 28: W aveguide set-up for dielectric measurement (left) and thin film sample o f cured
dielectric ink (right).
IV.1.2 Conductive Ink Characterization
Another important material property to characterize is the conductivity o f the
silver nano-particle ink. The properties o f the ink can vary depending on several
variables, including the amount o f time the ink is cured, the temperature it is cured at,
whether the ink is cured in an oven or a hotplate, batch o f ink and the age o f the ink itself,
and the thickness o f the ink, which depends o f the number o f passes or layers printed
with the Optomec Aerosol Jet printer. In order to properly characterize the conductive
ink, it is necessary to test the ink under different conditions multiple times to determine
the average conductivity value that can be expected and the ideal conditions under which
the best performance o f the ink is obtained. To test the conductivity o f the silver nano­
particle ink, strips o f the ink were printed using the Optomec aerosol printer and cured
using varying cure schedules. An example o f a printed strip o f the cured ink is shown in
Figure 29.
44
Figure 29: Printed sample of silver nano-particle ink used for test (left) and profilometer
measurement image o f height o f printed sample (right). The sample above was printed with 10 passes
of the printer, measuring 18.4 microns in height.
The samples are cured and sintered by heating to at least 200°C for at least two hours in
an oven or five minutes on a hotplate. Once the samples are cured, the thicknesses are
measured using a profilometer and the conductivity is measured with a four-point probe,
as shown in Figure 30.
Figure 30: Four point probe used for conductivity measurements.
45
IV. 1.3 Thermal Conductivity Characterization of Dielectric Ink
Thermal conductivity is the ability o f a material to transfer heat. In electronic
devices, heat dissipation is crucial, so using materials with high thermal conductivities is
desired. There are many methods o f characterizing the thermal conductivity o f materials.
The guarded hot plate method requires machining a solid uniform piece o f the material
and placing between two plates and heating one plate until the entire structure is a
uniform temperature. The run-time for the test can be lengthy and does not work for
liquids or high thermal conductivity materials [43]. Laser flash diffusivity is another
popular method, but requires the material to be machined into a specific shape and is
contingent on knowing other properties o f the material such as specific heat and density
[43,44],
The method used to measure the thermal conductivity o f the Creative Materials
dielectric ink is the 3-omega method described in [45]. A resistive heater line, which acts
as both a heater and thermometer is deposited on a glass substrate using photolithography
like the image in Figure 31. The four pads shown are leads for the current and voltage, I+,
I ' , V+, and V'.
Figure 31: Heater line for 3-omega thermal conductivity measurement without dielectric material.
46
The 3-omega method only requires a small amount o f the dielectric ink to be cured onto
the resistive heater line, which makes this method conducive for measuring the thermal
conductivity o f inks. A current is driven through the heater with an AC current operating
at frequency ©. The periodic heating o f the heater line occurs at 2©, which creates a heat
wave that penetrates through the surrounding environment at 2© with a phase lag, <D. The
amplitude o f the heat wave depends on the material properties o f the surrounding
environment. The temperature oscillation causes a change in the resistance at a 2©
oscillation. The current driven at © and the change in resistance at 2© result in a voltage
o f 3©. This process is done to the heater line without the cured dielectric and then with
the cured dielectric, as shown in Figure 24.
\
% ■>
'
i
Figure 32: Heater line for 3-omega thermal conductivity measurement with dielectric material.
IV.1.4 Thermal Expansion Measurement of Dielectric Ink
To get an accurate representation o f a structural model, it is necessary to measure
the mechanical properties o f the dielectric ink, such as Young’s modulus and the thermal
expansion coefficient. Both measurements are made with a dynamic mechanical analysis
machine (DMA). By filling in the air gap that is typically between a bare die microchip
47
and coplanar waveguides with a material, structural problems are potentially introduced
due to thermal expansion coefficient (TEC) mismatches between materials. In order to
get a thick enough sample for TEC measurements, the dielectric ink needs to built up in
thickness.
Since the material is so heavily solvent loaded (about 40%), a
Thermogravimetric Analysis (TGA) o f the ink in its uncured state needs to be conducted.
The TGA test takes a small sample o f the material and applies a specified temperature
profile with the goal o f identifying different stages in the curing process by measuring the
change in weight o f the sample as a function o f temperature and time. Figure 33 shows
the TA instruments Q500 TGA machine [46].
Figure 33: TA Instruments TGA. A small amount o f uncured sample gets loaded into the small pans
and is heated. The TGA measures the changes in weight in the pan as a function o f temperature [461.
The data sheet for the Creative Materials 118-12 dielectric [32] lists a cure schedule o f
80°C for four hours, 90°C for two hours or 100°C for 1 hour. The TGA test performed on
the sample o f the dielectric ink raised the temperature o f the ink to 50°C at 5°C/min, then
held the temperature at 50°C for 30 minutes, then increased the temperature to 80°C at a
rate o f 5°C/min, then hold the temperature at 50°C for 30 minutes. Finally, the
temperature was increased at 20°C/min for 30 minutes. The results o f the TGA are shown
in Figure 34.
800
120
100
-600
6Q.f
x:o>
-400
60
51.89%
I
48.43%
252.74“C
179.35’C
100
T im e (m in )
-200
120
140
U n iv ersal V 4.5A TA In stru m e n ts
Figure 34: TGA results o f uncured Creative Materials dielectric. Results show the percent weight left
o f the original weight o f the material across the temperature profile.
The TGA results show that the slope o f the percent weight decreases as the temperature is
held at 50°C. This indicates that most o f the solvent is evaporated from the material at
49
50°C. As the temperature increases to 80°C, the material loses a little more weight, but
holds steady until the temperature increases again. The part o f the percent weight graph
that occurs between 49.19% and 48.43% has a somewhat steady slope, but at 252.74°C,
the prevent weight begins to drop dramatically. This indicates that the material is unstable
at temperatures higher than 250°C, at which temperature, major components o f the
material begin to bum off.
The main take away from the TGA results is that when curing thick layers o f the
material, similar to the thermal expansion measurements, each layer should stay at 50°C
for at least an hour to bum off the solvent in the ink, then the temperature can be
increased to 80°C for crosslinking to occur in the material. To prepare the sample for
thermal expansion measurements, two pieces o f 7mil thick electrical tape were applied to
a Teflon substrate and the dielectric material was doctor bladed across the tape with a
razor blade. The first layer was heated to 50°C in an oven for an hour, another layer o f
tape was applied and a second layer o f ink was doctor bladed across the tape and heated
again to 50°C for an hour. This process was repeated 5 times, for a total tape thickness of
35 mils (0.889mm), and then the sample was cured at 80°C for 4 hours.
The sample was measured with the DMA with a compression fixture. The sample
thickness was 0.58 mm. An image o f the sample in the DMA fixture for measuring the
CTE is shown in Figure 35.
50
Sample
Figure 35: Dielectric sample in DMA fixture for measuring CTE.
The CTE test was started at room temperature (25°C) and a static force o f 0.05N was
applied. The temperature was increased at a constant rate o f 5°C/min until it reached
200°C.
TV. 1.5 Elasticity Measurement of Printed Inks
The Young’s modulus o f the Creative Materials controlled dielectric was
measured next. This tensile test required that a thin strip o f the material be cured for
testing. To make the test sample, 7-mil-thick electrical tape was applied to a Teflon
substrate to prevent sticking after curing and the dielectric material was doctor bladed to
achieve uniform thickness. The material was cured on the Teflon substrate for 90 minutes
at 100°C in a convection oven. An image o f the sample material fixed into the DMA for
analysis is shown in Figure 36.
Figure 36: Creative M aterials cured dielectric sample in Q800 DMA by TA Instruments for tensile
test.
It was also important to measure the elasticity o f the conductive ink used for the
interconnects because, as was mentioned in section III.2.1, the dielectric ink will expand
as the device is heated up. When the dielectric ink expands, it causes stress on the
conductive ink. The more flexible the conductive ink is, the less likely it is that the
conductive traces will break under pressure and cause shorts in the lines. The Paru nano­
particle silver ink is a low viscosity ink and printing thick layers is a difficult task.
Therefore, a more viscous conductive silver ink was measured for elasticity instead. The
Loctite ECI 1011 ink was used, which has similar electrical properties to the Paru ink.
The Loctite ink was cured into a thin film in the same manner as the dielectric ink and
tensile tests in the DMA were performed. The cured Loctite ECI 1011 loaded into the
DMA before measurement is shown in Figure 37.
52
Figure 37: Loctite ECI1011 sample in Q800 DMA by TA Instruments for tensile test.
I V .2 P r i n t i n g a n d M e a s u r e m e n t E q u i p m e n t a n d T e c h n i q u e
This section discusses the procedure and materials used in the prototypes o f the
printed interconnects. Three different prototypes are discussed:
•
T w o c o p la n a r w av eg u id es end to end, spaced 10 m il apart.
•
T w o c o p lan ar w av eg u id es end to end, spaced 20 m il apart.
•
C o p lan ar w av eg u id e to G aA s m icrochip, sp aced 15 m il apart.
IV.2.1 Two Alumina Coplanar Waveguides
Rather than begin with a prototype o f printed interconnects between a CPW and
microchip, a simple structure o f two alumina CPWs spaced 10 mil apart on a coppermolybdenum substrate is considered. The first step in building the interconnects was to
add a pillow material o f Dow Coming 3145 [47] in the gap between
in Figure 38.
the CPWs, asshown
53
Figure 38: Three sets o f two alumina CPWs end to end mounted in copper-moly substrate 10 mils
apart. Viscous Dow 3145 silicone pillow material deposited between CPWs with syringe. Polyimide
Kapton tape used to prevent silicone from curing onto conductive pads.
The purpose o f the pillow material is to build height for the Creative Materials onto
which the dielectric is deposited. Since the next dielectric material still needs to be
applied, the pillow material should not completely fill the gap, but leave a few mils o f a
gap between the top o f the silicone and the top o f the CPW substrate. The Dow 3145
silicone sets in a humid room temperature environment for at least 3 days to cure, after
which the Creative Materials 118-12 dielectric is applied atop the pillow material with a
syringe. The Creative Materials ink was cured in an oven at 100°C for one hour. Once the
dielectric ink was cured, the conductive interconnects were printed with the Optomec
Aerosol Jet printer. The interconnects on each set o f CPWs were printed seven layers
thick with a 200 micron inner diameter print head tip. An image o f all three sets o f CPWs
after the conductive ink was printed is shown in Figure 39.
54
|100ym!
Figure 39: Paru nano-particle silver ink interconnects printed on Creative M aterial dielectric ink
with Optomec Aerosol Jet Printer. Each set o f interconnects printed with seven passes o f conductive
ink.
Once the conductive ink was printed, the CPW structures were placed in the oven at
200°C for three hours to sinter the conductive ink.
Next, the components were measured using two 350 um pitch GSG probes. The
probes were calibrated from 0.5-20GHz using a GGB industries (GGB Industries Inc.,
Naples, FL.) CS-9 short open load thru (SOLT) calibration substrate. The measurements
were performed on an Agilent PNA network analyzer (Keysight Technologies Inc., Santa
Rosa, CA). The GSG probes were 18GHz probes, so the measurements were performed
from 0.5-20GHz.
IV.2.2 Coplanar Waveguide to GaAs Microstrip
The final prototype was made with a CPW and GaAs microchip. A GaAs
microchip was mounted onto a copper-moly heat spreader tab, then the tab and a CPW
were mounted onto a copper-moly ground substrate. The tab and the CPW were mounted
15 mils apart from each other. For this prototype, a less viscous pillow material, the Dow
Corning 3140 silicone, was chosen, [33]. The Dow 3140 has similar electrical properties
as the Dow 3145, but the less viscous material is able to be planarized more effectively,
allowing for a smoother surface for the Creative Materials dielectric to be printed upon.
To prevent the pillow material from flowing out o f the gap, a dam material is also
employed. The sole purpose o f the dam material is to prevent the pillow material from
flowing out, so a variety of different materials and methods are acceptable for the dam
material. The dam material can be printed or deposited. In the case o f this prototype,
layers o f Kapton tape were stacked and used as the dam material, as shown in Figure 40.
' s i* ',
p
Figure 40: Alumina Coplanar waveguide and GaAs thru microchip mounted on copper-moly heat
spreader substrate, IS mil apart. Layers o f Kapton tape stacked used as dam material.
56
After the dam material was applied, the Dow 3140 pillow material was applied in the gap
between the CPW and GaAs microchip and cured, the Creative Materials 118-12
dielectric is deposited onto the pillow material as shown in Figure 41.
Figure 41: Dow 3140 Pillow material deposited in gap, then Creative Materials dielectric deposited
atop it and cured.
For this sample, the dielectric material was cured on a hotplate for one hour at 100°C.
The use o f printed traces significantly shortens the length o f the interconnects as
compared to ribbon or wire bonds. Because the length o f the bond is shortened it will be
less inductive, so before printing interconnects on this sample, additional simulations
were conducted to determine if the gap between the components was narrow enough such
that the inductance o f a single line would be low enough to only use one signal line rather
than two. HFSS simulation results indicated that the return losses (Sn-parameters) were
lower with only one signal line with a 15 mil gap between components, as shown in
Figure 42.
57
-10
-20
•40
'Two Printed bonds
'One Printed Bond
-60
0
5
10
15
20
25
30
Frequency (GHz)
Figure 42: Sn parameters o f GaAs microchip between two coplanar waveguides 15 mil apart. Two
printed bonds shown in blue, one printed bond shown in red.
The simulation results in Figure 42 indicate that the use o f one printed bond results in
lower reflections over most o f the frequency range. The CAD file for the conductive
interconnects with one signal trace was made in AutoCad and loaded into the Optomec
software. The interconnects were printed, connecting the signals o f the CPW and GaAs
microchip. There were seven layers of the Paru silver nano-particle ink printed for each
interconnect using the Optomec Aerosol Jet printer. Since the proximity o f the bond pads
on the GaAs chip were much closer than the CPW, a smaller line width was desired. To
accomplish this, a 150 um inner diameter print head tip was used. Additionally, the
Optomec print head was tilted to 45° to ensure continuity o f the printed traces.
The silver ink was sintered by curing the devices in the oven at 200°C for 3 hours.
An image o f the cured interconnects is shown in Figure 43.
58
|100nm|
Figure 43: Cured silver nano-particle ink printed on dielectric, connecting GaAs and CPW. Single
signal line printed rather than two.
The spacing o f the bond pads on the GaAs microchip is smaller than the spacing on the
CPW, therefore the measurements o f this prototype used a 350 um pitch probe on the
input (CPW side) and a 250 [xm pitch probe for the output (GaAs side). The probes were
calibrated from 0.5-40GHz using a CS-9 calibration substrate. The S-Parameters were
measured using an Agilent PNA network analyzer from 0.5-40GHz.
V. RESULTS
The following sections discuss the measured results o f the material
characterization and the printed conductive traces.
59
V .l
M a t e r ia l C h a r a c t e r iz a t io n R e su l t s
This sections reviews the results o f the material characterization processes from
the previous section. The results from the material characterization analysis are used in
all subsequent model simulations.
V.1.1 Electrical Characterization Results
When modeling and simulating the performance o f a device, it is important to
have accurate material properties o f the materials used in the simulation to get a realistic
depiction o f the device performance across a desired frequency range. Due to the novelty
o f the dielectric characterization method used, a second method was applied to verify the
dielectric properties o f the material. The cylindrical capacitor method is used to
characterize the Creative Material 118-12 dielectric ink from l-30GHz and a resonant
cavity waveguide method is used to characterize the material at X-Band. This section
discusses and compares the results o f each method.
V.l. 1.1 Concentric Cylinder Method
The cylindrical capacitors used for test have an outer radius, Rout = 648 pm and
inner radius, Rm - 334 pm. Since the capacitors are etched from the copper cladded
substrate rather than printed, as in [40], the feature dimensions o f the cylindrical
capacitors are very precise and allow for more accurate extraction due to more accurate
measurements o f the feature dimensions. The capacitors were measured using a GSG
probe which was calibrated with a Short Open Load calibration procedure to remove the
errors and losses attributed to the transmission cables and probes. The measurements and
60
calibration were performed with a VNA from 1-35 GHz with 165 equally spaced
frequency points. The reflection 5-parameter o f the air-filled cylindrical capacitors
(reference DUTs) were stored and the impedance o f the capacitors were calculated using
(7). The dielectric was printed into the gap openings with the microdispensing Sonoplot
system and then cured. The reflection 5-parameters from the test DUTs were stored and
the impedance o f the capacitors with the cured MUT were calculated using (7). Using the
characterization method described in Section II and evaluated using simulations in
Section III, the permittivity and dielectric loss tangent were calculated in MATLAB
using (6) - (15). The average relative permittivity and loss tangent o f three measured
samples o f the Creative Materials ink are shown up to 30 GHz in Figure 44.
«
e
8
\
3
{»
0.3
1’
a>
. . . .
5
10
.
15
.
^
__________ _
20
25
_______
i
30
Frequency (GHz)
0.1
5
10
15
20
25
30
Frequency (GHz)
Figure 44: Measured dielectric constant (left) and loss tangent (right) o f Creative M aterials ink,
averaged over results from three printed samples.
V I.1.2 Waveguide Method Measurements
The method of calculation used in the Keysight software for this analysis is the
NIST method [2], a variation o f the Nicholson-Ross-Weir [1, 4] method, in which the
relative permeability is not measured and set equal to unity. This method uses various
linear combinations o f scattering equations and solves them iteratively, leading to a stable
result.
In order to verify the accuracy o f the cylindrical capacitor method, the complex
dielectric properties extracted for the Creative Material ink in Section IV.A are compared
to the results extracted using the NIST method [37] utilizing a cured sample o f the ink.
The results o f two methods are compared in Figure 45. The results show that the NIST
method results and the presented results match up very well, which indicates that the
presented method provides a very accurate means o f characterizing the complex
permittivity o f dielectric inks. The NIST method does show resonances at approximately
9.75 GHz. The NIST method is very sensitive to slight variations in the surface o f the
measured sample, which can cause uncertainties in certain frequencies [37]. Other than
the peaks caused by phase error, the two methods are in good agreement through the
entire frequency band (8.2 -
12.4 GHz). The main benefits o f the one-probe
characterization method using the cylindrical capacitors presented here are the ease o f
implementation and the very broadband characterization frequency range.
62
|— NIST method
i*—Cylindric Capacitor Method
9
10
11
0 .5
12
Frequency (GHz)
■NISTmethod
•Cyiindric Capacitor Method
9
10
11
12
Frequency (GHz)
Figure 45: M easured dielectric constant with NIST method versus presented method (left) and
measured loss tangent with NIST method versus presented method (right) o f Creative Materials
MUT.
V.l.1.3 Volume Resistivity Results o f Conductive Inks
Much like in the previous section, it is important to have correct material
properties to have an accurate model simulation o f a device. Volume resistivity o f
conductive materials is an important material characteristic for accurate electrical
simulation results. The volume resistivity o f printed conductive ink depends on several
variables, such as the cure time, the cure temperature, the thickness o f the cured ink, just
to name a few. The weighted average conductivity results for different cure schedules o f
the Paru silver nano-particle ink are shown in Figure 46.
63
P
e
4> 1.60E+07
>
<
41
i
1:381:8 ?
16.00E+06
:881:81
Conductivity Averages
1.40E+07.
1.38E*03------------------------------ _ _ _ _ _ — ^
—
JC
V 4.Q0E+06
2.00E+06
g> 0.00E+00
r
3
1.17E*07
III
✓
—
«<
s
/
Curing Schedule
Figure 46: Weighted averages of conductivity results for various curing method o f the Paru silver
nano-particle ink.
Based on the measured conductivity results o f the silver nano-particle ink, the average
conductivity is around 1.17 *107 S/m, this value is significantly less than that o f bulk
silver (about 6.3 * 107 S/m), which is expected o f printable conductive inks based on
datasheets o f available printable conductive inks.
V. 1.1.4 Simulated Results with Nominal Electrical Material Properties and Measured
Electrical Material Properties
Once the dielectric and conductive inks are electrically characterized, the material
properties are entered into HFSS and the model o f the GaAs microchip connected to two
coplanar waveguides with printed interconnects is simulated again. The difference
between the simulation results with a constant dielectric constant value o f four and the
measured dielectric properties is shown in Figure 47.
64
-10
-20
(2
CD
<D
E
CO
-50
-60
511 constant dielectric
512 constant dielectric
511 measured dielectric
512 measured dielectric
25
Frequency (GHz)
Figure 47: Insertion losses (S12 and S21) and return losses ( S ll and S22) for model o f GaAs
microchip connected to two coplanar waveguides with printed interconnects on top o f dielectric with
constant dielectric constant (red) and measured dielectric constant (blue).
It can be seen in Figure 47 that the measured dielectric material properties have a
significant effect on the simulated results, especially in the 10-22 GHz region. This is
expected because o f the measured frequency dependence o f the dielectric constant.
V.1.2 Mechanical Simulation Results with Measured Dielectric Thermal and
Structural Properties
V.l.2.1 Thermal Conductivity o f Dielectric Ink
The magnitude o f the 3-Omega voltage can be plotted in a semilog plot against
the frequency as shown in Figure 48 and the thermal conductivity o f the dielectric
material can be extracted from the difference in the slopes o f the 3-Omega plots with and
without the material.
65
60-
50-
o> 40-
30-
20-
10 I IIIIMIJ
7.38906
!54.59815
<53.42879
In(f) (Hz)
Figure 48: 3-Omega voltage versus frequency.
This method resulted in a thermal conductivity o f 0.25 W/(m*°K), which was entered
into the steady state thermal model.
V. 1.2.2 Thermal Expansion Characterization o f Dielectric Ink
The CTE test was started at room temperature (25°C) and a static force o f 0.05N
was applied. The temperature was increased at a constant rate o f 5°C/min until it reached
200°C. The linear portion o f the resulting curve is shown in Figure 49.
66
Temperature vs. Displacement Curve
200
—
Tem perature vs. Displacement
- — Best fit line Slope (C TE 'O riginal length): 2.0 3 3 2 5 7 (1/C )
150
100
-50
-10(
100
150
200
Tem p e ra tu re (C )
Figure 49: Displacement versus Temperature curve for CTE measurement.
The slope o f the displacement versus temperature curve is related to the CTE (a) by
Equation 3, where L0 is the initial thickness o f the sample.
1 M L\
“ -
z; f e )
<1 7 >
From this equation and the measured results, the CTE o f the dielectric was found to be
0.0023 0C '’. This information was entered into the material properties for the Creative
Materials dielectric in the Workbench environment and the model was simulated again
with this information.
V. 1.2.3 Elasticity o f Printed Inks
The DMA tensile test for both the dielectric ink and the conductive ink were run
at room temperature (25°C) with a force ramp rate o f 3N/min to 18N. The resulting stress
strain curve from the test for the Creative Materials dielectric ink is shown in Figure 50.
67
S tress vs. Sfraln Curve
Stress vs. Strain
Beat fit line Slope (Youngs Modulus): 646.180892 (MPa)
« 15
-
0.005
0
0.005
0.01
0.015
0.02
0.025
0.03
0.035
Strain
Figure 50: Stress-Strain Curve for Creative Materials dielectric.
The slope o f the best linear fit line o f stress strain curve is Y oung’s modulus, as shown in
Equation 18.
E =
S tr e s s
S tr a in
<j(£)
(18)
From this equation, the Young’s Modulus o f the dielectric material under test is 646.18
MPa. The resulting stress-strain curve for the Loctite ECI 1011 conductive silver ink is
shown in Figure 51.
68
S tre ss vs. Strain Curve
9
—stress vs. Strain
S
« Best fit line Slope (Youngs Modulus): 59.680125 (MPa)
7
6
at
I s
B>
<®A
£
4
0}
3
2
1
0
-
0.02
0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
0.16
Strain
Figure 51: Stress-Strain Curve for Loctite E C I 1011 silver ink.
Using Equation 18, the Y oung’s Modulus o f the Loctite silver ink was found to be low, at
59.68 MPa.
V .2 M e a s u r e d R e s u l t s o f P r in t e d I n t e r c o n n e c t s
This section discusses the measured results o f the printed conductive traces and
compares the measured results to the simulated results.
V.2.1 Two Alumina Coplanar Waveguides
Two coplanar waveguides were placed end to end with a 10 mil gap between
them. A pillow material was deposited in the gap between the CPWs and cured, followed
by the Creative Materials dielectric ink. Next, a conductive ink was printed atop the
dielectric ink, electrically connecting the signal o f each coplanar waveguide and the
ground lines o f both coplanar waveguides, as shown in Figure 52.
69
[lOOym!
Figure 52: Coplanar waveguides with printed interconnects (top) and HFSS model o f the coplanar
waveguides with printed interconnects.
Once the interconnects were printed, the structure was measured with a vector network
analyzer (VNA). The VNA measured the insertion and return losses from 1-18 GHz. The
measured return losses were compared to the simulated return losses with the dielectric
material having a nominal dielectric constant o f 4 as well as the measured dielectric
properties. A graph comparing the measured results and both simulated results is shown
in Figure 53.
-10
-20
-50
-60
-70.
Measured
Simulated, constant dielectric
Simulated, measured dielectric
Frequency (GHz)
Figure 53: Measured and simulated Sn results with a constant dielectric constant o f four, and
simulated results with the measured dielectric constant results for the two coplanar waveguides end
to end.
The results in Figure 53 show that using the measured dielectric properties in the
model bring the simulated results closer to the measured results. To improve the accuracy
o f the model to the measured results, the model was changed to look more like the
measured prototype. Figure 54 shows a profilometer image o f the cured dielectric ink.
The image indicates that the dielectric cross section is not flat, but rather wavy.
i!
Figure 54: Profile o f dielectric ink as viewed from the side. This image shows how the dielectric ink is
not flat, but is like two peaks with a valley between the peaks.
To improve the correlation between the simulated and measured results, the model in
HFSS was redrawn to reflect the measured profile o f the dielectric ink. A side view cross
section of the HFSS model is shown in Figure 55.
I___ L
Figure 55: Cross sectional view o f the two alumina CPW samples with a printed in terconnect. The
dielectric was redrawn to better match measurement taken with profilometer.
Another change made to the HFSS model is the width o f the dielectric. The original
model assumed that the dielectric ended at the edge o f the gold traces on the CPW. Upon
reexamination o f the prototype, the dielectric covers part o f the edge o f the gold traces, as
shown in Figure 56.
Figure 56: Image o f prototype, which shows the dielectric ink covering part o f the edges o f the gold
traces on CPW. This is significant because the length o f the printed traces atop the dielectric affects
the inductance o f the interconnects.
Another case considered in the simulated model is the case where one o f the signal
interconnects appears to not be connected to the signal line on the CPW, as shown in
Figure 57. This could significantly impact the performance o f the device and also could
greatly affect the impedance o f the interconnects. Since one o f the printed signal lines is
not connected, the inductance will increase and the inductive losses will increase as well.
This change was also reflected in the model, in which one o f the interconnects was taken
out, as shown in Figure 57.
Figure 57: Image o f prototype, which shows the printed interconnect not connected to gold trace on
CPW (left). M odel o f second interconnect taken out to account for the disconnect o f one o f the
printed interconnects.
Figure 58 shows the simulated results o f the modified model with the measured dielectric
properties, the original model with the nominal dielectric properties and the measured
results.
-10
-20
-30
-50
Simulated m easured dielectric
Simulated nominal dielectric
m easured
-60
-70
0
5
10
15
Frequency (GHz)
Figure 58: Measured and simulated Sn results with a nominal dielectric constant o f four, and
simulated results with the measured dielectric constant results used in modified model.
The results in Figure 58 show that the modified HFSS model with the changes to
the dielectric profile, the dielectric width and the omission o f one o f the printed
interconnects, all o f which more closely resemble the printed prototype, the simulated
73
and measured results are closely correlated. One important thing to note is that the losses
o f the structure with increasing frequency is clearly evident when observing the measured
results and modeled results with the measured dielectric properties. This is indicative of
how the dielectric properties o f the material change with frequency and that it is
important to have a material characterized over a frequency range rather than just at a
nominal frequency.
V.2.2 Coplanar Waveguide to GaAs Microstrip
The last prototype made was a GaAs microchip mounted onto a coppermolybdenum heat spreader tab, then the tab and a CPW were mounted onto a ground
substrate. The tab and the CPW were mounted 15 mil apart from each other. An image o f
the prototype with fully cured interconnects is shown in Figure 59.
Figure 59: Interconnects printed between a CPW and GaAs microchip.
A reference structure with a CPW connected to a GaAs microchip with traditional
wirebonds was also measured as a baseline and is shown in Figure 60.
Figure 60: CPW to GaAs microchip with ribbon bond interconnects.
For an additional point o f comparison, a model o f the structure with printed interconnects
atop the dielectric material and pillow material was also simulated in HFSS. The results
for the three cases are shown in Figure 61 and Figure 62. The input port results (Sn and
S21) are shown separately in Figure 61 from the output port results (S 22 and S 12), which
are shown in Figure 62.
•10
-20
r- -40
-50
Printed 811
"——Ribbon Bonds 811
— Simulated Printed 811
Printed 821
Ribbon Bonds 821
Simulated Printed 821
-60
-70
5
10
15
20
25
Frequency (GHz)
30
3S
40
Figure 61: Sn and S2i results of CPW to GaAs microchip. Simulated vs. measured with printed
interconnects vs. measured with ribbon bonds.
75
-10
-15
S -20
-35
Printed 322
— Ribbon Bonds S22
— Simulated Printed 822
Printed 812
Ribbon Bonds 812
Simulated Printed 812
-10
-45
•50
5
10
15
20
25
Frequency (GHz)
30
35
40
Figure 62: S2 2 and S(2 results o f CPW to GaAs microchip. Simulated vs. measured with printed
interconnects vs. measured with ribbon bonds.
The results show very good agreement between the measured results o f both the
printed interconnects and the ribbon bonds. Moreover, the simulated model shows
excellent agreement with the measured results. However, closer examination o f the
printed interconnects show that the dielectric is slightly concave rather than flat. To
account for this in the model, the dielectric and interconnects were altered to have a
concave appearance. The modified model is shown in Figure 63.
Figure 63: M odified model o f CPW to GaAs with concave dielectric material and interconnects.
76
The simulations were repeated with the modified model and the results were again
compared to the measured results. The input port results (Sn and S21) are, again, shown
separately in Figure 64 from the output port results (S 22 and S 12), which are shown in
Figure 65.
-10
-15
-20
-30
-35
— Printed S11
Ribbon Bonds S11
“ “ Simulated Printed!S11
Printed 821
Ribbon Bonds 821
Simulated Printed S21
•40
-50
5
10
15
20
25
30
35
40
Frequency (GHz)
Figure 64: Sn and S 21 results o f CPW to GaAs microchip. Simulated with modified model to reflect
printed appearance vs. measured with printed interconnects vs. measured with ribbon bonds.
0
77
-10
-15
N
N -30
„
-35
Printed S22
Ribbon Bonds S22
•— Simulated Printed 822
Printed S12
Ribbon Bonds 312
— Simulated Printed S12
-40
-45
•50
5
10
15
20
25
30
35
40
Frequency (GHz)
Figure 65: S22 a n d S i2 results o f C PW to GaAs m icrochip. Sim ulated w ith m odified m odel to reflect
p rin ted ap p earan ce vs. m easu red w ith p rin ted interconnects vs. m easured w ith ribbon bonds.
The modification o f the model helped shift the frequency resonances closer to those of
the measured results. Remaining discrepancies between measured and simulated results
are likely due to inconsistencies between the simulated model and measured sample.
VI. CONCLUSION
This work explored the design and fabrication o f printed interconnects between
components in microwave devices. Traditional wire and ribbon bond interconnects often
have unwanted inductances and uncontrolled impedances. A GaAs microchip was
modeled between two coplanar waveguides as a test case. Dielectric material was
inserted between the GaAs and CPW and printed interconnects were modeled on top o f
the dielectric. The dielectric material and interconnect thickness was optimized through
simulations. Based on the simulated results and available materials the Creative Materials
78
118-12 dielectric ink was chosen. A thermal and structural analysis o f the printed
interconnects between the CPWs and GaAs microchips were performed. Electrical and
mechanical material characteristics o f the dielectric and conductive inks were measured
and incorporated into the simulations. Finally, printed interconnects were printed between
two coplanar waveguides using the Optomec Aerosol Jet printer. A pillow material was
used to build height in the gap between the CPWs and the dielectric ink was deposited on
top o f the pillow material, followed by the printed interconnects. A second prototype o f a
CPW and GaAs microchip was fabricated. The gap was again filled with a pillow
material and covered with the Creative Materials 118-12 dielectric material. Once the
dielectric was cured, conductive interconnects were printed on top o f the dielectric
material. The devices with the printed interconnects and devices with ribbon bond
interconnects were measured with GSG probes. Measured results o f the prototype
showed very good consistency with both simulated results and devices with traditional
ribbon bond interconnects. The results indicate that the method o f printing conductive
interconnects between high frequency devices is a viable alternative to traditional wire
and ribbon bond interconnects. Additionally, with the use o f additive manufacturing, the
dimensions o f the conductive traces and the dielectric material can be optimized for more
impedance matched interconnects, resulting in lower return losses in microwave devices.
VII. FUTURE WORK
Some future work that can be applied to this thesis includes printing more
optimized and impedance matched interconnects. The work done in this thesis provides a
proof o f concept to show the potential for printed interconnects between microwave
devices, but the next step is to design and optimize impedance matched interconnects
79
with a reduced inductance. Another item for future work includes additively writing the
dielectric ink in the gap between the components. There were issues with the solvent in
the ink being used reacting with the syringes in the nScrypt, causing air bubbles in the
syringe, making it difficult to control the print parameters. Additionally, the thermal and
structural analysis o f the model indicated that the CTE mismatches could cause
expansions o f the dielectric material when heated. Both o f these factors indicate that
development o f materials with better performance is required.
VIII. LITERATURE CITED
[1] G. Harman, “The Technical Introduction to the Third Edition,” in Wirebonding in
Microelectronics, 3rd ed. New York: McGraw Hill, 2010, ch. 1, sec. 1.1, pp. 3-4.
[2] G. R. Blackwell, “CHAPTER TITLE,” in The Electronic Packaging Handbook, xth
ed. City: CRC-Press, 2000, ch. X, sec. x, pp. xxx-xxx.
[3] F. E. Terman, “Circuit Elements,” in Radio Engineers ’ Handbook, 1st ed., New York:
McGraw-Hill, 1943, ch.2 sec. 2, pp. 47-57.
[4] H. K. Kung e ta l., "Empirical Equation o f Wire Sag Model for Semiconductor
Packaging With Numerical and Experimental Verification," in IEEE Transactions on
Components, Packaging and Manufacturing Technology, vol. 3, no. 1, pp. 157-167,
Jan. 2013.
[5] H. K. Kung, et a l , “The wire sag problem in wire bonding technology for
semiconductor packaging,” in M icroelectronics Reliability, vol. 53, no. 2, pp. 288296, Feb. 2013.
[6] 2017, January. Printed Electronics M arket Size to Reach USD 19.15 Billion by 2025
[Online]. Available: http://www.grandviewresearch.com.
[7] G. Scardera et al., "Screen-printed dopant paste interdigitated back contact solar
cells," in 2015 IEEE 42ndPhotovoltaic Specialist Conference (PVSC '), New Orleans,
LA, 2015, pp. 1-4.
[8] A. Eshkeiti et a l , "Screen Printing o f Multilayered Hybrid Printed Circuit Boards on
Different Substrates," in IEEE Transactions on Components, Packaging and
Manufacturing Technology, vol. 5, no. 3, pp. 415-421, March 2015.
80
[9] T. Bjominen, et al. , "Testing and modeling the performance o f stretchable screen
printed UHF RFID tag under strain," 2016 IEEE International Symposium on
Antennas and Propagation (APSURSI),.Fajardo, 2016, pp. 465-466.
[10] R. Valmiro, et al., "A silk-screen printed RFID tag antenna," 2015 Asia-Pacific
M icrowave Conference (APMC), Nanjing, 2015, pp. 1-3.
[11] S. K. Sarkar et al., "Flash light sintering o f silver nanoink for inkjet printed thin film
transistor on flexible substrate," in IEEE Transactions on Nanotechnology, vol. PP,
no. 99, pp.1-1
[12] S. Kim et al., "Inkjet-printed antennas, sensors and circuits on paper substrate,"
in IETM icrowaves, Antennas & Propagation, vol. 7, no. 10, pp. 858-868, July 16
2013.
[13] M. Ahmadloo and P. Mousavi, "A novel integrated dielectric-and-conductive ink 3D
printing technique for fabrication o f microwave devices," 2013 IEEE MTT-S
International M icrowave Symposium D igest (MTT), Seattle, WA, 2013, pp. 1-3.
[14] C. Mariotti, et a l , "Development o f Low Cost, Wireless, Inkjet Printed Microfluidic
RF Systems and Devices for Sensing or Tunable Electronics," in IEEE Sensors
Journal, vol. 15, no. 6, pp. 3156-3163, June 2015.
[15] D. Unnikrishnan ,et al., "CPW-Fed Inkjet Printed UWB Antenna on ABS-PC for
Integration in Molded Interconnect Devices Technology," in IEEE Antennas and
Wireless Propagation Letters, vol. 14, n o ., pp. 1125-1128, 2015.
[16] C. Mariotti, e ta l., "Demonstration and charaterization o f fully 3D-printed RF
structures," 2015 IEEE 15th M editerranean M icrowave Symposium (MMS), Lecce,
2015, pp. 1-4.
[17] J. Bito, et al., "Fully inkjet-printed multilayer microstrip patch antenna for Ku-band
applications," 2014 IEEE Antennas and Propagation Society International
Symposium (APSURSI), Memphis, TN, 2014, pp. 854-855.
[18] J. H. Daniel, “Printed electronics: technologies, challenges and applications,” in
International Workshop on Flexible and Printed Electronics (IWFPE 10), Muju
Resort, Korea, 2010.
[19] “nScrypt Specification Sheet: SmartPump,” [Online]. Available:
http://www.nscrypt.com/wp-content/uploads/2017/02/2016-SmartPump-Gen2.pdf
[20] J. Chou, et al., “Aerosol Jet Printable Metal Conductive Inks, Glass Coated Metal
Conductive Inks and UV-Curable Dielectric Inks and Methods o f the Same,” US
Patent 2014/0035995 A l, Feb. 6, 2014.
81
[21] M. Haghzadeh, “Printed Ferroelectric Nanocomposite Based Dielectric Inks for
Reconfigurable RF and Microwave Applications,” Ph.D. dissertation, Electrical and
Computer Engineering Department, University o f Massachusetts Lowell, Lowell,
MA, 2016.
[22] T. Seifert, et al. “Aerosol Jet Printing o f Nano Particle Based Electrical Chip
Interconnects,” M aterials Today: Proceedings, vol. 2, Issue 8, pp. 4362-4271, Nov.
2015.
[23] B. K. Tehrani, et al., "Inkjet-printed 3D interconnects for millimeter-wave systemon-package solutions," 2016 IEEE MTT-S International M icrowave Symposium
(IMS), San Francisco, CA, 2016, pp. 1-4.
[24] T. R. Stockert, et a l , S. A. Mauger and M. F. A. M. van Hest, "Printed module
interconnects," 2015 IEEE 42nd Photovoltaic Specialist Conference (PVSC), New
Orleans, LA, 2015, pp. 1-4.
[25] S. Stoukatch et al., "Evaluation o f Aerosol Jet Printing (AJP) technology for
electronic packaging and interconnect technique," 2012 4th Electronic SystemIntegration Technology Conference, Amsterdam, Netherlands, 2012, pp. 1-5.
[26] M. Mengel, I. Nikitin, “Inkjet printed dielectrics for electronic packaging o f chip
embedding modules.” in M icroelectronic Engineering, vol. 87, no.4, pp. 593-596,
April 2010.
[27] K.K.B. Hon, et al., “Direct writing technology - Advances and developments,” in
CIRP Annals - Manufacturing Technology, vol. 57, no. 2, pp. 601-620, 2008.
[28] V. Pekkanen, et al., “Utilizing inkjet printing to fabricate electrical interconnections
in a system-in-package,” in M icroelectronic Engineering, vol. 87, no. 11, pp. 23822390, November 2010.
[29] A. A. Gupta, et a l , "Aerosol Jet Printing for printed electronics rapid
prototyping," 2016 IEEE International Symposium on Circuits and Systems (ISCAS),
Montreal, QC, 2016, pp. 866-869.
[30] J. A. Paulsen, et al., "Printing conformal electronics on 3D structures with Aerosol
Jet technology," 2012 Future o f Instrumentation International Workshop (FIIW)
Proceedings, Gatlinburg, TN, 2012, pp. 1-4.
[31] D. M. Pozar, Microwave Engineering: Wiley, 1997.
82
[32] “Creative Materials: 118-12 Solvent-Resistant Dielectric Ink,” [Online]. Available:
https://server.creativematerials.com/datasheets/DS_l 1 8 1 2 .p d f
[33] “Dow Coming 3140 RTV Coating,” [Online]. Available:
http://www.dowcoming.com/DataFiles/090276fe802eae31 .pdf
[34] W. K. W. Ali and S. H. Al-Charchafchi, "Using equivalent dielectric constant to
simplify the analysis o f patch microstrip antenna with multi-layer substrates," IEEE
Antennas and Propagation Society International Symposium, Atlanta, GA, 1998, pp.
676-679.
[35] A. M. Nicolson and G. F. Ross, "Measurement o f the Intrinsic Properties o f
Materials by Time-Domain Techniques," in IEEE Transactions on Instrumentation
and Measurement, vol. 19, no. 4, pp. 377-382, Nov. 1970.
[36] P.G. Bartley and S. B. Begley, "A new technique for the determination o f the
complex permittivity and permeability o f materials," 2010 IEEE Instrumentation 8c
Measurement Technology Conference Proceedings, Austin, TX, 2010, pp. 54-57.
[37] J. Baker-Jarvis, E. J. Vanzura and W. A. Kissick, "Improved technique for
determining complex permittivity with the transmission/reflection method," in IEEE
Transactions on Microwave Theory and Techniques, vol. 38, no. 8, pp. 1096-1103,
Aug. 1990.
[38] W. B. Weir, "Automatic measurement o f complex dielectric constant and
permeability at microwave frequencies," in Proceedings o f the IEEE, vol. 62, no. 1,
pp. 33-36, Jan. 1974.
[39] C. N. Works, T. W. Dakin and F. W. Boggs, "A resonant-cavity method for
measuring dielectric properties at ultrahigh frequencies," in Electrical Engineering,
vol. 63, no. 12, pp. 1092-1098, Dec. 1944.
[40] M. Haghzadeh, C. Armiento and A. Akyurtlu, "Microwave dielectric
characterization o f flexible plastic films using printed electronics," 2016 87th
ARFTG Microwave Measurement Conference (ARFTG), San Francisco, CA, 2016,
pp. 1-4.
[41] Zhengxiang Ma et al., "RF measurement technique for characterizing thin dielectric
films," in IEEE Transactions on Electron Devices, vol. 45, no. 8, pp. 1811-1816,
Aug 1998.
[42] M. Haghzadeh; C. Armiento; A. Akyurtlu, "All-Printed Flexible Microwave
Varactors and Phase Shifters Based on a Tunable BST/Polymer," in IEEE
Transactions on Microwave Theory and Techniques , vol.PP, no.99, pp.1-13
83
[43] "Understanding Thermal Conductivity Methods - C-Therm - Thermal Conductivity
Instruments". [Online]. Available: Ctherm.com. N.p., 2017. Web. 6 Apr. 2017.
[44] "Thermal Conductivity And Thermal Diffusivity". [Online]. Available:
http://www.tainstruments.com/wp-content/uploads/BRQCHThermalConductivityDiffusivity-2014-EN.pdf.
[45] D. Cahill, “thermal conductivity measurement from 30 to 750 K: The 3co Method,”
Review o f Scientific Instruments, vol. 61, no. 2, pp. 802-808, February 1990.
[46] "TA Instruments Thermal Analysis,".[Online]. Available:
http://www.tainstruments.com/pdf/brochure/2011 %20TGA%20Brochure.pdf
[47] Dow Coming 3145 RTV MIL-A-46146 Adhesive Sealant - Clear,” [Online].
Available: http://www.dowcoming.com/DataFiles/090276fe801f97f8.pdf
84
IX. BIOGRAPHICAL SKETCH OF AUTHOR
Elicia Harper transferred to University o f Massachusetts Lowell in 2013 with an
associates degree in Mathematics and an associates degree in Physics from Bunker Hill
Community College. She received her bachelor’s o f science degree from University o f
Massachusetts Lowell in 2015. Her research for her master’s degree was completed at the
Raytheon UMass Lowell Research Institute (RURI) which focuses on flexible printed
electronics and additive manufacturing. She interned at Raytheon Company for two
summers and will be joining the company full time.
Документ
Категория
Без категории
Просмотров
0
Размер файла
3 953 Кб
Теги
sdewsdweddes
1/--страниц
Пожаловаться на содержимое документа