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Virtual prototyping and optimisation of microwave ignition devices for the internal combustion engine

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BIAS AND TEMPERATURE DEPENDENT NOISE MODELING OF MICROWAVE
AND M ILLIM ETER-W AVE FIELD EFFECT TRANSISTORS
by
STEVEN MARC LARDIZABAL
A dissertation submitted in partial fulfillment
o f the requirements for the degree o f
Doctor o f Philosophy in Electrical Engineering
Department o f Electrical Engineering
University o f South Florida
December 1997
Major Professor: Lawrence P. Dunleavy, Ph.D.
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UMI Number: 9815445
Copyright 1998 by
Lardizabal, Steven Marc
All rights reserved.
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Graduate School
University o f South Florida
Tampa, Florida
CERTIFICATE OF APPROVAL
Ph.D. Dissertation
This is to certify that the PhD. Dissertation o f
STEVEN MARC LARDIZABAL
with a major in Electrical Engineering has been approved by
the Examining Committee on April 24, 1997
as satisfactory for the dissertation requirement
for the Doctor o f Philosophy degree
Examining Cor,'v,;" “ *'
Major Professor Lawrence P. Dunleavy, PI
Member Rudrilf^Hennirtg, D. Eng. S<
Member: Dennis Killinger, PhD.
Member: Glen Bpsterfield, PO X
Member Thomas Weller, PhD.
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To my mother andfather
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ACKNOWLEDGMENTS
I would like to thank all those that helped me to reach this goal. I would like to
thank my advisor Professor Lawrence Dunleavy for the opportunity and support in
pursuing my Ph.D. I would also like to thank my dissertation committee members for
their time in reviewing this work. For the financial support o f my work I am very
grateful to; Hughes Aircraft Company GAO, Texas Instruments DSEG, Martin Marietta,
the Florida High Technologies and Industries Council, the United States A ir Force
AFOSR Summer Research Program (Contract #F48620-90-C-0076), and Raytheon/ESystems EC I.
I would like to thank Professor RudolfHenning for providing me the opportunity
to study microwave engineering and for his genuine interest in my involvement with
professional societies. I must thank Dr. Z. Bardai, Dr. T. Midford and Dr. C. Chang of
Hughes Gallium Arsenide Operations for: the use o f their laboratory measurement
facilities, their generous interest in my research and for their time and hospitality during
our visits. I would also like to thank Dr. P. Carr, M r. R Webster and Mr. A. Slobodnik
o f the United States AFOSR Electromagnetics Research Directorate for an interesting
and productive summer studying noise parameter measurements and modeling. I would
like to thank Dr. R. Anholt for his software donation and discussions on temperature
dependent small signal modeling. The samples o f InP HEMTs provided by Hughes
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Research Laboratories from Dr. M . Matloubian are much appreciated. I would also like
to thank Dr. A. Boudiaf for the sampled temperature dependent data from his
measurement system and for his discussion on microwave noise parameter measurement
techniques. Thanks to M r. M att Smith, Dr. A. Nauda, and Mr. R_ Roeder for their
support and collaboration on a very successful project using the models developed here.
Discussions on FET modeling, between hectic periods assembling papers and reports,
with Dr. P. Winson and Dr. M . Calvo are greatly appreciated. For her help in editing and
processing this document, and her love and patience in supporting my work I would like
to thank Ms. Michelle Mawicke.
I would also like to acknowledge the generous contributions that have been made
to the laboratory which have enhanced my work. These include software donations from
HP/EEsof, Compact Software and GATEWAY Modeling Inc. Numerous hardware
donations are also acknowledged including wafer probes from GGB Industries and
Cascade Microtech. I would also like to thank Mr. V. Adamian and Mr. M . Fennelly o f
Automatic Testing and Networking Co. for the donation o f the noise parameter test-set
used in this work and their support in answering my questions.
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TABLE OF CONTENTS
LIST OF TABLES ....................................................................................................... vi
LIST OF FIGURES......................................................................................................... vii
LISTOFSYM BOLS .....................................................................................................xv
CHAPTER 1. INTR O D U C TIO N.....................................................................................1
1.0 IN TR O D U C TIO N ...........................................................................................1
1.1 PROBLEM SET-UP/DEFINITIO N................................................................ 4
1.2 COMPARISON OF NOISE MODELS ..........................................................6
1.2.1 FET Noise Fundamentals.................................................................. 7
1.2.2 Previous Temperature Dependent FET Noise Models ................... 10
1.3 SUMMARY OF OBJECTIVES.................................................................... 15
1.4 CHAPTER SUMMARY: ORGANIZATION OF THIS W O R K ................... 16
CHAPTER 2. SEMICONDUCTOR DEVICE THEORY ..............................................21
2.0 IN TR O D U C TIO N ........................................................................................ 21
2.1 FIELD EFFECT TRANSISTOR PHYSICAL PRINCIPLES .....................22
2.1.1 Energy Band Structure ..................................................................27
2.1.3 Equivalent Circuit Model Relations................................................32
2.1.3.1 Voltage Gain .............................................................................. 34
2.1.3.2 Modulation Efficiency..................................................................34
2.1.4 Important III-V FET Channel T yp es..............................................36
2.2. A REVIEW OF PHYSICAL MODELS OF FET NOISE ........................... 41
2.2.1 Types o f FET Noise........................................................................41
2.2.2 Velocity Saturated N oise................................................................44
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2.2.3 Numerical Noise Modeling Issues .............................
47
2.3 CHAPTER S U M M A R Y ............................................................
48
CHAPTER 3 C IR C U IT MODELING TH EO R Y..........................................
50
3.0 IN TR O D U C TIO N ......................................................................
50
3.1 EQ UIVALENT CIRCUIT MODELS OF N O IS E .....................
51
3 .2. D E FIN ITIO N OF NOISE FIGURE ..........................................
57
3.3 NOISE CORRELATION M A TR IX REPRESENTATION
60
3 .4 FET NOISE MODELS ..............................................................
64
3.5 TWO-PORT NOISE PARAMETER IN TE R R E LA T IO N .......
67
3.5.1 Interrelations o f the Four Noise Parameters.................
67
3.5.2 Data Comparisons and Examples.................................
74
3 .6 CHAPTER S U M M A R Y ............................................................
75
CHAPTER 4 A TEMPERATURE DEPENDENT MODEL FOR THE FET
76
4.0 IN TR O D U C TIO N ......................................................................
76
4.1 M ATERIAL FACTORS: EMPIRICAL MODEL SU R VEY. . . .
77
4.2 EXPERIM ENTALLY BASED TEMPERATURE MODELS ..
80
4.3 A TABLE BASED NOISE M O D E L ..........................................
82
4.4 FIGURES OF M ERIT: RELATIONS TO NOISE MODELING
84
4.5 CHAPTER S U M M A R Y ............................................................
87
CHAPTER 5. ANALYSIS AND MODEL EXTRACTION METHODS ..
88
5.0 FET NOISE MODELING TECHNIQUES ...............................
88
5.1 PARASITIC FET ELEMENT EXTRACTION .........................
91
5.1.1 Parasitic Capacitance Extraction.................................
93
5.1.2 Parasitic Inductance and Resistance Extraction ...........
97
5.1.2.1 Inductance Extraction...............................................
99
5.1.2.2 Parasitic Resistance Extraction for MESFET’s .........
99
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5.1.2.3 Parasitic Resistance Extraction for HEMTs and PHEM Ts
102
5.1.2.4 Assumptions and Comparison to Other Methods....................... 10S
5.1.3 Leakage Resistance M odels........................................................ 110
5.1.3.1 Leakage Resistor Extraction...................................................... 113
5.1.3.2 Noise Analysis o f Leakage Resistors..........................................114
5.2 INTR IN SIC FET MODEL ELEMENT EXTRACTION ........................... 116
5.3 INTRINSIC FET NOISE GENERATOR EXTRACTION
....................... 118
5.3.1 Intrinsic Noise Generator Extraction Technique.........................119
5.3.2 Noise Coefficient Selection Procedure..........................................122
5.4 CHAPTER S U M M A R Y .............................................................................127
CHAPTER 6. MEASUREMENT TECHNIQUES........................................................ 130
6.0 IN TR O D U C TIO N .......................................................................................130
6.1 ON-WAFERS-PARAMETER MEASUREMENT TECHNIQ UES
130
6.2 MICROWAVE NOISE PARAMETER M EASUREM ENTS..................... 135
6.2.1 Microwave Noise Figure Measurements........................................136
6.2.2 Conventional Noise Parameter Determination Technique
139
6.2.3 Review o f the Numerical Determination o f Noise Parameters . . . 140
6.3 ALTERNATIVE METHODS FOR NOISE PARAMETER DETERMINATION
............................................................................................................. 142
6.3.1 A Single Tuner State Noise Parameter Determination Technique 143
6.3.2 A Generalized Noise Figure Equation ..........................................145
6.4 RESULTS FOR A NOVEL DETERMINATION OF FET NOISE
PARAMETERS.....................................................................................150
6.5 CHAPTER S U M M A R Y ............................................................................ 153
CHAPTER 7. FET NOISE M ODELING RESULTS
..................................................154
7.0 MODELING RESULTS ............................................................................ 154
7.1 EQUIVALENT CIRCUIT PARAMETER TR EN DS..................................155
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7.2 LINEAR TEMPERATURE MODELS ................................................... 164
7.3 MODEL THERMAL CO EFFICIENTS......................................................168
7.3.1 Extrinsic Small Signal Model Thermal Coefficients .....................168
7.3.2 Intrinsic Small Signal and Noise Model Thermal Coefficients . . . 171
7.3.2.1 GaAsMESFET Thermal Coefficients........................................172
7.3.2.2 GaAs PHEMT Thermal Coefficients..........................................173
7.3.2.3 InP HEMT Thermal Coefficients................................................178
7.3.3 Discussion of Noise Temperature Thermal Coefficients...............178
7.3.4 Noise Temperature Correlation....................................................182
7.4 SMALL SIGNAL MODEL PERFORMANCE ..........................................184
7.5 NOISE PARAMETER SIM ULATION RESULTS ................................... 191
7.6 APPLICATION OF THE FET NOISE MODEL AT
M ILLIMETER-W AVES ......................................................................197
7.7 COMPARISON OF NOISE PERFORMANCE......................................... 200
7.8 CHAPTER S U M M A R Y ............................................................................203
CHAPTER 8. THEORY AND MODELING OF FET BASED NOISE SOURCES
.........................................................................................................................204
8.0 IN TR O D U C TIO N ..................................................................................... 204
8.1 AN IMPROVED THEORY AND MODELING OF FET NOISE SOURCES
............................................................................................................ 204
8.1.1 Assessment of Previous W o rk ..................................................... 207
8.1.2 Alternate Noise Parameters......................................................... 211
8.1.3 Source Temperature o f One Port Noise Generators.................... 212
8.1.4 Derivation o f the Reverse Noise Measure ...................................214
8.1.5 CAD and Simulation ofNoise Source Temperature.................... 217
8.2 HYBRID CIRCUIT IM PLEM EN TA TIO N ............................................... 219
8.2.1 Design Approach..........................................................................219
8.2.2 Measurements and Results........................................................... 220
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226
8.3 CHAPTER SUMMARY
CHAPTER 9. CONCLUSIONS AND RECOMM ENDATIONS................................. 227
9.0 SUMMARY OF W O R K ............................................................................ 227
9.1 SPECIFIC TECHNICAL CONTRIBUTIO NS........................................... 227
9.1.1 Novel Bias and Temperature Dependent Model o f FET Noise
. 228
9.1.2 Analysis and Model Extraction Methods ..................................... 229
9.1.3 FET Noise Generator M odeling....................................................229
9.1.4 Novel Method o f Determining FET Noise Parameters.................230
9.1.5 Temperature Dependent Modeling o f FET Noise Generators . . . 231
9.1.6 Investigation o f FET Noise Performance at Millimeterwave Frequencies ...................................................................... 231
9.1.7 Improved Modeling and Design ofFET-Based Noise Sources . . 232
9.2 RECOMMENDATIONS FOR FURTHER W O R K ................................... 233
9.2.1 Noise Model Enhancements and CAD Applications.....................233
9.2.2 Model Extraction Advancements................................................. 234
9.2.3 FET Noise Modeling at Millimeter-wave Frequencies .................234
9.2.4 Improved Determination o f FET Noise Parameters .....................234
APPENDIX A
ANALYSIS OF NOISY TWO-PORT CORRELATION M A TR IX
TRANSFORMATIONS.................................................................................... 235
APPENDIX B PROCEDURE FOR CALCULATING THE INTRINSIC FET NOISE
MODEL COEFFICIENTS FROM MEASURED D A T A ................................. 239
APPENDIX C TEST BENCH EQUATIONS FOR NOISE MODEL EXTRACTION
......................................................................................................................... 242
REFERENCES............................................................................................................. 249
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LIST OF TABLES
Table 1
Previous FET Noise Models and Their Noise Model Coefficients.............. 9
Table 2
FET Technologies Studied in This Work ..................................................14
Table 3
FET Channel Material Band Structure Parameters and Properties............. 37
Table 4
m -V FET Material Systems and Layering Structure.................................38
Table 5
MESFET A1 cold FET data for attracting the parasitic resistors R^,
Rg, R j and R ^, as well as the diode parameters a and n ........................ 100
Table 6
Results o f ideality factor fit and parasitic resistor attraction for
MESFET A1 and the mean values for seven tested samples o f the
same FET.................................................................................................101
Table 7
Calculated channel resistance o f heterostructure FETs including
related geometric and material data......................................................... 107
Table 8
Z-Parameters for Comparing o f Parasitic Resistance Extraction o f
(PHEMT A2) extrinsic resistances...........................................................109
Table 9
Mean value and relative standard deviation from the mean for gmand
Rds..........................................................................................................161
Table 10
Mean and relative standard deviation for extracted small signal model
parameters for a sampling (n=10) of FET A2 ....................................... 163
Table 11
Linear correlation coefficient, r, for the thermal coefficients o f the
intrinsic FET small signal model elements and Id s of PHEMT A2
167
Table 12
Table-model coefficients m and b, linear correlation coefficient r and
thermal coefficient P for FETs A1 and A2...............................................169
Table 13
Results for hybrid circuit prototype simulation for T0^ l and
versus Vv
(V ) for V „=1(V ) at 18GHz and 22GHz.................................................. 225
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LIST OF FIGURES
Figure 1 Microwave frequency noise equivalent circuit model o f a FET where
intrinsic denotes the active channel region under the gate and extrinsic
denotes circuit elements that model the connections to the channel..................... 8
Figure 2 Comparison o f layer structures o f MESFET (left) and HEMT (right)
cross-sectional views. Key MESFET dimensions shown are the channel
height “a” and the depletion depth “h” beneath the shaded depletion
region The gate length Lg and unit gate width “Z” are common to both
FETs depicted.................................................................................................... 22
Figure 3 Room temperature D C -IV curves for a depletion mode Ir^Ga^^As/GaAs
PHEMT............................................................................................................. 23
Figure 4 Energy diagrams for the conduction band in a GaAs/AlGaAs HEMT
under (a) forward bias, (b) reverse bias near pinch-off. ................................... 25
Figure 5 Illustration o f A^^Ga^sAs E-k diagram (Energy - Momentum or
k Vector diagram). Showing the three important conduction band valleys
and their energy minimums at T=300K (T, L, and X ) and the light-hole
(lh) and heavy-hole (hh) bands in k-space (reciprocal space)............................. 28
Figure 6 Electron average velocity (106 cm/s) versus electric field (kV/cm) for
GaAs, In0J3Ga04 7 As and InP at T = 3 0 0 K ........................................................ 30
Figure 7 Illustration of a general material layering structure for MESFETs and
HEMTs.............................................................................................................. 38
Figure 8 Physical relation o f FET noise processes and the geometry o f a typical
GaAs PHEMT (1) thermal noise, (2) Johnson noise, (3) high field
diffusion noise and (4) shot noise due to gate leakage....................................... 42
Figure 9 Illustration o f output noise power spectral density, Sfc (A 2/H z) versus
frequency (GHz) for a typical microwave FET.................................................. 44
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Figure 10 Noisy two-port equivalent circuit models for (a) noisy two-port
admittance and (b) an equivalent noiseless two-port and with associated
noise generators i^ and i^ ............................................................................. 52
Figure 11 Noisy two-port networks used for FET noise modeling (a) parallel noise
generators and a noiseless admittance matrix (b) hybrid parameter
network matrix and series/parallel noise generators and (c)
series/parallel noise generators and a noiseless chain m atrix.......................... 54
Figure 12 Microwave equivalent circuit model for the noisy FET, characterized by
two equivalent noise generators and i * . ..................................................... 64
Figure 13 Microwave equivalent circuit model for the noisy FET, characterized by
two parameters Tg and Td. ............................................................................ 66
Figure 14 Simulated effect o f a variable inductor,
(pH) on the factors K (
and K2 when placed at the source terminal o f FET C l. Lines with
symbols representing K 2 find a minimum value, equal to Kb where the
reactive component o f Zopt is tuned out by the inductive reactance o f
............................................................................................................... 75
Figure 15 Small signal model o f the FET including intrinsic (within the dotted
lines) and extrinsic elements............................................................................ 89
Figure 16 Flow chart summarizing procedure for small signal model extraction
(left) and noise model extraction (right). Frequency considerations are
indicated for typical FETs used in this work. ................................................90
Figure 17 Flow chart of small signal S-parameter bias conditions for FET
modeling performed in this work. Each condition relates a simplified
FET topology from which equivalent circuit elements are extracted
through direct calculations.............................................................................. 92
Figure 18 Simplified small signal equivalent circuit o f the FET bias under
“pinched” modeling conditions, ^ = 0 , V ^ V ^ -2 (V )................................... 93
Figure 19 Simplified pinched-FET model for use with gate width scaling
measurements..................................................................................................94
Figure 20 Illustration o f a typical metalization layout for FETs studied in this
work. Scale o f gate length,
is exaggerated for illustration.................... 96
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Figure 21 Pinched FET capacitors Cu and
(£F) versus FET gate width Cam).
Stem and wing lines indicate minimum and maximum values for S
samples at each gate width. .......................................................................... 96
Figure 22 Equivalent circuit model o f the forward biased “Cold FET” used for
extraction o f parasitic inductance, resistance, and the distributed gate
diode..............................................................................................................97
Figure 23 Comparison (left-axis) o f cold FET Re[ZtJ (Ohms) versus
(V ) for
FET A2 at various gate widths (pm), and HEM T C l. Also compared
(right-axis) are forward gate currents for A2 and C l,
^ (mA) versus V ,, (V ).................................................................................. 102
Figure 24 Cold HEM T extracted real impedances Re[Zn], Re[Z12] and RejZ^]
(Ohms) versus Frequency (GHz) for PHEMT A2 (W g = 300 pm).
Re[Zn] illustrates the predicted l/o>2 dependence due to the gate
capacitance. A constant (o<2% ) value is extracted above 10 GHz. ...........104
Figure 25 Traditional FET small signal model with resistor
added to simulate
the equivalent effect o f a gate-to-source leakage current...............................I l l
Figure 26 Noisy FET model for the PHEMT with a leakage component due to
substrate currents which flow underneath the FET channel and the drain
and gate contacts...........................................................................................112
Figure 27 Extracted values ofR ^ (Ohms) versus gate voltage
(V ) for several
types o f 300pm gate width FETs. The magnitude R^ for FET A2
reveals why this element is not negligible with respect to the modeling
of S-parameter and noise parameter data for that FET.................................. 113
Figure 28 Flow chart o f noise modeling algorithm used in this work. The bold
lines distinguish the normal path without modeling iteration........................ 124
Figure 29 Flow chart o f noise model coefficient post-processing algorithm for Tp
T * P, R, and C..............................................................................................125
Figure 30 Schematic o f small signal S-parameter measurement system used in this
work..............................................................................................................131
Figure 31
Ground Signal Ground (GSG) RF probe and illustrated FET configuration for the
wafer-level data measured in this work..........................................................131
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Figure 32 Schematic o f the automatic noise parameter and S-parameter
measurement system used in this work. The software used to control
the measurement system is ATN’s NP5 noise parameter measurement
software, which was modified at USF for an equipment specific setup
and to include large sweeps of bias (greater than 40 points)..........................136
Figure 33 Simplified schematic o f noise figure measurement system. Along with
the S-parameters o f each two-port shown here, the quantities r i 2 3 and
Gt 2 are used to deembedded the DUT noise figure NFZ. ........................... 137
Figure 34 Comparison o f measured and modeled noise parameters using the single
source state algorithm withZs=50 Ohms. The FET is a 0.25*300 pm
GaAs MESFET biased at V ^ V and % 15Idss............................................. 151
Figure 35 P, R and Im[C] versus state number for 16 different tuner source
impedances where noise figure was measured over the Smith Chart
152
Figure 36 Plot o f measured MESFET I* (mA) and experimentally extracted gm
(mS) versus Vv (V ) for two temperatures......................................................156
Figure 37 Plot o f experimentally extracted MESFET bias dependence for Rj and
R * (Ohms) versus
(V ) for two temperatures............................................ 156
Figure 38 Plot o f measured PHEMT I* (mA) and experimentally extracted g,,,
(mS) versus V9 (V ) for two temperatures......................................................157
Figure 39 Plot o f experimentally extracted PHEMT bias dependence for Rj and R^
(Ohms) versus
(V ) for two temperatures................................................. 157
Figure 40 Comparison o f extracted Tg (K) versus
(V ) for a variety o f FETs
modeled in this work at V * in the saturated D C -IV region with T=298
K ................................................................................................................... 159
Figure 41 Comparison o f extracted Td (K) versus
(V ) for a variety o f FETs
modeled in this work at
in the saturated D C -IV region with T=298
K ................................................................................................................... 159
Figure 42 Room temperature variation of extracted transconductance and output
resistance for FET A2 versus
(V ) with a one standard deviation
envelope for five samples...............................................................................162
Figure 43 Room temperature variation o f extracted transconductance and output
resistance for FET A1 versus Vgs (V ) with a one standard deviation
envelope for five samples...............................................................................162
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Figure 44 Linear trend o f the measured threshold voltage V * (V ) versus
Temperature (°C ) for the MESFET A l, as measured on a SUMMIT
probe station. Data represents 1.85 m V/°C variation for V ^ ......................164
Figure 45 Piece-wise linear trend o fthe measured threshold voltage
(V ) versus
Temperature (°C ) for the PHEMT A2, as measured on a SUMMIT
probe station. Data represents less than 0.2 m V/°C variation of
above 0 °C.................................................................................................... 165
Figure 46 Experimentally extracted gm (mS) and Ft (GHz) versus temperature
(C el.) for MESFET A l and PHEMT A2 measured on a SUMMIT
probe station over -55°C to 85°C. Additional PHEMT A2 data
measured at USF illustrates linear trend o f data from 25 °C to 85°C............ 166
Figure 47 Thermal coefficients, P (1CT3/°C ), for the parasitic resistors o f FETs A l,
A2 and C l as determined by a linear fit o f extracted values for
25°C £ T £ 85°C..........................................................................................170
Figure 48 Intrinsic model element thermal coefficients P (10-3/°C) for MESFET
A l (a) gm and C^ and (b) Rj and
versus
(V ) for several Vds
biases............................................................................................................ 174
Figure 49 MESFET A l thermal coefficients p (10-3/°C) of noise temperatures (a)
Tg and (b) T^ versus
(V ) for several V j, biases.......................................175
Figure 50
Intrinsic model element thermal coefficients P (10-3/°C) for PHEMT
A2 (a) gmand C& and (b) Rj and Rjs, versus
(V ) for several Vds
biases............................................................................................................176
Figure 51 PHEMT A2 thermal coefficients P (10-3/°C ) o f noise temperatures (a)
Tg and (b) Td, versus
(V ) for several Vds biases...................................... 177
Figure 52 Intrinsic model element thermal coefficients P (10-3/°C) for HEMT C l
(a) g,,, and C „ Rj and R j,, and (b) Tg and Td versus V (V ) for
1
(V )................................................................................................................179
Figure 53 Influence of bias and temperature on extracted correlation o f gn/gds
versus C ^C ^ for (a) FETs A l and C l and (b) FET A2. Two
temperature data sets include 25°C and 85°C...............................................181
Figure 54 Correlation for thermal coefficients o f noise temperatures Tg and Td
over bias for the PHEMT A2. Solid line represents linear trend for all
bias points.................................................................................................. 182
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Figure 55 Correlation for thermal coefficients o f noise temperatures Tg and Td
over bias for MESFET A l. Solid line represents linear trend for all bias
points..........................................................................................................183
Figure 56 Correlation for thermal coefficients o f noise temperatures Tg and Td
over bias for HEMT C l. Solid line represents linear trend for all bias
points..........................................................................................................184
Figure 57 Comparison o f 25°C measured and modeled FET A l S-parameters. V *
is 3V and
is swept at -0.2 V (squares), -0.4 V (stars) and -0.8 V
(circles)...................................................................................................... 186
Figure 58 Comparison o f 85°C measured and modeled FET A l S-parameters. V *
is 3V and V & is swept at -0.2 V (squares), -0.4 V (stars) and -0.8 V
(circles)...................................................................................................... 186
Figure 59 Comparison o f 25 °C measured and modeled FET C l S-parameters. V *
is 1 V and
is swept at -0.2 V (triangles), -0.4 V (squares), -0.8 V
(stars ) and -1.0V (circles)..........................................................................187
Figure 60 Comparison o f 85 °C measured and modeled FET C l S-parameters. V *
is 1 V and V^, is swept at -0.2 V (triangles), -0.4 V (squares), -0.8 V
(stars) and -1.0V (circles)..........................................................................187
Figure 61 Comparison o f 25°C measured and modeled FET A2 S-parameters. V *
is 3V and Vv is swept at -0.2 V (stars), -0.4 V (squares), -0.6V
(triangles ) and -0.8 V (circles)...................................................................188
Figure 62 Comparison o f 85°C measured and modeled FET A2 S-parameters. V *
is 3 V and
is swept at -0.2 V (stars), -0.4 V (squares), -0.6 V
(triangles) and-0.8 V (circles)....................................................................188
Figure 63 Comparison o f 45 °C measured and modeled FET A2 S-parameters. V *
is 3 V and
is -0.7 V. Simulated values are indicated by lines and
symbols represent measured S-parameters..................................................189
Figure 64 Correlation o f measured S-parameter correlations, r ^ and modeled Sparameter correlations, r ^ for FET A2 at a low-noise bias point with
T=300 K. ................................................................................................191
Figure 65 Measured (symbols) and modeled (lines) noise parameters F ^ . rw
and Xop,versus frequency for the HEMT C l at four Vv biases with V *
=1V and T=25°C. Modeled results represent performance o f a table
based model simulation............................................................................ 193
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Figure 66 Measured (symbols) and modeled (lines) noise parameters
rv R ^
and Xop,versus frequency for the HEM T C l at four V n biases with V *
=1V and T=85°C. Modeled results represent performance o f a table
based model sim ulation............................................................................... 194
Figure 67 Comparison o f simulated FET A2 (a) F ^ (dB) and (b)
(dB) versus
Vp (V ) and V4 (V ) at T=85 °C. F ^ differences are within ±0.1dB over
the bias plane................................................................................................195
Figure 68 Comparison o f measured and modeled F ,* (dB) versus Frequency
(GHz) up to 26.0 GHz. Modeled data represents the PHEMT A2
model developed from 18.0 GHz noise parameters o f one typical FET.
Measured F ^ represents the mean, minimum and maximum values for
a sampling o f five FETs from the same w afer.............................................. 196
Figure 69 Comparison o f measured and modeled F ^ (dB) versus Frequency
(GHz) up to 26.0 GHz. Modeled data represents the MESFET A l
model developed from 18.0 GHz noise parameters o f one typical FET.
Measured F ^ represents the mean, minimum and maximum values for
a sampling o f five FETs from the same w afer.............................................. 197
Figure 70 Comparison of F ^ (dB) versus frequency (GHz) for the simplified
linear model (lines) with the models developed in this work (symbols)
for FETs A l, A2 and C l. The frequency response is shown up to F,n„
for a given FET............................................................................................. 199
Figure 71 Comparison ofNGR (A//Hz/m m /Hz) versus %L,_ (mA) for FETs A l,
A2 and C l at T=298 K. .................................
201
Figure 72 Comparison ofNGR (A//H z/m m /H z), with values o f the Fukui factor,
Kp marked at each data point, versus
(V ) for FETs A l, A2 and C l
at T=298K. NGR values reflect performance potential that Kp does not
relate by itself. ............................................................................................ 201
Figure 73 Comparison ofNGR (A //H z/m m /H z) for FETs A l, A2 and C2 versus
(a) Vgs (V ) and (b) % Idasat T=25°C (closed markers) and T=85°C
(open markers)..............................................................................................202
Figure 74 Schematic illustration o f a FET-based Cold/Hot noise temperature
source for radiometric calibration o f antenna brightness temperature.
Sensed brightness temperature at the antenna is output as a voltage, V 0,
by the radiometer and converted into temperature, T,^, which is
calibrated against the reference temperature,
, set by the novel
integrated noise source................................................................................. 206
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Figure 75 Simplified noise model o f the FET used by Frater and Williams................... 208
Figure 76 Basic topology for a FET-based noise source. The additional
inductance added to the source o f the FET is denoted L *,**. .....................209
Figure 77 Two-port circuit for discussing noise temperature Toa,i- A similar
arrangement for T ,^ occurs with the load placed at Port 1.......................... 212
Figure 78 Simulated T ^ T«p T ^ and T ^ (K ) for HEMT C l versus variable
source inductance, L„ (pH) for a modeled FET. The comparison
illustrates the importance o f designing with respect to T b«,1as opposed
to other noise temperature terms at higher frequencies..................................217
Figure 79 Simulated comparison o f cold and hot noise source performance o f
HEMT C l with set at an optimal value
T ^ and T ^ (K ) are the
value o f T( at the input and output ports respectively...................................218
Figure 80 Comparison o f data ( f = 18GHz and T ^ = 296 K) measured at USF on
the hybrid Cold/Hot noise source and data measured at N IS T versus V *
(V ) for several V9 (V ) biases. USF measurements are plotted with solid
lines and symbols.......................................................................................... 221
Figure 81 Measured variation o f fabricated hybrid Cold Noise source (Port 1)
reflection magnitude for several bias voltage conditions at f = 18GHz
and T^a, = 296 K .......................................................................................... 222
Figure 82 Measured (USF) variation o f hot noise source (port 2) reflection
coefficient magnitude, r a at f = 18GHz and T ^ = 296 K . ......................... 222
Figure 83 Comparison of measured and modeled hybrid circuit cold and hot T,
performance at f - 18GHz and T ^ = 296 K. Simulated performance
is denoted by solid lines and open markers. Tontl and Tgoa are the value
of T, at the input and output ports respectively. ..........................................223
Figure 84 Comparison of measured (USF) and modeled hybrid circuit level
reflection coefficient magnitudes r u and r fi versus V p (V ) at V ^ IV .
Simulated performance is denoted by solid lines and open markers.
Lower values of modeled T u and r a are consistent with the simulation
not having a model for the coaxial-to-microstrip transitions..........................224
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LIST OF SYMBOLS
*
t
a
P
Pk
r
AEr.L
AEC
Af
Ax
e
€r
€s
^dB
1*0
p(y)
Ipj
T
a 12
a
Aj, Bj, Cj, D{
ABCD
\
B
b4
C
cA
^ds
CSd
C8d
Cgj
^gs
CP8
Cpd
complex conjugate
transpose conjugate
thermal coefficient
Hooge parameter
linear thermal coefficient (10* 3/°C )
empirical fitting parameter (-0 .3 )
Brillouin zone center
inter-valley scattering energy
conduction band discontinuity
equivalent noise bandwidth
sub-section length
error function
relative permittivity
semiconductor dielectric constant
thermal de Broglie wavelength
intrinsic low field mobility
MESFET channel charge density
magnitude of complex noise correlation
coefficient
time delay
reverse available gain
channel layer thickness
are functions of the noise parameters
chain parameter format
gate parasitic network chain-matrix
noise correlation matrix transform matrix
intercepts of table model parameters
complex correlation coefficient
noise correlation matrix, chain parameter
drain-to-source capacitance
gate-to-drain capacitance
gate-to-drain parasitic capacitance
gate-to-source capacitance
gate-to-source capacitance
gate pad capacitance
drain pad capacitance
xv
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Cy
C'
D
D||
E
E||
Ec
Em
e^
f
F
Fmin
$
Ga
Ggs
gm
Gnat
ggtii
h
h
Ids
Idss
Igs
Im
Inax
ind
k
k
kB
Kf
L
Ld
Leff
Lg
Ls
mj
M
nij
Mg
Mrev
n
noise correlation matrix, admittance format
a transformed noise correlation matrix
diffusion coefficient
longitudinal diffusion coefficient
applied electric field
electric field parallel to the gate
critical static electric field
static electric field forvm
intrinsic gate noise voltage generator
frequency
noise figure (dB)
maximum frequency o f oscillation
minimum noise figure in dB
unity current gain frequency
available gain
gate-to-source leakage conductance
transconductance
maximum available gain
unit width transconductance
depletion depth
reduced Planck’s constant
extrinsic drain-to-source current
saturated drain-to-source current
forward biased gate diode current
imaginary component
maximum drain-to-source current
intrinsic drain noise current generator
momentum
the reciprocal lattice vector
the Boltzmann constant
non-dimensional Fukui noise coefficient
Brillouin zone boundary at (V2 V2 V2)
drain inductance
effective gate length
gate inductance
FET gate length
source inductance
effective electron mass
noise measure
slopes o f table model parameters
noise figure coefficients
reverse noise measure
number o f unit fingers
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N
Na
Nd
NF
NFmm
NGR
Ni
P
Q2 D
R
r
R «h
Rd
R dd
R <b
R dy
Req
R*
Rgg
Rgs
Ri
K
*n
R opt
Rs
r«
T
T am b.2
Td
Tcq
Tg
T min
T0
T0
T o u t, I
T oua
Tr f
T rev
V *
V„i
(ve)
(v2,,)
V ds
Vgs
Lange’s invariant noise parameter
noise power
donor doping density
noise figure in linear magnitude
minimum noise figure in linear magnitude
noise gain ratio
intrinsic carrier density
drain noise coefficient
2DEG charge density
gate noise coefficient
linear correlation coefficient
FET channel resistance
drain resistance
parasitic drain pad shunt resistance
drain-to-source resistance
forward biased Shottky diode resistance
equivalent channel resistance
gate resistance
parasitic gate pad shunt resistance
gate-to-source leakage resistance
gate-source resistance
equivalent noise resistance
normalized equivalent noise resistance
optimum noise resistance
source resistance
linear self-correlation
transformation matrix
ambient two-port load temperature
equivalent drain noise temperature
equivalent noise temperature
equivalent gate noise temperature
Tmin expressed as noise temperature
standard temperature, 290K
reference temperature, 290 K
temperature for noise power exiting port 1
temperature for noise power exiting port 2
reference temperature
temperature o f noise power
gate barrier height
Shottky barrier built in potential
average electron velocity
average quadratic drift velocity
extrinsic drain-to-source bias potential
extrinsic gate-to-source bias potential
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vm
vm
Wp,
Wj
X
X^
Yc
Ygea
yt
Yopt
Z;
maximum electron velocity
electron saturation velocity
unit gate width
weighting function
Brillouin zone boundary at (100)
optimum noise reactance
noise correlation admittance
generator admittance
incremental channel thickness
optimum noise source admittance
intrinsic FET impedance matrix
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BIAS AND TEMPERATURE DEPENDENT NOISE MODELING OF MICROW AVE
AND M ILLIM ETER-W AVE FIELD EFFECT TRANSISTORS
by
STEVEN MARC LARDIZABAL
An Abstract
O f a dissertation submitted in partial fulfillment of
the requirements for the degree o f
Doctor of Philosophy in Electrical Engineering
Department o f Electrical Engineering
University o f South Florida
December 1997
Major Professor: Lawrence P. Dunleavy
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This work advances FET noise modeling capabilities at microwave and millimeterwave frequencies in the areas o f equivalent circuit modeling, noise parameter
measurement and low-noise circuit theory. Foremost, a powerful set o f experimentally
developed bias and temperature dependent microwave FET noise modeling procedures
are applied to metal-semiconductor field effect transistors (MESFETs) and high electron
mobility transistors (HEMTs). These procedures form the basis o f a comprehensive
software tool set for FET noise parameter modeling. Design analysis enabled by the
resulting computationally efficient model satisfies a fundamental need to simulate
microwave integrated circuit (M IC ) and monolithic microwave integrated circuit (M M IC )
transistor performance over the range -55°C < T < 85°C.
At a physical level, an ambient temperature change causes microwave frequency
FET amplifier gain and noise figure to change with respect to the semiconductor energy
bandgap and electron mobility. However, by applying proper modeling techniques, a
resulting table o f equivalent circuit element thermal coefficients provides a powerful
database for FET simulation. The model resulting from this work also allows the study
of FET physics over a wide range o f conditions, which is noticeably lacking in the
available literature.
This work compares differing III-V FET technologies in terms of thermally
induced variations in their equivalent circuit elements, noise model coefficients, and
figures of merit. Based on interpretation o f experimentally extracted models, this work
finds the large electron inter-valley scattering energy, AEr_L, of too 53Gao 47As to be well
suited to low-noise performance with a low relative dependence upon ambient
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temperature variation compared to GaAs MESFETs and PHEMTs.
A related effort developed a novel method o f determining linear two-port noise
parameters for an FET that does not require a variable input admittance tuner. Instead,
this method makes use o f noise figure data measured at one known source admittance
and knowledge o f the small signal equivalent circuit model to develop a noise model o f
the FET.
For the first time, a high electron mobility transistor (H E M T) series feedback
circuit is employed to achieve an electronically cold noise temperature at K-band
frequencies (18-22 GHz). This achievement resulted from advances in the theory, design,
modeling, and measurement o f FET-based noise sources. One new expression resulting
from this analysis is the reverse noise measure, Mrcv, which establishes the performance
potential o f a FET used as a noise source. Using the bias and temperature dependent
FET noise model to analyze a hybrid cold/hot noise source design, an InAlAs/InGaAs/InP
HEMT demonstrates 105 K performance in the 18-22 GHz range; the highest reported
frequency for a FET cold noise source.
Agreement between simulation and
measurements confirm a variable source temperature from 105K to over 1000K.
Abstract Approved:
Major Professor: Lawrence P. Dunleavy, Ph.D.
Assistant Professor, Department o f Electrical Engineering
Date Approved:
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CHAPTER 1. INTRODUCTION
1.0
INTRODUCTION
Microwave frequency semiconductor devices enhance the performance o f a wide
variety o f commercial and military electronic systems. In such systems, devices such as
the Field Effect Transistor (FET) are among the most widely used semiconductor
components. Circuits using FETs enable reliable microwave communications, radar, and
remote sensing functions. FET performance continues to dominate the development o f
both hybrid microwave integrated circuits (M IC s) and their monolithic counterparts,
monolithic microwave integrated circuits (M M IC s). This success is due to the excellent
low noise and power amplification characteristics o f FETs, as well as, the designers
knowledge of FET characteristics. Ultimately, the continual improvement o f microwave
(1-30 GHz) and millimeter-wave (30-300 GHz) system performance depends in part on
the ability to describe and improve FET performance.
Microwave frequency FET noise performance has improved dramatically along
with the evolution o f the materials and processing technology in the last 15 years.
Compound semiconductor FETs with electron-beam (E-beam) written gates which are
0.05 (im to 0.25 /im long have achieved record low-noise performance. In addition, a
variety o f new markets for wireless and microwave systems have put new demands on
performance. This has led to the development o f millimeter-wave low-noise amplifiers
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(LNAs) for space applications based on InGaAs/InP HEM T technology that provide 26
to 31 dB o f gain from 42 to 50 GHz with greater than 50% chip yield and less than 3 dB
noise figure [ I] ,[2 ]. Although other transistor technologies (such as bipolar junction
transistors, BJT’s, and metal oxide semiconductor FETs, MOSFET’s) are useful in some
respect to the applications previously mentioned, this work focuses on the dominant FET
technologies typically implemented in group III-V semiconductors.
The continued
success and improvement o f low noise FETs requires developments in the areas o f CAD
through the updating and enhancement o f FET models.
The impact o f both MICs and M M ICs on communication system sensitivity and
dynamic range are w ell known. For example, a common application o f FETs is in low noise amplification at a receiver’s front-end before down-converting a signal to a
baseband signal processing frequency. This arrangement lessens RF sub-system demands
for high transmitter power levels, because the minimum detectable signal level is
decreased. In turn, this leads to transmitters and antennas with smaller size and reduced
weight. Due to these effects, and even in light o f the realization o f highly integrated
digital communication receivers, low-noise amplifiers remain an important block in
microwave system design [3],
In electronic communications, noise is any unwanted signal which appears in the pass
band of the desired filtered signal. Usually, noise is inherent to a receiver/transmitter pair as
well as a transmission channel In the electronic components, noise generated by the receiver
before the signal processing unit limits the dynamic range o f the system. Therefore, it is
important that noise contributed by the front-end receiver electronics is minimized. T his
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requires the design ofboth low-noise devices and associated circuit topologies that minimize
the contribution ofdevice noise. To assessthe noise contributed by a FET, computer models
offer a variety o f capabilities. Such models can be coupled with CAD techniques to allow
accurate circuit level design o f system level components using FETs.
A ample means o fmodeling a FET is as a “black-boxf’ containing data measured over
a specified frequency band. Yet, despite recent progress in measuring high frequency onwafer data, such as scattering parameters and noise parameters, the black-box approach has
limitations including:
(1)
The cumbersome nature of measured data and its required storage space.
(2)
The discrete format o f data which limits extrapolation o f performance.
(3)
The increasing difficultly/cost encountered to measure data as frequency
increases or as more information about bias and temperature are desired.
Therefore, for a given data set, any changes in the frequency range, temperature conditions
or bias state cannot be easily predicted. Thus there has always been a need for FET models.
However, the process o f developing a model is not based on an exact method and
requires the insight and ingenuity o f the model designer. Such distinction occurs because
an equivalent circuit model is a mathematical approximation o f a physical device. To
make the problem tractable this approach usually inherits interpretations and/or
assumptions concerning the physical FET. Subsequently, various FET models appear due
to specific applications, such as noise modeling, and the unfortunate fact that the models
are somewhat device dependent. For example, for several decades the gallium-arsenide
metal-electrode- semiconductor field effect transistor (GaAs M ESFET) has been a
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paradigm for the development o f both M IC and M M IC technology. Recently, this trend
has been changed by FETs with better performance engineered in a variety o f alternative
materials. Variations on the MESFET using epitaxial heterostructure semiconductor
layers are establishing dominant roles for both low-noise and power amplification. The
most prolific o f these variations is the high electron mobility transistor (HEM T).
However, heterostructures display some distinct differences from MESFETs and this is
reflected in the modeling process.
In this chapter, the scope of this work is defined with detailed motivations of the
research. A short review outlines the various equivalent circuit models that previous works
have developed to characterize FET noise.
However, this review shows that little
experimental data on the temperature dependence o f these noise models exists. To this end,
this work develops a dynamic microwave FET noise model for performance prediction at
varied frequency, bias and temperature ranges. The remainder o f this chapter summarizes the
objectives and accomplishments and provides an overview o f the other chapters.
1.1
PROBLEM SET-UP/DEFINITION
For a circuit designer, the simulation o f transistor performance as a function o f
temperature is a fundamental problem. Since many applications that use MICs and
M M ICs do not have the luxury of a stabilized thermal environment, a temperature
dependent simulation o f FET performance is valuable. This is especially true for MMICs,
where each fabricated design iteration is much more costly than for hybrid or discrete
component types o f MICs. Traditionally, M IC and M M IC simulations consider only
room temperature operation, due to the general unavailability o f temperature dependent
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FET models in computer aided design (C A D ) programs.
This practice demands
expensive post fabrication temperature characterization o f M ICs and M M ICs and may
require a temperature compensation network at the subsystem level [4], [5]. W hile some
work towards developing temperature dependent FET models has been reported [ 6 ], [7],
[ 8 ] further work is needed to develop a more complete understanding o f FET noise
versus temperature, and to establish practical temperature dependent FET noise modeling
and design approaches.
To design low-noise small signal amplifiers requires knowledge o f the optimum
circuit design conditions for the transistor. On the other hand, since the FET is a
thermally sensitive device the optimum biasing conditions and design parameters will
change with temperature.
Currently, various equivalent circuit models exist to
characterize the small signal and noise properties o f microwave frequency FETs, but few
such models include temperature as a variable in the analysis. Therefore, one major goal
o f this work is to develop thermal models o f the constituent parameters o f a FET model.
This is accomplished by experimentally determining equivalent circuit model parameters,
and
investigating trends in their temperature dependence over a wide range of
frequencies, biases and temperatures. A key concurrent aspect in this work is the
implementation or improvement o f FET modeling techniques used to characterize the
model elements from the various data sets.
The modeling discussed above requires several interacting capabilities including:
measurement techniques, theoretic and empirical models, and numerical techniques for
calculating values o f quantities. For example, one approach to finding the model element
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values makes use o f analytical expressions derived from the model itself to calculate
element values from data. Too often, however, this task is approached by minimizing an
error function based on a wide range o f specifications and solved by tuning individual
element values such that the model fits the data. This procedure can yield some
undesirable results, such as, element values that are not physically meaningful w ith
respect to the actual FET. These solutions may also be sensitive to the initial conditions
of the model. Therefore, it is useful to temper the use o f random optimization efforts
with solutions based upon a sound theoretical foundation in solid state physics.
The resulting use o f these capabilities w ill allow for the study o f trends in model
parameters versus temperature. By addressing the need for improved models, this
systematic study focuses on state-of-the-art techniques for improving FET small signal
and noise modeling. Achievement o f the major goal o f developing dynamic model
elements with respect to temperature w ill allow computation o f the design parameters as
called for by a CAD simulator as a function o f temperature. To introduce the models and
physical processes considered further in this work, a review o f microwave frequency FET
noise modeling is presented in the following section.
1.2
COMPARISON OF NOISE MODELS
This section reviews an equivalent circuit approach to modeling FET noise
sources. An additional subsection reviews the characteristics o f such models as applied
to FET noise under ambient thermal variations. In this work, a frequency range from 2
GHz to 18 GHz is used to develop a baseline FET noise model. However, a FET model
is capable o f extrapolating performance versus frequency, but the accuracy o f this
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approach needs to be verified. To test frequency extrapolation, the small signal model
is compared w ith data up to 67.5 GHz, while the noise model is tested to the lim it o f
available data at 18 GHz and 26 GHz, as well as appropriate figures o f merit.
1
.2.1 FET Noise Fundamentals
The more one knows about a FET’s characteristics, such as performance as a
function o f frequency, bias or temperature, the more likely design goals are reached.
Ideally, the circuit designer should be enabled to perform trade-off analyses and meet
such design goals using a CAD model to predict performance at all expected conditions.
However, this ideal is not always realized due to the lack o f and/or limitations of
available FET models.
Further insight is gained over a black-box description using measured parameters
if a detailed small signal model of the FET
is used. A common model topology is shown
in Fig. 1. In this work, the circuit model representing the active region beneath the FET
gate is referred to as the intrinsic FET model, and the extrinsic circuits model the
parasitic connections at the gate, drain and source terminals. Noise modeling, therefore
describes what additional information is needed, other than the small signal model
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Drain
Gate
Rd
w cpd
jr*
!
INTRINSIC
I
EXTRINSIC
Source
Figure 1
Microwave frequency noise equivalent circuit model o f a FET where
intrinsic denotes the active channel region under the gate and extrinsic
denotes circuit elements that model the connections to the channel.
topology, to simulate the noise parameter data.
A review of existing models, illustrates that FET noise models can be categorized
by the number o f noise source coefficients used to define a model. The models listed in
Table 1 are arranged by their publication reference and in a decreasing order by the
number of coefficients used to define two intrinsic noise sources. The earliest work on
Si JFETs produced the conclusion that the real part o f the correlation coefficient is
negligible in a FET model that assumes two noise current generators [9]. This conclusion
by van der Ziel yields a three coefficient noise model. Models using three and four
coefficients usually associate two real coefficients, P and R, with the drain and gate noise
generators and a complex quantity C with their correlation [ 1 0 ],
Recent work by
Pospieszalski has shown the correlation to have a different interpretation than under the
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P, R and C representation, and a simplified model has emerged that reduces the number
o f noise model coefficients to two noise temperatures [11]. These are named Tg and Td,
and they represent the equivalent noise temperature o f the gate resistor
and the drain
resistor R,^. A single coefficient model by Gupta et. al. [12] results from assuming the
gate noise is o f an entirely thermal origin. Since all o f these models are equivalent, with
some assumptions, further considerations in choosing one include the fact that the low
order models require less computer memory storage and model processing effort.
Table 1
Previous FET Noise Models and Their Noise Model Coefficients
Number o f Coefficients
Name of Coefficients
R Pucel et. al. [10]
4
P, R, Re[C], Im [C]
A. vanderZiel [53]
3
P, R, Im[C]
M . Pospieszalski [11]
2
Tg,Td (K )
M . Gupta [12]
1
Sjo (A 2/H z)
Model Reference
Finally, a popular set o f modeling equations developed by Fukui do not constitute a
model in the sense o f Fig. 1. Rather, Fukui’s empirical relations allow the fitting o f
measured noise parameters by adjusting a set of four non-dimensional coefficients K f, K g,
Kb, Kr [13], Although Fukui’s equations are relatively simple to apply compared to the
models o f Table 1, the technique o f curve fitting to solve for the noise parameters can
lead to non-physical noise parameters [14].
Before addressing the concept o f a bias and temperature dependent noise model,
it is useful to review some o f the salient features o f the FET model used here. In the
equivalent circuit model o f Fig. I, the intrinsic noise generators describe the power
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spectral density o f the noise generated within the FET, but they do not affect the small
signal characteristics o f the model. While the intrinsic model simulates the voltage gain
and impedance characteristics of the FET under small signal excitations, the noise
generators act with the small signal elements to predict the noise properties. Therefore,
any reference in this work to the noise model inclusively refers to the intrinsic small
signal model also. The definition o f noise generators usually includes a set o f noise
coefficients whose values are determined empirically. W ith regard to the quiescent
operating point of the FET, the user should note that any o f the elements in an equivalent
circuit model are static functions of the DC operating point and temperature. Therefore,
such models only characterize performance at discrete bias and temperature conditions.
While various models for the noise power spectra in FETs exist in the literature, most
equivalent circuit models do not have a predictive capability for simulating noise figure
at different temperatures.
The static nature o f existing equivalent circuit models prompts this investigation
to ask several questions regarding FET noise. First, what functional dependence on the
ambient temperature or channel temperature do intrinsic FET noise generators exhibit?
Is one material or structure best suited for low-noise and is there one that is least
sensitive temperature? A literature search to consider these questions is presented below.
1.2.2 Previous Temperature Dependent FET Noise Models
The simplest noise source to characterize versus temperature is thermal noise, that is
found in the three electrodes on the FET. Thermal (or Nyquist) noise in these electrodes is
modeled by parasitic resistors that are expected to generate a frequency independent noise
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spectrum. The parasitic resistors are given a temperature dependence proportional to the
ambient temperature as given by Nyquist’s relation for the equivalent mean squared noise
voltage as,
e* =
h / . —
2
4K A /
V—
« pJ£(I)
« 4 *s r „ « A /
f b r k jT ^ f
( V 2 /H z)
where kB is the Boltzmann constant, T 0 is the reference temperature o f 290 K, R is the
resistance A f is the noise bandwidth, his the reduced Planck’s constant and/is the frequency.
In the frequency range o f this work the approximation in Eq. ( 1 ) applies. Also note that, an
increase in the ambient temperature will increase the noise o f a resistor by a factor t =
I T 0 [15], where T 0 is the standard reference temperature of290K.
In comparison to thermal noise, the temperature dependence o f the intrinsic FET
noise is not as clearly definable, because several noise processes contribute to its total
noise power spectral density. For microwave frequency FET noise only the average
effect o f a combination o f intrinsic noise processes are observed. These noise sources
are also partially correlated as opposed to un-correlated thermal noise in the FETs
parasitic resistors R^, Rg and R j. However, the manner in which noise produced in the
gate and drain circuit is correlated is somewhat controversial and different interpretations
o f the temperature dependence of these generators are reviewed next.
Current research into temperature dependent FET noise models centers around
11
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the models using the non-dimensional coefficients P, R and C or the noise temperatures
Tg and Td. Focusing on the noise contributed by the intrinsic FET, the minimum noise
figure is described in terms o f these model coefficients as [16], [ 1 1 ],
(2)
or
■I +f
i
A*
rd R, ts
l O Jt
(3)
Consider the temperature dependence o f P, R and C in Eq. (2) first. In an early attempt
to predict the cryogenic performance o f ion-implanted MESFETs Robertson and Ha
proposed a temperature dependent function for the gate and drain noise coefficients P
and R [17].
The correlation, C, was assumed to have a negligible temperature
dependence, since it is related to the capacitive coupling between the gate and drain
whose temperature dependence is small. That model consisted o f a simple approximation
for the relative temperature dependence o f three FET noise generating mechanisms, but
it proved to be too crude for accurate predictions on present day FETs [18]. For the two
parameter model o f Eq. (3) the variation o f the noise coefficients have been examined
versus temperature for both GaAs MESFETs and HEMTs. However, the results are
again limited to room temperature and one cryogenic level. Pospieszalski observed that
at a temperature o f 297 K the value o f Tg was 304 K while T d was 5514 K for a low12
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noise biased HEM T [11]. Upon cooling the FET to a new temperature o f 12.5 K the
value o f Tg was 14.5 K and Td was 1406 K. The observed changes in the noise
coefficient Tg, assigned to the resistor Rp was concluded to be due to the ambient
temperature change. In contrast, the effective noise temperature Td o f the output
resistance,
was observed to be on the order o f the effective temperature o f electrons
in a FET channel. This latter conclusion was reached by extrapolating, to the high
electric fields established in the FET channel, electron carrier temperatures obtained from
Monte Carlo simulations performed for lower electric fields [19]. Since no theoretical
development of the Tg and Td coefficients was made, this is a surprising result, because
it gives the appearance o f a physical meaning to these noise coefficients. The conclusion
about the temperature dependence o f Td has also been controversial due to the
observation of electron temperatures in excess o f the bandgap at higher applied electric
fields[142]. However, one subsequent study by Anholt[8 ] clarifies the matter o f the
extrapolation of temperatures in the hot-carrier regime. Since the velocity-field curve
peaks at low fields (~4kV/cm ) and subsequently falls off at the expected field magnitudes
in a modem sub-micron H I-V F E T (-10kV/cm ), the Td values do not represent the noise
temperature of electrons in the hot-carrier regime, therefore invalidating the previous
conclusion. With regard to the gate temperature it is found that the correlation o f drain
noise to the gate is self consistent in some results [2 0 ], but observations to the contrary
are also observed depending on the bias conditions, modeling and to an unknown extent
upon the FET composition and foundry processing^ 1 ],[2 2 ], How well the gate noise
can be described by purely thermal noise processes can be studied using equivalent circuit
13
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models. This depends upon how well the temperature dependent components o f the
intrinsic noise power spectra balance out against changes in Tg. To discuss this point and
address the variation o f Tdversus temperature requires a systematic comparison o f both
the small signal model parameters and noise coefficients, but related data in the literature
is lacking.
A number o f FET designs are modeled as part o f this work. Table 2 lists these
FETs and their outward characteristics. References to individual FETs are ordered
alphabetically with respect to foundry and numerically for each FET type from a foundry.
Table 2
FET Technologies Studied in This Work___________________________
FET Label
Type
Channel Material
System
Gate Length
(/im)
Gate
Width
________________________________________
Cum
Al
MESFET
GaAs
0.25
300-600
A2
PHEMT[23]
AlGaAs/InGaAs
0.25
300-800
Cl
HEMT[24]
InGaAs/InP
0.15
100-300
Dl
MESFET
GaAs
0.5
300
D2
MESFET
GaAs
0.25
200-600
El
PHEMT
AlGaAs/GaAs
0.25
150
The goal in modeling this variety o f FETs is to allow comparisons o f noise performance
degradation due to temperature changes. This also means that the methods used to
extract the model element values from measured data need to be adapted to the varying
device characteristics and layout geometries.
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1.3
SUMMARY OF OBJECTIVES
The most basic motivation o f this work was the need to establish a microwave
frequency (small signal and noise) measurement and modeling capability at the University
o f South Florida. Since the industry is also interested in obtaining data and models o f
FET performance at elevated temperatures, the additional thermal capability was a
natural step. The major objective o f this work was to investigate and develop CAD
models for bias and temperature dependent simulation o f microwave frequency FET
noise. Toward this goal several milestones included: (1 ) evaluating the bias, temperature
and frequency dependencies of experimentally extracted model parameters, ( 2 ) comparing
results from other works and between different FET designs, (3 ) evaluating and
implementing necessary equivalent circuit models. As mentioned in Section 1.2, several
supporting tasks necessary to the model development include: measurement techniques,
theoretic and empirical models and numerical techniques for evaluating quantities.
Specific tasks included: (1) developing improved small signal and noise model extraction
criteria and procedures for model elements, ( 2 ) investigating model element bias,
temperature and frequency dependencies, (3) analyzing additional sources o f microwave
noise due to gate leakage currents, (4) establishing on-wafer calibration and measurement
techniques for microwave and millimeter>wave measurements, and (5) using noise
correlation matrix techniques for analysis o f generalized noise models and measurement
apparatus.
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1.4
CHAPTER SUMMARY: ORGANIZATION OF THIS WORK
A summary o f chapter by chapter developments is given here as well as an
overview o f how the research was conducted. This serves two purposes, one o f which
was to organize the broad array o f concurrent capabilities required for this study. The
other more obvious purpose is to aid the reader in maintaining a focused point-of-view
on the overall goal o f obtaining a bias and temperature dependent FET noise model. An
outline o f the development o f the experimentally based noise model follows:
1.
Choose a baseline noise model and modeling technique such as one from Table
1 in Section 1.2.1.
2.
Measure and model a wide range o f FETs over a wide range o f bias and
temperature conditions.
3.
Analyze trends in bias and temperature dependent data and model as either
equations or tables with respect to these two variables. The tables model can be
made as flexible to conditions as the equations by an interpolation scheme.
4.
Compare results of steps 2 and 3 w ith expectations o f models assumed in step 1.
If necessary refine models of step 1 and reevaluate data.
5.
Incorporate changes to model elements from step 2 and 3 that result in a new
model with bias and temperature as dynamic variables o f the model.
In Section 1.2 a review o f available noise modeling studies was given. From this
review, this work is believed to be the first systematic study o f both the bias and
temperature variations of FET noise models. Chapter 1 defines the problem, presents a
review of related results and states the objectives o f this work.
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Chapter 2 covers a broad range o f topics related to semiconductor device theory
and noise in FETs. The discussion in Chapter 2 begins by introducing types o f FETs used
at microwave and millimeter-wave frequencies. Two types o f models are typically used
to simulate the noise in a FET. One type, referred to as physics based, uses an analytical
or numerical representation o f electron transport in a semiconductor to simulate the
terminal performance o f the FET.
Another type o f model for simulating FET
performance is based upon an equivalent electrical circuit representation. For this work,
the advantages o f the equivalent circuit model are discussed in Chapter 3. Subsequently,
theory and techniques for the analysis o f equivalent circuit models o f two-port noise are
reviewed and developed. One new development here involves the interrelation o f the
two-port noise parameters. This analysis provides bounding relations for modeling tw oport noise parameter data with an equivalent circuit representation. Chapter 4 introduces
a technique for modeling the bias and temperature dependence o f microwave FET small
signal and noise performance. Due to the moderate temperature dependencies o f the
small signal elements a simple linearly dependent model is discussed. While similar
knowledge about temperature variations o f the equivalent FET noise generators is
lacking, a linear model is also assumed for the baseline noise generator model.
Chapter S details the techniques used to calculate the values o f the equivalent
circuit model elements. This work advances a technique (denoted Cold-HEM T) for
extracting parasitic resistance in HEMTs and PHEMTs that is valid in the presence o f
gate leakage current. Furthermore, it establishes a connection between those desiring a
model extraction technique and the theory for forward biased gate currents in a
17
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heterostructure FET. As a result, previous assumptions based on modeling the metalsemiconductor barrier (Shottky barrier) are shown to neglect the effect o f quasi-Fermi
level bending at the heterostructure barrier.
Anomalous, 1 /f 2 dispersion o f FET
microwave noise behavior is analyzed and modeled in this work.
The frequency
dependent noise is shown to be contributed by leakage currents from gate-to-source, and
is explained through an analysis o f the noise correlation matrix for the associated
parasitic resistance. An example o f leakage effects in PHEMTs produces l/o >2 frequency
dependence in the noise generators. It was found that the parallel combination o f
parasitic resistance and capacitance explains why many studies find an increase in the low
microwave frequency noise spectral density. The completeness o f the analysis allows the
identification o f possible modeling errors at a variety o f stages in the overall model
development. This capability enhances modeling accuracy even in the presence o f large
data errors, because the software allows for identification o f a variety o f errors
encountered.
In Chapter 6 , the experimental setups for the microwave and millimeter-wave
measurements are described. These include the baseline S-parameter and noise parameter
measurements performed versus the FET bias condition and temperature setting. Also
included is a description o f a novel method o f determining the two-port noise parameters
of the FET that does not require a variable admittance tuner. The method makes use of
noise figure data measured at one known source admittance and knowledge o f the small
signal equivalent circuit model to develop a noise model o f the FET. The resulting noise
model allows the calculation o f the noise parameters at frequencies beyond the range of
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the noise figure data.
By developing a model for temperatures greater than room temperature, this work
resulted in the publishing o f data on model element thermal coefficients not previously
published. These results are detailed in Chapter 7. The trends in the thermally induced
model element variations are highly correlated with a linearly temperature dependent
model. Thermal coefficients are therefore easily compared between different laboratories
and/or FET technologies. One exception from a linear model occurs in the case o f
trapping energy levels, however, measurement o f FET threshold voltage for Id, provides
a means o f identifying trapping effects. A shift in the threshold voltage is shown to
correlate well with shifts in the model element values, thereby establishing a means o f
conditionally changing the model to deal with trapping events.
The results o f Chapter 7 enable the comparison o f a figure o f merit for
temperature dependent intrinsic FET noise in differing FET technologies.
This
comparison is unbiased by gate geometry scaling factors. The resulting comparison o f
material dependent factors finds the large electron inter-valley scattering energy, AEr.L,
of Ino 5 3 Gag 4 7 A s t 0 be weU suited to low-noise performance with the least dependence
upon ambient temperature variations. Furthermore, the improvement o f this performance
between GaAs and In0 1 5 Ga0 85As is shown to be dependent upon the 2DEG modulation
efficiency of the heterostructure FET employing Ihq.1 5 Gao.g5As as the channel.
In Chapter 8 , the usefulness o f the extracted FET model is demonstrated on the
improved design and evaluation of FET-based noise sources at microwave and
millimeter-wave frequencies.
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This work correctly defines the black-body noise source temperature, Ts, from an
analysis o f an alternate set o f noise parameters, used in the metrology o f noise calibration
standards. As a result, the quantity Toutj is defined as the desired temperature for FET
evaluation and design.
is equal to the measured quantity T s. Comparison o f Tout I
with previous work shows that the measured Ts is made up o f two components: (1 ) T rev
which denotes the temperature contributed by the two-port itself and (2 ) the product
A 12Tamb^ which denotes the available temperature contributed by the termination at port
2. Based on this improved definition, a further investigation considers the theoretical
limit for achievable noise source temperature. As a result, a new quantity known as the
reverse noise measure,
is defined.
indicates the minimum achievable two-port
noise temperature, T ^ for an infinite cascade o f identical, optimally matched, two-port
noise sources.
Compared to previous efforts, the approach taken in Chapter
8
overcomes
frequency limitations through the development and use o f advanced microwave FET
noise models. The resulting evaluation with state-of-the-art low-noise FET technology
predicts the lowest FET noise source temperature achieved to date in the 18 GHz to 22
GHz frequency range. The temperature model also presents the capability to account for
ambient temperature variations at the CAD level, thus satisfying a primary goal o f this
work.
The last chapter summarizes the original contributions achieved through this work
and lists recommendations for further study.
20
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CHAPTER 2. SEMICONDUCTOR DEVICE THEORY
2.0
INTRODUCTIO N
The field effect transistor as first described by Shockley [25] has, since then, been
advanced for use at microwave frequencies through the use o f a metal-semiconductor
contact in the gate as opposed to the original pn-junction [26], [27]. FET performance
at microwave frequencies has seen further improvement resulting from the use o f
heterostructure semiconductors and alloys o f GaAs, InP and GaN. A recent survey o f
FET technologies reveals about 10 varieties of FETs and 20 sub-variations that have been
created [28], but only a few are commonly used at microwave and millimeter-wave
frequencies. To understand the unique qualities o f FETs that operate at microwave and
millimeter-wave frequencies it is important to relate FET performance to the physical and
electronic properties o f group m -V materials, such as GaAs.
Furthermore, an
understanding o f these properties allows the interpretation o f important microwave and
millimeter-wave FET noise mechanisms.
There are a variety o f ways to describe or review FET operation and performance.
Usually, an introductory discussion reviews a FET’s key operational characteristics, such
as D C -IV curves, saturation, pinch-off and gain. A t another level o f understanding, FET
operation may be described relative to the role o f fundamental material characteristics
and semiconductor physics.
By understanding how the materials affect a FETs
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performance, comparisons between FETs o f differing semiconductor compositions are
possible. This knowledge is important since FETs can now be built in a variety o f
material compositions yielding a variety o f technology choices. In this chapter, important
physical aspects related to FET performance are reviewed w ith the goal o f providing a
physical basis on which FET noise performance and circuit model coefficients may be
compared.
2.1
FIELD EFFECT TRANSISTOR. PHYSICAL PRINCIPLES
In discussing the parts o f a MESFET (or HEMT) and its operation, it is useful to view
a cross-sectional schematic o f a MESFET as shown in Fig. 2. This illustrates the spatial
relation o fthe semiconductor channel and the gate, drain and source metal electrodes across
which static electric fields are applied to bias the electrical conduction properties of the
channel. The FET channel is the primary material through which carrier transport (as
electrons or holes) occurs. The drain and source terminals form ohmic metal contacts to the
Shottky Contact
Vds
Ohmic Contacts
nr-
n~
]
* /
Depiction
Region
Figure 2
I*
S.I. GaAs
1
L
nr
AIGaAs
/ GaAs
20E6 ^
S.l. GaAs
r
I
---------- 1
I
1
Comparison o f layer structures o f MESFET (left) and HEMT (right) crosssectional views. Key MESFET dimensions shown are the channel height
“a” and the depletion depth “h” beneath the shaded depletion region. The
gate length Lg and unit gate width “Z” are common to both FETs depicted.
22
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semiconductor channel. These are typically AuGe eutectic alloyed contacts with some
differences in the treatments used between MESFET[29] and heterostructure FETs[30]. In
contrast to the source and dram, the gate contact is a Shottky barrier contact located between
the source and drain. The DC current and voltage characteristics (D C -IV ) o f a FET with
common source potentials as illustrated in Fig. 2 are found by stepping the bias over a range
o fvalues to produce a family o f I* currents. An expression for I* versus V * and V „is [3 1 ],
where P is a function o fV * related to the channel material and V * is the threshold voltage,
which differs from the pinch-offvoltage, Vp by the Shottky barrier built in potential, V K. An
example o f measured DC -IV curves for a depletion mode PHEMT is shown in Fig.3. The
120
100
Vds(V)
Figure 3
Room temperature D C -IV curves for a depletion mode h^Gat ^As/GaAs
PHEMT.
23
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quadratic dependence on the gate voltage o f Eq. (4) may become more linear in the case o f
a PHEMT.
The potential, applied at the gate Shottky barrier, control (or modulate) current
flowing from drain to source, this is the “field effect”. For an n-channel depletion mode GaAs
MESFET, a forward bias potential applied from drain-to-source,
causes a current, 1^
to flow in the channel. The height ofthe channel “a”under the gate is controlled by a reverse
biased potential applied from gate-to-source, V^. The depletion depth “h” under the gate is
below the shaded region in Fig. 2. For a depletion mode FET when there is a sufficiently
large gate reverse bias value such that the channel is fully depleted of charge carriers (h=0 ),
the device is said to be “pinched-off.” With no bias applied to the gate, the saturated open
channel drain-to-source current occurs, 1^. A slight positive Vg, bias overcomes the built-in
potential o f the Shottky barrier such that h=a and this produces the maximum current, I ^ .
The current I* in the MESFET is made up o f electrons which are free to travel in a three
dimensional (3-D ) manner, but as shown next for the HEMT, two dimensional (2-D)
transport o f electrons is also possible.
In a heterostructure FET, such as the HEMT shown in Fig. 2, the properties o f the
AlGaAs/GaAs interface factor into how the current under the gate is modulated and how the
carriers travel. As first demonstrated by Dingle and Stormer, a structure composed of
epitaxial layers of large bandgap and small bandgap semiconductors forms an artificial
layering o f semiconductor and charge layers known as a superlattice. The superlattice is
based upon a layering of the small and large bandgap materials which creates a discontinuity
in their energy bands at the interface. In the conduction band, the energy discontinuity forms
24
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Metal
Figure 4
n+AIGaAs GaAs
Metal
n+ AIGaAs
GaAs
Energy diagrams for the conductionband in a GaAs/AIGaAs HEMT under (a)
forward bias, (b) reverse bias near pinch-off.
a potential well. I f the large bandgap material is doped and the small bandgap material is
undoped, then the potential well can be used to separate the electron carriers from their parent
donor ions in the large bandgap material [32]. This phenomena occurs in Fig. 4 between the
larger bandgap AIGaAs (doped n+) and the smaller bandgap GaAs (undoped).
Taking a closer look at how the potential well forms also reveals how electrons get
into the potential well. Beginning with the contact between the large bandgap and small
bandgap material in equilibrium, the Fermi level on either side o f the interface must line up,
which requires a bending o f the energy bands. A critical parameter here is the discontinuity
between the conduction bands o f the two materials, AEC, which forms a finite potential well
on the GaAs side o f the interface. Ideally, the larger AECis, the greater the carrier density
will be in the well and the less likely that carriers w ill have enough energy to leave the well
and conduct in the larger bandgap layer. Once the well is formed, electrons in the doped
AIGaAs have a higher affinity for the lower energy subbands in the quantum well on the GaAs
side. As a result, the free electrons in the AIGaAs diffuse into the well on the GaAs side.
25
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The electrons in the potential well behave according to the principles o f quantum
mechanics, and this affects how the carriers in the potential well are transported from drain
to source. Conditions for quantization o f energy levels in the potential well require the well
width to be less than the thermal de Broglie wavelength, Ajg, o f electrons in the AIGaAs. For
n' GaAs this yields a width o f 40()A. The type o f potential well illustrated in Fig. 4 is usually
approximated by a triangular potential. The possible quantum states or electron subband
structure has been calculated analytically based upon
and the energy dependent well
width[33]. The result o f such calculations yields the accumulated electron density in a quasitwo-dimensional plane (or two dimensional electron gas, 2DEG) due to the quantization of
the perpendicular wavevector. This is similar to the inversion layer formed at the interface
between an insulator and a conductor, as in a metal-oxide-semiconductor FET (MOSFET)
[34].
Having introduced the concept of a heterostructure channel, the modulation o f the
current I* in a HEM T/PHEM T is discussed. As with the MESFET, a positive V ds bias
draws a current Ids through the 2DEG. In a depletion mode HEMT, the gate Shottky
contact is used to deplete charge not already diffused into the quantum well. I f the
doped large bandgap layer (known as the supply layer) is not depleted, then this
undepleted charge may conduct in the supply layer. This component o f current is
parasitic to the channel current in a HEMT /PHEMT. By applying further reverse bias
at the gate the 2DEG sheet density is partially depleted and the channel current is
reduced. A t pinch-off, the electrons are completely depleted from underneath the gate
because the reverse bias offsets the conduction band discontinuity such that, the potential
26
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well becomes too shallow to conduct any significant current, as shown in the right-side
o f Fig. 4.
2.1.1 Energy Band Structure
The two FET channel types presented in Fig. 4 have differing conduction
properties yet they may be composed o f similar materials. To understand how FET
performance is related to the channel material the properties o f the materials energy band
structure must be known.
Also, this understanding is important for later
discussion/comparison o f MESFET, HEMT and PHEMT performance.
The relation between energy and momentum in a crystalline solid comprises its
energy band structure. In a three-dimensional solid, the energy is periodic with respect
to the reciprocal lattice vector k [34], and it is sufficient to specify the momentum in a
representative unit cell o f the lattice known as the first Brillouin zone. The Brillouin
zone identifies an energy surface associated with k or equivalently its momentum, k.
Continuous maps o f energy versus momentum (or k) from the center o f the Brillouin
zone (or T point) to the zone edges at points X and L describe the relation o f energy to
momentum, E-k, throughout the crystal[35]. Figure 5 is a simplified E-k diagram for
AIxGat_xAs with a mole fraction o f x=15% Al. The actual curve o f E versus k is
continuous. The bandgap energy is the distance between the valence band maximum and
the lowest conduction band minimum. An important feature for FET performance is the
location and difference between the conduction band minima at T, L and X shown in Fig.
5. The importance o f these features in relation to FET performance is developed in the
next section by considering other material properties including carrier mobility and
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x=15%
1.921
1.804
lh
Figure 5
hh
Illustration o f A l^G a^A s E -k diagram (Energy - Momentum or
k Vector diagram). Showing the three important conduction band valleys
and their energy minimums at T=300K (T, L, and X ) and the Iight-hoie (lh)
and heavy-hole (hh) bands in k-space (reciprocal space).
saturation velocity.
2.1.2 Electron Velocity and Currents in FET Channels
Knowledge o f the energy band structure and the location o f the conduction band
minima provides insight into IH -V FET performance when related to the carrier mobility
and velocity. A fundamental factor controlling the operating characteristics o f the FET
is the velocity of the mobile electrons in the FET channel. There are several factors that
affect the carrier velocity including the applied electric field and the semiconductor
energy band structure. Therefore, the following relates the applied electric field and the
energy band structure to key concepts characterizing the carrier velocity in m -V
semiconductors such as GaAs. This discussion is used later for interpretation o f results
when comparing measured temperature dependent performance o f a variety o f FETs
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having differing channel materials.
A t low V d 5 bias the FET behaves as a resistor, and the carrier velocity is
proportional to the applied electric field by the low-field mobility, g0, according to,
v (x , T ) = p0 (x , T ) £ j ( x )
(5 )
where x is the horizontal distance from the source electrode to the drain electrode, T is
the temperature o f the channel and £|| denotes the electric field parallel to the gate, which
is also spatially dependent. The low-field mobility is in turn a function o f the effective
mass o f the carriers. For GaAs the effective electron mass is m* = 0.063 while in In^Gaj.
,As
= 0.022. The higher value o f m* in GaAs results in a lower value for pQ. As the
electric field applied from drain-to-source is increased, the carrier velocity increases
linearly up to its maximum at a critical field, Em. A condition then occurs where any
further increase in the carrier energy created by the applied static electric field, is
returned to the lattice with no change in the average drift velocity. This condition is
defined as velocity saturation. The average electron velocity can be approximated by the
following expression [36],
(
2
+ V
VoE +
sat
JS d.
\
V ( E ) , ------------------------------------------------------------1
+(
I
vIff -u~ o £ m \i l ( £
^
*» ~ v-
H
(6)
2 Vm ' V o E m \
Vm-V«*
J
E*
where £ is the magnitude o f the applied electric field, vMt is the electron saturation velocity,
vm is the peak electron velocity and Emdenotes the corresponding electric field. Using
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30
GaAs
InGaAs (53% In)
InP
25
CO
|
20
&
o
><u
10
5
0
5
10
15
20
25
30
35
40
Electric Field (kV/cm)
Electron average velocity (10* cm/s) versus electric field (kV/cm) for
GaAs, lDoj]Oag 4 7 AS and InP at T~300K.
Eq. (6 ), a comparison is made between several materials in terms o f their velocity versus field
characteristics, shown in Fig. 6 , where the variables Em, vm, v ^ and
come from published
data for InP and GaAs [29] and IOo^Gao ^As [37]. In Fig. 6 , the mobility is given by the
slope o f the linear region occurring below the maximum average velocity. Since InP has a
larger effective mass than GaAs the slope o f the linear region for InP is smaller. Beyond the
peak, the velocity drops o ff negatively before it saturates. In this range, the differential
resistance is negative and the earliest class o f IH -V microwave oscillators and amplifiers was
based upon this effect[38]. However, the saturation region above the maximum average
velocity is most important for submicron FET performance and this case is discussed in
relation to the energy band structure next.
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Under velocity saturation, the energy band structure limits to some extent how
the carrier density contributes to the conduction current I d s
The effect upon the carrier
density as the applied field is increased above Emis that the electrons now have sufficient
energy to populate the upper conduction level subbands (L and X ).
transferred electron effect as shown by Ridley and Watkins [39].
This is the
The transferred
electron affect also occurs with increasing temperature, where the movement o f electrons
between the T and L valleys, also called inter-valley scattering, results from an increase
in collisions with the lattice. Electrons that do scatter into the L and X valleys have
higher effective masses and this results in their much slower velocity. This is important
in determining what part o f the available charge contributes to I* , and is discussed in
Section 2 .1 .4. The energy for intervalley scattering is defined by the distance between
the r valley and the next higher L valley and is abbreviated, AEr_L. A relation between
the saturated electron velocity and the inter-valley scattering energy, AEr.L, is given by
the kinetic energy required for such a transition [40],
(7)
where (ve) denotes the average electron velocity. Solving for (ve) in Eq.(7) gives the
following expression for the average saturated electron velocity in a polar semiconductor
31
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like GaAs, where,
(*)
The next section provides a description o f key intrinsic FET model elements in terms o f
the saturated velocity.
2.1.3 Equivalent Circuit Model Relations
The relations given up to this point for the physical parameters are used to explain
a variety o f measured data and modeling results in the later chapters o f this work.
However, in the preceding discussion the origins o f key intrinsic small signal equivalent
circuit model elements (shown in Fig.
1
) have not been addressed.
transconductance, g^, and the output conductance,
Here the
(or resistance R *) are defined, as
well as the drain-to-source current, I* .
In saturation, the channel current in a MESFET is proportional to vMt [41],
a
(9)
h
where a denotes the channel layer thickness, p(y) is the charge density in the channel and
the depth o f the depleted region beneath the channel, h , is given by,
(10)
>
1*4
32
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where es is the semiconductor dielectric constant, Vbi is the built in potential o f the Shottky
barrier and Nd is the donor doping density. Similarly, the carrier velocity in heterostructures
and the currents under the gate are functions o f
and the 2DEG charge density, Q2D. The
transconductance is defined by the change in I* that occurs due to a small change in Vg, for
a given fixed V * bias, and is given by,
g
=
dl.
—
*
(ii)
- constant
Similarly, g * is defined as the change in I* that results from a small change in V * for a
given fixed V_, such that,
(12)
&ds
Vv = constant
The FET D C -IV curves o f Fig. 3 can now be described in terms of Eqs. (11) and
(12). First, the change in I* between the family o f Vv curves for a fixed V * gives gn,
from Eq. (11) and the slope o f a given constant V v curve versus V * gives g * from Eq.
(12). Typically for GaAs, the values o f g„, and g * determined from D C -IV data and their
corresponding values determined from RF S-parameters (to be described in Chapter S),
may have different values. Specifically, why the high and low frequency values do not
agree is related to electron trapping in GaAs, and although models of this effect are
described in the literature[42], such trapping states are not critical to the small signal
models o f this work.
33
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2.1.3.1 Voltage Gain
The elements g„ and g * are not themselves dear indicators o f FET performance,
but a more meaningful indicator o f FET performance and operation, voltage gain, is
expressible in terms o f these quantities. The voltage gain o f the intrinsic FET is defined
by the ratio o f g* to
This is derived using Eqs. (11) and (12) and by noting that, the
change in V * for a small change in Vp is the voltage gain,
for a signal input across
the gate to source terminals and output across the drain to source terminals. For the
intrinsic FET model Av is given by,
V
W g,
V*
dVgt
gdJ
where the magnitude o f the RF signals are typically defined as small compared to the FET
bias potentials. Ideally, for an infinite \
the transconductance approaches infinity (a
large spacing between fixed V 9 curves) and the output conductance approaches zero (a
flat line for the saturation region of the DC IV curves). For example, from the D C -IV
data o f Fig. 3 gmis 90 mS, and g * is 0.001, which gives A*. = 90. The voltage gain w ill
appear later in this work in relation to the noise model o f Fig. 1. To more clearly identify
the importance o f A^ its usefulness in comparing FET performance as a function of bias
and channel material composition is discussed next.
2
. 1 .3.2 Modulation Efficiency
The preceding discussion is based on the assumption that all of the charge in the
FET channel contributes to I* as in Eq. (9). Physically, only a portion o f the total charge
34
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under the gate contributes to I* and this portion is accounted for in several ways. Some
o f the charge is slowed down below v * due to inter-valley scattering, as discussed above,
so the contribution o f this scattered charge is negligible with respect to
Also, in the
case o f a heterostructure FET, the supply layer can hold a charge bound by deep level
traps such that none of this bound charge contributes to I* . Because o f these effects,
there exists a finite ratio of charge that physically contributes to I 4 and the total charge
in the channel. This fact was the basis o f an analytical FET model developed by Foisy
et. al. [43], which defined how well a FET modulates charge under the gate as the
current, I*. Foisy et. al describe this characteristic as FET charge modulation efficiency.
Other works have used the concept o f charge modulation efficiency in relation to the
small signal circuit elements in order to compare differing FETs, which is discussed next.
The charge modulation efficiency can be related to the intrinsic FET equivalent
circuit model elements. This is important to the noise properties o f the FET which are
dependent upon physical phenomena, like inter-valley scattering, that limit the modulation
efficiency. Therefore, the relation reviewed below w ill be important in comparing FET
performance versus temperature, because this description allows one to make
comparisons at optimal bias conditions for FET charge modulation. In Eqs. (11) and
(12), g^ represents the control o f I* by Vv and g^. The conductance g^ is ideally zero,
and is a measure o f how good a conductor the channel is. The capacitance Cv is a
function of the charge modulated under the gate and
is a parasitic resulting from
electric field coupling from the gate to the drain. Kohn et. al. introduced a relationship
between the ratios C9 / Cg,, and g ^ g * for comparing FET channel charge modulation
35
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efficiency, such that,
~
* + % ~~
(14)
&ds
where the linear correlation coefficient, t)k, is an empirical fitting parameter [44]. As
experimentally shown by Kohn et. al., the empirical parameter qk is approximately 0.3
for variety o f GaAs and InP MESFETs, HEMTs and PHEMTs biased at optimal
conditions for low noise. Since a common value o f 0.3 was found for various FET types,
Kohn et. al. concluded that the quantum well confinement o f charge in a heterostructure
offers no improvement in performance versus the 3-D transport in MESFETs. In other
words, the charge under the gate in a HEM T or PHEMT is no more likely than that in
a MESFET to contribute entirely to I* . In this work, a comparison to the results o f
Kohn et. al. is given, but in contrast, this work investigates the results o f fitting Eq. (14)
for three FET types versus both bias and temperature.
2 .1.4 Important m -V FET Channel Types
Considering the importance o f the energy band structure to material properties,
the designer o f a low-noise microwave FET takes advantage o f material systems that
yield a high saturated carrier velocity and high low-field mobility. This choice reduces
noise contributed by the semiconductor channel and the parasitic contacts.
To
understand which materials are used to achieve the best performance, one can compare
the relevant material parameters in Table 3. These parameters include the semiconductor
bandgap (Eg), the electron saturated velocity (vMt), the low-field electron mobility (pe),
the inter-valley scattering energy (AEr.L), and the effective mass o f the electron in the
36
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dominant conduction band minimum (m* = mp/m,,) [45], [46]. Historically, perfonnance
was enhanced in channels made o f GaAs as opposed to silicon channels, because GaAs
has a higher electron saturation velocity, vMt, and a higher low field mobility, p0. The
effect o f
is to increase the operating frequency and the improved pQvalue decreases
parasitic resistances.
Table 3 FET Channel Material Band Structure Parameters and Properties.
1
He(cm2/V -s)
AEr.L(eV)
mp/nio
1 .0
1 2 0 0
-
0.27
1.42
1 .8
9200
0.34
0.063
InP
1.35
2.4
5370
0.63
0.08
^0.53 Ga<)4 7 As
0.78
2 .1
7800
0 .6 6
0.032
InAs
0.354
3.5
33000
1.27
0.0219
GaN
3.45
2 .2
1250
-
0 .2 2
SiC
3.26
2 .0
1140
-
-
Material
Er(cV)
Si
1 .1 2
GaAs
vsat
Note in Table 3, the ternary compound foasGaa^As has a relatively large AEp.^ higher lowfield mobility and a small effective mass, which provide excellent FET channel properties for
high frequency low-noise operation.
It is also instructive to consider how the channel materials have been incorporated
into microwave frequency FETs. The following reviews how materials like those o f
Table 3 are incorporated into MESFETs and HEMTs, and illustrates by example how
fabrication issues present additional choices with respect to FET performance at
microwave frequencies. Figure 7 illustrates a general layering scheme for IH -V FET
structures. The composition o f these layers is identified for several FET types listed in
37
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CHANNEL
Figure 7
Illustration o f a general material layering structure for MESFETs and
HEMTs.
Table 4. Each FET is listed from left to right in order o f performance improvement.
Table 4
H I-V FET Material Systems and Layering Structure
FET Type and Time Scale o f Developmental Progression
1966
1978
1986
1987
GaAs
AIGaAs
InGaAs
InP-Based
MESFET
HEMT
PHEMT
HEMT
CAP
n+ GaAs
n+GaAs
n+ GaAs
n+InGaAs
BARRIER
n+ GaAs
n+AIGaAs
n+ AIGaAs
n+ AUnAs
CHANNEL
n GaAs
p' GaAs
p* InGaAs
n* InGaAs
BUFFER
GaAs
p' GaAs
p'GaAs
n' AUnAs
SUBSTRATE
S.I. GaAs
S.I. GaAs
S.I. GaAs
S I. InP
LAYER
38
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I
I
I
Advantages o f HEMTs over conventional GaAs MESFETs for millimeter-wave
applications are well recognized [47]. Greater performance was first achieved over GaAs
MESFETs by using an AlGaAs/GaAs heterojunction to physically separate the mobile
electrons from their parent donors. By adding Indium to the GaAs channel to form
InGaAs, channels with even higher saturated velocities were achieved. W hile electron
mobility and carrier density are increased as the Indium concentration is increased, this
effect is limited by the strain caused between the GaAs substrate and the InGaAs channel
[48]. Because the crystal lattice dimensions o f these compounds are not the same, the
epitaxial layering o f InGaAs onto GaAs requires some strain at their interface. HEMTs
using these strained-layered structures are referred to as pseudomorphic HEMTs.
Eventually, a critical thickness o f the In^Gai.^As channel layer is reached and the lattice
will relax and form structural defects at the interface, such as misfit dislocations, which
degrade the channel conduction qualities [49].
In contrast to the conventional or pseudomorphic GaAs-based HEM T, the InP
HEMT incorporates an In^Ga^^As channel with higher indium concentrations (x > 53%),
and these alloys can remain latticed matched to the InP substrate. Compared with GaAsbased InGaAs/GaAs PHEMTs, the AlInAs/InGaAs/InP system exhibits higher electron
sheet densities and a higher room temperature mobility. For example, the peak electron
velocity is higher for the lattice matched channels having 53% In versus 25% in the GaAs
PHEMTs.
The previous discussion leads to the following question, can a promising material
like In^Gaj.jAs be applied to manufacture MESFETs with performance that rivals
39
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PHEMTs? Or is a heterostructure required to achieve the best FET performance with
the same channel material? Originally, heterostructure FETs were found to achieve
performance enhancements, such as improved v ^ and improved channel current
modulation efficiency when compared with MESFETs. As noted by Feng et. al., Mimura
suggested that such improvements are expected due to the quasi-2D transport in
heterostructures [79]. But based on interpretation o f the preceding discussion, these
improvements are dictated primarily by the energy band structure o f the channel material.
To demonstrate this point, Feng et. al. have fabricated low-noise InxGai.]tAs FET channels
to improve microwave performance over GaAs MESFETs [SO].
Upon comparing
MESFETs and HEMTs with Ii^Ga^jAs channels, Feng et. al originally concluded that vM
was more important to low-noise performance, than low-field mobility, at both cryogenic
and non-cryogenic temperatures.
A fter further investigation, it was shown that
MESFETs can be fabricated using an epitaxially grown Ia^Ga^^As channel on a GaAs
substrate with performance that rivals HEMTs [50], and that this was due to the larger
AEr.L in I^GapjAs, depending on the molar fraction o f indium, compared to that o f
GaAs.
Further evidence that supports the conclusion o f Feng et. al. is found in cases
where the heterostructure scheme used to free the carriers from collisions with their
parent donor ions is upset by placing the donor ions within the potential well. This is the
case with the doped channel HFET [51]. Doping within the quantum well is not found
to seriously degraded mobility [52]. The next section relates FET noise to the physical
and electronic properties o f m -V materials reviewed in this section. Specifically, the
40
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ii
t
!
*<'
_
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same material parameters, including v^,, A E ^ n„, Er etc., are important to microwave
and millimeter-wave FET noise mechanisms.
2.2. A REVIEW OF PHYSICAL MODELS OF FET NOISE
In the previous section, the impact o f material properties on the flow o f current
and the voltage gain o f a FET were interpreted. Similarly, microwave FET noise is the
result o f electron transport through the FET channel, where electrons are subject to
random interactions with the crystal lattice, ionized impurities, other carriers, etc. There
are a variety o f ways that these random interactions are modeled including: microscopic
models based on scattering induced fluctuations o f carrier velocity, mobility and
concentration, and macroscopic models based on noise power spectral density. Each o f
these solutions has been pursued in the literature, yet there exists a disjoint between
scientists using microscopic models o f FET physics and engineers developing
macroscopic models such as those in Table 1 for circuit design.
In this section, a review o f microwave FET noise theory is given to provide a
physical interpretation upon which experimental results and equivalent circuit model
values may be compared. The point o f this review is threefold: ( 1 ) to introduce the
dominant types of noise in FETs at microwave frequencies ( 2 ) to review physical
interpretations o f FET noise used in existing analytical models, and (3) to introduce some
o f the limitations and restrictions o f analytical and/or physical models.
2.2. 1 Types o f FET Noise
An illustration in Fig.
8
displays cross-sectional views o f a PHEMT, which
introduces the location and types o f noise generated within the FET. Noise mechanisms
41
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in a MESFET are analogous to those shown here, except that the channel is 3-D. Just
as the static bias conditions on the FET affect electron transport under the gate, the bias
conditions also affect the channel noise. A t low applied fields, the FET channel and the
parasitic contacts are governed by Nyquist’s relation and the noise spectral density is
proportional to the equilibrium temperature o f the system [53]. Thermal noise in FETs
is a function o f the low-field mobility o f the transistor. Recall from Eq. (1) that thermal
noise is independent of frequency in the range o f interest. A similar effect was identified
for the noise generated in a doped semiconductor under low electric fields and is known
as Johnson noise. For higher V *, biases the electron velocity saturates due to intervalley
scattering and FET channel noise is no longer determined solely by the equilibrium
temperature [54],[10], The noise generated under these conditions is generalized w ith
S.I. Substrate
Figure 8
Physical relation of FET noise processes and the geometry o f a typical
GaAs PHEMT ( I) thermal noise, (2) Johnson noise, (3) high field diffusion
noise and (4) shot noise due to gate leakage.
42
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respect to the diffusion o f electrons (diffusion noise) or with respect to electron velocity
fluctuations (fluctuation noise). The effect o f velocity saturation is explained further in
the next section, and is the basis o f understanding the dominant noise in microwave and
millimeter-wave FETs. The fourth type o f noise in Fig. 9 is due to processes such as
tunneling across material interfaces and is known as shot noise.
In contrast to the noise power spectra of the microwave frequency processes (1-4) o f
Fig. 8 , which are all frequency independent, the spectra o f frequency dependent noise sources
follow a 1/f8 characteristic, where a ~ l is the Hooge parameter [9]. Figure 9 illustrates the
output FET noise current power spectra versus frequency for a typical FET, where the region
dominated by 1/f noise is marked by the comer (or knee) frequency fj. The origin of
frequency dependent noise has been a topic o f research for many years [55], [9], and is
associated with fluctuation o f the number o f carriers. The importance of continued study of
such phenomena was stressed by Pucd et. al. [ 1 0 ], and an experimental study o f the trapping
and de-trapping o f carriers in the surface region and in the space charge region was ultimately
conducted [56]. In this work, only the effects of microwave frequency noise are investigated,
and the 1/f region (below 2 M Hz) of Fig. 9 is avoided during measurement. However, other
sources of noise due to material inhomogeneity and fabrication limitations may result in noise
generating factors, such as leakage currents, that result in a frequency dependence of the
FET’s noise spectral density in the microwave region.
43
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1/f Noise Region
Microwave Noise
Region
N
X
o
CO
1.0
Figure 9
Frequency (GHz)
Illustration of output noise power spectral density,
(GHz) for a typical microwave FET.
(A2/Hz) versus frequency
2.2.2 Velocity Saturated Noise
O f the variety o f noise processes in the FET, models o f noise in the channel region
differ the most. This depends in varying degrees upon velocity saturation. In this regard,
the relation o f the channel noise to the equilibrium temperature requires further
discussion. Previously developed analytic FET noise models have shown the importance
o f the effects o f velocity fluctuations and inter-valley scattering on modem submicron
FETs.
There are roughly three classes of analytical models for FETs. These include: (1)
those that assume noise is generated primarily by ohmic conduction in the FET channel,
( 2 ) those that assume noise is generated by both ohmic conduction and velocity saturated
current flow and (3) those that assume noise is generated primarily by velocity saturated
current flow. These models have developed as the gate length has decreased and the
emergence o f velocity saturated current flow has become dominant in short gate length
FET channels.
44
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Reviewing the developments for the models o f each class o f current flow, recall
that in an ohmic conductor, the diffusion coefficient, D, is related to the temperature by
the Einstein relation,
(IS)
where q is the electron charge and T is the electron temperature. The first FET noise
models were based upon a constant mobility with an electric field due to V * that changes
slowly with position [25]. Experimentally, channel mobility fluctuations in the low-field
case result in a fluctuation o f the channel conductance[57]. These assumptions comprise
the gradual channel approximation, GCA, first used by Shockely[25]. Other recent
examples describing noise generators for the well known gradual channel approximation
o f the FET were studied separately by Brewitt et al. [57] and Delagebeuf et. al. [58],
While the GCA is accurate up to the knee region o f the D C -IV curve, Fig.3, it does not
include the effect o f velocity saturation. Because o f this, models emerged which included
regions o f both ohmic conduction and velocity saturated current flow. In practice, a field
dependent carrier temperature for FET channels with small velocity saturated regions was
considered first by Baechtold [59], Similar models followed that eventually led to a
variable model boundary between the two regions dependent upon the spatial variation
o f the electric field, Grebene and Ghandhi [54].
For sub-micron gate length FETs, carrier transport is primarily velocity saturated.
To understand the dominant noise processes under this condition, recall the relation o f
va to key material parameters such as the inter-valley scattering energy, AEr.L. Due to
45
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I
the transferred electron effect, current flow in GaAs FETs is dominated by noise due to
by inter-valley scattering[51] and high field diffusion [60], [10]. The spectral density is
expressed in the form o f the Nyquist relation, but the appropriate temperature is now the
electron temperature[10]. This is different from the previous model since, it is well
known that the ensemble electron temperature is much larger than the ambient
equilibrium temperature. As a result, high field diffusion noise is often called “hotelectron” noise.
In a velocity saturated channel, Ohm’s law and Einstein’s relation for the diffusion
coefficient are no longer valid. Further treatment for the velocity saturated FET was
given based upon quasi-equilibrium conditions defined in the work o f Pucel et. al. [ 1 0 ].
The noise spectral density may still be determined from the conductivity o f the channel,
but this requires some further knowledge o f the field dependence o f the diffusion
coefficient, D . The conductivity o f the FET channel may be expressed in terms o f the
diffusion coefficient parallel to the gate as,
q%
°
n
-k p r
™
where n is the carrier concentration. I f the diffusion coefficient in Eq. (16) were known, then
this result could be applied to Nyquist’s relation. However, as reviewed next, knowledge of
D requires much theoretical development and/or complex measurements.
46
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2.2.3 Numerical Noise Modeling Issues
A large body o f theory already developed for FETs has allowed the development
o f full numerical noise models [9],[10], [61].
For modem sub-micron FETs the
development o f a noise model based upon physical phenomena involves analysis o f
electron transport and the related energy and momentum balances, as well as the effects
o f carrier collisions [62], [63]. The relevant material parameters, such as diffusivity, for
numerical simulations can be deduced from Monte Carlo calculations [64]. Carrier
transport equations are typically solved using a relaxation time approximation together
with Poisson’s equation. W ith the conditions o f current continuity imposed upon the
channel, the mean square value o f the noise current related to each section o f a sub­
sectioned FET channel is modeled for example by,
q 2 N. v.
( j 2).j = — —L J~ ( v . )
(A 2/mm)
(17)
where (v ^ ) is the average quadratic drift velocity, N( is the carrier density, y t- is the
channel thickness, and Ax is the length o f a sub-section o f the channel in a numerical
model. The term y,- Nj f A x represents the number o f carriers in a sub-section. The
resulting noise power spectral density is determined from velocity-field considerations
with a diffusion coefficient [9], [65]:
{A11Hz I mm)
where
(18)
is the longitudinal diffusion coefficient. In spite of advances made in such
numerical schemes, the experimental determination (or verification) o f Z)|( is difficult,
47
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i
i
which leads to uncertainty in these models.
This situation is apparent for a few reasons including: ( 1 ) the fact that the
diffusion versus field relation is difficult to measure in a real device [6 6 ], [67], (2 ) Monte
Carlo simulations are regarded as more reliable than measurements, but conflicting results
occur [6 8 ], [69] and (3) the diffusivity is device dependent at the high fields and small
dimensions o f modem FETs. For example, the Einstein relation between the diffusion
coefficient and the mobility is not valid for a degenerate semiconductor and the relation
must be determined from approximate methods, such as the Joyce-Dixon
approximation[34]. Additional complication arises since p 0 and D |( are geometrically
related and bias dependent, which makes the development o f a variety o f models for
varying geometries and FET technologies difficult.
These facts together with the
additional need to investigate thermally induced variations have led this work toward
alternative means using experimentally derived equivalent circuits.
2.3
CHAPTER SUMMARY
This chapter reviews basic principles and differences in several dominant FET
technologies used at microwave and millimeter-wave frequencies. An introductory
discussion reviewed key operational characteristics, such as D C -IV curves, velocity
saturation, pinch-off and gain. Further understanding o f FET operation was described
relative to the energy band structure o f the channel material. By understanding how the
channel material affects a FETs performance, comparisons between FETs o f differing
semiconductor compositions were presented. This review explains why the compound
Ir^Ga^jAs (with a high, x > 53%, indium mole fraction) has enabled high gain and low48
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noise FET circuits. A review o f related literature on models o f physical noise generating
processes in FETs was presented in contrast to the experimental models described in
Chapter 1. The limitations o f physical models with respect to the goals o f this work have
traditionally made experimental models attractive to the design engineer. The next
chapter begins by describing the advantages o f equivalent circuit models for use in
microwave frequency FET small signal and noise modeling, and reviews the relevant
theory for the development o f equivalent circuit models.
49
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CHAPTER 3 CIRCUIT MODELING THEORY
3.0 INTRODUCTION
la contrast to the limitations o f theoretical models, experimentally-based
equivalent circuit models can be broadly applied to modeling FET noise. The theory
underlying the noise models o f Table 1 in Section 1.2.1 describes the internal noise o f the
FET in terms o f equivalent circuit elements.
This approach is advantageous for several reasons:
•
First, the models are empirical and, as a result, they adapt to new FET materials
technology and layout geometry. These models also retain a physical correlation
so that comparisons can be made.
•
An equivalent circuit model may also be simplified by lumping several effects
together, such as grouping the extrinsic and intrinsic noise into two equivalent
elements. In contrast, several equivalent sources can be specified, one for each
o f the intrinsic and extrinsic noise sources in a FET.
•
Furthermore, equivalent circuit models are computationally efficient and require
few parameters as compared to numerical models developed from a “first
principles” approach.
The following describes the results o f the theory for linear noisy two-port networks
developed in the late I950's [70], [74]. Later developments which make the mathematics
50
i
!
i
f
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for two-port noise calculations more efficient appeared in published form in the 1980's.
This secondary development implements the “noise correlation matrix” technique which
enhances the analysis.
The modeling techniques are based upon the theory o f noisy two-ports, which
describes concepts for modeling noise with equivalent noise generators and applying
standard circuit analysis. Because the equivalent noise generators are treated as nonrandom sinusoids, their correlation must be related a priori. To ensure that this is done
properly, this work presents a derivation o f limitations on the noise parameters and the
noise model.
3. 1 EQUIVALENT CIRCUIT MODELS OF NOISE
A classic reference on modeling noise in linear noisy two-port networks, such as
the small signal FET model, is the work o f Rothe and Dahlke [70]. The general concept
presented in Fig. 10 is that the internal noise o f the two-port can be concentrated into a
pair of lumped equivalent generators. In this model, the internal noise generated by the
FET is represented by two equivalent noise generators inI and in2. Two-port models such
as Fig.
10
(b) figure prominently in this work for the analysis o f noise in FETs.
Since
these generators represent random variables in time, their description is typically given
in terms o f statistical averages rather than as signal functions. From this representation,
the theory o f noisy two-ports shows that the noise in a linear two-port can be
characterized by a set o f noise parameters (four real numbers). This result is amenable
to varied combinations o f noisy current and voltage sources.
51
i
]
•i
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M
noisy
two-port
(a)
noise-less
Figure 10
(b)
Noisy two-port equivalent circuit models for (a) a noisy two-port
admittance and (b) an equivalent noiseless two-port admittance with
associated noise generators i^ and i^..
The random processes inherent to the carrier flow are expected to produce noise
representative o f stationary random variables having finite amplitudes. For small signal
modeling, the central limit theorem is envoked to approximate the ensemble of random
variations in carrier flow by a Gaussian distribution with zero mean. Since the signals are
stationary, or ergodic, the ensemble average is equivalent to the time average. This results
in equivalent circuit model elements that are treated as independent sources. The only
difference between these noise generators and regular current or voltage sources is that they
may be statistically correlated. For example, an open-circuit noise voltage v(t) across a port
can be equivalently represented by its mean square value, v 2 (r), or its
52
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[
I
spectral density, Sw(co), or its Fourier amplitudes, Fm(&>) as,
v2( / ) = Um I
v2(/)<# = / "
=
£
| ^ * ( “
) | 2
(W)
where the amplitudes Vm are those obtained as T-*°°. This fundamental relation o f the
noise power spectra to mean squared noise currents or voltages is given by the WienerKhintchine theorem [71].
For circuit design or analysis, it is desirable to treat the noise generators as nonrandom sinusoidal sources so that KirchhofFs laws can be applied. To discuss the theory
o f noisy two-ports in relation to the FET models that have been introduced, recall that
the intrinsic small signal model is a noiseless network, and the noise generators are
impressed upon it. Figure
10
illustrated this concept, and Figs. ll(a -c ) show various
networks based upon the theory o f noisy two-ports. The first of these networks uses
noise current generators as in Fig. 11(a), which are amenable to an admittance parameter
formulation and parallel connected two-port analysis. A hybrid model in Fig. 11(b) is
applicable to a FET, where gate noise is due to gate fluctuations and the drain current
dominates the output noise o f the FET. Finally, Fig. 11(c) locates all o f the noise at the
input o f the two-port.
53
• i
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V .1
noiseless
(a)
noiseless
(b)
[ABCD]
noiseless
(c)
Figure 1 1
Noisy two-port networks used for FET noise modeling (a) parallel noise
generators and a noiseless admittance matrix (b) hybrid parameter network
matrix and series/parallel noise generators and (c) series/parallel noise
generators and a noiseless chain matrix.
54
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The short circuit model is described by its y-parameter definition o f the open
circuit and short circuit currents in Fig. 11(a),
A
> i
u r*
A
7*
+
V
(20)
/V
Another useful form for FET noise modeling is a hybrid parameter model o f Fig. 11(c)
described by open circuit input voltage and short circuit output noise currents,
hl2
> 1
A
+
h?i
V
(21)
*
1
.A.
The chain matrix representation which transforms the output noise current
to the input
•
resulting in a series parallel combination, for the circuit o f Fig. 11(c) is described by,
K
A B
A .
C D
+
[ A J
(22)
A.
Each two-port represents a different set o f noise parameters. For the admittance model,
Fig. 11(a), these are,
Gi =
4 kB T A /
4 kB Ta A /
(23)
9C =
l n l l n2
:,
where p is complex.
'- H U *
55
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For the hybrid model (Fig. lib ) the noise parameters are,
I5T
e*\2
4 kB Ta A /
4 kB T0 A /
(24)
e n h ink
pch = ------------------,
where pA is complex.
/F
Also for the chain matrix or (ABCD matrix) model (Fig. 11c) the noise parameters are,
R. =
*
Sn *
4 kB r„ A /
”
'■I*
4 k , T„ A/
(25)
e„ #
P = ----------------- .
where p is complex
•-I* Kl*
The noise sources in Fig. 11(b) are typically transformed into the model o f Fig.
11
(c)
where ea and ^ are now uncorrelated, and their formerly correlated component is
developed in the fictitious admittance Yc. The elements o f Fig. 11(c) are the equivalent
noise resistance and conductance ^ and Gn and the previously mentioned correlation
admittance given by,
v
Y C
_
- =
n ft
(26)
en <
56
<
_
_
.
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iI
The uncorrelated part o f in is then associated w ith a new term Ga as,
me
2
4kBT0* f
where
—
in - Y ce
2
n
(27)
4kB TQL f
denotes the uncorrelated part o f
The various equivalent noisy two-port
forms reviewed here are useful in developing a definition o f noise figure.
The
representations are also used later to deembed the various sources o f FET noise from a
more commonly measured set o f noise parameters.
3.2. DEFINITIO N OF NO ISE FIGURE
In relation to the analysis techniques discussed above, it is useful for a circuit or
system designer to have a measure o f how much a signal is degraded by FET noise in an
amplifier. The circuit designer also requires an indicator for optimizing FET noise
performance when a FET is used as an amplifier. The noise figure, F, is described as the
signal-to-noise ratio at the input port compared to the signal-to-noise ratio at the output
o f a linear two-port. The noise figure is expressed in decibels as,
-
F =
1A
10
,
Input signal to noise ratio
in .
• log — ----- 2— ---------------------= 10 • log —— Output signal to noise ratio
^ / iVo
.
( dB )
ram
where S; / Nj denotes the input signal-to-noise ratio and SQ / N 0 denotes the output
signal- to-noise ratio. Alternatively, the quantity known as noise power is defined as,
Pn = kBTB, where B is the bandwidth o f the measurement, kB is Boltzmann’s constant
and T is the reference temperature in Kelvin. Since a change in the input noise would
change F, the noise figure is standardized to a reference temprature known as Ta which
57
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by convention is given the value o f 290K[68]. The ratio in Eq. (28) is known as the
noise factor, NF, and is given by,
jyp.
____________ Totalavailableoutputnoise power_________
Portion o f output noise power due to the generator resistance
(2 9 )
The noise figure written out in terms o f Eq. (29) becomes,
AT + kB TaB G
1 0 - ‘eg « ■ >
F -
(30)
where Gdenotes the available gain o f the two-port and Na denotes the noise power
added by the two-port. The noise power added by the two-port is commonly w ritten in
terms o f an equivalent noise temperature, Te, such that Na=kBTcB. Substituting Na into
Eq. (30) and then solving for Te yields the expression,
Te = T0 { N F - \ )
(K )
.
(3 i)
Using these definitions, the noise factor o f the uncorrelated chain matrix model o f Fig. 11(c)
is written in terms o f the ratio o f noise input by the generator impedance and the noise added
to the output by the intrinsic noise generators o f the two-port,
r„ ]
For an input generator with a known impedance, and a two-port network at thermal
equilibrium, the term 4 kB T 0 factors out and the noise factor equation becomes,
58
i.
_ _ _ _____ __
__
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(33)
The noise factor equation o f the two-port model with a generator admittance Y gen =
Ggcn + jBgcn can now be written as [70],
(34)
where the optimum generator admittance, Yopt = Gopt + jB opt, is the value o f
that
minimizes NF. The components o f the optimum noise matching admittance are,
G.opt
(35)
Solving for the minimum noise factor (NFm,-n) and substituting into Eq. (30) gives the
noise parameter equation,
II tgen where quantities NFmjfB
t opt
2
(36)
and Rqare four commonly measured noise parameters for a two-
port network at microwave frequencies [72]. Another quantity, N = R„ Gopt = gn R opt, was
introduced by Lange to replace
because R,, is sensitive to measurement conditions. The
usefulness of N is that it is invariant upon a transformation of the two-port reference plane,
through a lossless embedding network or transmission line [73].
59
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3.3
NOISE CORRELATION M A TR IX REPRESENTATION
The linear two-port noise models o f the previous section relied upon the
relationship between the spectral densities and the mean-square fluctuations to describe
the noise factor. Unfortunately, these nodal type representations become cumbersome
in the analysis o f larger circuits and multi-ports. However, a matrix based notation, used
in place o f the lengthy nodal KirchhofF equations, simplifies the analysis to an algebraic
form. This section introduces the noise correlation matrix and its relationship to the
noise factor.
The normalized noise correlation matrix for the admittance representation, Cy, of
Fig. 11(a) is,
1
4
kB Ta A /
Ki
*nl
. *n2 .
*n2 .
t
K l^ r a
1
4
kBT M
'n lK l
(37)
I 'J 2 .
where t denotes the transpose conjugate, the overbar denotes a statistical average and
* denotes a complex conjugate [74], The correlation matrices possess the following
properties,
c* . * °c^ i 0 -
(38)
C* , ■
d« ( C ) * C,„ C,„ '
C
I3
*2 1
60
*/
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I
Taking the conjugate o f the transposed matrix, [[Cy]*](, yields the adjoint [Cy]r. This
does not change the relations in Eq. (33), (ie. the correlation matrix is equal to its
adjoint). Therefore, a noise correlatin matrix is referred to as self-adjoint or Hermitian.
The noise correlation matrix is also nonnegative due to the relations in Eq. (38). A
general form o f Nyquist’s relation describes the noise correlation matrix for passive linear
two-ports in terms o f the network parameter matrix[74]. For example, the admittance
matrix is,
c, = 2*„r,d/(r + n) .
(39)
A similar relation exists for an impedance matrix representation by substituting the
impedance matix for the admittance matrix.
Several mathematical operations are needed to analyze circuits with the
correlation matrix These include transformation o f one network form to another and a
procedure for connecting noisy two-port matrices.
The transformation between
representations is accomplished by an orthogonal (also called a congruence) transform
o f the original matrix,
C' = T C P
(40)
where C ' is the desired noise correlation matrix, C is the existing one and T is the
necessary transformation matrix The T matrix is developed by applying short circuit and
open circuit conditions on the relations Eqs. (20-22) such that an equivalence between
the existing and desired form is determined.
For reference, a table o f T-matrix
61
if
j
I
f
r
<
.
_ _
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f
conversions between admittance, impedance and chain matrix forms is found in [106],
A solution for the transform from chain matrix to the hybrid matrix format is given in
Appendix A, since such a solution is not typically found in the literature and is important
for FET noise modeling. The algebra for interconnecting noisy two-ports is similar to
the network parameter formulation. Impedance and admittance correlation matrices
corresponding to series or parallel connected networks simply add. For a cascaded pair
o f networks (a) and ( 6 ) an overall matrix C ^ b ) is written as,
CA = /4 (a)C j6 )4 (a)t + Cja)
(41)
where A(a) is the ABCD-parameter matrix o f two-port (a). Finally, an expression for the
noise factor in terms o f the chain parameter correlation matrix is,
# C AZ
NF = 1 +
Re { * - >
(42)
Z =
gen
where Z denotes the two-port impedance matrix, Re denotes the real part and Zgen is the
generator impedance. In turn,
may be written out in terms o f the noise parameters
o f Eq. (36) to yield the relations,
62
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r
\
C«n
C , ]
2
12
mcA
+ J
f r C *1
A1
mcA
which is an important result used extensively in the experimental modeling done in the
later chapters o f this work.
63
i
(
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3.4
FET NOISE MODELS
Two dominant models from Table I are discussed here to introduce how
equivalent noise generator elements are used to model FET noise. For example, Fig. 12
represents a standard small signal model o f the intrinsic FET with a common source
connection. The thermal noise sources associated with the parasitic resistances R„ R,
and R,, are omitted for illustration. Impressed upon this noiseless equivalent circuit are
Gate
Drain
Source
Figure 12
Microwave equivalent circuit model for the noisy FET, characterized by two
equivalent noise generators and i^.
two noise generators whose mean squared values are characterized by the correlated
quantities e„g and i^ . These quantities are determined by the small signal model elements
64
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and by a circuit transformation o f the noise generators which yields the relations,
£
5
=
4 kg T A f P g m
= 4 *8 r i / - 5 .
(44)
(45)
where the overbar denotes a mean value, A f denotes the noise bandwidth, T denotes the
reference temperature, g,„ is the transconductance o f the FET and R and P are nondimensional coefficients previously described. The noise generator coefficients R and P can
be developed from device physics [ 1 0 ] or used as fitting coefficients. Solutions for the
unknowns in Table 1, through their equivalence to the models in Fig. 1l(a, b and c), are
detailed in Chapter 3. As an example o f the first step in this process, comparing Fig. 11(c)
and Fig. 12 one finds R„ and g„ of Eq.(25) to have an equivalence given by [10],
= Rfgm
s„ = Pgm
(46)
where C is a complex variable representing the correlation between the gate and drain
noise generators.
A similar model, shown in Fig. 13 [11], develops equivalent mean squared noise
generators with the uncorrelated thermal noise o f resistors Rj at the input and Rds at the
output.
65
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Drain
Source
Figure 13
Microwave equivalent circuit model for the noisy FET, characterized by two
parameters Tgand Td.
Their respective equivalent temperatures, Tg and Td, are the fitting coefficients in this model.
The value o f the noise temperatures Tg and Td are in general different than the ambient
temperature, but as noted in [ 1 1 ] their values may be experimentally determined.
Comparing the model of Fig. 12 to the model of Fig. 13, gives equivalence relations
for the two models,
(47)
To calculate the coefficients P, R and C or Tg and Td the expressions for the noise
parameters in Eq. (36) are equated to Eqs. (46) and (47). Before these relations are
considered further, the next section reviews the underlying mathematical interrelations
66
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between the noise parameters that w ill enable a robust determination o f P, R and C or Tg
and Td.
3.5. TWO-PORT NOISE PARAMETER INTERRELATION
A fundamental relation in the theory o f linear noisy two-port networks is that the
two-port noise generators cannot be more than 100 percent correlated. This condition
must hold for the noise parameters to represent a physical device.
However, this
criterion can be violated by errors in measured noise figure data that is then used to
determine the noise parameters. This criteria also applies to the mathematical procedure,
which is known as deembedding, that separates a desired set o f parameters o f an internal
network from measured parameters. In modeling a two-port such as a FET, the
procedure for deembedding may start from noise parameter data that satisfies the
correlation criterion, but an incorrect deembedding technique can later invalidate the
resulting intrinsic noise parameters. For example, parasitic elements that are inaccurately
determined can cause such errors upon deembedding. Since the noise parameters are
prone to these errors, the properties o f the noise correlation matrix are discussed in more
depth below.
3.5.1 Interrelations of the Four Noise Parameters
In this section, a review o f available literature reveals an important criterion that
applies to two-port noise parameters. To begin with, the noise parameters may be
substituted into the correlation matrix description o f Eq.(37). From the nonnegative
definite properties o f the Hermitian matrix introduced in Section 3.3, one finds that,
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
(48)
[Pi s 1
F m m '1 S
R n G op'
An additional statement on the limitations o f the two-port noise parameters is the
inequality [14],
4NTa
(49)
nun
where N is the previously described invariant noise parameter [73] and Tmin is
expressed as noise temperature using Eq. (31).
This relation was developed by
Pospieszalski and Wiatr, who note that the lower bound in this inequality has the physical
interpretation that no pair o f noise sources can be more than 100 percent correlated. The
derivation o f Eq. (49) has not been published in the available literature and the upper
bound applies only to the modeled two-port noise parameters, not the measured values.
Since the baseline procedure of this work relies upon measured noise parameters, the
following investigates Eq. (49) in further detail.
The physical condition imposed upon the lower bound (described above) and the
complex-valued correlation coefficient are now established in mathematical terms. The
correlation coefficient, p, for zero mean, Gaussian noise sources is given by [75],
(50)
68
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where x and y may be either e or / depending upon the noise generator representation
chosen from Fig. 11. For example, in the case o f the chain matrix format of Fig. 11(c),
x = en and y —in. In this discussion, the correlation matrix (ABCD form) is also useful
if it is written in terms o f the noise parameters as,
CA = 4 kBT b ,f
(51)
where Fe is used in place o f the quantity ( F ^ - 1), and for this discussion, Fmtn is
understood to be a scalar magnitude and not in decibels in order to avoid later confusion
with the parameter N. The limitation o f two physically correlated generators is usually
w ritten
-1
< p s + 1 . However, for the complex-valued correlation coefficient pz ,
boundary limits are defined by a unit disk in the complex plane such that, I Pz I S +1.
This is the argument upon which the following analysis is based.
The following gives a proof o f the lower bound based upon the relation o f noise
parameters o f two noise sources which have a complex correlation. Furthermore,
choosing to solve for | pz | in the proof provides a fundamental upper lim it to the result.
The analysis procedure is based upon a common method used to prove the CauchySchwartz (or triangle inequality) in complex analysis. In the following discussion, the
square o f Eq. (50) is solved first, and the desired result is simply found by taking the
square root. To begin with, one may write the square o f the noise correlation coefficient
as,
69
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i p j 2 - i p j i = pzp; * i
(52)
Equating Eq. (50) for pz with the necessary terms o f CA in Eq. (51) gives,
F,
- f - W m
Pz
F
—
- Rw
Y 'op
2
Pr = A
(53)
Multiplying terms in the numerator finds,
/e
|r„|*
-
2
PzPz =
(54)
opf
Since Re[
]
5
|
| and positive, this may be factored into a quadratic form which
yields the inequality,
(55)
Pz Pr 5
opr
The result for the squared quantity is,
Y
Pz
- R n\ r opt
£
(56)
R: K < \2
Taking the square root o f this result and enforcing a unit disk (|pz|= l) as the limit on the
70
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complex correlation coefficient gives,
■»
"
1
(S7)
To complete the proof, a rearrangement o f terms finds the desired complex form o f the
lower lim it on the noise parameters,
m m
- I
7V
,
ly im
where the right-hand fraction has been written in terms of
,5 8 )
for comparison to Eq.(49).
Comparing this result with the previous expression given by W iatr and Pospieszalski in
Eq. (49) shows that the reactive component o f the inequality is now included.
To obtain the form of Eq. (49) from the result in Eq. (58), recall that
and the
product Rn'Gop, (or N ) are invariant to a lossless transform o f a port reference plane. If
the lossless transform is chosen to resonate out the reactive part o f Yopt then only the
invariant parameters remain. Therefore, W iatr’s result is valid upon deembedding a
lossless reference plane extension, just as Lange’s work describes [73]. However, the
general complex valued result is manifest anytime the reactive component (X opt) o f the
optimum noise matching impedance is not resonated out.
For measured noise
parameters, |p| must still be less than or equal to unity, but the upper limit o f Eq. (49) is
no longer exactly two.
This effect upon the upper limit o f Eq. (49) becomes necessary in evaluating
topologies for which invariance o f Fmin and N is not valid. For example, two common
networks that appear in the topology o f the extrinsic FET include; various combinations
71
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o f series feedback, and a lossy transformation o f the reference plane. This is important
because series inductive feedback constitutes an industry-standard topology for low-noise
microwave amplifier design [76], and deembedding o f the gate resistance is fundamental
to understanding intrinsic FET noise [13]. This applies to the modeling o f the intrinsic
noise generators o f the FET by noting that i f the inequality is not satisfied upon
deembedding, then the deembedding was in error and not the measured noise parameters.
The two criteria may be written in a conditional form as,
4N T
- ,
lossless deembedding.
(59)
IF f|
— ,
feedback applications.
To place a lim it on the upper bound o f this inequality, note that the following
must be true,
This upper limit must hold for both measured and modeled noise just as the lower limit
applies. When the upper bound o f Eq. (60) is violated then there are true numerical
errors in the measurement or modeling of the noise parameters. For frequencies where
fcff, the criteria for the upper bound in Eq. (60) may be simplified by applying relations
between the noise temperature model and the noise parameters (using Eqs. 101 (a-d) of
72
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Section 5.3.2) to give,
(61)
where gds= I/R ds. While the earlier limit o f Eq. (49), given by the value o f 2, is an
inherent limit o f the intrinsic model only [77], Eq. (61) relates how the deembedding o f
the noise parameters can yield non-physical parameters. For example, extrinsic values
o f the transconductance and output conductance are related to the parasitic resistors by,
(62)
where gmext and gdscxt denote extrinsic values for gm and gds. Therefore, if Rj is
extracted too small, then gn, becomes smaller than it should be, which increases the righthand side o f Eq. (61).
In summary, based upon this result for the lower and upper bounds, the following
observations are noted,
1.
Only for a purely real correlation, such that Bopt = 0, does the usual result o f Eq.
(49) imply an invariant criteria for the interrelation o f the noise parameters. That
is, the criteria is invariant to a transformation of a reference plane through a
lossless embedding network or transmission line.
2.
For a purely imaginary correlation, such that Gopt = 0, the numerator o f the
inequality Eq. (49) is given by 4
, which is not invariant.
73
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III
3.
For any other nonzero combination o f partial correlation between a physical pair
of noise sources, pz is bounded on the right-hand side by the triangle inequality
o f complex analysis. This condition is also not invariant to a lossless transform
o f the two-port input reference plane.
Therefore, a new fundamental natural limitation on the interrelation o f the noise
parameters o f a physical two-port with two correlated noise generators has been proven.
This proof provides natural upper and lower limits to the interrelation o f the noise
parameters. This solution is applied as an analysis tool for deembedding FET noise from
lossy parasitic networks in the remainder o f this work.
3.5.2 Data Comparisons and Examples
The criteria limiting the noise parameter values are applied to all models
developed in this work. Hereafter, the criteria o f Eq. (49) is referred to as K t and the
complex valued term of Eq. (58) is denoted K2 .
To show that Ki and Kg are equivalent upon the transformation o f the noise
parameters through a lossless embedding network, an example o f series feedback applied
to a FET is given. The simulation o f a variable inductance connected to the source
terminal o f a FET data model is shown in Fig. 14. In Fig. 14, the deembedding o f the
reactive component o f
due to the applied series feedback appears as a minimum in
the output o f the criteria K2. The variation o f both criteria K | and K2, as plotted with
respect to frequency in Fig. 14, illustrates that K j varies by less than 1% for a widerange
o f source inductance (0 to 800 pH). On the other hand, K2 approaches K , as the value
of
tunes out the FET’s input capacitive reactance over frequency.
74
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3.5
CM
*
•12
• 15
•18
2.5
-*V *12
" 0 “ 15
-0 -1 8
1.5
100
200
300
400
500
600
700
800
Lsweep (pH)
Figure 14
Simulated effect of a variable inductor,
(pH) on the factors K t and
K2 when placed at the source terminal o f FET C l. Lines with symbols
representing ^ find a minimum value, equal to K t, where the reactive
component o fZ opt is tuned out by the inductive reactance o fL ^ ^ .
3.6 CHAPTER SUMMARY
This chapter described the results o f a theory for the analysis o f linear noisy twoport networks. After reviewing noisy two-port equivalent circuits and a definition o f
noise figure, the noise correlation matrix technique is discussed. The noise correlation
matrix technique enhances the analysis for later use in the modeling o f FET noise. Since
the equivalent noise generators are treated as non-random sinusoids, their correlation
must be related a priori. This is ensured by the limiting relations derived for the noise
parameters and the correlation of the equivalent noise generators.
75
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CHAPTER 4 A TEMPERATURE DEPENDENT MODEL FOR THE FET
INTRODUCTION
4 .0
This chapter presents techniques for developing a bias and temperature dependent
model as proposed in Chapter 1. Here, a set o f FET models extracted from discrete
biases and temperatures are used to build a variable bias and temperature dependent
model. This variable or multi-state model is built by mathematically transforming the
discrete data sets into a compressed database o f model values. Further steps are taken
in Chapter 5 to develop the discrete models from data in a manner that still retains
correlations to their real physical causes. In addition to describing a temperature
dependent noise model, this section studies physical correlations to support the form o f
the model. The first part o f this chapter reviews experimentally observed variations o f
physical parameters and the last section o f this chapter presents a figure o f merit for
comparing the temperature dependent noise performance o f FET’s.
Previous research into the temperature dependent performance and characteristics
o f GaAs-based and InP-based MESFETs and PHEMTs has been approached both
through theoretical development o f two-dimensional Possion’s equation solving
simulators and by experimental investigations using equivalent circuits[7]. While both
approaches are valuable to the investigation o f temperature dependent performance, this
work chooses to concentrate on the circuit model representation.
76
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The following
experimentally based bias and temperature dependent model for the FET is based upon:
( I) observations on the temperature dependence o f model elements and ( 2 ) practical
considerations for CAD model development. The resulting model values are based upon
experimental data. Aside from simulation purposes, the overall FET model variation due
to ambient temperature changes may be compared between differing technologies, such
as MESFET and HEMT.
4.1
M ATERIAL FACTORS: EMPIRICAL MODEL SURVEY
Traditionally, modeling o f FETs with an equivalent circuit model yields a static
characterization with respect to the bias voltages and temperature. O f course these
variables are dynamic, and one approach establishes a dynamic model which fits an
* empirical expression to a range o f experimental data. Although commercially available
software exists that employs default thermal coefficients for FET circuit parameters,
several assumptions are made about: ( 1 ) the applied bias conditions, (2 ) the
semiconductor technology, and (3 ) the functional dependence of the parameters on
temperature [6 ].
A good starting point for discussing the expected thermal variation is to consider,
as functions o f temperature, some principal parameters for GaAs and related compounds
used in microwave FET channels. The dominant characteristics to consider are the lowfield mobility, p0, and the energy band gap, Eg. A rise in the baseplate temperature
increases the channel temperature and afreets these properties and the FET characteristics
dependent upon them. Dominant effects seen in MESFETs or HEMTs are summarized
as follows:
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i
II
•
The low-field electron mobility decreases with increasing temperature in the 298 K
to 358 K range. This is primarily due to increased lattice scattering, and this results
in increased resistivities for the ohmic layers giving larger parasitic resistances. This
situation is somewhat lessened in a doped semiconductor. However, the amount o f
variation in the resistances is larger in heterostructures that employ undoped layers.
•
The energy band gap decreases with increasing temperature and this helps to reduce
the electron saturation velocity, as more carriers can occupy higher conduction level
subbands. Secondly, a smaller band gap reduces the Shottky barrier height and
therefore more negative pinch-off voltages result. As temperature is reduced,
trapping states that are normally ionized at room temperature may also factor into
shifting the threshold (or pinch-ofl) voltage, but in this case the shift is a discrete step
as opposed to the continual slope associated with the decreasing barrier height.
The result o f thermally induced variations on these properties ultimately effects the FET
model characteristics. Reduced vMt gives smaller transconductance and larger output
resistance. The decrease in Eg reduces the Shottky contact potential, which increases
intrinsic capacitances with temperature. Finally, due to the increased lattice scattering
and variation o f vMt, the saturated FET noise current density increases in the FET
channel.
In choosing a model for temperature variations, a review o f typical functional
dependencies for related physical factors was performed. Here, a complete study o f
thermally induced changes upon GaAs was performed by Blakemore [78], who found the
78
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low-field mobility to behave as,
»<r> - M.f ?f\
where fig is the room temperature value,
<«)
denotes the reference temperature and a is
the thermal coefficient (a=2.3 for undoped GaAs). The gate barrier height, y » and the
relative permittivity, ep are also functions of temperature, and can be described by the
linear relations [79], [77],
W
- 'W
[ i ♦ * ( r - »v>]
e W
= *,(^ [1
m
(64)
.
(65)
and,
*v(r-r^)]
Results from several studies show k to have a value between 1.6 and 0.25 mV/K [5], [ 6 ],
[7] and v to be 0.9 to 1.2 * 10~7K [5], [ 8 ]. The thermal coefficient for V bi varies widely
depending upon the materials and processing techniques used to fabricate the Shottky
barrier. The thermal dependence o f Hqs. (64) and (65) affect performance by altering
such quantities as the depletion depth in MESFETs or the 2-DEG carrier concentration
in HEMTs. Other physical factors include the energy bandgap, Eg, and the donor doping
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density, Nc or Nv,
Eg( T ) = 1.54 -
5.4 x I0 4 r
T + 204
2
(eF)
(66)
1.5
(67)
Since the shallow donors in GaAs are all ionized independent o f temperature, the effect
o f Eq. (67) is not as significant compared to Eq. (63). The threshold voltage in
MESFETs is, however, affected by the broadening o f the electron concentration profile
w ith respect to temperature [8 ]. Finally, to provide a complete review o f analytical
expressions for physical quantities with respect to temperature, the temperature
dependence o f the inter-valley scattering energy AEr_L in GaAs is related by the
expression [80],
O //ip
«r =nL
m,L
\
O
312
e L E v.L
(68)
where n° and n° denote the intrinsic carrier concentration in the T or L valley and mr
and mL are the related effective mass at each level (T or L).
4.2
EXPERIMENTALLY BASED TEMPERATURE MODELS
A standard notation for the thermal coefficients o f the desired circuit models is
introduced here. Whereas empirical physical models are represented by more than one
functional dependence as given by Eqs. (63) and (64), equivalent circuit models based
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on linear functions such as Eq. (64) have been demonstrated for small signal models [6 ],
This is advantageous for several reasons. For example, the exponential dependence o f
Eq. (63) can be used to model a wide range o f linear to nonlinear responses, however the
relation in Eq. (63) is best fit about a median data point. This is a drawback to using the
exponential because it becomes difficult to know what the reference temperature value
is, as denoted by Eqs. (64) and (65). Also, a common fitting temperature would help in
correlating effects between different elements o f the FET model.
To
avoid the
difficulties involved with the exponential a coefficients, a model based upon a series
expansion o f a about Tref is useful. The first two terms o f a binomial expansion o f a
about Tref yields the linear relation,
1 + p - ( T - T ^)
Lref
(69)
where P(T) is the value o f the subject model parameter at the temperature o f interest T.
For simplicity the term a /T ^ is redefined as an alternative thermal coefficient, ft, whose
units are (10'3/°C ) in this work.
The straight line fitting o f the model parameters and noise coefficients by Eq. (69)
is the baseline model for this work. Results validating this model appear in the literature
[6 ], [8 ], Further verification o f Eq. (69) results from considering the range o f o values
reported for the low-field mobility and the electron saturated velocity, v ^ . From the
example a values listed above, it is found that the small signal model parameters are fit
well by Eq. (69) over at least the 298 K to 358 K range.
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4.3 A TABLE-BASED NO ISE MODEL
An algorithm for simulating bias and temperature dependent FET small signal and
noise performance is described in the literature [81], As described by Winson [81], the
algorithm performs two-dimensional linear interpolation on a single stored data table to
quickly produce bias and temperature dependent model simulations. The table-based
model is implemented in HP/EEsoFs Series IV Libra V . 6 software as a User Defined
Element using USF developed C-programs as part o f the Libra Senior software code.
In particular, this work has extended the model developed by Winson [73] to use the
noise coefficients P, R and C or Tg and Td.
Within the table-based model, the thermal coefficients are developed from the first
derivative o f the model elements with respect to temperature, T, as a function o f both
bias potentials V ds and V gs. Therefore, instead o f Eq. (69), the table model uses,
p iy ^ T )
where P(Vgs,
=
pcv^
t j
* -p ( i r
y .V )
BT
(70)
T) is the value o f the parameter o f interest at a particular bias and
temperature. In Winson’s method [81], the three dimensional problem is solved by
searching for the appropriate bias conditions in two dimensions and using the equation
o f a line to fit the temperature dependence in the third dimension. The slope and
intercept terms o f (70) are programmed in discrete form as,
(71)
where the bias dependent lines fitting the element temperature trends are represented by their
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i
slopes, ittp and intercepts, bf. Coefficients n^ and b-t are tabulated over a rectangular grid o f
desired bias potentials Va, and Vgj. Non-regular grids containing quadrilaterals can also be
accommodated, since the linear search and interpolation algorithm in the bias potential plane
is based upon a search of four comer points dividing two triangles. In this work, all bias and
temperature dependent model parameters are determined in this way.
The table-based model has several distinct advantages for bias and temperature
dependent noise modeling at small input RF signal levels. First o f all, the table reduces
computer memory requirements. In comparison to a set o f measured S-parameter and
noise parameter data for a
1 0 *1 0
bias grid at 5 temperatures, the table based model
occupies less than 1% o f memory storage. The same table-model achieves a 40%
reduction in data storage versus a set of discrete noise models. Furthermore, the method
is simply more efficient because it avoids the tedious manual manipulation o f measured
data models.
The bias and temperature dependent table model also enables several possible
circuit design and analysis techniques. For example, one may dynamically optimize
circuit performance because the quiescent bias variables are part o f the computer
algorithm. This could lead to variable gain stage simulations which optimize system level
performance in a more precise manner than a conventional technique where only discrete
data sets are available. In critical space applications, where IS year on orbit lifetimes are
required, computer control o f the bias potentials might allow remote calibration and or
tuning of a FET’s performance due to system aging or environmental stress.
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4.4
FIGURES OF M ERIT: RELATIONS TO NOISE M ODELING
To compare the noise performance o f FETs it is necessary to understand how the
noise properties o f the FET model are coupled to the small signal model characteristics.
The simple empirical model o f Fukui helps to introduce how the small signal and noise
performance are tied together. The Fukui equation for F„,,n can be written as [13],
=
1
+ Kf j ^ 8 m ( Rg + Rs)
(72)
where Kf is the non-dimensional Fukui noise coefficient associated with the fitting o f F**,
gm is the transconductance, Rg and Rr are the extrinsic resistances at the FET gate and
source terminals andf t is the unity current gain frequency. The effect o f a temperature
change can be forecast by noting that the slope o f Fmin versus frequency is proportional
to K f / ft. Therefore, F,^ increases with increasing temperature as £ decreases.
Since the publication o f Fukui’s equation for noise figure, the concept o f low
noise FETs with high ^ and low K f has been widely referenced. It is recognized that in
addition to possessing a high ft the parasitic resistance in the gate and source must be
minimized so as not to degrade even the best o f FET channels. The historical record
shows a push towards increasing ft and reducing R, and R , by following the paths of
geometric scaling and materials science. Material studies seek optimal carrier transport
characteristics such as high electron drift velocity to increase
4
and a high low-field
mobility to reduce parasitic noise in R,. Further low noise improvement results from
optimizing f* R, and R, due to geometric scaling. These include reduced gate lengths due
to finer electron beam (E-beam) line widths used for gate metal patterning and multilayer
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epitaxial lift-o ff techniques acheiving optimal gate metal cross-sectional ratios. Along
with these developments, the offset layout o f the source-to-gate spacing with respect to
the drain-to-gate spacing helps to reduce R,.
The preceeding discussion appears to imply that comparison o f FET technologies
could be based upon Rg, R„ and £ at least for FETs built with a given semiconductor
channel type. In this approach, K f remains to a large extent, a characterizing factor rather
than a useful quantity for FET design. The inadequacy o f K f by itself becomes more
apparent as new FET channel technologies are developed. For example, assuming
equivalent R* Rg and £ w ill a GaAs MESFET channel based on three-dimensional (3-D )
transport yield a FET with better noise performance than a similar GaAs based
heterostructure channel employing electron transport that is 2 -dimensional [82] or 1 dimensional (1-D ) [83] and [84].
The relation between physical factors and the observed trends is well known for
parameters such as the transconductance (dominated by v^, behavior), but for the noise
processes several competing factors make such associations more difficult. An attempt
to normalize such factors as the gate length, L gate, and the frequency, ft, was performed
by Hughes [85], However, that data was limited to the sampling o f points given by
various published sources from which parameters such as ft were not available. For this
work, the following reviews a figure of merit proposed by Pospieszalski [11] and also
Tutt [142]. This figure of merit, referred to in this work as the noise-to-gain ratio (NG R)
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is given abstractly by the ratio o f the mean drain noise current density to £ [137],
NGR = I -s ft
where
(73)
denotes the intrinsic drain noise current. This is similar to the figure o f merit
proposed by Pospieszalski which applies the noise temperature model coefficients to give
a figure o f merit, identified as f (V ^ I^ [ 1 1 ],
/(* ■ * ,/* ) = £ J k £ * _
(74)
Jt
where Td is defined in the model schematic o f Fig. 12. Note that no scaling o f NGR
values is required to compare FETs o f differing gate widths, because dividing by ft in the
NGR equation accounts for differing width FETs. This is shown explicitly in Eq. (75)
where ft is given by,
/l =
2 * (£ ■ * < :„)
m
where Cgs is the gate-to-source capacitance, Cgd is the gate-to-drain parasitic capacitance
due to field fringing effects, gmuis the unit width transconductance,
is the unit gate
width and n is the number o f unit fingers. This work w ill use the NGR to compare the
noise performance o f differing FETs in Chapter 7.
As shown above, the N G R is
advantageous for such a comparison because 1 ) it includes both small signal and noise
behavior and 2) it is normalized by the total FET width.
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4.5
CHAPTER SUMMARY
By characterizing a FET at various biases and temperatures, a technique is
proposed to develop a bias and temperature dependent FET noise modeL This model is
intended for use at microwave and millimeter-wave frequencies. The proposed model is
efficient in terms o f simulation speed and memory resources with respect to an equivalent
measurement database.
Based upon previous experimental work on small signal
modeling and examples o f trends in physical parameters, such as Eg and |tQ, this work
proposes a linearly dependent temperature model for the FET noise model elements.
Finally, a figure o f merit is described to provide unbiased comparisons o f FET noise
performance with respect to temperature.
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CHAPTER 5. ANALYSIS AND MODEL EXTRACTION METHODS
FET NOISE M ODELING TECHNIQUES
5 .0
The circuit models introduced in the previous chapters are the result of
both experimental and theoretical attempts to represent the electrical performance o f a
FET. The equivalent circuit topologies used reflect physical qualities such as, voltage
gain, capacitive input and resistive output characteristics o f a FET. Popular equivalent
circuit modeling techniques exploit these characteristics, such that, depending upon the
FET bias conditions one can simplify the model to a select few elements.
This chapter introduces and develops techniques to calculate the values o f the
equivalent circuit elements. This is done by comparing experimental data with an
analytical expression o f the network parameters and then calculating element values
based upon a measured version o f similar parameters. If the FET model elements are
calculated at several bias and temperature points, then trends in the variation o f elements
may also be observed. This data is then used as input to the linear temperature models
o f Chapter 2 to calculate; thermal coefficients for each resistor, capacitor, inductor,
transconductance and noise generator. As a result, this chapter establishes a consistent
methodology for reverse engineering or “extracting” models o f a FET.
The extraction procedure to be described is based upon the small signal/noise
model shown in Fig. 15. The model elements are divided between extrinsic elements that
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f
I
t
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comprise parasitic effects due to the contact terminals (and/or packaging) and intrinsic
elements that model the FET channel. The extrinsic and intrinsic elements are denoted
by:
•
•
Extrinsic (Bias Independent): L„ Lp L * R„ R *
Intrinsic (Bias Dependent): Rj,
C^, C^
g ^ Tau or (t), Cgjj Cjg, C p j.
The model also includes noise sources belonging to each o f these two categories as
follows:
•
Extrinsic (Thermal Noise): e„ eg, ed due to R^, Rg, and R j.
•
Intrinsic (Bias Dependent): gate noise voltage
and drain noise current i^j.
Drain
Gate
Rd
Cpd
INTRINSIC
EXTRINSIC
Source
Figure 15
Small signal model of the FET including intrinsic (within the dotted lines) and
extrinsic elements.
Figure 16 summarizes these procedures for each small signal bias and temperature
condition.
(
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FET Small Signal Model and Noise Model
Measurement and Extraction Flow Diagram
Measure S-Parameters
Measure Noise Parameters
LRM CalibraUon a tT ^ T ^
1. Pinched FET Bias
2. Cold FET/HEMT Bias
3. Hot FET Bias
LRM Calibration at T=TcfHJCk
Calibrate Noise System at T=TC
Measure Hot FET Bias
put
Extract Intrinsic Noise
Parameters
Using gate width scaling,'
C =Cl1(W =0) and
Remove lossless elements
a' o* *v pa* pd' gd
Remove lossy elements from
correlation matrix Rg, R#, Rd
or
Assume C pg
^ = C,i
put
Extract Parasitic Resistors:
Extract Noise Model
Coefficients vs. Frequency*
L, Rs, Rdfrom Cold FET/HEM
Extract Parasitic Inductors:
Solve for P, R, C
Solve for Tg and Td
•(Average data cleared by
K, and K2 criteria)
Lg. Ld. Kfrom Cold FET
Extract Intrinsic Elements:
Input
Average Data vs. Frequency*
9m* ^d» ’V - Cds*.
C *Tau , R;**
'(omit data below 0.5 GHz)
'•(omit data if dipersive for F<10GHz)
Figure 16
Flow chart summarizing procedure for small signal model extraction (left)
and noise model extraction (right). Frequency considerations are indicated
for typical FETs used in this work.
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In this chapter, four key issues underlying the development o f a FET modeling
procedure are used repeatedly to first find the extrinsic elements, then the intrinsic ones
and finally the noise generator coefficients. The first step is to develop analytical
expressions for calculating the element values from the data. Next comes the task o f
applying the extraction which depends upon the bias conditions, the FET type and its
geometry. Success here implies several things. First, the element values should have a
frequency dependence consistent with the model being used. Secondly, when put
together as a model, these element values should fit the data closely. Finally, the element
values should reflect physical reality as much as possible. In the sections that follow,
FET model extraction procedures are presented for both parasitic and intrinsic model
elements. In both cases, new techniques and comparisons of previous methods are
presented for wafer probed FETs having various material and geometric designs.
5. 1
PARASITIC FET ELEMENT EXTRACTION
It is advantageous to measure a FET under several bias conditions for the
extraction o f the parasitic capacitance, inductance and resistance. A passive mode o f
operation generally assumed for this purpose is referred to as “cold F E T ’, because the
drain-to-source voltage is either set to zero or left floating, thereby deactivating the
current generator in the FET model. Three commonly exploited conditions under cold
biasing are: 1) pinched FET, where
FET, where
is reversed-biased beyond pinch-off, V ^ ; 2) cold
is forward biased at high gate current and; 3) unbiased, where V gs is also
set to zero potential. Figure 17 charts the bias conditions for the MESFETs and
HEMT/PHEMTs studied in this work. The modeling techniques
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FET Bias Conditions for
Small Signal Modeling
Pinched FET Bias:
V^O
lv9.l > lVpm*H*r
Y-Parameters dominated by
capacitive reactance.
MESFET-
Cold FET:
V_=0
Resistors 3 Values of current
I * -3 0 , 60 90 mA/mm
Igs* - 90 mA/mm
Inductors
----------------- I,
* Z-Parameters dominated by
resistance and inductive
reactance.
HEMT-
Cold HEMT:
v* s°
0 <V g .< V . U
~ 0
Resistors One
bias*
Inductors Igs** - 90 mA/mm
* RetZ,,] dominated by
capacitive reactance at lower
frequencies, R e ^ ], R e [^ ]
dominated by resistance.
** lm[Z]-Parameters dominated
by Inductive reactance.
Hot FET Bias:
V ,. > 0 ,1, as desired'
* Y-parameters dominated by
conductances g,, g^ and
capacitive reactances due to
Ca»’ C«h and Cfld*
Figure 17
Flow chart o f small signal S-parameter bias conditions for FET modeling
performed in this work. Each condition relates a simplified FET topology
from which equivalent circuit elements are extracted through direct
calculations.
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synthesize complete FET models using these bias conditions to successively remove
circuit elements constituting poles in the admittance parameters and zeroes in the
impedance parameters. This section describes the simplified topologies that the FET
model assumes when V * is set to zero and a particular Vg, bias is chosen
[86],[87],[88],[89]. Most “cold” FET modeling techniques calculate circuit element
values from closed form solutions, which are easily programmed and numerically
efficient.
5.1.1 Parasitic Capacitance Extraction
The procedure used in this work extracts the parasitic capacitances Cpg and
first. When the FET gate is reverse-biased into pinch-off a space charge layer forms
under the gate which can be modeled as a capacitance. For gate biases sufficiently large
to deplete the free charge carriers under the gate, the model simplifies to that o f Fig. 18.
In this “cold” model of the FET, R js is very large and the parasitic resistances are small
Gate
Drain
Source
Figure 18 Simplified small signal equivalent circuit of the FET bias under “pinched” nwvfcling
conditions, Vds=0 , V ^ V ^ -2 (V).
93
of the copyright owner. Further reproduction prohibited without permission.
compared to the capacitive reactances [90], The imaginary components o f the "pinched
FET" admittance matrix are:
Im[Yxi] = >0,( C« + f Cft)
W
/m [ri2]= -]<*-—
Im[Yn \
(77)
+ | c 6J
(78)
where Im denotes the imaginary component. Physically, the parasitic capacitors involve four
properties o f the FET [91]. These include the channel capacitance that is dependent on gate
width and length, and on the bias conditions. Also included is the fringing capacitance in the
semiconductor and the fringing capacitance above the semiconductor surface that also
depends on the passivation material. Finally, there is also constant capacitance due to the RF
pad metalization and the metalization not including the FET gate metalization. These
properties are sometimes lumped into the simple pi-model o f Fig. 19. The values o f Cre and
Gate
C.
>fi2
%
—
Drain
p
-J
^
;n
-
<
22
Source
Figure 19
Simplified pinched-FET model for use with gate width scaling measurements.
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for this model are determined from geometric considerations. To demonstrate this, the
capacitances o f Fig. 19 are derived from the imaginary parts of the associatedy-parameters
[91], which give,
c n ~ Cpg + w (pgi + cgj)
(79)
(80)
(81)
In Eqs. (79-81), w is the total gate width, CgI and Cdl are related to channel capacitance
and Cpf, Cg2 and Cd2 are related to fringing capacitance. In comparison to the other
works, the pinched FET models o f Dambrine, and more recently White et. al. [92], do
not include the width scaling o f Eqs. (79-81). Mathematically, these relations are
consistent with the model o f White et. al. [81] which also uses a symmetric model for the
FET reversed biased beyond pinch-off.
The width dependent model was applied to FETs studied in this work. Figure 20
illustrates the “inter-digitated” layout that is typical o f the FETs measured here. To
demonstrate the parasitic pad capacitance modeling technique, PHEMTs (FET A2) of
varying gate widths and equal numbers o f gate fingers were measured. Figure 21 shows
the extracted values of Cn and C22 for Eqs. (79) and (81). The data represents 15 FETs
with gate widths varying from 300 to 800 pm. The values o f Cpg and
are found by
extrapolating Cu and C2 2 to zero width in Eqs. (79) and (81). The average extracted
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Figure 2 0
Illustration o f a typical metalization layout for FETs studied in this work.
Scale o f gate length, Le.t> is exaggerated for illustration.
180
160
140
^ 1
2
0
felOO
CM
CM
O
80
60
40
20
0
100
90
80
70
_ g 60
50
o 40
30
20
10
0
-
C22-Mean
C11-Mean
'Linear Trend
'Linear Trend
-
Cpg= Cl1(Wg=0) = 12.3
Cpd = C22(Wg=0) = 18.1
-
-
-
J
------- 1-------u
1
J____ u
100 200 300 400 500 600 700 800 900
Gate Width (^m)
Figure 2 1
Pinched FET capacitors Cu and
(£F) versus FET gate width (pm).
Stem and wing lines indicate minimum and maximum values for 5 samples
at each gate width.
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values from Fig. 21 are
= 16 £F and C pg = 12 fF. These results also show that the
gate parasitic capacitance Cu depends less upon gate width than the drain parasitic C ^Therefore, an approximate method to extract Cpg and C ^, calculates C pg from Eqs. (79)
and (81) and assumes
= C re - pad capacitance. Measurement o f these quantities for
the range o f gate widths investigated here are typically well behaved. However, several
factors describe why the geometrically identical RF-pads measure different values o f
capacitance. First, the experiment finds that these quantities are also dependent upon
probe placement and may vary by as much as 5 fF due to uncertainty in the probe contact
point. Secondly, the larger drain pad capacitance values may result from the increased
metalization required for current handling capabilities o f the drain manifold.
S. 1.2 Parasitic Inductance and Resistance Extraction
For forward gate to source voltages the cold FET equivalent circuit model
assumes a simplified tee-network[l02], this approximation is illustrated in Fig. 22.
Gate
R
9
Drain
Source
Figure 22 Equivalent circuit model of the forward biased “Cold FET’ used for
extraction of parasitic inductance, resistance, and the distributed gate diode.
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The impedance matrix for the network o f Fig. 22 is given by,
(82)
zu =
'12
- Z2l - Rs+ctRch
701
Ls
(83)
(84)
Z 22 = R d + R s + 2 a R ck + J< *C L d + L x )
where ag ( < Vb ) and a ( < Vz ) denote fitting factors that decrease with increasing gate
current, R* is the gate metalization resistance, R, and R j are parasitic resistances at the source
and drain terminals, R ^ represents the resistance o f the channel and R jy represents the
forward biased Schottky barrier diode resistance. Since there are five unknown resistors, the
real parts ofthe impedance parameters cannot be used alone to solve for the resistor values.
In contrast, the imaginary parts o f the z-parameters completely describe the three inductances
L„ Lgand Ld. The following discussion describes the inductance extraction first. Extracting
the parasitic resistors requires some specialized techniques depending upon the channel type
(MESFET or HEMT/PHEMT) and the bias conditions used. The most notable change is in
the cold-FET biases required to characterize the diode resistance,
and the channel
resistance, R ^ for different FET types. Because such decisions must be made early, this
work separates discussion o f MESFET and HEMT/PHEMT resistor extraction into two
distinct sections. Both sections reference comparisons to the appropriate literature, and in
the case o f the HEMT/PHEMT a clear advancement is made over current techniques.
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5.1.2.1 Inductance Extraction
The reactive half o f the z-parameters in Eqs. (82-84) allow for direct calculation
o f the parasitic inductors from data. The parasitic inductors Ls, Lg and Ld in Fig. 22
result from the metallization at the gate and drain pads and from the source grounds (via
holes) and/or metallization. These inductors are determined at a cold FET bias (V d s = 0
and 1^ -9 0 mA/mm2 [102]). This bias current must only be large enough to assure that
the diode is conducting at a level where the gate-to-source capacitance is negligible
compared to the inductive reactance. While this is a straightforward solution, some
concern is associated with the gate metal quality due to excessively large gate currents.
Although the FETs tested under such conditions are not likely to be used in a circuit, it
is important, for consistent development of the FET model, that the gate is not degraded
before similar data is taken at other temperatures and or bias conditions. To avoid this
situation, an alternative is described by Tayrani et. al. to calculate the inductor values
using z-parameter data from a pinched FET and an unbiased FET [89]. Despite this
alternative, l9 o f less than 40 mA/mm2 is used to extract all parasitic inductances in this
work, and excessively large currents were found to be unnecessary for the subject FETs.
5.1.2.2 Parasitic Resistance Extraction for MESFET’s
This discussion applies the technique o f Dambrine et. al. [102] to extract the
parasitic resistors from S>parameter data o f the MESFET A l. In this technique one
measures two-port S-parameters at several forward-biased gate currents. In Eq. (84),
the real component o f Z u is equal to R,,y plus the sum o f the resistances Rg, R, and Rch
which will be referred to as Rs,,m. The diode resistance extracted by Dambrine et. al. is
99
i
i
|
It
J
._
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given by,
nkB T
R* * ~ z r
<85)
where n denotes the diode ideality factor, T is the ambient temperature, q denotes the
electron charge and Ig, denotes the forward-biased gate diode current. To solve for Rsam
the Re[ZtI] data is plotted versus l/I^and then the y-axis intercept (zero R ^ ) o f a linear
regression through this data locates the value o f R ^ . Then the method o f Anholt [93]
is used to solve for the ideality factor and the channel current factors a and ag. This
requires a self-consistent solution o f VgJ, Igs and the real parts o f the z-parameters by
fitting the ideality constant and the alpha factors, where a and ag are themselves
functions o f a normalized current, / [94], The normalized current variable / is given by
Igs R ^ / n kB T [82]. For the MESFET A l, Table 5 lists the results of several forwardbiased gate measurements.
Table 5
MESFET A l cold FET data for extracting the parasitic resistors
(Ohms)
Re[Zu]
(Ohms)
Re[Z12]
(Ohms)
R e^
(Ohms)
2.678
1.278
10.182
3.042
7.112
1.507
2.712
1.370
5.730
2.895
6.852
1.650
2.883
2.726
1.266
4.703
2.806
6 .6 8 8
1.664
3.380
2.7301
1.243
4.535
2.784
6.643
Ygs
(V )
R,
(Ohms)
i
0.7
1.664
0 .8
Rd
(Ohms)
0.451
1.622
0.9
0.95
100
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Table 6 lists the resulting values for Rg, Rj, R j and R ^. Here, the low relative standard
deviation, o, for Rg, R , and R j averaged versus / indicates that the diode model fits the
bias dependent data well.
Table 6
Parameter
Results o f ideality factor fit and parasitic resistor
extraction for MESFET A l and the mean values for
seven tested samples o f the same FET.
Value for A l
(Ohms)
%a
Mean for n=7
Ohms, (% o )
Rs
1.650
1 .0
1.610, (1.9)
Rg
1.289
0 .8
1.035, (5.3)
Rd
2.712
3.9
2.625, (1.3)
Rch
2.862
—
2.769, (9.9)
n (unitless)
1.143
—
1.063, (1.5)
The last column of Table 6 indicates the statistical variation o f results for seven samples
o f MESFET A l. These results indicate good uniformity o f the parasitics and consistency
in the measurement and modeling procedures. The channel resistance shows the largest
variation o f the seven samples tested, and this variation is explained by a larger variation
of FET channel properties in comparison to the gate metalization or source/drain ohmic
contacts that makeup Rg, R , and R j.
It is important to note that in similar data for the PHEMT A2 the real part o f Z n ,
and more specifically R ^, cannot be characterized in the same way as for M ESFET A l.
Experimentally, this work observes that for HEMTs and PHEMTs, R jy increases as V gs
is forward-biased past the point where the diode turns on, while in MESFETs, R ^ tends
toward zero as Igs increases. Anholt [ 8 8 ], also observes this dependence and refers to
101
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the experimental observation o f a non-ideal (n »l) H EM T diode characteristic. The next
section addresses each o f these observations and presents a new parasitic resistor
extraction method fo r HEMTs/PHEMTs.
5.1.2.3 Parasitic Resistance Extraction for HEMTs and PHEMTs
The cold FET extraction technique is based upon a FET model for a forward-biased
gate-to-source Shottky barrier diode. While success o f this technique centers on the ability
to simplify the model o f Fig. 22 by characterizing
versus Igg, this bias dependence does
not apply to R ^ in heterostructure FETs. Figure 23 shows the results o f measuring the
Re[Zn] versus forward gate current, with
floating, for both HEM T C l and PHEMT A2
Wg-300, PHEMT
Igs, 600 PHEMT
Wg-600
—»--W g*150, InP HEMT
Wg*800
-♦ --Ig s , InP HEMT
50
40
CO
E
sz
O
30®
20 >
O
tr
0.2
0.4
0.6
0.8
1.2
1.4
Vgs (V)
Figure 23
Comparison (left-axis) of cold FET Re[Zu] (Ohms) versus V 9 (V)
for FET A2 at various gate widths (pm), and HEMT C l. Also
compared (right-axis) are forward gate currents for A2 and C l,
Ip (mA) versus V9 (V).
102
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(at various gate widths). The bias dependence shown in Fig. 23 for PHEMT A2 is described
by three distinct regions as follows:
(1)
For
< +0.5 V, the Shottky barrier height suppresses current flow and the real
impedance is constant versus forward gate bias voltage.
(2)
For +0.5 V <
< 1.1 V, the gate voltage is approximately equal to the Shottky
barrier, this region is dominated by the resonance o f the diode capacitance and the
parasitic inductance in the gate and source. No useful information can be
extracted here for R ^, since Re[Zn] is a function o f Rjy, C^, Lg and Ls.
(3)
ForVgs> 1.1 V the gate voltage is larger than the barrier height and the diode begins
conducting. Except for a small range o f voltage after the diode turns on, the real
impedance increases with increasing forward gate bias.
The effect in Region (3) is due to the additional barrier at the heterostructure interface
that suppresses current due to bending o f the quasi-Fermi level for a large forward bias at the
Shottky barrier [95]. Further evidence o f this is seen in work describing a simplified SPICE
model o f an AlGaAs/GaAs HEMT gate diode I-V relation based upon the effects o f both the
metal/semiconductor barrier and the supply layer/channel layer barrier [96]. Therefore, the
experimental observations o f forward biased I-V characteristics in this work are clearly
described by the theory o f quasi-Fermi level bending in heterostructure FETs.
Similar behavior is seen in the HEMT C l, where the Shottky diode turn on
voltage, Vt, is about 0.4 V. These results suggest that HEMTs and PHEMTs require an
alternative cold FET biasing scheme, and the following solution is one novel contribution
of this work.
103
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The gate diode should not be strongly forward biased when extracting
to
versus Vmdue to current suppression by heterostructure barrier
avoid the increase of
The following technique takes advantage o f the bias region ( I) where the gate
capacitance dominates the input impedance in the lower microwave frequency range. For
example, using PHEMT A2 experiments verify that below V ^ + 0 . 6 V R ^ is large (small
Igs), and the gate capacitance, C^, shunts R*y such that the following applies,
nkBT
rg > K W
**-
R■<fy
1 + jwRdyCgs
I
yuC
(86)
~
0
.
f/gs< frty and
large.
gr
where Vt denotes the forward turn-on voltage o f the gate diode. Substituting this
30
Vgs = +0.5 V, Cold HEMT
'tn
E
JC
O
25
Re[Z11]
Re[212]
Re[Z22]
2 0
8
§
15
E
T5
10
■a
m
w
Q.
01
IT
5
0
20
30
40
50
60
70
Frequency (GHz)
Figure 24
Cold HEMT extracted real impedances Re[Zu], Re[Z12] andRefZjJ (Ohms) versus
Frequency (GHz) for PHEMT A2 (Wg= 300 pm). Re[Zu] illustrates the predicted
1 / g>2 dependence due to the gate capacitance. A constant (o<2%) value is extracted
above 10 GHz.
104
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condition for R^ in Eq. (85) gives a real component o f Z lt that decreases as the square
o f frequency. A t sufficiently higher frequencies the resulting R e[Zn] levels out to a
constant value as
becomes negligible . This is demonstrated clearly in Fig. 24, for
PHEM T A2 (Wg = 300 pm) biased at Vgs = +0.5 V, as determined from Fig. 23.
In Fig. 24, the frequency dependence given by Eq. ( 8 6 ) for Re[Zu ] is illustrated
over the 1GHz to 67 GHz range. To model Rg and R , the Re[Zu ] above 10 GHz is
substituted for the real parts o f Eq.(82), providing R ^ can be defined or assumed
negligible. This technique is denoted in the rest o f the text as the Cold-HEM T method.
Resistors R j and R, are not complicated by R jy, and their Cold-HEMT bias point was
determined experimentally to be the same gate bias as for Rg. However, before the
values o f Rg, R j and R, can be extracted, the following discussion addresses the
definition o f R ^ further.
5.1 .2.4 Assumptions and Comparison to Other Methods
The channel resistance, R^, represents a fifth unknown in the parasitic resistance
extraction. However, R ^ in heterostructures is not currently solved for as it is in the
cold-FET method used on MESFETs. Pending the development o f such a solution, this
work performs two investigations which complete the Cold-HEMT extraction described
above.
First, an approximate technique based on measured DC I-V data was
adopted[8 8 ]. Second, an approximate analytic formula is used to calculate Rch. Third,
results for PHEMT A2 are compared to another S-parameter based “Cold FE T’
technique.
The first measurement involves an approximation for R^ based on a simultaneous
105
I
ri
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solution o f Poisson’s equation and the wave equation for the 2D and 3D charge density
in a HEM T. This solution finds that for Ids measured at low V * (linear regime) and
V gs> V b Rch is approximately given by [8 8 ],
where Lgate denotes the gate length in units o f microns and
is in amps. Equation (89)
neglects the output conductance, thermal effects and voltage drop across the source
resistance. Measured D C -IV data for the PHEM T A2 gives Rch = 0.5 Ohms (±0.2
Ohms) from Eq.(87).
A second means o f calculating
uses an analytical formulation.
For
comparison, a similar MESFET expression is also introduced with experimental results.
The value o f Rch in a FET is proportional to the doped active region beneath the gate.
This is expressed for MESFETs approximately by [97],
(88)
q\iQNdaW g
where Nd is the doping density o f the channel and a is the channel height. For the HEM T
or PHEMT, Rch is defined by a two-dimensional sheet o f charge[93],
(89)
W g Q lD
where Q2d represents the sheet charge density.
Therefore, calculating
106
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for a
heterostructure FET is relatively direct, as long as Q2D is known. Example calculation
for FET samples A2 and C l yield the results o f Table 7.
Table 7
Calculated channel resistance o f heterostructure FETs including related
geometric and material data.
™ * (pm)
Wtt(pm)
pc (cm2/V s)
Qa, (cm*2)
Rch (Ohms)
A2
0.25
300
5,000
3 * 10u
0.316
Cl
0.15
300
FET
1
1 0 ,0 0 0
to
1 1 ,0 0 0
2.5 x
1 0 12
0.135
Comparing these results with published values for a single quatum well AlGaAs /GaAs
HEM T, a value o f R * = 0.75 Ohms results for a 0.25 pm * 300 pm geometry, where
Q2D is 1.3 x
1 0 12
cm' 2 [84]. Since Q2 D is larger in both A l and C l, these results are
agreeable. Also note, the measured DC value o f R,* = 0.5 Ohms compares well with the
computed results in Table 7 using Eq. (89).
In comparing the expression for the MESFET and HEMT Rch , Eq. ( 8 8 ) and
Eq.(89), note that R^, = 2.862 Ohms for MESFET A l, as determined from the cold-FET
method.
Since the total gate width ,W g> and gate length, Lgate, o f A l and A2 are
equivalent, the only difference is in the channel itself. Under the gate, R jy accounts for
the forward-biased Shottky diode resistance. The remainder o f the doped channel
comprises Rch- In HEMTs/PHEMTs this region is defined by the 2-DEG which is
dimensionally small and highly concentrated compared to the 3-D doped region in a
MESFET. Therefore, due to the carrier confinement in heterostructure FETs the channel
resistance is much smaller than for epitaxial or ion-implanted MESFETs.
107
•4
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Whether or not
might be determined for PHEMT A2 by another S-parameter
method is the last investigation discussed here. This study compares the Cold-HEM T
technique to a published technique that uses the real components o f the ^-parameters
from an unbiased-FET and a pinched-FET[89]. However, the following discussion first
assembles several possible combinations o f unbiased, cold and pinched-FET expressions
from the real components o f the corresponding z-parameters. The unbiased technique
[81]
is a subset o f these expressions. Approximate models o f the FET under unbiased
and pinch-off conditions are given by Tayrani et. al. [89].
From the resulting z-
parameter expressions for these models the following sets o f independent equations have
been assembled here to yield possible solutions for extrinsic resistive FET elements. The
first set o f expressions allows direct extraction o f Rs from pinched-FET Z , 2 data, and
finds R& by subtraction o f the pinched-FET Z l 2 data from the unbiased FET Z 1 2 data as
given by,
R e \Z .,\
t
L 12 Jpinched
r
=R
s
t
R e \Z
xA
= R 1 + 0 . 5 / ?c«*
L 12 J unbiased
.
(90)
A second set of expressions allows extraction o f R& by subtraction o f pinched-FET Z u
data from the unbiased FET Z n from,
Re\Zn \
L * spinched
r
= R + Ro
1
8
!
R e\Zn
]
= R + Ro + 0.5 Reh
L 11 Imbiased
*
g
c*
(91)
The third set o f expressions allows extraction of Rt by subtraction o f unbiased-FET Z 1 2
108
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data from the unbiased FET Z tl data using,
- * . * °-5* (92)
Upon implementation o f these three schemes for calculating either Rch, Rg or R, one finds
the data o f Table 9 for FET A2. Starting with Eq. (90) a large value (9.9 Ohms) is found
for Rs. These results agree with Tayrani et. al.[89], who note that the measured value
o f R, is extremely dependent upon calibration and difficult to extract correctly for gate
widths greater than 100 microns.
Since this is a typically unreliable method for
calculating Rch, Eq. (91) is used by Tayrani to extract R ^. However, Table
8
shows
Re[Zn] pinched =12.16 which is greater than Re[Zn ] ^biased = 3 .8 9 , and this contradicts
the model described by Eq. (91).
Table 8
Z-Parameters for Comparing o f Parasitic Resistance Extraction o f (PHEMT
A2) extrinsic resistances.
R e[Z,J
(Ohms)
Re[Zl2]
(Ohms)
RetZ^J
(Ohms)
Unbiased, ^ = 0 .0
3.89
1 .8 6
4.51
Pinched, Vg=-3.5
12.16
9.96
19.74
Cold, V ^ + 0 .5
3.66
1.76
4.31
R*
R,
R*
1.81
1.61
2.45
Gate Bias Condition (V )
Results:
Cold-HEMT
Rch
0.32
S et#l
-12.14
-
9.96
-
Set #2
-16.54
-
-
-
2.03
-
-
Set #3
109
!
d
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t
iI
Unfortunately, PH EM T A2 develops increased gate leakage current at the pinched bias
(Vpinchcd = 2 V beyond V ^ ), and this requires yet another element to be discussed later.
Therefore, a value o f Rch for the PHEMT cannot be resolved using Eq. (90). Next,
applying the unbiased data o f Eq. (91) finds Rg = 2.03 Ohms. Similarly, the Cold-HEMT
technique finds Rg — 1.9 Ohms. These last two conditions are somewhat equivalent since
in E q.(82) ag= '/i below Vu however, some lowering in the real part o f Z u is typically
observed for the Cold-HEM T bias for both A 2 and C l, as shown in Fig. 20.
In summary, the Cold-HEMT technique is applied to extract the parasitic
resistances o f HEMTs and PHEMTs in this work as follows:
(1 )
Measure S-parameters o f the forward-biased FET at 0 V < V gs < Vt with Vds
unbiased and floating. Convert the measured S-parameters to z-parameters.
(2 )
Calculate the value o f Rch using Eq. (89) or measure Rch using the approximate
relation in Eq. (87).
(3 )
Extract R , from the real part o f Z l 2 after first subtracting Rch as in Eq. (83),
where o = l/2 . Observe the frequency dependence o f Eq. (85), extract Rg from the
real part o f Z u as in Eq. (82). Finally, extract R j from the real part o f Z 2 2 as in
Eq. (84).
5.1.3 Leakage Resistance Models
Leakage current from gate-to-source is typically represented by a shunt resistor
Rp as illustrated in Fig. 25. The gate leakage resistance, R^ (or conductance Ggs), which
represents a sixth unknown in the parasitic resistance extraction, was considered
negligible in the preceding discussion. Two observations highlight the importance o f this
110
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c
Gate
dg
Drain
^d»
^ds
e,ng
R.
%
vgme -)-
Source
Figure 25
Traditional FET small signal model with resistor Rg, added to simulate the
equivalent effect of a gate-to-source leakage current
element to the model. First,
accounts for a reduction in the magnitude o f Sn at low
frequencies. Secondly, Rg, affects S21 by reducing the transconductance by a factor o f
1/(1 + R, GgJ. Rg, also affects the noise performance o f the FET due to the equivalent
thermal noise generator that it represents. For the PHEMT A2, additional dispersions
in the low frequency magnitudes o f
Su,
and mid-band S2t are also observed.
These effects are attributed to the mis-match of lattice dimensions at the
pseudomorphic interface [98], A t the interface, threading dislocations and resulting
microcracks may occur below the parasitic and active regions of the device, and the resulting
leakage currents are proportional to the microcrack density. Microcrack effects have been
modeled by resistors in shunt with the gate and drain pad parasitic capacitance to account for
the low frequency dispersion o f the magnitudes o f Su ,
and mid-band S21 [12], In this
work we have added such additional elements to a noise equivalent circuit model that
improves both the S-parameter and noise model at low frequencies (0.5 to 6.0 GHz and 2.0
111
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c dg
Gate
Drain
Cgs q ^ tV
C__
pg
Rgg
Source
Figure 26
Noisy FET model for the PHEMT with a leakage component due to
substrate currents which flow underneath the FET channel and the drain
and gate contacts.
to 6 . 0 GHz respectively). This scheme (see Fig. 26) with resistors Rgg and
is similar to
that reported by Cappy et. al. [99], where a shot noise process was included to improve the
low frequency noise model. In addition, the shot noise was found to be correlated with an
additional drain side shot noise component. In that case the model o f Cappy et. al. [89]
appears equally applicable to microcracks, that cause leakage along the entire device width.
Further identification of the leakage mechanism in A2 comes from a low-frequency
(<100KHz) noise measurement [100], which finds the gate 1 /f noise is a surface generationrecombination type[9].
112
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!
5.1.3.1 Leakage Resistor Extraction
An extraction o f the gate leakage resistor,
(or Rgg), is conceivable from S-
parameter data o f a FET, when biased at its small signal operating point [101], From the
model in Fig. 25, the real component o f the parameter Y u is given by,
* [ * . 1 ] ■ J - * • * * ,< £
•
(93)
V
The dependence o f Rg,, on R,- and Cg, is removed when the real part o f Y u(co2) is fit to
a line, using w2 as the independent variable. The intercept o f that line is R gs. Extracted
values o f Rgs at several gate biases (-1.0 to -0.2V ) is shown in Fig. 27 for FETs A l, A2
at V ds=3V and for C l at vds-IV . This plot shows that the extracted resistance values
8000
6000
FET Type:
• MESFET A1
▲ PHEMT A2
■ HEMTC1
4000
-1.3 -1.1
-0.9 -0.7 -0.5 -0.3 -0.1
0.1
Vgs(V )
Figure 27
Extracted values o f Rgg (Ohms) versus gate voltage V ^ (V ) for several
types of300pm gate width FETs. The magnitude Rgg for FET A2 reveals
why this element is not negligible with respect to the modeling o f Sparameter and noise parameter data for that FET.
113
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II
!
are high for those FETs (A l and C l) which measure less than 10 jlA o f leakage current
under normal FET bias conditions. However, A2 exhibits a leakage current from gate-to-
source that is not negligible. Figure 27 shows the extracted Rg, values o f A2 that are a
factor o f three less than the extracted R^, in A l or C l.
S.1.3.2 Noise Analysis o f Leakage Resistors
While the noise contributed by the gate-to-source leakage current can be modeled
by an equivalent conductance having thermal noise given by the Nyquist relation, the
noise spectra o f an intrinsic FET having substantial gate leakage w ill show a dispersion
due toor R^ o f Fig. 25 or R ^ o f Fig. 26. However, the 1 /f spectra o f GaAs FETs is not
observed to any substantial magnitude (< -80 dB) beyond
10
KHz, where the noticeable
microwave frequency dispersion effect for A2 extends. To further investigate this
problem, an analysis o f the models’ noise spectral density was performed. The analysis
proceeds as follows: 1 ) derive the impedance matrix o f the parallel RC combination, 2)
determine the associated noise correlation matrix and 3) identify the spectral behavior o f
the resulting noise correlation matrix. The impedance m atrix o f the input parasitic
network is found to be,
________ gg _______
1
z
where U = 1 + w2
r
pg gg
114
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(94)
I
From the Nyquist equation the correlation matrix for the passive impedance matrix is the
dual o f Eq. (39) which gives,
Cz = 4 * a r oA /R e [Z
1
= 4kBTab f
Rgg Rgg
U U
Kgg Rgg
u
(95)
U
So, the noise spectral density is frequency dependent for this model o f the gate-to-
source leakage current. The frequency dependence is carried through to the intrinsic
FET by superposition o f the noise spectral densities. This is demonstrated by the
summation o f the noise correlation matrices o f the intrinsic FET, with the parasitic
elements modeling gate leakage. This analysis has shown that the dispersion o f the low
frequency (2 - 6 GHz) noise spectra o f the intrinsic FET is due to the parallel combination
of leakage resistance, Rgg, and the input capacitance o f the FET. Similar results due to
the interaction o f
and Cv in the model o f Fig. 26 also result. In the case o f the
PHEMT A2 having a leaky structure due to lattice mismatch effects, this can be described
by the similar combination including the pad capacitance and the leakage resistance.
115
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5.2
INTRINSIC FET MODEL ELEMENT EXTRACTION
The following section describes the application o f the extraction procedure to
calculate the remaining intrinsic elements o f the small signal model. Theory explaining
the direct extraction o f model equivalent circuit parameter values is well documented
[87],[102],[93]. A complete FET model extraction first removes the effects o f the
parasitic elements found in the previous sections o f this chapter. To remove the parasitic
elements the initial S-parameters are converted to y-parameters and the shunt capcitances
Cpg and Cpd are subtracted. The next step transforms the y-parameters to z-parameters
and the series connection o f resistances Rg, R , and R j with corresponding inductors Lp
L, and Ldare subtrated from the impedance matrix. The data is then converted back into
admittance parameters. Analytical expressions for the resulting y-parameters o f the
intrinsic FET are used to extract each element o f intrinsic the admittance matrix given by,
^12 ~ ~J*°Cdg
(96)
^
* 7 T + J<*£ * * c 4
ds
116
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Solving Eq. (95) for C * first in Y 12, and successively back substituting into
expressions for Y u, Y 2 1 and y » yields the intrinsic element values. Berroth and Bosch
[87] provide these expressions for the intrinsic elements as follows [87],
I m ( r i2)
CO
c
l m ( r tt) - 0 ) C grf
"
®
t
(
(R e (rit»
,2
(Im (F u ) ~<*Cgd? )
R =
'
(h n (r u ) - < d C ^ + (R e (F u
) ) 2
gm= ]/((Re(^i))2 + (to(r2l) + »cgd)2){ l + o>2*,2c£)
(97)
1
. _[ f -CO Cgd - Im (F 21) - coCggjg, R e (r2 l)
t = — sin 1
co
co
^
= Re ( r 22)
.
Experimentally, Eqs. (97 a-g) show little dispersion over the measurement frequency
range (2-67.5 GHz) when the extrinsic elements are extracted as described previously in
this chapter. These expressions also work well for all V ds bias points measured in the
saturated region o f the D C -IV curve for this work. Some frequency dispersion is
however, observed for t and R* which are complicated by the extraction of second order
frequency terms. However, consistent model values for r and Rj are extracted at
117
t
. ____ _ _________
_____ ___
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frequencies above approximately 12 G Hz for the 0.25 pm *300 pm FETs studied here.
Averaging the data over frequency finds the values for the remaining parameters. In
practice, USF developed software tools to perform the numerical processing o f Sparameter data by an implementation o f the circuit parameters within the Libra Series IV ,
V . 6 simulator. Alternatively, the small signal FET model extraction capabilities o f the
software program SPECIAL™ can be used to extract the small signal model elements in
much the same way. To use SPECIAL™ , a knowledge o f the Cold-HEM T bias limits
are necessary. These are the gate biases at which the parasitic resistors are extracted
(using A2 for example, V^=+0.5 V ) and the bias value used to extract the inductances
(Ig, ~ 40 mA/mm2).
5.3
INTRIN SIC FET NOISE GENERATOR EXTRACTION
The technique o f analytically determining the values o f the small signal model
parameters has been carried over into the noise model development in the last few years.
U ntil recently however, the noise generator coefficients were found as a result o f
numerical fitting o f the model to the noise parameter data [ 1 0 ], [ 1 1 ], The first published
direct calculation o f the noise coefficients P, R and C was given in 1991 by Riddle [103].
In Riddle’s work, the noise correlation matrix is used to deembed parasitic thermal noise
and allow direct calculation o f P, R and C associated with two intrinsic noise current
generators. Since then, the most recent works refer to this procedure as noise coefficient
extraction. A complete description o f the noisy parasitic/embedding o f the intrinsic FET
noise generators has been described by Pucel et. al. [104], An alternative to the noise
correlation matrix deembedding was proposed by Hughes [105]. Hughes describes a
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direct calculation o f the value Td coefficient in the noise temperature model, which are
the alternatives to P, R and C. This is done by assuming Tg to be equal to the ambient
temperature. Also, the thermal noise o f the lossy parasitics is not accounted for, but
instead the value o f Td accounts for both extrinsic and intrinsic noise processes.
Therefore, this simplified model also avoids the need to apply noise correlation matrix
techniques to deembbed Td.
5.3.1 Intrinsic Noise Generator Extraction Technique
Working from the developments discussed above, a procedure using the technique
o f Riddle was developed for use in CAD simulators such as Libra by Ikalainen [106], and
this technique is adopted in this work. This further development also provides a
connection between the various intrinsic FET models resulting from admittance, chain
matrix and hybrid parameter formats, which Riddle’s solution did not explicitly provide.
In this section, analysis o f the noise temperature model is included for completeness,
since both Riddle and Ikalainen use P, R and C. The task o f deembedding the intrinsic
noise generators from the extrinsic FET model is achieved by straight forward application
o f noise correlation matrix techniques [107], and this is detailed in Appendix B.
The advantage o f intrinsic noise generator extraction versus curve fitting, is the
ability to describe the elements o f the noise correlation matrix in closed form as functions
o f the measured noise parameters. For example, in the admittance representation o f the
intrinsic FET shown in Fig. 10(a), the y-parameters o f the FET and the four noise
parameters allow determination o f the noise currents ig and id. Using the equivalent
model o f Fig. 11(c), the generators i n and en result from a similar relation [70]. Since
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each o f these representations is equivalent, one can transform between different model
formats using the techniques o f Section 3.1. The extraction procedure presented below
follows the conventional chain matrix format developed by Rothe and Dahlke, and the
analysis with respect to measured data follows the work o f Ikalainen.
The procedure begins by writing the noise parameters o f the chain matrix model
in terms o f the measured noise parameters. Recall the chain matrix parameters from
Section 3.1 are the equivalent noise conductance, G0 the equivalent noise resistance, Rn
and the correlation admittance, Yc. In terms o f the standard noise parameters ( N F ^ ,
Y ,^ and R „) this gives the following relations,
- ropt
(98)
Relating the chain matrix and admittance formats by applying open circuited input and
short circuited output conditions on Eqs. (20) and (22) gives,
e,FI
(99)
where
is the uncorrelated part o f the chain matrix model. The noise generators used
in the P, R and C model as well as Tg and Td in the noise temperature model are
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equivalent to the hybrid parameter noise voltage e^ and noise current ih which can be
found in terms o f Eq. (98) by similarly relating the admittance format to the hybrid
parameter form, This yields the relations,
1
v
.
^n l
Ml
(100)
IL. =
-
l n2
Ml
To solve for the mean square values o f the hybrid generators in Eq. (100) requires first
writing Eq. (99) in terms o f Eq. (98). This is done by using Eq. (98) along with the
mean square generator relations o f Section 3.4 in Eq. (46). Once this is done the mean
square values o f Eqs. (44-45) are solved for in the desired format. The results are,
hi
(101)
■ru P
',P =
‘ 21
(102)
11
p = 4 * f lr
a/
Y
m
M21
l
lr ,,l
G. - « .
i
(g , - k
V, h
- M
(103)
-n p i(G „ * «„ m i2)
where Ta is the standard temperature, 290 K. The noise model coefficients P, R and C
as well as Tgand Tdare calculated directly from relations Eqs. (46) and (47). As a result,
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tt
a direct technique for calculating the noise generator coefficients o f a variety o f models
has been described. However, criteria for selecting coefficient values and validating the
resulting noise model need to be established before the direct calculation technique can
be used effectively.
S.3.2 Noise Coefficient Selection Procedure
Just as in the case with the small signal model elements, the noise coefficients may
be calculated at each frequency where noise parameters are measured. Likewise, the
determination o f the parameter values may become frequency dependent if the modeling
technique does not adequately address all significant sources o f noise, and have an
adequate small signal modeL In addition, the noise parameters are also determined with
greater uncertainty than the S-parameters (as discussed in Chapter 6 ), thus introducing
another issue in selecting the appropriate value for a model coefficient. The interrelation
o f the noise parameters described by the limits set in Section 2.4 w ill aid in this part o f
the noise model extraction. In this sense, the noise parameter limits are used as selection
criteria to cull bad data points. The criteria also serve to objectively quantify the choice
of a set o f noise modeling coefficient values for models that must extrapolate beyond the
range o f the measured data.
The algorithm for implementing the noise model coefficient extraction described
above is illustrated in the flowcharts o f Fig. 28 and 29.
Figure 28 describes the
processing o f a raw set o f model coefficients and Fig. 29 describes the selection o f the
final model values. Figure 28 begins by tracing the flow o f measured S-parameters into
the small signal model extraction process described in Sections S .l and 5.2. The
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measured noise parameters are tested according to the criteria o f Chapter 3 where 1 £
K j s 2 at this stage, although complete satisfaction o f these criteria may not be achieved
from the measurement, this test helps to establish the quality o f the measurement before
proceeding. The next step is to deembbed the intrinsic FET noise parameters. This
requires two inputs, namely the small signal equivalent circuit element values and the
measured noise parameters. Upon deembedding the intrinsic FET noise, the desired
model coefficients and noise parameter criteria are calculated at each frequency for a
given bias and temperature condition.
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Measure
Noise
Parameters
Small Signal
Modeling
Re-Measure
Noise
Parameters
Deembed
Intrinsic FET
Noise
Extrinsic Noise
Violates K,
Redo Extraction
Extract Noise
Model Versus
Frequency
Tune
Any K, > 1?
R„ Fits?
Any IC, <2?
Fits?
Output Data List for Post Processing
[Frequency, K,, T ^ , T ^ , P, R, q
Figure 28
Flow chart ofnoise modeling algorithm usedin this work. The bold lines
distinguish the normal path without modeling iteration.
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Input Data List for Post Processing
[Frequency, IC,, Tgate, Tdran, P. R, C]
Delete Data Points
For
{jC,<1 and K^2>
Sort Data Then
Find Medan and
Average Values
r-Yes-
Data N
Bimodal?.
'NoFfcd Median
Values
Find Average
Values
Save Model Values
Figure 29
Flow chart of noise model coefficient post-processing algorithm for Tg, Td, P, R,
and C.
The resulting plurality o f models can be tested at once within the simulator for comparison
to the data from which it was extracted. The first tests at this point in the flow chart are again
the upper and lower limits o f K j. If a non-physical result is returned here at all frequencies
then the small signal modeling must be in error. After passing these tests, the procedure
compares the measured noise parameters versus noise parameter values calculated from the
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extracted model coefficients and the input small signal model. These functions are given in
terms o f noise coefficients Tg and Tdand the small signal model elements by the relations,
(101)
Tmm
- = 2
where ft = gm / 2 it Cgs for the intrinsic FET and Tmtn is the noise temperature
corresponding to Fmin as in Eq. (31). Note that the reactive component, X opt, is a
function o f the small signal model only, and this makes Cgs an effective parameter for
tuning the model versus the data. In particular, tuning Cgs in concert with gm (to
preserve Q is effective in refining the fit versus frequency o f
and F ^ . In
general, this is found to be unnecessary for the majority o f data sets and if agreement
between the model and measurements cannot be reconciled by these means then either
additional noise sources exist or the data itself is in error. Nevertheless, the algorithm
proceeds by printing the related frequency, noise model coefficients and K t to a data list
for post-processing.
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Post-processing as depicted in Fig. 29 is required for several reasons. First, the
post-processor culls erroneous noise model coefficients based upon the Kt criteria for
each associated measured data point versus frequency. Secondly, due to the upper bound
on K2 it is not possible to anticipate what maximum value the noise coefficients may
attain. Therefore, the data points are sorted to acquire the mean and median values o f
the noise coefficients. It is experimentally observed that the dispersion in the noise
coefficients is small and random, therefore the noise coefficients are found to be
frequency independent and a mean value could be chosen. However, when an extreme
dispersion is encountered it is also apparently random and a bimodal distribution o f
values occurs. In this case a median value is useful. The nature o f the large dispersion
suggests that these points result from measurement uncertainty, although such points do
sometimes satisfy both K t and K2.
5.4
CHAPTER SUMMARY
Contributions o f this Chapter to FET small signal and noise modeling are three­
fold. First, this work advances techniques for parasitic resistor extraction in HEM T and
PHEMTs and implements a procedure whereby such an extraction is justified. Secondly,
the anomalous microwave frequency noise dispersion, exhibited below 4 GHz, is not only
associated with gate leakage currents, but the spectral behavior o f this parasitic effect is
characterized by noise correlation matrix methods. Finally, through a study o f the inter­
relation o f the noise parameters and resulting limiting criteria, a diagnostic software tool
for FET noise modeling has been implemented in an industry standard CAD simulator
These advancements provide a consistent means o f obtaining equivalent circuit model
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parameters at varied biases and temperatures. Each topic is summarized in further detail
below.
This work advances a technique (denoted Cold-HEM T) for extracting parasitic
resistance in HEMTs and PHEMTs. Experimental results for an InGaAs/GaAs PHEMT
also find the cold HEMT technique to be valid in the presence o f gate leakage current.
Furthermore, the Cold-HEMT technique establishes a connection between those desiring
a model extraction technique and the theory for forward biased gate currents in a
heterostructure FET. As a result, previous assumptions based on modeling the metalsemiconductor barrier (Shottky barrier) are shown to neglect the effect o f quasi-Fermi
level bending at the heterostructure barrier. This is why traditional techniques do not
apply to heterostructure FETs and why the Cold-HEMT technique is required.
Anomalous, 1/f2 dispersion o f FET microwave noise behavior is analyzed and
modeled in this work. The frequency dependent noise is shown to be contributed by
leakage currents from gate-to-source, and is explained through an analysis o f the noise
correlation matrix for the associated parasitic resistance. An example o f leakage effects
in PHEMTs produce l/o ) 2 frequency dependence in the noise generators. It was found
that the parallel combination o f parasitic resistance and capacitance explains why many
studies find an increase in the low microwave frequency noise spectral density.
This chapter described extraction procedures for bias and temperature dependent
FET noise modeling. The extraction procedures and measurements are tailored to
individual FETs through a consistent modeling methodology.
The software tool
associated with Fig. 28 for FET noise parameter modeling was developed and utilized
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extensively in the modeling o f a wide variety o f microwave FET technologies. The
completeness o f the analysis allows the identification o f possible modeling errors at a
variety o f stages in the overall model development. This capability enhances modeling
accuracy even in the presence o f large data errors, because the factor k l serves as a
quality control o f a variety o f possible errors.
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CHAPTER 6 MEASUREMENT TECHNIQUES
.
6.0 INTRODUCTION
An integral part o f the study o f FET small signal and noise performance versus
temperature is the measurement apparatus. This section describes the small signal Sparameter and noise parameter measurement systems used in this work.
Baseline
calibration procedures are discussed for both measurement systems, and the effects o f the
wafer stage temperature on these measurements are addressed. The final section o f this
chapter introduces a novel noise parameter determination technique that avoids lim iting
factors of the current baseline (and industry standard) technique.
ON-WAFER S-PARAMETER MEASUREMENT TECHNIQUES
6 .1
Accurate S-parameter measurements comprise a fundamental data set for
microwave CAD applications and FET research efforts. At USF these measurements are
made at the wafer level, and temperature control o f the wafer-stage temperature allows
thermal cycling o f a transistors base plate temperature. The experimental setup for small
signal S-parameter measurements used in this work is shown in Fig. 30, and a typical RF
wafer probe configuration is illustrated in Fig. 31.
The baseline S-parameter
measurement system at USF includes a computer controlled HP 851 OB Vector-NetworkAnalyzer (VNA) covering the 45 M Hz to 26.5 G Hz frequency range. DC bias is applied
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COMPTER
CONTROLLER
u
IEEE 488 BUS
HP6628A
DC BIAS SUPPLY
\ z
TEMPTRONIX
TP03
(25-200 C)
HP85106
ANA
WILTRON 360B
ANA
HP8340B
SWEEPER
WIL68169A
SWEEPER
HP8340B
S-PARAMETER
TEST SET
WIL3623A
S-PARAMETER
TEST SET
0.045-26.5 GHz
0.040-67.5 GHz
CASCADE MODEL 10
RF PROBE STATION
AND
TEMPTRONIX THERMALWAFER
STAGE
Figure 30
Schematic of small signal S-parameter measurement systemused in
work.
Gate
Drain
Source
Source
Figure 31
Ground Signal Ground (GSG) RF probe and illustrated FET
configuration for the wafer-level data measured in this work.
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via an HP 6628A Dual Channel power supply. The manual RF wafer probe station is a
CASCADE Model 42, and the wafer stage includes a Temptronix TP03 A thermal chuck
for cycling the wafer backside temperature over a maximum range o f 25 °C to 200 °C .
An additional VNA, a Wiltron 360B, extends the frequency range o f S-parameter
measurement to an upper lim it o f 67.5 GHz at the USF laboratory. Collaboration w ith
Hughes Aircraft Company helped to extend the S-parameter measurement resources for
this w ork through the use o f a CASCADE SUM M IT probe station [108]. With the
CASCADE SUM M IT station, a HP 8510C covers the 45 M Hz to 40.0 GHz frequency
range and includes an integrated thermal controlling capability for wafer stage
temperatures covering the -55 °C to 125 °C range in this work. The SU M M IT probe
station includes features that are particularly desirable for thermal cycling which includes
a vacuum micro-chamber enclosure for the RF wafer probes and the device under test
(D U T ). This environment is important for achieving low dew point temperatures and
minimizing interference due to undesirable lightwave and RF sources. In addition, the
calibration procedure, which is manually performed at USF, is computer controlled with
the SU M M IT system, and this improves both the S-parameter calibration and
measurement due to improved probe contact repeatability.
Calibration o f the VN A for on-wafer RF S-parameters is performed to remove the
intervening S-parameters o f the RF cables, probes, etc., as well as, internal VN A errors.
This procedure allows for the measurement o f only the DUT’s S-parameters.
Measurement errors include systematic errors, instrumentation errors and random errors
[109]. The systematic errors are predictable and identified in the process o f calibration.
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!t
These include: impedance mismatch and directivity errors, isolation errors between the
reference and test signals, and the non-ideal frequency response characteristics o f system
elements. Instrumentation errors include: system resolution and sensitivity, frequency
inaccuracy, frequency instability and dynamic instability. Random errors which occur but
cannot be removed through calibration include: noise, environmental effects, frequency
drift, and changes to the test setup between calibration and measurement. By performing
a calibration, an error model is constructed that establishes the desired port impedance
and measurement reference planes in an on-wafer environment. This is accomplished
using one o f several types o f well known techniques [110], [111], [112]. For this work,
errors are corrected for by measuring a set o f three reference standards, which comprise
1 2
independent data sets for correction o f
1 2
error terms is a standard two-port
correction scheme.
A common set o f standards for RF wafer probing includes the following; (1) a
reference impedance standard consisting o f either a matched resistive load or a
transmission line impedance, ( 2 ) a reference reflection standard consisting o f a pair of
short circuit or open circuit connections at each port, and (3) a reference phase (or time)
delay standard which allows the definition o f the measurement reference plane. This
Line-Reflect-Match (LRM ) calibration with coplanar standards is the current baseline
calibration methodology used in this work. Note that w ith LRM, the S-parameter
reference planes are typically defined at the probes tips [113] and [114]. This calibration
method is also both accurate and efficient for temperature dependent on-wafer Sparameter measurements at microwave frequencies [ 1 IS ], An advanced version o f LRM
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ii
includes one additional reflection standard to account for additional reactive parasitics
in the load standard. This latest technique is known as Line-Reflect-Reflect-Match
(LRRM )[116].
Once the S-parameter calibration is completed, several on-wafer measurement
issues exist that are critical to the measurement o f S-parameters. The resistive match
standard exhibits the most temperature variation, but even its thermal coefficient is only
rated at 100 ppm/°C [108]. For the temperatures studied in this work this yields an error
in the reference impedance o f less than 0.5% . A t millimeter-wave frequencies, the
crosstalk between the RF probes and the proximity o f the FET to the RF probes may
require the addition o f intervening transmission lines to offset the probes from the FET.
The baseline procedure used in this work for calibration and measurement o f Sparameters versus temperature is as follows:
(1)
Set the temperature of the thermal chuck and allow 15 minutes for stabilization
o f the equipment setup with respect to the thermal chuck temperature.
(2 )
Calibrate S-parameters using LR M standards and the associated error correction
algorithm internal to the HP8510 firmware.
The S-parameter measurement
reference plane is located at the RF probe tips for the data measured in this work.
Measure data as required.
(3)
Before the temperature is cycled to a new value, the RF probes are lifted clear o f
the substrate. The cycle begins again at Step (1) above.
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6 .2
MICROWAVE NOISE PARAMETER MEASUREMENTS
The following provides a discussion o f the noise parameter measurement
techniques studied through the course o f this work. These techniques are based upon a
noise figure measurement, from which the noise parameters are calculated. First, the
system o f Fig. 32 is shown as it was used to measure the noise figure and S-parameters
of FETs. The standard technique for noise parameter determination depends upon the
ability to measure the noise figure at several known input impedance values. After
discussing recent advancements in the standard technique, a novel technique is then
introduced that does not depend upon the use o f a variable impedance tuner. The new
method requires both a noise figure measurement at several frequencies for one known
source impedance and knowledge of the FET small signal model. The significance o f the
method is expected to impact several topical subjects including: advancement o f
measurements at millimeter-wave frequencies, determination o f noise parameters for
ultra-low noise FETs and noise figure measurement versus temperature. The method
may also be applicable to the improvement o f conventional tuner based noise parameter
systems by identifying ill conditioned tuner states.
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CONTROLLER
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BUS
HP6628A
DC BIAS SUPPLY
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ATN NP5B
NOISE PARAMETER
TEST SET
HP8510B
ANA
DC +28 V
A - S-PARMS.
B« NOISE
HP8340B
SWEEPER
B
HP8971
NOISE FIGURE
METER
U D flQ 7 fl
DOWNCONVERTER
h
IF
U
HP8340B
S-PARAMETER
TEST SET
HP 346B NOISE
SOURCE
(IS dB E N R )
RF
L
ATN
MICROWAVE
TUNER
RF WAFER PROBES
RECEIVER.
S
— (NOISE
POWER)
. . S
CASCADE MODEL 10
RF PROBE STATION
AND
TEMPTRONIX THERMAL WAFER STAGE
Figure 32
Schematic of the automatic noise parameter and S-parameter measurement
system used in this work. The software used to control the measurement
system is ATN’s NP5 noise parameter measurement software, which was
modified at USF for an equipment specific setup and to include large
sweeps o f bias (greater than 40 points).
6.2 . 1 Microwave Noise Figure Measurements
The noise parameter measurement setup o f Fig. 32 is based on the ATN NP5B
noise parameter measurement system and the software provided with the system
automates both calibration and measurement [117], A detailed discussion o f the theory
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and setup o f such systems is found in the references [118],[119].
The following
discussion reviews how the device noise figure is deembedded from the noise power
measured at the noise figure meter and down converter o f Fig. 32.
A simplified diagram for the noise measurement system in Fig. 33 illustrates a
basic problem encountered when measuring the noise figure o f a device. In Fig. 33, the
noise figure, F2, and S-parameters o f the device under test, DUT, are desired. While the
S-parameters o f the DUT are measured at the reference planes
1
and 2 , the noise figure
o f the entire cascade o f two-ports is measured at the receiver and F2 must be calculated
using the cascaded noise figure equation [ 1 2 0 ],
NF. - I
NF,~ 1
+ — -p
+ r 'r '
1
^1
2
(1 0 2 )
where NFmis the noise figure measured at the receiver, and the NFa and Ga terms are the
noise figure and available gain o f the blocks n = l, 2 and 3. Solving for the DUT noise
TUNER
DUT
PRE-AMP
NF1
NF2
G2
NF3
G3
Figure 33
Simplified schematic of noise figure measurement system. Along with the
S-parameters o f each two-port shown here, the quantities r, 2 3 and G, 2
are used to deembed the DUT noise figure NF2.
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RECEIVER
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figure in Eq. (102) gives,
NF,3 - n
M 2 = GA NFm - NFt
Gl G2 ,
+ 1
(103)
The available gains are found from S-parameter measurements and are given by,
„ _
l-s2,.„P(i-ff’.-.PX*-ir;p)
Cr^ —
1( 1 "
-
(104)
^ 22, n ~
(I “
where * denotes the complex conjugate, n denotes the two-port associated with GA and
n-1 denotes the reflection coefficient to the left o f two-port n. In Eq. (104) the reflection
coefficient looking back into the two-port n is given by,
T> _ C
n -
____
_
S 22,n + “J
1
~ -----n -I ll,n
<1 0 5 )
From G[ and G3, both N F t and NF3 are calculated using the relation for the noise o f a
passive, linear component,
NF = 1 +
' ^1 - • i h
)
rT
<««*>
where GA is the available gain and T„ is the standard temperature, 290K. To perform a
frequency dependent measurement, an automated system stores the available gain data
and noise figure measured over frequency. For a given DUT, NF2 can be calculated from
Eq. (103). Once the noise figure is known for a given set o f input reflection coefficients
presented to the DUT, the noise parameters may be calculated as discussed next.
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6.2.2 Conventional Noise Parameter Determination Technique
For a given frequency, the noise factor o f a linear two-port is a function o f the
generator or source admittance Y , = G, + jB , presented to the input port as given by
[ 121],
(107)
where the minimum noise factor (N F ,*,), the equivalent noise resistance (R J and the
optimum source admittance (G^+jB^t) are the noise parameters (also discussed in
Chapter 3 o f this work). A minimum number (n = 4) o f independent noise factor
measurements, NFroat source admittance states, Y m, are sufficient to solve for the four
noise parameters. However, more data is usually necessary to average out the effects o f
errors introduced by the noise figure measurement and uncertainty in knowing the source
admittances, Y m. An earlier and valuable approach required a tedious search for Fmin and
Yopt[122].
The first solution o f the noise parameters from a set o f noise figure data measured
at various source admittance states was given by Lane [123]. Since then, a variety o f
other solutions have been published for the determination o f the noise parameters from
a redundant set o f noise figure measurements based upon Eq. (107), [124], [125], [126],
[127]. For a given noise measurement system, the most common procedure to determine
the noise parameters involves a least-squares error criteria to find a solution for the noise
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!
parameters. For example, Lane’s technique transforms Eq. (107) into the linear form,
C + B 2G 2 +■ DB ,
NF, = A +BGsi
M + -------------Q£ ---------- iL
(108)
s,t
where A, B, C and D are functions o f the noise parameters [123]. A solution o f Eq.(107)
for a number of noise figure measurements i - n > 4 at / admittance states is obtained by
to
"
-
1 *
14
minimizing the error, e, with respect to A, B, C and D o f Eq. (108),
A +B G
\
X ,,
2
i=i
C
B
+D
- F.
GS , t
GS , l
i —i
Qi *>'
(109)
which includes a weighting factor, w-v for a given set o f i noise figure and source
admittance measurements.
6.2.3 Review of the Numerical Determination o f Noise Parameters
The original technique developed by Lane did not address two important issues.
First, Lane noted that selection o f appropriate tuner states should be considered to avoid
singularities in the solution matrix for the A, B, C and D coefficients in Eq. (108).
Secondly, the original technique did not include the uncertainty o f the tuner state Y s ;
(Gsi and Bs^) in the error coefficient equation. In determining the noise parameters, Lane
did suggest a need for an improved data processing technique[123]. Sannino then
reported on an investigation o f loci of Y s on the Smith Chart which produced
singularities and experimentally exhibited an updated procedure for selecting source tuner
states [128]. In that work, it was concluded that a measurement o f data from tuner states
140
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that belonged to at least two families o f the singular loci was adequate for a solution that
characterized the surface described by the noise figure equation. The singular loci are
circles on the Gs, Bs plane o f the Smith Chart. One o f the singular locus conditions is
when Gs, Bs and [Ys |2 equal constant values.
Solutions for the noise parameters are also dependent upon the impendance
presented to the input port, a significant advancement in the determination o f noise
parameters that accounts for errors due to tuner state uncertainty was published by
Mitama and Katoh [127], They improved the least-squares fitting algorithm o f Lane by
accounting for the sum o f the squares o f e in E q .(l09) due to the source state
components Gs and Bs, in addition to the error in the noise figure. However, the least
squares algorithm for two dimensional variations (both
and Y si) requires some initial
assumptions about the error. Therefore, to efficiently solve for the noise parameters, the
work o f Boudiaf [129] extends Williamson’s method [130] to rewrite Eq. (108) as the
equation o f a straight line. As noted in a review o f these noise parameter fitting
techniques [131], this solution is both more efficient in terms of computational speed and
less sensitive to the choice o f admittances chosen for the noise figure measurements.
Further numerical techniques have been implemented to improve the
determination o f the noise parameters, since a procedure was first suggested by
Lane[l23]. Adamian and Uhlir introduced a novel receiver calibration technique used
by the ATN System in this w ork[l32]. Other notable advancements include the use of
a vectored error correction approach to the noise parameter measurement [133]. In this
method a linearized noise figure equation, similar to that o f [127], minimises the error
141
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sensitivity due to the noise figure as well as Gs and B#. Because the vectored method
is built upon a projection theorem argument, quantitative as well as qualitative analyses
o f the error sensitivity are demonstrated. As in Lane’s work [123], a coefficient matrix
for the linearized set o f equations is developed. However, O’CaUaghan et. al. [133]
proceed to solve for the coefficients of the linearized equations in closed form. The least
squares fit o f these coefficients is avoided by a decomposition o f the matrix (Cholesky's
Method [134]). The singularity o f the matrix can then be addressed by standard vector
methods. Additionally, the type o f successful vectored error correction that is common
to S-parameter network analyzer calibration is applied to the projection o f the vectors
which comprise the linearized noise figure equation. The result is that a quantitative
analysis o f the measurement error sensitivity and the degree o f ill-conditioning o f the
equation matrix is addressed directly.
6.3
ALTERNATIVE METHODS FOR NOISE PARAMETER DETERMINATION
The greatest drawback to Lane’s technique is the limitation o f the variable
impedance tuner. Variable impedance tuners add loss to the measurement system, are
difficult to calibrate and repeatability is a significant issue with respect to minimizing
errors. Although continuing improvement o f mechanical and electronic tuners have
achieved high reflection coefficients (F
* 0.9) at W-band, the necessary transmission
lines required to connect the tuner can degrade performance signficantly (V
+
£
0.2). The next section introduces several alternative techniques to omit or at least limit
the need for a tuner.
I f the use o f a source tuner is abandoned, then additional information is required
142
4
...
._
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to solve for the noise parameters. One such alternate method obtains the necessary
information about the FET from the small signal equivalent circuit model. This technique
was first published in 1991 by Dunleavy et. al. [135] and was historically begun w ith the
work o f Webster and Patience [13 6 ]. An account o f the published method is detailed in
the section that follows. It is based upon the measurement o f FET noise figure at one
known source impedance state (nominally 50 Ohms) and knowledge o f a FET small
signal model. Following the work o f Dunleavy et. al., Tasker et. al.[2 0 ] modified the
original algorithm by using the noise temperature model o f Pospieszalski. Another work,
that follows the example o f [135] is that o f Dambrine et. a l.[l3 7 ], however, this
measurement utilizes a coplanar line at the gate o f the FET to synthesize a simplified
tuner. Later, Burocco [138] advanced this technique whereby the simplified tuner is not
needed. The development o f the original technique has also been generalized and
improved upon here.
6.3.1 A Tunerless Noise Parameter Determination Technique
The relation between the noise factor o f a linear two-port and its noise parameters
given in Eq. (36) o f Chapter 2 may also be written in terms o f the reflection coefficient
as,
F = Fmm + 4 -
(HO)
where Tsis the reflection coefficient presented to the input o f the two-port,
ropt is the
optimum reflection coefficient for minimum noise and ZDis the reference impedance. As
143
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described above, conventional noise parameter determination methods make use of
redundant sets o f noise figure data for the analysis o f device noise parameters. However,
the method described here requires a measurement o f the noise figure over several
frequencies at only one source state, r m, because a small signal equivalent circuit model
provides the balance o f the information needed to solve for the noise parameters. As
developed by Dunleavy et. al., the intrinsic FET noise model is characterized by
equivalent gate and drain noise current generators, ig and id. These generators are
functions o f the noise coefficients P, R and C as detailed in Chapters 3 and 5 o f this
work, and the two current generators have a related noise correlation matrix, C^, in the
admittance parameter format.
The noise figure equation o f a pair of correlated noise sources with mean squared
values | /g | , I /j | , | i ’ id | and [ igQ | is in general a quadratic form, that for the case of
ig and id, may be represented in terms o f the noise coefficients P, R, and C as,
NF =
+ M2 R +
P + M4 Im [C ] { R P
.
( ill)
where Im denotes the imaginary part o f C and M b M2, M 3 and M 4 are functions o f the
equivalent circuit model and the source impedance presented to the input o f the FET.
Although the correlation coefficient is in general a complex value, the real component may
be small and negligible for the noise model using two noise currents [139], In the original
work by Webster et. al. [137], P, R, and Im[C] were fit such that the error between the
measured noise figure data and Eq. (105) was minimized
This was accomplished by
144
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linearizing E q.(l 11) and iteratively solving with a least-squares algorithm, SIMQ [140]. A
more robust determination o f P, R, and Im[C] was later applied to oprimize the parameters
inEq. (111) using a Levenberg-Marquardt algorithm, found in mathematical libraries such as
LINPACK[141]. A summary o f the noise parameter determination is as follows,
1.
Measure small signal S-parameters and extract an equivalent circuit model for the
FET as described in Chapter 3 o f this work.
2.
Measure noise figure at one known source impedance for “n” frequencies with
n>4.
4.
Fit the noise model coefficients P, R and Im [C] based upon the noise factor
expression in Eq. (111).
5.
Using P, R and Im[C] o f Step 4, generate a simulated set o f noise figure data
based upon a random selection o f input source impedance states.
6
.
Based upon the computed noise figure data in Step 5, apply Lane’s technique to
determine the noise parameters at each frequency.
The “synthesized” noise figure measurement o f Step 5 is a major drawback to this
procedure. The following section, describes a direct method o f determining the noise
parameters using noise correlation matrix methods to embed the noise generators and
their coefficients P, R and Im [C] within a FET noise model.
6.3.2 A Generalized Noise Figure Equation
In keeping with the theme o f Chapter 3, which directly calculates model elements and
noise coefficients from data, a direct extraction method is described in this section for the
tunerless method of determining noise parameters. The procedure has three parts: ( 1 )
145
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deembed the intrinsic noise parameters, (2) fit the coefficients P, R and Iin[C ], (3) embed the
generators described by P, R and Im [C] into the FET model and calculate the noise
parameters using the modeL Similar to the method described above, the noise modeling
method presented here has two input data sets:
1
)
Small signal model equivalent circuit parameters.
2
)
Noise figure measured at a known source impedance.
These noise model coefficients (P, R and Im [C ]) are related to the noise figure
through Eq. ( Il l ) , which was derived from a nodal circuit analysis. However, E q .(l 11)
can be derived as a summation o f noise correlation matrices. Equation (42) o f Chapter
3 relates the noise figure o f the extrinsic FET through the noise correlation matrix CA,
and this expression is rewritten here,
& Ca z
NF = 1 + -------- ---Re t^ e J
a i2 )
i
Z=
where Re denotes the real part,
is the input generator impedance, f denotes the conjugate
transpose and Z is the vector o fthe input impedance. Within CA the intrinsic noise generators
o f the FET may be further specified in terms o f a two parameter noise model using noise
temperatures Tg and Td or a four parameter model with sources ig and id having coefficients
P, R, and Im[C], Whichever intrinsic matrix is chosen, the analysis proceeds by decomposing
the matrix CA into components of the extrinsic and intrinsic noise generators. The result of
the analysis that follows yields an expression similar to Eq. (111), but is now derived in terms
146
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o f matrix quantities.
The coefficients M (,
M 3, and
o f Eq. ( I l l ) are reformulated through the
correlation matrix CA. Substituting the noise correlation matrix o f the intrinsic FETCyj and
the necessary transformation matrices into Eq. (112) gives the expression,
(113)
where 2 is as defined in Eq. ( 1 12), Tis a two-port matrix that comprises the extrinsic noise
generators and B is a transform matrix described in detail below. Comparing Eq. (113) and
Eq. (112), the coefficient M t can be separated and written in terms o f the matrix T as,
The extraction o f the parasitic elements comprising matrix T are dealt with in Appendix
A and the remaining disscusion concentrates on solving for the intrinsic FET noise.
The matrix C is introduced and defined as a noise correlation matrix for the
intrinsic FET given by,
(115)
where, Ag is the gate parasitic network chain-matrix, Zxis the intrinsic FET impedance
m atrix, and Ais is the Z-/o-A matrix noise transform o f the intrinsic FET with a series
connected source network. To solve for the coefficients M2, M 3, M 4, the right hand side
147
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o f the sum in the parentheses in E q .(ll3 ), which is the intrinsic part o f the FET noise
correlation matrix, is expanded and set equal to Eq. (111). The desired expanded form
to equate to Eq. ( I l l ) is a quadratic relation which is another way o f writing C such
that,
C ~
^11
+ C2lZgen + Cl2Zsm +
(116)
To simplify the algebra, Eq. (116) is rewritten as,
C = X C ^Y
where X = Ag Ais
and Y = X* .
(117)
The result found upon expanding Eq. (117) is Eq. (115), and this result is equated with
E q .(lll) to provide a solution for the coefficients M 2, M 3, and M 4 in terms o f the
components o f matricies X , Y and C^,
148
j(
-
_
______
___
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K - K r , , -x nynz^ *x uraz±. - V az ^ \
(“ C „ r
(118)
i
^ 3 = 1^ 1 2 ^ 2 1 + -^1 2 ^2 2 ^gen + ^ 2 2 * 2 1 ^wi + ^ 2 2
•
a/ 4
^22
^gen^gat\
(119)
*»
* * tzgJ
-
=
f t l^ 2 |-
V u ) + F x J n - W u fc e n +
*
(*2 1
*2 2
'
(120)
J ^ CgS
■ •ft-]
With these coefficients determined, the noise model coefficients P, R, and Im [C] are
solved for by curve fitting Eq. (111) to the measured noise figure o f a FET. Finally, the
modeled version o f the extrinsic FET correlation matrix is recovered by embedding the
characterized sources within the noise model as presented in Chapter 2 and detailed in
Appendix A. Two benefits come from this result: (1) the last step avoids the need to
“synthesize” a measurement of noise figure data as in Step 5 o f the previous section and
(2 ) the description can be generalized to whichever intrinsic noise generators are desired.
149
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6.4 RESULTS FOR A NOVEL DETERM INATION OF FET NO ISE PARAMETERS
To demostrate the viability o f the single source state algorithm, the following
procedure was adopted:
( 1)
Obtain noise parameters from a conventional tuner based technique. Since the
conventional system stores the “raw” noise figure data at each o f the tuner
impedance states, this data serves to test the single state algorithm at a variety o f
tuner impedances.
(2)
Determine the small signal FET equivalent circuit model parameters.
(3)
Format the raw noise figure data from the conventional system as independent
measurements for each associated tuner state over frequency.
(4)
Apply, as the measured input, the independent data sets assembled in Step (3) to
the single source state algorithm. Tabulate P, R and Im [C] for each data set and
calculate the noise parameters using the resulting FET noise model.
(5)
Compare the original measured noise parameters from Step (1 ) with the resulting
noise parameters o f Step (4).
150
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As an example, the algorithm developed in this work from correlation matrix
deembedding was tested on a conventionally measured noise parameter data set, for a
GaAs MESFET. This data consists o f noise figure measured at sixteen tuner state
impedances per frequency. Following the plan laid out above, the single source state
algorithm calculated P, R, and Im [C] for each one o f the sixteen input source impedance
states presented to the FET. As a result, sixteen possible model sets o f P, R and C
coefficients were calculated. The most natural source impedance state to present to the
FET is nominally 50 Ohms, where no tuner is needed.
Figure 34 compares the
conventionally measured noise parameters with the noise parameters resulting from the
single source state algorithm versus frequency for a 0.5 * 300 pm GaAs MESFET. The
4
to
1
a
3.5
X
▲ Fmin
O m
+
X
Ropt
Xopt
160
a
140
A
120 7J
3
o
10032.
2 .5
X
o
c
^
2
CD
5 ,1 .5
c
40
E
20 w
LL
80
60 5
1
§
0.5
10
15
20
25
30
-20
Frequency (GHz)
Figure 34
Comparison o f measured and modeled noise parameters using the single source
state algorithm with Z, = 50 Ohms. The FET is a 0.25*300 pm GaAs MESFET
biased at V4=3V and %151^.
151
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■A— lm[C]
1.2
1.3
1
0.8
0.9 -
0.6
0.7
0.4
0 .2
0.5
. q
0.3
0
0
2
4
6
8
10
12
14
16
Source Impedance State
Figure 35
P, R and Im[C] versus state number for 16 different tuner source
impedances where the noise figure was measured over the Smith Chart.
FET resulting noise model was derived from the noise figure measured at a SO Ohm
source impedance, and the associated noise model coefficients are P=0.91, R=0.19 and
C=0.86. Differences between Fminare attributable to the rapid falling o ff o f the available
gain above 20 GHz. An associated comparison o f the values for P, R and Im [C]
determined at each tuner state is shown in Fig. 35. This shows a general trend for the
noise coefficients having mean values o f P = 0.86, R = 0.24 and C = 0.79. Tuner states
2, 9 and 16 vary the most from the mean, and their associated noise parameters similarly
fit the data less well.
152
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6.5 CHAPTER SUMMARY
The S-parameter and noise parameter measurement systems used in this work
have been reviewed. Calibration procedures are based on standard practices for on-wafer
S-parameter measurements at frequencies up to 67 GHZ. The temperature control o f the
wafer baseplate is held within
± 1
°C over the 25 °C to 85 °C range. Procedures to
account for the thermal settling o f the system upon cycling o f the wafer-stage
temperature were implemented to allow for accurate repeatable calibrations.
A new method has been described for FET noise parameter determination at
millimeter-wave frequencies.
This method avoids the complications o f a variable
impedance tuner, and requires only the knowledge o f a small signal equivalent circuit, and
noise figures measured across a range o f frequencies for a single known source
impedance. Noise parameters derived from this method are shown to agree w ell with
those obtained from tuner based measurements. A review o f previously reported noise
parameter measurement techniques reveals a common dependence on tuner based
measurements or the use o f approximations that are not valid at millimeter-wave
frequencies. Further utility o f this technique may be in its use as a diagnostic tool for
examining ill-conditioned tuner states used in tuner based measurements. Since this
solution for the noise parameters also solves for a set o f noise model coefficients, the
model is readily available to extrapolate the noise parameters beyond the range o f
measured data.
153
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CHAPTER 7. FET NOISE MODELING RESULTS
MODELING RESULTS
7 .0
This chapter applies the theory and techniques developed in Chapters 2,3,4 and
5 to demonstrate a systematic modeling o f FET noise performance versus bias and
temperature. The effects o f temperature on low-field mobility and the energy bandgap
are the two major controlling factors in the variation o f the modeled element values.
W hile some work towards temperature dependent FET small signal equivalent circuit
modeling was noted in Chapter I, little knowledge o f related microwave noise
performance exists in the literature.
In this respect, this work demonstrates a
temperature dependent noise modeling technique applied to a variety o f microwave FETs.
The advanced noise model extraction technique is applied to present new plots o f
FET noise model coefficients and their thermal coefficients. The thermal coefficients are
based on the linear relation proposed in Chapter 4. Therefore, this chapter begins by
presenting results for the linear dependence o f the FET model parameters. After the new
noise model thermal coefficients are presented, simulations using the table based model
are compared to measured S-parameters and noise parameters. The value o f the table
model is then demonstrated through frequency and temperature extrapolation
comparisons to data and bias dependent simulations. Finally, a comparison is made
between several FET types based on the noise-to-gain ratio, NGR, o f Chapter 3 .
154
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7.1
EQUIVALENT CIRCUIT PARAMETER TRENDS
Common conditions for the results that follow include: S-parameter and noise
parameter data measured at baseline 2.0 GHz to 18.0 GHz. A transistor baseplate
temperature controlled at the wafer chuck from 2S°C to 85°C and held within ±1 °C .
Gate and drain bias potentials were selected over a grid o f points in the saturated region
o f the FET D C -IV plane. Additional cold-biased measurements were measured as
described in Chapter 3. Model extraction procedures were applied to the measured data
sets and the equivalent circuit parameters were tabulated at each bias point and
temperature. Initially, five temperatures were chosen to evaluate element temperature
dependencies. Once a clear linear dependence on temperature was verified, subsequent
data collection was optimized to a minimum o f three temperatures. Next, a least squares
decomposition o f the data was performed to calculate the slopes and intercepts o f the
temperature model at each bias point. Examples o f the extracted model parameters for
FETs A l, A2 and C l are detailed in the results that follow. These represent several
distinct variations o f microwave FET technology.
Examples o f MESFET A l and PHEMT A2 intrinsic model parameters are shown
in Figs. 36-39. These plots illustrate the bias-dependent variation o f some intrinsic
parameters extracted for the subject MESFETs and PHEMTs at 25 °C and 85 °C . The
most notable trend includes the saturation o f the PHEMT transconductance versus V„c
gs
which doesn’t occur in the MESFET. The saturation is due to the accumulation o f 3-D
charge in the supply layer as the Fermi level (with respect to the bottom o f the 2-D w ell)
is raised above the conduction band in the charge supply layer.
155
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60
£
50
C?
40
w
O
t
T«J
MsJZSC
gm_2SC
ldsjB5C
gm_85C
1
Figure 36
-
0.8
-
-0.4
Vgs (V)
0.6
0
Plot ofmeasured MESFET I* (mA) and experimentally extracted gm(mS) versus
Vp (V) for two temperatures.
Ri 25C
Rds 2SC
- O - Ri 85C
-■G- Rds 25C
~ 350
a 200
-0.6
-0.4
Vgs (V)
Figure 37
Plot of experimentally extracted MESFET bias dependence for
versus (V) for two temperatures.
156
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and R * (Ohms)
I
180
140
120
160
09
100
S
V
60
120
(A
■o
100
20
80
-
0.8
-
0.6
-0.4
-
0.2
Vgs (V)
Figure 38
Plot of measured PHEMT Ij, (mA) and experimentally extracted
(V) for two temperatures.
(mS) versus Vg,
170
—A—Rds 25C
-■&- Rds 85C
Ri 2SC
- Q - Ri 85C
150
E 130
& 110
-
0.8
-
0.6
-0.4
-
0.2
Vgs (V)
Figure 39
Plot of experimentally extracted PHEMT bias dependence for R.and R* (Ohms)
versus Vg, (V) for two temperatures.
157
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i
i\I
This charge does not contribute appreciably to Ids, but serves to decrease gm. The low noise bias point for FET A2 is near ^ = -0 .9 V. A t this bias point, A2 shows the least
variation in
and Ids due to temperature, but the gain is also lower here, as this is
close to pinch-off, V p=-1.2 V. A2's transconductance is also three times that o f A l at
the same gate width o f 300 pm, and the resulting high £ for A2 improves its noise
performance.
In comparison, MESFET A l shows decreasing gm with increasing
temperature below Vg, = -0.54 V, and increasing gm above this point.
Figures 40 and 41 pldt the gate bias dependence o f the noise coefficients Tg and
Td for a variety o f FETs modeled during the course o f this study.
Similar room
temperature variations are found in a number o f published works. For example, on a
variety o f state-of-the-art low-noise HEMTs (0.1, 0.25 pm* 100 pm), Nguyen et. al. find
Td variations with V9 between 1000 K and 12000 K and Tg between 100 K to 800 K.
Tasker reported Td values o f 2098 K and 1834 K for low-noise biased PHEMTs (0.3
gm* 100 pm), but in this case Tg is assumed to be the room temperature value. Tutt also
assumes Tg =
for highly strained taajGagjAs HEMTs (0.15 gm *90 pm)[142] and
extracts gate bias dependent values o f 2000 K < Td < 3300 K for low V ds biases and
2800 K < Td > 10000 K for higher Vds biases. For comparison to the highly strained
Inft7 Ga0JAs HEMTs, Tutt finds 4600 K < Td < 11000 K for low-noise GaAs MESFETs
(0.5 gmx300 pm) at higher
biases. In each case, Td increases with drain current, and
the drain noise is two to four times larger than the gate temperature.
158
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1000
— 0 — A1
A2
—3-— A3
☆ C1
800
600
09
I-
©
☆
T=298 K
400
--<b-"
- Q-----
200
Q
L .
i
1
-1.3 -1.1
I
. . . .
I
. . . .
I
. . . .
I
. . . .
I
.
i
.
-0.9 -0.7 -0.5 -0.3 -0.1 0.1
Vgs (V)
Figure 40
Comparison of extracted Tg(K) versus Vg, (V) for a variety of FETs modeled in this
work at V * m the saturated DC-IV region with T=298 K.
12000
10000
A1
A2
“Q— A3
8000
T=298 K
6000
4000
2000
1.3 -1.1
-0.9 -0.7 -0.5 -0.3 -0.1
0.1
Vgs (V)
Figure 41
Comparison of extracted Td(K) versus Vg, (V) for a variety of FETs modeled in this
work at V j, in the saturated DC-IV region with T=298 K.
159
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In this work, a few FETs are modeled over a wide range o f biases and
temperatures, as opposed to modeling a statistically significant sample o f FETs over a
limited range o f conditions. Because o f this trade-olf in the evaluation o f performance,
it is important that a representative FET sample is chosen for each type tested. The
uniformity o f each sampled FET type was screened from a sample population, depending
upon size, to include various wafer locations and/or number o f individual die. Helpful
data for performance screening includes: ( 1 ) the threshold voltage, Vth, which is
dominated by the repeatability o f the gate etch depth and cap layer thickness, ( 2 ) the
forward transducer gain, SI 2 (dB), which is indicative o f transconductance variations, (3)
the minimum noise figure, F ^ (dB), which is an indicator o f ohmic contact uniformity
and gate contact quality due to leakage current noise and (4) the D C -IV curves which
also indicate gate etch depth repeatability, pinch-off characteristics and in the case of
heterostructures, trap densities which result in a D C -IV kink effect. Once the initial
screening o f performance is complete, a more detailed comparison o f extracted model
parameters for a few FETs is made.
Mean values and the standard deviation from the mean for gm and
o f five
samples o f A l and A2 are listed in Table 9. Except near pinch-off, these variations are
small. The relative standard deviation from the mean for the transconductance is < 5%
and < 7% for A l and A2 respectively. The percent deviations for the output resistances
is < 3% and < 5%for A l and A2 respectively At pinch-off, a wider variation for both
parameters is exhibited due to variations in the threshold voltage, Vta, o f each FET.
Figures 42 and 43 relate the gate bias dependence of g,,, and
for five samples of FETs
160
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A l and A2. The envelope o f variation shown in Figs. 42 and 43 represents one standard
deviation from the mean.
Based on the initial screening results and these latter
comparisons a representative FET was measured and modeled for each technology
studied.
Statistics for A2 (n=5)
V SS
(V )
8 m
Mean
m
StdDev
8
R ds
Mean
Statistics for A l (n=5)
1
R ds
StdDev
Sol
Mean
8 m
StdDev
R ds
Mean
R ds
StdDev
-I
108.477
17.5616
144.841 24.8803
-0 . 8
177.897
1.82836
94.514
5.01477 30.3337 7.79948
171.285
18.71
-0 . 6
187.926 7.59042
91.4927
1.18166
43.902
10.6131
155.728
12.464
-0.4
169.169 9.64643
99.8107
1.19413
53.7443
8.58252
150.583
2.5597
-0 . 2
145.418 7.76409
119.908 3.25763
62.9443
6.21742
155.538
10.6097
0
124.624 5.44183
150.291
70.9993
3.88698
163.819
10.2569
7.07985
19.0867 8.71217 225.481
161
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39.4361
200
co 180
E
xz
O
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co
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tr 140
120
O)
« « ^ ***** Rds
0 Q r ■. . . I ■. . ■I "
. I ■. I ■.. . I • . ■I . .
80
1.2 -1 -0.8 -0.6 -0.4 -0.2
0
-1.2
i
i
i
i
V gs o n
Figure 42
Room temperature variation of extracted transconductance and output resistance for
FET A2 versus
(V) with a one standard deviation envelope for five samples.
80
300
gm +/-
cn
&
60
250
40
200 o
I
20
150
Rds
100
1.2
-1
-0.8 -0.6 -0.4 -0.2
Vgs
Figure 43
0
on
Room temperature variation of extracted transconductance and output resistance for
FET A l versus Vg, (V) with a one standard deviation envelope for five samples.
162
i
._
______________
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
i
In some cases, like FET A2, a single bias point was used to illustrate typical statistical
variations in the small signal extraction. For example, Table 10 gives results for models
extracted from n~ 1 0 FET samples at room temperature. Typical variations o f the relative
standard deviation are less than 5% for dominant parameters like g^ Cp and R *. Two
parameters, Rj and t , are particularly sensitive to the deembedding process and subject
to numerical rounding errors. However, the greater than 10% variation in these elements
is not particularly alarming as the small signal performance is not as sensitive to these
element values. Finally, the reactive parasitic elements are subject to larger variations
due to probe placement repeatability, but the good uniformity o f the extracted intrinsic
model elements does not indicate this is a problem.
Table 10 Mean and relative standard deviation for extracted small signal
_________ model parameters for a sampling (n= 1 0 ) o f FET A2________
Parameter
Mean
%o
166.073
gm(mS)
3.6
(^ (fF )
377.135
5
CWCfF)
57.711
4.6
62.783
Cgd(fF)
2.5
(ohms)
78.633
3.1
0.356
Tau(ps)
14.7
Rj (ohms)
1 .2 1 2
1 2 .1
Rs (ohms)
1.645
1.9
Rd(ohms)
2.453
1 .6
Rg (ohms)
1.819
1.4
Ls(pH)
2.855
1.3
Ld(pH)
32.264
6
Lg(pH)
14.086
20.5
24.027
5.9
CpgCff)
33.944
7.2
Cpd(ff)
F.fG H z)
49.556
1.9
163
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7.2
LINEAR TEMPERATURE MODELS
When plotted versus temperature, the intrinsic circuit model parameters display
linear trends. However, it is instructive to first consider the variation o f the gate-tosource threshold voltage, V*. The threshold
I ds versus
is defined here by the intercept o f the
plot for the PHEMT and the square root o f I
dyersus V
MESFET. Figures 44 and 45 illustrate the temperature dependence o f
Jpr the
for the subject
MESFET and PHEMT at V ds = 3V. Figure 44 shows that as the Shottky barrier height
decreases with increasing temperature, the threshold voltage becomes more negative with
increasing temperature. These results for
are agreeable with other published results
[ 8 ]. MESFETs with higher doping densities exhibit less variation than shown in Fig. 44
[ 8 ]. In contrast to Fig. 44, Fig. 45 illustrates a step-like shift in the threshold voltage
-1.05
-
1.1
*N
Vd* (V)
■ 2.5
#3.5
- - - • LinearTrend
Linear Trend
a
-1.15
-
AVth = 260 mV
1.2
-1.25
-1.3
-1.35
AVth = 277 mV
-1.4
-1.45
-60
-40
-20
0
20
40
60
80
Temperature (°C)
Figure 44
Linear trend of the measuredthresholdvoltage V * (V) versus Temperature (°C) for
the MESFET A l, as measuredon a SUMMIT probe station. Data represents 1.85
mV/°C variation for V*.
164
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
versus temperature that is characteristic o f trapping in GaAs HEMTs and PHEMTs. In
AlGaAs/GaAs HEMTs a threshold voltage shift is commonly related to the ionization o f
deep trapping levels (generally referred to as D X centers [143]) with increasing
temperature. For InGaAs channels these shifts in
are related to trapping at the
AlInAs/InGaAs interface [144], The D C -IV data for both the MESFET A l and PHEMT
A2 were obtained on a SU M M IT RF probe station and the sample FETs were not
illuminated during the measurement to avoid possible persistent photo-conductivity
related effects. As a result o f these measurements, electron trapping poses some
difficulty in modeling these FETs over a wide range o f temperature. I f such a model is
desirable, then a piecewise linear fit o f linearly temperature dependent models above and
below the trap activation energy is useful.
Vds(V)
-
-* •2 .5
1.1
-
1.11
-
1.12
>
-1.13
0
-1.14
-•-•3 .5
AVth * 51 mV
-1.15
-1.16 AVth *1 0 1 .6 mV
-1.17
-1.18
-60
-40
-20
0
20
40
60
80
Temperature (°C)
Figure 45
Piece-wise linear trend o f the measured threshold voltage
(V) versus
Temperature (°C) for the PHEMT A2, as measured an a SUMMIT probe station.
Data represents less than 0.2 mV/°C variation of above 0 °C.
165
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
190 r
180 - *
170 r
'* ----160 150 I140 I130 iW=300um
120 I- Vds*3V, Vg**-0.4
110-k
.
* -4 > .
Vg**-0.6V
v
«3... ' Jr' — ^
jlt l N C W * * !
CO
E
E
O)
70 I60 j50 r
40 ^
Figure 46
,,
d” n - a N * ---------
42
40
38
36
34
32
30
28
26
24
22
J.
0
1
N
Parameter Legend:
▲ FtJUSF
——•Linear Trend
□ gmJUSF
- - — Linear Trend
-•fr-gm Summit/PHEMT
••■*•• FtjSummit/PHEMT
O gm Summit/MESFET
♦ FtjSummit/MESFET
Linear Trend
Unear Trend
-40 -20 0 20 40 60
Temperature (°C)
Experimentallyextracted ^ (mS) and Ft (GHz) versus temperature (Cel.) for
MESFET A l and PHEMT A2 measured on a SUMMIT probe station over -55 aC
to 85°C. Additional PHEMT A2 data measured at USF illustrates linear trend of
data from 25°C to 85°C.
Figure 46 plots the transconductance and unity current gain frequency versus
temperature for the MESFET A l and PHEMT A2. This data spans a -55°C to 85 °C
range for models extracted from S-parameters measured on a SU M M IT probe station.
The bias conditions in the plot are for V ds = 3V and 50% Idss for both FETs. The
decrease in gm indicates a reduction o f the electron saturated velocity with increasing
temperature. Additional data measured at USF is plotted to illustrate the linear trend in
the extracted circuit parameters versus temperature over the range 25 °C to 85°C . This
comparison also illustrates the need for a piece-wise linear model for FET A2, due to the
166
4
________________
_____ ___
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step-like threshold voltage shift displayed in Fig. 45.
Confidence in the linear temperature model is supported by the linear correlation
coefficient, r, o f the thermal model to the extracted data. Table 11 lists the r-values for
sample A2 obtained over a 25°C to 85°C temperature range at several drain and gate
bias conditions.
Table 11
1
o
N)
v„(V )
-0 . 2
-0 . 2
-0 . 2
pi
00
-1
-0 . 6
oi
-0 . 2
Linear correlation coefficient, r, for the thermal coefficients o f the intrinsic
FET small signal model elements and L . o f PHEMT A2.
Tau
Vd,(V ) IriT
cri,
Ri
Crfr
I
-0.99 -0.96 -0.90 -0.63
0 .8 8
-0.73 -0.94 0.93
-0.99 -0.97 -0.93 0.98 -0.89 -0.98 -0.93 0.94
2
-0.98 -0.97 -0.93 0.96 -0.94 -0.98 -0.94 0.93
3
4
-0.99 -0.97 -0.93 0.97 -0.96 -0.98 -0.96 0.94
0.57 1 . 0 0
4
0.45 -0.97 -0.76 -0.97 -0 . 6 8
0.49
4
-0.26 -0.99 -0.97 -0.98 -0.79
0.87 -0.98 0.96
4
-0.67 -0.98 -0.96 -0.30 -0.92 -0.91
-0.95 0.92
4
-0.91 -0.97 -0.95 0.93 -0.94 - 1 . 0 0
-0.98 0.92
4
-0.99 -0.97 -0.93 0.97 -0.96 -0.98 -0.96 0.94
The r-values show the linear model to be highly accurate for most bias points modeled.
Often, as with Rjs near pinch-off, the thermal coefficient is negligible (see Fig. 39) and
a low r-value results. The linear correlation coefficient is not well-suited to conditions
where the slope is zero. Similar discrepancies occur in Table 11 for Id, near pinch-off.
At lower
biases near pinch-off, the threshold voltage is approximately equal to V gs,
and since 1 ^ is a function o f the difference between Vg, and Vth, a shift in
can cause
Ids to either increase or decrease. Couple this effect with the decrease in vMt and what
results are bias points where the temperature coefficient o f Ids, for example, is zero.
167
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iI
!
7.3 MODEL THERMAL COEFFICIENTS
The thermal variation o f the noise model coefficients has not been widely
published except for specialized cryogenic applications [IS ],[ 1 1 ] and proprietary models
[145]. In response to increasing interest in noise performance above 300 K , Lardizabal
et. al. [146] presented a technique that concurrently extracts small signal models and
noise models from 298 K to 373 K. The relevant parameters for noise modeling include
the noise coefficients P, R and C or Tg and Td and the small signal model elements gm,
Ri and R ds. In comparison, the capacitors C p C dgand C dsand the time constant ?
typically vary by an order o f magnitude less compared to the dominantly temperature
sensitive elements such as gm.
However, the extrinsic model elements do have
comparable thermal coefficients and these are discussed in more detail before the intrinsic
parameter results are presented.
7.3. 1 Extrinsic Small Signal Model Thermal Coefficients
The “cold” modeling techniques presented in Chapter 5 assume bias-independent
extrinsic small signal model elements.
However, the extrinsic element values are
thermally sensitive. Increasing temperature reduces the low-field mobility in GaAs,
which results in larger parasitic resistances. For the reactive parasitics the thermal
variation may range widely.
The wide variation is due to the repeatability o f the
measurement contact between temperatures, which directly affects the values o f the
reactive parasitics. For example, as temperature is increased, the substrate and thermal
chuck expand upward towards the RF probes. The resulting overtravel o f the probes in
the z-direction, induces further inward movement or “skating” o f the probes toward the
168
t
(
!
i
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FET. Excess amounts o f skating (> 4 mil) may occur for large temperature excursions
(-65°C to 12S°C). Since this may damage the RF probes, it becomes necessary to lift
the RF probes from the wafer surface allowing the chuck and FET to temperature
stabilize.
The temperature coefficients o f the extrinsic inductors and capacitors for FETs
A l and A2 are listed in Table 12.
Table 12
Al
Element
Is
Id
lg
cpg
end
A2
Element
Is
Id
Table-model coefficients m and b, linear
correlation coefficient r and thermal
coefficient P for FETs A l and A2.
m (/°C)
b1
r
0 no-3/°a
-0.006
-0.549
-0.345
-0 . 0 0 2
-0 . 0 0 2
m f/°C )
3.008
72.196
54.726
30.709
30.709
bl
-0.587
-0.920
-0.979
0 .0 2 1
-2.005
-9.389
-7.489
-0.055
-0.055
r
Bao-3/°a
2.567
36.725
27.233
31.367
31.367
-0 . 8 6 6
-0.997
-0.219
-0.429
-0.429
-2.439
-6.365
-2.608
-1.545
-1.545
-0.007
-0 . 2 0 2
-0.067
lg
-0.047
cpg
-0.047
end
1L (p H ),C (fF )
0 .0 2 1
Here the probes remained in contact with the wafer, and an inward movement o f the
probes resulted in negative thermal coefficients for the parasitic inductors. Otherwise,
these thermal coefficients may vary randomly according to placement repeatability. The
parasitic capacitors w ill also display thermally induced variation due to probe skating or
placement repeatability, and to a lesser extent due to changes in the substrate dielectric
169
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constant. The thermal coefficient for the dielectric constant o f GaAs is positive, p6r
~ 1 .0 * I0 't/K [8][78]. Although the increase o f 6 r reduces capacitance, its effect upon the
parasitics Cpg and
is less than the thermal coefficient observed in Table 12 for the
capacitors o f FET A2, but er variations alone appear to explain results for FET A l.
The thermal coefficients o f the drain and source resistances o f the three subject
FETs are plotted in Fig. 47.
These values are in good agreement with other recent
studies for MESFETs and PHEMTs [ 8 ], [15], [147]. Comparing the MESFET A l with
the heterostructures A2 and C l, the thermal coefficients for R , and
show less than half
the thermal variation in A l than they do in A2 or C l. This effect is expected due to
ionized impurity scattering in the MESFET, which helps to offset a negative thermal
coefficient due to lattice scattering [34]. In comparison, the source and drain resistances
in PH EM T A2 are dominated by lattice scattering for the range 298 K to 358 K
70
60
p
50
co* 4 0
o
^
30
&
20
10
0
Figure 47
Thermal coefficients, p (10-3/°C), for the parasitic resistors of FETs A l, A2 and Cl
as determined by a linear fit of extracted values for
25°C s T £ 85°C.
170
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represented in Table
1 2
.
The parasitic gate resistance shows a positive thermal
coefficient similar to those o f other modem sub-micron FETs.
7.3.2 Intrinsic Small Signal and Noise Model Thermal Coefficients
While some physical correlation o f noise temperature coefficients Tg and Td have
been reported at room and cryogenic levels, these results are often broadly interpreted
over bias and temperature. The variation o f the noise coefficients P, R and C or Tg and
Td are related to both these physical effects and inter-related to variations o f g,* R * and
Ri- All o f these correlation make interpretationo o f physical relations difficult. To a first
degree, variation o f the small signal model elements are the result of the reduction o f
both Eg and pQwith increasing temperature, and these effects can be interpreted in many
o f the results that follow.
In this section, results are presented to show the
experimentally extracted thermal variations in the intrinsic small signal model parameters
and the intrinsic noise generators.
The intrinsic model elements are expected to be well behaved functions o f bias
and temperature. While the following results are in agreement with theory, several
considerations are o f technical interest for noise modeling. First, is Tg equivalent to Ta
within the limitations on measuring Rj? Secondly, is Td easily interpreted as a proportion
o f the ambient temperature at all biases? Finally, is the correlation (or lack thereof) o f
gate and drain noise reflected in the thermal variation o f Tg and Td? The extracted model
results presented here address these questions.
171
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Some lesser temperature dependencies were also investigated in this work.
Compared to g„ R * and Rj, the gate-to-source capacitance is o f interest as
and gn
describe the unity current gain frequency, ft. Modeling the normalized noise correlation
coefficient C, was also considered, but since C is not used to relate the noise
temperatures Tg and Td, the complete extraction o f the four parameters P, R, Re[C] and
Im [C] requires more modeling effort. So one conclusion o f this work is that the noise
temperature model, which is equivalent to the noise generator model, is preferred for
temperature dependent modeling due to its practicality. In the discussion that follows,
the normalized thermal coefficient, or P value, o f Eq. ( 6 8 ) is calculated for each element.
Results for R* R ^, gm Cgs, Tg and Td are presented for FETs A I, A2 and C l below.
7.3.2.1 GaAs MESFET Thermal Coefficients
Thermal coefficients for the GaAs MESFET A l show a strong V gs and
bias
dependence for ^ and R^, as shown in Figs. 48 (a) and (b). These elements also show
a similar decrease in their thermal coefficients as Ids approaches I dss. The intrinsic
resistance R{ shows a flatter V gs bias dependence than these elements, but its thermal
coefficients are increasingly positive with increasing V ds- In contrast, Cgs is a slowly
increasing function o f temperature for most bias points. The drain bias dependence o f
gm and R ^ agrees well with the degradation o f vMt as Ids approaches Idss.
A large positive change in both Tg and Td with increasing temperature is related
by the positive thermal coefficients in Figs. 49 (a) and (b). As with the small signal
elements, the thermal coefficients show an inflection near Vgs = -0.2 V, and in this case
reduce to a negligible amount. Most notably, PTd is a strong function o f V ds while PTg
172
i
I
l
b
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shows little variation with the drain bias at all V& potentials.
7.3.2.2 GaAs PHEMT Thermal Coefficients
Thermal coefficients for FET A2 are illustrated in Figs. SO and 51.
The
transconductance o f A2 is found to linearly decrease with temperature over the bias
plane, where the amount o f change increases as Ids increases with
and V gs. As with
A l, Cgs is a slowly varying function o f temperature and PCgs shows little bias dependence
in comparison to gm. The negative thermal coefficient for Cgs is similar to that observed
in other works[148],[l 1 ] and is explained for the PHEMT in part by parasitic conduction
in the supply layers with increasing temperature. The thermal coefficient o f R js for A2
is also a slowly varying function o f temperature, which experiences zero temperature
coefficient points both near pinch-off and at Vgs=-0.2 V where gm saturates. Rj shows
a near constant gate bias dependence except for Vds = IV , where the D C -IV plane is
approaching the ohmic conduction region. In contrast to A l, the noise temperatures o f
A2 do not experience the large temperature variations closer to pinch-off.
173
!
{
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
0
-0.6
Vds (V)
-0.4
-0.2
Vgs (V)
(a)
-
______
•1 >0
Q.
Vds (V)
cn
9
-5 6
•••••••>
-7
-9
-
0.8
-
0.6
-0.4
-
0.2
Vgs (V)
(b)
Figure 48
Intrinsic model element thermal coefficients p (10-3/°C) for MESFET A l (a )^
and Cg, and (b) and versus Vg, (V) for several V j. biases.
174
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Vds (V)
2 0
O
«o
i
o
CO.
0.8
0.6
0.4
-
0.2
0
Vgs (V)
(a)
30
Vds (V)
2 2
CO
I
o
CO.
-10
-
0.8
-
0.6
-0.4
-
0.2
0
Vgs (V)
(b)
Figure 49
MESFET A l thermal coefficients p (l0-3/°C ) of noise temperatures (a) Tgand (b)
Tj, versus Vg, (V) for several V * biases.
175
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Vds (V)
?*;swwn»
2
3
4
-
0.2
Vgs (V)
24
20
oo
16
-0
c*r
i
o 12
S
ax
.5
a.
Vds (V)
8
4
-1
-0.8
-0.6
-0.4
-0.2
Vgs (V)
(b)
Figure 50
Intrinsic model elementthermal coefficients P (10-3/°C) for PHEMT A2 (a) ^ and
Cg, and (b) Rj and R*, versos Vg, (V) for several VA biases.
176
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
1 2
o
0
«■
1
o
8
Vds (V)
W
- \
*
«
4
* i
p
CO.
0
-4
0.8
-1
-
0.6
0.4
0.2
Vgs (V)
(a)
1 2
1 0
o
0
Vds (V)
8
CO*
1
o
p
ea.
6
4
2
v*
0
1
-
0.8
0.6
0.4
0.2
Vgs (V)
(b)
Figure 51
PHEMT A2 thermal coefficients P (10-3/°C) of noisetemperatures (a) Tgand (b)
T* versus Vg, (V) for several VA biases.
177
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I
j
7.3.2.3 InP H EM T Thermal Coefficients
FET C l also shows little gate bias dependence for PCgs, which is small and
positive. Both gmand
are slowly decreasing functions o f temperature for most gate
biases. In contrast to A l and A2, Rj o f C l is a strongly decreasing function of
temperature from pinch-off to zero applied gate bias. The bias dependence o f the thermal
coefficients fo r Tg and Td are similar to those o f the PHEMT.
7.3.3 Discussion o f Noise Temperature Thermal Coefficients
Thermal coefficients for Tg and Td are bias dependent, increasing functions of
temperature for both the MESFET and HEM T technologies. The linear variation o f Tg
described by Pospieszalski over temperature would correspond to a thermal coefficient,
Ptp equal to 3.33x1 O' 3 /°C . The deviation from this dependence can be accounted for
by the differences in the variation o f the transconductance, gn , and the channel
resistance, R*. For example, Fig. 52 (b) illustrates that the variation o f R{ for the
PHEMT, A2, is small compared to the change in g mwhich has a negative P coefficient
that increases with increasing current levels as gmsaturates. Similar effects occur for
FET A2, with the greatest change in g,„ occurring near pinch-off. Other than biases near
pinch-off (where the noise figure may degrade rapidly with bias) the thermal coefficient
results presented here yield a range o f possibile variations o f Tg with the ambient
backside temperature, such that 0 < Pt* < 8 -
178
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o
0
Circuit
Parameter
1
O
- - - Cgs
-10
-12
-
0.6
-0.5
-0.4
-0.3
-
0.2
Vgs (V)
(a)
14
oo
<rT
o
TK
CQ.
i.
O
O)
1 0
Noise
Coefficient
6
2
2
Vds=1 (V)
-
0.6
-0.5
-0.4
-0.3
-
0.2
Vgs (V)
(b)
Figure 52
Intrinsic model element thermal coefficients 0 (l0-3/°C ) for HEMT Cl
(a) g„ and C^Ri and Rj„ and (b)Tgand Tdversus Vg,(V) for V j, 1 (V).
179
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!
i
To address the observed temperature dependence o f the drain noise temperature
the drain noise coefficient, T j, is found to be related to P by the open circuit voltage gain
gm/gds, such that [ 1 1 ],
Figures 53 (a) and (b) shows the correlation g^/g* versus Cgs/C gd for A l, A2 and C l at
T=25 °C and 85 °C.
With respect to Figs. 53 (a) and (b) the following bias dependencies are noted.
First, an increase o f the ratio
is observed in A l and A2 as V p is lowered (greater
IdJ compared to C l which displays a minor decreasing change in C JC # for V9 < -0.4
V. Relating this to the FET correlation,
C l modulates charge more efficiently than
A l or A2 for increasing I* . Furthermore, C l shows little temperature variation with
respect to
for V&< -0.4 V. While the ratio g jg * for C l does decrease for V p
< -0.4 V, the relationship between gjg* and CJC# yields a low pK ratio o f less than the
value o f V& reported by Kohn [44], For Vp < -0.4 V, C l achieves its lowest noise
condition, which is advantageous because the ft o f C l is larger than in a more negative
gate bias range. In comparison to C l, FETs A l and A2 show a correlation ratio that is
optimally one third at much greater reverse biases corresponding to ~ 15% to ~20% o f
Id*, respectively. At smaller negative Vp biases, FETs A l and A2 do not maintain an
optimal charge modulation efficiency and the parasitic effects o f
and R * cause PKto
increase.
180
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2
. i r r r r n ‘n
1 0
9
*
8
7
■o
a>
(0
a>
O
9nV9ds
4
5
3
i i r rr r n
6
7
8
i i
T*
9
n-T
1
A1 25C
A185C
C1 85C
C1 25C
6
-0.3
-0.4
^r'-0?2 f 4 -0.5
/ /
^ > - 0.6
5
4
3
*♦"-0.7 Vgs
2
1
■1.1 a I Li-I J. L t-u iU ^ u l
■
0
6
7
1 L l i
i I. I
1 t _» i
8
9
9m/9ds
Ifah Ull. XLJ-U d-Ufa
10
11
12
13
(a)
30
•
*
25
A2 25C
A2 85C
Vds 4 V
• -0 . 2
4 -0.4
■D
O)
J
M
D)
J
2 0
,3 V •
15
4 - 0.6
1 0
V 0 -0 .8
Vgs
5 ^1V
0
0
5
1 0
15
9m/Qds
2 0
25
(b)
Figure 53
Influence ofbias and temperature on extracted correlation of gjg& versus C^/C^
for (a) FETs A l and C l and (b) FET A2. Two temperature data sets include 25°C
and85°C.
181
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Figure 53 (b) in particular illustrates a decrease in gg/g* which is appreciable to
the amount o f variation in the noise temperature Td. Similar responses are seen in FETs
A l and C l for thermally induced variation o f gg/g*. The observed variation o f the gg/g*
versus
plot for A2 is greater than for A l or C l appears to correspond w ith the
larger channel current density in A l. As a result, the thermal variation o f the noise
temperature Tdis observed to be dominated by an increasing value o f the noise coefficient
P with increasing temperature only below the gate bias range at which the thermal
variation o f gg/g* becomes an appreciable component o f pxd.
7.3.4 Noise Temperature Correlation
The noise temperature coefficients Tc amd Td relate the “effective” thermal noise
o f the two uncorrelated resistors (R| and
to the correlated generators e ^ and idn.
As proposed by Pospieszalski, the noise temperature Td is expected to represent purely
uncorrelated noise in the drain o f the F E T [ll]. I f this is so, little correlation should be
expected between the thermal variation o f Tg and Td. As noted in the beginning o f this
•
PTd(10-3/K) 1
•
0.8
PHEMT A2
• A2 M s
-------Linear Trend
04.
U.Z
i
•
. i*
0.2
-0.4
f
0.4
------- lj
0.6
0.8
*
t
P T|(10-3/K)
-0.6
5).8
Figure 54
Correlation for thermal coefficients of noise temperatures Tgand Tdover bias for
the PHEMT A2. Solid line represents linear trend for all bias points
182
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
0.8
MESFETA1
▲ A1 Data
Linear Trend
0
.6
-
-
0.4 -
-0.4 -0.2,
■0.2 k
-0.4
Figure 55
Correlation for thermal coefficients ofnoise temperatures Tgand Tdover bias for
MESFET A l. Solid line represents linear trend for all bias points.
section, a comparison o f the thermal variation o f noise temperature coefficients Tg and
Td is readily tabulated as output o f the table-based noise model. Figure 54-56 below plot
the normalized thermal coefficient for temperatures Td and Tg against each other. The
data points represent thermal coefficients for Tg and Td at each DC bias point measured.
Regarding the possible partial correlation o f drain noise to the gate, the observed
temperature coefficients pXg and pTd (for T g and T a) should be about the same. This
trend is not seen in the values for PTg and P xd shown in Figs. 54 and 55 respectively.
Exact agreement is not expected since only partially correlated drain noise was observed.
183
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
PTd(10-3/K)
::
HEMTC1
■ C1 Data
Linear Trend
0.2 0.4 0.6 0.8
-0.6 -0.4 -0.2
-
0.2
-
1
PTg(10-3/K)
- 0 .4 -
Figure 56
0.6 *
Correlation for thermal coefficients ofnoise temperatures Tgand Tdover bias for
HEMT C l. Solid line represents linear trend for all bias points.
7.4
SMALL SIGNAL MODEL PERFORMANCE
Bias and temperature dependent S-parameter simulation o f FETs, A l, A2 and C l
are demonstrated here. In the simulations to follow, the linear temperature model and
the table-based interpolation scheme set the FET model parameter values. For the
following demonstrations, several gate biases are swept at two temperatures. The drain
bias is fixed for these examples to simplify the display and comparison of measured and
modeled performance. However, the results are typical o f other V ds bias points in the
saturated region o f the FET D C -IV curve. The baseline frequency range o f models
developed for these results is from 2.0 to 18.0 GHz, an extended frequency range o f data
up to 67.5GHz is also included for further verification.
184
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II
!
The S-parameters o f MESFET A l are compared first. Figure 57 shows the
measured 25 °C S-parameters as symbols and the simulated values as lines. The scale
factors for S2 1 and S1 2 are included on the same unit dimensioned polar plot. A similarly
good agreement between the model and data is displayed in Fig. 58 for the same FET at
a baseplate temperature o f 85°C. Further comparisons o f small signal models for
heterostructure FETs are displayed in Figs. 59-62. The PHEM T A2 o f Figs. 59 and 60
also illustrates a good fit o f the model to data measured out to 26.5 GHz for a model that
is extracted from 18 GHz S-parameters. Finally, results for HEMT C l are compared in
Figs. 61 and 62.
Overall, the results show excellent agreement between the bias
dependent S-parameter data and the table-based model at both 25°C and 85°C. In each
case, the percent difference in each of the measured S-parameters is less than 5% for any
real or imaginary component.
185
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
90
60
1 2 0
S21
Sl2
x0.1
0.6
150
A 0.6 0.8
S22
2 1 0
240
300
270
Frequency 2.0 to 18.0 GHz
Figure 57
Comparison of 25°C measured andmodeled FET A l S-parameters. V * is 3V and
Vp is swept at -0.2 V (squares), -0.4 V (stars) and -0.8 V (circles).
90
S21
60
1 2 0
S12
0 .8
xO.1
150
0 -6
ft'
.4
180
0 .6
0 .8
S22
330
2 1 0
240
300
270
Frequency 2.0 to 18.0 GHz
Figure 58
Comparison of 85°C measured and modeled FET A l S-parameters. V * is 3V and
Vp is swept at -0.2 V (squares), -0.4 V (stars) and -0.8 V (circles).
186
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
270
Frequency 2.0 to 18.0 GHz
Figure 59
Comparison of 25 °C measured andmodeled FET C l S-parameters. V^is 1V and
V? is swept at -0.2 V (triangles), -0.4 V (squares), -0.8 V (stars ) and -1.0V
(circles).
90
1 2 0
©
3 .1
xO
.0 ,8
0 .6
150
0.4
180
U
0.4_0.6_0.8
330
2 1 0
240
300
270
Frequency 2.0 to 18.0 GHz
Figure 60
Comparisonof 85 °C measured andmodeled FET C l S-parameters. V * is 1V and
V? is swept at -0.2 V (triangles), -0.4 V (squares), -0.8 V (stars) and -1.0V
(circles).
187
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
1 2 0
Szi
S 12
0 .8
0 .6
150
.0.4
.4 0.6 0.8
180
S22
330
2 1 0
240
300
270
Frequency 2.0 to 26.5 GHz
Figure 61
Comparison of 25°C measuredandmodeled FET A2 S-parameters. V * is 3 V and
Vg, is swept at -0.2 V (stars), -0.4 V (squares), -0.6V (triangles) and -0.8 V
(circles).
90
S21
1 2 0
S12
0 .8
xO.1
0.6
150
0.4
180
0
0
.
.4 0.6 0.8
S2 2
330
210
240
270
300
Frequency 2.0 to 26.5 GHz
Figure 62
Comparison of 85°C measured andmodeled FET A2 S-parameters. VA is 3 V and
V? is swept at -0.2 V (stars), -0.4 V (squares), -0.6 V (triangles) and -0.8 V
(circles).
188
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
To further demonstrate the linearly dependent bias and temperature models,
Fig. 63 compares simulated S-parameters for FET A2 versus data representing a bias and
temperature not directly tabulated during the model extraction process. In addition, note
that this test includes frequency extrapolation o f the model versus data measured out to
67.5 GHz.
90
120
S21
S12
0.8
x 1/7
x6
0.6
150
>°/_ JP-2 0.4 0.6 <0.8
180
S22
S 11
210
330
240
300
270
Frequency 2.0 to 67.5 GHz
Figure 63
Comparison of 45 °C measured and modeled FET A2 S-parameters. V* is 3 V and
Vp is -0.7 V. Simulated values are indicated by lines and symbols represent
measured S-parameters.
189
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The measured and modeled S-parameter comparisons show that the models
attracted here represent the data well over a range o f bias and temperature. However,
this does not mean a unique solution for the model parameters has been found. In fact,
many o f the model elements are known to be correlated to one another, as for example,
the intrinsic transconductance depends on the calculation o f the source resistance.
Similarly, the components o f the measured S-parameters can be viewed as correlated
quantities. For example, the forward gain is highly correlated to the magnitudes o f the
input and output reflection coefficients.
To gain further insight into the model’s
agreement with the data, the following correlations were studied,
(1)
Inter-correlations o f the components o f the measured S-parameters, which are
denoted as rn.
(2 )
Inter-correlations for the modeled S-parameters, denoted r^.
(3)
Correlation o f measured versus modeled components.
The final correlation, (3 ), results from plotting the components o f rn versus r^. This is
shown in Fig. 64 for FET A2. The linear correlation coefficients o f the components of
and r ^ listed in Fig. 64, result from the plot in Fig. 64. As listed in Fig. 64, ryy
correlates with
to a high degree for all o f the S-parameter components.
190
i
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
rxx
T 1.5
■1
-0.5
-1.5
0.5
1.5
• - -0.5
Linear Correlation
Re[S11] 0.999
lm[S11] 0.997
Re[S12] 0.993
lm[S12] 0.994
Re[S21] 0.988
lm[S21] 0.991
Re[S22] 0.994
lmfS221 0.972
--1
Figure 64
Correlation of measured S-parameter correlations,
and modeled S-parameter
correlations,
for FET A2 at a low-noise bias point with T=300 K.
7.5
NOISE PARAMETER SIMULATION RESULTS
This section demonstrates the bias and temperature dependent simulation o f FET
noise parameters. These results follow the same bias and temperature conditions used
in the S-parameter comparisons. Figure 65 displays a comparison o f measured to
modeled noise parameters for the HEMT C l at 25°C. Each plot represents the frequency
dependence o f the four noise parameters Fmin, r„, Ropt and
at a particular bias
condition. A legend in each plot also designates the symbols used to represent data and
line types used to represent the model. Equally good agreement between the data and
the model are displayed at a baseplate temperature o f 85°C for HEMT C l in Fig.
6 6
.
Measurement errors in Fig. 65 (b) for Fmin at frequencies below 6 G Hz cause the
191
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
only appreciable differences in these comparisons. The measurement sensitivity is
approximately 0.2 dB, so errors such as this are common for Fmfn in the lower microwave
frequency region. That the data is in error can be deduced from the quality factor kt
described in Chapter 3 of this work. In contrast, the modeled F ^ is not skewed by these
bad data points and it therefore serves as a useful tool in extrapolating noise performance
to these lower microwave frequencies.
Comparison o f measured and modeled performance for FET A2 is shown in Fig.
67 (a) as a function o f bias for T=55 °C. The bias plane simulated for FET A2 covers
IV s V * ^4 V and -1.0 V s V p $ -0.2 V. Figures 67 (a) and (b) compare F ^ and
respectively, but these plots also illustrate another useful aspect o f the table model.
Figures 67 (a) and Fig. 67 (b) combine to show the data required to perform a trade-off
analysis between noise and gain. By design, the table model incorporates bias and
temperature into the trade-off analysis. Modeled contours o f F ^ and
plotted in the
Vp - plane relate the bias sensitivity o f optimal bias points for F,,*, and G ^ .
192
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
vx^i.ooo
vgsMis
.
-&VOO
0
Ropt.Xopt
Fmln (dB), rn (Ohms)
V8— 0.7
<>ooo0 ''a-<y-0j ►
o o
>®53"80
^***>*yggc
6
8
10
12
Frsquancy (GHz)
(b)
><x o mm x «• vto*i.o(V)
+ !■ Va»»-0.3
— to
120 X
6
8
10
12
6
14
8
10
12
14
Frsqusncy (GHz)
Frequency (GHz)
(d)
(C)
Figure 65
to
Ropt.Xopt
Fmin («®), f n (Ohms)
O
Measured (symbols) and modeled (lines) noiseparameters r„,
and
versus frequency for the HEMT C l at four Vg, biases with V * =1V and T=25°C.
Modeled results represent performance of a table basedmodel simulation.
193
•<
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
o
2
nhw
Ao
\
x
v a » i.0 (V )
+fit Vj^-o.7
O WMN
O *
*
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V d ^ t.0 (V )
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Ropt 1%opt
(cunio) “i *(9P) “(‘“d
4
OW
—r
'1 5 0
4-+I | | | I I IfrfrVsUOJl-
05 -
!6 0
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6
8
10
12
0
14
16
6
18
8
(a)
O NFMN
O «H
x
10
12
14
16
Fraquancy (GHz)
Fraquancy(GHz)
(b)
Ml* Vd»»1.0 (V)
+ Mq Vg^O.5
x
O
o
MM
*h
X Uk
+ Ana
va»*1.0 (V)
V ga^O.3
o
(SUIMO)
Ui ‘(ap) UIU
Jj
Ropt 1Xopt
120 X
0
6
8
10
“Oo
12
6
Fraquancy (GHz)
(C)
Figure 6 6
8
10
12
Fraquancy (GHz)
GO
Measured (symbols) andmodeled (lines) noise parameters Tm
and
versus frequency for the HEMT C l at four Vp biases with = IV and T=85°C.
Modeled results represent performance of a table based model simulation
194
•r
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Fmin
(dB)
-0.4
-
VdS (V)
0.6
Vgs (V)
“° * 8
Gmax (dB)
-
Vds (V)
Figure 67
* ° - 8
0.6
Vgs (V)
Comparison of simulated FET A2 (a)
(dB) and (b)
(dB) versus Vg, (V)
®>dVd,(V)atT=85 °C. F,,^ differences are within ±0 . ldB over the bias plane.
195
f
I
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
As with the S-parameters, further verification o f the noise model is presented at
frequencies beyond the baseline 2.0 GHz to 18.0 GHz range. Using a room temperature
noise parameter measurement system with an upper frequency lim it o f 26.0 GHz, several
(n=5) FETs o f types A l and A2 were measured at Hughes Aircraft Company. The
measured minimum noise figure is compared with the developed models in Figs. 6 8 and
69 for FETs A l and A2 respectively. In each case the fit to the extended data set is
good.
Unfortunately, higher frequency data is difficult to obtain, but the trends
illustrated here suggest that the model may bypass the need for such systems except for
verification purposes. To help gain a better understanding o f the frequency scaling
capability o f the models developed in this work, the next section compares several figures
o f merit.
3.5
S ' 2.5
TO
C
E 1.5
u.
Y-Maan
Y-Maan
Im5h1a j
ImShlcJ
0.5
0
Figure 6 8
5
10
15
20
25
Frequency (GHz)
30
35
40
Comparison ofmeasured and modeled
(dB) versus Frequency (GHz) up to 26.0
GHz. Modeled data represents the PHEMT A2 model developed from 18.0 GHz
noise parameters of one typical FET. Measured Fminrepresents the mean, minimum
and maximumvalues for a sampling of five FETs from the same wafer.
196
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
2.5
03
-a
c
E
u_
Legend
0.5
Frequency (GHz)
Figure 69
7.6
Comparisonof measuredandmodeled
(dB) versus Frequency (GHz) up to 26.0
GHz. Modeled data represents the MESFET A1 model developed from 18.0 GHz
noise parameters ofone typical FET. Measured Fa*, represents the mean, minimum
and maximum values for a sampling of five FETs from the same wafer.
APPLICATION OF THE FET NOISE MODEL AT MILLIMETER-W AVES
Simulating the performance of a FET at frequencies beyond the range o f
measured data is valuable to the design engineer. However, without a model or data one
may resort to less sophisticated approximations o f performance.
approximation o f
Recently, an
demonstrated good agreement for a wide range o f FETs, and the
resulting database provides a useful comparison for the full circuit model developed in
this work. A simple approximation is to extrapolate the F,^ data linearly with frequency.
For a less crude approximation, Hughes [149] developed a relation based on the linearly
scaling of F ^ (expressed in decibels) up to frequencies approaching the maximum
frequency o f oscillation,
for MESFETs and HEMTs. The approximate expression
197
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
for
given by Hughes is written[147],
10
In (
1 0
(119)
)
where Tg and Td are fitting factors for the extrinsic FET, T„ is the ambient temperature
and fn is the figure-of-merit. Importantly, however, the fiill model is still desirable,
because it also simulates the remaing noise parameters required for matching network
design, namely R„ and
To further validate the powerful frequency extrapolation
capability o f the models developed in this work, Hughes’ approximation of F ^ is
compared to the circuit models for FETs A l, A2 and C l next.
There are several reasons to compare Eq. (119) against a circuit model. As noted
by Hughes, below Fm^ a variation o f Fmin from a straight line may imply several factors
including: ( 1 ) additional sources o f noise, such as leakage currents, (2 ) errors in the data
used to extract the models and (3 ) additional frequency dependent elements (or
distributed effects) that cause the data to vary from linear. Therefore, this study seeks
to compare Eq. (119) to the full circuit model, and if there is a disagreement to find if it
is due to a modeling error or a limitation o f Eq. (119). Figure 70 illustrates a comparison
o f the approximate expression for F ^ given by Eq. (119) and F ^ calculated by the
models developed in this work for FETs A l, A2 and C l.
Fitted values o f the
temperature Td in the approximate models for FETs A l, A2 and C l were 280 K, 540 K
and 470 K respectively. These values compare well with model temperatures published
by Hughes[149], which exhibit typical values of 500 K down to as low as 97 K.
198
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
7
6
CD
TJ
C
5
E
4
u.
O
>
N
-n
3
3’
3
"ql
k .
o
CM
00
2
<
1
T=298K
0
0
0
20
40
60
80 100 120 140 160 180
Frequency (GHz)
Figure 70
Comparison of (dB) versus frequency (GHz) for the simplified linear model
(lines) with the models developed in this work (symbols) for FETs A l, A2 and C l.
The frequencyresponse is shownup to F for a given FET.
Similar to Hughes’ work, a Tg value equal to 298 K was chosen to simplify the fitting in
each case. These results agree with those o f Hughes indicating that the approximate
expression for F ,^ Eq. (119), is useful up to frequencies approaching Fmax. Since no
major deviations are exhibited by the complete circuitl model, this lends credit to their
ability to extrapolate Fminversus increasing frequency. Hughes also notes that measured
F ^ data for some HEMTs increased with decreasing frequency below 4 GHz [149], and
that this behavior was not explained in published literature. This behavior is in fact well
defined by the model derived in Chapter 5 o f this work for gate leakage current, and was
shown to contribute to the good fit o f the model with data. A further advantage o f the
equivalent cirucit model is that it can simulate all of the noise parameters, not just F ^ .
The good agreement o f the model to the measurements shown in the comparisons
199
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illustrated here and in Section 7.4 illustrates the value o f the noise modeling alogrithm
for a FET-based low-noise circuit design at millimeter-wave frequencies. To emphasize
this value, Chapter 8 demonstrates the successful design o f such an application.
7.7 COMPARISON OF NOISE PERFORMANCE
Using the models developed in this work, a comparison o f each FET’s (A l, A2
and C l) minimum noise figure is performed. The figure o f merit used for this comparison
is the noise-to-gain ratio (NGR) described in Chapter 4. Furthermore, the tabulated
model allows for this comparison over a range o f measured temperatures (25 °C to
85 °C ). An interpretation of experimental results are given to qualify the NGR as an
unbiased estimator o f temperature dependent small signal and low-noise performance for
microwave FETs.
Figure 71 compares the NGR versus the percentage o f drain current flowing in
the FET channel for A l, A2 and C l. The low value o f the NGR for C l reflects its high
ft and low drain noise spectral density. In Figure 72, the value o f the Fukui noise is
computed from the noise coefficient P, where K f is 2 /P . This illustrates that the noise
coefficient or Kf is not a good figure o f merit by itself. Finally, in Fig. 73, the NGR is
compared at two temperatures for the same FETs. Figure 73 reflects the reduced
temperature dependence o f the In0 53 Ga0 47As/InP HEMT.
200
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
A1, A 2 V d s «3 V
C1 Vds®1 V
-09
A1
a:
Legend
- ■ * - A2 25C
- « ♦ - A1.25C
- - * - C 1 25C
*
0
z
A2
-10
20
40
60
80
100
% ldss
Figure 71
.
Comparison ofNGR (A/VUz/mm/Hz) versus %I(ta (mA) for FETs A l, A2 and Cl
at T=298 K.
^-09
10
(NGR with Kf marked at each bias)
u
*
2
0521^2*02
2.05
* «-02
1*37
1 3 7
q:
1.65
1.43
O
z
2.955
-10
1 0
1.91
- t i. 7 3 %1S P -#
1.581.64
1 5
FET Labels
- ■ * - A2 25C
A1__25C
C1 25C
A1, A2 Vds » 3 V
C1 Vds * 1 V
»
i
-1.1
-0.9 -0.7
-0.5 -0.3 -0.1
V g s (V )
Figure 72
Comparison ofNGR (A/SHz/mm/Hz), with values of the Fukui factor, KFmarked
at each data point, versus Vp (V) for FETs A l, A2 andC l at T=298K. NGR
values reflect performance potential that Kp does not relate by itself.
201
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
A1, A2 Vds = 3 V
C1 Vds * 1 V
-09
FET Labels
• C1_25C
• A1_25C
-♦•A 2_25C
C1JB5C
A1 85C
A2 85C
10
tr
o
±
-1.1
-0.9 -0.7 -0.5 -0.3 -0.1
V gs (V )
A1, A2 Vds = 3 V
C1 Vds = 1 V
10
-09
FET Labels
- C1_25C
- ♦ ■A1_25C
- » ■A2_25C
- A - C1_85C
- e - A 1 85C
A2~85C
a:
o
±
20
40
60
80
100
% ldss
Figure 73
Comparisonof NGR (A/VHz/mm/Hz) for FETs A l, A2 and C2 versus (a)
and (b) %I<taat T-25°C (closed markers) and T=85°C (open markers).
202
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(V)
i
r
i
7.8
CHAPTER SUMMARY
A bias and temperature dependent study o f the intrinsic noise model generators
associated w ith two prevalent FET noise models has been conducted. The significance
o f this work lies in the wide variation of bias, temperature and FET types that are studied
and modeled. As a result, the first published results fo r experimentally determined
thermal coefficients o f the gate and drain noise model coefficients T( and Tdare presented
This chapter presents new results for temperature dependent FET noise modeling.
The results presented for the experimentally extracted model show a linear temperature
dependent model performs well for both small signal and noise simulations. Furthermore,
the noise temperature model emerges as a practical form for the model since it requires
less coefficients to describe it.
While the results shown in this chapter provide a unique comparison o f key model
parameters and their temperature dependencies, these results also allow for interpretation
o f FET noise behavior based on comparisons o f results for differing FET technologies.
This is why the review o f FET semiconductor physics is given in Chapter 2. Specifically,
the FET C l, an InP based HEMT, shows the least temperature variation, because o f its
better material properties compared to the GaAs based FETs (A l and A2). These
properties include a high saturated carrier velocity and a large inter-valley scattering
energy-level difference.
203
•d
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
CHAPTER 8. THEORY AND MODELING OF FET BASED NOISE SOURCES
8.0
INTRODUCTION
The FET models developed in this work motivate new circuit applications. The
novelty and strength o f the model for use w ith new applications results because it
overcomes traditional limitations o f FET noise models. For example, most models
operate at one static D C -IV point at a specific temperature and over a limited frequency
band. Applications o f noise modeling are particularly more important at millimeter-wave
frequencies due to the difficulty in measuring noise parameters beyond 40 GHz. To
highlight the usefulness o f the model for such an application, the following chapter
presents a reevaluation and improved analysis o f a novel circuit: a FET-based noise
temperature source. Utilizing the developed models and a new theoretical description,
a novel variable temperature FET-based noise source circuit is described that
demonstrates record low-noise performance at K-band frequencies.
8 .1
AN IMPROVED THEORY AND MODELING OF FET NOISE SOURCES
In this section the bias and temperature dependent FET noise model is used to
design and simulate a novel low-noise FET circuit. The resulting circuit realizes an
electronically cold noise temperature, Tv at the input port. This is the temperature o f the
noise power exiting a matched port defined by Pn = kBTSB, where B is bandwidth as in
204
t
_
__
__
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
iI
j
Chapter 3. Temperature T( also refers to the blackbody radiation o f an object for
radiometric measurements. In turn, radiometric measurements are commonly calibrated
against natural objects which have well known "brightness” temperatures. Thus, the
novelty o f the described circuit is in electronically generating a range o f reference
temperatures, which has application to alternative calibration equipment and procedures.
Noise temperature references based on electronically controlled solid state
components are useful, but until now the temperature range o f such circuits has been
limited. For modem radiometric systems, the semiconductor diode is one means o f
electronically generating a hot reference noise temperature (» 3 0 0 K ). In contrast, FETbased circuits have demonstrated the capability to electronically generate a cold noise
temperature («300K ) at low microwave frequencies [150], [151]. The advancement o f
this latter capability for use at higher microwave and millimeter-wave frequencies was
previously limited by FET noise performance. This situation has changed over the last
decade due to the improved low-noise properties o f not only MESFETs, but also
heterostructure FETs. Therefore, the present work considers a renewed investigation o f
the performance limits for a FET-based noise source.
The primary motivation behind this work is the need for variable (at least two)
temperature noise calibration standards for microwave and millimeter-wave radiometry.
One calibration temperature is usually at ambient. The second temperature would best
be within, or near, the temperature range o f measurement interest. Typical brightness
temperatures measured by both ground- and satellite-based radiometers are illustrated in
Fig. 74. By developing a bias controlled FET noise source it is possible to generate (by
205
t
i
ij
•<
_
.
_
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Antenna
Brightness
Temperature
Radiometer with
Cold/Hot Source
V,bias
AMAZON
(350K-310K)
Tea,. (K)
ant (K)
. . Pre-Launch
Cal.
” O
g f/
&>
NEW ICE
(105K) '
COLO SKY
(2-7K) '
V
\
«r /
■-
/
*
/
/
0
-I
Potential' ' ■§
On Orbit - .
Agn
.
+ - I- - M
bias
Figure 74
tr
.. S
(V)
Schematic illustration o f a FET-based Cold/Hot noise temperature source
for radiometric calibration o f antenna brightness temperature. Sensed
brightness temperature at the antenna is output as a voltage, V0, by the
radiometer and converted into temperature, T ^ , which is calibrated against
the reference temperature,
, set by the novel integrated noise source.
stepping the bias voltage) a range o f calibration temperatures with one circuit. The
stepped Cold/Hot noise source is a simple device that can be located internally to a
radiometer or other low-noise receiver for calibration. Raytheon E-Systems and USF
have submitted two patent applications on this circuit that w ill potentially replace
complex, bulky external calibration mechanisms.
There are several reasons why an integrated electronic noise source is advantageous:
(1)
The electronically controlled noise source temperature eliminates the need
for sighting reference objects such as, forests, fresh water, cold-sky, etc.,
which can require the costly maneuvering o f a spacecraft or aircraft.
(2)
The device eliminates significant problems in spacecraft and/or aircraft
206
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
payload integration that currently require sky horns or large external cold
calibration feedhom reflectors and large heated targets (absorbers).
(3)
When mounted close to the antenna feed, the device can be readily
switched to the input o f the receiver to provide radiometer calibration,
receiver linearity measurement, noise figure measurement and it also
provides a Built-In-Test capability.
(4)
It allows for adaptive calibration time intervals so that the measurement
intervals o f earth can be maximized.
(5)
In addition to radiometric applications, the device is a candidate for onwafer standards since it is readily adaptable to M M IC integration.
Two areas o f study require improvement in the FET-based approach. These
include applying the developed FET noise model to improve upon previous design
approaches and to improve the theoretical description o f Tt. This work begins by
reviewing a previously used design approach for analyzing a FET-based noise
temperature source. Improving the theoretical description o f Tgis accomplished through
the use of an existing alternative set o f two-port noise parameters. A fter a review o f the
design approach and fabrication considerations, circuit level simulations of a hybrid
prototype are compared to measured results.
8.1.1 Assessment o f Previous Work
The concept o f using a one-port FET circuit as an equivalent cold noise source
was established nearly two decades ago [148]. Using a common source FET circuit with
the drain terminated, Frater and Williams demonstrated a T , o f less than 50K for the gate
207
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
port o f a hybrid circuit at a frequency o f 1400MHz. One other notable work explored
gate-to-drain feedback [149]. Results from that work were somewhat inconclusive and
failed to benchmark a working Cold Noise source circuit. Thus, until now, only limited
demonstrations o f FET Cold Noise sources at low microwave frequencies have been
reported. This work describes significant advances in the area o f theory, modeling and
design o f FET-based cold, as well as hot, solid-state noise sources. A related effort
establishes a new state-of-the-art prototype circuit [152] with a cold noise temperature
(—1 0 OK) in the 18-22GHz frequency range. Variability to over 1000K is demonstrated
through bias adjustment and the concept o f port switching.
The work o f Frater and Williams [150, 151] builds upon the even earlier work on
electronically cold RF tube circuits[153],[l54], but their work describes a design
technique to develop a FET-based noise source. The starting point for Frater and
Williams’ analysis is the application o f series feedback to the common source FET having
the simplified model o f Fig. 75 [150, 151]. Their analysis o f this model yields two sets
of equations[150, 151]. One set calculates a series inductance that achieves an optimum
Gate
Drain
•— ©
ng
Source
Figure 75
Simplified noise model of the FET used by Frater and Williams
208
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
noise match, and another expression finds the input mean squared noise current used to
calculate an equivalent noise temperature at the input port.
Their resulting noise
temperature is denoted, Teq, which is seen at the input o f the FET. Calculation o f T^ is
derived from the sum of the noise currents flowing in the signal source load at the circuit
input. The relation for Teq is,
r-
= '* '
w
(IM )
where R , denotes the system source resistance at the input port, / 2 denotes the mean
square noise current flowing in R , due to the FET noise generators in Fig. 75. In the
development that follows, the source inductance,
refers to that reactive impedance
added to the FET in Fig. 76.
gs
—
FET
DEVICE
INPUT
BATCH/
BIAS
as
OUTPUT
BATCH/
BIAS
FEEDBACK
INDUCTOR
^SOURCE
Figure 76
Basic topology for a FET-based noise source. The additional inductance
added to the source o f the FET is denoted L„
209
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The primary design equations from [150] describe the source matching resistance
as,
R t0urce
= ^
+
R n
(1 2 1 )
where Rn=R/gm, R denotes the gate noise generator coefficient[lO], gm is the
transconductance and
is a series feedback resistance. A noiseless, non-zero, series
feedback resistor, R ^is realized with reactive components as,
Rjb = 7 % - • j Source
(1 2 2 )
where C9 denotes the gate-to-source capacitance. The design approach develops the
optimum matching condition in Eq. (121) by applying series inductive feedback according
to Eq. (122). Some o f the drawbacks o f this approach include:
1.
A lack o f a gate-to-drain capacitance, which becomes important for higher
frequency simulations [139].
2.
A simplified model o f the drain side o f the FET that limits the ability to
assess circuit performance under differing port-two (drain-to-source)
loading conditions.
3.
A nodal analysis technique that is good for calculating noise currents, but
does not easily lend itself to conventional noise parameter expressions.
4.
A static FET characterization at one set o f bias and temperature
conditions.
210
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Ia contrast, an analysis with the bias dependent model developed in this work w ill
allow for a design o f a variable temperature source, which also satisfies items (l)-(3 )
listed above. Before proceeding with such an analysis, this work compares the desired
T , to Teq in terms o f an alternate set o f noise parameters, advanced by Engen and
W ait[155].
8
.1.2 Alternate Noise Parameters
Engen and Wait describe the noise temperature, Te, (Eq. 31) as a function o f an
alternate set o f two-port noise parameters defined by the relation [156],
. K 0*g> -
T - f
e
(l-IPF) ( K - l - l )
emirt
2
The four alternate noise parameters
T , and P (a complex value) are related to the
conventional noise parameters Trfmfn) or
(
p/
_ I
______
Trev
°Pt~ {
^
_ Ta
I^ a n d
through the following relations:
P
* Tt
(1
^
+K)-Tm ( 1 -|p p ) (I-IQ
* e ( m ia )
-
(1 2 4 )a -C .
optsJ2
where the conventional noise parameter for the optimum reflection coefficient,
is
related to the primed variable in Eq.124 (a) by,
r»
*
'
^opt + $ ii
1
1 optA
11'
211
•i
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
< I2 5 )
j
and
K
Here,
=
1
+
< T, Tm |p|»
[T. * Tm (HPI* ) ] 5
(126)
is simply the conjugate o f Su for the two-port. Engen’s text [156] provides a
solution for
in terms o f the conventional noise parameters as,
T
.
l£ V 2
(127)
d - ir ^ P )
where Tk = 4 TaRHGapt and P opt is derived from Eq. (125).
8
.1.3 Source Temperature o f One Port Noise Generators
In this work, the equivalent black-body temperature o f a noise source is described
using Engen’s description for a noisy two-port depicted in Fig. 77 [140]. The noise
power emerging from port 1 o f Fig.77 is related to the input port temperature T0Ut I,
out,1
SYSTEM
LOAD
®21
l 1
Figure 77
rH
®22
*r22 ii
l2
Two-port circuit for discussing noise temperature T ^ j. A similar
arrangement for T ^ occurs with the load placed at Port 1.
212
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where “ 1” indicates the input o f a two-port device. T0IItI is a sum o f Trev and the product
o f the reverse gain, A [2, and the temperature o f the port-2 termination T2. This sum is
written,
Toua =
A n tz
(128)
where the reverse available gain for the two-port o f Fig. 75 is,
1 ^ 1
A i2
1
- l ^ l
2
i - i r£l 2
i ■ ir If-l2
(129)
and the conjugate o f the load reflection coefficient, T2 is,
rv
*
r 2
~
-
Commonly, T2 is the ambient temperature
(I3 0 )
but the load may be cooled for optimal
performance. The second term in the left-hand side o f Eq. (129) is the reverse power
gain. For most applications Eq (129) is reduced by the assumption
r£ - ~ sn
for r2=o.
As in Engen’s original work, the output port temperature, Tout^, is found by
interchanging the port numbers ( I) and (2) in Eqs. (128-130).
Comparison o f T ^ with the temperature Teq o f Frater and Williams shows that
Teq does not include the reverse gain term. Although Teq is a fairly good approximation
for their 1400 M Hz design [150], Dunleavy et. al. point out that at higher microwave
frequencies the feedback effect o f Cgd [139] and the influence o f the product A 1 2 -Ta m b 2
213
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cannot be ignored[157], For both o f these reasons
increases. Therefore,
8
diverges from Teqas frequency
is the desired temperature o f interest above S-band (~3G H z).
.1.4 Derivation o f the Reverse Noise Measure
In the following discussion a measure o f FET performance is given in terms o f T ^
and A i 2 that provides a designer with insight to achieve the lowest physically realizable
This is necessary because, by definition, Trev is the equivalent temperature o f the
noise power exiting port one with the load at port two set to zero Kelvin. Under this
condition Trev equals
As this is an ideal lim it, it would be useful to define the
minimum Tout^ that is physically realizable for a given FET that has a load with a finite
temperature.
Minimizing the achievable noise source temperature developed by a FET noise
source at room temperature requires insight about the limitations and characteristics o f
the variables in Eq. (130), namely TonU, Trev, A 1 2 and T2. There are a variety o f ways
to minimize TouU, including the following:
(1)
The application o f frequency selective feedback to reduce A I 2 and
consequently T ^ , Although development o f such a circuit is beyond the
scope o f the present work.
(2)
The selection o f a FET and an associated bias with a lowest
value.
(3)
The optimization o f a trade-off between Trev and A 1 2 through the use o f
a figure o f merit, introduced below.
(4)
Use o f a multi-stage Cold/Hot noise source to reduce noise contributed by
the Port 2 load in combination with the trade-off o f item (3).
214
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Although a comparison o f
for several FETs is presented below with regards to item
( 2 ) o f the previous list, items ( 1 ) and ( 2 ) are not dealt with directly here because, they
may be best studied as separate circuit design or FET design issues. This w ork studies
item (3 ), since the available literature does not address the relation o f T rev and the
product
to FET-based noise source design.
Set apart from the design oriented tasks o f items (1) and (2) above, a relation
satisfying item (3) requires some theoretical development that this work contributes.
This contribution is based on replacing the load and its temperature
second Cold Noise source. The temperature T 2 o f Fig. 77 then becomes T OI^
with a
1
o f the
second stage Cold Noise source. Now consider an infinite cascade o f identical noise
sources where each subsequent stage establishes a load temperature, such that T 2 is
always TooU of the next identical stage. Applying Eq. (128) to such a cascade o f n
optimally matched noise sources yields a geometric series in A j2,
The minimum achievable Tout,l> for an infinite cascade o f Cold Noise sources is found by
evaluating the limit as n approaches infinity. What results is a new quantity defined here
as the reverse noise measure, M rcv,
(132)
215
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Since A 1 2 < 1, Eq. (132) converges, the effect o f T_J. ?goes to zero and
is,
(133)
This result is similar to the well known noise measure, M , described for linear noisy twoport networks [158],
°
1
-
—
(134)
where G , denotes the forward available gain of the two-port. However, the noise
measure is a scalar measure of FET performance as an LNA and
is a limiting
temperature for a cascade o f noise sources. Comparing Eqs. (133) and (134) further, a
low value o f M indicates a low Te and/or a high forward amplifier gain, and a high
forward gain is important in reducing noise contributed by a second stage amplifier
(usually a gain stage with a higher T J .
In the case o f Eq. (134),
is a lower
temperature limit that a cascade o f identical noise source stages w ill approach. This is
because staging reduces A , 2 geometrically as in Eq. (131). This lowers the effective
ambient load temperature which reduces Too,!- While the preceding discussion assumes
r 2 = 0 , Eq. (130) can be further generalized to include treatment o f T 2 * 0. In that case,
the full expressions for A 12 and T2 are required as they have to be written in Eqs. (129)
and (130).
216
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8
.1.5 CAD and Simulation o f Noise Source Temperature
With Tt now identified as T ^ , the design procedure of Section 8.1.1 is
reconsidered and comparisons are made to
and Tjmin. The design problem is
solved here by a parametric sweep o f LKIWGe within the simulator. A t a particular
frequency the CAD model yields a minimum value o fT oatjl with respect to
For
example, a comparison o f temperatures TonU, Trev Teq, and Temin in Fig. 78 applies a
simulated, variable, series feedback inductance to FET C l at a frequency o f 18.0 GHz.
Referring to Eqs. (121) and (122) the curvature o f the different temperatures is
dominated by C9 at L, values below where the minimum occurs and L( above that point.
Figure 78 clearly illustrates the need to evaluate the noise source temperature using
200
Tamb=296 (K) F=18 (GHz)
g
180
160
^
140
a
120
g
80
£
60,
— Trev
☆ Teq
H— Toutl
O Temin
§ 100
40
20
0
100 200 300 400 500 600 700
Lsource (pH)
Figure 78
Simulated T ^ , T,*,, T ^ i T ^ j (K ) for HEMT C l versus variable source
inductance, L„ (pH) for a modeled FET. The comparison illustrates the
importance o f designing with respect to
as opposed to other noise
temperature terms at higher frequencies.
217
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Iii comparison, if Frater and Williams’
the FET o f Fig. 78, then the resulting
was used to design a noise source for
would actually be 32 K higher than predicted
by Teq and the design value o f series inductance would be 120 pH larger than required
to minimize T ^ j. FETs A l, A2, and C l achieved low Tgvalues o f 93K, 105K and 41K
respectively at their optimal bias points and L .*** values.
Before discussing the Cold Noise source implementation and performance it is
instructive, for comparison, to present the T, performance o f an unmatched FET. In
addition, the bias-dependent simulation o f FET noise source performance has not been
reported in the literature. Figure 79 presents a bias-dependent simulation o f noise source
temperatures TooU and T o u t> 2 for FET C l. This model simulation o f FET C l predicts a
minimum TouU = 70 K for an optimal valued source feedback inductance with
250
F=18 (GHz) Vds=1 (V) Tamb=296 (K)
Tout1_w/data
Tout1_w/model
▼ Tout2_w/data
-•-••T o u t2 w/model
▼
■
200
S
150
►
2200
•H
O
/
*
O
h-
%
2600
1800 S.
rv>
/
✓
100
1400 3
50
?0.8
1000
▼
l
-0.7
-0.6
-0.5
-0.4
-0.3
600
-
0.2
Vgs (V)
Figure 79
Simulated comparison o f cold and hot noise source performance o f HEMT
C l with set at an optimal value
Toat,l and Tou^ (K ) are the value of
T( at the input and output ports respectively.
218
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
T2=T-nW=300K. This represents state-of-the-art microwave performance for a FET Cold
Noise source temperature at the FET reference plane. Figure 79 also shows that
achieves a hot noise temperature o f2600 K. By using the models developed in this work,
the designer can also account for ambient temperature variations at the CAD level, thus
satisfying a primary goal o f this work.
8.2
HYBRID CIRCUIT IM PLEM ENTATION
Using the theory, modeling and design methods described above, a circuit design
was enabled by the powerful bias and temperature-dependent FET noise model described
in Chapter 7. The design and fabrication o f the circuit was executed by M . Smith o f
Raytheon/E-Systems with collaborative support from the USF Microwave and Wireless
Research Lab. For the first time, a high electron mobility transistor (H EM T) series
feedback circuit is employed to achieve an electronically cold noise temperature at Kband frequencies (18-22 GHz). As applied to a hybrid Cold/Hot noise source design
using an InAlAs/InGaAs/InP HEMT, the following demonstrates a 105 K cold
temperature in the 18-22 GHz range; the highest reported frequency for a FET cold
noise source. Agreement between simulation and measurements are shown to validate
the capability to design a variable temperature noise source within a linear circuit
simulator.
8.2.1 Design Approach
Using the developed models, a parametric analysis o f the Cold Noise source
performance potential is introduced. The design problem is solved, to a degree, by a
parametric sweep o f source inductance, L ^ ^ as was performed to generate Fig. 78. In
219
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Figure 78, a minimum value o f T ^ occurs with respect to
Using this minimum to set
, at a given frequency.
the input matching network o f a one-stage design
continued by providing a narrow band Su match at the FET input. This CAD analysis
procedure is also useful because, during the parametric sweep all the related two-port
network measurements are available including; stability factor “k”, input impedance,
VSW R, etc,.
The hybrid noise source designed and fabricated by an industry collaborator had
a design frequency o f 22 GHz using the models developed in this work. The designer’s
insight was particularly helpful in considering performance comparisons o f the fabricated
circuit and the CAD simulation over the frequency band o f interest. Issues that occurred
due to discrepancies between the design layout and the physical circuit included:
1
)
variations in the microstrip width due to etch variations, 2 ) variations in the bond wire
lead inductance and fringing capacitance used in the assembly and 3) reflections due to
microstrip to coaxial package connections. While the circuit simulation was corrected
for etch variations by measuring and adjusting microstripline widths, the remainder o f
these factors require a more detailed modeling effort. In spite o f the work to be
completed on the coaxial connections, outstanding Cold/Hot noise source performance
was measured without any post fabrication tuning, as discussed next.
.
8 2 .2
Measurements and Results
Using the described models and Eqs. (128) and (129) to predict T ^ i a hybrid
Cold Noise source circuit was designed, built and measured in two separate
laboratories[159]. One set o f noise source temperature, T ^ ,, measurements was made
i
is
i
f
220
!
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
450
400
350
?
-*-V gs=-.8 USF
Vgs=-.4 USF
—Q—Vgs=0 USF
Vgs=-.8 NIST
Vgs=~4 NIST
Vgs = 0 NIST
300
Z - 250
J
200
150
100
50
0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5
Vds (V)
Figure 80
Comparison o f data ( f = 18GHz and
= 296 K ) measured at USF on
the hybrid Cold/Hot noise source and data measured at NIST versus V *
(V ) for several
(V ) biases. USF measurements are plotted with solid
lines and symbols.
at the National Institute o f Standards and Technology (N IS T) using an 18-26GHz
substitution radiometer, referenced to a cryogenic waveguide noise standard. The other
measurements were taken at USF, using the noise power measurement mode o f a 0.0118GHz HP8970B/HP8971B noise figure measurement system. This measurement is
referenced to a HP346B solid-state noise diode. Figure 80 shows good correlation
between the USF data and the N IST data.
The input reflection coefficient magnitude also varies versus V^and V * as shown
in Fig. 81. This variation may necessitate the use o f a circulator for some applications,
and is responsible for some o f the differences between the USF and N IST temperature
data in Fig. 80. That is, the effect o f source reflection was corrected for in the NIST
221
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
measurements, but the reflection related uncertainty remains in the USF noise
temperature measurements. The increasing |r,J with more negative V p correlates well
with results for
j in Fig. 80. Figure 82 shows the output port reflection coefficient
measurement.
1
0.9
0.8
0.7 ' —
|Tli| 0.6
0.5
0.4
Vgs=-0.8
L — 0— Vgs=-0.4
| —<=>-* Vgs=0
F
®L—. . .
0.3 r q ' * - q - — 11******$
------0.2
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
Vds(V)
Figure 81
Measured variation of fabricated hybrid Cold Noise source (Port I)
reflection magnitude for several bias voltage conditions at f - 18GHz and
T ** = 296 K.
0.8
0.6
0.4
0.2
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
VdsOO
Figure 82
Measured (USF) variation o f hot noise source (Port 2) reflection
coefficient magnitude, r a at f = 18GHz and
= 296 K.
222
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Finally, the measured and simulated
are compared in Fig. 83.
and TobU results fo r the hybrid circuit
Figure 83 shows good correlation between the circuit
simulation and the measured 18GHz input port (cold) noise temperature. As expected,
at zero V * or a large
bias, where the gate is pinched-off, the temperature is
approximately equal to the ambient room temperature (-296K ). Variable equivalent
temperatures between 105K and room temperature were achieved from the input port o f
the prototype. Additional 22GHz N IS T measurements (not shown) exhibit variability
from 126K through room temperature. Output port (hot) noise source measurements
were taken at USF, and are also compared to the circuit simulation shown in Fig. 83.
350 -Q-- Toutl model
Tout1~NIST
- * ■ Tout2_USF
300 ~ - £ s ■Tout2 model
1050
k
/
850
£
250
m
§
200
650 m
/ N
I-
450
150
250
1 0 0
Vgs(V)
Figure 83.
Comparison o f measured and modeled hybrid circuit cold and hot T(
performance at f = 18GHz and
= 296 K. Simulated performance is
denoted by solid lines and open markers.
and
are the value of T ,
at the input and output ports respectively.
223
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Hot source variability from room temperature to over 1000K was observed. The forward
gain for the circuit was lower than the device, which is consistent w ith the lower hot
(output port) noise temperature observed in Fig. 80 versus that predicted for the device
in Fig. 79 at similar biases. As with T o o t ^1 and
, a demonstration o f the measured
and simulated circuit performance is shown for the reflection coefficients in Figs. 84.
The modeled bias-dependent trends agree well for both T u and Fg , and the lower
magnitudes o f T ont>1 in Fig. 79. The lower values o f T u and r a for the circuit simulation
are also consistent with the limitations o f the physical models o f the passive structures
in the circuit. For example, the degradation in the reflection coefficient due to coaxial
connectors in not modeled.
- A - Model_.1l
- A - Measured.ii
- 0 - Model_2i
MeasuredJZi
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
-
Vgs(V)
Figure 84
Comparison o f measured (USF) and modeled hybrid circuit level reflection
coefficient magnitudes Tu and r a versus Vv (V ) at V ^ l V . Simulated
performance is denoted by solid lines and open markers. Lower values o f
modeled r u and r a are consistent with the simulation not having a model
for the coaxial-to-microstrip transitions.
224
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Table 13 evaluates the simulated circuit results for TonU and M rev at 18G Hz and
22G Hz for various bias points. The last column in Table 13 is the difference between
T 0 u t,l
and
which increases with more negative Vn due to the concurrent increase
o f A 12. This illustrates the amount o f improvement that further design efforts may obtain
for example, through a multistage design. Whether or not the 20K improvement can be
realized will also depend on maintaining circuit stability in addition proper port matching
conditions. Also note that this simulation for V * =1V does not reach the 100K minimum
achieved at V * = 0.5 V.
Table 13
VpCV)
i
©
-0.7
-0 . 6
-0.5
-0.4
-0.3
•
o
•
©
I*
-0 . 6
-0.3
Results for hybrid circuit prototype simulation for Toalil
and Mrev versus V9 (V ) for V ^ lfV ) at 18GHz and
22GHz.
Freq. (GHz)
T o u t,! “ M r e v
T o u t, l @ 9
M xevC K )
2 2
241.569
201.734
191.399
183.331
183.616
234.048
186.686
173.551
164.065
164.321
(K)
7.52
15.047
17.848
19.265
19.295
18
18
18
18
18
197.545
168.212
161.039
155.599
155.352
190.295
153.302
143.626
137.544
137.479
7.250
14.910
17.413
18.055
17.872
2 2
2 2
2 2
2 2
225
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8.3
CHAPTER SUMMARY
This work makes significant advances toward establishing state-of-the-art FET
Cold/Hot noise source development. In comparison to broad-band diode hot noise
sources, the FET Cold/Hot noise sources are a solution that needs to be tailored to a
specific frequency range. Effective design and modeling tools, enabled by accurate biasdependent FET modeling, have been established and demonstrated for development and
optimization o f variable solid-state noise sources. The performance o f the 18-22GHz
prototype circuit, developed in collaboration with Raytheon/E-Systems represents the
highest frequency reported for a FET Cold Noise source. The flexibility o f the circuit in
providing a variable hot or cold noise temperature should prove useful in a number o f
applications.
Compared to previous efforts, the technique described here overcomes frequency
limitations by using the advanced microwave FET noise models. This comparison also
recognizes that the noise temperatures T ^ and TQut£ define the desired Ts for modeling
FET-based noise sources. Based on this improved definition, a further investigation
considered the theoretical limit for achievable noise source temperature. From this study,
the reverse noise measure, M ^ is defined. M rev indicates the minimum achievable twoport noise temperature, Tont, for a cascade o f identical, optimally matched, two-port
noise sources. The resulting evaluation o f current low-noise FET technology predicts
the lowest microwave frequency noise source temperature achieved to date, and a related
circuit has demonstrated cold noise temperatures in the
1 00
K range at 18 GHz and 22
GHz [141].
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CHAPTER 9. CONCLUSIONS AND RECOMMENDATIONS
9.0
SUMMARY OF WORK
Chapter 1 outlined the two main goals o f this work: 1) to build a bias and
temperature dependent microwave FET noise model and 2) to relate the modeling
procedures to physical causes. This work achieves the first major goal o f developing an
experimentally-based CAD model for the bias and temperature-dependent simulation o f
microwave noise in FETs. In accomplishing this goal, several advancements have been
made to FET small signal and noise modeling and microwave noise parameter
determination.
A further goal set up in Chapter 1 was accomplished through the
comparison o f noise model coefficients for a variety o f state-of-the-art FET technologies.
Specific technical contributions are reviewed below along with recommendations for
research continuing from this work.
9.1 SPECIFIC TECHNICAL CONTRIBUTIONS TO MICROW AVE FET NOISE
This work developed and validated a new bias and temperature-dependent FET
noise model. The model and associated set o f modeling procedures apply to CAD within
existing standard microwave simulation software. Through the course o f this study this
model was applied to both MESFET and HEM T/PHEM T technologies supplied from
several supporting industrial foundries. While two dominant intrinsic FET microwave
noise models were developed, the noise temperature model became the baseline model.
This choice followed from the simplicity o f the noise temperature model. The final CAD
model uses discrete noise temperature model results from a database o f individual bias
227
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points. This is the table-based bias and temperature-dependent FET noise model. The
resulting bias and temperature dependent model saves computer memory w ith respect to
an equivalent database and the model is shown to be computationally efficient.
9.1.1 Novel Bias and Temperature Dependent Model o f FET Noise
In this work, the extracted model data was used to study trends in the FET model
elements due to variations in bias, temperature and frequency. The frequency, bias and
temperature dependence o f the FET S-parameters and noise parameters were measured
experimentally and an extraction methodology was used to model the FET. The three
operating point variables are accounted for in different ways:
(1)
The frequency dependence o f the small signal and noise properties o f the model
is well-predicted due to the systematic extraction o f both the intrinsic and
extrinsic small signal model elements. This improves the likelihood that the
element values represent the physical FET.
(2 )
Bias dependence is predicted through 2-D linear interpolation o f a table of
experimentally extracted element values. The bias dependence is not assumed to
be linear and the accuracy of the 2-D interpolation can be improved arbitrarily by
increasing the number of data points defined within a fixed grid o f Vv and V *
biases.
(3)
Finally, the temperature dependence o f both the small signal and noise model
elements are predicted by linear thermal coefficients for each element.
By developing a model for temperatures greater than room temperature, this work
resulted in publishing data on model element thermal coefficients not previously
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published. The trends in the thermally induced model element variations are highly
correlated with a linear temperature-dependent model. Thermal coefficients are therefore
easily compared between different laboratories and/or FET technologies. One exception
from a linear model was found to occur fo r the GaAs PHEMT (A2). In studying the
temperature dependence o f a MESFET and PHEMT below room temperature, the
MESFET parameters were found to vary linearly as temperature decreased. In contrast,
the PHEMT parameters show a distinct change in slope that may be interpreted to be
caused by electron trapping. Therefore, the extrapolation o f FET model element values
below room temperature should be approached with caution, as a possible shift in the
values may occur that is not linear.
9.1.2 Analysis and Model Extraction Methods
This work advances a technique (denoted Cold-HEMT) for extracting parasitic
resistance in HEMTs and PHEMTs. Experimental results for an InGaAs/GaAs PHEMT
also find the Cold-HEMT technique to be valid in the presence o f gate leakage current.
Furthermore, the Cold-HEMT technique establishes a connection between a model
extraction technique and existing theory for forward biased gate currents in a
heterostructure FET. Previous assumptions, based on modeling the metal-semiconductor
barrier (Shottky barrier), are shown to neglect the effect o f quasi-Fermi level bending at
the heterostructure barrier.
This is why traditional techniques do not apply to
heterostructure FETs and why the Cold-HEMT technique is required.
9.1.3 FET Intrinsic Noise Modeling
A theory for physically real, noisy two-port parameters was proved, and the
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results were explained in terms o f masting theory. The masting theory is shown to be a
subset o f the present derivation. From this theory, a criterion for evaluating intrinsic
noise parameters is described. The new theory is applicable to identifying errors caused
by lossy deembedding o f the noise parameters or from deembedding series inductive
feedback.
A comprehensive software tool for FET noise parameter modeling was developed
and utilized extensively in the modeling o f a wide variety o f microwave FET
technologies. The completeness o f the analysis allows the identification o f possible
modeling errors at a variety o f stages in the overall model development. This capability
enhances modeling accuracy even in the presence o f large data errors, because the
software allows for identification o f a variety o f errors encountered.
Anomalous, 1 /f2 dispersion o f FET microwave noise behavior is analyzed and
modeled in this work. The frequency noise is shown to be contributed by leakage
currents from gate-to-source, and is explained through an analysis o f the noise
correlation matrix for the associated parasiuc resistance. An example of leakage effects
in PHEMTs produce 1 /f2 frequency dependence in the noise generators. It was found
that the parallel combination o f parasitic resistance and capacitance explains why many
previous studies find an increase in the low microwave frequency noise spectral density.
9 .1 .4 Novel Method of Determining FET Noise Parameters
A novel method o f determining the two-port noise parameters o f the FET is
described that does not require a variable admittance tuner. The method makes use of
noise figure data measured at one known source admittance and knowledge o f the small
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signal equivalent circuit model to develop a noise model o f the FET. The resulting noise
model allows the calculation o f the noise parameters at frequencies beyond the range o f
the noise figure data.
9.1.5 Temperature-Dependent Modeling o f FET Noise Generators
A figure o f merit (referred to as the noise gain ratio, NG R) demonstrated
comparison o f temperature-dependent intrinsic FET noise in differing FET technologies.
This comparison is unbiased by gate geometry scaling factors. The resulting comparison
o f material-dependent factors finds the large electron inter-valley scattering energy,
AEr_L, o f Ino 5 3 Ga0 47As to be well-suited to low-noise performance with the least
dependence upon ambient temperature variations. Furthermore, the improvement o f this
performance between GaAs and Ino l 5 Gao gsAs is shown to be dependent upon the 2DEG
modulation efficiency o f the heterostructure FET employing 1% 15Gao 85As as the
channel.
9.1.6 Investigation o f FET Noise Performance at Millimeter-wave Frequencies
A preliminary study investigated the usefulness o f the models developed here for
use at millimeter-wave frequencies (£>30 GHz). FET small signal models extracted at
microwave frequencies (up to 18 GHz) show good agreement compared to millimeterwave S-parameters measured through 67.S GHz.
Since the intrinsic FET noise
generators are frequency independent, there is high confidence in the ability to
extrapolate the noise nodel through 67 GHz. The related noise model performance
agrees well with an existing model that describes a linear scaling o f FET minimum noise
figure, Fmin, up to the unity current gain frequency, ^ , o f a transistor.
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I
9.1 .7 Improved Modeling and Design o f FET-Based Noise Sources
The usefulness o f the extracted FET model is demonstrated by improving the
design methods for, and evaluation of, FET-based noise sources at microwave and
millimeter-wave frequencies. This work correctly defines the proper black-body noise
source temperature o f interest, T„ from an analysis o f an alternate set o f noise
parameters, used in the metrology o f noise calibration standards. As a result, the quantity
T ^ i is defined as the desired temperature for FET noise source evaluation and design.
Toum is equal to the measured quantity Ts. A new interpretation o f TouU shows that it
is made up o f two components: ( I) Trev which denotes the temperature contributed by
the two-port itself and (2) the product A l?Tginlt? which denotes the available temperature
contributed by the termination at Port 2. Based on this improved definition, a further
investigation considered the theoretical limit for achievable noise source temperature, and
as a result defines the reverse noise measure, M rev.
M (ev indicates the minimum
achievable two-port noise temperature, Toot„ for an infinite cascade o f identical,
optimally matched, two-port noise sources.
Compared to previous efforts, this work describes a design approach that
overcomes previous frequency limitations through the development and use o f advanced
microwave FET noise models. The resulting hybrid circuit prototype achieved the lowest
FET noise source temperature to date, in the 18 GHz to 22 GHz frequency range. The
temperature model also presents the capability to account for ambient temperature and
bias variations at the CAD level, thus satisfying a primary goal o f this work.
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9 .2
RECOMMENDATIONS FOR FURTHER WORK
This work has led to the development o f an unproved FET CAD model and a
comprehensive set o f modeling techniques. Comparisons using this model result in
conclusive findings concerning the dependence o f FET channel technology on
temperature performance above 300 K. From this point, several issues may be addressed
further as a result o f this work. These include several areas including; FET noise
modeling, model extraction, FET noise parameter measurement, CAD applications and
FET-based noise source design.
9.2.1 Noise Model Enhancements and CAD Applications
The table based model, as it exists, performs well as both a bias and a
temperature-dependent model for the 300 K to 368 K range studied here. For wider
temperature variations and particularly at lower temperatures, the inclusion o f trapping
related threshold voltage shifts needs to be addressed to retain the table format o f this
model. Also, the accuracy o f the linearly interpolated bias model would benefit from the
use o f a spline-based interpolation.
In addition, to the developments that this work presents, the FET noise model
study accomplished by this work could be expanded upon for additional CAD
applications. First, the inclusion o f temperature dependent 1 / f noise w ill enhance the
model for low-noise mixer and oscillator phase noise design. Secondly, the development
o f a noise model which is consistent with the non-linear modeling algorithms^ such as
harmonic balance, would be useful for high dynamic range applications. This would also
benefit the development of FET amplifiers used as both transmitter and receiver blocks.
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9.2.2 Model Extraction Advancements
The topic o f model extraction w ill continue to evolve as new FET technologies
and environments are studied.
The Cold-HEMT method described here could be
improved upon over the experimental trials presented in this work. This could be based
on a fitting o f the forward biased gate-to-source diode, as is done for a conventional cold
FET, but with the included modeling o f the heterostructure diode. Such a systematic
evaluation o f the heterostructure parasitic resistances would enhance the model
extraction algorithm for noise modeling versus bias and temperature.
9.2.3 FET Noise Modeling at Millimeter-wave Frequencies
Millimeter-wave modeling o f FET noise w ill be enhanced by several advanced
models o f the small signal FET equivalent circuit. This requires improved parasitic
element evaluation including the frequency dependence o f effects like the skin depth o f
the gate metal. O f course, validation o f noise performance beyond 26 GHz should be
undertaken immediately by obtaining millimeter-wave noise parameter data. Obtaining
appropriate millimeter-wave data is discussed next.
9.2.4 Improved Determination o f FET Noise Parameters
This work has reviewed and presented techniques to calculate the four noise
parameters. The novel tunerless method appears well suited to further investigation at
millimeter-wave frequencies. To proceed, one should evaluate the possibility o f fixing
Tg to a constant because a direct extraction procedure for Td results if this assumption
does not affect the fit o f the model to data.
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APPENDIX A ANALYSIS OF NOISY TWO-PORT CORRELATION MATRIX
TRANSFORMATIONS
In the analysis o f noisy two-port networks it is often desirable to transform from
one network format o f the noise correlation matrix: to another format.
The
transformation o f one two-port form into a desired alternate form is illustrated here
through and example. This example describes the transformation o f a hybrid parameter
format to an admittance parameter format, as this case is a desired transformation for
FET noise modeling.
From Section 2.3 the short circuit model is described by its y-parameter definition
and the noise currents inI and
A
A/
M—
'
+
^22
»
----
>1
> 1.
V
*
»
o f Fig. 10(a),
The hybrid model o f Fig. 10 (c) is similarly described by the /r-parameter definition and
the noise generators eh and ib o f Fig. 10(b),
*
»----
II
> 1
hn *>n A
h2l
ha . /V
+
V
A.
235
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(13d)
(APPENDIX A CONT.)
To find the appropriate matrix for transforming from hybrid form to admittance form
apply to Eqs. (136) and (137) the conditions that characterize the noise generators of a
hybrid matrix. Namely, an open circuit noise voltage at the input and a short circuit noise
current at the output. This procedure gives,
Open Circuit - Fu Vx + inl - 0
Short Circuit -
= Y2l Fj + in2
/ 2
(137)
for Eq. (136), and for Eq. (135):
Open Circuit - Fj = eh
Short Circuit -
/ 2
= ih
(138)
Comparing open circuit conditions and short circuit conditions in Eqs. (138) and (139)
gives the relations,
1
eh
l nl T T "
Ml
(139)
lh =
~ ~ZT~ l nl + ' « 2
7ll
Now rewriting Eq. (136) with open circuit conditions on the input (V ^ e j,) and short
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(APPENDIX A CONT.)
circuit conditions (V 2 =0) on the output gives with substitutions from Eq. (140),
0
1
~Ki
(140)
-y
The signs o f the noise generators in Eq. (141) are o f little consequence, because they
cancel out in forming the noise correlation matrix. The noise correlation matrix is the
mean o f the outer product o f Eq. (141), which is written,
0f
0
V
(
h #»r
1
^21
i *21 I
\ .'*]
l n ir ra
*n l
n2
/
(141)
ij'n l
where the brackets denote the mean value and f denotes the transpose conjugate.
Comparing the result for the general transform relation o f Eq. (36) in Chapter 2 with
Eq. (142) finds,
pv,][c.][iv,r* [c,]
(!«)
where h - y denotes the transform from /(-parameter form to ^-parameter form. So the
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i
»iI
(APPENDIX A CONT.)
appropriate transform matrix, P, is,
*ii 0
A-y
^21
(143)
1
Similarly for the admittance to hybrid noise correlation matrix transform, Py _ h, the use
o f open circuit conditions on Eqs. (136) and (137) gives,
hn
0
*2 1
1
(144)
y-h
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APPENDIX B PROCEDURE FOR CALCULATING THE INTRINSIC FET
NOISE MODEL COEFFICIENTS FROM MEASURED DATA
The procedure for de-embedding the intrinsic FET noise generators uses the noise
correlation matrix mathematics o f Section 2.3. The following solution is presented to be
used in concert with the FET noise modeling and measurement techniques described in
Chapters 3 and 4 o f this work. Similar solutions are found in the text by Dobrowolski
[160] and the paper by Pucel et. al. [104]. The goal here is to develop an equivalent
expression for the intrinsic FET noise correlation matrix, but now in terms o f the
measured noise parameters. This de-embedding procedure begins by calculating the
matrix CA from measured noise parameters using,
R,n
2
-
2
R
j ’apt
- R nJ opt
m,
(145)
R n \ r opt[2
The lossless elements o f the gate parasitic network can also be written in terms its chainm atrix
These elements are removed from CA by a reverse transform to a first
intermediate result, CA1, as follows,
(146)
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t
________ .____________
- _____
____
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(APPENDIX B CONT.)
The resistances
and R j are then removed by subtraction o f their respective A-
parameter noise correlation matrices,
and
resulting in the intermediate form,
i t ' i
(147)
where the product^^ 4 transforms the drain noise to the input port. CAiI represents the
combined noise correlation matrix o f the intrinsic FET and the source parasitic network.
To remove the series connected source parasitic Qais in Eq. (146) is transformed to an
impedance form by the orthogonal relation of Eq. (36) as,
= PC
C
(148)
The Chain-matrix-to z-matrix transform P in Eq. (147) is given by [106],
P =
1 -Zis,n
0
(149)
-Zis.21
The source resistance is now subtracted from Czis in Eq. (149) directly to give the
intrinsic noise correlation matrix o f the FET as,
Cn = Czis - Czs
C * is transformed to the admittance form
using the intrinsic FET admittance
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(150)
(APPENDIX B CONT.)
parameters,
(151)
The thermal noise associated with the leakage resistance
subtracted from
(or conductance G^) is
as given by Pucel et. al. [103].
Cyd. = C„
- GgsF F f
yi
(152)
where the matrix F is a hybrid parameter transform whose matrix is Eq. (142). Finally,
this produces the desired intrinsic noise matrix from which the noise coefficients are
found be direct comparison to the matrix o f Eq. (122),
p
=
C yda
gm
(153)
where the subscripts ( 1 and 2 ) denote the matrix elements o f the two-port noise correlation
matrix for the intrinsic FET Cyd- Once P, R, and C are found, the noise parameters can be
calculated at any frequency. This completes the de-embedding o f the intrinsic noise generator
coefficients P, R and C. The FET model equivalence relations o f Chapter 2 can then be used
to find the noise temperature model coefficients Tgand Td.
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APPENDIX C TEST BENCH EQUATIONS FOR NOISE MODEL EXTRACTION
The following is net listed output o f the HP/EEsof Comms Simulator Test Bench
developed in this work for extracting the necessary intrinsic noise model coefficients from
measured noise parameter data.
Mathematical notation used for equation block
programming is detail in the Series IV Users Manual. The equation block is arranged to
perform three primary functions: ( 1 ) to extract intrinsic noise model coefficients from
data, ( 2 ) to provide a quality control check on the measured data and the extraction
process, and (3) to compare the resulting simulated noise parameters versus the measured
noise parameters. Additionally flexibility in extracting the noise model coefficients is
built into the equation block which can extract key intrinsic elements like gm, Ri, Rds and
Cgs at each frequency o f interest or allow direct input o f known values as constants for
all frequencies.
Model Units
UNITS UNITS DEFAULT
FREQ=GHz
RES=Ohm
COND=S
DMD=pH
CAP=fF
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(APPENDIX C CONT.)
LNG=um
TIME=psec
ANG=deg
POWER=dBm
VO LT=V
CUR=mA
DIST=mi
Model Constants and Reference Values
RREF RREFJDEFAULT
R=50
TEMP TEMPJDEFAULT
TEMP=25
NFM IN NFMIN1
GM NGM N1
RNRNI
YM NYM N1
NFAC NFAC1
YIJYIJ1
1=1
J=1
243
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(APPENDIX C CONT.)
NMAT NMAT1
ZUZUl
1=1
J=1
ZUZIJ2
«
1=1
J=2
SU SIJ1
1=2
J=l
SU SU2
1=1
J=2
SMAT SMAT1
ZIJ ZU3
1=2
J=1
ZIJ ZU4
1=2
J=2
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(APPENDIX C CONT.)
YU YIJ2
1=2
J=l
YU YU 3
1=1
J=2
!
ZM NZM N1
NFAC NFAC2
YU YIJ4
1=2
J=2
OUT_EQN _OUTEQN
To=16.85
Cgdo=0
Cgs=143.6
Ri=2.080
Ri_data=2.848
Rds=161.5
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(APPENDIX C CONT.)
Model Extraction Equations
Cgdo_eqn=l *(-im (YU3>* l)/(2 *3 .141 *_freq* lO ^ )
Cg=IOAl 5*(-im (YU 3)*l)/(2*3.141 *_freq^lO ^)
Ri_eqn=(re(YU 1))/ ((im (TU l)-im (YU 3))A2 + (re (Y U l))A2)
Cgso=((-im (YUl)* l)/(2 *3 .141 *_freq*10A9»-Cgdo
G M =l*sqrt( ((re(YU 2))A2 + (im (YD2)-im (YU3))A2) *
(1 + (2
*3.141 *_freq* 10A9)A2*CgsoA2*R iA2))
I
Rds_bak=(l/re(YU4»
fswp=_freq * 1E9
rgd=-l/re(YD3)
gopt=re(YM Nl)
Cgs_bak=10A15*(l*((-im (YU l)*l)/(2*3.141*__freq*10A9))-Cgdo)
fsubt=l*G M / ( 2 * 3.1415 * Cgs*lE-15)
bopt=im (YMNl)
yopt=gopt + j(bopt)
nf=10A(N FM IN l/10)
yc=((nf- 1 )/ (2*RN 1* 50))-yopt
gn=(nf-l) * (g o p t-(n f-l)/ (4*RN1*50))
D =(2*3.14l5*_freq*lE+9*C gs*lE-15)A2
DD=1+ (D * RiA2)
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(APPENDIX C CONT.)
y 1ld = re (Y U l) + J (im (Y U l»
y l ldd=((D *Ri)/D D) +j((sqrt(D »/D D )
y21d=re(YD2) + j(un(YU 2»
y2ldd=(GMZDD) + j((sqrt(D )*R i*G M )/D D )
R=GM * (gn +• RN1 *50 * sqr(mag(yl ldd -yc)) y sqr( mag( y l ldd ) )
P=(1/GM) * ( sqr(mag( y21dd / y l ldd ) )* ( gn + ( RN1 *50 *sqr(mag(yc) ))))
tg=R * (To+273.15)/ ( G M *R i)
tgu=(gn+ (RN1*50* (sqr(mag(y 1Id -yc)) )))
!
*(T o + 2 7 3 )*D D /(D *R i)
td=(P ) *(To+273.15)* (GM*Rds)
!
Model Comparison Equations
!
tgf=370
td£==2150
xsubopt=l .0/sqrt(D)
rsubopt=sqrt( (sqr(fsubt/fswp) * Ri * Rds * (tg / td) )+■(R i * Ri) )
rsubopt3=sqrt( sqr(fsubt/fswp) * Ri * Rds * (tg f / tdf) + (R i * R i))
Zopt=rsubopt +j (xsubopt)
Zopt3=rsubopt3 -4 ' (xsubopt)
Yopt3=l/Zopt3
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(APPENDIX C CONT.)
gsubopt3=Re(Yopt3)
rsubn=((tg *Ri/290) + (td/(Rds*290*G M *G M ))*( 1 + (sqr(fswp*2*3.1415926)
*(Cgs*Cgs*lE-15* lE -15*R i*R i) ) ) )/50
rsubn3=((tgf*Ri/290) + (tdfir(Rds*290*GM *GM ))*
( I + sqr(fswp*2*3.141)*(Cgs*Cgs*lE-15*lE-15*Ri*Ri)))/50
gsubn=((td/290) *(l/(R ds *G M *G M ))*( sqr(fswp*2*3. 141)*(Cgs*Cgs* IE -15* IE -15 )))
tsubmin=2* (fswp/fsubt) * sqrt ( ((Ri/Rds) * tg *td) + (sqr (fswp/fsubt) * R i* Ri * (l/(R ds
*Rds»* (td *td ) ) ) + ( 2 *sqr(fswp/fsubt) * (Ri/Rds) *td)
tsubmin3=2* (fswp/fkibt) * sqrt ( ((Ri/Rds) * tgf *tdf) + (sqr (fswp/fsubt) * R i* Ri * (l/(R ds
*Rds))* (td f *td f) ) ) + (2*sqr(fswp/fsubt) * (Ri/Rds) *td)
fsubmiii2=l0*log(l+tsubinin/290)
fsubmin3=10*Iog(l+tsubmiii3/290)
gamopt=(Zopt - 50)/(Zopt+50)
gamopt3=(Zopt3 - 50)/(Zopt3+50)
TM IN1=290.0* ( nf - 1 )
Model Error Checking Criteria
kappa=(4*RNl *50*gopt*(To+273.15))/TM IN l
kappa3=(4*rsubii*50*gsubopt3 *(To+273.15))-tsubmin
kappa_my=(4*RN 1 * 50*mag(yopt)*(To+273.15))-TM IN 1
foum =(4*RNl*50*m ag(yopt))
fmin_ 1 =TM IN 1/(273.15+To)
248
fi
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V IT A
STEVEN MARC LARDIZABAL
EDUCATIONAL
BACKGROUND
Pfa-D. Electrical Engineering, University ofSouth Florida, Tampa, FL, 1997.
Dissertation Title: Bias and Temperature Dependent Noise Modeling of
Microwave andMillimeter-Wave FieldEffect Transistors.
M.S. Electrical Engineering, University of South Florida, Tampa, FL, 1991.
B.S. Electrical Engineering, University of South Florida, Tampa, FL, 1988.
EXPERIENCE
Dr. Lardizabalbeganworkingasa SeniorScientist in the Research Laboratory
at Raytheon Microelectronics Advanced Device Center in 1997.
Dr. Lardizabal was employed by the U.S.F. Wireless Circuits and Systems
Laboratory from 1990 to 1997 in Tampa, Florida.
Dr. Lardizabal was as appointed a summer research internship by the
AF.O.S.R. with the Rome Laboratory, HanscomAir Field, Bedford, MA on
May 1991.
PUBLICATIONS/
PROCEEDINGS &
PRESENTATIONS
Published works are found in the IEEE Transactions on Microwave Theory
andTechniques, IEEE International Microwave Symposium Digest of Papers,
International Device ResearchConference Digest of Papers.
HONORS/
AWARDS
Quality Presentation Recognition - 1994 IEEE Microwave Symposium
Technical Program. 1992 and 1994 Sigma Xi, Student Grants in Aid of
Research, U.S.F. Chapter.
End Page
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