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Metamaterial-inspired CMOS tunable microwave integrated circuits for steerable antenna arrays

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Metamaterial-Inspired CMOS Tunable
Microwave Integrated Circuits For
Steerable Antenna Arrays
by
Mohamed A.Y. Abdalla
A thesis submitted in conformity with the requirements
for the degree of Doctor of Philosophy
Graduate Department of Electrical and Computer Engineering
University of Toronto
c Copyright by Mohamed Abdalla 2009
°
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Metamaterial-Inspired CMOS Tunable Microwave
Integrated Circuits For Steerable Antenna Arrays
Mohamed A.Y. Abdalla
Doctor of Philosophy, 2009
Graduate Department of Electrical and Computer Engineering
University of Toronto
Abstract
This thesis presents the design of radio-frequency (RF) tunable active inductors (TAIs)
with independent inductance (L) and quality factor (Q) tuning capability, and their
application in the design of RF tunable phase shifters and directional couplers for
wireless transceivers.
The independent L and Q tuning is achieved using a modified gyrator-C architecture
with an additional feedback element. A general framework is developed for this Qenhancement technique making it applicable to any gyrator-C based TAI. The design
of a 1.5V, grounded, 0.13µm CMOS TAI is presented. The proposed circuit achieves a
0.8nH-11.7nH tuning range at 2GHz, with a peak-Q in excess of 100.
Furthermore, printed and integrated versions of tunable positive/negative refractive
index (PRI /NRI) phase shifters, are presented in this thesis. The printed phase shifters
are comprised of a microstrip transmission-line (TL) loaded with varactors and TAIs,
which, when tuned together, extends the phase tuning range and produces a low return
loss. In contrast, the integrated phase shifters utilize lumped L-C sections in place of
ii
the TLs, which allows for a single MMIC implementation. Detailed experimental results
are presented in the thesis. As an example, the printed design achieves a phase of -40o
to +34o at 2.5GHz.
As another application for the TAI, a reconfigurable CMOS directional coupler is presented in this thesis. The proposed coupler allows electronic control over the coupling
coefficient, and the operating frequency while insuring a low return loss and high isolation. Moreover, it allows switching between forward and backward operation. These
features, combined together, would allow using the coupler as a duplexer to connect a
transmitter and a receiver to a single antenna.
Finally, a planar electronically steerable patch array is presented. The 4-element
array uses the tunable PRI/NRI phase shifters to center its radiation about the broadside direction. This also minimizes the main beam squinting across the operating
bandwidth. The feed network of the array uses impedance transformers, which allow
identical interstage phase shifters. The proposed antenna array is capable of continuously steering its main beam from -27o to +22o off the broadside direction with a gain
of 8.4dBi at 2.4GHz.
iii
Acknowledgments
I would like to gratefully acknowledge the enthusiastic supervision of my advisors Professor Khoman Phang, and Professor George Eleftheriades for their continuous guidance, and inspiration. Throughout the course of my Ph.D. I have learned alot from
them, and I will always remain indebted to them. I would like to thank Professor
Khoman Phang for consistently being there for me, week after week to meet and discuss all the different aspects of this work. As for Professor George Eleftheriades, I
would like to deeply thank him for his invaluable advice and feedback, without which
this work would not have been accomplished.
I would also like to extend my thanks the former and current graduate students in my
research group as well as in the electro-magnetics group for their invaluable technical
assistance and friendship from which I have learned alot. From the electronics group,
I would like to thank Dr. Anas Hamoui, Dr. Ahmed Gharbiya, Dr. Mohammad Hajirostam, Joseph Aziz, Pradip Thachile, Masum Hossain, Farsheed Mahmoudi, Stephen
Liu, Euhan Chong, Kentaro Yamamoto, Dr. Faisal Musa, Robert Wang, Dr. Afshin
Haftbaradaran, Imran Ahmed, Navid Yaghini, Oleksiy Tyshchenko, Kevin Banovic,
Tony Kao, David Allred, Akram Nafee, Trevor Caldwell, Samir Parikh, and Nasim
Nikkhoo.
From the Electro-magnetics group, I would like to thank Marco Antoniades for all
the long hours we spent in technical discussions, and also Rubaiyat Islam, Dr. Omar
iv
Acknowledgements
Siddiqui, Ashwin Iyer, Joshua Wong, and Peter Wang. Also, I would like to thank Tse
Chan and Gerald Dubois for their continuous technical support.
I would also like to extend my thanks the Canadian Microelectronics Corporation
(CMC) for providing the fabrication facilities, and for NORTEL Networks, and the
Natural Sciences and Engineering Research Council (NSERC) of Canada for financially
supporting this work.
Lastly, I would like to thank my beloved wife Aliaa, my parents, and my sister for
their continuous support, and encouragement throughout the course of my Ph.D., and
last but not least, I would like to thank my daughter Jana, whom without knowing has
been a motivation for my accomplishments. The least I can do is to dedicate this work
to them.
v
List of Related Publications
The material presented in this thesis has been presented in part in the following journal
and conference publications.
Journal Publications
1. M. Abdalla, K. Phang, and G. V. Eleftheriades, “A 0.13µm CMOS phase shifter
using tunable positive/negative refractive index transmission line,” IEEE Microw.
Wireless Components Lett., Vol. 16, no. 12, pp. 705-707, Dec. 2006.
2. M. Abdalla, K. Phang, and G. V. Eleftheriades, “Printed and integrated CMOS
positive/negative refractive-index phase shifters using tunable active inductors,”
IEEE Trans. Microw. Theory and Tech., Vol. 55, no. 8, pp. 1611-1623, August
2007.
3. M. Abdalla, K. Phang, and G. V. Eleftheriades, “A compact highly- reconfigurable CMOS MMIC directional coupler,” IEEE Trans. Microw. Theory and
Tech., Vol. 56, no. 2, pp. 305-3019, Feb. 2008.
4. M. Abdalla, K. Phang, and G. V. Eleftheriades, “A Planar Electronically Steerable Patch Array Using Tunable PRI/NRI Phase Shifters,” IEEE Trans. Microw.
Theory and Tech., accepted for publication Dec. 2008.
vi
Conference Publications
1. M. Abdalla, and K. Phang , “A 0.13µm CMOS active inductor based on a modified gyrator-C architecture,” Micronet Annual Workshop, Ottawa, Canada, May
2005.
2. M. Abdalla, G. V. Eleftheriades, and K. Phang, “A differential 0.13µm CMOS
active inductor for high frequency phase shifters,” Proc. IEEE Circuits and Systems ISCAS 06, Kos, Greece, pp. 3341-3344, May 2006.
3. M. A. Y. Abdalla, K. Phang, and G. V. Eleftheriades, “a tunable metamaterial
phase-shifter structure based on a 0.13µm CMOS active inductor,” Proc. 36th
European Microwave Conf., Manchester, Great Britain, pp. 325-328, Sept. 2006.
4. M. A. Y. Abdalla, K. Phang, and G. V. Eleftheriades, “A bi-directional electronically tunable CMOS phase shifter using the high-pass topology,” 2007 IEEE
MTT-S Int. Microwave Symp. Dig., Honolulu, Hawaii, pp. 2173-2176, June
2007.
5. M. A. Y. Abdalla, K. Phang, and G. V. Eleftheriades, “A steerable series-fed
phased array architecture using tunable PRI/NRI phase shifters,” Invited paper,
Int. Workshop on Antenna Tech. iWAT 08, Chiba, Japan, March 2008.
vii
Contents
List of Figures
xii
List of Tables
xviii
List of Acronyms
xx
List of Symbols
xxii
1 Introduction
1
1.1
1.2
1.3
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phased Antenna Array Front-Ends . . . . . . . . . . . . . . . . . . . .
Thesis Scope and Outline . . . . . . . . . . . . . . . . . . . . . . . . .
2 Background
2.1
2.2
2.3
1
1
5
8
Metamaterials . . . . . . . . . . . . . . . . .
2.1.1 History . . . . . . . . . . . . . . . . .
2.1.2 Metamaterial Applications . . . . . .
Tunable Inductors . . . . . . . . . . . . . . .
2.2.1 MEMS Tunable Inductors . . . . . .
2.2.2 Varactor-Based Tunable Inductors . .
2.2.3 Transmission-Line Tunable Inductors
2.2.4 Gyrator-C Tunable Inductors . . . .
Phase Shifters . . . . . . . . . . . . . . . . .
2.3.1 Switched-Line Phase Shifters . . . . .
viii
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Contents
2.4
2.5
2.3.2 Reflection-Type Phase Shifters . . . . . . . .
2.3.3 Transmission-Type Phase Shifters . . . . . .
2.3.4 Lumped-Element L-C Phase Shifters . . . .
2.3.5 PRI/NRI Metamaterial Phase Shifters . . .
Directional Couplers . . . . . . . . . . . . . . . . .
2.4.1 Branch-Line Directional Couplers . . . . . .
2.4.2 Coupled-Line Directional Couplers . . . . .
2.4.3 Lumped-Element L-C Directional Couplers .
2.4.4 PRI/NRI Metamaterial Directional Couplers
Phased Antenna Arrays . . . . . . . . . . . . . . .
2.5.1 Antenna Arrays Basics . . . . . . . . . . . .
2.5.2 Microstrip Patch Antenna . . . . . . . . . .
2.5.3 Phased Array Feed Network Topologies . . .
2.5.4 Metamaterial Phased Antenna Arrays . . . .
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3 CMOS Tunable Active Inductors
3.1
3.2
3.3
3.4
53
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Traditional Gyrator-C Architecture . . . . . . . . . . . . . . . .
3.2.1 Quality Factor Analysis . . . . . . . . . . . . . . . . . .
3.2.2 Q-Enhancement Technique For Gyrator-C TAIs . . . . .
The Modified Gyrator-C Architecture . . . . . . . . . . . . . . .
A Grounded 0.13µm CMOS TAI . . . . . . . . . . . . . . . . .
3.4.1 Circuit Design . . . . . . . . . . . . . . . . . . . . . . . .
3.4.2 TAI Small-Signal Analysis . . . . . . . . . . . . . . . . .
3.4.3 TAI Noise Analysis . . . . . . . . . . . . . . . . . . . . .
3.4.4 Physical Realization and Experimental Characterization
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4 Wide Tuning Range CMOS Phase Shifters
4.1
4.2
4.3
4.4
Introduction . . . . . . . . . . . . . . . . . .
High-pass Phase Shifter . . . . . . . . . . .
4.2.1 Analysis . . . . . . . . . . . . . . . .
4.2.2 Design and Physical Implementation
4.2.3 Experimental Characterization . . . .
TL PRI/NRI Phase Shifter . . . . . . . . . .
4.3.1 Analysis . . . . . . . . . . . . . . . .
4.3.2 Design and Physical Implementation
4.3.3 Experimental Results . . . . . . . . .
MMIC PRI/NRI Phase Shifter . . . . . . . .
4.4.1 Analysis . . . . . . . . . . . . . . . .
4.4.2 Design and Physical Implementation
ix
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53
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83
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103
105
108
Contents
4.5
4.6
4.4.3 Experimental Results . . . . . . . . . . .
Passive MMIC PRI/NRI Phase Shifter . . . . .
4.5.1 Analysis . . . . . . . . . . . . . . . . . .
4.5.2 Design and Physical Implementation . .
4.5.3 Experimental Results . . . . . . . . . . .
Discussion and Comparison . . . . . . . . . . .
4.6.1 Group Delay of PRI/NRI Phase Shifters
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5 A Highly-Reconfigurable Directional Coupler
5.1
5.2
5.3
5.4
5.5
131
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.1 Tunable Coupling Coefficient Directional Couplers . . . . . . . .
5.1.2 Tunable Operating Frequency Directional Couplers . . . . . . .
Theoretical Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.1 Analysis of the MMIC Directional Coupler . . . . . . . . . . . .
5.2.2 MMIC Directional Coupler Modes of Operation . . . . . . . . .
Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.1 MMIC Directional Coupler Design . . . . . . . . . . . . . . . .
Physical Implementation and Experimental Results . . . . . . . . . . .
5.4.1 Physical Implementation . . . . . . . . . . . . . . . . . . . . . .
5.4.2 Experimental Characterization of the MMIC Directional Coupler
Effect Of The TAI On The Coupler Noise Performance . . . . . . . . .
6 Electronically Steerable Series-Fed Patch Array
6.1
6.2
6.3
6.4
6.5
6.6
Introduction . . . . . . . . . . . . . . . . .
Theory . . . . . . . . . . . . . . . . . . . .
6.2.1 Antenna Array Architecture . . . .
6.2.2 Feed Network Design . . . . . . . .
6.2.3 Interstage Phase Shifters . . . . . .
Antenna Array Design . . . . . . . . . . .
Physical Implementation and Experimental
6.4.1 Interstage Phase Shifter . . . . . .
6.4.2 Steerable Antenna Array . . . . . .
Antenna Array Linearity . . . . . . . . . .
Discussion and Comparison . . . . . . . .
7 Conclusion
7.1
7.2
7.3
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Results
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Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
x
Contents
Appendix A: Beam Squinting Analysis
208
Appendix B: Simulation Procedure
210
References
212
xi
List of Figures
1.1
1.2
1.3
1.4
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
Wireless network established between wireless device and access point
in the presence of interferers. . . . . . . . . . . . . . . . . . . . . . . . .
A transceiver front-end employing a phased antenna array. . . . . . . .
Prototype of a 2-D interface between a region with positive permittivity
and permeability (left-side) and a NRI region (right-side). . . . . . . .
Single-stage, two-stage, four-stage, and eight-stage metamaterial phase
shifters compared to a conventional TL phase shifter. . . . . . . . . . .
Photograph of the lefthanded metamaterial (LHM) sample, reproduced
from [1]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tunable TL inductor designed by terminating λ/4 TL with a tunable
capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Circuit symbol of the gyrator, showing the polarities and directions of
the port voltages and currents, respectively. . . . . . . . . . . . . . . .
(a) Block diagram implementation of the gyrator using transconductors.
(b) Tunable active inductor designed by terminating the second port of
the gyrator with a capacitor. . . . . . . . . . . . . . . . . . . . . . . . .
(a) CS-CD TAI using an NMOS-NMOS realization. (b) CS-CD TAI
using an NMOS-PMOS realization. . . . . . . . . . . . . . . . . . . . .
(a) CG-CS TAI using an NMOS-NMOS realization. (b) CG-CS TAI
using an NMOS-PMOS realization. . . . . . . . . . . . . . . . . . . . .
(a) CS-CD TAI using a cascoded CS stage. (b) CS-CD TAI using a
gain-boosted cascoded CS stage. . . . . . . . . . . . . . . . . . . . . . .
Cascoded CS-CD TAI with a feedback resistance Rf . . . . . . . . . . .
A single stage of a switched-line phase shifter. . . . . . . . . . . . . . .
xii
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18
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21
23
List of Figures
2.10 Reflection-type phase shifter utilizing a 3dB coupler loaded with varactors.
2.11 Single stage of a transmission-type phase shifter. . . . . . . . . . . . . .
2.12 Different high-pass and low-pass topologies for constant-impedance secondorder L-C phase shifters. . . . . . . . . . . . . . . . . . . . . . . . . . .
2.13 All-pass constant-impedance second-order L-C phase shifter. . . . . . .
2.14 PRI/NRI metamaterial phase shifter unit-cell. . . . . . . . . . . . . . .
2.15 Block diagram of a 4-port directional coupler. . . . . . . . . . . . . . .
2.16 Diagram of a microstrip branch-line directional coupler. . . . . . . . . .
2.17 Diagram of a microstrip coupled-line directional coupler. . . . . . . . .
2.18 lumped-element L-C low-pass and high-pass Π realizations of a branchline coupler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.19 L-C lumped-element high-pass Tee realization of a branch-line coupler.
2.20 L-C lumped-element realization of a coupled-line coupler. . . . . . . . .
2.21 N-element uniform linear antenna array with equal amplitude excitation
and a progressive phase constant φ. . . . . . . . . . . . . . . . . . . . .
2.22 Array factor of a 4-element antenna array fed in-phase and with dE = λ/2.
2.23 Array factor of a λo /2 4-element antenna array fed with a progressive
phase shift of ±90o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.24 Rectangular microstrip patch antenna fed with a microstrip TL . . . . .
2.25 Inset-fed rectangular microstrip patch antenna. . . . . . . . . . . . . .
2.26 Elevation plane gain plot for a 2.4GHz rectangular microstrip patch
antenna: (a) in the y-z plane, (b) in the x-z plane. . . . . . . . . . . . .
2.27 A 4-element parallel-fed antenna array. . . . . . . . . . . . . . . . . . .
2.28 A 4-element corporate-fed antenna array. . . . . . . . . . . . . . . . . .
2.29 A basic 4-element series-fed antenna array. . . . . . . . . . . . . . . . .
2.30 A 4-element series-fed traveling wave in-line antenna array using a termination load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.31 A 4-element series-fed traveling wave out-of-line antenna array without
a termination load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
Gyrator-C architecture and its equivalent circuit. . . . . . . . . . . . .
Function f (RS ) versus the negative series resistance RS . . . . . . . . .
Modified gyrator-C loop and its equivalent circuit. . . . . . . . . . . . .
The modified differential gyrator-C architecture. . . . . . . . . . . . . .
Proposed TAI circuit with the tunable feedback resistance. . . . . . . .
Digital/analog feedback resistance Rf . . . . . . . . . . . . . . . . . . .
Grounded active inductor equivalent circuit. . . . . . . . . . . . . . . .
Simplified TAI schematic with the main current and voltage noise sources,
and equivalent lumped noise current model. . . . . . . . . . . . . . . .
Tunable active inductor die micrograph. . . . . . . . . . . . . . . . . .
xiii
24
25
27
29
30
32
33
35
36
37
37
40
41
42
43
44
45
47
47
48
49
49
54
57
58
61
62
64
65
67
68
List of Figures
3.10 Measured TAI characteristics versus frequency when VC1 =0V and VC2
changes from 0.3V to 0.6V: (a) Inductance, (b) Quality factor. . . . . .
3.11 Measured TAI characteristics versus frequency when VC1 =0.1V and VC2
changes from 0.3V to 0.6V: (a) Inductance, (b) Quality factor. . . . . .
3.12 Measured TAI characteristics versus frequency when VC1 =0.2V and VC2
changes from 0.3V to 0.4V: (a) Inductance, (b) Quality factor. . . . . .
3.13 Measured TAI characteristics versus frequency when VC1 changes from
0V to 0.4V and VC2 =0.3V: (a) Inductance, (b) Quality factor. . . . . .
3.14 Theoretical and measured self-resonance frequency, fr , versus the inductance, L, for the different bias conditions. . . . . . . . . . . . . . . . . .
3.15 Theoretical and measured peak quality factor frequency, fQ , versus the
self-resonance frequency, fr . . . . . . . . . . . . . . . . . . . . . . . . .
3.16 Measured Q versus frequency for different feedback voltages Vf . . . . .
3.17 Measured S11 of the TAI for different feedback voltages Vf . . . . . . . .
3.18 Measured and simulated results versus frequency when VC1 =0V and VC2
is set to 0.6V and 0.4V: (a) inductance (b) series resistance. . . . . . .
3.19 Circuit setup used for the simulation of the TAI circuit. . . . . . . . . .
3.20 Experimental test setup used for characterizing the TAI circuit linearity.
3.21 Amplitude of the power reflected back by the TAI versus the input power
when applying a single RF signal source. . . . . . . . . . . . . . . . .
3.22 Amplitude of the power reflected back by the TAI at f1 and 2f1 − f2
versus the input power when combining two RF signal sources. . . . . .
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
4.12
4.13
4.14
4.15
70
71
71
72
73
73
75
75
77
77
78
79
80
Different series-fed phased array designs and their radiation patterns. . 84
High-pass phase shifter unit-cell. . . . . . . . . . . . . . . . . . . . . . . 87
Phase tuning range versus the capacitor tuning ratio rC . . . . . . . . . 89
Proposed high-pass phase shifter circuit implementation. . . . . . . . . 90
High-pass phase shifter die micrograph . . . . . . . . . . . . . . . . . . 91
Measured phase vs. freq., for different bias conditions . . . . . . . . . . 92
Measured S11 and S21 vs. freq., for different bias conditions . . . . . . . 93
Measured phase and S21 at 4GHz vs. VB . . . . . . . . . . . . . . . . . 93
Measured S21 at 4GHz versus the feedback voltage Vf . . . . . . . . . 94
Amplitude of the output power versus the input power when applying a
single 4GHz RF signal source . . . . . . . . . . . . . . . . . . . . . . . 95
Amplitude of the output power at f1 and 2f1 −f2 versus the input power
when combining two RF signal sources . . . . . . . . . . . . . . . . . . 95
TL PRI/NRI metamaterial phase shifter unit-cell. . . . . . . . . . . . . 97
TL PRI/NRI metamaterial phase shifter unit-cell. . . . . . . . . . . . . 99
Photograph of the tunable PRI/NRI phase shifter unit-cell. . . . . . . . 100
The measured and theoretical phase responses vs. freq. for different bias
conditions. The phase expression of Eq.(4.10) is used for the comparison. 101
xiv
List of Figures
4.16
4.17
4.18
4.19
4.20
4.21
4.22
4.23
4.24
4.25
4.26
4.27
4.28
4.29
4.30
4.31
4.32
4.33
Measured S11 vs. freq. for different bias conditions. . . . . . . . . . . . 102
Measured S21 vs. freq. for different bias conditions. . . . . . . . . . . . 102
Proposed IC PRI/NRI metamaterial phase shifter unit-cell. . . . . . . . 104
Dispersion diagram of the periodic structure composed of the proposed
MMIC PRI/NRI phase shifter unit-cells. . . . . . . . . . . . . . . . . . 106
Proposed IC PRI/NRI metamaterial phase shifter unit-cell. . . . . . . . 109
MMIC PRI/NRI metamaterial phase shifter die micrograph. . . . . . . 110
The measured and theoretical phase responses vs. freq. for different bias
conditions. The phase expression of Eq.(4.19) is used for the comparison. 111
Measured S11 vs. freq. for different bias conditions. . . . . . . . . . . . 112
Measured S21 vs. freq. for different bias conditions. . . . . . . . . . . . 112
Measured S21 and phase shift φ at 2.6GHz versus the TAI feedback
voltage Vf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Unit cell of the proposed MMIC PRI/NRI tunable phase shifter. . . . . 115
Dispersion diagram of the periodic structure composed of the proposed
passive PRI/NRI MMIC unit-cells. . . . . . . . . . . . . . . . . . . . . 117
Proposed passive MMIC PRI/NRI phase shifter circuit implementation. 119
Phase MMIC PRI/NRI shifter die micrograph . . . . . . . . . . . . . . 121
Measured phase vs. freq., for different bias conditions . . . . . . . . . . 122
Measured S11 and S21 vs. freq., for different bias conditions . . . . . . . 122
Measured phase and S21 at 2.6GHz vs. the varactor reverse bias voltage
VB1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
The measured group delays of the metamaterial phase shifter and the
simulated group delay of two cascaded 2nd -order all-pass filters . . . . . 129
5.1
Block diagram of a 4-port directional coupler configured in: (a) the
forward mode of operation, and (b) the backward mode of operation. . 132
5.2 The high-pass topology used by the proposed MMIC directional coupler. 135
5.3 The equivalent circuit with even-mode excitation. . . . . . . . . . . . . 135
5.4 The equivalent circuit with odd-mode excitation. . . . . . . . . . . . . 136
5.5 Series capacitance C2 and the shunt inductance L required to satisfy the
conditions of Eq.(5.9) and Eq.(5.10) versus the series capacitance C1 . . 139
5.6 Coupling coefficients achieved by the MMIC coupler circuit . . . . . . . 139
5.7 Operating frequency of the MMIC coupler and the series capacitance C1
versus the shunt inductance L. . . . . . . . . . . . . . . . . . . . . . . . 142
5.8 Proposed lumped-element MMIC directional coupler circuit implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
5.9 MMIC directional coupler die micrograph. . . . . . . . . . . . . . . . . 147
5.10 Measured and theoretical coupling coefficients C vs. freq. for different
bias conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
5.11 Measured isolation S41 vs. freq. for the same bias conditions as Fig. 5.10.149
xv
List of Figures
5.12 Measured reflection coefficient S11 vs. freq. for the same bias conditions
as Fig. 5.10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.13 Measured and theoretical S41 vs. freq., for different bias conditions . .
5.14 Measured S11 vs. freq., for different bias conditions . . . . . . . . . . .
5.15 Measured S21 and S31 to the left and S41 to the right vs. the coupler
operating frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.16 Measured MMIC coupler S-parameters vs. frequency. Case 1: forward
operation, the input power is equally divided between ports 3 and 2
while port 4 is isolated. . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.17 Measured MMIC coupler S-parameters vs. frequency. Case 2: backward
operation, the input power is equally divided between ports 3 and 4 while
port 2 is isolated. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.18 Differential phase response of the MMIC coupler vs. frequency for the
forward and the backward modes of operation. . . . . . . . . . . . . . .
5.19 Duplexer operation (a) Receive mode is achieved by configuring the coupler in the forward mode. (b) Transmit mode is achieved by configuring
the coupler in the backward mode. . . . . . . . . . . . . . . . . . . . .
5.20 Measured S21 and S31 at 2.6GHz on the left and S41 at 2.6GHz on the
right vs. the input power level. . . . . . . . . . . . . . . . . . . . . . .
5.21 Block diagram of a 3dB coupler with the noise current sources representing the effect of the active circuits within the TAIs. . . . . . . . . .
6.1
6.2
6.3
150
153
154
155
158
158
159
160
161
163
Basic 4-element series-fed antenna array. . . . . . . . . . . . . . . . . . 169
4-element series-fed antenna array with λ/4 impedance transformers. . 169
Alternating patch array diagram indicating the required ideal power
splitting ratios and all the λ/4 transformer impedances. . . . . . . . . . 171
6.4 Power mismatch between the first and fourth antennas versus the interstage phase shifter insertion loss. . . . . . . . . . . . . . . . . . . . . . 175
6.5 Normalized array factors for a 4-element λo /2 antenna array. . . . . . . 175
6.6 Transmission-line tunable PRI/NRI metamaterial phase shifter unit-cell. 177
6.7 Photograph of the fabricated tunable TL PRI/NRI interstage phase shifter.183
6.8 The measured insertion phase φP S vs. freq. for different bias conditions. 184
6.9 Measured S21 and S11 at 2.4GHz versus the insertion phase of the interstage phase shifter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
6.10 Photograph of the fabricated electronically steerable series-fed patch array utilizing the tunable TL PRI/NRI interstage phase shifters. . . . . 186
6.11 Measured co- and cross-polarization and simulated co-polarization gain
patterns in the azimuth plane (x-z plane) for different bias conditions. . 189
6.12 Measured peak gain of the antenna array and the half-power beamwidth
versus the scan angle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
xvi
List of Figures
6.13 Measured co- and cross-polarization and simulated gain patterns in the
y-z plane. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.14 Input return loss, S11 , of the antenna array versus frequency for all the
different bias conditions given by Fig. 6.11. . . . . . . . . . . . . . . . .
6.15 Beam squinting characteristics: antenna array main-lobe angle, θp , and
the peak gain, Gp , versus frequency. . . . . . . . . . . . . . . . . . . . .
6.16 Experimental setup used to characterize the linearity of the steerable
antenna array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.17 Measured output power, Pout , of the horn antenna at 2.4GHz versus the
antenna array input power Pin . . . . . . . . . . . . . . . . . . . . . . .
6.18 Measured horn output power at the fundamental frequency f1 and at
third-order intermodulation frequency 2f1 − f2 versus the antenna array
input power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
191
192
193
195
195
196
B-1 Flow chart showing the procedure used to simulate the TL PRI/NRI
metamaterial phase shifters. . . . . . . . . . . . . . . . . . . . . . . . . 211
B-2 Flow chart showing the procedure used to simulate the steerable antenna
array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
xvii
List of Tables
2.1
2.2
3.1
3.2
3.3
3.4
4.1
4.2
4.3
4.4
4.5
4.6
5.1
5.2
5.3
Comparison Between Different Directional Coupler Topologies. . . . . .
Comparison Between Different Antenna Array Feed Network Topologies
And The Requirements On The Interstage Phase Shifters. . . . . . . .
Transistor Sizes of the TAI Circuit . . . . . . . . . . . . . . . . . . . .
Transistor Sizes of the Digital/Analog Tunable Feedback Resistance Rf
Measured Inductances for the TAI at 2GHz for Different Values of the
Bias Voltages VC1 and VC2 . . . . . . . . . . . . . . . . . . . . . . . . . .
Comparison Between Different Tunable Active Inductor Implementations
39
51
63
63
70
81
Summary of The High-Pass Phase Shifter Performance. . . . . . . . . . 96
Summary of the TL PRI/NRI Phase Shifter Performance. . . . . . . . 103
Summary of the TAI-Based MMIC PRI/NRI Phase Shifter Performance. 114
Summary of the Passive MMIC PRI/NRI Phase Shifter Performance. . 124
Comparison Between Different Phase Shifter Designs Presented In This
Chapter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Comparison Between Different PRI/NRI Phase Shifter Implementations 127
Comparison Between the Proposed MMIC Directional Coupler and Other
Variable Coupling Coefficient Couplers . . . . . . . . . . . . . . . . . . 152
Comparison Between the Proposed MMIC Coupler and Other Couplers
with Variable Operating Frequency . . . . . . . . . . . . . . . . . . . . 156
Linearity Comparison Between Different TAI based Couplers . . . . . . 161
xviii
List of Tables
6.1
6.2
6.3
Series Feed Network Efficiency For Different Interstage Phase Shifter
Loss Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Comparison Between The Proposed Steerable Patch Array And Other
Published Series-Fed Steerable Antenna Arrays. . . . . . . . . . . . . . 198
Comparison Between The Measured Beam Squinting Of The Proposed
Array And Other Published Antenna Arrays. . . . . . . . . . . . . . . . 200
xix
List of Acronyms
1-D
One-Dimensional
2-D
Two-Dimensional
BiCMOS Bipolar Complementary Metal Oxide Semiconductor
BW
Bandwidth
CD
Common-Drain
CG
Common-Gate
CMOS
Complementary Metal Oxide Semiconductor
CPW
Co-Planar Waveguide
CS
Common-Source
DAC
digital-to-analog converter
FOM
Figure-of-merit
GaAs
Gallium Arsenide
GSG
Ground-Signal-Ground
GSGSG
Ground-Signal-Ground-Signal-Ground
HPBW
Half Power Beamwidth
xx
List of Acronyms
IC
Integrated Circuit
ISM
Industrial, Scientific and Medical
LHM
Left-Handed Medium
LNA
Low-Noise Amplifier
MEMS
Micro-electromechanical systems
MESFET Metal-Semiconductor Field Effect Transistor
MIM
Metal-Insulator-Metal
MMIC
Monolithic Microwave Integrated Circuit
NF
Noise Figure
NMOS
N-channel Metal Oxide Semiconductor
NRI
Negative Refractive Index
PCB
Printed Circuit Board
PIFA
Planar Inverted F Antenna
PMOS
P-channel Metal Oxide Semiconductor
PRI
Positive Refractive Index
QFN
Quad Flat-Pack No Lead
TAI
Tunable Active Inductor
TL
Transmission-Line
TX
Transmitter
RF
Radio Frequency
RHM
Right-Handed Medium
RX
Receiver
SiGe
Silicon Germanium
WSN
Wireless Sensor Network
xxi
List of Symbols
AF
β
c
C
C
dE
dP S
D
²r
²ef f
E
EF
f
ft
φ
gm
G
γ
Γe,o
h
H
i2nMx
I
k
L
Antenna array factor
Propagation constant
Speed of light
Directional coupler coupling coefficient
Capacitance
Inter-element distance
Phase shifter length
Directional coupler directivity
Relative dielectric constant
Effective relative dielectric constant
Electric field
Antenna element factor
Frequency
Transistor unity-gain frequency
Phase shift
Transconductance
Interstage phase shifter absolute power gain
Transistor noise coefficient
Reflection coefficient for even- and odd-mode circuits
Substrate height
Magnetic field
mean-square value of the drain current thermal noise for transistor Mx
Current
Boltzmann constant
Inductance
xxii
List of Symbols
λ
nf
ηf eed
N
P
Q
QP
rC
rL
ro
R
RS
s
S11
Sxy
T
Te,o
Tgd
θ
2
vnR
x
V
VDS,sat
VEF
VGS
VT H
W
Wf
ω
ωo
ωp
ωr
X
Z
ZA
Zo
ZP S
ZT
Wavelength
Number of transistor fingers
Feed network efficiency
Number of antenna array elements
power
Tunable active inductor quality factor
Peak-Q
Capacitance tuning ratio
Inductance tuning ratio
Transistor small-signal output resistance
Resistance
Tunable active inductor series resistance
Complex frequency variable
Input reflection coefficient
Transmission coefficient from port x to port y
Temperature
Transmission coefficient for even- and odd-mode circuits
Phase shifter group delay
Angle of antenna array main beam
mean-square value of the thermal noise voltage for resistor Rx
Voltage
Transistor saturation drain-source voltage
Transistor overdrive voltage
Transistor gate-source voltage
Transistor threshold voltage
Patch antenna width
Transistor finger width
Angular frequency
Zero phase frequency
Tunable active inductor peak-Q frequency
Tunable active inductor resonance frequency
Susceptance
Impedance
Antenna impedance
Characteristic impedance
Phase shifter impedance
λ/4 transformer impedance
xxiii
CHAPTER
1
Introduction
1.1 Overview
W
ireless communications is one of the major foundations of the current revolution
in information technology. Due to its unlicensed nature, the 2.4-2.5GHz industrial, scientific and medical (ISM) band has become a popular choice for a variety of
wireless applications. Unfortunately, this popularity is causing congestion, resulting in
more interference and eventually degrading the performance of wireless links. Furthermore, the increasing level of interference from the neighboring wireless devices imposes
tough constraints on the transceiver design, starting with the specified level for the
transmitted power and ending with the specified receiver noise figure. To meet the
required performance from a wireless link, and at the same time relax the transceiver
design constraints, one can utilize the principle of phased antenna arrays.
1.2 Phased Antenna Array Front-Ends
Phased antenna arrays are capable of producing narrow, high-gain beams compared
to omni-directional antennas. In a phased array wireless link, the transmitted power
1
1.2. PHASED ANTENNA ARRAY FRONT-ENDS
Wireless access
point
Interference
TX
2
TX
RX
Interference
RX
(a)
(b)
Figure 1.1: Wireless network established between wireless device and access point in
the presence of interferers. (a) In this case, all devices use omni-directional
antennas, (b) In this case, the wireless device under consideration uses a
phased antenna array, resulting in a narrow and steerable beam.
is focused towards the intended wireless device, and at the same time, the receiving
device is focused in the direction of the transmitting device. This is illustrated in
Fig. 1.1-a and Fig. 1.1-b, which show qualitatively how the effect of interference from
the neighboring devices and the effect of noise from the surrounding environment can
be reduced by deploying phased antenna arrays. This will result in higher signal to
noise ratios, leading to lower bit-error rates. It is also worth mentioning that, using
phased antenna arrays reduces the effects of issues such as multi-path fading.
A simplified block diagram of a transceiver front-end utilizing a phased antenna array is shown in Fig. 1.2. The electronic beam steering network is required to feed the
different antennas with the appropriate signal amplitudes and phases by utilizing electronically tunable phase shifters. Currently, the use of phased arrays is largely limited
to high-precision military radar systems and satellite communications due to the lack
of compact, broadband, electronically tunable phase shifters that are cost-effective and
can easily be integrated onto the same printed circuit board (PCB) with printed antennas. Furthermore, the large area occupied by the beam steering network of parallel-fed
arrays, which are, to date, the dominant choice for high data-rate applications, has also
been a deterring factor for deploying phased arrays in wireless consumer applications.
1.2. PHASED ANTENNA ARRAY FRONT-ENDS
3
Electronic Beam Steering
RX
TX
Duplexer
Power
Amplifier
Power monitoring
Low Noise
Amplifier
RSSI
Transceiver
Figure 1.2: A transceiver front-end employing a phased antenna array.
The beam steering network of series-fed arrays, on the other hand, is very compact, but
suffers from large beam squinting1 with frequency. However, with the recent developments in the field of metamaterials, there is the potential to design compact, broadband
phase shifters suitable for series-fed antenna arrays, allowing their deployment in high
data-rate wireless consumer applications.
Metamaterials are artificial dielectrics that display electromagnetic properties that
do not exist in naturally occurring materials: for example, simultaneous negative permittivity and permeability. Consequently, they can possess a negative index of refraction (NRI). For radio frequency (RF) applications, the interest in metamaterials was
sparked by their compact planar implementation proposed in 2002 [3, 4], which allows
for its integration with various RF and microwave electronic systems. Fig. 1.3 shows a
photograph reproduced from [2] of a 2-D metamaterial. The unit-cell of this 2-D NRI
metamaterial is comprised of two microstrip TLs loaded with series capacitors and a
shunt inductor. Metamaterials concepts have been used to develop compact, broadband phase shifters with small and relatively flat group delays [5]. These phase shifters
are designed by cascading multiple 1-D unit-cells of a NRI metamaterial. The compact
implementation of these metamaterial phase shifters, which is illustrated in Fig. 1.4,
1
Beam squinting is defined here as the variation in the angle of the main beam of the antenna array
with frequency.
1.2. PHASED ANTENNA ARRAY FRONT-ENDS
4
Figure 1.3: Prototype of a 2-D interface between a region with positive permittivity and
permeability (left-side) and a NRI region (right-side). Picture reproduced
from [2]. The inset magnifies a single unit cell of the NRI region, consisting
of a microstrip grid loaded with surface-mounted capacitors and an inductor
embedded into the substrate at the central node.
Metamaterial phase shifters
Conventional 360o TL phase shifter
Figure 1.4: Single-stage, two-stage, four-stage, and eight-stage metamaterial phase
shifters compared to a conventional TL phase shifter. Picture reproduced
from [5].
1.3. THESIS SCOPE AND OUTLINE
5
is necessary for the beam steering networks of series-fed antenna arrays. Furthermore,
the low group delay of metamaterial phase shifters will result in smaller variations in
the direction of the array’s main beam across the operating bandwidth [6], which makes
them suitable for high date-rate applications. However, until now, metamaterial phase
shifters have utilized discrete, or printed capacitors and inductors having fixed values,
and as such, are not tunable. By utilizing the capabilities offered by CMOS monolithic
microwave integrated circuits (MMICs) to replace the fixed capacitors and inductors
with tunable ones, the phase response of these metamaterial phase shifters would potentially be electronically tuned. Besides tunability, utilizing CMOS MMIC technology
would result in a more compact implementation compared to current, TL-based implementations. These compact, electronically tunable metamaterial phase shifters could
then be integrated within the feed network of series-fed antenna arrays. This would allow implementing the antenna array with the beam steering network on a single planar
PCB, making it more appealing for high data-rate wireless consumer applications.
The benefits of tunability could also extend to the duplexer. The duplexer in the
phased array front-end of Fig. 1.2 operates as a switch, and is a necessary component in
the transceiver front-end to allow sharing the same antenna array between the transmitter and the receiver. However, duplexers are usually designed using discrete, or
printed components. Hence, duplexers are bulky and are not tunable. If the duplexers
could be made tunable, transceivers could be made to support multi-standard operation. This can also be achieved by using CMOS MMICs to design highly-reconfigurable
compact duplexers, which in the future will allow their integrating the duplexer with
the transceiver front-end on a single CMOS integrated circuit (IC). Moreover, the transmitted and received power could be monitored by replacing the 3-port duplexer with
a 4-port highly-reconfigurable directional coupler. This would allow for precise control
over the level of the TX power and the gain of the low-noise amplifier.
1.3 Thesis Scope and Outline
This thesis investigates the design of RF tunable active inductors (TAIs), and their
application in the design of tunable phase shifters, directional couplers, and steerable
antenna arrays. An electronically tunable version of the compact, broadband, TL metamaterial phase shifter is presented. Furthermore, two novel fully-integrated, tunable,
1.3. THESIS SCOPE AND OUTLINE
6
versions of the metamaterial phase shifter are presented in this thesis. Tunability is
achieved by combining the use of varactors and TAIs. The thesis also presents the
design of a compact, CMOS MMIC, highly-reconfigurable, directional coupler to replace the duplexer in wireless transceiver front-ends, and at the same time allow for
multi-standard operation as well as power monitoring. Similar to the tunable phase
shifters, the proposed MMIC directional coupler combines the use of varactors and
TAIs. Since the TAI plays a major role in the design of both the phase shifters and
the directional coupler, this thesis also presents a design methodology for TAIs that
allows independently tuning its inductance (L) and quality factor (Q). Tuning L and
Q independently is a key feature to overcome the degradation of the insertion loss and
return loss of the TAI-based circuits while electronically tuning their response. In addition, the tunable metamaterial phase shifters presented in this thesis are used to design
the beam steering network of a series-fed patch array, and electronic beam steering is
demonstrated using a prototype antenna array.
Chapter 2 of this thesis starts by briefly summarizing the recent developments in
the field of metamaterials and its applications. Following that, it gives the necessary
background information about TAIs, phase shifters, directional couplers, and phased
antenna arrays.
Chapter 3 presents a design methodology for RF TAIs that allows independent tuning
of their L and Q, by using a modified gyrator-C architecture with an additional feedback element. The proposed Q-enhancement technique is generalized for the gyrator-C
architecture, which makes it applicable to any gyrator-C based TAI. To verify the proposed architecture, a novel grounded TAI design is presented along with the simulation
and experimental results.
In chapter 4, TL-based and fully-integrated versions of electronically tunable metamaterial phase shifters are presented. The TL-based phase shifters presented in this
thesis have evolved from the metamaterial phase shifter topology presented in [5] by
replacing the fixed, discrete components with IC, tunable, active elements (i.e. varactors and the TAIs presented in chapter 3). Combining the use of varactors and TAIs
results in a wide phase tuning range, and allows the phase shifters to achieve a very
low return loss across their entire tuning range. To the author’s knowledge, the CMOS
MMIC designs presented in this chapter are considered the first attempts to design
fully-integrated, tunable, metamaterial phase shifters in a standard CMOS process.
1.3. THESIS SCOPE AND OUTLINE
7
Following that, a novel CMOS MMIC, highly-reconfigurable directional coupler is
presented in chapter 5. The directional coupler uses varactors and the TAIs presented
in chapter 3 to allow extensive electronic control over the coupling coefficient. At
the same time, this allows the coupler to be re-configured for operation over a wide
range of frequencies. To the author’s knowledge, this is the first coupler that combines
those two features; i.e. simultaneously providing a tunable coupling coefficient and
a tunable operating frequency. Moreover, the symmetric configuration of the coupler
allows it to switch from forward to backward operation by simply exchanging the bias
voltages applied to the varactors. This makes the proposed directional coupler ideal to
replace the bulky passive duplexers in transceiver front-ends, enabling multi-standard
operation as well as power monitoring.
Chapter 6 presents a planar electronically steerable series-fed patch array for 2.4GHz
ISM band applications. The proposed steerable array uses the tunable TL metamaterial phase shifters, presented in chapter 4, to center its radiation about the broadside
direction and allow scanning in both directions off the broadside. Also, using the metamaterial phase shifters reduces the squinting of the main beam across the operating
bandwidth. The feed network of the proposed array uses λ/4 impedance transformers.
This allows using identical interstage phase shifters, which share the same control voltages to tune all stages. Furthermore, using the impedance transformers in combination
with the CMOS-based, constant-impedance metamaterial phase shifters guarantees a
low return loss for the antenna array across its entire scan angle range. To the author’s
knowledge, the proposed antenna array is the first resonant antenna-element structure that demonstrates electronic beam steering utilizing tunable metamaterial phase
shifters.
Finally, Chapter 7 concludes the thesis and suggests directions for future research.
CHAPTER
2
Background
This chapter reviews the basic concepts in topics related to the work presented in this
thesis. This chapter does not present new material and readers can skip it and proceed
to chapter 3 for the main contributions of the thesis.
2.1 Metamaterials
A
metamaterial is a broad word referring to any artificial material having properties
that are not found in nature. It stems from the Greek word meta meaning beyond.
Throughout this thesis, the term metamaterial will refer to mediums possessing a
negative permeability simultaneously with a negative permittivity.
2.1.1 History
In 1968, Veselago proposed that materials with simultaneously negative permeability
and permittivity will provide a negative index of refraction [7]. Furthermore, in such
a medium, the electric field, E, the magnetic field, H, and the propagation vector, k,
will form a left-handed triplet instead of a right-handed one, thus it can also be termed
8
2.1. METAMATERIALS
9
Figure 2.1: Photograph of the lefthanded metamaterial (LHM) sample, reproduced
from [1]. The LHM sample consists of square copper split ring resonators
and copper wire strips on fiber glass circuit board material. The rings and
wires are on opposite sides of the boards.
a left-handed medium. However, their realization was not possible before 1999 when
Pendry et al. showed how to realize a negative permeability from a split ring resonator
structure [8]. Following that, Smith et al. showed a composite 3-dimensional (3-D)
material that exhibits simultaneously negative permittivity and permeability [1, 9].
These structures use strip wires to realize the negative permittivity and use split ring
resonators to synthesize the negative permeability [8]. The dimensions of the split
ring resonators and strip wires determine their resonance frequencies and hence the
overlapping regions with negative permittivity and permeability [1,9]. Figure 2.1 shows
a photograph reproduced from [1] of a 3-D NRI medium based on an array of split
ring resonators and strip wires. The dependence on the resonance of the split ring
resonators to synthesize a negative permeability makes the NRI medium inherently
narrow-band, the design presented in [1] shows a negative index of refraction over a
range of frequencies from 10.2GHz to 10.8GHz. Furthermore, the implementation of
the 3-D NRI medium is quite bulky.
In his paper, Veselago pointed out many interesting phenomena related to wave
propagation in NRI metamaterials, such as: reversed refraction, or, in different terms,
inverted Snell’s law, and reversed Doppler effect. Hence, metamaterials moved from
a theoretical concept to a practically realizable medium, and their reverse refraction
characteristic made them suitable for focusing electromagnetic waves at a PRI1 /NRI
boundary with sub-wavelength resolving properties. This idea was proposed in 2000
2.1. METAMATERIALS
10
when a 3-D NRI metamaterial lens was presented in [10]. However, metamaterials still
remained bulky 3-D structures, which hindered their application within various RF
and microwave electronic systems.
In 2002, Eleftheriades et al. proposed a new approach to build a 2-dimensional
(2-D) NRI metamaterial by periodically loading TLs with series capacitors and shunt
inductors [11], thus replacing the bulky 3-D wire strips and split ring resonators by a 2D planar design. The same method was also proposed by another group at UCLA [12].
A photograph of a 2-D metamaterial designed using microstrip lines as the host TLs is
shown in chapter 1 in Fig. 1.3. The unit-cell of this NRI metamaterial is comprised of
microstrip TLs loaded with series capacitors and a shunt inductor. These developments
allowed the first experimental demonstration of focusing from a planar 2-D PRI/NRI
interface [3]. Following this, interest in NRI metamaterials was sparked in the RF and
microwave community.
2.1.2 Metamaterial Applications
Novel RF and microwave circuits were designed utilizing the additional degree of freedom offered by NRI media, such as building compact broadband TL PRI/NRI zerodegree phase shifters with small and relatively flat group delays [5]. These phase shifters
are designed by cascading the 1-D version of the unit-cell shown in Fig. 1.3 to create
a 1-D metamaterial line. One application that would benefit from these PRI/NRI
phase shifters is series-fed antenna arrays, as will be described in more detail throughout this thesis. Furthermore, broadband PRI/NRI series power dividers have been
proposed in [13] to feed loads in phase that are not electrically close to each other.
Directional couplers can also benefit from the advances in planar NRI metamaterials;
a dual-frequency branch-line coupler was presented in [14] and two high directivity
coupled-line couplers were presented in [15] and [16]. Moreover, it was demonstrated
in [17] that one of the dimensions of a coupler can be significantly reduced by coupling
the electromagnetic power between a NRI line and a PRI TL as opposed to a conventional coupler design in which power is coupled between two PRI TLs. The compact
planar metamaterial implementation also enabled other applications, such as the leaky
1
PRI stands for a positive-refractive-index media, which corresponds to having a positive permittivity
and permeability.
2.2. TUNABLE INDUCTORS
11
backward-wave antennas presented in [18]. Also, electrically-small, metamaterial-based
antennas have recently been presented in [19, 20]. Hence, the field of metamaterials
appears to have much potential for both RF and microwave applications.
Electronically tuning the characteristics of metamaterials, by replacing the fixed series capacitors and shunt inductors with electronically tunable capacitors and inductors,
can provide re-configurability to all the different metamaterial applications. Furthermore, this may open-up a whole new range of applications, such as designing planar
RF lenses which posses a tunable focal length. Since tunable capacitors can easily be
obtained by using varactors, the next section will focus instead on techniques used to
design tunable inductors.
2.2 Tunable Inductors
The most widely used method to design printed inductors on PCBs or integrated inductors in current IC technologies is by means of planar spirals. However, the inductance
of spiral inductors is a function of their geometry. Hence, spiral inductors provide only
fixed inductances.
2.2.1 MEMS Tunable Inductors
Micro-electromechanical systems (MEMS) have demonstrated the capability of synthesizing RF tunable inductors. For instance, a MEMS tunable RF inductor is presented
in [21], which consists of two loops self-assembled with a specific angle between them.
By controlling the ambient temperature of the inductor, this angle and hence the effective distance between the two loops can be varied, which in turn changes the mutual
inductance component. This, however, results in a limited inductance tuning range;
0.83-0.65nH at 4GHz for varying the temperature from 25o C to 200o C, respectively,
and a low Q of 6, where Q is a measure of the efficiency of an inductor, and is given
by Im(Zin )/Re(Zin ).
In another more recently published paper [22], an electronically tunable MEMS inductor was presented. This inductor is composed of an aluminum layer micro-machined
on top of an amorphus silicon layer. The tunability of the inductor is based on the
bimorph effect, which can be explained as follows. When a voltage is applied across
2.2. TUNABLE INDUCTORS
12
the inductor, its structure deforms in a controllable manner, which occurs due to difference in the thermal expansion coefficients of the two layers. The inductor achieves
a 6.5-9.8nH tuning range at 3GHz, and achieves quality factors ranging from 5 to 15
respectively. However, the inductor dissipates 220mW to actuate the necessary deformation in its structure. This power is required to raise the temperature of the
structure.
Although MEMS tunable inductors, in general, can provide high self-resonance frequencies and high-speed operation, most of them use thermal effects to tune the inductance. This dramatically reduces the speed of switching, which is the time required
to change the inductance from one value to another. Furthermore, most of the MEMS
inductors rely on vertical movements to tune their inductance. Consequently, the resulting 3-D moving structures make it challenging to package and to integrate MEMS
inductors with electronic circuits fabricated in a standard CMOS process.
2.2.2 Varactor-Based Tunable Inductors
Another common method to tune the inductance of IC spirals is to use varactors.
By connecting a varactor in series, or in shunt, with a fixed spiral inductor, one can
tune the effective inductance by varying the bias voltage applied across the varactor.
On such example is demonstrated in [23], where a series varactor is used to tune the
inductance of a 2-port, i.e. series, spiral inductor to design a tunable phase shifter.
However, this technique is only valid over a very narrow-band of frequencies (with
fractional bandwidths of 10%-20% as reported in [23]), since the effective inductance
can only be assumed constant over a narrow-band of frequencies. This is a result of the
direct relation between the effective inductance and the frequency, which for a shunt
connection is given by:
1
(2.1)
Lef f = L − 2 ,
ω C
where L and C are the fixed spiral inductance and the tunable varactor capacitance respectively. Furthermore, this technique results in low quality factors, since the effective
Q is limited by the low-Q of the IC spiral inductors.
2.2. TUNABLE INDUCTORS
in
13
/4
CL
Figure 2.2: Tunable TL inductor designed by terminating λ/4 TL with a tunable capacitor.
2.2.3 Transmission-Line Tunable Inductors
Another very simple approach to build tunable inductors can be derived from the basic
TL model. Terminating a λ/4 TL with an arbitrary impedance ZL , where λ = c/f
is the wave-length, c is the speed of light, and f is the design frequency, results in an
input impedance of:
Z2
(2.2)
Zin = o ,
ZL
where Zo is the characteristic impedance of the TL [24]. As Eq.(2.2) indicates, a λ/4
TL acts as an impedance inverter. Hence, loading this TL with a capacitor results in
an inductive input impedance, with an inductance of:
L = Zo2 CL ,
(2.3)
where CL is the load capacitance. Furthermore, the inductance can be tuned by replacing the fixed capacitor with a varactor as shown in Fig. 2.2. Although this technique
might seem unsuitable for IC designs due to the need for TLs, when operating at high
frequencies the TL size becomes practical for IC implementations. However, this technique results in very narrow band inductors; since Eq.(2.2) is only valid at the design
frequency f , which limits its applicability.
2.2.4 Gyrator-C Tunable Inductors
The most popular technique used to build tunable synthetic inductors is by terminating
a gyrator with a capacitive load. This technique has greatly benefited from the advances
in modern CMOS technologies, which are now capable of providing transistors with very
high unity-gain frequencies (ft ), allowing the design of RF TAIs. The use of RF TAIs
have been demonstrated in numerous applications. For instance, they were used by
2.2. TUNABLE INDUCTORS
14
+ I2
I1 +
I1 +
+ I2
V1
V2
V1
V2
-
-
-
-
(a)
CL
(b)
Figure 2.3: Circuit symbol of the gyrator, showing the polarities and directions of the
port voltages and currents, respectively.
Mukhopadhyay et al. in [25] to design wide-tuning range voltage-controlled oscillators
(VCOs), they were also used by Wu et al. in [26] to design RF tunable filters, and
in [27] and [28] to design RF phase shifters and power dividers respectively.
History
The gyrator, of which circuit symbol is shown in Fig. 2.3-a was originally introduced
as a new circuit element in 1948 by Tellegen [29]. Using the standard 2-port network
representation, the impedance matrix of a gyrator can be defined as:
" # "
#" #
V1
0 −r1 I1
=
,
V2
r2 0
I2
(2.4)
where V1,2 and I1,2 are the voltage and current at ports 1 and 2 of the gyrator, respectively, as indicated in Fig. 2.3-a, and r1 and r2 are the gyration resistances. Terminating a gyrator with a load impedance ZL , as shown in Fig. 2.3-b, results in an input
impedance Zin , which is expressed as:
Zin =
r1 r2
.
ZL
(2.5)
Hence, terminating the circuit with a capacitive load CL results in an inductive input
impedance with an inductance L expressed as:
L = r1 r2 CL .
(2.6)
According to Eq.(2.6), the inductance of the circuit can simply be tuned by varying
either the load capacitance or the gyration resistances r1 or r2 . Hence, the gyrator-C
2.2. TUNABLE INDUCTORS
15
io1=gm1vin1
vin1
io1
gm1
gm1
V1
V2
I1
I2
CL
Zin
-gm2
-gm2
vin2
io2
io2=-gm2vin2
(a)
(b)
Figure 2.4: (a) Block diagram implementation of the gyrator using transconductors.
(b) Tunable active inductor designed by terminating the second port of the
gyrator with a capacitor.
architecture is capable of synthesizing a tunable inductance. The gyrator-C inductors
are termed active, since gyrators are implemented using active devices (transistors).
Furthermore, unlike Eq.(2.1), Eq.(2.5) is valid for all frequencies as long as the gyrator
characteristics can still be described by the impedance matrix of Eq.(2.4).
To the author’s knowledge, the first circuit implementation of a gyrator was presented
by Morse et al. in 1964, and was based on operational amplifiers [30]. The proposed
circuit implementation used four operational amplifiers. Following that, other designs
were presented in the literature trying to minimize the number of operational amplifiers required to implement the gyrators. For instance, the design in [31] was published
in 1971, and requires only two operational amplifiers. An alternative circuit implementation for a gyrator is to use two transconductors connected back-to-back (gm1
and gm2 ) as shown in Fig. 2.4-a. This approach was originally proposed by Sharpe
in 1957 [32], and the first circuit implementation of a such a circuit was presented
along with its experimental characterization in 1965 [33]. Using operational amplifiers initially seemed more attractive to build gyrators, due to their standard designs.
However, most of the RF TAIs presented in the literature use transconductors, since
this approach is more suitable for high-speed applications [25, 26, 34–43]. Hence, our
focus here is directed towards this latter approach to build TAIs, and throughout this
2.2. TUNABLE INDUCTORS
16
thesis, the term gyrator-C TAI will refer to the transconductor-based design. It is
worth mentioning that, the gyrator-C active inductor in Fig. 2.4-b is single-ended, or,
in other words, it represents a grounded inductor. Although the generalized gyrator-C
circuit in Fig. 2.3-b can produce 2-port, or floating, inductors, the difficulty of its implementations prohibits the design of 2-port active inductors. This will be one of the
main factors in the selection of the appropriate architectures for the TAI-based phase
shifters and the TAI-based coupler in chapters 4 and 5, respectively.
First-Order Analysis of Gyrator-C TAIs
Assuming ideal transconductors, one can show that the impedance matrix of the circuit
in Fig. 2.4-a is given by:
" #
V1
V2

0

= 1
gm2
−
1

" #
gm1  I1 .

I2
0
(2.7)
By comparing Eq.(2.7) with Eq.(2.4), it becomes evident that the circuit is equivalent
to a gyrator. Furthermore, terminating the circuit with a capacitive load CL , as shown
in Fig. 2.4-b, results in an inductive input impedance, and the inductance L can be
expressed as:
CL
.
(2.8)
L=
gm1 gm2
According to Eq.(2.8), the inductance of the circuit can simply be tuned by varying
the load capacitance CL , gm1 , or gm2 . This analysis assumes ideal transconductors with
infinite input and output impedances as well as zero input and output capacitances.
This results in an ideal inductor with an infinite Q, which is defined as:
Q=
Im(Zin )
,
Re(Zin )
(2.9)
where Zin is the input impedance of the gyrator-C circuit. A more detailed analysis of
the gyrator-C architecture will be presented in chapter 3 which takes into account the
second-order effects.
2.2. TUNABLE INDUCTORS
17
Vdd
Vdd
I1
Vdd
Vdd
I2
I1
M2
M2
M1
I2
Zin
M1
Zin
(a)
(b)
Figure 2.5: (a) CS-CD TAI using an NMOS-NMOS realization. (b) CS-CD TAI using
an NMOS-PMOS realization.
Overview of Transistor-Based Gyrator-C TAIs
The simplest implementation of a high-Q TAI can be obtained by replacing each
transconductor in Fig. 2.4 with a single-transistor transconductor2 . Only two different
combinations of transistor topologies are possible to maintain the negative feedback;
a common-source, common-drain topology (CS-CD), and a common-gate, commonsource topology (CG-CS). Using different combinations of NMOS and PMOS transistors results in eight different TAI circuit implementations. These eight different TAI
realizations are summarized in [34]. Figure 2.5-a shows the CS-CD topology using
an NMOS-NMOS realization, whereas Fig. 2.5-b shows the CS-CD topology using an
NMOS-PMOS realization. In either case, the capacitor CL , used to terminate the gyrator in Fig. 2.4, is removed and the circuit relies on the input capacitance of the second
transconductor instead, i.e. the capacitance at the gate of M2 . Eliminating CL and relying on the parasitic capacitance makes the TAI circuit capable of operating at higher
speeds. The circuit in Fig. 2.5-a was originally proposed in [45], and requires a minimum supply voltage of 2VGS + VDS,sat . The circuit in Fig. 2.5-b was originally proposed
in [46], and requires only VGS + 2VDS,sat making it more appealing for low-voltage oper2
Active inductors can also be designed using a single transistor. For example, in the presence of a
gate resistance the impedance looking into the source terminal of a common-drain amplifier, has
an inductive component [44]. However, this techniques are not suited for high-Q wide-tuning range
active inductors.
2.2. TUNABLE INDUCTORS
18
Vdd
Vdd
Vdd
I2
I1,2
M1
VB
M2
VB
M1
(a)
M2
Zin
I1+I2
Zin
(b)
Figure 2.6: (a) CG-CS TAI using an NMOS-NMOS realization. (b) CG-CS TAI using
an NMOS-PMOS realization.
ation. However, one can show that for both transistors to be ON and operating in the
saturation region the value of the overdrive voltage of transistor M2 , which is given by
VEF F 2 = VSG2 − |VT HP |, has to satisfy the following equation: VEF F 2 < VT HN − |VT HP |,
where VT HN and VT HP are the threshold voltages of the NMOS and PMOS transistors respectively. In modern CMOS processes, where the values of VT HN and VT HP
are close, this results in a small ft for transistor M2 making the circuit of Fig. 2.5-b
incapable of high-speed operation. The two other CS-CD TAI circuit realizations can
be derived from Fig. 2.5 by using a PMOS-PMOS and a PMOS-NMOS configuration
for M1 and M2 respectively.
Figure 2.6-a shows the CG-CS topology using an NMOS-NMOS realization. This
circuit was originally proposed in [47], and requires a minimum supply voltage of
VGS + VDS,sat . This makes it suitable for low-voltage applications. Furthermore, both
transistors use the same bias current making this TAI topology suitable for low-power
applications. The NMOS-PMOS realization of the CS-CG topology is shown in Fig. 2.6b. It requires a minimum supply voltage of VGS + 2VDS,sat , which is slightly higher than
that of the NMOS-NMOS realization. Also, the ability to control the bias current of
both transistors results in a wider inductance tuning range at the expense of higher
power consumption.
2.2. TUNABLE INDUCTORS
19
Vdd
Vdd
Vdd
I1
Vdd
I1
M2
M2
VB
VB
M3
M1
+
A
-
M3
M1
I2
I2
Zin
(a)
Zin
(b)
Figure 2.7: (a) CS-CD TAI using a cascoded CS stage. (b) CS-CD TAI using a gainboosted cascoded CS stage.
Quality Factor Enhancement Techniques For Gyrator-C TAIs
Replacing each transistor with its small-signal equivalent model and neglecting all the
capacitances except for Cgs2 , one can show that the input impedance of the CS-CD
TAI circuit of Fig. 2.5-a can be approximated as:
Zin ≈
sCgs2
1
+
.
gm2 × (ro1 gm1 ) gm1 gm2
(2.10)
Equation (2.10) indicates that the TAI can be modeled by an inductor in series with a
resistor. The series resistor represents the loss associated with the TAI circuit. To minimize the losses and achieve a high-Q, it is desired to minimize the value of this series
resistance. In other words, it is desired to move the zero of the input impedance transfer
function, i.e. the zero of the numerator of Eq.(2.10) ωz = 1/ro1 Cgs2 , to lower frequencies. On the other hand, more elaborate analysis reveals that the input impedance
of the TAI circuit has a pole frequency at ωp = gm2 /Cgs2 , which is responsible for
degrading the inductor Q at high frequencies. Hence, it is desired to move the pole to
higher frequencies. It is worth mentioning that, adding an extra capacitor CL at the
gate of M2 to terminate the gyrator results in the following expression for the input
2.2. TUNABLE INDUCTORS
impedance:
1
+ s(Cgs2 + CL )
ro1
Zin ≈
.
(gm1 + sCL )(gm2 + sCgs2 )
20
(2.11)
Hence, besides affecting the value of the TAI inductance, the capacitor CL also adds a
pole frequency which further limits the operating frequency of the TAI circuit. Therefore, in most high-speed TAIs the load capacitor CL is not used and the circuit relies on
the parasitic capacitances of the transistors. By investigating Eq.(2.10) closely, one can
show that the series resistance is equal to the resistance looking into the source of M2
divided by the CS stage gain, i.e. gm1 ro1 . To reduce the series resistance of the TAI, a
cascode device can be added to the circuit as shown in Fig. 2.7-a. Adding the cascode
device, increases the output impedance of the CS amplifier and consequently increases
its gain by a factor of gm3 ro3 , this decreases the series resistance by approximately the
same factor. This technique was proposed in [42], furthermore, the authors of [42]
proposed a gain-boosted cascode implementation, which is shown in Fig. 2.7-b. This
reduces the series resistance by a factor A×gm3 ro3 compared to the circuit of Fig. 2.5-a,
where A is the gain of the feedback amplifier. This Q-enhancement technique can be
applied to any of the various CS-CD or CG-CS TAI topologies.
Another approach that is used to enhance the Q of TAIs is by using cross-coupled
differential pairs to generate a negative resistance to cancel the resistive losses. This
technique was used in [47] to enhance the Q of a differential CG-CS TAI, and in [43] to
enhance the Q of a differential-pair-based TAI. However, this technique is more suited
for two port inductors excited by differential signals. Using more elaborate transconductors, such as differential pairs in [43] and [40], to implement the TAIs enhances the
inductor characteristics by giving the designer more freedom in shaping its frequency
response, namely in the locations of the zeros and poles of the input impedance transfer function. This comes at the expense of power dissipation. Whether a TAI circuit
uses a two-transistor topology or a differential-pair-based topology, the inductance is
electronically tuned by changing the bias currents of the two transconductors, or it
can also be tuned by changing the value of the load capacitor CL , when one is used to
terminate the gyrator.
Another Q enhancement technique that has recently been proposed for TAIs involves
adding a feedback resistance in the gyrator loop. This was first proposed in [41], where
2.2. TUNABLE INDUCTORS
21
Vdd
Vdd
I1
Rf
VB
M2
M3
M1
I2
Zin
Figure 2.8: Cascoded CS-CD TAI with a feedback resistance Rf .
a differential-pair-based TAI used a tunable MOS-based resistance inserted between
the output of the first differential-pair and the input of the second differential pair.
However, no analysis was presented that explained the effect of adding the feedback
resistance in the gyrator loop. Following that, another TAI circuit employing a feedback
resistance within a cascoded CS-CD topology was presented in [39]. This TAI circuit
is shown in Fig. 2.8, where the feedback resistance is inserted between the output of
the cascoded CS stage and the input of the CD transistor. In [39], the analysis of the
cascoded CS-CD TAI circuit with the additional feedback resistance was presented,
and experimental results were provided to validate the idea. The same circuit, i.e.
the CMOS cascoded CS-CD TAI, was also presented in [25] together with a BiCMOS
implementation using a common-emitter, common-collector topology. Both circuits
in [25] use the feedback resistance to enhance the Q. However, the analysis presented
in [39] and [25] is limited to the specific circuits presented by each paper. Consequently,
an intuitive understanding of the effect of adding this feedback resistance is missing.
This will be explained later on in chapter 3, as it is one of the contributions of this
thesis to generalize this Q-enhancement technique (i.e. adding a feedback resistance to
the gyrator-C architecture), and to explain its effect with the aid of very simple and
intuitive equations.
2.3. PHASE SHIFTERS
22
TAIs with Tunable Inductance and Quality Factor
Most of the previously published TAI implementations suffer from one major drawback,
which is their inability to independently control both the TAI inductance and Q. Tuning the inductance without affecting the Q is a key feature to overcome the degradation
of the insertion loss and return loss in any TAI-based application, due to the decrease
of the TAI’s Q when its inductance is being tuned. Moreover, it is important to have
control over the TAI’s Q without affecting its inductance, since this allows controlling
the level of the losses in a TAI-based application without significantly affecting the
desired response. Very few published TAI circuits have demonstrated independent L
and Q tuning capability [25,38,48]. The designs presented in [48] and [38] utilize GaAs
MESFETs. The first CMOS TAI with L and Q tuning capability was presented in [25].
The CMOS design in [25] employs a tunable feedback resistance in the gyrator loop.
Besides enhancing the Q of the TAI, the additional tunable feedback resistance allows
tuning both the L and the Q. Again, the methods used to achieve the independent
tuning in [25, 38, 48] are specific to each individual presented circuit. Hence, a generalized method that can be directly applied to the gyrator-C architecture is missing and
would prove to be very useful. This will be discussed in more detail in chapter 3, as it
is one of the contributions of this thesis to provide a general method applicable to any
gyrator-C TAI to achieve the independent L and Q tuning capability.
2.3 Phase Shifters
Electronically tunable phase shifters are essential building blocks for many RF and
microwave applications. In steerable antenna arrays, the direction of the antenna
array’s main beam is controlled by the inter-element phase shift. An excellent review for
the different classifications of phase shifters can be found in [49] and [24]. This section
will very briefly summarize the main types of electronically tunable phase shifters.
Electronically tunable phase shifters can be classified into many categories depending on
different criteria. For example, phase shifters can be analog in nature or digital, which
refers to having a continuous phase tuning range or discrete phase values respectively.
At the same time, phase shifters can be classified according to their design into five
main categories:
2.3. PHASE SHIFTERS
23
L2
L1
Figure 2.9: A single stage of a switched-line phase shifter.
• Switched-line or switched-network phase shifters
• Reflection-type phase shifters
• Transmission-type or loaded-line phase shifters
• Lumped-element L-C phase shifters
• PRI/NRI metamaterial phase shifters
2.3.1 Switched-Line Phase Shifters
Switched-line phase shifters rely on using single pole, double throw switches to select
between one of two TLs having different lengths as shown in Fig. 2.9. The differential
phase shift, i.e. the phase difference between the two paths, is given by:
|∆φ| = β |L1 − L2 | ,
(2.12)
where β is the propagation constant of the two TLs, and L1 and L2 are their lengths. To
obtain a large differential phase shift, the difference between the length of the TL should
be increased. Also, more than one stage can be cascaded to obtain larger phase shifts.
Usually, each stage of a cascaded switched-line phase shifter is designed to achieve
binary weighted phases. For example, a 3-bit phase shifter would employ 180o , 90o ,
and 45o stages, which results in a maximum phase shift of 315o and a minimum phase
shift (resolution) of 45o . Hence, the resolution of the discrete phase shifter depends
on the number of digital control bits. For an n-bit phase shifter employing 180o ,
90o , 45o , etc. stages, the resolution of the phase shifter becomes 360o /2n . The same
concept can be used to design a lumped-element phase shifter by switching between
different networks, for example, switching between a low-pass network and a high-pass
2.3. PHASE SHIFTERS
24
(1)
(2)
-90o
CL
o
Input port
-1
80
-90
o
(4)
80
-1
Output port
(3)
o
CL
Figure 2.10: Reflection-type phase shifter utilizing a 3dB coupler loaded with varactors.
network [50].
The insertion loss of the switched-line phase shifters becomes an issue as more stages
are cascaded to increase its resolution. This is a result of the increasing number of
switches that the signal has to propagate through. This problem becomes more obvious
for IC implementations, which use transistor-based switches. To overcome the losses of
the switches, amplifiers can be employed. This, however, makes the phase shifters unidirectional. Furthermore, switched-network phase shifters occupy a large area, since
they require at least two networks for each control bit.
2.3.2 Reflection-Type Phase Shifters
Reflection-type phase shifters, rely on terminating a 3dB coupler with a reactive load.
Either varactors or TAIs can been used to terminate a 3dB coupler, however varactors
are more commonly used. Fig. 2.10 shows a simplified diagram of a reflection-type
phase shifter terminated with varactors. Assuming that the coupler is ideal, i.e. the
coupler has no losses, equally divides the input power from port 1 among ports 2 and
3, and provides -90o and -180o phase shifts at the two ports respectively, one can show
that the power reflected back from ports 2 and 3 adds up in-phase at port 4 and out-ofphase at port 1. Furthermore, the phase of the output signal at port 4 is proportional
to the phase of the reflection coefficient at ports 2 and 3, Γ, which is given by:
Γ=
1 − jωCL Zo
ZL − Zo
=
,
ZL + Zo
1 + jωCL Zo
(2.13)
2.3. PHASE SHIFTERS
25
S21
S11
CL
Figure 2.11: Single stage of a transmission-type phase shifter.
where ZL is the varactor impedance, CL is its capacitance. Using Eq.(2.13), one can
show that the output phase at port 4 can be expressed as:
φ = −2 tan−1 (ωCL Zo ) .
(2.14)
If the varactor capacitance is varied from CLmax to CLmin , the phase tuning range is
given by:
|∆φ| = 2 tan−1 (ωCLmax Zo ) − 2 tan−1 (ωCLmin Zo ) .
(2.15)
The return loss, i.e. S11 , of reflection-type phase shifters remains very low as long as the
two varactors are perfectly matched. Reflection-type phase shifters tend to have a small
bandwidth on the order of 15% [49], with the main limiting factor being the bandwidth
of the 3dB coupler. Furthermore, reflection-type phase shifters tend to occupy a large
area, since their size is mainly governed by the size of the 3dB coupler. Hence, the
focus of research into reflection-type phase shifters has been directed towards designing
lumped-element couplers to reduce area [51, 52].
2.3.3 Transmission-Type Phase Shifters
Transmission-type (or loaded-line) phase shifters are one of the popular methods to
implement phase shifters due to their simplicity. A transmission-type phase shifter
consists of a TL loaded with a shunt reactive impedance, which in most cases is a
varactor. A simplified diagram of such a phase shifter is shown in Fig. 2.11. One
can show that if a TL with a characteristic impedance Zo is loaded with a varactor
with a capacitance CL , the return loss and the transmission coefficient, as indicated on
2.3. PHASE SHIFTERS
26
Fig. 2.11, are expressed as:
S11 =
−jωCL Zo
, and
2 + jωCL Zo
(2.16)
2
2 + jωCL Zo
(2.17)
S21 =
respectively. Hence, the excess phase shift due to loading the TL with the varactor is
given by:
¶
µ
ωCL Zo
−1
.
(2.18)
φ = − tan
2
If the varactor capacitance is varied from CLmax to CLmin , the phase tuning range is
expressed as:
µ
|∆φ| = tan
−1
ωCLmax Zo
2
¶
µ
− tan
−1
ωCLmin Zo
2
¶
.
(2.19)
By comparing Eq.(2.19) with Eq.(2.15), one can conclude that for the same capacitance
tuning range, transmission-type phase shifters result in a smaller phase tuning range
compared to reflection-type phase shifters. However, they do not require a 3dB coupler
which makes them more compact. Furthermore, transmission-type phase shifters are
more wide-band compared to reflection-type phase shifters.
Examining Eq.(2.16) reveals that, unlike reflection-type phase shifters, transmissiontype phase shifters always suffer from finite return losses. In other words, S11 does not
approach zero except for CL = 0, which limits the phase tuning range of such phase
shifters. To overcome this, the TL can be loaded with two identical varactors separated
by λ/4, where λ is the wavelength of the propagating signal. This causes the reflected
signals from the two varactors to cancel-out and reduces the return loss of the phase
shifter [24].
2.3.4 Lumped-Element L-C Phase Shifters
The first three phase shifter topologies presented in this chapter mainly rely on using
either TLs or coupled TLs. For IC applications operating in the low GHz frequency
range, the length of these TLs becomes excessively long, which makes these techniques
unsuitable for such applications. Hence, most IC designs operating in the low GHz fre-
2.3. PHASE SHIFTERS
27
C
C
L
C
L
(a)
(b)
L
C
L
C
(c)
C
L
L
(d)
Figure 2.12: Different high-pass and low-pass topologies for constant-impedance
second-order L-C phase shifters [53].
quency range use standard lumped-element filters (low-pass, high-pass, etc.) to implement phase shifters. Although R-C filters have been extensively used by IC designers to
implement on-chip phase shifters (for example, for the generation of quadrature-phase
signals in RF transceivers), R-C filters are not suitable for beam steering applications.
This stems from the fact that they cannot provide matching to a real impedance (Zo ).
Although matching is usually not an issue for on-chip applications, the focus of this
thesis is directed towards phase shifters for beam steering applications, and so matching
is one of the main criteria.
This leads us to L-C phase shifters, which can provide both the matching as well
as the required phase shift. Second-order bi-directional L-C phase shifters can take
one of the four implementations shown in Fig. 2.12 [53]. The high-pass T architecture
of Fig. 2.12-a and the low-pass Π (Pi) architecture of Fig. 2.12-b use the minimum
number of inductors and hence occupy a smaller area. This makes the high-pass T and
the low-pass Π architectures more suitable for compact IC implementations.
The phase shift, φHP , of the high-pass Tee phase shifter of Fig. 2.12-a can be expressed as3 :
√
2
.
(2.20)
φHP ≈ √
ω LC
2.3. PHASE SHIFTERS
28
Equation (2.20) indicates that the phase can be tuned by changing the capacitance and
the inductance, which can be achieved by using varactors and TAIs. Simultaneously
changing the capacitance from Cmax to Cmin and the inductance from Lmax to Lmin
results in the following phase tuning range:
√
√
2
2
− √
.
|∆φHP | = √
ω Lmin Cmin ω Lmax Cmax
(2.21)
If the capacitance and inductance tuning ratios are defined as rC = Cmax /Cmin and
rL = Lmax /Lmin , Eq.(2.21) can be re-written as:
µ
|∆φHP | = φHPmin
1
1− √
rC × rL
¶
.
(2.22)
Similarly, the phase response of the low-pass phase shifter of Fig. 2.12-b can tuned
by changing the capacitance and the inductance. However, since the low-pass Π architecture uses a floating (or 2-port) inductor, it becomes difficult to replace the inductor
with a TAI. For this reason, the phase response of L-C low-pass phase shifters is usually tuned using varactors [54, 55], whereas for high-pass designs, both varactors and
TAIs can be employed to extend the tuning range. In spite of this, most high-pass LC phase shifter designs published in the literature use a single tuning element to tune
their phase response; varactors in [56,57], and TAIs in [27]. Although it is evident from
Eq.(2.22) that combining the use of varactors and TAIs will extend the phase tuning
range, to the author’s knowledge, until now, a phase shifter that combines the use of
varactors and TAIs has not been published. A detailed discussion about combining the
use of varactors and TAIs is presented later in chapter 4.
L-C phase shifters can also be designed using all-pass networks.
For example,
Fig. 2.13 shows a second-order all-pass phase shifter, which has a constant resistive
input and output impedance Zo for all frequencies [53]. The transmission-coefficient of
3
This phase expression is derived under the assumption that the phase shifter is matched, the detailed
derivation of this expression is presented later on in chapter 4.
2.3. PHASE SHIFTERS
29
L1
C1
C1
C2
L2
Figure 2.13: All-pass constant-impedance second-order L-C phase shifter.
the all-pass phase shifter can be expressed as:
ωr
s + ωr2
Qp
,
=
ωr
s + ωr2
s2 +
Qp
s2 −
S21
(2.23)
where ωr and Qp are the frequency and the quality factor of the complex conjugate
poles. Using Eq.(2.23), the phase shift can be expressed as:
µ
φ = −2 tan
−1
ωωr /Qp
ωr2 − ω 2
¶
.
(2.24)
Equation (2.24) indicates that the phase can be tuned by varying the value of ωr .
However, since the values of the circuit components (the capacitors and inductors) are
related to the all-pass filter parameters by the following equations: L1 = 2Zo /ωr Qp ,
C1 = Qp /ωr Zo , L2 = Qp Zo /2ωr , and C2 = 2Qp /ωr (Q2p −1)Zo , this necessitates changing
the values of all the circuit elements. Tuning four different elements simultaneously
complicates the tuning process. Furthermore, as discussed in section 2.2.4, the floating
inductor is difficult to synthesize using TAIs. However, this approach using all-pass
filters results in a relatively flat magnitude response compared to the low- and high-pass
approaches.
All-pass phase shifters have also been designed using active circuits. For example
a recently published design in [58] uses two transistors in feedback, where a series
resonator consisting of a fixed inductor and a varactor form the feedback path. The
2.3. PHASE SHIFTERS
30
C
TL
TL
d/2
L
C
d/2
Figure 2.14: PRI/NRI metamaterial phase shifter unit-cell.
phase is tuned via a single varactor voltage, and the phase shifter achieves 100o tuning
range at 1GHz. Another active phase shifter that was published in [23], combines a
gain stage together with two different classes of phase shifters. The design in [23] uses
a switched-network phase shifter, but instead of cascading multiple stages to cover the
entire phase tuning range, only one stage is used to realize a coarse tuning of 180o ,
while the rest of the phase tuning range is covered by varactor-tuned L-C low-pass
phase shifters. In spite of the numerous advantages offered by amplifier-based active
phase shifters, using amplifiers to design all-, low-, or high-pass phase shifters results in
uni-directional designs which makes them unsuitable for operating in both the transmit
and receive modes when incorporated within the beam steering network of a wireless
transceiver.
2.3.5 PRI/NRI Metamaterial Phase Shifters
The recent developments in the field of metamaterials have generated strong interest
in building phase shifters by cascading NRI metamaterial lines with PRI TLs [5].
Figure 2.14 shows the unit-cell of a TL PRI/NRI phase shifter [5]. It is composed of a
regular microstrip line (PRI section) loaded with two series capacitors, C, and a shunt
inductor, L (NRI section). Cascading the PRI TL, which has a low-pass response, with
the NRI section, which has a high-pass response, compensates the phase shift incurred
by the propagating signal. One can show that, the phase shift of the PRI/NRI phase
shifter in Fig. 2.14 can be approximated as:
√
2
− 2θT L ,
φ≈ √
ω LC
(2.25)
2.3. PHASE SHIFTERS
31
where θT L is the phase shift of a single microstrip TL. Equation (2.25) was originally
derived in [5]. According to Eq.(2.25), the PRI/NRI phase shifter can be designed
to produce a zero-degree phase at the design frequency. This is achieved through the
phase compensation process as opposed to accumulating a -360o or a +360o , which
would be necessary to achieve the zero-degree phase in a traditional low-pass or highpass topology respectively. Although, both approaches seem identical in terms of the
phase value at the design frequency, the latter approach (using low- or high-pass structures) results in a significantly larger group delay and consequently a much smaller
bandwidth. Hence, using the PRI/NRI approach allows building compact broadband
phase shifters with a linear frequency response, this was demonstrated in [5] and will
be also demonstrated in chapter 4 of this thesis. Centering the phase shift at 0o is desirable, for example, for scanning about the broadside direction in series-fed steerable
antenna arrays. This will be explained in more detail in section 2.5.1, as well as in
chapter 6.
It is obvious from the phase expression of Eq.(2.25), that the phase of the PRI/NRI
phase shifter can be tuned using the capacitance C and the inductance L. Simultaneously changing the capacitance from Cmin to rC × Cmin and the inductance from Lmin
to rL × Lmin results in the following phase tuning range:
√
µ
¶
1
2
1− √
.
|∆φ| = √
rL rC
ω Lmin Cmin
(2.26)
Equation (2.26) reveals that, tuning both the capacitance and inductance results in increasing the phase tuning range compared to only varying the capacitance. A tunable
composite PRI/NRI TL phase shifter was presented in [59] using two tunable loading
elements: series and shunt ferroelectric varactors. However, this implementation requires high control voltages (15V ). Furthermore, the design in [59] uses a fixed shunt
inductor which makes it impossible to achieve a low return loss across the entire phase
tuning range. This will be explained in more detail in chapter 4. Also, the ferroelectric
varactors result in a modest phase tuning range of 12.5o /unit-stage.
The above discussion summarizes the different types of phase shifters and the stateof- the-art in phase shifters’ design. This section also described the recent advances in
metamaterial-based phase shifters, and highlighted the main differences and similarities
between them and traditional phase shifters.
2.4. DIRECTIONAL COUPLERS
32
Input port
(1)
Isolated port
(4)
Through port
(2)
S31 Coupled port
(3)
S41
Figure 2.15: Block diagram of a 4-port directional coupler.
2.4 Directional Couplers
Since chapter 5 of this thesis describes a novel MMIC directional coupler, it is instructive to present here a brief section describing directional couplers. Directional couplers
are one of the most commonly used building blocks in microwave and RF systems.
Some applications of directional couplers are: signal monitoring and automatic level
control, in-phase/quadrature-phase modulators, signal splitting, combining, and phase
shifting. The block diagram of a 4-port directional coupler is shown in Fig. 2.15. The
input signal is applied to port 1 and is divided among the through and coupled ports,
ports 2 and 3 respectively, according to the value of the coupling coefficient C. A directional coupler is characterized by the coupling coefficient C, and the isolation I, which
are defined as:
µ ¶
P1
= −20 log |S31 |, and
(2.27)
C = 10 log
P3
µ ¶
P1
= −20 log |S41 |,
I = 10 log
(2.28)
P4
where P1 is the input power at port 1, and P3 and P4 are the output powers from the
coupled and isolated ports respectively. If a directional coupler is designed to achieve
equal output powers at the coupled and through ports, P2 = P3 (in other words, a
3dB coupling coefficient), it is usually termed as a hybrid coupler. The isolation of a
coupler indicates how well the coupler prevents the input signal from leaking to port
4 (isolated port). Another popular parameter used in the literature to characterize
couplers is the directivity D, which is defined as:
µ
D = 10 log
P3
P4
¶
¯
¯
¯ S31 ¯
¯.
= 20 log ¯¯
S41 ¯
(2.29)
2.4. DIRECTIONAL COUPLERS
33
Input port
(1)
Through port
(2)
/4
/4
Isolated port
(4)
Coupled port
(3)
Figure 2.16: Diagram of a microstrip branch-line directional coupler.
However, the directivity can be inferred from the coupling coefficient and the isolation
using the following equation:
D =I −C
(dB).
(2.30)
Using printed microstrip TLs to design directional couplers is one of the most common methods to implement planar couplers suitable for low form factor RF and microwave systems. An instructive review of printed TL directional couplers is available
in [24]. Printed TL implementations of directional couplers impose limitations on the
area occupied by the couplers especially for systems operating in the low GHz frequency
range. This has hindered the integration of couplers into MMICs and has motivated the
development of various lumped-element coupler topologies [60]. Directional couplers
can be classified into four main categories according to their structure:
• Branch-line directional couplers
• Coupled-line directional couplers
• Lumped-element L-C directional couplers
• NRI/PRI metamaterial directional couplers
The following sections summarize the main topologies of printed and integrated directional couplers and highlights the recent advances in the design of directional couplers
using NRI metamaterials.
2.4. DIRECTIONAL COUPLERS
34
2.4.1 Branch-Line Directional Couplers
A branch-line coupler consists of four λ/4 TLs with a characteristic impedance of
√
Z1 = Zo , and Z2 = Zo / 2 connected as shown in Fig. 2.16, where λ is the wavelength.
Following the analysis outlined in [24], one can show that if the coupler is excited
at port 1 while the rest of the ports are terminated with Zo , then the input port is
perfectly matched at the design frequency, i.e. S11 (ω = ωo ) = 0. Furthermore, the
transmission coefficients of the through, coupled, and isolated ports can be expressed
as:
j
(2.31)
S21 (ω = ωo ) = − √ ,
2
1
S31 (ω = ωo ) = − √ , and
2
(2.32)
S41 (ω = ωo ) = 0
(2.33)
respectively. Equation (2.31) and Eq.(2.32) indicate that the input signal power is
equally divided among the through and coupled ports. Furthermore, the two signals
at the through and coupled ports have a 90o phase difference. On the other hand,
Eq.(2.33) indicates that port 4 is completely isolated from the input signal. However,
since the operation of the branch-line coupler relies on having λ/4 TLs, its bandwidth
is usually limited to about 15% [24]. Branch-line couplers can be designed for different
coupling coefficients, by changing the characteristic impedances of the microstrip TLs
Z1 and Z2 . In fact, one can show that, in the general case [61], the amplitude of the
through and coupled signals can be expressed as:
S21 (ω = ωo ) = −j
Z1
, and
Zo
(2.34)
Z1
.
Z2
(2.35)
S31 (ω = ωo ) = −
Hence, the ratio Z1 /Z2 can be used to determine the coupling coefficient of a branch-line
coupler. However, for a lossless design, power conservation dictates that the following
equation should be satisfied:
µ
Z1
Zo
¶2
µ
+
Z1
Z2
¶2
= 1.
(2.36)
2.4. DIRECTIONAL COUPLERS
Input port
(1)
35
Through port
(2)
/4
Coupled port
(3)
Isolated port
(4)
Figure 2.17: Diagram of a microstrip coupled-line directional coupler.
This can be obtained from the more intuitive expression |S21 |2 + |S21 |2 = 1, and using
Eq.(2.34) and Eq.(2.35) to substitute for S21 and S31 , respectively.
2.4.2 Coupled-Line Directional Couplers
A printed coupled-line coupler consists of two closely spaced microstrip TLs, as shown
in Fig. 2.17. The amount of coupling, and hence the coupling coefficient, C, between
the two microstrip TLs is a function of their width and spacing, as well as the substrate
thickness and dielectric constant [24]. But, the amount of power coupled to port 3, is
not only a function of the coupling coefficient, C, but is also a function of the length
of the coupler. To maximize the coupled power an electrical length of π/2 is usually
picked for the design of coupled-line couplers, which corresponds to a λ/4 length.
Given a specific coupling coefficient C, and a characteristic impedance Zo , then the
required even- and odd-mode characteristic impedances of the coupled TLs should be
calculated using the following equations:
r
ZoE = Zo
1+C
,
1−C
r
and ZoO = Zo
1−C
.
1+C
(2.37)
The even- and odd-mode characteristics impedances, ZoE and ZoO , are used to characterize any two coupled TLs when excited by a common-mode and a differential signal
respectively [24]. Based on the values of ZoE and ZoO , obtained from Eq.(2.37), one
can determine the coupled TLs parameters such as their width, separation, and the
required substrate height and dielectric constant using standard charts, such as the one
found on page 388 of [24]. In practice coupled-line couplers are usually used to achieve
small power coupling levels. In contrast, higher power coupling levels close to 3dB
2.4. DIRECTIONAL COUPLERS
36
Figure 2.18: lumped-element L-C low-pass and high-pass Π realizations of a branch-line
coupler.
are only achievable using branch-line couplers. However, coupled-line couplers usually
have much larger bandwidths compared to branch-line couplers.
2.4.3 Lumped-Element L-C Directional Couplers
Printed branch- and coupled-line couplers occupy a large area, since they rely on λ/4
TLs, which tend to be a few centimeters for applications operating in the low GHz
frequency range. This prevents their integration with other RF and digital circuits
on the same chip for a fully-integrated system, and has motivated the development of
various lumped-element topologies for implementing integrated couplers [60].
Most of the lumped-element realizations of couplers are inspired from the TL branchline or the TL coupled-line topologies. For example, replacing each λ/4 TL of the
branch-line coupler in Fig. 2.16 with a -90o low-pass, Π, L-C phase shifter results in
the L-C coupler realization of Fig. 2.18-a. On the other hand, using +90o high-pass, Π,
L-C phase shifter results in the L-C coupler realization of Fig. 2.18-b. In both designs
of Fig. 2.18, the values of the inductors and capacitors are chosen to achieve the desired
±90o phase shift, and, at the same time, set the required line impedances. Both the
L-C couplers of Fig. 2.18 use four inductors, and four capacitors. It is interesting to
note that the high-pass, Π, L-C coupler topology of Fig. 2.18-b constitutes the core
of a 2-D unit-cell of a NRI metamaterial medium. This points out the strong relation
between the field of NRI metamaterials and directional couplers. In fact, couplers have
2.4. DIRECTIONAL COUPLERS
37
C1
L
C1
(1)
(2)
C2
C2
L
L
C2
C2
(4)
(3)
C1
L
C1
Figure 2.19: L-C lumped-element high-pass Tee realization of a branch-line coupler.
C1
(1)
L1
C2
C1
(2)
C2
(4)
(3)
C1
L1
C1
Figure 2.20: L-C lumped-element realization of a coupled-line coupler.
benefited from the recent developments in the field of metamaterials [4, 17, 62–65], and
this point will be discussed in more detail in section 2.4.4.
Other L-C coupler realizations can be obtained by using -90o low-pass, Tee, L-C phase
shifters or by using +90o high-pass, Tee, L-C phase shifters. The former requires the
use of eight inductors, which makes the size of the coupler excessively large compared to
the architectures of Fig. 2.18. On the other hand, using +90o high-pass Tee L-C phase
shifters, as shown in Fig. 2.19, results in the same number of inductors, however it
requires eight capacitors. IC capacitors usually occupy a much smaller area compared
to IC inductors, so this does not result in a larger area. However, having two capacitors
in the signal path of each phase shifter will result in more losses especially for a tunable
coupler design where these capacitors are to be replaced with on-chip varactors.
2.4. DIRECTIONAL COUPLERS
38
Lumped-element L-C couplers can also be designed based on TL coupled-line couplers
by replacing the two λ/4 TLs with two -90o , Π, L-C sections (L1 and C1 ), as shown
in Fig. 2.20, and adding two coupling capacitors, C2 , to model the coupling occurring
between the two TLs. This implementation requires only two spiral inductors, which
makes it very attractive for designing compact on-chip couplers. Furthermore, for IC
implementations the two inductors can be replaced with two coupled spiral inductors.
This further reduces the area occupied by the L-C coupler [66]. Although lumpedelement couplers, in general, offer numerous advantages over their printed counterparts,
such as small area and ease of integration with RF and digital circuits, lumped-element
couplers have smaller bandwidths compared to printed couplers. One technique that
is used to extend the bandwidth of L-C couplers is to use a cascade of multiple L-C
sections [67].
2.4.4 PRI/NRI Metamaterial Directional Couplers
PRI/NRI metamaterial coupler designs [4, 17, 62–65] are relatively new and have all
emerged following the planar L-C realization of metamaterials. The interesting properties of NRI metamaterial lines have motivated designers to investigate the benefits
of using NRI lines to build branch-line and coupled-line couplers. In [17], it was shown
that combining the use of PRI and NRI lines to design printed branch-line couplers
results in a much more compact size without any bandwidth degradation. Two branchline couplers designs were presented in [17]. In the first design, the low impedance
√
lines (50/ 2Ω) were implemented using regular PRI microstrip TLs, whereas the high
impedance lines (50Ω) were implemented using NRI lines. This resulted in an area of
λ/4 × λ/12 (i.e. length by width) for the coupler, which corresponds to an area savings
of 66% compared to a traditional branch-line coupler. The second design presented
√
in [17] uses NRI lines to implement the low impedance lines (50/ 2Ω), and regular
PRI microstrip TLs to implement the high impedance lines (50Ω). In this case, the area
of the coupler is λ/4 × λ/14, which corresponds to an area savings of 77% compared
to a traditional branch-line coupler.
Furthermore, NRI metamaterial lines have been used to design dual-band branchline couplers [4]. Dual-band operation is enabled by replacing the PRI microstrip TLs
of a branch-line coupler with NRI metamaterial TLs. As demonstrated in [4], NRI lines
2.5. PHASED ANTENNA ARRAYS
39
Table 2.1: Comparison Between Different Directional Coupler Topologies.
Parameter
Integration
Coupling coeff.
Bandwidth
Size
Branch-line
X
>3dB
Average
Large
Coupled-line
X
<3dB
Large
Medium
Lumped-element
√
Arbitrary
Small
Very small
Printed PRI/NRI
X
Arbitrary
Average
Medium
allow full control over the values of the two frequencies f1 and f2 at which the NRI lines
achieve a +90o and a +270o (which is equivalent to -90o ) phase shift respectively. This
guarantees identical operation of the branch-line coupler at the two frequencies f1 and
f2 , allowing for dual-band operation. On the other hand, in a traditional branch-line
coupler using only PRI TLs, the PRI TLs would achieve the -90o and a -270o (which is
equivalent to -90o ) phase shifts only at fo and 3 × fo respectively, where fo is the design
frequency. Hence, using traditional PRI TLs does not give control over the choice of
the two frequencies, since f2 has to be three times f1 , which is usually not suitable for
most dual-band applications.
Coupled-line couplers have also benefited from the advances in metamaterials. NRI
/PRI metamaterial couplers have been designed by coupling a PRI TL with a NRI
metamaterial line in [4,62,64,65] and by coupling two NRI metamaterial lines together
in [63,65]. The main benefit from using NRI lines to design such couplers is the ability
to achieve high power coupling levels, as opposed to traditional coupled-line designs,
using only PRI TLs, which limit the coupling level to small values. By using NRI
metamaterial lines, coupling levels of -3dB were demonstrated in [62,63], and near 0dB
coupling levels were demonstrated in [4, 63].
Table 2.1 qualitatively compares between the achievable performance from the different directional coupler topologies presented in this section.
2.5 Phased Antenna Arrays
2.5.1 Antenna Arrays Basics
A phased antenna array, as defined by the glossary of telecommunication terms [68],
is a group of antennas in which the relative phases of the signals feeding the antennas
are set in such a way that the effective radiation pattern of the array is reinforced in
2.5. PHASED ANTENNA ARRAYS
40
Ae+j
A
dE
Ae+j2
Ae+j(N-1)
dE
Figure 2.21: N-element uniform linear antenna array with equal amplitude excitation
and a progressive phase constant φ.
a desired direction and suppressed in undesired directions. Generally, phased arrays
are either planar (2-D) or linear (1-D). This thesis focuses on linear arrays, as they are
considered the basic building block for planar arrays.
In general, the radiation pattern of an antenna array can be decomposed into the
product of two terms: an array factor AF (θ), which depends on the geometry of the
array, the number of elements, and the relative amplitudes and phases of the signals fed
to each antenna, and an element factor EF (θ), which represents the radiation pattern
of a single antenna [69]. Fig. 2.21 shows a uniform, linear antenna array, i.e. the
array has equally spaced elements which are excited with equal amplitudes A and a
progressive phase shift φ. The array factor of this array can be expressed as:
µ
¶
N
sin
(kdE sin θ + φ)
1
2
µ
¶,
AF (θ) =
1
N
(kdE sin θ + φ)
sin
2
(2.38)
In Eq.(2.38), dE is the inter-element spacing, θ is the angle measured from the normal
to the array axis, and k is the wave-number, which is related to the operating frequency
by k = ω/c, where c is the speed of light. The zeros of the array factor will result in
nulls in the antenna array’s radiation pattern. Also, if the individual antenna elements
are omni-directional, then the locations of the maxima in the array’s radiation pattern
are mainly determined by the maxima of the array factor. Using Eq.(2.38), one can
2.5. PHASED ANTENNA ARRAYS
41
0°
Major lobe
−30°
30°
HPBW
Side lobes
−60°
60°
−30
−90°
−20
−10
0
90°
Figure 2.22: Array factor of a 4-element antenna array fed in-phase and with dE = λ/2.
show that the maxima of the array factor occur at:
µ
θm = sin
−1
¶
λo
(−φ ± 2mπ) ,
2πdE
m = 0, 1, 2, . . . ,
(2.39)
where λo is the free-space wavelength, given by λo = c/f .
In many applications, it is desired to center the main beam of the array about the
broadside direction, i.e. at θ = 0o . The necessary condition for broadside radiation
can be obtained from Eq.(2.39) by setting θ0 = 0o to obtain the first maximum of the
radiation pattern at broadside. This results in the following condition for broadside
radiation:
φ=0
(2.40)
indicating that a uniform array should be fed in-phase in order to center its main
beam at broadside. This is demonstrated in Fig. 2.22, which plots the theoretical
expression of the array factor, Eq.(2.38), of a 4-element array when the elements are
fed in-phase and the inter-element spacing, dE , is set to λo /2. The array factor plot of
Fig. 2.22 shows one major lobe and two side lobes. Side lobes represent radiation in
undesired directions, which should be minimized. According to Fig. 2.22, a 4-element
array with omni-directional antenna elements would achieve a side lobe level of -11dB.
Furthermore, its half-power beamwidth (HPBW) would be 26o as shown by Fig. 2.22.
2.5. PHASED ANTENNA ARRAYS
42
φ=+90o
φ=−90o
0°
−30°
30°
−60°
60°
−30
−90°
−20
−10
0
90°
Figure 2.23: Array factor of a λo /2 4-element antenna array fed with a progressive
phase shift of ±90o .
In general, when the antenna elements are fed with a progressive phase shift of φ,
the direction of the main beam (i.e. the scan angle) can be written as:
µ
−1
θ0 = − sin
¶
λo
φ .
2πdE
(2.41)
Equation (2.41) indicates that, using phase shifters capable of generating negative
progressive phase shifts results in positive scan angles θ0 , and vice versa. Hence, to scan
the main beam about the broadside direction, the progressive inter-element phase shift
should acquire both positive and negative values. This conclusion plays an important
role in the selection of the topology of the inter-element phase shifters, especially in
series-fed arrays as will be described later. For a progressive inter-element phase shift
of ±90o the main beam of the array factor can be scanned all the way from −30o
to +30o about the broadside direction as illustrated in Fig. 2.23. Also, as the main
beam is scanned off the broadside direction another minor lobe appears in the radiation
pattern. However, its level remains below -11dB.
In most applications, it is also important to avoid the creation of grating lobes in
the radiation pattern (i.e. other global maxima for the array factor). Using Eq.(2.39),
it can be shown that, to avoid creating grating lobes in the radiation pattern while
2.5. PHASED ANTENNA ARRAYS
43
L
Z
W
Y
h
r
X
Figure 2.24: Rectangular microstrip patch antenna fed with a microstrip TL .
operating the array at broadside, the following condition should be satisfied:
dE ≤
λo
.
2
(2.42)
Equation (2.42) is a fundamental equation, since it sets the maximum separation distance between two consecutive antenna elements. Hence, tight limitations are set on
the phase shifter dimensions to fit in-between the antenna elements of a series-fed
design, if it is desired to integrate the phase shifters with the antennas on a single
PCB. However, if the array uses a parallel feed network, such tight constraints are not
imposed on the phase shifter dimensions.
2.5.2 Microstrip Patch Antenna
Phased antenna arrays can use a variety of antenna elements. However, for wireless
consumer applications where size, weight, form factor, and cost are constrained, microstrip patch antennas become a popular choice. A patch antenna consists of either
a rectangular or circular shaped conductor on top of a ground plane. Figure (2.24)
shows a rectangular patch antenna fed with a microstrip TL. The geometry of a patch
antenna is a function of the desired resonance frequency, i.e. the frequency of operation, and the substrate properties [69]. Given the desired resonance frequency fr of a
rectangular patch and the substrate dielectric constant ²r and height h, its width can
2.5. PHASED ANTENNA ARRAYS
44
L
W
yo
Figure 2.25: Inset-fed rectangular microstrip patch antenna.
be calculated using:
1
W =
√
2fr µo ²o
r
2
.
1 + ²r
(2.43)
To a first order of approximation, the length of the patch is equal to the resonance
√
length, L ≈ λo /2 ²r , where λo is the free space wavelength. However, due to the
existence of fringing fields the patch antenna seems electrically longer than its physical
length. Hence, a more accurate estimate of the patch length can be obtained using the
following expression [69]:
where
²ef f =
λo
− 2∆L,
L= √
2 ²ef f
(2.44)
²r − 1
²r + 1
+ p
, and
2
2 1 + 12h/W
(2.45)
(²ef f + 0.3)(W/h + 0.27)
.
(²ef f − 0.26)(W/h + 0.8)
(2.46)
∆L = 0.4h
At resonance, the input impedance of a patch antenna is real and usually takes very
large values. For example, the patch resistance can take values close to 300Ω. This,
however, depends on the patch and substrate properties. To bring the patch resistance
down to reasonably low values (i.e. to values close to the characteristic impedance of
the microstrip feed line), the microstrip TL feeding the patch is recessed inwards as
shown in Fig. 2.25 [69]. The value of the inset feed point yo determines the value of
2.5. PHASED ANTENNA ARRAYS
45
0°
0°
−30°
30°
−30°
−60°
−90°
60°
−30
−20
−10
0
30°
−60°
60°
10
90°
−90°
(a)
−30
−20
−10
0
10
90°
(b)
Figure 2.26: Elevation plane gain plot for a 2.4GHz rectangular microstrip patch antenna: (a) in the y-z plane, (b) in the x-z plane.
the patch resistance at resonance.
Figure 2.26-a and Fig. 2.26-b show the gain of a microstrip patch antenna in the
x-y plane (as shown in Fig. 2.24). The patch is designed to operate at 2.4GHz with
a dielectric constant, ²r , of 4.5 and a substrate thickness h of 3.175mm (125mil). The
gain plot of Fig. 2.26-a is for the y-z plane, whereas that of Fig. 2.26-b is for the xz plane. Both plots show that the patch antenna has a large HPBW. Hence, when
patches are used it is necessary to employ arrays to produce more directive, high-gain
beams.
2.5.3 Phased Array Feed Network Topologies
The popular approach to building a phased array transceiver for low GHz applications is by using a single transceiver combined with a beam steering network to feed
the different antennas with the appropriate signal amplitudes and phases. As will
be described in this section, the beam steering network of this type of phased arrays
can either take a parallel or a series configuration. Aside from utilizing electronically
tunable phase shifters, in the RF domain, to generate the appropriate signal phases,
the beam steering network has to take care of the power splitting and combining.
The reason for the popularity of this approach for low GHz applications, is the large
size of the antennas and the large distance between them, which scale with the wavelength. Consequently, the transmission-lines (TLs) connecting the printed antennas to
2.5. PHASED ANTENNA ARRAYS
46
the transceiver can readily be used for power splitting, combining, and phase shifting,
without significantly increasing the area occupied by the phased array. Furthermore,
the TLs provide an adequate means for designing low-loss power splitters and combiners, which are very challenging to design and integrate on-chip at these frequencies. It
is also worth mentioning that, this type of phased array transceivers require only one
low-noise amplifier, mixer, and power amplifier.
On the other hand, for millimeter-wave applications, performing the phase shifting in the RF domain becomes a challenge. This necessitates performing the phase
shifting at lower frequencies, which requires each antenna in the phased array to have
a separate transceiver. Consequently, the majority of millimeter-wave phased array
transceivers utilize a parallel architecture, which requires a separate transmit/receive
path for each antenna in the array [70, 71]. An N-element phased array transceiver of
this type would require roughly N times the area and the power consumption of a single transceiver, which is why this approach is not attractive at the low GHz frequency
range. This approach has been used in many recent publications to design millimeterwave phased array transceivers, as it conveniently allows integrating the entire phased
array transceiver onto a single chip. Furthermore, at these high frequencies the antenna dimensions shrink, allowing their integration with the transceivers on a single
chip. This, however, is still being investigated, as there are many challenges facing the
design of efficient on-chip antennas in silicon [72–74].
The objective of this thesis is to demonstrate beam steering for 2.4GHz ISM band applications. Consequently, the first approach, is adopted to design the steerable phased
array.
Feed networks for microstrip patch arrays can take a series or a parallel configuration.
A good review of the different feeding configuration of patch arrays can be found in [75].
Parallel-Fed Arrays
In parallel-fed arrays, the individual antennas are fed in parallel using a TL power
division network as illustrated in Fig. 2.27. Parallel-fed arrays are the popular choice
for electronic beam steering, since they easily allow inserting phase shifters to control
the phase excitation of each patch. However, the simplified parallel architecture of
Fig. 2.27 uses unequal TLs to feed the individual patches, which results in unequal
2.5. PHASED ANTENNA ARRAYS
dE<
Figure 2.27: A 4-element parallel-fed antenna array.
d E<
Figure 2.28: A 4-element corporate-fed antenna array.
47
2.5. PHASED ANTENNA ARRAYS
48
dE<
Figure 2.29: A basic 4-element series-fed antenna array.
phase variations across the signal bandwidth. Figure 2.28 shows another version of
the parallel-fed architecture, which uses equal length TLs to feed the patches, termed
the corporate-fed architecture. Using equal length TLs makes the phase excitations,
and hence the radiation pattern of the array, less sensitive to frequency variations,
i.e. results in less beam squinting. This makes corporate-fed arrays relatively wideband, making them a popular choice for beam steering in high data-rate applications.
This, however, comes at the expense of the large area occupied by the feed network.
Occupying a large area also increases the insertion losses associated with the feed
network lowering the array’s efficiency. Furthermore, another disadvantage of paralleland corporate-fed architectures is that they require phase shifters having a very wide
tuning range; an N-element parallel- or corporate-fed array requires a maximum phase
shift of (N − 1)φ to produce a progressive phase shift of φ.
Series-Fed Arrays
In a series-fed array, the individual patch antennas are excited in series as illustrated
in Fig. 2.29. Here, the power is delivered to the patch antennas one after the other.
The feed network of this type has the advantage of being less complex, and much more
compact in terms of area compared to the parallel or corporate types. Its compact
size also minimizes the insertion losses, and the undesired radiation caused by the feed
network. This makes series-feed arrays more efficient than their parallel- or corporatefed counterparts. Furthermore, an N-element series-fed array requires a maximum
phase shift of only φ to produce a progressive phase shift of φ, since in the series
configuration each phase shifter is reused by more than one patch.
2.5. PHASED ANTENNA ARRAYS
dE<
49
LPS
Zo
Figure 2.30: A 4-element series-fed traveling wave in-line antenna array using a termination load.
dE<
LPS
Figure 2.31: A 4-element series-fed traveling wave out-of-line antenna array without a
termination load.
2.5. PHASED ANTENNA ARRAYS
50
Series-fed arrays can use in-line feeding or out-of-line feeding. In-line fed arrays
utilizes a single TL which directly feeds all the patch antennas as shown in Fig. 2.30.
On the other hand, out-of-line fed arrays utilize short TLs to connect the patches
to the main feed line as shown in Fig. 2.31. Series-fed arrays using the in-line feeding
technique occupy a very small area [76,77], and hence have the smallest insertion losses
associated with the feed network. However, the in-line feeding technique makes the
series-fed array very narrow band as it makes the inter-element phase shift a function
of the patch’s narrow-band impedance and the interconnecting TLs. On the other hand,
the out-of-line feeding technique alleviates the dependence of the inter-element phase
shift in series-fed arrays on the patch characteristics [78]. Furthermore, as illustrated
in Fig. 2.31, moving the patches off the centerline of the array gives more room for the
inclusion of the inter-element phase shifters required for beam steering.
Series-fed antenna arrays can also be classified into resonant [76–78] or traveling
wave arrays [77]. Resonant series-fed arrays can be designed using the in-line or the
out-of-line architectures. In either case, the array is terminated with either a short
circuit or an open circuit. Hence, the reflected wave creates a standing wave. Placing
the microstrip patches m × λ apart, where m could take any integer value, excites all
the patches with the same amplitude and with the same phase, i.e. φ = 0o . This makes
resonant series-fed arrays a very popular technique to build broadside arrays. However,
resonant arrays are not usually used for electronic beam steering. Furthermore, they
are very narrow-band, as any frequency variation changes the way the incident and
reflected waves add up at the patches, resulting in mismatches at the array input.
On the other hand, the feed-line of a traveling wave array is designed to be well
matched, and ideally free of any reflections. Similar to series-fed resonant arrays,
traveling wave arrays can be designed using the in-line or the out-of-line architectures.
However, the spacing between the elements does not have to be multiple integers of
the λ, which allows series-fed traveling wave arrays to produce off-broadside beams,
as well as broadside beams, if their spacing is a multiple of λ. For electronic beam
steering, this is achieved using electronically tunable inter-element phase shifters. The
signal amplitude on the main feed-line of a traveling wave array tapers due to the
power radiated by the patches and due to the insertion loss of the phase shifters. This
results in an imbalance in the signal power feeding each patch antenna. However, by
using proper design techniques, this amplitude imbalance can be eliminated. This will
2.5. PHASED ANTENNA ARRAYS
51
Table 2.2: Comparison Between Different Antenna Array Feed Network Topologies And
The Requirements On The Interstage Phase Shifters.
Parameter
Feed network size
Scan angle rangea
Bandwidth
Beam Squinting
Req. phase tuning range
Req. phase shifter losses
Req. phase shifter size
a
Parallel-Fed
Corporate
Large
Small
Large
Low
(N-1)φ
Relaxed
Relaxed
Series-Fed
In-line
Out-of-line
Very small Small
Large
Large
Small
Small
High
High
φ
φ
Small
Small
Very small Small
Scan angle range is estimated for the same phase tuning range.
be described later on in chapter 6. At the end of a series-fed traveling wave array, the
remaining power is usually absorbed by a termination impedance, usually a 50Ω load, as
illustrated in Fig. 2.30 for an in-line architecture. This implies that a small percentage
of the input power in the TX mode (or the received power in the RX mode) is dissipated
in the termination, which reduces the overall efficiency of the array. To increase the
efficiency of a traveling wave series-fed array, the conductance of the individual antennas
can be increased to couple into them more power from the main feed-line. However,
this loads the main feed-line resulting in higher mismatches. Alternatively, higher array
efficiencies are achieved by increasing the number of elements [79]. Another approach
used is to design the array in such a way that the last patch absorbs this remaining
power, as illustrated in Fig. 2.31 for the out-of-line architecture.
Table 2.2 qualitatively compares the achievable performance from the different feed
network topologies presented in this section as well as the requirements set on the
interstage phase shifters.
2.5.4 Metamaterial Phased Antenna Arrays
With the recent advances in metamaterial phase shifters, it is natural that antenna
arrays would also benefit from these advances. As described in section 2.3.5, metamaterial phase shifters are capable of achieving zero-degree phase shifts using the concept
of phase compensation, and it was demonstrated in [5] that these metamaterial-based
phase shifters achieve much lower group delays as opposed to a traditional -360o TL
2.5. PHASED ANTENNA ARRAYS
52
segment. A low group delay is necessary to minimize the beam squinting with frequency variations in series-fed antenna arrays. In order to demonstrate this, one can
obtain the derivative of the main beam angle θo using Eq.(2.41). This results in the
following expression:
µ
¶
λo
dθo
φ
≈
+ Tgd ,
(2.47)
dω
2πdE ω
where Tgd = −dφ/dω is the group delay of the inter-element phase shifters. Equation
(2.47) clearly indicates that a low group delay would result in less beam squinting
with frequency variations. This was verified experimentally in [6] where a series-fed
dipole array using PRI/NRI metamaterial phase shifters was presented. In [6], the
performance of a zero-degree metamaterial-based dipole array was compared to two of
the traditional approaches which achieve a -360o phase at the design frequency; the
first uses long meandered TLs, and the second uses a capacitively loaded TL. It was
demonstrated that the metamaterial-based dipole array results in less beam squinting
and occupies a more compact area compared to the traditional designs.
It is the aim of chapter 6 of this thesis to demonstrate the use of the electronically
tunable PRI/NRI metamaterial phase shifters, presented in chapter 4, towards the
design of series-fed antenna arrays in order to achieve electronic beam steering as well
as low beam squinting.
CHAPTER
3
CMOS Tunable Active Inductors
3.1 Introduction
T
he most popular technique used to build tunable active inductors (TAIs) is by
using gyrators. This technique has greatly benefited from the advances in modern
CMOS technologies, which are now capable of providing transistors with very high
unity-gain frequencies (ft s), thereby allowing the design of RF TAIs. However, most
of the published TAI designs suffer from one major drawback, which is their inability to independently control both the TAI inductance and quality factor. Moreover,
the few published TAI designs which demonstrated the independent L and Q tuning
capability [25, 38, 48] use techniques which are specific to each individual circuit implementation. Hence, a generalized technique that can be directly applied to the gyrator-C
architecture is missing and would prove to be very useful.
In this chapter, the addition of a feedback element to enhance the Q of TAIs is
generalized to the block diagram level of the gyrator-C architecture, thus making this
Q-enhancement technique applicable to any TAI based on the gyrator-C architecture
as opposed to previously published work [25, 38, 48], which do not provide this general framework. The effect of adding the feedback resistance is analyzed and design
53
3.2. TRADITIONAL GYRATOR-C ARCHITECTURE
54
gm1
Co1
Zin
ro1
L
Zin
ro2
Cin1+Co2
Rs
-gm2
Cin1+Co2
ro2
Cin2
Figure 3.1: Gyrator-C architecture and its equivalent circuit.
equations are presented. It will be shown that the modified gyrator-C architecture
allows independent control over L and Q. The proposed architecture is used to design
a 0.13µm CMOS grounded TAI operating from a 1.5V supply. Experimental results
from a test chip are used to verify some of the design equations, and to demonstrate
that the L and Q can be independently tuned.
The principles of enhancing the Q of the traditional gyrator-C architecture are described in section 3.2. Following that, the modified gyrator-C architecture is presented
in section 3.3. Finally, the design of the grounded TAI is presented in section 3.4.
3.2 Traditional Gyrator-C Architecture
The gyrator-C architecture consists of two transconductors (gm1 and gm2 ) connected
back-to-back, as shown in Fig. 3.1. If the output resistance and capacitance of the
transconductor gmi (where i = 1, 2) are modeled by roi and Coi , respectively, and its
input capacitance is modeled by Cini , then the input impedance, Zin , of the gyrator-C
circuit is expressed as:
1
+ s(Co1 + Cin2 )
ro1µ
¶
.
Zin =
1
Co1 + Cin2 Cin1 + Co2
2
+
+
+ gm1 gm2
s (Co1 + Cin2 ) (Cin1 + Co2 ) + s
ro2
ro1
ro1 ro2
(3.1)
This can be represented by the equivalent circuit shown in Fig. 3.1, where the series
and parallel resistors (RS and ro2 ) model the losses, and the capacitor is incorporated
3.2. TRADITIONAL GYRATOR-C ARCHITECTURE
55
to model the self-resonance of the TAI circuit. Furthermore, the inductance, L, and
the series resistance, RS , of the equivalent circuit are given by:
L=
Co1 + Cin2
, and
gm1 gm2
(3.2)
1
.
gm1 gm2 ro1
(3.3)
RS =
According to Eq.(3.2), the inductance of the TAI circuit can simply be tuned by varying
the transconductances gm1 and gm2 . This is usually done by varying the bias currents of
the two transconductors. However, this will also affect the value of the series resistance
RS .
3.2.1 Quality Factor Analysis
To understand the effect of tuning the inductance, L, on the TAI’s Q, one has to derive
the expression for Q using its basic definition Q = Im(Zin )/Re(Zin ), which results in
the following expression:
Q=ω×
Lro2 (1 − ω 2 (Cin1 + Co2 ) L) − ro2 (Cin1 + Co2 )RS2
.
RS2 + ro2 RS + ω 2 L2
(3.4)
It is instructive to obtain the expression of the circuit’s self-resonance frequency, ωr ,
since it helps in pointing out the dominant terms in Eq.(3.4). The self-resonance frequency is defined as the frequency at which the imaginary part of the input impedance
becomes zero, which for a gyrator-C TAI is expressed as:
s
ωr =
L − (Cin1 + Co2 )RS2
.
(Cin1 + Co2 )L2
(3.5)
Equation (3.5) indicates that for a high-Q TAI to have a high self-resonance frequency,
which is necessary for high-speed operation, L should be much greater than (Cin1 +
Co2 )RS2 , resulting in the following simplification for the self-resonance frequency:
s
ωr ≈
1
.
(Cin1 + Co2 )L
(3.6)
3.2. TRADITIONAL GYRATOR-C ARCHITECTURE
56
Furthermore, the quality factor expression of Eq.(3.4) can be simplified to:
Q≈ω×
Lro2 (1 − ω 2 (Cin1 + Co2 )L)
,
f (RS )
(3.7)
where the function
f (RS ) = RS2 + ro2 RS + ω 2 L2 .
(3.8)
As Eq.(3.7) indicates, Q is a function of frequency, starting at a low value and increases
with frequency until it peaks, then it starts to drop again due to the resonance with
the parasitic capacitance. The frequency at which Q reaches its peak value, ωp , can be
found by differentiating Eq.(3.7) and equating the derivative to zero. This results in
the following expression for ωp :
2RS + ωr2 L2
×
ωp =
4L2
s
Ã
1+
8RS ωr2 L2 (ro2 + RS )
1−
(2RS + ωr2 L2 )2
!
,
(3.9)
which can be approximated as:
s
ωp ≈ ωr ×
ωr
1 RS ro2
− 2 2 ≈√ .
2
ωr L
2
(3.10)
It is interesting to note that, the ratio between peak-Q frequency, ωp , of a gyrator-C
√
TAI and its self-resonance frequency, ωr , is approximately fixed and equal to 1/ 2.
To arrive at the result of Eq.(3.10), the frequency dependence of the equivalent series
resistance RS was neglected. This simplification results in a very small error between
the values of ωp predicted by Eq.(3.10) and the values obtained from the experiential
characterization of a gyrator-C based TAI, which will be demonstrated later in section
3.4.4. Substituting with ωp in Eq.(3.7) results in a peak-Q, Qp , of:
s
ro2
×
Qp ≈
2f (RS )
L
.
2(Cin1 + Co2 )
(3.11)
In order for the gyrator-C TAI to have a high peak-Q, the value of the function f (RS )
should be minimized. According to Eq.(3.3), which only allows positive values for RS ,
this implies that RS should be very small in order to minimize f (RS ). Consequently,
3.2. TRADITIONAL GYRATOR-C ARCHITECTURE
57
Negative RS
0
Figure 3.2: Function f (RS ) versus the negative series resistance RS .
one can neglect the first two terms of Eq.(3.8). Combining this with Eq.(3.10) and
Eq.(3.6), one can simplify Eq.(3.11) to:
r
Qp ≈ ro2 ×
(Cin1 + Co2 )
.
2L
(3.12)
Equation (3.12) shows the direct relationship between the inductance and the peak-Q
for a gyrator-C TAI, indicating that as L is tuned, via gm1 and gm2 , the peak-Q also
changes, which is not desirable in most applications. Instead, having independent control over L and Q is necessary to provide the capability of optimizing the performance.
3.2.2 Q-Enhancement Technique For Gyrator-C TAIs
To overcome this interdependence between the L and Q of a gyrator-C TAI, we further
exploit the dependence of the peak-Q on f (RS ), and hence RS . Figure 3.2 shows a
sketch for the quadratic function f (RS ) versus RS , the function f (RS ) has two negative
real roots given by:
ro2 1 q 2
±
ro2 − 4ωp2 L2 .
(3.13)
RS1,2 = −
2
2
Values of RS between the two roots (RS1 and RS2 ) will produce a negative Q possibly
resulting in an unstable TAI, therefore this region is avoided in general. Otherwise, if
3.3. THE MODIFIED GYRATOR-C ARCHITECTURE
58
gm1
Co1
Zin
ro1
L
Rf
Zin
ro2
Z
-gm2
Cin1+Co2
ro2
Rs
Cin1+Co2
Cin2
Figure 3.3: Modified gyrator-C loop and its equivalent circuit.
RS < RS2 or RS > RS1 , the Q is positive and the circuit is stable. To obtain a high
value for the peak-Q, RS should be picked close to either of the two roots but outside
the unstable region. Consequently, the TAI circuit has two possible operating points
on Fig. 3.2; P1 and P2 in regions 1 and 2 respectively. From Eq.(3.5), operating at P1
with a smaller |RS |, will result in a higher self-resonance frequency than operating at
P2 , but will make the Q more sensitive to any parasitic resistance that might add to
RS . Also, the effect of RS on the Q differs according to the operating point chosen;
increasing RS while operating at P1 lowers the Q. On the other hand, increasing RS
while operating at P2 increases the Q. In the next section, a modified structure for
the gyrator-C architecture, which uses an additional feedback resistance, is proposed.
Adding a feedback resistance allows the series resistance RS to achieve negative values.
Furthermore, it allows RS to be tuned without affecting the inductance. Consequently,
this modified gyrator-C architecture will achieve independent L and Q tuning.
3.3 The Modified Gyrator-C Architecture
This section analyzes the effect of adding a feedback resistance to the traditional
gyrator-C architecture. It will be shown that adding a feedback resistance to the
gyrator-C architecture generates the negative resistance RS necessary to enhance the
TAI’s Q. The modified gyrator-C block diagram and its equivalent circuit are shown in
Fig. 3.3, where the resistance Rf is the additional feedback resistance. One can show
3.3. THE MODIFIED GYRATOR-C ARCHITECTURE
59
that the expression for the input impedance of the modified gyrator-C architecture is:
µ
µ
¶¶
1
Rf
+ s Co1 + Cin2 1 +
+ s2 Co1 Cin2 Rf
ro1
ro1
,
Zin =
D(s)
(3.14)
where
D(s) = s3 Rf Cin2 Co1 (Co2 + Cin1 )
¶
¶
µ
µ
Rf
Rf
2
+ (Cin1 Cin2 + Co1 Co2 ) 1 +
+ Cin1 Co1 + Co2 Co1
+ s Co1 Cin2
ro2
ro1
µ
¶¶
µ
Cin1 + Co2 Co1 Cin2
Rf
+
+
1+
+ s
ro1
ro2
ro2
ro1
1
1
+
.
(3.15)
+
ro1 ro2 gm1 gm2
Although Eq.(3.14) appears to be very cumbersome, comparing it to Eq.(3.1) shows
that adding the feedback resistance Rf to the gyrator-C loop adds a zero and a pole to
the input impedance transfer function, which allows more control over the frequency
response of the TAI. To be specific, the additional zero in the input impedance transfer
function generates a negative, frequency dependent term that can be used to enhance
the TAI Q.
To understand more how the Q-enhancement takes place, the same approach of
section 3.2 is followed here and the circuit is modeled by the L-C circuit shown in
Fig. 3.3. It can be shown that the impedance of the inductive branch (Z), given by
the series combination of the equivalent inductance L and equivalent series resistance
RS , is expressed as:
µ
µ
µ
¶
¶
¶
1
Rf
1
2
× s Rf Co1 Cin2 + s Cin2 1 +
+ Co1 +
.
Z=
gm1 gm2
ro1
ro1
(3.16)
Hence, the equivalent inductance L and the equivalent series resistance are expressed
as:
µ
µ
¶
¶
1
Rf
× Cin2 1 +
+ Co1 , and
L=
(3.17)
gm1 gm2
ro1
µ
¶
1
1
2
×
− ω Cin2 Co1 Rf .
(3.18)
RS =
gm1 gm2
ro1
3.3. THE MODIFIED GYRATOR-C ARCHITECTURE
60
Equation (3.17) indicates that the inductance is independent of the feedback resistance
Rf as long as the feedback resistance is much smaller than the output resistance ro1
of the first transconductor. On the other hand, Eq.(3.18) indicates that, RS can take
negative values, and its value can be controlled via the feedback resistance Rf . By
comparing the L-C models of Fig. 3.1 and Fig. 3.3, one can conclude that the addition
of the feedback resistance to the gyrator-C loop generates the negative tunable resistance RS necessary for the Q-enhancement technique described in section 3.2. Thus, a
variable feedback resistance will allow us to control the TAI operating point on Fig. 3.2,
which will guarantee stable operation with a tunable high-Q. Furthermore, controlling
RS via Rf does not affect L (assuming ro1 >> Rf ), which consequently allows us to
independently tune L and Q. An intuitive way to explain how adding Rf enhances the
gyrator-C Q, is to consider the phase shift the output of the first transconductor gm1
undergoes before it feeds the second transconductor gm2 . Tuning Rf allows us to set
this phase shift in order to push the loop towards positive feedback.
As previously explained in section 3.2.2, the circuit has two possible operating points
for high-Q operation, which are represented by points P1 and P2 in Fig. 3.2. If the
TAI operates at point P1 , a smaller feedback resistance Rf is required. This will make
Q very sensitive to any interconnect resistance in the feedback path. Furthermore, if
the feedback resistance is slightly nonlinear, this will cause Q to be sensitive to the
signal level in the feedback path, which may lead to distortion and instability. This
nonlinearity might arise due to the implementation of the variable feedback resistance,
Rf , since, in most cases, Rf will vary with the signal level as will become evident in
section 3.4. On the other hand, the TAI will have a lower self-resonance frequency at
point P2 . However, operating at point P2 requires a larger feedback resistance, which
alleviates the sensitivity, distortion, and instability issues.
It is worth mentioning that this Q-enhancement technique is applicable to any TAI
based on the gyrator-C architecture. Consequently, the previous analysis provides a
general framework for the design of TAIs with independent L and Q, unlike previously
published work [25, 39, 48]. Moreover, the 1-port, modified gyrator-C architecture of
Fig. 3.3 can be easily extended to build differential or 2-port TAIs simply by replacing the single-ended transconductors gm1 and gm2 with differential transconductors as
shown in Fig. 3.4. Following the same theoretical procedure of the grounded architecture presented in section 3.3, one can show that adding two tunable feedback resistors
3.4. A GROUNDED 0.13µm CMOS TAI
61
+
+
Zin,diff
gm1
-
ro2
ro1
ro1
-
L
Co1
Rf
ro2
Co1
Rf
ro2
Cin1+Co2
Rs
ro2
Cin1+Co2
Rs
Zin,diff
+
+
Cin1+Co2
Cin1+Co2
Cin2
-gm2
-
Cin2
L
-
Figure 3.4: The modified differential gyrator-C architecture.
to the differential gyrator-C architecture produces a differential inductor with independently tunable L and Q. This differential topology was presented in more detail by
the author in [80]. However, an in-depth analysis of this differential topology was not
included as part of this thesis since all the circuits presented in chapters 4, 5, and 6
rely on the single-ended, 1-port, architecture.
3.4 A Grounded 0.13µm CMOS TAI
This section presents the design of a grounded 0.13µm CMOS TAI circuit capable
of independently tuning the L and Q by using the modified gyrator-C architecture
presented in section 3.3.
3.4.1 Circuit Design
Figure 3.5 shows the proposed TAI circuit, the first transconductor gm1 of the modified gyrator-C architecture is replaced by a differential pair (M1 − M2 ), and the second
transconductor gm2 is replaced by a common-source amplifier (M4 ). A tunable feedback
resistance Rf is inserted between the output of the first transconductor gm1 and the
input of the second transconductor gm2 . Although the transconductors were replaced in
this design with a differential pair and common-source stages, as previously mentioned,
this Q-enhancement technique is applicable to any gyrator-C TAI. As another exam-
3.4. A GROUNDED 0.13µm CMOS TAI
Vdd
62
Vdd
M6
Vdd
M5
IC
Vdd
Vc2
M12
Vdd
Vc1
M11
gm1
M1
M2
VCM
M8
M10
Zin
-gm2
M4
IB
M3
M7
M9
Rf
Figure 3.5: Proposed TAI circuit with the tunable feedback resistance.
ple, a differential, 2-port TAI circuit was presented by the author in [80], where two
differential-pair transconductors were used with the tunable feedback resistors. This
differential TAI, however, is not presented as part of this thesis, since it is not relevant
to the subsequent circuits presented in chapters 4, 5, and 6.
In the grounded TAI circuit of Fig. 3.5, transistors M3 and M5 mirror a ratio of the
reference current in (M7 − M8 ) and M6 , respectively, to bias the circuit. Moreover,
M12 mirrors half of the current in M11 to generate the necessary current to bias M2 .
To ensure that M3 and M9 mirror the desired current from the reference transistor
M7 , a low-voltage cascode current mirror is used. Sizing cascode transistors M8 and
M10 appropriately will guarantee that the drains of M3 , M7 , and M9 have the same
potential, this is achieved by setting:
W10
W2 W7 /L7
W8
=
=2
×
.
L8
L10
L2
W3 /L3
(3.19)
The transistor sizes of the proposed grounded TAI circuit are given in Table 3.1, where
3.4. A GROUNDED 0.13µm CMOS TAI
63
Table 3.1: Transistor Sizes of the TAI Circuit
Transistor Size nf × Wf × L
Transistor Size nf × Wf × L
M1 , M2
M8 , M10
40 × 2.85µm × 0.12µm
4 × 2.85µm × 0.12µm
M 7 , M9
M3
60 × 3.3µm × 0.2µm
3 × 3.3µm × 0.2µm
M6
3 × 4µm × 0.2µm
M5
36 × 4µm × 0.2µm
M12
20 × 4µm × 0.2µm
M11
2 × 4µm × 0.2µm
M4
40 × 4.5µm × 0.12µm
Table 3.2: Transistor Sizes of the Digital/Analog Tunable Feedback Resistance Rf
Transistor Size nf × Wf × L
Transistor Size nf × Wf × L
Mf 1
1 × 0.5µm × 2µm
Mf 2
1 × 0.5µm × 1µm
Mf 4
1 × 2µm × 1µm
Mf 3
1 × 1µm × 1µm
Rf 0
500Ω
Mf 5
1 × 4µm × 1µm
MP
12 × 5µm × 0.12µm
MN
4 × 5µm × 0.12µm
nf is the number of fingers used to implement each transistor and Wf is the finger width.
The choice of the transistor sizes, especially M1 , M2 , and M4 dictates the achievable
range of inductances by the TAI circuit. In general, to achieve large inductances,
smaller sizes should be picked. However, using small sizes for the transistors makes
the TAI circuit incapable of supporting a large signal swing at its input port with an
acceptable level of distortion. On the other hand, to achieve smaller inductances, either
the sizes of the transistors should be large, which will add more parasitic capacitance
to the TAI circuit, or their bias current should be increased, which increases the power
dissipation. Hence, there exists many trade-offs between the desired inductance range,
power dissipation, speed, signal swing, and area. Consequently, careful simulations
were required to determine the appropriate transistor sizes.
Tunable Feedback Resistance
To implement the tunable feedback resistance Rf , binary weighted NMOS transistors
operating in the triode region are connected in parallel as shown in Fig. 3.6. The NMOS
transistors are also connected in parallel to a fixed resistance, Rf 0 , to improve linearity
by making the overall feedback resistance and hence Q less sensitive to the variations
in the overdrive voltage of the transistors. This will make Q less sensitive to the input
signal swing and will improve the circuit stability. The NMOS transistors are switched
3.4. A GROUNDED 0.13µm CMOS TAI
64
Rf
Rf0
Vf
Mf1
Vf
Digital word
D1
Mf5
D5
Figure 3.6: Digital/analog feedback resistance Rf .
ON and OFF using a 5-bit digital word, this allows coarse tuning of the Q. To enable
fine tuning, the digital word is applied to the gates of the NMOS transistors through
five CMOS inverters having a variable supply voltage, Vf , as shown in Fig. 3.6. The
voltage Vf is used to set the level of the gate voltage for the ON NMOS transistors [81].
Combining digital and analog control to tune the resistor value allows a wider tuning
range for the feedback resistance, and hence for the Q. This also makes the circuit more
robust to process and temperature variations. To reduce the number of pads required
by the TAI circuit and hence reduce the circuit area, the 5-bit digital word is serially
shifted into an on-chip shift-register. The sizes of the transistors used to implement
the digital/analog tunable feedback resistance Rf are given in Table 3.2.
3.4.2 TAI Small-Signal Analysis
An approximate expression for the TAI equivalent L and RS can be directly obtained
from Eq.(3.17) and Eq.(3.18) by replacing gm1 and gm2 with gm1,2 /2 and gm4 , respectively. This results in the following expressions for the inductance and series resistance
3.4. A GROUNDED 0.13µm CMOS TAI
65
L
Cgs1/2+Cgd1+
Zin C +C +C
db4
gd5
db5
Rs
ro4||ro5
Z
Figure 3.7: Grounded active inductor equivalent circuit.
of the equivalent L-C circuit of Fig. 3.3:
L≈
µ
2
gm1,2 gm4
RS ≈
µ
× Cgs4
2
gm1,2 gm4
µ
×
Rf
1+
ro
¶
¶
+ Co , and
1
− ω 2 Co Cgs4 Rf
ro
(3.20)
¶
,
(3.21)
where ro and Co are the output resistance and capacitance of the differential pair
transconductor. Equation (3.20) shows that, provided that Rf is much smaller than
ro , L is independent of the feedback resistance and hence is independent of Q.
Also, by closely investigating Eq.(3.20), one will realize that the value of the inductance has some dependence on process, supply, and temperature variations. Since
the focus of this work has been on the initial development and validation of the TAI,
a detailed sensitivity analysis of the performance of the TAI to process, supply and
temperature variations lies outside the scope of this thesis. However, when using this
circuit in a practical application, one can ensure that it achieves a process, supply, and
temperature independent inductance by using a constant-gm bias circuit [82] to bias
transistors M1 , M2 , and M4 . Alternatively, since the circuit provides a tunable inductance, one can simply ensure that the circuit’s tuning range is wide enough to calibrate
for process, supply, and temperature variations. Similarly, since Q is a function of the
feedback resistance which is implemented using MOS transistors it exhibits process,
supply, and temperature dependence. However, a high Q can be achieved by means of
the independent L and Q tuning capability of the circuit.
More elaborate circuit analysis replaces each transistor by its small-signal equivalent
model (gm , ro , Cgs , Cgd ), but results in a fairly complicated expression for the input
impedance. To obtain a simplified expression, which is necessary to gain insight in
the circuit operation, the effect of the output resistance of the NMOS transistors is
3.4. A GROUNDED 0.13µm CMOS TAI
66
neglected. The input impedance Zin obtained from the analysis can be represented by
the equivalent circuit shown in Fig. 3.7. The impedance of the inductive branch, Z,
which consists of the series combination of L and RS , can be expressed as:
¶¶
µ
µ
1
Rf
+
s Rf Co Cgs4 + s Co + Cgs4 1 +
ro
ro
.
Z ≈2×
gm1,2 gm4
2
(3.22)
This results in the same inductance and series resistance expressions given by Eq.(3.20)
and Eq.(3.21), respectively, which is consistent with our generalized gyrator-C block
diagram analysis presented in section 3.3.
3.4.3 TAI Noise Analysis
This section analyzes the noise generated by the TAI circuit due to the various transistors as well as the feedback resistor Rf . Our goal is to find an equivalent noise
current source (inL ), which can be connected in parallel to the TAI circuit to model
the effect of the various noise sources. The results of this analysis will be used later on
in chapter 5 to quantify the noise performance of the TAI-based directional coupler.
In this analysis, the effect of the flicker noise generated by the transistors is neglected,
since for RF applications the design frequency is well above the 1/f corner frequency.
Therefore, only the thermal noise components are considered.
A simplified schematic of the TAI circuit with the different noise sources is shown
in Fig. 3.8, where i2nMx is the mean-square value of the drain current thermal noise
2
is the mean-square value of the thermal noise
generated by transistor Mx , and vnR
f
voltage generated by the feedback resistance Rf . For simplicity, the gate noise is
neglected throughout this analysis as well as the output resistances ro1,2 , and the gatesource capacitances Cgs1,2 of transistors M1 and M2 . Assuming all the various noise
sources are uncorrelated, one can use superposition to show that, the mean-square
value of the input referred noise current (inL ) at the inductor input port is expressed
3.4. A GROUNDED 0.13µm CMOS TAI
67
Vdd
Vdd
in5
M5
in12
M12
Vdd
in1
in2
M1
M2
Inductor
input port
Inductor
input port
in4
L
inL
in3
M4
M3
vnRf
Rf
+-
Figure 3.8: Simplified TAI schematic with the main current and voltage noise sources,
and equivalent lumped noise current model.
as:
2
vnR
(1 + ω 2 Co2 ro2 )
i2n1 + i2n2 + i2n3
f
+ i2n12 +
4
ro2
2
i2nL (ω) = i2n4 +i2n5 +gm4
×µ
¶¶2 , (3.23)
¶2
µ
µ
1
R
f
− ω 2 Rf Co Cgs4 + ω 2 Co + Cgs4 1 +
ro
ro
where ro and Co are the output resistance and capacitance of the differential pair
respectively. If the TAI circuit is configured for high-Q operation, one should set the
feedback resistance Rf to cancel the resistive part of the circuit’s input impedance.
According to the approximate expression of Eq.(3.21), this results in the following
value for the feedback resistance:
Rf ≈
1
ωo2 ro Co Cgs4
,
(3.24)
where ωo is the design frequency. Hence, for high-Q operation, the mean-square value
3.4. A GROUNDED 0.13µm CMOS TAI
68
1mm
Open
ct. pad
Digital
circuitry
inputs
G
S
Digital
control
circuit Short
ct. pad
G
S
G Active
inductor
circuit
0.5mm
DC/bias
inputs
G
S
G
Figure 3.9: Tunable active inductor die micrograph.
of the input referred noise current becomes:
2
vnR
(1 + ωo2 Co2 ro2 )
i2n1 + i2n2 + i2n3
f
2
+ in12 +
4
ro2
2
2
2
2
.
inL (ωo ) ≈ in4 + in5 + gm4 ×
¶¶
µ
µ
2
Rf
2
ωo Co + Cgs4 1 +
ro
(3.25)
The transistor drain thermal noise current i2nMx is given by 4kT γgmx , whereas the
2
is given by 4kT Rf , where k = 1.38×10−23 J/K is the
resistor thermal noise voltage vnR
f
Boltzmann constant, and T is the absolute temperature in degrees Kelvin. The value
of the coefficient γ typically ranges from 2 to 3 for short-channel transistors [44, 83].
This results in the following expression for the TAI equivalent noise current:

Rf (1 + ωo2 Co2 ro2 )
2gm1,2 + gm3
+ gm12 +


4
γro2


2
2
inL (ωo ) = 4kT γ gm4 + gm5 + gm4 ×
.
¶¶2
µ
µ


R
f
ωo2 Co + Cgs4 1 +
ro
(3.26)

3.4.4 Physical Realization and Experimental Characterization
Figure 3.9 shows the die micrograph of the fabricated grounded TAI circuit, the chip
was fabricated in a 1.5V , 0.13µm CMOS process. The TAI circuit occupies 150µm ×
3.4. A GROUNDED 0.13µm CMOS TAI
69
170µm. A 150µm-pitch GSG (ground-signal-ground) probe was used to probe the TAI,
while two 80µm-pitch multi-contact wedges with DC needles were used to provide the
bias and control voltages. A CS-5 calibration substrate was used to perform a 1-port
calibration to de-embed the frequency response of the RF probe, connectors, and cable.
The TAI was characterized by measuring the reflection coefficient, S11 , that was in turn
used to extract the L and Q. As indicated by Fig. 3.9, open- and short-circuited pads
were included on the fabricated chip to estimate the input’s pad parasitic capacitance
and inductance. The pad capacitance and series inductance were obtained from the
measured input reflection coefficients of the open- and short-circuited pads respectively.
For a 65µm×65µm square pad, the measurements show that, the capacitance is 30fF,
and the inductance is 70pH. Consequently, they will not have a large effect on the TAI
performance, and all the measurements presented herein will include the effects of the
pad parasitics, i.e. the pad parasitics were not de-embedded. The tuning characteristics
of the TAI circuit are demonstrated through tuning modes I and II described below.
Tuning Mode I: Variable L and Fixed Peak-Q
In this mode, the inductance is tuned while maintaining a fixed peak-Q. The TAI L
is tuned via gm1,2 and gm4 according to Eq.(3.20), where the two transconductances
are set by the two bias voltages VC2 and VC1 , respectively (see Fig. 3.5). However,
this will also change the value of the peak-Q according to Eq.(3.11). To compensate
for this change, the feedback resistance Rf is tuned to bring the peak-Q back to its
desired value. According to Eq.(3.20), changing Rf does not have a significant effect
on L. As indicated by Eq.(3.6), changing the bias point to tune L will also affect the
TAI self-resonance frequency, fr , since the change in L necessitates a change in the
frequency at which L resonates with the TAI parasitic capacitance.
To fully characterize the TAI circuit performance, the two bias voltages VC1 and VC2
are swept using two DC voltage sources and the measured L and Q are reported herein.
The measured L and Q are plotted in Fig. 3.10 when VC1 is fixed at 0V and VC2 is swept
from 0.3V to 0.6V. As indicated by Fig. 3.10-a, increasing VC2 results in a larger value
for the bias current IB , and consequently gm1,2 increases. This causes L to decrease.
Across this inductance tuning range, the peak-Q is maintained in excess of 100 as
shown by Fig. 3.10-b. This high Q is achieved by adjusting the value of the feedback
* VC2=0.3V, + VC2=0.35V
∆ VC2=0.4V, x VC2=0.5V
O VC2=0.6V
4
3
2
1
0
1
2
3
4
Frequency (GHz)
70
Measured TAI quality factor
Measured TAI inductance (nH)
3.4. A GROUNDED 0.13µm CMOS TAI
250
200
* VC2=0.3V, + VC2=0.35V
∆ VC2=0.4V, x VC2=0.5V
O VC2=0.6V
150
100
50
0
5
1
2
3
Frequency (GHz)
(a)
4
(b)
Figure 3.10: Measured TAI characteristics versus frequency when VC1 =0V and VC2
changes from 0.3V to 0.6V: (a) Inductance, (b) Quality factor.
Table 3.3: Measured Inductances for the TAI at 2GHz for Different Values of the Bias
Voltages VC1 and VC2 .
Voltage
VC1
0V
0.1V
0.2V
0.35V
0.4V
0.3V
4.4nH
5nH
6.5nH
9.5nH
11.7nH
0.35V
2.1nH
1.9nH
2.4nH
VC2
0.4V
1.3nH
1.5nH
1.8nH
0.5V
0.9nH
1.1nH
0.6V
0.8nH
0.9nH
voltage Vf , which controls the value of the series resistance, RS . However, increasing
the inductance shifts the self-resonance frequency of the TAI to lower frequencies. This,
in turn, moves the the location of the peak-Q to lower frequencies as expected from
Eq.(3.10).
Figures (3.11) and (3.12) show the measured L and Q when VC1 is fixed at 0.1V and
0.2V, respectively, and VC2 is swept. In Fig. 3.11, VC2 is swept from 0.3V to 0.6V,
while in Fig. 3.12, VC2 is swept from 0.3V to 0.4V. On the other hand, Fig. 3.13 shows
the measured L and Q of the TAI circuit when VC1 is swept from 0.4V to 0V and VC2
is fixed at 0.3V. Decreasing VC1 results in a larger transconductance gm4 , resulting in
a lower inductance.
5
4
3
2
1
0
−1
* VC2=0.3V, + VC2=0.35V
∆ VC2=0.4V, x VC2=0.5V
O V =0.6V
C2
1
71
Measured TAI quality factor
Measured TAI inductance (nH)
3.4. A GROUNDED 0.13µm CMOS TAI
2
3
4
Frequency (GHz)
150
100
50
0
5
* VC2=0.3V, + VC2=0.35V
∆ VC2=0.4V, x VC2=0.5V
O VC2=0.6V
1
1.5
2
2.5
3
Frequency (GHz)
(a)
3.5
4
(b)
∆ VC2=0.3V, O VC2=0.36V
x VC2=0.4V
6
5
4
3
2
1
0
−1
1
2
3
Frequency (GHz)
(a)
4
Measured TAI quality factor
Measured TAI inductance (nH)
Figure 3.11: Measured TAI characteristics versus frequency when VC1 =0.1V and VC2
changes from 0.3V to 0.6V: (a) Inductance, (b) Quality factor.
250
∆ VC2=0.3V, O VC2=0.36V
x V =0.4V
C2
200
150
100
50
0
1
1.5
2
Frequency (GHz)
2.5
3
(b)
Figure 3.12: Measured TAI characteristics versus frequency when VC1 =0.2V and VC2
changes from 0.3V to 0.4V: (a) Inductance, (b) Quality factor.
10
300
O VC1=0.4V, x VC1=0.35V
∆ VC1=0.15V, + VC1=0V
5
0
0.5
1
1.5
2
Frequency (GHz)
(a)
72
Measured TAI quality factor
Measured TAI inductance (nH)
3.4. A GROUNDED 0.13µm CMOS TAI
2.5
3
O VC1=0.4V, x VC1=0.35V
∆ VC1=0.15V, + VC1=0V
250
200
150
100
50
0
0.4
0.6
0.8
1
1.2
1.4
Frequency (GHz)
1.6
(b)
Figure 3.13: Measured TAI characteristics versus frequency when VC1 changes from 0V
to 0.4V and VC2 =0.3V: (a) Inductance, (b) Quality factor.
In summary, the results show that the proposed TAI circuit has a very wide inductance tuning range; the inductance can be tuned from 0.93nH to 2.7nH at the 2.4GHz
ISM band, while maintaining a peak-Q greater that 100 across the entire inductance
tuning range. However, the Q at 2.4GHz ranges from a maximum of 180, at the middle
of the inductance tuning range, to a minimum of 15 at the extremes of the tuning range.
The largest inductance tuning range is achieved by the circuit at 2GHz, where the circuit can provide inductances as low as 0.8nH and as high as 11.7nH while maintaining
a peak-Q in excess of 100. Table 3.3 summarizes the measured inductance values at
2GHz for the different values of the bias voltages VC1 and VC2 .
As illustrated by the various inductance plots, when the inductance increases the
TAI’s self-resonance frequency, fr , decreases. As previously explained, this behavior
is expected from analyzing Eq.(3.6). The measured TAI self-resonance frequencies,
fr , are plotted versus the measured TAI inductance, L, in Fig. 3.14 together with
the theoretical values predicted from Eq.(3.6). The plot shows very good agreement
between the theoretical prediction and the measured values although the expression of
Eq.(3.6) is derived based on the gyrator-C block diagram and it neglects the second
term of Eq.(3.5). This also shows that the simple passive L-C model of Fig. 3.1 yields
accurate results.
3.4. A GROUNDED 0.13µm CMOS TAI
73
Resonance frequency, fr (GHz)
5.5
Measurements
Theory
5
4.5
4
3.5
3
2.5
2
1.5
1
2
3
4
5
Measured TAI inductance, L (nH)
6
Figure 3.14: Theoretical and measured self-resonance frequency, fr , versus the inductance, L, for the different bias conditions.
p
Peak−Q frequency, f (GHz)
4
3.5
3
2.5
2
1.5
1
2
Measured TAI
Theory
CMOS TAI [25]
CMOS TAI [39]
GaAs TAI [48]
3
4
5
Resonance frequency, fr (GHz)
6
Figure 3.15: Theoretical and measured peak quality factor frequency, fQ , versus the
self-resonance frequency, fr . The measured data presented is from the
proposed circuit and from [25], [39], and [48], while the theoretical expression used for the comparison is fQ = √fr2 , which is given by Eq.(3.10).
3.4. A GROUNDED 0.13µm CMOS TAI
74
As previously mentioned, increasing L causes the peak-Q frequency, fp , to shift to
lower values. This is a result of using the gyrator-C architecture to implement the
TAI, which results in a direct relationship between both its peak-Q and resonance frequencies as given by Eq.(3.10). The measured peak-Q frequencies of the proposed TAI
circuit and the theoretical values predicted by Eq.(3.10) are plotted in Fig. 3.15 versus
the self-resonance frequency, fr . The figure shows good agreement between the measurements and the theoretical expression of Eq.(3.10), although it was derived using the
generalized gyrator-C block diagram. To further demonstrate this, Fig. 3.15 also plots
fp versus fr for other gyrator-C based TAI circuits presented in the literature [25,39,48].
Despite being fabricated in different technologies; GaAs, 0.18µm CMOS, and 0.13µm
CMOS, in most of the cases, their peak-Q frequencies can be accurately estimated
from the theoretical expression of Eq.(3.10). This is true even though the derivation
of Eq.(3.10) neglects the frequency dependence of the equivalent series resistance RS .
The difference between the measured fp and the theoretical predication in Fig. 3.15 can
be attributed to the negative term of Eq.(3.10) which was neglected. Also, Fig. 3.15
shows that the proposed TAI circuit has a very wide tuning range as it can operate
with a peak-Q in excess of 100 over a very wide frequency range; 1.3-3.3GHz. The
circuit inductance, for each of these cases, can be obtained by combining the results of
Fig. 3.14 and Fig. 3.15.
Tuning Mode II: Variable Q and Fixed L
In this mode, L is fixed and the peak-Q is tuned by changing the feedback resistance Rf .
Increasing Rf will decrease the series resistance RS according to Eq.(3.21). Assuming
the TAI is operating at point P2 on Fig. 3.2, f (RS ) will increase causing the peak-Q to
decrease. On the other hand, decreasing Rf will result in a higher peak-Q. Tuning the
peak-Q via the feedback resistance Rf does not affect the TAI bias point. Consequently,
the transconductances gm1,2 and gm4 are unaffected. Moreover, during the design phase
the feedback resistance Rf was chosen much smaller than the output resistance of
the differential pair transconductor, ro . According to Eq.(3.20), this ensures that the
inductance will remain unchanged while the Q is set to its desired value, thus allowing
us to achieve independent tuning.
The measured Q of the TAI is plotted versus frequency in Fig. 3.16 for different
3.4. A GROUNDED 0.13µm CMOS TAI
75
Measured TAI quality factor
250
Vf=800mV
Vf=900mV
V =920mV
f
V =950mV
200
f
150
V increasing &
f
Rf decreasing
100
50
0
1
1.5
2
2.5
Frequency (GHz)
3
3.5
Figure 3.16: Measured Q versus frequency for different feedback voltages Vf .
Vf=0.8V® 0.95V
6.7% variation in
L at the peak Q
frequency,
fQp=2.4GHz
TAI resonates at
f =3.1GHz
r
Figure 3.17: Measured S11 of the TAI for different feedback voltages Vf .
3.4. A GROUNDED 0.13µm CMOS TAI
76
values of the feedback voltage Vf . These measurements were obtained with the TAI
configured for a nominal inductance of 1.7nH. The plot shows that the peak-Q can be
tuned from 10 to 200 by sweeping Vf from 800mV to 950mV. Across this tuning range,
the measured inductance variation at 2.4GHz is less than 6.7% of its nominal value.
As indicated by the measured Q plots, the peak-Q frequency, fp , remains relatively
fixed at 2.4GHz, which is a direct result of the independent L and Q tuning capability,
since the relatively unchanged L results in the same self-resonance as well as peak-Q
frequencies as indicated by Eq.(3.6) and Eq.(3.10) respectively. The measured reflection
coefficient of the TAI is plotted in Fig. 3.17 for the different values of the feedback
voltage. The TAI circuit resonates at 3.1GHz regardless of the value of its peak-Q.
It is also worth mentioning that, tuning Q using the feedback resistance Rf does not
require any additional power dissipation, as opposed to using traditional methods such
as cross-coupling a differential pair to generate a negative resistance [43].
Although all the measured results that were presented in the previous sections were
obtained from a single die, other dice were also tested to verify the consistency of the
results. Furthermore, the consistency of the die-to-die performance will be practically
demonstrated in chapter 6, through the use of multiple chips to design the steerable
antenna array, which uses 6 packaged TAI chips within its beam steering network.
Measurements Versus Simulations
The proposed TAI circuit does not use a capacitor to terminate the the output of the
differential-pair transconductor, instead it relies on the gate capacitance of transistor
M4 . As previously explained in chapter 2, this makes the TAI circuit suitable for
high-speed operation. However, it makes the TAI circuit very sensitive to any parasitic
capacitance, requiring special care during the design, simulation, and layout phases in
order to obtain the desired response.
Figure 3.18 shows the simulated L and series resistance for a subset of the bias conditions; (VC1 =0V, VC2 =0.6V) and (VC1 =0V, VC2 =0.6V), and compares the simulated
results with the measurements. Good agreement is achieved between the measured and
simulated inductances with a mismatch of approximately 15% at 2.4GHz. To achieve
this fairly good agreement between the measured and simulated inductance, a fixed
100pH inductor is added in series with the TAI, as shown in Fig. 3.19, to model the
3.4. A GROUNDED 0.13µm CMOS TAI
5
Series Resistance (Ω)
Inductance (nH)
20
Measurements
Simulations
4
3
2
Vc2=0.4V
1
Vc2=0.6V
0
−1
1
77
2
3
4
Frequency (GHz)
15
10
Vc2=0.4V
5
0
−5
1
5
Measurements
Simulations
Vc2=0.6V
1.5
2
2.5
3
Frequency (GHz)
(a)
3.5
4
(b)
Figure 3.18: Measured and simulated results versus frequency when VC1 =0V and VC2
is set to 0.6V and 0.4V: (a) inductance (b) series resistance.
VC1
Vdd
VC2
Lpad
M1
VCM
M2
100pH
TAI
circuit
Zin
M3
Cp
100fF
Vf
Figure 3.19: Circuit setup used for the simulation of the TAI circuit.
3.4. A GROUNDED 0.13µm CMOS TAI
78
RF signal
combiner
f1
+
Circulator
probe
1-port
DUT
f2
RF signal
sources
Grounded tunable
active inductor chip
Spectrum
Analyzer
Figure 3.20: Experimental test setup used for characterizing the TAI circuit linearity.
pad and input port interconnect inductance. Also, a fixed 100fF capacitor was added
at the gate of M4 to model the parasitic capacitance associated with this critical node.
The measured and simulated series resistance values, shown in Fig. 3.18-b, fairly match
with each other. However, they are off by approximately 4Ω at 2.4GHz.
To this end, the TAI was extensively characterized, and its measured S-parameters
were used to design all the subsequent circuits presented in this thesis (the phase
shifters, the directional coupler, and the antenna array). This approach will enable us
to accurately predict the response of the different TAI-based circuits, and achieve good
matching between the measured and the desired response.
Linearity Measurements
Numerous measures are incorporated in the design of the TAI to achieve good linearity.
The TAI circuit is designed to allow a large signal swing at its input port by setting the
common-mode voltage, Vcm , to VDD /2. Also, the bias current of transistor M4 , IC , is
selected large enough to allow the TAI to supply and drain the input current without
considerably affecting the bias point of M4 .
Despite being a 1-port device, the linearity of the grounded TAI circuit can be experimentally characterized by using an RF signal source to excite it through a circulator
as shown in Fig. 3.20. The circulator directs the reflected wave from the TAI circuit
to its third port and the various inter-modulation components are analyzed using a
3.4. A GROUNDED 0.13µm CMOS TAI
79
−5
Output power (dBm)
−10
−15
−20
−25
−30
−35
−40
−45
−30
−25
−20
−15
−10
−5
Input power (dBm)
0
5
10
Figure 3.21: Amplitude of the power reflected back by the TAI versus the input power
when applying a single RF signal source.
spectrum analyzer. This experimental setup was presented in [84] to characterize the
linearity of a grounded GaAs TAI. The 1-dB compression point of the TAI circuit is
characterized by using only one RF signal source, and measuring the amplitude of the
power reflected by the TAI. Figure 3.21 shows the amplitude of the reflected power at
the same frequency of the RF signal source, f1 , which was selected as 4GHz. The measured results show that the TAI achieves a +2.16dBm input compression point, which
corresponds to approximately an 800mVpp voltage swing at the TAI input port while
operating from a 1.5V supply. This is considered a very high 1-dB compression point
for an active inductor. However, this comes at the expense of the power consumption,
which is reported in the Table 3.4. The IIP3 (third-order input intercept point) of the
TAI is characterized by combining two input frequencies f1 and f2 and extrapolating
the measured output powers at f1 and 2f1 − f2 until they intersect. The measured
output power at f1 and 2f1 − f2 are plotted in Fig. 3.22, where f1 is chosen as 4GHz
and the frequency separation between the two input signals was chosen as 10MHz. As
indicated by Fig. 3.22, the TAI achieves an IIP3 of 12.5dBm.
3.4. A GROUNDED 0.13µm CMOS TAI
80
0
Output power (dBm)
−20
−40
−60
−80
−100
Ouput power at f1
Ouput power at 2f1−f2
−120
−140
−30
−20
−10
0
Input power (dBm)
10
Figure 3.22: Amplitude of the power reflected back by the TAI at f1 and 2f1 −f2 versus
the input power when combining two RF signal sources.
GaAs
65⇒90
–
–
–
1.1
GaAs
9.6⇒56
@1.7GHz
3400
1.7
2.2
Technology
L tuning range (nH)
measured at
Peak Q Qp
Peak Q freq. fQ (GHz)
Res. freq. fr (GHz)
–
-0.9dBm
–
369
900×700
–
–
Power diss. (mW@VDD )
TAI size (µm×µm)
1dB comp. point
IIP3
–
–
900×700
240⇒90
6V
–
b
RS :-5.6⇒20.8
1
–
–
–
65⇒110
GaAs
1µm
[38]
–
-7dBm
40×50
1.8
1.8V
–
–
>9.5
7⇒2
>50
d
@5GHz
1⇒8
BiCMOS
0.18µm
[25]
–
–
100×50
7.2
1.8V
–
–
–
1.65
–
@2.1GHz
2.1⇒5.6
CMOS
0.18µm
[25]
–
–
100×50
7.2
1.8V
–
–
4.1⇒2.5
3⇒0.5
>50
@2GHz
1⇒8.5
CMOS
0.18µm
[25]
–
–
88×90
8
2V
–
–
2.5,2.8
1.55,2.2
70,51
–
5.7,8
CMOS
0.18µm
[39]
+12.5dBm
+2.16dBm
150×170
52.5⇒22.5
1.5V
6.7%@2.4GHz
Q:10⇒200
5.35⇒2.4
3.5⇒0.75
>100
@2GHz
0.83⇒11.7
CMOS
0.13µm
This work
b
Tuning mode II can be characterized by measuring the tuning range for either RS or Q.
Size includes bias and on-wafer measurement pads
c
Input power at which strong dependence was observed between both L and RS and the input power level.
d
Simulated input power at which the 2nd -order harmonic in the inductor current becomes equal to the fundamental component.
a
c
1200×1700
–
9V
Supply voltage VDD
b
4%
2%@1.7GHz
b
RS :-10⇒15
RS :-20⇒44
Q or RS tuning range
L variation
a
1µm
1µm
Min. feature size
[37]
[48]
Specification
Table 3.4: Comparison Between Different Tunable Active Inductor Implementations
Comparison of TAI Performance
3.4. A GROUNDED 0.13µm CMOS TAI
81
3.4. A GROUNDED 0.13µm CMOS TAI
82
Table 3.4 presents a detailed comparison between the proposed TAI and different
TAIs presented in the literature [25, 37–39, 48]. Among these recently published TAIs,
this work provides the largest inductance tuning range and the highest resonance frequencies (with the exception of the BiCMOS design) in spite of the low-voltage CMOS
process. Furthermore, the proposed design provides a mechanism to control the Q with
very small variations in the inductance. Compared to the other CMOS and BiCMOS
implementations, the proposed TAI dissipates more DC power in order to achieve better
linearity. Unfortunately, linearity was not reported in most of the previous publications
to allow for an adequate comparison.
CHAPTER
4
Wide Tuning Range CMOS Phase Shifters
P
hase shifters are essential building blocks for many RF and microwave applications.
One of the most important applications of phase shifters is electronically steerable
antenna arrays. The direction of the antenna array’s main beam can be controlled by
appropriately setting the relative phases of the signals feeding each antenna element in
the array. To achieve a wide scan-angle range, it is necessary to design phase shifters
with a wide tuning range. Furthermore, to avoid power losses due to reflections at
the input and output ports of a phase shifter, it is required to have a constant input
and output impedance across its entire tuning range. These two constraints (i.e., wide
tuning range, and matching) limit our choice of the phase shifter’s architecture.
4.1 Introduction
As described in chapter 2, to achieve a wide tuning range from an L-C phase shifter,
two tunable elements are necessary. This requires the use of both varactors and TAIs
to extend the phase tuning range. To facilitate using TAIs to design phase shifters, one
should use L-C phase shifter architectures requiring grounded inductors as opposed
to floating or 2-port inductors. Among the different L-C architectures in Fig. 2.12,
83
4.1. INTRODUCTION
84
-ve
C
C
TAI
Electronic Beam Steering Network
(a) MMIC High-pass TAI-based PS
-ve
+ve
C
C
TAI
(b) Printed TAI-based PRI/NRI PS
C
Lo
C
Lo
TAI
Co
Co
Co
Co
Electronic Beam Steering Network
(c) MMIC Lumped-Element TAI-based PRI/NRI PS
C
Lo
Co
Lo
Co Cv
L
Co
C
Co
(d) MMIC Lumped-Element Passive PRI/NRI PS
Figure 4.1: Different series-fed phased array designs and their radiation patterns: (a)
shows the high-pass phase shifters used by the top design, (b) to (d) show
the PRI/NRI phase shifters used by the lower design.
4.1. INTRODUCTION
85
this limits us to the high-pass Tee architecture redrawn here in Fig. 4.1-a, since it
uses the minimum number of inductors as opposed to the high-pass Π architecture.
Consequently, the first wide tuning range phase shifter presented in this chapter uses
the high-pass Tee architecture. Although this is a standard phase shifter architecture,
the design presented here combines the use of varactors and TAIs to insure the matching
of the phase shifter across its entire phase tuning range besides extending its tuning
range.
The high-pass phase shifter is only capable of providing positive phase shifts, which
according to Eq.(2.41) will only result in negative scan angles if used in the feed network
of a series-fed phased array1 . Figure 4.1 shows two series-fed phased arrays, the top one
uses tunable high-pass phase shifters, which makes the array only capable of achieving
negative scan angles. Whereas, the lower one uses phase shifters which enable the
antenna array to center its main beam around the broadside direction. To achieve this,
the phase shifters are required to generate both positive and negative phase shifts1 . In
other words, their phase response should be centered around 0o . As described in chapter
2, PRI/NRI metamaterial phase shifters are capable of achieving 0o phase shifts with
much lower group delays compared to traditional −2π TL phase shifters. This makes
them more suitable for broadband applications, in which it is required to minimize the
beam squinting with frequency variations. To this end, this chapter presents three novel
electronically tunable PRI/NRI metamaterial phase shifter designs, which are capable
of achieving both positive and negative phase shifts. To the author’s knowledge, this
represents the first published attempt to design tunable PRI/NRI metamaterial phase
shifters that have a phase response centered around the 0o , and at the same time have a
low return loss across their entire phase tuning range. The proposed PRI/NRI tunable
phase shifters shown in Figs.(4.1-b), (4.1-c), and (4.1-d), can be used in series-fed
phased arrays to steer the main beam about the broadside direction.
The TL PRI/NRI tunable phase shifter of Fig. 4.1-b is presented in section 4.2. It
uses the same architecture of the TL PRI/NRI phase shifter presented in [5]. However,
electronic tunability and matching are simultaneously achieved by replacing the fixed
1
This conclusion is reached assuming that the progressive inter-element phase shift is only generated
by the phase shifters, which neglects the phase contribution of the feed network. The effect of the
feed network phase response is discussed in more detail later in chapter 6 since it depends on the
array architecture.
4.1. INTRODUCTION
86
series capacitors with varactors and the fixed shunt inductors with the grounded TAIs
presented in chapter 3. Following this, a fully-integrated version of the PRI/NRI
tunable phase shifter, shown in Fig. 4.1-c, is presented in section 4.3. This design
replaces the TL sections with lumped L-C sections, which enables integrating the entire
phase shifter on a single MMIC resulting in a much more compact implementation.
The CMOS grounded TAI of chapter 3 is used to design the first three tunable phase
shifters; the high-pass design of Fig. 4.1-a, the TL PRI/NRI design of Fig. 4.1-b, and
the MMIC PRI/NRI design of Fig. 4.1-c. The capability to tune its inductance and
quality factor independently is a key feature to overcome the degradation of the phase
shifter’s insertion loss and return loss due to the variation of the TAI’s Q when the TAI
inductance is tuned. Furthermore, having control over the TAI’s Q without affecting
its inductance, allows controlling the phase shifter’s insertion loss. Moreover, the TAI
is capable of generating a negative series resistance, which can be used to partially
compensate the varactor losses while maintaining the bi-directionality of the phase
shifters as opposed to using amplifiers.
Another MMIC PRI/NRI tunable phase shifter design is presented in section 4.5.
However, this design is passive and does not use TAIs to tune the shunt inductance.
Alternatively, it uses a variable capacitor connected in parallel with a shunt spiral
inductor as shown in Fig. 4.1-d. Compared to the TAI-based design of Fig. 4.1-c, this
design does not consume any DC power and at the same time it eliminates the noise
and non-linearity contributions of the TAI circuit.
In summary, this chapter presents four different electronically tunable phase shifter
designs:
• The high-pass TAI-based phase shifter of Fig. 4.1-a [Section 4.2]
• The TL PRI/NRI TAI-based phase shifter of Fig. 4.1-b [Section 4.3]
• The MMIC PRI/NRI TAI-based phase shifter of Fig. 4.1-c [Section 4.4]
• The MMIC PRI/NRI passive phase shifter of Fig. 4.1-d [Section 4.5]
Throughout this chapter, we follow the same procedure for each phase shifter design, by
presenting its design equations, implementation, and its experimental characterization.
Following that, the advantages and disadvantages of the different phase shifter designs
are discussed and they are compared to previous designs published in the literature.
4.2. HIGH-PASS PHASE SHIFTER
87
C
C
L
Figure 4.2: High-pass phase shifter unit-cell.
4.2 High-pass Phase Shifter
This section presents the design of the tunable high-pass phase shifter. The phase
shifter achieves a wide phase tuning range and at the same time a low return loss
across its entire tuning range by combining the use of two tunable elements; varactors
and TAIs. Also, this section presents the experimental characterization of critical
performance limits of the TAI-based phase shifter, such as linearity, which is rarely
reported in other publications.
4.2.1 Analysis
Phase Response
If the high-pass phase shifter of Fig. 4.2 is terminated with a source and load impedance
of Zo , one can show that the forward transmission coefficient, S21 , can be expressed as:
S21 = µ
1
s+
CZo
¶µ
s3
1
Zo
+
s +s
2L 2CL
¶.
(4.1)
2
Eq.(4.1) shows the high-pass nature of the phase shifter, and at the same time it reveals
that the phase shifter has one real pole at ωp1 = 1/CZo and a pair of complex poles
√
at ωp2,3 = 1/ 2CL. The operating frequency of the phase shifter should be chosen
greater than the pole frequencies in order to avoid attenuating the input signal. Using
Eq.(4.1), one can show that the insertion phase, φ, is expressed as:
3π
− tan−1
φ=
2
µ
2ωCZo (1 − ω 2 LC)
1 − ω 2 C(2L + CZo2 )
¶
.
(4.2)
4.2. HIGH-PASS PHASE SHIFTER
88
At the same time, to match the impedance of the phase shifter to the source and load
impedances, Zo , one equates the input reflection coefficient, S11 , to zero:
S11 = µ
1 + s2 (2CL − Zo2 C 2 )
¶µ
¶ = 0.
1
1
Zo
2
+
s+
s +s
CZo
2L 2CL
(4.3)
This results in the following matching condition:
L=
1 + ω 2 C 2 Zo2
.
2ω 2 C
(4.4)
Since the phase shifter should be designed to operate at frequencies higher than its
pole frequency, 1/CZo , the matching condition of Eq.(4.4) can be approximated as:
CZo2
⇒ Zo =
L≈
2
r
2L
.
C
(4.5)
Using the result of Eq.(4.4), the phase shift expression can be simplified to:
√
2
.
φ≈ √
ω LC
(4.6)
Equation (4.6) indicates that the phase shifter provides a phase advance, i.e. a positive
phase shift. Furthermore, the insertion phase, φ, can be tuned by varying the values
of both the series capacitors, C, and the shunt inductor, L. If L and C are varied from
their nominal value to rL ×L and rC ×C, the phase tuning range can be expressed as:
µ
|∆φ| =
1
1− √
rL rC
¶
√
2
× √
.
ω LC
(4.7)
Figure 4.3 plots the phase tuning range given by Eq.(4.7). To generate this plot, a
nominal value of 3nH is chosen for L, also the operating frequency is arbitrarily chosen
as 2.4GHz, and the value of C is calculated using the matching condition of Eq.(4.5).
The figure plots the tuning range for two cases; the first one assumes we use fixed
inductors and variable capacitors, i.e. rL =1, and the second one assumes we use both
variable capacitors and inductors with rL = rC . As indicted by Fig. 4.3, tuning both
elements results in increasing the tuning range by 53%. Furthermore, tuning both
4.2. HIGH-PASS PHASE SHIFTER
89
50
Phase tuning range (deg)
↓
40
30
↑
53% increase
in tuning range
20
Tuning L and C → rL=rc
10
Tuning only C → r =1
L
0
1
1.5
2
2.5
3
Capacitor tuning ratio rc
3.5
4
Figure 4.3: Phase tuning range versus the capacitor tuning ratio rC .
elements allows one to maintain the matching condition of Eq.(4.5) across the entire
phase tuning range, by setting rL = rC . In contrast, designs using only one tunable
element are not capable of satisfying the matching condition across the entire tuning
range.
Loss Compensation
To investigate the effect of the series resistance, RS , associated with the shunt TAI,
on the phase shifter loss, one can derive the expression for the forward transmission
coefficient, S21 taking into account the effect of RS . Under the matching condition of
Eq.(4.5), S21 can be expressed as:
¶
µ
RS
s s+
L
¶µ
¶.
=µ
Zo + 2RS
1
1
2
s +
s+ 2 2
s+
CZo
CZo2
C Zo
2
S21
(4.8)
As previously mentioned the phase shifter has a pair of complex conjugate poles. However, Eq.(4.8) indicates that the quality factor associated with the complex conjugate
4.2. HIGH-PASS PHASE SHIFTER
C
90
C
gm1
TAI
Zin
Gyrator-C
-gm2
active inductor
Rf
C
Figure 4.4: Proposed high-pass phase shifter circuit implementation.
poles, ωp2,3 , is a function of RS , and is given by:
Qp2,3 =
Zo
.
Zo + 2RS
(4.9)
Hence, the value of RS determines the poles’ quality factor, i.e. it determines the
damping factor associated with the two poles. By generating a negative resistance, RS ,
through the TAI circuit, higher values of Qp2,3 can be achieved. This will increase the
peaking that occurs in the frequency response of S21 , which can be used to partially
compensate for the series capacitors’ losses. This will, in turn, minimize the phase
shifter insertion loss.
4.2.2 Design and Physical Implementation
The circuit diagram of the proposed high-pass phase shifter is shown in Fig. 4.4. It is
designed in the 1.5V, 0.13µm CMOS process. The variable capacitors are implemented
using 10×0.8µm×10µm on-chip hyper-abrupt junction varactors2 , whereas the tunable
inductor is implemented using the same grounded TAI circuit described in chapter 3.
The reverse bias voltage across the varactors sets their capacitance. The cathode
voltages, VB , is set through the input and output ports of the phase shifter via two
external bias-Tees. On the other hand, their anode voltages have a fixed value which is
set from within the TAI circuit and is approximately equal to VCM of the TAI circuit.
The varactors’ capacitance can be tuned from 0.8pF to 0.3pF by changing the reverse
2
Hyper-abrupt junction varactors have P-N junctions which are doped to optimize the range of
capacitance versus the reverse bias voltage.
4.2. HIGH-PASS PHASE SHIFTER
91
DC/Bias inputs
Phase
shifter
G
G
S
S
G
G
550 m
250 m
250 m
500 m
Figure 4.5: High-pass phase shifter die micrograph
bias voltage across them from 0V to 3V. Although the supply voltage for this process
is 1.5V, it offers varactors which can have reverse bias voltages up to 3V.
4.2.3 Experimental Characterization
Figure 4.5 shows the die micrograph of the fabricated phase shifter. The circuit occupies
250µm×250µm, out of which the TAI occupies 150µm×170µm. Two 150µm-pitch GSG
(ground-signal-ground) probes were used to characterize the phase shifter, while two
80µm-pitch multi-contact wedges with DC needles were used to provide the bias and
control voltages.
S-parameter Measurements
Figure 4.6 shows the measured insertion phase, φ, for different bias conditions. To tune
the phase shift φ, the series capacitance and the shunt inductance are varied using the
input and output port DC voltage, VB , and the TAI bias point (Vc1 , Vc2 , Vf ). VB is swept
from 0V to 3.6V, and for each bias voltage the appropriate inductance is generated by
the TAI circuit using Vc1 and Vc2 in order to satisfy the matching condition of Eq.(4.5).
4.2. HIGH-PASS PHASE SHIFTER
92
180
160
φ tuning range at
4GHz = 14o to 110.5o
Insertion phase φ (deg)
140
120
↓
100
80
V = 0V → 3.6V
B
60
40
20
↑
0
−20
3
3.5
4
Frequency (GHz)
4.5
5
Figure 4.6: Measured phase vs. freq., for different bias conditions
This will double the phase tuning range compared to tuning only the capacitance and
at the same time will ensure a low return loss across the entire tuning range. The phase
shift can be tuned from 14o to 110.5o at the design frequency, which for this design is
4GHz.
Figure 4.7 shows the measured input reflection coefficient, S11 , and the insertion
loss, S21 , for the same bias conditions used to generate the phase responses in Fig. 4.6.
Across the entire tuning range, the worst S11 at 4GHz is -18dB, and the phase shifter has
a bandwidth of 250MHz over which S11 <-10dB. Although the frequency independent
nature of the matching condition of Eq.(4.5) implies that the phase shifter will have
a wide bandwidth, the measurements indicate that the phase shifter has a relatively
narrow bandwidth. This is due to the self-resonance of the TAI, which according to
the measurements presented in chapter 3 resonates in the vicinity of the phase shifter
design frequency. For each of the bias points, used to generate the phase responses
of Fig. 4.6, the feedback voltage, Vf , of the TAI is selected to achieve an appropriate
negative resistance that partially compensates the varactor losses. As demonstrated
by Fig. 4.7, across the entire phase tuning range S21 varies from -1.3dB to -2.7dB at
4GHz. The tuning characteristics are presented in Fig. 4.8, which shows φ and S21 at
4GHz versus the varactor voltage, VB .
To demonstrate the effect of the negative resistance generated by the TAI on the
4.2. HIGH-PASS PHASE SHIFTER
93
↓
0
↑
−10
BW = 250MHz
←
→
−10
−20
−30
−20
Insertion loss S21 (dB)
Return loss S11 (dB)
0
S21 at 4GHz varies
from −1.3dB→ −2.7dB
−40
Worst case S11 at
4GHz = −18dB
−30
3.5
3.75
4
Frequency (GHz)
4.25
4.5
Figure 4.7: Measured S11 and S21 vs. freq., for different bias conditions
←
−1
80
−1.5
60
−2
40
→
−2.5
21
−0.5
Insertion loss at 4GHz S
Insertion phase at 4GHz φ (deg)
100
(dB)
0
20
0
0.5
1
1.5
2
2.5
Varactor reverse bias voltage VB (V)
3
3.5
−3
Figure 4.8: Measured phase and S21 at 4GHz vs. VB
4.2. HIGH-PASS PHASE SHIFTER
94
S21 dB
o
o
Vf V
Figure 4.9: Measured S21 at 4GHz versus the feedback voltage Vf
phase shifter loss, RS is varied by sweeping the feedback voltage, Vf , of the TAI, and
the measured S21 is plotted in Fig. 4.9. This shows that the insertion loss can be
enhanced by 2dB with less than 23o phase variation. This variation is due to the slight
dependence between the TAI L and RS , as well as the additional terms that appear in
Eq.(4.8) due to RS . The effect of Vf on S21 can be explained by the variation in the TAI
series resistance, i.e. Re(Zin,T AI ). Using the results of chapter 3, one can show that
the TAI series resistance Re(Zin,T AI ) = ωL/Q is directly proportional to the function
f (RS ), which was plotted in Fig. 3.2. Hence, as Vf increases, the feedback resistance
Rf decreases, resulting in an increase in the series resistance of the TAI equivalent
circuit, RS . This will lead to a decrease in Re(Zin ), until f (RS ) reaches its minimum
value. After that, Re(Zin ) will start to increase. This is the reason behind the decrease
of S21 in Fig. 4.9 after it reaches the maximum loss compensation point.
Linearity Measurements
To characterize the linearity of the high-pass phase shifter, the 1-dB compression point
for an input signal at 4GHz is measured. As shown by Fig(4.10), the high-pass phase
shifter achieves a 1-dB input compression point of -2.2dBm, which corresponds to an
input signal swing of 0.55Vpp , while operating from a 1.5V supply. The inter-modulation
4.2. HIGH-PASS PHASE SHIFTER
95
Output power at 4GHz (dBm)
20
10
0
−10
−20
−30
−40
−40
−30
−20
−10
0
Input power at 4GHz (dBm)
10
20
Figure 4.10: Amplitude of the output power versus the input power when applying a
single 4GHz RF signal source
Output power (dBm)
50
0
−50
−100
Output power at f1
Output power at 2f −f
1
−150
−40
−30
−20
−10
0
Input power (dBm)
10
2
20
Figure 4.11: Amplitude of the output power at f1 and 2f1 − f2 versus the input power
when combining two RF signal sources
4.3. TL PRI/NRI PHASE SHIFTER
96
Table 4.1: Summary of The High-Pass Phase Shifter Performance.
Parameter
Design frequency
Technology
Phase shift
Insertion loss
FOMa
Size
No. of unit-cells
S11
Bandwidthb
Fractional BW
Max. bias volt.
1-dB comp.
IIP3
Value
4GHz
0.13µm CMOS
14o ⇒110.5o =96.5o
1.3dB to 2.7dB
48.2o /dB
0.25mm×0.25mm
1
-18dB
0.25GHz
6.25%
3.6V
-2.2dBm
+7.4dBn
∆φ
|.
Figure of merit [85]: F OM = | min|S
21 |dB
b
Bandwidth measurement criterion: S11 < −10dB.
a
distortion components are also evaluated to fully characterize the linearity of the phase
shifter. Two signals the first at f1 =4GHz and the second at f2 = f1 -10MHz are
obtained from two RF signal generators and combined together using an RF signal
combiner. This frequency spacing is chosen to guarantee that the two input signals are
treated as in-band signals. The combined signal is then applied to the phase shifter, and
the inter-modulation products are measured at the output using a spectrum analyzer.
Figure 4.11 shows the output power at f1 and 2f1 − f2 versus the input power. The
phase shifter achieves an input third-order intercept point (IIP3) of +7.4dBm.
To summarize, the measured performance of the TAI-based high-pass shifter is presented in Table 4.1. The high-pass design achieves a figure of merit, FOM, of 48.2o /dB,
which is defined as the phase tuning range per dB of insertion loss [85].
4.3 TL PRI/NRI Phase Shifter
This section presents an electronically tunable TL PRI/NRI metamaterial phase shifter,
which is capable of achieving both positive and negative phase shifts. To the author’s
knowledge, this is considered the first published attempt to design an electronically
tunable TL PRI/NRI metamaterial phase shifter that has a phase response centered
4.3. TL PRI/NRI PHASE SHIFTER
C
97
TL
TL
L
d/2
C
d/2
Figure 4.12: TL PRI/NRI metamaterial phase shifter unit-cell.
around the 0o , and at the same time has a low return loss across its entire phase tuning
range. The proposed phase shifter uses the same architecture of the TL PRI/NRI phase
shifter presented in [5]. However, electronic tunability and matching are simultaneously
achieved by replacing the fixed series capacitors with varactors and the fixed shunt
inductor with a TAI.
4.3.1 Analysis
Figure 4.12 shows the unit-cell of the TL PRI/NRI phase shifter [5]. It is composed of a
p
regular microstrip TL, with a characteristic impedance Zo = Lo /Co , where Lo and Co
are the TL inductance and capacitance per unit-length, respectively. The microstrip TL
is loaded with two series capacitors, C, and a shunt inductor, L. Cascading the PRI TL
with the NRI section compensates the phase shift incurred by the propagating signal.
The phase shifter unit-cell is analyzed herein using periodic analysis for terminated
periodic structures. This technique can be applied to a finite number of unit-cells
when terminated with the corresponding Bloch impedance [24]. Using this technique
simplifies the analysis and offers good design insight. One can show that the insertion
phase, φ, of the unit-cell is given by [3, 5]:
µ
cos φ = cos 2θT L
1
1− 2
2ω CL
¶
µ
+ sin 2θT L
1
Zo
+
ωCZo 2ωL
¶
−
1
2ω 2 CL
,
(4.10)
where θT L is the phase lag due to one section of the PRI microstrip TL, given by
√
θT L = βT L d/2 = ω Lo Co d/2. By equating the phase shift, φ, to zero, one can find the
zero-phase frequencies of the periodic structure. The full analysis of the TL PRI/NRI
unit-cell can be found in [3, 5], therefore only the important results are pointed-out
here. In summary, this analysis reveals that the underlying periodic structure exhibits
4.3. TL PRI/NRI PHASE SHIFTER
98
√
a stop-band centered around the zero-phase frequency, ωo = 1/ LCo d, over which the
input signal is attenuated. In order to close this stop-band, the following condition has
to be satisfied:
r
r
Lo
2L
=
.
(4.11)
Zo =
Co
C
Interestingly, satisfying the stop-band closure condition of Eq.(4.11) insures that
the TL phase shifter is perfectly matched at the zero-phase frequency, ω = ωo . This
becomes evident by deriving the expression of the phase shifter reflection coefficient,
S11 . If a unit-cell of the TL phase shifter is terminated with an impedance Zo , one can
show that, at the zero-phase frequency, the reflection coefficient is expressed as:
2L Lo
−
C
Co
√
.
S11 (ω = ωo ) =
2L Lo
LLo
−
+ 2j √
C
Co
Co d
(4.12)
When the condition of Eq.(4.11) is satisfied, the two terms in the numerator of S11
cancel-out, which results in perfect matching at the zero-phase frequency. However,
when the component values (L and C) are varied to tune the phase shift, the location
√
of the zero-phase frequency, ωo = 1/ LCo d, changes. Hence the frequency at which
the phase shifter is matched changes. Nevertheless, the TL phase shifter still achieves
a low return loss across a wide range of frequencies as long as the stop-band closure
condition of Eq.(4.11) is satisfied. This is mainly due to the nature of the PRI TL
sections, which determines the characteristic impedance of the loaded TLs.
Under the stop-band closure condition, the phase shift can be approximated as:
√
2
− 2θT L .
φ≈ √
ω LC
(4.13)
Equation (4.13), which was originally derived in [5], indicates that positive and negative
phase shifts can be realized by a single unit-cell without having to go through a complete
phase rotation as in a traditional high-pass or low-pass architecture. Furthermore, the
phase can be tuned by simultaneously changing the values of both loading elements;
L and C. If L and C are varied from their nominal value to rL × L and rC × C, the
4.3. TL PRI/NRI PHASE SHIFTER
CVAR
99
TL
TL
CVAR
d/2
d/2
TAI
gm1
Zin
Packaged
TAI chip
Gyrator-C
active inductor
Rf
-gm2
C
Figure 4.13: TL PRI/NRI metamaterial phase shifter unit-cell.
phase tuning range can be expressed as:
µ
|∆φ| =
1
1− √
rL rC
¶
√
2
.
× √
ω LC
(4.14)
Similar to the high-pass phase shifter, varying both L and C results in increasing the
phase tuning range compared to varying C only. Furthermore, setting rL = rC will
maintain the matching condition of Eq.(4.11) and will result in a low return loss across
the entire phase tuning range.
4.3.2 Design and Physical Implementation
The TAI circuit described in chapter 3 is packaged using a 4mm×4mm high-speed QFN
(Quad Flat-Package No Lead) package to minimize the parasitics associated with the
package, and the packaged chip is used to implement the TL PRI/NRI phase shifter.
Figure 4.13 shows the unit-cell of the proposed tunable TL phase shifter. The series capacitors, C, are replaced by discrete varactors, where the reverse voltage across
the varactors controls their capacitance. The PRI TL sections are implemented using printed microstrip lines on a low-loss 10mil Rogers RT/duroid 5880 substrate. To
design the TL PRI/NRI metamaterial phase shifter both circuit and electromagnetic
simulations had to be carried out. This was necessary to choose the appropriate varactor capacitance tuning range and the properties of the printed TL structure. A detailed
explanation of the method used to simulate and consequently design the TL PRI/NRI
4.3. TL PRI/NRI PHASE SHIFTER
100
10.8mm
Varactors
RFout
RFin
10.4mm
DC bias/control lines
Active inductor
chip
Figure 4.14: Photograph of the tunable PRI/NRI phase shifter unit-cell.
metamaterial phase shifter is presented in Fig. B-1 in Appendix B.
A picture of the TL phase shifter is given in Fig. 4.14, the bias and control lines
going to the TAI chip are supplied from the lower side of the board, whereas the right
and left connectors are the input and output ports of the phase shifter, which also
supply the bias voltages to the series varactors. A low substrate permittivity, ²r , of 2.2
was chosen to reduce the phase shift incurred by the signal, hence making the phase
shifter more wide-band. The varactors used are 1.7mm×0.9mm plastic packaged silicon
hyper-abrupt junction varactor diodes from Skyworks, Irvine, CA (SMV1232). The
TL phase shifter unit-cell size is 10.8mm×10.4mm; the TL and series varactors occupy
10.8mm×1mm, while the chip and the bias lines roughly occupy 10.8mm×9.4mm.
The unit-cell width is mainly set by the MMIC inductor package, which can be easily
reduced by more than 22% by using a smaller package size (3mm×3mm). The smaller
package was not used here, since the chip contained other test circuits that needed to
be packaged.
4.3.3 Experimental Results
Figure 4.15 shows the measured and theoretical phase responses when both the TAI
inductance and varactor capacitance are varied. The theoretical response is predicted
using the exact phase expression of Eq.(4.10). The figure shows good agreement between the measurements and theory. Using the approximate expression of Eq.(4.13)
4.3. TL PRI/NRI PHASE SHIFTER
Measurements
Theory
100
Insertion phase φ (deg)
101
φ tuning range at
o
o
2.5GHz = −40 to +34
50
↓
Vvar = 0V → 4.2V
0
−50
−100
1.5
↑
2
2.5
Frequency (GHz)
3
3.5
Figure 4.15: The measured and theoretical phase responses vs. freq. for different bias
conditions. The phase expression of Eq.(4.10) is used for the comparison.
results in an error of less than 6.5o , hence Eq.(4.13) can still serve as a good starting
point for initial hand calculations, and at the same time, it gives good design insight.
The good agreement between the theoretical and experimental results is achieved by
extracting the values of the different circuit components using accurate simulations
(electromagnetic/circuit simulations). The component values obtained are then used
to predict the phase response based on the theoretical equations.
At the design frequency of 2.5GHz, the phase can be varied from -40o to +34o passing
through the zero-phase point. The phase shifter unit-cell is capable of achieving both
positive and negative phase shifts at the design frequency without going through an
entire 360o rotation, which requires an 88mm microstrip TL. This corresponds to a 73%
area saving compared to meandering the microstrip TL. Furthermore, over the entire
phase tuning range the matching condition is satisfied, and S11 is maintained below
-19dB at the design frequency, as shown in Fig. 4.16. As the varactors’ reverse bias
voltage, Vvar , increases, their capacitance decreases, and the TAI’s L has to decrease to
satisfy Eq.(4.11). When Vvar approaches 4.2V, the matching condition is increasingly
difficult to satisfy, since the package adds a fixed inductance to the TAI inductance,
thereby setting a minimum achievable L. Nevertheless, the phase shifter achieves a
bandwidth of 2.6GHz over which S11 is less than -10dB (see Fig. 4.16). The measured
S21 is presented in Fig. 4.17, the insertion loss is set by the varactor losses and the
4.3. TL PRI/NRI PHASE SHIFTER
102
Input reflection coefficient S11 (dB)
0
−5
−10
←
S < −10dB over a
11
bandwidth of 2.6GHz
→
−15
−20
−25
−30
→
−35
−40
1.5
2
2.5
3
Worst case S11 at
2.5GHz = −19dB
V = 3.9V & 4.2V
var
3.5
Frequency (GHz)
4
4.5
5
Figure 4.16: Measured S11 vs. freq. for different bias conditions.
5
↓
↑
Insertion loss S21 (dB)
0
−5
S21 at 2.5GHz varies
from −0.55dB → −1.1dB
−10
−15
−20
−25
−30
1
2
3
4
Frequency (GHz)
5
6
Figure 4.17: Measured S21 vs. freq. for different bias conditions.
4.4. MMIC PRI/NRI PHASE SHIFTER
103
Table 4.2: Summary of the TL PRI/NRI Phase Shifter Performance.
Parameter
Design frequency
Technology
Phase shift
Insertion loss
FOM
Size
No. of unit-cells
S11
Bandwidth
Fractional BW
Max. bias volt.
Av. power diss.
Av. Sim. NF
Value
2.5GHz
0.13µm CMOS/microstrip
-40o ⇒+34o =64o
0.5dB to 1.1dB
128o /dB
10.8mm×10.4mm
1
-19dB
2.6GHz
> 100%
4.2V
49.4mW@1.5V
7.6dB
TAI Q. The insertion loss at 2.5GHz varies from 0.55dB to 1.1dB over the entire
phase tuning range. Across the entire 2.6GHz bandwidth, the insertion loss varies
from 0.25dB to 4.6dB.
The TL phase shifter dissipates an average DC current of approximately 32.9mA from
a 1.5V supply which corresponds to 49.4mW across the entire phase tuning range. This
power is required to bias the TAI circuit in order to generate the required inductance.
The average noise figure of the TL phase shifter is predicted from simulations to change
from 6.1dB to 9.3dB at 2.5GHz across the phase tuning range with an average value of
7.6dB. From simulations, the main noise contributor to the phase shifter’s noise figure
is the TAI circuit. The performance of the TL PRI/NRI phase shifter is summarized
in Table 4.2.
4.4 MMIC PRI/NRI Phase Shifter
To reduce the size of the TL PRI/NRI phase shifter unit-cell, it is desirable to get rid
of the TL sections. The TL sections are important to compensate the phase incurred
by the signal due to the NRI loading elements. By replacing each TL with a lumpedelement L-C section and carefully selecting the values of the series inductance and
shunt capacitance, a similar phase response can be achieved while occupying a much
smaller area. This implementation will eliminate the need for bulky microstrip TLs
and will allow integrating the entire PRI/NRI phase shifter onto a single MMIC. To
4.4. MMIC PRI/NRI PHASE SHIFTER
C
104
Lo
Co
Co
Lo
L
Co
C
Co
Figure 4.18: Proposed IC PRI/NRI metamaterial phase shifter unit-cell.
the author’s knowledge, this work is considered the first published attempt to design a
fully-integrated tunable PRI/NRI phase shifter.
The proposed MMIC PRI/NRI phase shifter unit-cell is shown in Fig. 4.18. The
microstrip TL sections are replaced with a low-pass Π section Lo -Co . The resulting
lumped-element phase shifter can admittedly be thought of as a band-pass filter, created
by cascading low-pass and high-pass sections. However, here we are mainly interested in
its phase response, as opposed to conventional band-pass filters which are mainly used
for their magnitude response. Moreover, the corresponding structure should be thought
of as being a periodic one and having the unit-cell of Fig. 4.18. This is also unlike bandpass filters which typically are non-periodic. The architecture of the proposed lumpedelement PRI/NRI phase shifter is similar to that presented in [3] to model a TL, which
was loaded with discrete series capacitors and shunt inductors for the sake of analyzing
it. However, a complete Π section with two shunt capacitors and a series inductor
is used here to synthesize the TL sections. This creates two zeros in the reflection
coefficient transfer function, S11 , resulting in two frequencies at which the phase shifter
is perfectly matched. This extends the MMIC phase shifter bandwidth as opposed to
a lumped-element phase shifter based on the unit-cell presented in [3]. Furthermore,
this topology makes the phase shifter more suitable for implementation in IC form,
since the discrete components are replaced with on-chip components fabricated on a
silicon substrate. More specifically, the explanation lies with the implementation of the
series capacitors C, which will be replaced with MOS capacitors, as will be described
later in section 4.4.2. The series MOS capacitors are associated with large parasitic
gate and drain/source diffusion capacitance to the substrate. Therefore, these parasitic
capacitors can be naturally lumped with the shunt capacitor Co , and accounted for as
a contributor to the phase of the PRI section. Similarly, the effect of the parasitic
4.4. MMIC PRI/NRI PHASE SHIFTER
105
capacitance associated with the series inductors can also be lumped within the shunt
capacitors Co . This makes the proposed unit-cell in Fig. 4.18 well suited for the MMIC
phase shifter implementation.
4.4.1 Analysis
Using periodic analysis one can show that the phase shift of the MMIC PRI/NRI phase
shifter unit-cell is expressed as:
¶
µ
¶
Co
6Co Lo Lo Co
2
− ω Lo Co 4 +
+
+
cos φ = 2ω
1+
C
C
L
LC
¶
µ
1
4Co Lo 2Lo Co
+
+
− 2
.
+
1+
C
L
LC
ω LC
µ
4
L2o Co2
(4.15)
A simpler and more intuitive expression for the phase shift can be obtained by assuming
that the signal incurs a small phase shift φ, hence cos φ ≈ 1 − φ2 /2. This is used to
simplify Eq.(4.15) resulting in the following expression:
√
p
2 p
(1 − ω 2 Lo (C + Co )) × (1 − ω 2 Co (Lo + 4L) + 2ω 4 Co2 LLo ).
φ≈ √
ω LC
(4.16)
By equating the phase shift φ to zero, one can find the zero-phase frequencies:
s
1
, and
Lo (C + Co )
s
p
Lo + 4L ± L2o + 16L2
.
=
4Co LLo
ωo1 =
ωo2,3
(4.17)
Furthermore, Eq.(4.16) reveals that there is a range of frequencies over which the
phase is imaginary. This indicates that the underlying periodic structure exhibits a
stop-band, over which the input signal is attenuated. Figure 4.19 shows the dispersion
diagram of the periodic structure, where the component values are picked in such a way
to show the stop-band. In order to close the stop-band centered around the 0o mark,
the two zero-phase frequencies, ωo1 and the lower frequency of ωo2,3 should coincide,
i.e. ωo1 = ωo2 . This is similar to the method adopted in [3] for the TL-based structure.
4.4. MMIC PRI/NRI PHASE SHIFTER
106
5
L=3nH
C=2.4pF
Lo=1.7nH
C =0.18pF
o
4.5
Frequency (GHz)
4
pass−band
3.5
ω
o2
periodic structure
stop−band
3
2.5
2
pass−band
ω
o1
1.5
1
−150 −100
−50
0
50
Phase (deg)
100
150
Figure 4.19: Dispersion diagram of the periodic structure composed of the proposed
MMIC PRI/NRI phase shifter unit-cells.
This results in the following stop-band closure condition:
Lo (C + Co )
2L
Lo
2L
=
⇒
≈
.
C
Co (Co + 2C)
C
2Co
(4.18)
This approximation is based on the assumption that the shunt capacitor Co is smaller
than the series loading capacitor C, which will ensure that the cut-off frequency of the
low-pass section is higher than the cut-off frequency of the high-pass section. This stopband closure condition is similar to the condition obtained for the TL implementation
(Eq.(4.11)), since a TL section with a characteristic impedance Zo can be modeled by
p
two shunt capacitors, Co , and a series inductor, Lo , given that Zo = Lo /2Co .
If the stop-band closure condition of Eq.(4.18) is satisfied, then the phase shift per
unit-cell can be re-written as:
√
2
√
× (1 − ω 2 Lo (C + Co ))
(4.19)
φ ≈
ω LC
√
√ p
2
√
− 2 2ω Lo Co .
(4.20)
≈
ω LC
4.4. MMIC PRI/NRI PHASE SHIFTER
107
Similar to Eq.(4.13), the phase expression of Eq.(4.20) has two terms. The first term
results in a phase lead and is caused by the NRI section (high-pass), whereas the
second term results in a phase lag and is caused by the PRI section (low-pass). Hence,
similar to the TL phase shifter, a zero-degree phase shift can be realized by a single
unit-cell without having to go through a complete 360o phase rotation. Furthermore,
positive and negative phase shifts can be realized depending on which of the two terms
dominate. To center the phase shift around the zero-degree mark, the lumped-element
values should be chosen such that the phase contributions of the PRI and NRI sections
cancel out.
It is also important to investigate the return loss of the phase shifter unit-cell. When
a unit-cell of the MMIC phase shifter is terminated with an impedance Zo , one can
show that the reflection coefficient, S11 , at the zero-phase frequency is expressed as:
Lo (C + Co )
2L
−
C
Co (Co + 2C)
S11 (ω = ωo1 ) =
.
2L(C + Co )2
Lo (C + Co )
2L
+j 2
−
Co (Co + 2C)
C
C Co (Co + 2C)ωo1 Zo
(4.21)
Similar to Eq.(4.12), this indicates that by satisfying the stop-band closure condition
of Eq.(4.18), the MMIC phase shifter becomes perfectly matched at the zero-phase
frequency, ω = ωo1 . However, when the component values are varied to tune the
phase response, the location of the zero-phase frequency changes according to Eq.(4.17).
Hence the frequency at which the phase shifter is matched changes. Since it is desired
to achieve a wide bandwidth, it is important to investigate the phase shifter matching
at frequencies different from the zero-phase frequency. One can derive the matching
condition by equating S11 to zero at frequencies different from the zero-phase frequency
(ω 6= ωo1 ). This results in the following matching condition:
r
Zo ≈
(C(2L + Lo ) + Co (4L + Lo ))ω 2 − 1
.
ω2C 2
(4.22)
Equation (4.22) indicates that the proposed IC phase shifter has a second frequency
at which it is perfectly matched. This is a result of an additional zero in the reflection
coefficient transfer function. Using Eq.(4.22), one can show that this second frequency
4.4. MMIC PRI/NRI PHASE SHIFTER
108
where S11 dips is expressed as:
1
ωm = p
.
Lo (Co + 2C)
(4.23)
Having two frequencies at which S11 dips, ωo1 and ωm , helps extend the bandwidth
of the MMIC phase shifter compared to a lumped element phase shifter based on the
unit-cell of [3], where S11 dips only at the zero-phase frequency. Also, as indicated by
Eq.(4.20), the MMIC implementation allows varying the phase contribution of both
the PRI and NRI sections, as opposed to the TL implementation which only allows
varying the phase of the NRI section. In the MMIC implementation, the phase of the
NRI section is tuned via L and C, while that of the PRI section is tuned via Co . To
demonstrate this, L, C, and Co are varied from their nominal values to become rL × L,
rC × C, and rCo × Co respectively. This results in the following phase tuning range:
√
¶
µ
√ p
√
1
2
+ 2 2ω Lo Co × ( rCo − 1),
× 1− √
|∆φ| = √
rL rC
ω LC
(4.24)
where the tuning ratios rL , rC , and rCo should be chosen in order to satisfy the stopband closure condition of Eq.(4.18) as well as the matching condition of Eq.(4.22). By
comparing Eq.(4.14) and Eq.(4.24), one can see that the MMIC phase shifter has an extra term which further extends its phase tuning range compared to the TL phase shifter
while still satisfying the matching condition. Furthermore, integrating the phase shifter
on a single MMIC eliminates the parasitics associated with the individual component
packages, which in turn extends the tuning range even more.
4.4.2 Design and Physical Implementation
The schematic diagram of the MMIC PRI/NRI tunable phase shifter is shown in
Fig. 4.20. A 0.13µm CMOS process was chosen to fabricate the phase shifter since
the TAI has already been characterized in that process. The same TAI circuit described in chapter 3 is used to implement the phase shifter’s shunt inductor. The series
capacitors, C, are implemented using on-chip MOS varactors; each MOS varactor consists of an array of 16 by 15 small MOS varactors with an aspect ratio of 1µm/0.5µm,
and can be tuned from 0.38pF to 1.4pF via the gate to drain/source voltage. The gate
4.4. MMIC PRI/NRI PHASE SHIFTER
109
Figure 4.20: Proposed IC PRI/NRI metamaterial phase shifter unit-cell.
voltage of the MOS varactors is set by the DC voltage applied at the input and output
ports of the phase shifter, VDC . On the other hand, the drain/source voltage is generated by the TAI, and is approximately equal to VCM ≈ 0.6V. The Q of the series MOS
varactors has a strong impact on the phase shifter insertion loss, given that its effect
can be modeled as a series resistance in the signal path. To achieve the large capacitance value required to make the design frequency 2.6GHz, a larger series capacitance
is required. To this end, a fixed 0.67pF on-chip high-Q MIM (Metal-Insulator-Metal)
capacitor, CM IM , is connected in parallel with the MOS varactor to achieve the required capacitance without reducing S21 . The shunt capacitors of the PRI sections,
Co , are implemented using on-chip hyper-abrupt junction varactors, which provide a
wide tuning range. The varactors’ capacitance can be tuned from 90fF to 270fF by
changing the varactor cathode voltage, VB , from 3.8V to -0.1V. The varactor anodes
are biased by the voltage generated by the TAI. The series inductors of the PRI sections, Lo , are implemented using on-chip 1.7nH spiral inductors with 2.5 turns and an
outer diameter of 200µm. The spiral inductors have a low-Q at the design frequency,
which will contribute to the insertion loss of the phase shifter.
The die micrograph of the MMIC phase shifter is shown in Fig. 4.21, it occupies
an area of 550µm×1300µm, from which the core circuit without the pads occupies
380µm×960µm. To the author’s knowledge, this is the smallest tunable PRI/NRI
metamaterial phase shifter reported in the literature, that operates in this frequency
band. The TAI occupies 150µm×170µm from the overall area, and is located in the
4.4. MMIC PRI/NRI PHASE SHIFTER
110
G
G
S
S
G
G
TAI
550 m
380 m
960 m
Series spiral
inductors (Lo)
G
Series MIM
capacitors
(CMIM)
DC/bias inputs
1300 m
Figure 4.21: MMIC PRI/NRI metamaterial phase shifter die micrograph.
middle section of the layout. The spiral inductors to the left and right of the TAI are
the series inductors of the PRI sections, Lo . They occupy a larger area than the TAI,
and are surrounded by ground shields to minimize the coupling between them. The
series MIM capacitors, CM IM , occupy a very small area, and can be seen in the die
micrograph. On the other hand, the series MOS varactors and the shunt varactors are
not visible in the die micrograph because they are covered by the metal fill introduced
by the foundry to achieve certain layer densities. The bias and control voltages are
provided to the circuit from the bottom pads. Large on-chip de-coupling capacitors
are used to stabilize the bias and control voltages by providing a low-impedance path
to ground. The right and left pads correspond to the input and output ports of the
phase shifter, which also provide the bias voltage to the series MOS varactors.
4.4.3 Experimental Results
The MMIC phase shifter is characterized by probing the dies and measuring the Sparameters. Two GSG probes are used for the RF ports while a multi-contact wedge
with 8 DC needles is used to probe the DC pads. Figure 4.22 shows the measured and
theoretical phase responses for different bias conditions. The theoretical response is
predicted here using the approximate phase expression of Eq.(4.19), which results in
4.4. MMIC PRI/NRI PHASE SHIFTER
111
Measurements
Theory
Insertion phase φ (deg)
150
100
↓
50
VDC & VB are swept
from −0.3V→2.05V
& 3.8V→0V, resp.
0
−50
1.5
φ tuning range at
o
o↑
2.6GHz = −35 to +59
2
2.5
Frequency (GHz)
3
3.5
Figure 4.22: The measured and theoretical phase responses vs. freq. for different bias
conditions. The phase expression of Eq.(4.19) is used for the comparison.
good matching between the measurements and theory. Unlike the TL phase shifter, the
exact phase expression of Eq.(4.15) and the approximate phase expression of Eq.(4.19)
yield very accurate results. On the other hand, comparing the measured phase with
the approximate phase expression of Eq.(4.20) results in a 12.2o phase error; this is
mainly due to the approximations made in the derivation of Eq.(4.20) which utilizes
the approximate matching condition of Eq.(4.18). Still Eq.(4.20) can serve as a good
starting point for initial hand calculations, and at the same time, it gives good design
insight.
To tune the phase shift φ, the series loading capacitance, CM OS , the shunt inductance,
as well as the shunt capacitance, CV AR are varied using VDC , the TAI bias point (Vc1 ,
Vc2 , Vf ), and VB , respectively. The voltage VDC is swept from -0.3V to 2.05V and for
each value the appropriate inductance is generated using Vc1 and Vc2 to satisfy the
matching condition given by Eq.(4.18). In addition to that, VB is swept from 0.1V to
3.8V to extend the phase tuning range. The phase shift at 2.6GHz can be tuned from
-35o to +59o passing through the zero-phase mark, without the need for an entire 360o
rotation. This represents a 50% increase in the phase tuning range compared to the
TL phase shifter presented in the previous section. As explained in section 4.4.1, this
is due to the ability to control the shunt capacitance, CV AR . Furthermore, the MMIC
phase shifter eliminates the parasitics associated with the TAI package, which limited
4.4. MMIC PRI/NRI PHASE SHIFTER
112
Input reflection coefficient S11 (dB)
0
S < −10dB over a
11
bandwidth of 1.9GHz
−5
←
−10
→
−15
−20
−25
Worst case S at
11
2.6GHz = −19dB
−30
−35
1.5
2
2.5
3
3.5
Frequency (GHz)
4
4.5
Figure 4.23: Measured S11 vs. freq. for different bias conditions.
0
Insertion loss S21 (dB)
↓
↑
−5
S21(2.6GHz)=−3.8dB
for the case V =0V
B
& V =2.05V
DC
−10
−15
1
S21 at 2.6GHz varies
from −2.8dB→−3.8dB
1.5
2
2.5
3
Frequency (GHz)
3.5
4
4.5
Figure 4.24: Measured S21 vs. freq. for different bias conditions.
4.4. MMIC PRI/NRI PHASE SHIFTER
Maximum loss
compensation
|∆φ|≈7.4o
−3.3
−3.4
14
12
←
10
−3.5
→
−3.6
8
−3.7
6
−3.8
4
2
−3.9
Phase shift φ at 2.6GHz (deg)
Insertion loss S
21
at 2.6GHz (dB)
−3.2
113
o
−4
1
|∆φ|≈5.1
1.1
1.2
1.3
1.4
Feedback voltage V (V)
0
1.5
f
Figure 4.25: Measured S21 and phase shift φ at 2.6GHz versus the TAI feedback voltage
Vf .
the inductance tuning range in the TL phase shifter. Figure 4.23 shows the measured
input reflection coefficient S11 , for the same bias conditions used to sweep the phase.
The worst case S11 at the design frequency is -19dB. The phase shifter has a bandwidth
of 1.9GHz across which S11 is less than -10dB. The MMIC phase shifter has a smaller
bandwidth compared to the TL phase shifter, which is expected, and is mainly due to
the frequency dependent nature of the matching condition of Eq.(4.22).
Figure 4.24 shows the measured insertion loss S21 for the same bias points. As
indicated by the figure, S21 varies from -2.8dB to -3.8dB at the design frequency.
Across the entire phase shifter bandwidth, i.e. the 1.9GHz, the insertion loss varies
from 2.8dB to a worst case of 7.2dB. The phase shifter insertion loss is mainly due
to the losses associated with the spiral inductors and the series MOS varactors. It is
also important to note that, as the shunt capacitance increases, the cut-off frequency
of the PRI section decreases, which increases the phase shifter insertion loss. Hence,
as indicated by Fig. 4.24, the worst case S21 results when VDC and VB are set to 2.05V
and 0V respectively.
To demonstrate the effect of the negative resistance generated by the TAI circuit
on the phase shifter performance, the amount of negative resistance RS is varied by
4.5. PASSIVE MMIC PRI/NRI PHASE SHIFTER
114
Table 4.3: Summary of the TAI-Based MMIC PRI/NRI Phase Shifter Performance.
Parameter
Design frequency
Technology
Phase shift
Insertion loss
FOM
Size
No. of unit-cells
S11
Bandwidth
Fractional BW
Max. bias volt.
Av. power diss.
Av. Sim. NF
Value
2.6GHz
0.13µm CMOS
-35o ⇒+59o =96o
2.8dB to 3.8dB
34o /dB
0.38mm×0.96mm
1
-19dB
1.9GHz
73%
3.3V
31.5mW@1.5V
10.3dB
sweeping the feedback voltage, Vf , of the TAI, and the measured S21 is plotted in
Fig. 4.25. The plot shows that, at 2.6GHz, the phase shifter insertion loss can be
enhanced by 0.8dB with less than 7.4o phase variation, which corresponds to a change
of 7.8% of the phase tuning range.
The MMIC phase shifter dissipates an average DC current of 21mA from a 1.5V
supply which corresponds to 31.5mW across the entire phase tuning range. This power
is required to bias the TAI circuit in order to generate the required inductance. The
MMIC PRI/NRI phase shifter has a lower average DC power consumption compared to
the TL-based design, which consumes 49.4mW. The higher average power consumption
of the TL-based design is mainly due to the parasitic package inductance, which adds
a fixed series inductance to the TAI. Hence, in order to satisfy the matching condition,
lower inductance values are required by the TAI in the TL-based design, which in turn
requires higher bias currents for the TAI circuit. The noise figure of the MMIC phase
shifter is predicted from simulations to change from 8.4dB to 12.8dB at 2.6GHz across
the phase tuning range, with an average value of 10.3dB. Similar to the TL phase
shifter, the main noise contributor is the TAI circuit. The performance of the MMIC
PRI/NRI phase shifter is summarized in Table 4.3.
4.5. PASSIVE MMIC PRI/NRI PHASE SHIFTER
C
Co
Lo
Co
115
Lo
Cv
L
Co
C
Co
Figure 4.26: Unit cell of the proposed MMIC PRI/NRI tunable phase shifter.
4.5 Passive MMIC PRI/NRI Phase Shifter
This section presents another compact tunable MMIC PRI/NRI phase shifter. The
phase shifter is based on a similar L-C topology to that of the TAI-based MMIC
PRI/NRI phase shifter presented in the previous section. However, this design is
passive and does not use TAIs to tune the shunt inductance. Alternatively, it uses
a variable capacitor connected in parallel with a shunt spiral inductor as shown in
Fig. 4.26. The resulting topology still exhibits phase compensation properties which
allows it to center its phase response around the zero-degree mark while having a small
group delay. The series and shunt varactors are used to tune the phase and at the same
time maintain the matching, which allows the phase shifter to achieve a low return loss
across its entire phase tuning range. Compared to the TAI-based designs presented by
the previous sections, this design does not consume any DC power and at the same
time it eliminates the noise and non-linearity contributions of the TAI circuit.
4.5.1 Analysis
The passive MMIC PRI/NRI phase shifter consists of two lumped-element PRI sections
that replace the TLs in order to generate the low-pass response, which is required
to achieve the phase compensation. On the other hand, the high-pass response is
achieved via the series loading capacitors, C, and the shunt loading inductor, L. To
eliminate the active circuits used in the previous designs in order to tune the shunt
inductance L, a variable capacitor, Cv , is added in parallel with a shunt spiral inductor
to tune its effective inductance. The effect of adding this shunt capacitor on the phase
response, the tuning range, and the matching are explained in this section. Similar to
the previous designs, the passive MMIC PRI/NRI phase shifter unit-cell of Fig. 4.26
4.5. PASSIVE MMIC PRI/NRI PHASE SHIFTER
116
is analyzed using the periodic analysis [24]. One can show that the phase shift per
unit-cell is expressed as:
¶
Cv
Cv
Co
+
+
cos φ = 2ω
1+
C
2C 2Co
¶
µ
6Co Lo Lo Co Cv 2Cv
2
+
+
+
+
− ω Lo Co 4 +
C
L
LC
Co
Co
¶
µ
1
4Co Lo 2Lo Co Cv
+
+
+
− 2
.
+
1+
C
L
LC
C
ω LC
µ
4
L2o Co2
(4.25)
A simpler and more intuitive expression for the phase shift can be obtained, by assuming
that the signal incurs a small phase shift, φ, hence cos φ ≈ 1 − φ2 /2. This is used to
substitute in Eq.(4.25), resulting in the following expression:
√
2 p
√
1 − ω 2 Lo (C + Co )
φ ≈
ω LC
s
×
1−
ω 2 (Co (Lo
+ 4L) + Cv L) +
(4.26)
µ
2ω 4 Co LLo
¶
Cv
.
Co +
2
By equating the phase shift, φ, to zero, one can find the zero-phase frequencies:
1
, and
ωo1 = p
Lo (C + Co )
ωo2,3
q
p
LCv + 4LCo + Lo Co ± (LCv − Lo Co )2 + 8L2 Co (Cv + 2Co )
p
.
=
2LLo Co (2Co + Cv )
(4.27)
(4.28)
Furthermore, Eq.(4.26) reveals that there is a range of frequencies over which the
phase is imaginary. This indicates that the underlying periodic structure exhibits a
stop-band, over which the input signal is attenuated. Figure 4.27 shows the dispersion
diagram of the periodic structure, where the component values are picked in such a way
to show the stop-band. In order to close the stop-band centered around the 0o mark,
the two zero-phase frequencies, ωo1 and the lower frequency of ωo2,3 should coincide,
4.5. PASSIVE MMIC PRI/NRI PHASE SHIFTER
117
5
L=2.7nH
C=1.5pF
L =1.5nH
o
C =0.17pF
o
Cv=1.3pF
4.5
Frequency (GHz)
4
pass−band
ω
3.5
o2
periodic
structure
stop−band
3
2.5
2
pass−band
ω
o1
1.5
1
−150 −100
−50
0
50
Phase (deg)
100
150
Figure 4.27: Dispersion diagram of the periodic structure composed of the proposed
passive PRI/NRI MMIC unit-cells.
i.e. ωo1 = ωo2 . This results in the following stop-band closure condition:
Lo (C + Co )
2L
Lo
2L
=
⇒
≈
.
C
Co (Co + 2C) + Cv C/2
C
2Co + Cv /2
(4.29)
This approximation is based on the assumption that the shunt capacitor Co is smaller
than the series loading capacitor C, which will guarantee that the cut-off frequency of
the PRI (low-pass) section is higher than the cut-off frequency of the NRI (high-pass)
section. Based on the stop-band closure condition of Eq.(4.29), the phase shift per
unit-cell can be re-written as:
√
√ p
2
− 2ω Lo (4Co + Cv ).
(4.30)
φ≈ √
ω LC
The phase expression of Eq.(4.30) has two terms. The first term results in a phase lead
and is caused by the NRI section, while the second term results in a phase lag and is
caused by the PRI section, and the additional shunt capacitor, Cv . Hence similar to the
previous two designs, a 0o phase shift can be realized by a single unit-cell without having
to go through a complete 360o phase rotation. Furthermore, positive and negative phase
4.5. PASSIVE MMIC PRI/NRI PHASE SHIFTER
118
shifts can be realized depending on which of the two terms dominate. Hence to center
the phase shift around the 0o mark, the lumped component values should be chosen
such that the two terms in Eq.(4.30) cancel out.
It is also important to investigate the return loss of the phase shifter unit-cell. When
a unit-cell of the proposed passive MMIC PRI/NRI phase shifter is terminated with
an impedance Zo , one can show that the reflection coefficient, S11 , at the zero-phase
frequency, ωo1 , is expressed as:
Lo (C + Co )
2L
−
C
Co (Co + 2C) + CCv /2
S11 (ω = ωo1 ) =
.
4L(C + Co )2
Lo (C + Co )
2L
+j 2
−
Co (Co + 2C) + CCv /2
C
C (2Co (Co + 2C) + CCv )ωo1 Zo
(4.31)
This indicates that, by satisfying the stop-band closure condition of Eq.(4.29) the
MMIC phase shifter becomes perfectly matched at the zero-phase frequency. But
when the component values are varied to tune the phase shift, the location of the
zero-phase frequency changes. Since it is desired to achieve a wide bandwidth, it is
important to investigate the phase shifter matching at frequencies different from the
zero-phase frequency. One can derive the matching condition by equating S11 to zero
at frequencies different from the zero-phase frequency (ω 6= ωo1 ). This results in the
following matching condition:
r
Zo ≈
(C(2L + Lo ) + Co (4L + Lo ) + LCv )ω 2 − 1
.
ω2C 2
(4.32)
Similar to the TAI-based design, Eq.(4.32) indicates that the passive MMIC phase
shifter has a second frequency at which it is perfectly matched. This is a result of an
additional zero in the reflection coefficient transfer function. Using Eq.(4.32), one can
show that the second frequency where S11 dips is expressed as:
1
.
ωm = p
Lo (Co + 2C)
(4.33)
Re-analyzing the PRI/NRI phase shifter unit-cell without the shunt capacitor, Co , indicates that Co is the reason behind the additional zero that appears in the S11 transfer
4.5. PASSIVE MMIC PRI/NRI PHASE SHIFTER
119
CMIM
CMIM
Lo
Lo
CMOS
CMOS
L
Co
Co
Cv
Co
Co
VB1 VB2
Figure 4.28: Proposed passive MMIC PRI/NRI phase shifter circuit implementation.
function. Having two frequencies at which S11 dips, ωo1 and ωm , helps extending the
bandwidth of the MMIC phase shifter compared to a lumped-element phase shifter
based on the unit-cell of [3], where S11 dips only at the zero-phase frequency.
Similar to the TAI-based design, this phase shifter allows varying both terms of the
phase expression of Eq.(4.30). If C, Co , and Cv are varied from their nominal values
to become rC × C, rCo × Co , and rCv × Cv , respectively, this results in the following
phase tuning range:
√
¶
µ
³p
´
p
√ p
1
2
+ 2 2ω Lo ×
× 1− √
4Co rCo + Cv rCv − 4Co + Cv ,
|∆φ| = √
rC
ω LC
(4.34)
where the varactor tuning ratios rC , rCo , and rCv should be chosen in order to satisfy
the stop-band closure condition of Eq.(4.29), and the matching condition of Eq.(4.32).
The effect of varying Cv can be seen from the second term of Eq.(4.34), which helps
extend the phase tuning range of the phase shifter although it does not use any active
circuits to tune the shunt inductance. Furthermore, integrating the entire phase shifter
on a single MMIC eliminates the parasitics associated with the individual component
packages, which in turn increases its tuning range even more as opposed to TL-based
design.
4.5. PASSIVE MMIC PRI/NRI PHASE SHIFTER
120
4.5.2 Design and Physical Implementation
The schematic diagram of the passive fully-integrated PRI/NRI tunable phase shifter
is shown in Fig. 4.28. Since there is no need for any printed or off-chip components,
the phase shifter was implemented using a single MMIC. The series capacitors, C, are
implemented using on-chip MOS varactors, each MOS varactor consists of an array of
10 by 10 small MOS varactors with an aspect ratio of 2.3µm/0.5µm, and can be tuned
from 0.32pF to 1.26pF. The MOS capacitance, CM OS , is set via the gate voltage. The
gate voltage of the MOS capacitors is set by the DC voltage applied at the input and
output ports of the phase shifter, VDC . The Q of the MOS varactors has a strong
impact on the phase shifter insertion loss, given that its effect can be modeled as a
series resistance in the signal path. To achieve the large capacitance value required
to make the design frequency, fo , 2.6GHz, a larger series capacitor is required. To
this end, a fixed 0.96pF on-chip high-Q MIM capacitor, CM IM , is connected in parallel
to achieve the required capacitance without reducing S21 . The shunt capacitors of
the PRI sections, Co , are implemented using on-chip hyper-abrupt junction varactors,
which provide a wide tuning range. The varactor capacitance can be tuned from 250fF
to 80fF by changing the varactor cathode voltage, VB1 , from 0V to 3.3V. The series
inductors of the PRI sections, Lo , are implemented using on-chip 1.6nH spiral inductors
with 3.25 turns and an outer diameter of 200µm. However, the spiral inductors have
a low-Q at the design frequency, which will have a direct effect on the phase shifter
insertion loss. The shunt inductor, L, is implemented using a 1.1nH spiral inductor with
2.5 turns and an outer diameter of 240µm, while the shunt varactor, Cv , is implemented
using a hyper-abrupt junction varactor. The varactor capacitance Cv is controlled via
its cathode voltage, VB2 , and can be tuned from 0.54pF to 1.6pF.
The passive MMIC PRI/NRI phase shifter was fabricated in a standard 0.13µm
CMOS process, and the die micrograph is shown in Fig. 4.29. The phase shifter occupies an area of 700µm × 1300µm. This is a very small area for a tunable PRI/NRI
metamaterial phase shifter operating in this frequency band. The spiral inductor located in the middle section of the layout in Fig. 4.29 is the shunt inductor, L. Whereas,
the two spiral inductors to the left and right are the series inductors, Lo , of the PRI
sections. Each inductor is surrounded by a ground shield to minimize the coupling. The
bias and control voltages are provided to the circuit from the bottom pads. Whereas,
4.5. PASSIVE MMIC PRI/NRI PHASE SHIFTER
Shunt spiral
inductor (L)
121
Series spiral
inductors (Lo)
G
G
S
S
G
G
700 m
380 m
1100 m
G
Series MIM
capacitors
(CMIM)
DC/bias inputs
1300 m
Figure 4.29: Phase MMIC PRI/NRI shifter die micrograph
the right and left pads correspond to the input and output ports of the phase shifter,
which also provide the bias voltage to the series MOS varactors.
4.5.3 Experimental Results
The passive MMIC PRI/NRI phase shifter was characterized by probing the dies and
measuring the S-parameters. Figure 4.30 shows the measured insertion phase, φ, for
different bias conditions. To tune φ, the series capacitor C, the shunt capacitors Co ,
and Cv are varied using the input/output port DC voltage, VDC , and the bias voltages
VB1 and VB2 , respectively. VB1 and VB2 are swept from 0V to 3.3V, and for each bias
condition the necessary series capacitance, CM OS is set through the bias voltage VDC in
order to satisfy the matching condition of Eq.(4.32). This will guarantee a low return
loss across the entire phase tuning range. The phase passes through the 0o mark at the
design frequency, 2.6GHz, and is tunable from -25.5o to +27o , which corresponds to a
51.5o per stage. Figure 4.31 shows both the measured input reflection coefficient S11
and the measured insertion loss, S21 , for the same bias conditions used to sweep the
4.5. PASSIVE MMIC PRI/NRI PHASE SHIFTER
122
120
100
φ tuning range at
2.6GHz = −25.5o to 27o
Insertion phase φ (deg)
80
60
V
40
20
&V
are swept
B1,2
from −0.6V→1.5V
and 3.3V→0V
DC
↓
0
−20
↑
−40
−60
−80
−100
1.5
2
2.5
Frequency (GHz)
3
3.5
Figure 4.30: Measured phase vs. freq., for different bias conditions
S21 at 2.6GHz varies
from −4.9dB→ −5.1dB
Insertion & Reflection loss (dB)
0
↓
↑
−5
−10
BW=2GHz
←
→
−15
−20
−25
Worst case S11 at
2.6GHz = −21dB
−30
−35
1
1.5
2
2.5
3
3.5
Frequency (GHz)
4
4.5
5
Figure 4.31: Measured S11 and S21 vs. freq., for different bias conditions
4.5. PASSIVE MMIC PRI/NRI PHASE SHIFTER
123
30
−4.8
10
→
0
−5
−10
−5.2
←
−20
Insertion loss at 2.6GHz S21 (dB)
Insertion phase at 2.6GHz φ (deg)
−4.6
20
−5.4
−30
0
0.5
1
1.5
2
2.5
Varactor reverse bias voltage VB1 (V)
3
Figure 4.32: Measured phase and S21 at 2.6GHz vs. the varactor reverse bias voltage
VB1
phase. The worst case S11 at the design frequency is -21dB, and the phase shifter has
a very wide bandwidth of 2GHz, across which S11 is less than -10dB. This corresponds
to a fractional bandwidth of more than 76%. The wide bandwidth achieved is due to
the additional zero in the S11 transfer function, described in section 4.5.1. In practice,
the losses associated with the structure combines the two S11 dips into one wider dip,
resulting in a wide bandwidth. The insertion loss, S21 , varies from -4.9dB to -5.1dB at
the design frequency. The relatively large insertion loss is mainly due to the series MOS
varactors’ low-Q, as well as the losses associated with the spiral inductors. It is worth
mentioning that, using this topology to design phase shifters at higher frequencies will
require smaller capacitors and inductors, which can be realized on-chip with higher Q
values, hence resulting in lower insertion loss.
The tuning characteristics of the phase shifter are presented in Fig. 4.32, where the
measured phase and insertion loss at 2.6GHz are plotted versus the shunt varactor
reverse bias voltage, VB1 . The phase shifter has a very small insertion loss variation
of 0.2dB across the entire tuning range. Table 4.4 summarizes the performance of the
passive MMIC PRI/NRI phase shifter.
4.6. DISCUSSION AND COMPARISON
124
Table 4.4: Summary of the Passive MMIC PRI/NRI Phase Shifter Performance.
Parameter
Design frequency
Technology
Phase shift
Insertion loss
FOM
Size
No. of unit-cells
S11
Bandwidth
Fractional BW
Max. bias volt.
Av. power diss.
Av. NFa
a
Value
2.6GHz
0.13µm CMOS
-25.5o ⇒+27o =51.5o
4.9dB to 5.1dB
10.5o /dB
0.7mm×1.3mm
1
-21dB
2GHz
76%
3.3V
0
4.9dB to 5.1dB
The noise figure is roughly estimated from the phase shifter insertion loss.
4.6 Discussion and Comparison
Using the PRI/NRI phase shifter topology of [5] to build electronically tunable phase
shifters (i.e. the TL and the MMIC PRI/NRI phase shifters) has allowed building
compact, low group delay phase shifters with phase responses centered around the
zero-degree mark. As explained in section 2.5.1, compactness is an important feature
for beam steering networks, especially for series-fed arrays, in order to avoid capturing
grating lobes in the radiation pattern as the beam is scanned. Moreover, centering the
phase response around the zero-degree mark is desirable for series-fed antenna arrays in
order to allow scanning the main beam around the broadside direction. In addition, the
proposed phase shifter design approach maintains their bi-directionality, thus allowing
the same antenna array to operate as a transmitter and as a receiver. The low group
delay property of PRI/NRI phase shifters is described in detail in section 4.6.1, and its
importance for the design of series-fed antenna arrays will be demonstrated in chapter
6.
Using TAIs to design the TL and the MMIC PRI/NRI phase shifters resulted in a
wide phase tuning range and at the same time maintained the matching of the phase
shifters as opposed to other implementations published in the literature which use
a single tuning element [27, 56, 57], or use two tunable elements but in the form of
4.6. DISCUSSION AND COMPARISON
125
Table 4.5: Comparison Between Different Phase Shifter Designs Presented In This
Chapter.
Parameter
Technology
Phase shift
Broadside rad.
Insertion loss
Size
Bandwidth
Av. power diss.
IIP3
Noise figure
High-pass
Integrated
+
X
Average
Very small
Small
Average
Average
High
TL PRI/NRI
Printed
±
√
MMIC PRI/NRI
Integrated
±
√
Passive PRI/NRI
Integrated
±
√
Low
Large
Large
High
Average
Average
Average
Small
Large
Average
Average
High
High
Small
Large
0
High
Low
series and shunt varactors only [59]. On the other hand, as mentioned in chapter 3,
the TAI achieves a +2.16dBm 1-dB input compression point, which corresponds to
approximately a 0.8Vpp voltage swing while operating from a 1.5V supply voltage, and
a +12.5dBm IIP3. Consequently, using TAIs imposes limitations on the phase shifter’s
linearity, especially since it operates from a low-voltage supply of 1.5V. This will be
critical when an antenna array using these phase shifters operates in the transmit
mode. As an example, the TAI-based high-pass phase shifter presented in section 4.2
achieves a -2.2dBm 1-dB input compression point, and a +7.4dBm IIP3. Although
the proposed TAI-based phase shifters achieve a significantly higher 1-dB compression
point compared to other TAI-based phase shifters in the literature [86], their limited
power handling capability precludes their use in base stations. However, they can find
applications in short-range wireless applications requiring low transmit power levels
such as wireless sensor networks (WSN) and RF applications using ZigBee. Also,
designing the PRI/NRI phase shifters utilizing TAIs results in higher noise figures
compared to passive designs: 7.6dB and 10.3dB for the TL and MMIC phase shifters,
respectively. Nevertheless, in a practical application, the noise figure of the phase
shifter can be enhanced by preceding the phase shifter with a low noise amplifier when
operating within a receiver [23].
The passive PRI/NRI phase shifter tries to address some of the drawbacks of the
active designs by eliminating the TAI and using instead a shunt varactor. The resulting topology still exhibits phase compensation properties, which allows us to center its
phase response around the zero-degree mark while having a small group delay. Furthermore, it is also capable of maintaining the phase shifter matching. The passive
4.6. DISCUSSION AND COMPARISON
126
PRI/NRI design does not consume any DC power and at the same time it eliminates
the noise and non-linearity contributions of the TAI, which will potentially result in
a lower noise figure and a higher IIP3, respectively. This, however, comes at the expense of a slightly lower phase tuning range, and a higher insertion loss. Table 4.5
qualitatively compares between the different phase shifter designs presented in this
chapter.
The phase shifters presented here are prototypes fabricated to prove the concept and
to experimentally characterize them. When using these phase shifters within a practical
system, a look-up table together with multiple DACs (Digital-to-Analog Converters)
can be implemented to set the different bias voltages according to a single control
input. All of the biasing circuitry can be easily integrated on the same die with the
TAI for the case of the TL phase shifter or on the same die with the MMIC phase
shifters. This is one of the main advantages of using a standard CMOS technology to
implement the phase shifters as opposed to using other high ft technologies such as
GaAs. Furthermore, this should not result in a significant increase in the die sizes, since
removing the DC/bias pads would result in some area saving. Moreover, generating
the bias voltages on-chip will reduce the number of pins required from the TAI IC
package for the case of the TL phase shifter and from the IC package of the MMIC
phase shifter, making it possible to move to a smaller package size for both designs.
This will allow us to further shrink the dimensions of both designs.
-19dB
-19dB
S11
1.9GHz
73%
3.3V
31.5mW@1.5V
8.4dB⇒12.8dB
2.6GHz
>100%
4.2V
49.4mW@1.5V
6.1dB⇒9.3dB
Max. bias volt.
Av. power diss.
Simulated NF
1
Phase shift, insertion loss, and size are reported per unit-cell.
Bandwidth
Fractional BW
3
1
1
No. of unit-cells
o
0.38mm×0.96mm
34 /dB
o
2.8dB to 3.8dB
-35 ⇒+59 =96
o
10.8mm×10.4mm
128 /dB
o
0.5dB to 1.1dB
-40 ⇒+34 =64
o
Size1
FOM
2
Insertion loss1
Phase shift
o
Fully-integrated
o
& microstrip
o
0.13µm CMOS
Technology
1
2.6GHz
0.13µm CMOS
2.5GHz
Design frequency
IC phase shifter
TL phase shifter
Specification
–
0
15V
30%
>5GHz
-12dB
4
1.8mm×0.96mm
13 /dB
o
1dB to 1.3dB
12.5
o
& CPW
Ferroelectric varactors
17GHz
[59]
–
0
26V
30%
1.9GHz
-9dB
6.5
20mm×5mm
60 /dB
o
0.25dB to 0.5dB
32
o
& microstrip
Varactors
6.5GHz
[85]
–
0
20V
22%
2.2GHz
-12dB
9
2.6mm×0.5mm
30o /dB
0.8dB to 1dB
28o
& CPW
Ferroelectric varactors
10GHz
[87]
Table 4.6: Comparison Between Different PRI/NRI Phase Shifter Implementations
4.6. DISCUSSION AND COMPARISON
127
4.6. DISCUSSION AND COMPARISON
128
Table 4.6 presents a detailed comparison between the TAI-based TL and MMIC
PRI/NRI phase shifters along with related PRI/NRI phase shifters reported in the
literature. Note that, although the phase shifters presented in [59, 85, 87] utilize the
PRI/NRI structure, they do not achieve a phase centered around the zero-degree mark
at their design frequencies. Tuning the inductance in both the proposed TL and MMIC
phase shifters results in a very wide phase tuning range compared to the other implementations. To this end, the TL phase shifter achieves the highest figure of merit
(FOM=128o /dB). In contrast, the MMIC phase shifter has the largest phase tuning
range, but it achieves a figure of merit of only 34o /dB. This is attributed to the higher
losses of the MMIC phase shifter due to the low Q of the on-chip series spiral inductors
and MOS varactors. In spite of this, the MMIC phase shifter implementation occupies
a very small area compared to the other implementations, and has the potential of integration with RF and digital circuitry in a standard low-voltage and low-cost CMOS
process. Furthermore, the fractional bandwidth of both the TL and MMIC phase
shifters is much wider than those of other implementations reported in the literature.
This is mainly due to the ability to tune the shunt inductance, which allows one to
maintain the matching condition across the entire phase tuning range. Moreover, the
designs in [59, 85, 87] require very high control voltages; 15V up to 26V, which makes
them less suitable for hand-held applications.
4.6.1 Group Delay of PRI/NRI Phase Shifters
As previously described in chapter 2, a low group delay is necessary to minimize the
beam squinting with frequency variations in series-fed antenna arrays. In [5], it was
demonstrated that printed PRI/NRI phase shifters using fixed discrete components
achieve low group delays compared to traditional -360o TLs. In this section, we demonstrate the same, but for the electronically tunable PRI/NRI phase shifters. As an example, this is demonstrated here for the passive MMIC PRI/NRI phase shifter presented
in section 4.5.
The group delay of the passive MMIC PRI/NRI phase shifter, Tgd , can be obtained
using Eq.(4.30), which results in the following expression:
Tgd
√
√ p
2
dφ
+ 2 Lo (4Co + Cv ).
= √
=−
dω
ω 2 LC
(4.35)
4.6. DISCUSSION AND COMPARISON
129
1
0.8
0.3
→
0.6
0.25
←
0.4
0.2
0.2
All−pass filter group delay (nsec)
Phase shifter group delay (nsec)
0.35
0.15
1.5
2
2.5
3
Frequency (GHz)
3.5
0
4
Figure 4.33: The measured group delays of the metamaterial phase shifter and the
simulated group delay of two cascaded 2nd -order all-pass filters achieving
a -360o at 2.6GHz
Note that, the individual phase contributions of the PRI and NRI sections in Eq.(4.30)
do not need to be large to achieve the phase compensation. In fact, they can be small
in magnitude, and to achieve the phase compensation they only need to be equal.
Consequently, looking closely at Eq.(4.35), where the same two terms add up, one can
see that this architecture results in smaller group delays compared to using other types
of phase shifters which require a complete -360o or +360o phase rotation.
Since, all-pass filters are well suited to design phase shifters, we will use the group
delay of an all-pass filter as the reference for the comparison. Using the all-pass phase
shifter described in chapter 2 to achieve a -360o phase shift requires us to cascade two
of the 2nd -order constant-resistance stages. The resonance frequency of the all-pass
filter, ωr , is chosen as 2.6GHz, and the filter quality factor, Q, is chosen as 2 to result
in equal inductances. This results in the following group delay expression:
Tgd =
2Qωr (ω 2 + ωr2 )
.
Q2 (ω 2 − ωr2 )2 + ω 2 ωr2
(4.36)
The group delay of the all-pass filter obtained from Eq.(4.36) is plotted in Fig. 4.33
with the measured group delays of the passive MMIC PRI/NRI phase shifter for all
the different bias conditions. As indicated by Fig. 4.33, the PRI/NRI phase shifter is
4.6. DISCUSSION AND COMPARISON
130
capable of achieving the 0o phase with a 76% reduction in the group delay compared to
the reference all-pass phase shifter design. Furthermore, the PRI/NRI phase shifter’s
group delay varies by 63% over the entire 2GHz bandwidth compared to a variation
of 85% for the all-pass phase shifter design. It is also worth mentioning that, the
group delays of the passive MMIC PRI/NRI phase shifter plotted in Fig. 4.33 remain
relatively constant for the different bias conditions. This takes place because the phase
is tuned by varying the contribution of the NRI and PRI sections of Eq.(4.30) in an
opposite manner, which results in a very small variation in the group delay given by
Eq.(4.35). These results are not only specific to the passive MMIC PRI/NRI phase
shifter. In fact, it can be shown that the active TL and MMIC PRI/NRI phase shifters
also achieve low and relatively fixed group delays. As explained in section 2.5.4, the
low group delay property of PRI/NRI phase shifters is important to minimize the beam
squinting in series-fed antenna arrays. This will be described in more detail in chapter
6.
CHAPTER
5
A Highly-Reconfigurable Directional
Coupler
D
uplexers are necessary building blocks for transceiver front-ends, since they allow
sharing the same antenna between the transmitter and the receiver, as shown
in Fig. 1.2. Duplexers are usually designed using printed or discrete components.
Consequently, they are bulky and do not provide any tunability. Also, for a transceiver
to support multi-standard operation, it is necessary to employ an electronically tunable
duplexer, capable of operating at different frequencies. In this chapter, the design of
a highly-reconfigurable CMOS MMIC directional coupler is presented. The proposed
directional coupler has the capability to operate with a tunable coupling coefficient, and
at the same time to operate at a tunable center frequency. Also, the proposed coupler
has the capability to switch the input power among its different ports. This makes it
suitable for replacing the bulky passive duplexers in transceiver front-ends. Also, as
explained in chapter 1, replacing the 3-port duplexer with 4-port highly-reconfigurable
directional coupler enables one to monitor the transmitted and received power. Thus,
allowing for precise control over the level of the TX power and the gain of the low-noise
amplifier.
131
5.1. INTRODUCTION
132
Through port
(2)
(1)
Isolated port
(4)
Coupled port
(3)
(a) Forward
Isolated port
(2)
(1)
Through port
(4)
Coupled port
(3)
(b) Backward
Figure 5.1: Block diagram of a 4-port directional coupler configured in: (a) the forward
mode of operation, and (b) the backward mode of operation.
5.1 Introduction
The most popular method used to design directional couplers is using printed TL
structures. However, the TL implementations impose limitations on the area occupied
by the couplers, especially for systems operating within the low GHz frequency range.
This has hindered the integration of the couplers to produce single MMIC solutions
for such systems. Hence, various methods have been presented in the literature to
design lumped-element directional couplers [60]. Furthermore, the recent demand for
reconfigurable circuits capable of operating within multi-standard systems has created
a need for couplers capable of operating within different frequency bands [86, 88–92],
as well as capable of providing configurable coupling levels [93–95].
As a 4-port device, the directional coupler has the potential to simultaneously realize
multiple functions:
1. Tuning the coupling coefficient
2. Tuning the operating frequency
3. Switching from forward to backward operation, as illustrated by the block diagram of Fig. 5.1, where the coupler is capable of switching the power between the
through port (P2) and the isolated port (P4) while perfectly isolating the other.
To date, existing reconfigurable couplers individually realize only one of the above
features [86, 88–95]. Furthermore, to the author’s knowledge, none of the MMIC directional couplers reported in the literature has demonstrated the capability of electronically switching between backward and forward operation. This feature could prove
to be very useful for diversity systems, in which it is desired to electronically switch
between different sub-systems (for example: antenna diversity systems). Also, it can be
5.1. INTRODUCTION
133
used within transceivers to connect the TX and RX ports to the antenna (duplexing).
This will be explored in more detail later on in this chapter.
5.1.1 Tunable Coupling Coefficient Directional Couplers
Directional couplers with electronically tunable coupling coefficients are presented in
[93–95]. In [93] and [94], varactors are used to control the coupling between two printed
TLs. The design in [93] achieves a large tuning range of 4.1dB to 19dB for the coupling
coefficient, from the input port to the coupled port, over a wide bandwidth. Also,
the design in [94] achieves a 6dB to 10dB coupling coefficient tuning range. However,
in both designs the discrete varactors require a large reverse bias voltage; 25V for the
former and 10V for the latter. The design in [95] proposes to use switches to control the
coupling coefficient between two coupled TLs, resulting in coupling coefficients of 8dB
to 16dB. Nevertheless, the switches are not actually implemented and they are replaced
by hardwired connections (ideal short/open). Furthermore, both designs utilize printed
TL structures, hence they occupy a large area compared to a lumped-element approach.
To the author’s knowledge, lumped-element couplers with tunable coupling coefficients
have never been published yet in the literature.
5.1.2 Tunable Operating Frequency Directional Couplers
Directional couplers with electronically tunable operating frequencies have also been
presented in the literature [86,88–92]. In one of the most recently published papers [88],
varactors are used to terminate the open-circuited TL stubs of a dual-band TL coupler,
which was originally presented in [96]. Hence, the reverse bias voltage across the
varactors controls the operating frequency, within a limited range, around each of the
coupler bands by changing the effective electrical length of the stubs. Although the
reverse bias voltage across the discrete varactors goes up to 30V, this technique results
in a limited frequency tuning range of 0.62GHz to 0.9GHz and 1.63GHz to 1.8GHz for
the lower and upper frequency bands respectively. Furthermore, the coupler isolation
level is limited to 20dB and the design occupies a large area of approximately 6cm×6cm.
Other printed TL coupler designs have also been published in the literature [89–91]
that utilize varactors in different ways to tune the coupler operating frequency. But
all of them occupy a large area compared to lumped-element couplers and they require
5.2. THEORETICAL ANALYSIS
134
large reverse bias voltages for the discrete varactors. Furthermore, they do not achieve
a wide frequency tuning range: 1.3GHz to 1.7GHz and 1.7GHz to 2.17GHz for the
designs in [89, 90] and [91] respectively.
Very few electronically tunable lumped-element directional coupler designs have been
published. The coupler published in [92] utilizes discrete varactors with chip inductors
to reduce the footprint of the coupler by 80% compared to the printed coupler of [91].
Nevertheless, using only tunable capacitors results in a limited frequency tuning range
(1.7GHz to 2.17GHz). To the author’s knowledge, the coupler published in [86] is the
first fully-integrated MMIC coupler achieving a tunable center frequency. The MMIC
coupler in [86] is based on the high-pass Tee L-C coupler topology of Fig. 2.19, and uses
TAIs with fixed on-chip Metal-Insulator-Metal (MIM) capacitors to achieve a tunable
operating frequency. However, it can only operate with a fixed coupling coefficient and
still does not offer the switching capability described in Fig. 5.1.
In this chapter, a highly-reconfigurable compact CMOS MMIC directional coupler
is presented. The MMIC directional coupler utilizes lumped-element varactors and
TAIs to allow electronic tuning of both the coupling coefficient as well as the coupler’s
operating frequency. To the author’s knowledge, this is the first coupler that combines
both functions. Furthermore, combining the use of varactors and TAIs results in a very
wide frequency tuning range while maintaining good isolation. Moreover, the MMIC
directional coupler can be electronically reconfigured to operate as a forward or as a
backward coupler, i.e. it is capable of switching the power from the through port to the
isolated port, see Fig. 5.1. The design equations of the MMIC directional coupler are
presented in section 5.2. Section 5.3 describes the MMIC directional coupler circuit
implementation. The experimental results are presented in section 5.4. Finally, the
noise performance of the MMIC coupler is evaluated in section 5.5.
5.2 Theoretical Analysis
5.2.1 Analysis of the MMIC Directional Coupler
The proposed MMIC lumped-element directional coupler uses the high-pass architecture shown in Fig. 5.2. Each branch of the coupler consists of a lumped element L-C
section that provides the necessary 90o phase shift at the design frequency. The high-
5.2. THEORETICAL ANALYSIS
135
L
L
C1
(1)
(2)
C2
C2
C1
(4)
(3)
L
L
Figure 5.2: The high-pass topology used by the proposed MMIC directional coupler.
L
+1/2
C1
L
Te
e
Zo
Te
C1
+1/2
e
L
L
Zo
Figure 5.3: The equivalent circuit with even-mode excitation.
pass L-C topology requires grounded inductors as opposed to a traditional low-pass
topology which requires floating inductors [92]. This allows the use of the TAIs in
place of the spiral inductors. Furthermore, the high-pass Π topology is chosen to minimize the number of inductors, and hence the area occupied by the MMIC coupler. At
the same time, this topology reduces the number of series capacitors in the signal path,
which in turn, reduces the MMIC coupler insertion loss.
To analyze the operation of the proposed MMIC directional coupler, the lumpedelement L-C high-pass coupler is analyzed using the even-odd mode technique, originally presented in [97]. The effect of an input signal applied at any of the ports (port
1 in this case) while terminating the rest of the ports with an impedance Zo , is eval-
5.2. THEORETICAL ANALYSIS
L
+1/2
o
136
L
C1
2C2
To
Zo
2C2
V2
V1
2-port
Network
I1
2C2
2C2
C1
-1/2
I2
To
Odd mode circuit
o
L
L
Zo
Figure 5.4: The equivalent circuit with odd-mode excitation.
uated by decomposing the original coupler of Fig. 5.2 into two circuits: an even-mode
circuit shown in Fig. 5.3, and an odd-mode circuit shown in Fig. 5.4, where Te,o and
Γe,o are the transmission and reflection coefficients of the even- and odd-mode circuits,
respectively. The transmission coefficients S21 , S31 , S41 and the reflection coefficient S11
of the MMIC coupler can be obtained by properly superimposing the responses of the
even- and odd-mode circuits [97].
In standard 2-port network theory, the ABCD matrix is defined as:
" # "
#" #
V1
A B V2
=
,
I1
C D I2
(5.1)
where V1,2 and I1,2 are the voltage and current, respectively, at ports 1 and 2 of the
odd-mode circuit shown in Fig. 5.4. Performing circuit analysis, one can show that the
ABCD matrix of the odd-mode circuit is expressed as:








2β2 −
1+
β1µ
¶
µ
1
−
2j 2β2 −
XL

1
XL
1
2β2 −
XL
jβ1
¶2



,
1 

2β2 −
XL 
1+
β1
1
jβ1
(5.2)
5.2. THEORETICAL ANALYSIS
137
where β1 , β2 , and XL are the susceptances of the series capacitors C1 , C2 and the reactance of the shunt inductors L respectively. Using the standard relationship between
the scattering parameters and the ABCD matrix of a 2-port network [24], one can
evaluate the transmission and reflection coefficients of the odd-mode circuit, To and
Γo , which are expressed as:
2
To =
2
2+
β1

µ
µ
¶

1
1
2

2β2 −
+
−
+ jZo 4β2 −
XL
jβ1 Zo
XL

1
2β2 −
XL
β1
¶2  ,
(5.3)




and
µ
¶2 
1
2β2 −

1
2
XL 


−
− jZo 4β2 −

jβ1 Zo
XL
β1




Γo =
2
2+
β1
µ
1
2β2 −
XL
¶
µ

1
2

+
−
+ jZo 4β2 −
jβ1 Zo
XL

1
2β2 −
XL
β1
¶2  .
(5.4)




Similarly by analyzing the even-mode circuit, one can show that the transmission and
reflection coefficients of the even-mode circuit, Te and Γe , are expressed as:
and
¶
2
¶,
(5.5)
¶
µ
1
j
2
+ jZo
−
−
β 1 Zo
XL β1 XL2
¶
¶.
µ
µ
Γe =
j
1
1
2
−
− jZo
−
2 1−
XL β1
β 1 Zo
XL β1 XL2
(5.6)
Te =
µ
1
2 1−
XL β1
j
−
− jZo
β 1 Zo
µ
1
2
−
XL β1 XL2
To fully characterize the lumped-element directional coupler, the S-parameters are
evaluated by superimposing Te,o and Γe,o , in Eq.(5.3) through Eq.(5.6), according to
5.2. THEORETICAL ANALYSIS
138
[24]. To guarantee a low reflection coefficient, S11 , the following equation has to be
satisfied:
Γo Γe
+
= 0.
(5.7)
2
2
Furthermore, to guarantee high isolation, the following equation has to be satisfied:
S11 =
S41 =
Γe Γo
−
= 0.
2
2
(5.8)
Solving Eq.(5.7) and Eq.(5.8) results in the following two conditions:
β12 =
1
1
+ β22 ⇒ ωo2 C12 = 2 + ωo2 C22 , and
2
Zo
Zo
XL =
1
1
⇒ ωo L =
,
β1 + β2
ωo C1 + ωo C2
(5.9)
(5.10)
where ωo is the design frequency. Moreover, at the design frequency the transmission
coefficients of the through and coupled ports, S21 and S31 respectively, are given by:
s
s
S21 (ω = ωo ) = j
1−
β22
β12
S31 (ω = ωo ) =
=j
1−
C22
, and
C12
−C2
−β2
=
.
β1
C1
(5.11)
(5.12)
Hence, the output signals at the coupled and the through ports, P3 and P2 respectively,
have a 90o phase difference at the design frequency. At the same time, the magnitude
of the signals delivered to both ports is determined by the ratio of the series capacitors
C1 and C2 .
5.2.2 MMIC Directional Coupler Modes of Operation
Tunable Coupling Coefficient
As indicated by Eq.(5.12), the coupling coefficient C of the MMIC directional coupler
can be tuned, and at the design frequency, is expressed as:
C(ω = ωo ) = −20 log |S31 | = −20 log
C2
.
C1
(5.13)
5.2. THEORETICAL ANALYSIS
139
1.8
2
←
1.8
1.4
1.6
1.2
1.4
1
Inductance L (nH)
Capacitance C2 (pF)
1.6
1.2
0.8
→
1
0.6
1.3
1.5
1.7
1.9
Capacitance C1 (pF)
2.1
2.3
Figure 5.5: Series capacitance C2 and the shunt inductance L required to satisfy the
conditions of Eq.(5.9) and Eq.(5.10) versus the series capacitance C1 .
9
Coupling coefficient C (dB)
8
7
6
5
4
3
2
1
1.4
1.6
1.8
Capacitance C1 (pF)
2
2.2
Figure 5.6: Coupling coefficients achieved by the MMIC coupler circuit when the
lumped-element components are chosen to satisfy both the matching and
the isolation conditions.
5.2. THEORETICAL ANALYSIS
140
For example, in order to implement a 3dB coupler, the capacitance C1 has to be chosen
√
equal to 2 × C2 . Furthermore, if the series capacitors are replaced by varactors, the
coupling coefficient can be electronically tuned by changing the bias voltages applied
across the varactors. In order to achieve a low return loss and a very high isolation while
tuning the coupling coefficient, both conditions expressed by Eq.(5.9) and Eq.(5.10)
must be satisfied across the entire coupling coefficient tuning range. Equation (5.9)
reveals that, if C1 is increased to tune the coupling coefficient, the value of C2 must
also increase for the MMIC directional coupler to operate at the same frequency. At
the same time, the value of the shunt inductor L has to decrease according to the
condition of Eq.(5.10). Figure 5.5 shows the values of C2 and L resulting from the
theoretical expressions of Eq.(5.9) and Eq.(5.10) respectively when C1 is swept to tune
the coupling coefficient. This plot is generated assuming a nominal design frequency
of 2.6GHz and a 50Ω termination impedance (Zo ). Although the coupling coefficient
depends on the ratio of the two series capacitances, the nonlinear relationship between
C1 and C2 in Eq.(5.9) is enough to result in an 8.5dB tuning range for the coupling
coefficient. This is demonstrated by Fig. 5.6 which plots the theoretical expression of
the coupling coefficient given by Eq.(5.13) versus the value of C1 . For each point the
value of C2 , calculated from Eq.(5.9), is used to calculate the coupling coefficient.
We have so far shown that, the coupling coefficient of the MMIC directional coupler
can be electronically controlled while maintaining a low return loss and a very high
isolation across the entire tuning range. However, to achieve full electronic tunability
for the coupling coefficient, electronically tunable inductors are required. Thus, the
lumped-element approach used to implement the coupler proves to be a valid choice,
since this enables the integration of the coupler with the active circuits necessary to
synthesize the TAIs on the same chip.
Further circuit analysis can be performed on the lumped-element coupler to show
that the power delivered to the coupled port (P3), and hence the coupling coefficient
are, in general, a function of frequency. Moreover, the power delivered to the coupled
5.2. THEORETICAL ANALYSIS
141
port is expressed as:
S31 (ω) =
¶
µ µ 2
¶
ω
− 1 − jωL
Zo
ωo2
¶
µ µ 2
¶
2ω
− 1 − jωL
(ωL − jZo ) Zo
ωo2
1
×
2
(Zo (2C1 Lω − 1) − jωL) (Zo (2C2 Lω 2 − 1) − jωL)
4C1 C2 Zo2 L3 ω 5
(5.14)
Equation (5.14) indicates the high-pass nature of the lumped element coupler. Furthermore, evaluating S31 at the design frequency ωo results in the simple expression of
Eq.(5.13) as long as the two conditions of Eq.(5.9) and Eq.(5.10) are satisfied.
Tunable Frequency of Operation
The frequency of operation of the lumped-element coupler is defined as the frequency
at which high isolation and low return loss are achieved, while realizing the desired
coupling coefficient. This can simply be obtained by re-writing Eq.(5.10), which results
in the following expression for the coupler operating frequency:
ωo = p
1
L(C1 + C2 )
.
(5.15)
The coupler operating frequency, ωo , given by Eq.(5.15) is a function of the shunt
inductance L and the series capacitances C1 and C2 . However, to achieve low return
loss and high isolation the condition of Eq.(5.9) must also be satisfied, which can rewritten as:
L
(5.16)
C1 = 2 + C2 .
Zo
As confirmation, further circuit analysis showed the frequency dependent nature of
5.2. THEORETICAL ANALYSIS
142
3
3.2
→
←
2.6
2.8
2.2
2.4
1.8
2
1.4
1.6
0.8
Capacitance C1 (pF)
Operating frequency fo (GHz)
3.6
1.2
1.6
Inductance L (nH)
2
2.4
Figure 5.7: Operating frequency of the MMIC coupler and the series capacitance C1
versus the shunt inductance L. The series capacitance C1 is chosen to
satisfy both the matching and the isolation conditions, while C2 is chosen
to achieve an arbitrary coupling coefficient of 3dB.
the isolation of the lumped element coupler, which could be expressed as:
S41 (ω) =
jLZo ω 3 (ω 2 − ωo2 ) (ωo2 L2 − Zo2 )
(ω 2 ωo2 L2 + Zo2 (ω 2 − ωo2 ) − jωo2 Zo Lω) (ωωo2 L + jZo (2ω 2 − ωo2 ))
×
(ωωo L + jZo (ω − ωo )) (ωωo L − jZo (ω + ωo ))
(ω 2 ωo2 L2 − Zo2 (ω 2 − ωo2 ) + jωo2 Zo Lω) (ωL − jZo )
(5.17)
This result is derived under the assumption that the conditions of Eq.(5.9) and Eq.(5.10)
are satisfied. Equation (5.17) confirms the existence of a zero in the transfer function
of S41 at ω = ωo , which results in perfect isolation at the operating frequency.
To tune the operating frequency ωo of the coupler, the shunt inductance L is varied
and for each inductance value, the series capacitance C1 is calculated from Eq.(5.16).
This is necessary in order to guarantee a low return loss as well as high isolation across
the entire frequency tuning range. The resulting operating frequencies based on the
theoretical expression of Eq.(5.15) are plotted in Fig. 5.7 together with the values of
5.2. THEORETICAL ANALYSIS
143
the shunt capacitance C1 versus the value of the shunt inductance L. To generate this
plot the value of the shunt capacitance C2 is chosen according to Eq.(5.13) in order
to achieve an arbitrary coupling coefficient of 3dB. Also, the termination impedance is
set to 50Ω. Figure 5.7 indicates that changing the operating frequency from 3.6GHz to
1.6GHz (a 77% tuning range) requires tuning the inductance by a factor of 2.2, and at
the same time it requires tuning the capacitance C1 , and consequently C2 , by a factor
of 2.2.
It is also possible to achieve a tunable frequency of operation for this MMIC coupler
by using a fixed shunt inductance and varying both series capacitances C1 and C2 .
This will eliminate the need for TAIs if the coupler is only intended to have a tunable
operating frequency and not a tunable coupling coefficient as described earlier. However, this will drastically reduce the frequency tuning range. To demonstrate this, one
can show that the frequency tuning range achieved by tuning the shunt inductance L
as well as the series capacitance C1 while fixing C2 is expressed as:
¯
¯
¯
¯
¯ ∆L ¯
¯ ∆ωo ¯
2C
1
¯
¯
¯
¯
¯ ωo ¯ = C1 + C2 × ¯ L ¯ .
(5.18)
On the other hand, if the shunt inductance is fixed and both series capacitors C1 and C2
are varied to tune the operating frequency, and at the same time, satisfy the condition
of Eq.(5.16), the frequency tuning range decreases to:
¯
¯
¯
¯
¯ ∆C1 ¯
¯ ∆ωo ¯
C
1
¯
¯
¯
¯
¯ ωo ¯ = C1 + C2 × ¯ C1 ¯ .
(5.19)
Hence, for the same component tuning range, combining the use of varactors and TAIs
extends the frequency tuning range by 50% compared to a design that uses series
varactors and fixed shunt inductors. The wider tuning range makes the proposed
lumped-element directional coupler utilizing varactors and TAIs attractive for multistandard applications where the coupler would be required to operate over a wide range
of frequencies.
5.3. CIRCUIT IMPLEMENTATION
144
Power switching
Another interesting feature of this lumped-element MMIC coupler is its ability to be
electronically reconfigured to operate as either a forward or a backward coupler, as
described in the introduction. One can argue by symmetry that interchanging the two
series capacitors C1 and C2 would result in interchanging the isolated and through
ports of the MMIC directional coupler. Thus, implementing the series capacitors C1
and C2 using varactors allows switching from forward to backward operation by simply
switching the bias voltage applied across the varactors.
This section has summarized the three different modes of operation of the proposed
MMIC directional coupler. The next sections describe the design details of the MMIC
directional coupler circuit as well as its experimental characterization.
5.3 Circuit Implementation
5.3.1 MMIC Directional Coupler Design
The schematic diagram of the proposed highly-reconfigurable CMOS directional coupler is shown in Fig. 5.8. Since there is no need for any printed or off-chip components,
the entire directional coupler has been implemented on a single MMIC. The series capacitors C1 and C2 are implemented using on-chip MOS varactors, each MOS varactor
consists of an array of 5 by 18 small MOS varactors with an aspect ratio of 2µm/0.5µm,
and can be tuned from 0.25pF to 1pF. The Q of the varactors has a strong impact on
the coupler’s insertion loss, given that its effect can be modeled as a series resistance
in the signal path. To achieve the large capacitance value required to make the design frequency, fo , 2.6GHz, a larger series capacitance is required. To this end, a
fixed 0.95pF on-chip high-Q MIM capacitor, CM IM 2 , is connected in parallel. This
will slightly reduce the series capacitance tuning range, but it is necessary in order to
achieve a low insertion loss for the coupler. The series MOS capacitance, CM OS , is set
via the gate to drain/source voltage. The gate voltage of the series MOS capacitors in
the top and bottom branches of the coupler are set by the DC voltage Vr1 through a
10kΩ bias resistor R as shown in Fig. 5.8. Furthermore, the capacitance of the right
and left branches is set through the bias voltage Vr2 . The drain/source voltage of all
the series MOS capacitors is set by the TAI circuit. To isolate the gate voltage of the
5.3. CIRCUIT IMPLEMENTATION
145
Vr1
CMIM2
R
TAI
CMIM1
TAI
(1)
(2)
CMOS
CMIM2
Vr2
R
CMIM1
CMIM2
CMOS
CMOS
R
CMOS
CMIM1
(4)
(3)
CMIM1
TAI
R
CMIM2
TAI
gm1
Zin
Vr1
Tunable Active
Inductor
-gm2
C
Figure 5.8: Proposed lumped-element MMIC directional coupler circuit implementation.
5.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS
146
series MOS capacitors from the DC voltage generated by the TAI circuit, an additional
DC-blocking MIM capacitor CM IM 1 is added in series. Since CM IM 1 has a fixed value
and is connected in series with the effective tunable capacitor (the parallel combination
of CM OS and CM IM 2 ), it reduces the tuning range of the overall series branch capacitance. To avoid the reduction in the tuning range, CM IM 1 should be significantly
larger than CM OS + CM IM 2 . However, CM IM 1 can not take an arbitrarily large value
since its parasitic capacitance to the substrate increases as well. This decreases its selfresonance frequency and losses, which potentially increases the coupler losses. Since
CM OS + CM IM 2 can vary from 1.2pF to 1.95pF, 10pF was found to be a good design
choice for CM IM 1 , which was also verified using simulations.
5.4 Physical Implementation and Experimental Results
5.4.1 Physical Implementation
The MMIC directional coupler was fabricated in a standard 0.13µm CMOS process.
The die micrograph is shown in Fig. 5.9, the dimensions of the fabricated chip are
1540µm×900µm, which includes the MMIC coupler as well as some test structures
and the biasing/RF pads. The MMIC directional coupler occupies 730µm×600µm
without the bias/RF pads. Arguably this is a very small area for a highly-reconfigurable
directional coupler operating in this frequency band.
Some test structures are fabricated beside the MMIC coupler circuit to help in characterizing the TAI as well as the varactors. It is worth mentioning that, adding these
test structures together with their RF probing pads has resulted in some asymmetry in
the MMIC directional coupler layout, making the interconnecting wires from the RF
pads to two ports of the MMIC coupler (P3 and P4) longer than those of the two other
ports (P1 and P2) as shown in Fig. 5.9. The effect of this asymmetry on the MMIC
coupler performance will be discussed in the following section.
As indicated by Fig. 5.9, the majority of the area of the MMIC coupler is occupied by
the TAI circuits, which occupy 150µm×170µm, followed by the series MIM capacitors
CM IM 1 . On the other hand, the series varactors CM OS and the MIM capacitors CM IM 2
occupy a very small area. The MOS varactors are not visible in the layout because
of the metal fill required by the foundry to maintain certain layer densities. The bias
5.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS
147
1540 m
DC/bias inputs
Test TAI
Directional coupler circuit
G
P4
G
S
S
G
G
S
S
G
G
P1
900 m
P3
G
P2
G
Test varactor
DC/bias inputs
VDD
730 m
Shunt
TAI
P4
P1
600 m
Series
capacitors
CMIM2 &
CMOS
P3
P2
Series MIM capacitor CMIM1
VDD
Figure 5.9: MMIC directional coupler die micrograph. The top figure shows the entire fabricated chip and the bottom figure shows a close-up on the MMIC
directional coupler circuit.
5.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS
148
and control voltages are provided to the circuit from the top and bottom pads. The
rightmost and leftmost pads correspond to the four ports of the MMIC directional
coupler as indicated by Fig. 5.9. To distribute the bias and control voltages to the
different TAI circuits (VDD , Vcm , Vc1 , Vc2 ) as well as the varactors reverse bias voltages
(Vr1 , Vr2 ), the directional coupler circuit is surrounded by several bias distribution rings.
Each bias voltage is tapped off its ring whenever a connection is required to one of the
circuit components. This helps reduce the voltage drop across the bias lines, which
reduces mismatches between the responses of the different TAI circuits. Furthermore,
this facilitates the layout and routing process.
5.4.2 Experimental Characterization of the MMIC
Directional Coupler
The MMIC directional coupler was characterized by probing the dies and measuring the
corresponding 4-port S-parameters using a 4-port network analyzer. A pair of 150µmpitch differential GSGSG probes were used to probe the 4-ports of the MMIC coupler.
Two multi-contact wedges, each with 8 probe needles at 150µm-pitch, were used to
supply the bias and control voltages to the circuits. A CS-2 differential calibration
substrate from GGB Inc. is used to perform a 4-port calibration to de-embed the
frequency response of the RF probes, connectors, and cables. The different operating
modes of the MMIC directional coupler, which were described in section 5.2.2, have
been experimentally characterized and are summarized here.
Tunable coupling coefficient
The MMIC directional coupler was configured to operate at the nominal design frequency of 2.6GHz, and the value of the series MOS capacitor C1 was varied using the
bias voltage Vr1 to tune the coupling coefficient of the MMIC coupler. To keep the
return losses low and the isolation of the coupler very high, the second series MOS
capacitor C2 is tuned via Vr2 and the shunt inductance is tuned via Vc1 and Vc2 according to the conditions of Eq.(5.9) and Eq.(5.10) respectively. The resulting coupling
coefficient C and the isolation of the MMIC coupler for different biasing conditions are
plotted versus frequency in Fig. 5.10 and Fig. 5.11 respectively. Figure 5.10 also com-
5.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS
Coupling coefficient C (dB)
10
8
149
Measured
Theory
C tunable from 1.42dB
to 7.14dB at 2.6GHz
↓
6
4
2
↑
0
2.3
2.4
2.5
C /C
2 1
decreasing
2.6
2.7
2.8
Frequency (GHz)
2.9
3
Figure 5.10: Measured and theoretical coupling coefficients C vs. freq. for different bias
conditions.
0
Isolation S
41
(dB)
−10
−10dB bandwidth = 0.45GHz
←
→
−20
Worst case isolation
at 2.6GHz is 41dB
−30
−40
−50
2.2
2.4
2.6
Frequency (GHz)
2.8
3
Figure 5.11: Measured isolation S41 vs. freq. for the same bias conditions as Fig. 5.10.
5.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS
150
0
Return loss S11 (dB)
−5
−10
−15
−20
−25
−30
−35
2.3
2.4
2.5
2.6
2.7
Frequency (GHz)
2.8
2.9
3
Figure 5.12: Measured reflection coefficient S11 vs. freq. for the same bias conditions
as Fig. 5.10.
pares the measured and theoretical coupling coefficients, which are predicted using the
expression of Eq.(5.14). The figure shows good agreement between the measurements
and theory. Using the exact expression of Eq.(5.14) is necessary for the comparison
in order to predict the frequency response of the coupling coefficient since the simple
expression of Eq.(5.13) is only valid at the design frequency.
The measurements in Fig. 5.10 and Fig. 5.11 show that the coupling coefficient of
the MMIC coupler can be electronically tuned from 1.4dB to 7.1dB at 2.6GHz, while
maintaining the isolation of the MMIC coupler higher than 41dB across the entire
coupling coefficient tuning range. This coupling coefficient tuning range corresponds to
directing 72% to 19% of the input power at port 1 to the coupled port (P3), respectively.
Furthermore, across this tuning range, the return loss is maintained below -16.5dB, as
indicated by Fig. 5.12. There is an exception to this, which takes place when the MMIC
coupler is configured to operate with a coupling coefficient of -1.42dB which results in
a S11 of -12.6dB.
The MMIC directional coupler draws an average DC current of approximately 139mA
from a 1.5V supply which corresponds to dissipating 208mW across the entire coupling
coefficient tuning range. This power is required to bias the TAI circuits in order to
5.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS
151
generate the required inductance. A more detailed discussion about power consumption
is presented towards the end of section 5.4.2.
-17dB
-16⇒-35.4dB
10V
0
-14⇒-19dB
-22⇒-45dB
25V
0
12mm×12mm
Return loss (S11 )
Isolation (S41 )
Max bias voltage
Power dissipation
Size
45mm×50mm
–
–
-15dB
-15dB
Discrete
8⇒16dB
b
b
at 5.2GHz
Switches are not implemented, they are replaced by fixed short/open connections.
Different coupling coefficients are obtained from different prototypes.
c
Size estimation is based on λ/4 × λ/4 for an ²r of 2.2.
a
Continuous
Continuous
Tuning
14.8mm×2.2mm
6⇒10dB
4.1⇒19dB
Coupling coeff. (C)
c
at 2GHz
at 4.5GHz
730µm×600µm
208mW@1.5V
2V
-41⇒-51dB
-12.6⇒-32dB
Continuous
1.4⇒7.1dB
2.1⇒3.1GHz
Tunable
Fixed
Fixed
Center frequency
Fixed
0.13µm CMOS
This work
Printed/Varactors Printed/Varactors Printed/Switchesa
[95]
Technology
[94]
[93]
Specification
Table 5.1: Comparison Between the Proposed MMIC Directional Coupler and Other Variable Coupling
Coefficient Couplers
5.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS
152
5.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS
0
153
Measured
Theory
−5
Isolation S41 (dB)
−10
−15
−20
−25
−30
−35
−40
−45
−50
2
2.2
2.4
2.6
2.8
Frequency (GHz)
3
3.2
Figure 5.13: Measured and theoretical S41 vs. freq., for different bias conditions
Table 5.1 summarizes the performance of the proposed MMIC directional coupler
with other tunable coupling coefficient couplers presented in the literature [93–95].
The proposed coupler provides a smaller coupling coefficient tuning range compared
to [93]. Also, using the lumped-element approach to design the proposed coupler results
in a smaller bandwidth compared to the printed designs in [93] and [94]. Nevertheless,
using the lumped-element approach to design the coupler results in a very compact
implementation. This enables fabricating the coupler in a standard CMOS process
allowing its integration with other RF/digital circuits on the same chip. Furthermore,
the integrated MOS varactors used in this design, require a much lower bias voltage
compared to the discrete varactors used in [93] and [94]. Moreover, the proposed MMIC
coupler achieves very high isolation levels compared to other designs.
Tunable Frequency of Operation
As explained in section 5.2.2, the proposed directional coupler is capable of operating
at different center frequencies. This is achieved by changing the value of the shunt
inductance via Vc1 and Vc2 and simultaneously changing the series MOS capacitance
C1 via Vr1 in order to satisfy the condition of Eq.(5.16). This will guarantee a low
5.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS
154
0
−5
Return loss S11 (dB)
−10
−15
−20
−25
−30
−35
−40
−45
1.5
2
2.5
Frequency (GHz)
3
3.5
Figure 5.14: Measured S11 vs. freq., for different bias conditions
return loss and a very high isolation for the MMIC coupler across its entire frequency
tuning range. Figure 5.13 shows the measured coupler isolation for the different biasing
conditions, and compares it with the theoretical isolation, which is predicted using the
expression of Eq.(5.17). The figure shows good agreement between the measurements
and theory. As indicated by Fig. 5.13, the MMIC coupler can be electronically tuned to
operate over a very wide band of frequencies; namely 2.15GHz to 3.1GHz. Across this
wide frequency range, the isolation level between the input port (P1) and the isolated
port (P4) remains higher than 40dB. An exception to this happens when the coupler
is configured to operate at 3.1GHz, where the isolation drops to 34dB. At the same
time, the return loss of the MMIC coupler at each operating frequency is maintained
below -18.6dB over the entire frequency range, except for the case when the coupler is
configured to operate at 2.15GHz where the return loss goes slightly up to -15dB as
shown by Fig. 5.14.
As previously explained in section 5.2.2, varying L and C1 in order to tune the
operating frequency while fixing the value of C2 will affect the value of the coupling
coefficient. During measurements, in order to ensure that the coupler satisfies the
matching and isolation conditions, and achieves equal power splitting between the
through and coupled ports (S21 = S31 ), the value of C2 is linearly scaled with C1 using
5.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS
−3
155
0
S21 & S31 at fo (dB)
−4
←
−20
−5
−30
−40
−6
Isolation S41 at fo (dB)
−10
→
−50
−7
2
2.2
2.4
2.6
2.8
Coupler center frequency fo (GHz)
3
−60
3.2
Figure 5.15: Measured S21 and S31 to the left and S41 to the right vs. the coupler
operating frequency. Electronically tuning the capacitances C1 and C2
provides precisely equal power splitting between the through and isolated
ports, i.e. S21 = S31 .
Vr2 . The measured MMIC coupler power levels at the coupled (P3) and through ports
(P2), as well as the coupler isolation levels are plotted versus the coupler operating
frequency in Fig. 5.15. The measured results show that across this entire range of
operating frequencies, S21 and S31 are equal and both of them vary from -3.35dB to
-4.44dB. This corresponds to a best case insertion loss of 0.35dB and a worst case of
1.44dB.
In this mode of operation, the MMIC directional coupler draws an average DC current
of approximately 132mA from a 1.5V supply, which corresponds to dissipating 197mW
across the entire frequency tuning range. According to Fig. 5.7, higher operating
frequencies require smaller inductance values, which require larger bias currents, and
vice versa. Hence, configuring the coupler to operate at 3.1GHz results in dissipating
the maximum power which is 216mW. On the other hand, configuring the coupler to
operate at the 2.15GHz results in dissipating the minimum power which is 132mW.
A more detailed discussion about power consumption is presented towards the end of
section 5.4.2.
Fixed
20dB
-36⇒-32dB,
–
<-43dB,
<50dB
– , 0.15dB
16V, 11.2V
0
–
Fixed
3dB
-24⇒-10dB,
-40⇒-27dB
-25⇒-20dB,
-20dB
0.5dB
30V
0
60mm×60mm
Coupling coeff. (C)
Insertion loss
Max bias voltage
Power diss. (mW)
Size
a
Fractional freq. range = ∆f /fo .
Isolation (S41 )
Return loss (S11 )
25%, 35%
1.3⇒1.9GHz
1.63⇒1.8GHz
33%, 10%
1.5⇒1.93GHz,
0.62⇒0.9GHz,
Freq. tuning range
Frac. freq. rangea
Printed/Varac.
Printed/Varac.
Technology
[89], [90]
[4]
Specification
18mm×18mm
0
8V
0.3⇒0.8dB
–
-27.4⇒-21.1dB
3dB
Fixed
24%
1.7⇒2.17GHz
Printed/Varac.
[91]
8mm×8mm
0
8V
1.3⇒1.4dB
–
-25⇒-14dB
3dB
Fixed
24%
1.7⇒2.17GHz
Lumped/Varac.
[92]
400µm×200µm
17.6⇒24.6@1.8V
1.8V
0.2⇒0.4dB
-18⇒-14dB
-28⇒-21dB
3dB
Fixed
26%
3.2⇒4.7GHz
0.18µm CMOS
[86]
730µm×600µm
132⇒216@.15V
2V
0.3⇒1.4dB
-50⇒-34dB
-43⇒-15.8dB
1.4⇒7.1dB
Tunable
36%
2.1⇒3.1GHz
0.13µm CMOS
This work
Table 5.2: Comparison Between the Proposed MMIC Coupler and Other Couplers with Variable Operating Frequency
5.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS
156
5.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS
157
Table 5.2 summarizes the performance of the proposed MMIC coupler with other
couplers presented in the literature [86, 88–92]. The proposed MMIC coupler has the
widest frequency tuning range (∆f /fo ), and at the same time, offers very high isolation
levels compared to the other designs. The design in [90] offers both a comparable
frequency tuning range and high isolation levels, but requires a high bias voltage of
11.2V for the discrete varactors. Besides, its printed implementation would require
a large area. Moreover, the compact CMOS implementation of the proposed MMIC
coupler allows integrating it with other RF/digital circuits, as opposed to the printed
designs of [88–91].
Similar to our proposed design, the coupler published in [86] also utilizes TAIs in a
high-pass topology. However, it does not employ varactors together with the TAIs. As
such, the coupler presented in [86] can only operate with a fixed coupling coefficient and
can not switch between forward and backward operation, as in the proposed design.
Furthermore, using TAIs only to tune the operating frequency does not allow satisfying
both the matching condition and the isolation condition simultaneously (see Eq.(5.15)
and Eq.(5.16)). This results in modest isolation and a lower relative frequency tuning
range, ∆f /fo . The design in [86] operates at slightly higher frequencies and consumes
less power, but this comes at the expense of the linearity of the coupler, and hence its
power handling capability, as will be discussed later.
Power switching
As described in section 5.2.2, one can electronically configure the MMIC coupler to
operate as either a forward coupler or as a backward coupler, i.e. switching the power
between the through port (P2) and the isolated port (P4). This is simply achieved
by interchanging the values of the bias voltages Vr1 and Vr2 applied at the gates of
the series MOS varactors C1 and C2 respectively. Figure 5.16 shows the measured
S-parameters of the MMIC coupler when it is configured to operate in the forward
mode at the nominal design frequency of 2.6GHz. By interchanging the values of the
bias voltages applied at the gates of the series MOS varactors, Vr1 and Vr2 , the MMIC
coupler switches to the backward mode of operation as indicated by Fig. 5.17. For
both modes of operation, the MMIC coupler has an isolation level higher than 42dB
and a return loss that is less than -20dB. Furthermore, in both modes of operation
5.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS
0
S21
−5
S
31
−10
S−parameters (dB)
158
S41
−15
−20
−25
−30
−35
−40
−45
1.5
2
2.5
Frequency (GHz)
3
Figure 5.16: Measured MMIC coupler S-parameters vs. frequency. Case 1: forward
operation, the input power is equally divided between ports 3 and 2 while
port 4 is isolated.
0
S21
−5
S
31
S−parameters (dB)
−10
S41
−15
−20
−25
−30
−35
−40
−45
1.5
2
2.5
Frequency (GHz)
3
Figure 5.17: Measured MMIC coupler S-parameters vs. frequency. Case 2: backward
operation, the input power is equally divided between ports 3 and 4 while
port 2 is isolated.
5.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS
140
Forward
Backward
130
Differential phase (deg)
159
120
110
100
90
←
80
70
60
2
2.2
2.4
o
→
94±2 over
a bandwidth
of 0.3GHz
2.6
2.8
Frequency (GHz)
3
3.2
Figure 5.18: Differential phase response of the MMIC coupler vs. frequency for the
forward and the backward modes of operation.
the output power is divided equally between the two output ports; P3 and P2 in the
forward case, and P3 and P4 in the backward case.
In the backward mode of operation, the MMIC coupler achieves a differential phase
(between P3 and P4) of 94±2o across a 0.3GHz bandwidth centered around the design
frequency. However, when the MMIC coupler is configured to operate in the forward
mode of operation, the asymmetry in the layout of the MMIC coupler, described in
section 5.4.1, results in some offset in the differential phase between the output ports
(P3 and P4), which becomes 98.6o . This is shown in Fig. 5.18, which plots the differential output phase for both cases. This differential phase offset can be eliminated
by positioning the MMIC coupler circuit in the center of the fabricated chip to make
the interconnecting lines from the MMIC coupler circuit to the RF pads symmetrical.
However, in this fabricated prototype the test structures were positioned in between
the MMIC coupler circuit and the left-side RF pads due to area constraints.
One potential application for this mode of operation is to connect the TX and RX
ports of a transceiver to its antenna (duplexing) while providing very high isolation.
This is shown in Fig. 5.19, where in Fig. 5.19-a, the coupler is configured to operate
5.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS
Monitoring
device
(2)
Antenna
(1)
RX
(3)
TX: Isolated
(4)
(a)
160
Monitoring
device
(2)
Antenna
(1)
TX
(4)
RX: Isolated
(3)
(b)
Forward operation: Receive mode,
Figure 5.19: Duplexer operation (a) Receive mode is achieved by configuring the coupler in the forward mode. (b) Transmit mode is achieved by configuring
the coupler in the backward mode.
in the forward mode. Hence, if the coupling coefficient, C, is configured to a very low
value (1.4dB), then most of the received power is directed to the receiver and only
a small portion goes to the through port, which could be connected to a monitoring
device to control the gain of the programmable LNAs in the receiver. Furthermore, the
TX port is isolated from the received signal. On the other hand, when transmitting,
the reconfigurable coupler is switched to the backward mode of operation. As shown in
Fig. 5.19-b, the input port of the coupler becomes port 4, which is connected to the TX
port. However, since the coupler is operating in the backward mode, the transmitted
signal is now isolated from the RX port and is divided among the antenna and the
monitoring device. In this case, the coupling coefficient can be configured to have a
very high value (7.1dB). Hence, most of the transmitted signal power is directed towards
the antenna. Finally, with measured operating frequencies ranging from 2.15GHz to
3.1GHz, the proposed design would be a suitable duplexer for multi-band applications.
The power dissipation of the proposed coupler, as it stands, is too high to be used
in portable transceivers, which tend to have low-power requirements. One possible
method to reduce the power consumption is to switch between more than one TAI
circuit in order to cover the required inductance tuning range. Hence, instead of increasing the bias currents of transistors M1 , M2 , and M4 in Fig. 3.5, the TAI circuit
responsible for small inductances can use a larger gate width for transistors M1 and
M2 and a smaller width for M4 . This follows from Eq.(3.20), which can be re-written
5.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS
−3
0
−40
−50
−9
−10
−30
Isolation S41 at 2.6GHz (dB)
−20
→
31
&S
←
−6
−8
S
−10
−5
21
at 2.6GHz (dB)
−4
−7
161
−25
−20
−15
−10
Input power level (dBm)
−60
0
−5
Figure 5.20: Measured S21 and S31 at 2.6GHz on the left and S41 at 2.6GHz on the
right vs. the input power level.
Table 5.3: Linearity Comparison Between Different
Specification
[86]
1dB compression point (P1dB )
-16dBm
–
Isolation (S41 ) at P1dB
as:
TAI based Couplers
This work
-4.16dBm
-28.3dB
s
Cgs4
∝
L∝
gm1,2 gm4
W4
,
IM 1,2 W1,2 × IM 4
(5.20)
where Wi and IM i are the width and bias current, respectively, of transistor Mi in
Fig. 3.5. Another method is to use a single TAI circuit, but replace each of the transistors M1 , M2 , and M4 with more than one parallel-connected transistors. Hence, instead
of increasing the bias current, the TAI inductance can be decreased by appropriately
switching in and out transistors.
Linearity measurements
To characterize the linearity of the MMIC directional coupler, the circuit is biased to
operate at the nominal frequency of 2.6GHz. The input power of a 2.6GHz signal is
5.5. EFFECT OF THE TAI ON THE COUPLER NOISE PERFORMANCE
162
swept from -20dBm to 0dBm and the resulting S-parameters are plotted in Fig. 5.20.
The MMIC coupler achieves a 1-dB compression point of -4.16dBm, which corresponds
to a peak-to-peak voltage swing of 391mV at the MMIC coupler input port while operating from a 1.5V supply. Also, as indicated by Fig. 5.20, as the input power increases
the isolation of the MMIC coupler drops and reaches a value of 28.3dB at the 1-dB
compression point. For input powers below -17dBm the isolation appears to remain
unchanged at approximately 55dB, which is due to the limited dynamic range of the
measurement setup. Table 5.3 summarizes the linearity performance of the proposed
MMIC coupler and compares it with the TAI-based coupler presented in [86]. Although
the proposed coupler achieves a significantly higher 1-dB compression point compared
to the TAI-based coupler in [86], its limited power handling capability precludes its use
in base stations. However, it can find applications in short-range wireless applications
requiring low transmit power levels such as wireless sensor networks (WSN) and RF
applications using ZigBee.
5.5 Effect Of The TAI On The Coupler Noise Performance
Combining the use of varactors and TAIs to implement this MMIC directional coupler
have made it a versatile highly-reconfigurable coupler capable of operating with different coupling coefficients as well as operating at different frequencies while ensuring both
a low return loss and very high isolation. Furthermore, the coupler can electronically
switch between forward and backward operation. However, using active circuits and
varactors to synthesize the tunable inductors and capacitors, respectively, affects the
noise performance of the MMIC coupler, with the main noise contributors being the
TAI circuits. Hence, this section will demonstrate the effect of the noise contribution
of the TAI circuits on the MMIC coupler noise performance.
Figure 5.21 shows the block diagram of the MMIC coupler when it is configured to
operate in the forward mode as a 3dB coupler, which is used here to derive an expression
for the output referred noise of the MMIC coupler at its through and coupled ports.
The results will then be generalized for any arbitrary coupling level.
The noise contribution of each of the grounded (1-port) TAI circuits is modeled
by a shunt noise current source inLx where x is the port number. The relationship
between these noise current sources and the noise contribution of the various TAI
5.5. EFFECT OF THE TAI ON THE COUPLER NOISE PERFORMANCE
Input port
Isolated port
Zo
inL1
inL2
(1)
Through port
(2)
inL4
inL3
(4)
163
(3)
Zo
Coupled port
Noiseless 3dB
coupler
Zo
Figure 5.21: Block diagram of a 3dB coupler with the noise current sources representing
the effect of the active circuits within the TAIs.
circuit elements (the transistors and the feedback resistor Rf ) was presented in section
3.4.3. It is interesting to note that each of the noise sources of Fig. 5.21 sees the
same impedance, which is the parallel combination of the source impedance (Zs = Zo )
and the input impedance of the coupler Zin . This fact facilitates the calculation of
the output referred noise voltages of the MMIC coupler. Assuming that the noise
generated by the TAI circuits is uncorrelated, one can use superposition to show that,
the mean-square value of the output referred noise voltage at the through port P2 is
expressed as:
2
vn2
(ω) =
´
(Zo ||Zin (ω))2 ³ 2
× inL1 (ω) + 2i2nL2 (ω) + i2nL4 (ω) .
2
(5.21)
If the average noise power generated by the four TAI circuits is the same (i2nL1 = i2nL2 =
i2nL3 = i2nL4 ), this results in the following:
2
vn2
(ω) = 2 (Zo ||Zin (ω))2 × i2nL (ω).
(5.22)
At the design frequency, the coupler input impedance is equal to Zo in order to achieve
good power matching. Hence the output referred noise voltage can be re-written as:
2
vn2
(ωo ) =
Zo2
× i2nL (ωo ).
2
(5.23)
5.5. EFFECT OF THE TAI ON THE COUPLER NOISE PERFORMANCE
164
To obtain an expression for the total output noise, the noise contribution of the
source/termination impedances should be accounted for. Assuming that the noise
sources associated with each port are uncorrelated, the expression of the output referred noise voltage becomes:
2
vn2
(ωo ) =
´
Zo2
Z2 ³
× i2nL (ωo ) + o × i2ns1 + i2ns4 ,
2
8
(5.24)
where i2nsx = 4kT /Zo is the thermal noise current generated by the source/termination
impedance at port x. Since the noise power generated by all the source/termination
impedances are equal, the total output referred noise voltage at the through port P2
can be re-written as:
Z2
Z2
2
vn2
(ωo ) = o × i2nL (ωo ) + o × i2ns .
(5.25)
2
4
From the symmetry of the coupler circuit, one can show that the output referred noise
voltage at the coupled port P3 is identical to that of the through port P2 given by
Eq.(5.25). Equation (5.25) also indicates that minimizing the noise current of the TAI
circuits is essential for optimizing the MMIC noise performance.
If the coupler is re-configured to operate with any arbitrary coupling level C, the
output referred noise voltage at the through port P2 becomes:
2
vn2
(ωo ) =
¢ i2 (ωo )Zo2
i2nL1 (ωo )Zo2 ¡
× 1 − A2 + nL2
+
4
4
¡
¢ Z 2 i2
i2nL4 (ωo )Zo2
Z 2 i2
× A2 + o ns1 × 1 − A2 + o ns4 × A2 ,
4
4
4
(5.26)
where the factor A is given by A = 10−C/20 . Again, assuming that the average noise
power generated by the four TAI circuits is the same, one obtains the same expression
of Eq.(5.25) for the output referred noise voltage at the through port. Hence, the noise
at the through and coupled ports remains the same for any arbitrary coupling level C
achieved by the MMIC coupler.
Substituting with the expression of the TAI’s noise current, given by Eq.(3.26), which
5.5. EFFECT OF THE TAI ON THE COUPLER NOISE PERFORMANCE
165
was derived in chapter 3, the output referred noise voltage becomes:
vn2 (ωo ) ≈
kT Zo + 2kT Zo2 γ (gm4 + gm5 )
Rf (1 + ωo2 Co2 Ro2 )
2gm1,2 + gm3
+ gm12 +
4
γRo2
2
, (5.27)
+2kT Zo2 γgm4
×
¶¶2
µ
µ
R
f
ωo2 Co + Cgs4 1 +
Ro
where k = 1.38 × 10−23 J/K is the Boltzmann constant, and T is the absolute temperature in degrees Kelvin. The value of the coefficient γ typically ranges from 2 to 3 for
short-channel transistors [83].
To verify the expression of Eq.(5.27), noise simulations were carried out for the
MMIC coupler while configured to operate as a 3dB coupler. The simulated MMIC
√
coupler output noise voltage, vn , and the TAI noise current, inL , were 5.25nV/ Hz
√
and 0.17pA/ Hz respectively at the design frequency. On the other hand, the corresponding noise voltage and current obtained from using the theoretical expression
√
√
of Eq.(5.27) and Eq.(3.26) are 6.2nV/ Hz and 0.2pA/ Hz respectively. This shows
that Eq.(5.27) provides a fairly accurate representation of the MMIC directional coupler
noise.
To minimize the noise of the MMIC coupler, one should design the TAI circuit using
small values for the transistor transconductances, as well as design the differential pair
to achieve a large output resistance Ro . On the other hand, large transconductances
are required to achieve the low inductance values which are necessary for configuring the coupler to operate at high frequencies. Hence, a tradeoff exists between the
maximum frequency of operation and the noise generated by the MMIC coupler. In a
telecommunication system, the effect of the noise generated by the MMIC coupler on
the overall noise figure can be reduced by preceding it with a low noise amplifier [23].
CHAPTER
6
Electronically Steerable Series-Fed Patch
Array
6.1 Introduction
T
he majority of consumer wireless applications use omni-directional antennas, and,
in some cases, antenna arrays are employed, producing narrow beams and providing better wireless coverage for specific, fixed areas. However, the lack of compact
electronically tunable phase shifters that can easily be integrated with printed antennas
has hindered the use of electronically steerable phased arrays in most wireless consumer
applications, and limited the use of electronic beam steering to high-precision, military
radar systems and satellite communications.
As explained in chapter 2, the compact feed network of a series-fed array is one of the
main advantages which make it more attractive as opposed to its parallel- or corporatefed counterparts. Besides compactness, the small size of series-fed arrays results in less
insertion loss and less radiation by the feed network. Also, the cumulative nature of the
phase shift in series arrays relaxes the design constraints on the phase tuning range of
the interstage phase shifters. For example, an N-element series-fed design can achieve
166
6.1. INTRODUCTION
167
the same scan angle range as a parallel-fed design with (N-1) times less phase tuning
range. However, this cumulative nature also results in increased beam squintinga with
frequency variations, which is one of the main limitations in series-fed designs. Another
design challenge for series-fed designs is the tight limitations set on the size occupied by
the interstage phase shifters, as well as on the variation in its input impedance across
its phase tuning range. Furthermore, in most applications it is desired to center the
main beam about the broadside direction, which is achieved by feeding the individual
antennas, of a uniform array, in-phase. This implies that an inter-element phase shift
of zero-degrees is required. Moreover, to scan the angle of the main beam about the
broadside direction, the interstage phase shifters have to be capable of generating both
positive and negative phase shifts.
Traditionally, phase shifters have employed either a low-pass or a high-pass topology.
Hence, the in-phase feeding of the antennas was achieved by feeding them with an interelement phase shift of -360o or +360o , respectively. This, however, requires cascading
multiple stages, or using meandered delay lines to achieve such large phase shifts,
potentially increasing the size and insertion loss of the phase shifters. This also increases
the group delay of the phase shifters, which in turn results in more beam squinting.
With the recent developments in the field of metamaterials [3, 4], it is now possible
to design compact PRI/NRI phase shifters having phase shifts centered around the
zero-degree mark and at the same time having small group delays [5]. The work
in [5] was combined with CMOS microelectronic circuit techniques in chapter 4 of this
thesis to build printed as well as fully-integrated compact tunable PRI/NRI phase
shifters by using both varactors and TAIs. These tunable PRI/NRI phase shifters
also feature constant input impedance and are capable of producing both positive and
negative phase shifts. The compact size of these PRI/NRI phase shifters allows them
to be integrated with series-fed antenna arrays onto a single PCB. The resulting planar
structure is more appealing for low-cost wireless consumer applications, as opposed to
traditional designs in which the phase shifters and the antennas are implemented on
separate PCBs [98]. Furthermore, using the PRI/NRI phase shifters allows centering
the main beam of the array at the broadside direction and electronically scanning it in
both directions. In contrast, in the majority of the previously published designs this
a
Beam squinting is defined here as the variation in the angle of the main beam of the antenna array
with frequency.
6.2. THEORY
168
is achieved by physically terminating the input port and exciting the array from the
opposite port [98–100]. PRI/NRI phase shifters have been employed in [101] to design
a high-gain leaky-wave antenna array. This array is capable of electronically scanning
its main beam about the broadside direction, achieving both positive and negative
scan angles. However, using only varactors as the tunable elements results in a poor
return loss for the antenna array across its entire scan angle range, with a best case
of -12.5dB and a worst case of -6dB. Furthermore, the leaky-wave design results in a
very large gain degradation of 55% when the beam is merely scanned beyond ±6o off
the broadside direction.
In this chapter, an electronically steerable, series-fed patch array for 2.4GHz ISM
band applications is presented. The entire antenna array (i.e. the antennas, phase
shifters, and the feed network) is integrated onto a single PCB. The proposed steerable
array uses zero-degree tunable PRI/NRI phase shifters to center its radiation about
the broadside direction and allow scanning in both directions off the broadside. Also,
using these PRI/NRI phase shifters minimizes the squinting of the main beam across
the operating bandwidth. Furthermore, the feed network of the proposed array utilizes
λ/4 impedance transformers, which allows using identical interstage phase shifters,
and the sharing of the same control voltages to tune all stages. To the author’s knowledge, the proposed antenna array is the first resonant antenna-element structure that
demonstrates electronic beam steering utilizing tunable PRI/NRI phase shifters. The
proposed steerable array uses the TAI-based, TL zero-degree PRI/NRI phase shifters
presented in chapter 4 in order to extend the scan angle range and at the same time
maintain a low return loss. Furthermore, the proposed array is capable of steering its
beam with small variations in its gain and its HPBW.
6.2 Theory
6.2.1 Antenna Array Architecture
The electronically steerable antenna array presented in this chapter consists of four
series-fed antennas and three interstage phase shifters as depicted by the basic architecture in Fig. 6.1. The array has a travelling-wave nature, however, it is not terminated
with a 50Ω load impedance as in traditional travelling-wave designs. Instead, the real
6.2. THEORY
169
dE<
T
PS
ZPS1
PS
ZPS2
PS
ZPS3
Figure 6.1: Basic 4-element series-fed antenna array.
dE<
T
PS
PS
PS
ZPS
ZPS
ZPS
Figure 6.2: 4-element series-fed antenna array with λ/4 impedance transformers.
part of the antenna impedances are used as the termination for the array. Eliminating the load impedance improves the overall efficiency of the array, since it suppresses
the power dissipated in the termination, which could be on the order of 12.5% of the
input power as in the 5-element series-fed patch array in [99, 100]. For such an array
configuration, the standard and simplest design approach used in previously published
work (for example [98]) to feed the antennas is to progressively change the characteristic impedance of the main feed line in order to maintain good matching for the array.
This, however, requires all the interstage phase shifters to have different impedance levels, which complicates the array design by requiring different interstage phase shifter
designs. Furthermore, it complicates the process of electronic scanning by requiring a
separate set of control voltages to be applied to each interstage phase shifter.
An alternative approach is proposed in this chapter to allow using identical interstage
phase shifters, and to permit using a single set of control voltages to tune all the
stages. In this architecture, two λ/4 transformers are inserted before and after each
interstage phase shifter, which helps set the impedance level of the feed line to the value
required by the phase shifters (ZP S ). Hence, the impedance of the λ/4 transformers is
6.2. THEORY
170
adjusted to achieve the desired matching, while keeping all the interstage phase shifters
identical. This allows using a single set of control voltages for tuning all the stages
simultaneously, thereby simplifying the steering of the antenna beam. Furthermore, if
constant input impedance phase shifters are utilized, the return loss of the series-fed
array can be minimized across the entire phase tuning range, or in other words, across
the entire scan-angle range. Moreover, these λ/4 transformers allow one to control the
power splitting ratios at each junction in Fig. 6.2, which helps ensure equal amplitude
excitation for the individual antennas. This will be described in more detail later in
section 6.2.2.
In the array architecture of Fig. 6.2, each λ/4 transformer contributes a -90o phase
shift. Hence, the total cumulative phase shift from one antenna to the next, φT , is
given by:
π
+ φP S .
(6.1)
2
To achieve the desired broadside radiation, the antennas need to be fed in-phase, i.e.
φT = −2 ×
φT = 0, which according to Eq.(6.1) requires the phase response of the interstage
phase shifters φP S to be centered around +180o . But as described above, such large
phase shifts result in large group delays, which, in turn, will result in increased beam
squinting.
To address this problem, the array architecture in Fig. 6.2 is modified by alternating
the antennas with respect to the feed line as shown in Fig. 6.3. Alternating the antennas
is a known technique for the design of series-fed arrays. However, this is the first
time it has been used with tunable metamaterial PRI/NRI phase shifters to realize an
electronically steerable phased array. To achieve broadside radiation using the proposed
alternating architecture, the total cumulative phase shift φT should be set to 180o ,
which is already realized by the intrinsic phase shift of the two λ/4 transformers. Hence,
according to Eq.(6.1) the interstage phase shift φP S should be centered around the zerodegree mark. This means that the alternating series-fed array architecture of Fig. 6.3
can take advantage of the recent developments in small group delay metamaterial
PRI/NRI phase shifters to scan the main beam about the broadside direction, and at
the same time, minimize beam squinting.
6.2. THEORY
171
(1:3)
PA
¾ PA
dE<
¼ PA
ZPS
A
B
ZT5 ZT4
ZT6
ZPS
C
PS
PS
PS
ZT7
Zin1
ZPS
ZT3
PC
̄ PB
(1:2)
ZT1
(1:1)
̃ PB
PB
ZT2
½ PC
½ PC
Figure 6.3: Alternating patch array diagram indicating the required ideal power splitting ratios and all the λ/4 transformer impedances.
6.2.2 Feed Network Design
As described in section 6.2.1, the feed network of the antenna array uses λ/4 impedance
transformers, which allows us to use identical interstage phase shifters (i.e. the phase
shifters have the same phase shift φP S and the same impedance ZP S ). Also, to simplify
the design, we use 4 identical antennas which have the same real input impedance, ZA ,
at the design frequency. Starting the design of the feed network from the right-side of
Fig. 6.3, the characteristic impedance of the first λ/4 transformer, ZT 1 , should be set
to:
p
ZT 1 = ZA ZP S
(6.2)
in order to guarantee that this interstage phase shifter is properly terminated and
consequently eliminate any reflections at its input and output ports. On the other
hand, the second λ/4 transformer, ZT 2 , gives us an additional degree of freedom to
adjust the impedance level which is loading the main feed line at junction C. One
should design this impedance level for a 1:1 power splitting ratio at junction C to
achieve equal amplitude excitations for the last 2 antennas. This, however, is only
valid under the assumption that the interstage phase shifters are lossless. Later on we
will demonstrate how the phase shifter loss can be incorporated in the design to still
6.2. THEORY
172
maintain the equal amplitude excitation. For the lossless case, the loading impedance
to the left side of junction C, Zin1 in Fig. 6.3, should be set to ZA . This is satisfied if
the second transformer has an impedance of:
ZT 2 =
p
Zin1 ZP S =
p
ZA ZP S .
(6.3)
Following the same procedure, one can derive the values of the characteristic impedances
of all the λ/4 transformers, which are given by the following equations:
r
ZT 3 = ZT 4 =
and
ZA ZP S
,
2
(6.4)
r
ZA ZP S
.
(6.5)
3
The power splitting ratios are shown in Fig. 6.3. Note how the power splitting ratio
changes for each junction; at junction B, 1/3 of the power should be delivered to the
ZT 5 = ZT 6 =
antenna whereas 2/3 of it should be directed to the subsequent stages, i.e. the power
splitting ratio should be 1:2. Similarly, at junction A, 1/4 of the input power should be
delivered to the antenna whereas 3/4 of it should be directed to the subsequent stages,
i.e. the power splitting ratio should be 1:3. Constraints represented by Eq.(6.2)-(6.5)
ensure the same amount of power is delivered to all the antennas regardless of the
power division happening at each junction. An additional λ/4 transformer is added
at the input port of the series-fed array in order to match its input impedance to the
source impedance, Zo . Hence, the characteristic impedance of the input transformer is
expressed as:
r
ZA Zo
.
(6.6)
ZT 7 =
4
The feed network presented in [98] uses a similar approach to achieve equal power
splitting. However, the power splitting ratios at each junction are adjusted by varying
the impedance level of the interstage phase shifters. In contrast, in our proposed design,
this is achieved by varying the impedance of the interconnecting microstrip TLs while
using identical interstage phase shifters, which allows using only one set of control
voltages for beam steering.
Also, as previously mentioned, the λ/4 transformers inserted before and after each
6.2. THEORY
173
interstage phase shifter ensure matching the phase shifter’s input and output impedance
ZP S to its source and load impedances, respectively. Hence, when the electrical length
(or the phase shift φP S ) of the interstage phase shifters is varied to scan the angle of
the main beam, the input impedance of the entire series-fed array remains unchanged.
This ensures a low return loss, S11 , for the array for all scan angles. However, this is
only valid as long as the interstage phase shifters can provide a fixed impedance ZP S
across their entire phase tuning range, which imposes an important constraint on the
interstage phase shifter’s design. This will be explored in more detail in section 6.2.3.
If the interstage phase shifters have a finite insertion loss which can be represented by
their forward transmission coefficient S21 , one can show that the power splitting ratios
at junctions A, B, and C should be modified to 1 : (1 + G + G2 )/G3 , 1 : (1 + G)/G2 ,
and 1 : 1/G, respectively, where the factor G represents the absolute power gain of
the interstage phase shifters given by G = 10S21 /10 , where S21 is in dB. Consequently,
the characteristic impedance of the different λ/4 transformers need to be adjusted
according to the following equations:
ZT 1 =
p
p
ZA ZP S , and ZT 2 = ZA ZP S G,
r
ZT 3 =
r
ZT 5 =
r
ZA ZP S G2
,
1+G
r
ZA ZP S G3
=
,
1 + G + G2
ZA ZP S G
, and ZT 4 =
1+G
(6.7)
ZA ZP S G2
, and ZT 6
1 + G + G2
r
Zo ZA G3
ZT 7 =
.
1 + G + G2 + G3
(6.8)
(6.9)
(6.10)
Equation(6.7)-(6.10) ensure delivering the same amount of power to all the antennas
regardless of the interstage phase shifter losses, and regardless of the power division
taking place at each junction. Furthermore, one can extend this analysis to obtain an
expression for the efficiency of the proposed feeding network, which can be expressed
as follows:
P4
Pantenna,i
4G3
=
ηf eed = i=1
(6.11)
Pin
1 + G + G2 + G3
Table 6.1 lists the achievable efficiency by the proposed feed network for different
6.2. THEORY
174
Table 6.1: Series Feed Network Efficiency For Different Interstage Phase Shifter Loss
Values
S21
G
ηf eed
0dB
1
-0.5dB
0.89 83%
-1dB
0.79 68%
-1.5dB
0.71 56%
-2dB
0.63 44%
100%
values of the interstage phase shifter loss. It is clear from the table that using this
series architecture puts tight constraints on the interstage phase shifter losses.
To demonstrate how much the antenna power mismatch can be reduced by using the
proposed approach, Fig. 6.4 plots the maximum power mismatch, calculated between
the first and the fourth antennas versus the interstage phase shifter losses, |S21 |. The
maximum power mismatch shown in Fig. 6.4 is computed for two different designs.
The first design employs only power splitting ratio compensation. Hence, the phase
shifters are assumed lossless in the design phase and Eq.(6.2)-(6.5) are used to size the
transformers. As the figure indicates, the power mismatch is only zero when the phase
shifter losses |S21 |=0dB, and increases for higher values of |S21 |. On the other hand, the
second design employs both phase shifter loss and power splitting ratio compensation.
A phase shifter loss of 1.5dB is assumed in the design phase and Eq.(6.7)-(6.10) are
used. Here we see that the location of the zero power mismatch has moved to the point
where |S21 |=1.5dB. Consequently, when the phase shifters have a loss of 1.5dB, this
approach reduces the worst case power mismatch between the antennas by 64%.
Mismatches in the signal power feeding the antennas will affect the radiation pattern
of the array, which is a function of both the amplitude and the phase of the array excitation. Figure 6.5 shows the normalized array factor for the previous two designs (i.e.
the design employing only power splitting ratio compensation and the one employing
both phase shifter loss and power splitting ratio compensation), and compares them
with the array factor of a standard array which does not employ any type of compensation and assumes that the signals split equally at each junction. All three designs
assume a 4-element, λo /2 array, and a phase shifter loss |S21 | of 1.5dB. As indicated
6.2. THEORY
175
Power mismatch (%)
80
60
↑
40
64%
reduction
in power
mismatch ↓
20
0
−20
w power splitting comp.
w PS loss and power
splitting comp.
−40
−60
0
0.5
1
1.5
2
2.5
Interstage phase shifter loss |S | (dB)
3
21
Figure 6.4: Power mismatch between the first and fourth antennas versus the interstage
phase shifter insertion loss for two different cases: (a) array designed with
power splitting ratio compensation, (b) array designed with both phase
shifter loss and power splitting ratio compensation.
−15°
0°
15°
−30°
30°
−45°
45°
−60°
60°
−75°
−90°
75°
−30
−20
−40
w/o comp.
w power splitting comp.
w PS loss and power splitting comp.
−10
0
90°
Figure 6.5: Normalized array factors for a 4-element λo /2 antenna array designed for
three different cases: (a) the standard design without compensation and
assuming the signals split equally at each junction, (b) designed with power
splitting ratio compensation, (c) designed with both phase shifter loss and
power splitting ratio compensation.
6.2. THEORY
176
by the figure, reducing the power mismatch by employing compensation enhances the
quality of the radiation patterns by increasing the antenna rejection at the pattern
nulls. This is achieved at the cost of a 0.6dB drop in the gain of the antenna array.
6.2.3 Interstage Phase Shifters
As previously described in section 6.2.1, in order to center the radiation pattern of the
proposed antenna array at the broadside direction, tunable zero-degree phase shifters
should be used to implement the interstage phase shifters. As demonstrated in chapter
4, PRI/NRI phase shifters are capable of centering their phase response around the
zero-degree mark, and are capable of generating both positive and negative phase
shifts. This makes tunable PRI/NRI phase shifters a suitable choice to implement the
interstage phase shifters. Furthermore, the tunable PRI/NRI phase shifters presented
in chapter 4 are capable of maintaining a constant impedance, ZP S , across their entire
phase tuning range. This was achieved by employing both varactors and TAIs. Having
a constant impedance is important to provide the array with a low return loss across
its entire scan-angle range. It also helps to minimize the mismatch in the power level
feeding the different antennas, since the power splitting ratios are determined by the
impedance levels. Furthermore, these PRI/NRI phase shifters possess small group
delays, which is important to achieve low beam squinting. In order to quantify this,
Eq.(A-3) in Appendix A gives the relationship between the variation in the azimuthal
angle, θ, of the main beam of the proposed antenna array and the group delay, Tgd , of
the interstage phase shifters. The key result is that one should try to minimize Tgd in
order to reduce the effect of frequency on the direction of the main beam. This makes
the tunable PRI/NRI phase shifters of chapter 4 suitable for the implementation of the
interstage phase shifters.
Among the different tunable PRI/NRI phase shifters presented in chapter 4, the
TL-based design seemed a natural choice, due to several reasons. First of all, it can
be easily integrated onto the same PCB with the feed network, and the printed antennas. Secondly, it provides the lowest insertion loss, and the highest FOM, i.e. the
highest phase tuning range per dB of loss. Also, the TAI package parasitics were already accounted for during the design phase of the TL PRI/NRI phase shifter, and no
additional packaging was required. This made the tunable TL PRI/NRI phase shifter
6.2. THEORY
177
Figure 6.6: Transmission-line tunable PRI/NRI metamaterial phase shifter unit-cell.
more attractive for the design of the proposed printed antenna array.
The design of the TL PRI/NRI phase shifter was described in detail in chapter 4.
However, for completeness, some of the relevant design equations are briefly highlighted
in this section. Figure 6.6 shows the unit-cell of the TL tunable PRI/NRI phase shifter,
which is composed of a regular microstrip line, with a characteristic impedance Zo . The
microstrip line is loaded with two series varactors, with capacitance C, and a shunt
TAI, L. Cascading the PRI TL with the NRI section (i.e. the series capacitors and
shunt inductor in Fig. 6.6) compensates the phase shift incurred by the propagating
signal. The phase shift of the PRI/NRI phase shifter unit-cell can be approximated as:
√
2
− 2θT L
φ≈ √
ω LC
(6.12)
where θT L is the phase lag due to one section of the PRI microstrip TLs, given by
θT L = βT L dP S /2. Equation (6.12) indicates that positive and negative phase shifts
can be realized by a single unit-cell without having to go through a complete 360o
phase rotation as in traditional high-pass or low-pass architectures. This inherently
guarantees a small group delay for these phase shifters, which is expressed as:
Tgd
1
dφ
≈
=−
dω
ω
à √
!
2
√
+ 2θT L .
ω LC
(6.13)
6.3. ANTENNA ARRAY DESIGN
178
One can intuitively understand this small group delay nature by investigating Eq.(6.12)
and Eq.(6.13) simultaneously; Eq.(6.12) indicates that one achieves the zero phase
without the need for large values by either of its two terms, i.e. +2π by the NRI section
as in a traditional high-pass design, or -2π by the PRI section as in a traditional lowpass design. Alternatively, the zero phase is achieved by having two small and equal
contributions from the NRI and PRI sections, which eventually cancel-out due to the
negative sign in Eq.(6.12). Now looking at the group delay expression of Eq.(6.13), in
which the two terms add-up, one can see that the small phase contributions by the
NRI and PRI sections will automatically result in a small group delay.
The phase response of the PRI/NRI phase shifter is tuned by simultaneously changing the values of both the loading elements L and C. This is achieved by using both
TAIs and varactors, and results in a larger phase tuning range compared to varying C
only as was demonstrated in chapter 4. Furthermore, changing L and C simultaneously
according to the following equation,
r
Zo =
2L
C
(6.14)
where Zo is the microstrip TL characteristic impedance, will result in a constant phase
shifter impedance, i.e. ZP S = Zo , and consequently result in a low return loss across
the entire phase tuning range.
6.3 Antenna Array Design
A 4-element series-fed array is designed to operate in the 2.4GHz ISM band. The array
is based on the proposed alternating architecture of Fig. 6.3, and uses the TL tunable
PRI/NRI phase shifters of chapter 4 to implement the three interstage phase shifters.
Four identical λ/2 resonant rectangular patches are used as the antenna elements.
Although patch antennas have a relatively small impedance bandwidth, they are used
here for their simplicity. In order to be able to integrate the patches and the beam
steering network onto the same PCB, the interstage phase shifter and the two λ/4
transformers have to fit between each pair of consecutive patches, which might imply
increasing the inter-element distance, dE , to accommodate them. On the other hand,
it is important to avoid capturing grating lobes in the radiation pattern, which can be
6.3. ANTENNA ARRAY DESIGN
179
guaranteed if the following condition is satisfied:
dE ≤
λo
,
2
(6.15)
where λo is the free-space wavelength. Eq.(6.15) is a fundamental equation, since it
sets the maximum distance between each two consecutive patches. Consequently, this
sets tight limitations on the interstage phase shifter dimensions. In this design, the
inter-element distance was chosen to be λo /2 in order to avoid capturing any grating
lobes in the radiation pattern, and at the same time provide the maximum allowable
space, which corresponds to an inter-element distance dE of 6.25cm at 2.4GHz.
To increase the phase tuning range and consequently the scan-angle range, two unitcells of the TL PRI/NRI phase shifter shown in Fig. 6.6 are cascaded to form each
interstage phase shifter. This will double the phase tuning range, while having a minor
effect on the phase shifter return loss S11 . However, this will increase the interstage
phase shifter insertion loss. The average insertion loss of the PRI/NRI phase shifter
unit-cell was extracted from simulations to be 0.77dB, resulting in an average interstage
phase shifter loss of 1.55dB. This estimated loss was used in the design of the feed
network by using Eq.(6.7)-Eq.(6.10) to size the transformers.
Integrating the antenna array, feed network, and phase shifters onto a single-layer
PCB prevents us from designing each one of them independently, and forces us to treat
their design as three coupled designs. For instance, if one would design the patches
separately, a low substrate relative permittivity, ²r , and would be desirable in order to
increase the patch bandwidth and at the same time its radiation efficiency. On the other
hand, one has to trade-off between the patch bandwidth and efficiency when choosing
the substrate thickness, h [102]. However, a lower ²r entails longer λ/4 impedance
transformers and longer PRI/NRI phase shifters, as now we require a longer microstrip
TL to compensate for the positive phase shift from the NRI section. This becomes
evident by re-writing the phase shift expression of the PRI/NRI unit-cell as:
√
ωdP S √
2
−
²ef f ,
φ≈ √
c
ω LC
(6.16)
where ²ef f is the effective relative dielectric constant of the phase shifters’s microstrip
6.3. ANTENNA ARRAY DESIGN
180
TLs [24], and is given by:
²ef f =
1
²r + 1 ²r − 1
+
×p
.
2
2
1 + 12h/W
(6.17)
In Eq.(6.17), h and W are the substrate height and the microstrip TL width, respectively. Now by looking at Fig. 6.3, one can see that the λ/4 impedance transformers
and the interstage phase shifter have to fit in a fixed distance, dE , to avoid meandering
the lines. Consequently, ²r can not take an arbitrarily small value. Furthermore, we
will show that for a given value of the positive phase shift, φN RI , from the NRI section,
there exists an optimum value for ²r , that will allow centering the radiation around
the broadside direction, and at the same time satisfy the physical constraints imposed
by the requirement for a single PCB implementation. This physical constraint simply
requires that the sum of the lengths of the two λ/4 transformers and the interstage
phase shifter to be λo /2, i.e.:
dE =
λ
λo
= × 2 + 2dP S ,
2
4
(6.18)
√
where λ = λo / ²ef f is the guided wavelength, and the factor 2 in the second term is
added to account for the cascading of two PRI/NRI unit-cells for each interstage phase
shifter. However, this assumes that the two λ/4 transformers have the same ²ef f , which
neglects the change in their width. For the sake of simplicity, all the microstrip TLs
are assumed to have an equal ²ef f , which represents an average value for the different
width TLs. Equating Eq.(6.16) to zero and solving it with Eq.(6.18) results in the
following expression for the optimum substrate dielectric constant:
µ
²ef f =
φN RI
1+2
π
¶2
,
(6.19)
where φN RI is the average phase shift generated by the NRI section, which is expressed
as:
√
2
.
(6.20)
φN RI = √
ω LC
Now substituting the result of Eq.(6.19) in Eq.(6.16), one can obtain the length of the
TL PRI/NRI phase shifter unit-cell required for broadside radiation. This results in
6.3. ANTENNA ARRAY DESIGN
181
the following expression:
dP S = λo
φN RI
.
√
2π ²ef f
(6.21)
As Eq.(6.19) and Eq.(6.21) indicate, the design parameters ²ef f and dP S are a function of the NRI section’s phase shift, φN RI . The value of φN RI can be calculated
using the average TAI inductance and varactor capacitance. The average inductance
generated by the TAI chips is obtained from the measurements presented in chapter
3. However, a fixed 2.7nH inductance is added to the inductance values reported in
chapter 3 to account for the parasitic bond wire and package inductance. The varactor
capacitance values can be obtained from the matching condition, given by Eq.(6.14),
which results in C = 2L/ZP2 S . In this design, the impedance of the PRI/NRI phase
shifters, ZP S , was not set to 50Ω, but was chosen as 75Ω. This choice was made in
order to extend the phase tuning range of the phase shifters, which can be expressed
as:
ZP S
|∆φP S | =
2ωL
¯ ¯
¯¶
µ¯
¯ ∆C ¯ ¯ ∆L ¯
¯+¯
¯
¯
¯ C ¯ ¯ L ¯ .
(6.22)
Eq.(6.22) indicates that, for a fixed inductance value, the phase tuning range can be
increased by designing the phase shifters to exhibit a high impedance level. Note that
the matching at the higher impedance level requires smaller capacitance values.
Now we can substitute in Eq.(6.19) to evaluate the optimum ²e , which results in a
value of 3.44. Using Eq.(6.17), one can use the value of ²ef f to calculate the optimum
substrate ²r . This, however, this requires knowledge of the substrate height and the
average TL width. A 125mil thick substrate is chosen for the design. From simulations,
this thickness allows us to achieve a reasonable trade-off between the patch bandwidth
and its radiation efficiency. As for the average microstrip TL width, a reasonable
assumption is to equate it to the desired width of the middle section TLs (i.e. ZT 3
and ZT 4 in Fig. 6.3), which was chosen as 2.5mm. Now one can use the correction
factor h/W in Eq.(6.17) to obtain the optimum substrate relative permittivity ²r ,
which turns out to be 4.9. If the value of ²r obtained does not result in an adequate
radiation efficiency or an adequate bandwidth for the patches, one can change the value
of φN RI by picking different lumped-element values. In this design, the value of φN RI
was dictated by the inductance values obtained from the fabricated TAI chips. Based
on these calculations, a 125mil TMM4 Rogers ceramic substrate with an ²r of 4.5 was
6.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS
182
selected for the design of the steerable array. This results in a length of 14.41mm for
each of the TL PRI/NRI phase shifters. Electro-magnetic simulations were carried-out
in Agilent-Momentum, and the results show that the length of the TL PRI/NRI phase
shifters should be 14mm. This shows very good agreement between the value obtained
from the theoretical expression of Eq.(6.21) and the value obtained from simulations.
6.4 Physical Implementation and Experimental Results
The proposed steerable antenna array was fabricated on a 125mil TMM4 Rogers ceramic substrate. In order to characterize the electronically steerable array, one first
needs to determine the appropriate control voltages required to obtain the different
scan angles. To this end, a separate prototype of the TL PRI/NRI interstage phase
shifter was fabricated using the same substrate material and characterized.
6.4.1 Interstage Phase Shifter
A picture of the fabricated interstage phase shifter prototype is given in Fig. 6.7. It is
composed of a cascade of two tunable TL PRI/NRI phase shifters. Each stage is composed of a microstrip TL loaded with 2 series SMV1232 silicon hyper-abrupt junction
varactor diodes from Skyworks, and the TAI chip which uses a 4mm×4mm high-speed
QFN (Quad Flat-Pack No Lead) package to minimize the package parasitics. The input and output of the interstage phase shifter are connected through the surface mount
right-angled SMA connectors to the left and right sides of the board, whereas the bias
and control lines going to the varactors and the TAI chips are supplied from the upper
and lower sides of the board. Printed RF chokes are used to provide the varactor control voltages to the main TL while providing a high impedance at 2.4GHz for the signal
on the main TL. This is achieved by connecting radial stubs through high-impedance
λ/4 TLs. The minimum reliable trace width (100µm) allowed by the fabrication process was used for these λ/4 TLs to provide high isolation. Also, a set of three parallel
de-coupling capacitors, 68pF each, are used to stabilize each of the bias and control
voltages by providing a low-impedance path to the ground plane. The interstage phase
shifter roughly occupies an area of 3.6cm×6cm. As previously mentioned in section 6.3,
the interstage phase shifters are designed to exhibit an impedance of 75Ω, so in order
6.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS
Bias & control
inputs
183
Tunable active
inductor (TAI) chips
6cm
Varactors
Printed
RF choke
3.6cm
De-coupling
capacitors
Figure 6.7: Photograph of the fabricated tunable TL PRI/NRI interstage phase shifter.
6.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS
184
Insertion phase φ
PS
(deg)
300
φPS = −97o → +100o
at 2.4GHz
↓
V
200
100
VAR
increases
0
−100
↑
−200
2
2.5
Frequency (GHz)
3
Figure 6.8: The measured insertion phase φP S vs. freq. for different bias conditions.
to characterize the phase shifters in a 50Ω environment, two printed λ/4 transformers
were added before and after the phase shifter to match it to the 50Ω equipment. However, the phase shift due to these transformers together with the connectors response
were de-embedded by characterizing a TL through connection fabricated on the same
substrate material.
Figure 6.8 shows the measured phase response of the TL PRI/NRI interstage phase
shifter when both the varactor capacitance and the TAI inductance are varied. To
generate these different phase responses the varactor control voltage Vvar was swept
from 3V to 15V, and for each case, the appropriate TAI control voltages that result
in the desired inductance, given by Eq.(6.14), are determined. This, however, requires
the characterization of the TAI chips, which was presented in chapter 3. At the design
frequency of 2.4GHz, the insertion phase can be varied from -97o to +100o passing
through the zero-phase point by changing the varactor control voltage from 3V to 15V,
respectively. The interstage phase shifter is capable of achieving both positive and
negative phase shifts at the design frequency without going through an entire 360o
rotation. Furthermore, across this entire phase tuning range, the matching condition
is satisfied, and the return loss, S11 , is maintained below -15dB at 2.4GHz. Figure 6.9
shows the measured S11 and S21 at 2.4GHz versus the interstage phase shift. Across the
6.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS
−1
185
−5
−15
−4
−20
at 2.4GHz (dB)
−3
11
−10
S
−2
S
21
at 2.4GHz (dB)
←
→
−5
−6
−100
−75
−50
−25
0
25
50
Insertion phase at 2.4GHz (deg)
−25
75
−30
100
Figure 6.9: Measured S21 and S11 at 2.4GHz versus the insertion phase of the interstage
phase shifter.
entire phase tuning range S11 varies from -27.5dB to a worst case of -15dB at the two
extremes. Also the interstage phase shifter S21 changes from -1.6dB to a worst case of
-2.4dB at the two extremes. The phase shifter achieves a bandwidth of 0.44GHz across
which S11 is less than -10dB. Across the phase tuning range, the interstage phase shifter
dissipates an average DC current of approximately 116mA from a 1.5V supply, which
corresponds to an average power consumption of 174mW.
x
7.1cm
ZT7
ZT6
ZT5
ZT4
22.6cm
PRI/NRI interstage
phase shifters
ZT3
ZT2
Bias & control inputs
ZT1
Figure 6.10: Photograph of the fabricated electronically steerable series-fed patch array utilizing the tunable TL
PRI/NRI interstage phase shifters.
RF RX/TX
port
z
y
De-coupling
capacitors
6.4.2 Steerable Antenna Array
6.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS
186
6.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS
187
A picture of the fabricated 2.4GHz electronically steerable antenna array is given in
Fig. 6.10. As shown in the figure, the antennas, the feed network, and the TL PRI/NRI
interstage phase shifters are all fabricated on a single-layer PCB and the bottom conductor acts as the ground plane. The core of the antenna array occupies an area of
22.6cm×7.1cm and is fabricated on a 125mil TMM4 Rogers ceramic substrate with
an ²r of 4.5. The RF transmit/receive signal is connected through the surface mount
right-angled SMA connector on the left side of the PCB, whereas the bias and control
lines going to the interstage phase shifters are supplied from the upper and lower sides
of the PCB. Note that the array is fed only from one end, making it truly electronically
steerable, and it does not require switching the feeding and terminating ports as in
the other array designs presented in [98]- [100], where the switching is necessary to
center their radiation about the broadside. The proposed array uses four identical alternating rectangular patches. The size of each patch antenna is 2.7cm(L)×3.7cm(W).
The patch’s width is chosen to be longer than the length to decrease the real part of
the patch impedance at resonance. This, however, is not enough to bring the patch
impedance to the desired value and the inset feeding technique, which was briefly described in chapter 2, is used to achieve a patch impedance ZA of 190Ω. To provide good
power matching, the patches are then connected to the main feed line through 190Ω
microstrip TLs. Using a characteristic impedance equal to ZA allows us to maintain
good matching at the design frequency regardless of the length of these interconnecting
lines, which are 7.5mm long measured from the center of the feed line to the patch edge.
The value of the patch impedance was dictated by the PCB fabrication process, which
allows us to use a minimum trace width of 100µm. This, in turn, results in a maximum
realizable microstrip TL characteristic impedance of 190Ω.
As evident in Fig. 6.10, the width of the λ/4 impedance transformers decrease as
we move away from the RF port, which accounts for the increasing characteristic
impedances computed from Eq.(6.7)- Eq.(6.10). To avoid having a very wide microstrip
TL for the left-most λ/4 impedance transformer ZT 7 , the array is designed to have a
75Ω input impedance (i.e. Zo in Eq.(6.10) is set to 75Ω), and another tapered transformer placed right at the SMA connector is designed to match the array impedance to
the 50Ω environment. Also one can see from Fig. 6.10 that the array uses identical TL
PRI/NRI interstage phase shifters. The DC bias and control voltages are supplied to
the TL PRI/NRI interstage phase shifters using a ribbon cable which runs underneath
6.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS
188
the PCB, and a small 2.5mm×40mm rectangular-shaped cut in the bottom conductor
(i.e. the ground plane) allows us to connect these DC voltages to the bias lines on the
top side of the PCB. Another set of four parallel de-coupling capacitors (91pF, 1nF,
0.1µF, 10µF) are used to stabilize each of the bias and control voltages in Fig. 6.10 by
providing a low-impedance path to the ground plane. Printed RF chokes are used to
provide the varactor control voltages to the main TL, while providing a high impedance
at 2.4GHz for the signal on the main TL.
Gain Patterns
The fabricated antenna array was characterized in an antenna anechoic chamber while
operating in the receive mode. The measured co- and cross-polarization gain patterns
and the simulated co-polarization gain patterns in the azimuth plane (i.e. the x-z plane)
are presented in Fig. 6.11 for different bias conditions. To generate these different plots,
the control voltages of the varactors, Vvar , and of the TAI chips were obtained from the
characterization of the TL PRI/NRI interstage phase shifter. For each set of control
voltages, the interstage phase shifters generate a different phase while maintaining low
return and insertion losses. The results in Fig. 6.11 show that the proposed array is
capable of continuously steering its main beam from an angle of -27o to an angle of
+22o passing through the broadside direction by simply changing Vvar from 15V to 3.5V
and accordingly adjusting the control voltages going to the TAI chips to achieve the
desired inductance level. As previously explained in section 6.2, the ability to achieve
both negative and positive scan angle is due to the use of the tunable PRI/NRI phase
shifters. Across this entire 49o scan angle range, the gain of the antenna array varies
from a maximum of 8.4dBi to a worst case of 6.9dBi and the side-lobes are at least
10dB lower than the the main-lobe. Furthermore, the cross-polarization gain is always
less than that of the co-polarization by at least 14.7dB measured at the peak angles.
It is worth noting that, in the proposed design, the gain variation across the entire 49o
scan angle range is less than 1.5dB compared to more than 10dB gain degradation in
the leaky-wave design reported in [101] when its beam is merely scanned beyond ±6o
off the broadside direction.
Note that the radiation patterns are not perfectly symmetric for both positive and
negative scan angles. For example Fig. 6.11-b and Fig. 6.11-f have slightly different
6.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS
−30°
−15°
0°
15°
30°
−30°
−45°
45°
−60°
−75°
75°
90°
−20
−105°
105°
−10
−120°
120°
0
−135°
0°
15°
30°
−45°
60°
−90°
−15°
45°
−60°
60°
−75°
75°
−90°
90°
−20
−105°
105°
−10
−120°
135°
120°
0
−135°
135°
−150°
150°
10165°
−165°±180°
−150°
150°
10165°
−165°±180°
(a)
(b)
−30°
−15°
0°
15°
30°
−30°
−45°
45°
−60°
−75°
75°
−90°
90°
−20
−105°
105°
−10
−120°
120°
0
−135°
−15°
0°
15°
30°
−45°
60°
45°
−60°
60°
−75°
75°
−90°
90°
−20
−105°
105°
−10
−120°
135°
120°
0
−135°
135°
−150°
150°
10165°
−165°±180°
−150°
150°
10165°
−165°±180°
(c)
(d)
−30°
−15°
0°
15°
30°
−30°
−45°
45°
−60°
−75°
75°
−90°
90°
−20
−105°
105°
−10
−120°
120°
−135°
0
−15°
0°
15°
30°
−45°
60°
135°
189
45°
−60°
60°
−75°
75°
−90°
90°
−20
−105°
105°
−10
−120°
120°
−135°
0
135°
−150°
150°
10165°
−165°±180°
−150°
150°
10165°
−165°±180°
(e)
(f )
Figure 6.11: Measured co- and cross-polarization and simulated co-polarization gain
patterns in the azimuth plane (x-z plane) for different bias conditions:
(a)Vvar =15V, (b)Vvar =9.5V, (c)Vvar =7V, (d)Vvar =6.5V, (e)Vvar =5V,
(f)Vvar =3.5V. Solid line: measured co-polarization, dashed line: measured
cross-polarization, dash dot line: simulated co-polarization.
6.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS
190
gain and side-lobe levels. This can be attributed to two main factors; first of all, one
can clearly see from Fig. 6.10 that the antenna array is not fully symmetric around the
y-z plane, due to the tapering of the feed line and due to having a single input/output
port. Secondly, as indicated by Fig. 6.9, the interstage phase shifters do not have the
exact same insertion and reflection losses for both positive and negative phase shifts.
Consequently, this would lead to different values for the gain and side-lobe levels.
Figure 6.11 also compares the measured co-polarization gains with the results obtained from simulations. The figure shows good agreement between the simulated and
measured results for the different bias conditions. The good agreement between the
measurements and simulations was achieved by adopting a two step simulation process.
First, the patches were simulated together with the feed network using the full-wave
simulator of Agilent-Momentum. However, the tunable PRI/NRI phase shifters were
excluded from this simulation, and instead, each end of a λ/4 transformer was terminated with a port impedance equal to that of the phase shifter ZP S (i.e. 75Ω), and the
following λ/4 transformer was excited by another port with a 75Ω source impedance,
and so on. But to obtain the array’s radiation pattern, we still need to determine the
appropriate amplitudes and phases for the different ports. To obtain this information,
the measured S-parameters of the TL PRI/NRI interstage phase shifter, presented in
section 6.4.1, were used to obtain an accurate estimate of the phase shifter’s magnitude
and phase responses. One can use this information together with the power splitting
ratios at the three junctions of the feed network to calculate the amplitude and phase
excitation at each of the ports. These results were provided to the full-wave simulation
of the patches and the feed network to obtain the radiation patterns of the array. This
two step process was adopted here to obtain accurate simulation results, and more importantly, to avoid having to include the patches, the feed network, and the tunable TL
PRI/NRI phase shifters into one simulation. This separation is important since it was
not possible to obtain the radiation patterns using Agilent-Momentum in the presence
of the active lumped-element components, specifically, the varactors and the CMOS
TAIs. The simulation procedure which was used to obtain the radiation patterns of
the steerable antenna array is briefly summarized in Fig. B-2 in Appendix B.
The measured peak gain of the antenna array and the HPBW are plotted in Fig. 6.12
versus the scan angle. The proposed array has a relatively constant gain across its entire
49o scan angle range, with a peak gain of 8.4dBi and a maximum gain variation of 1.5dB.
6.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS
191
40
←
35
6
30
4
→
25
2
20
0
−30 −25 −20 −15 −10 −5
0
5 10
Scan angle θ (deg)
15
20
HPBW at 2.4GHz (deg)
Peak Gain at 2.4GHz (dBi)
8
15
25
Figure 6.12: Measured peak gain of the antenna array and the half-power beamwidth
versus the scan angle.
−30°
−15°
0°
15°
30°
−45°
45°
−60°
60°
−75°
75°
−90°
90°
−20
−105°
105°
−10
−120°
120°
−135°
0
135°
−150°
150°
10165°
−165°±180°
Figure 6.13: Measured co- and cross-polarization and simulated gain patterns in the
y-z plane. Solid line: measured co-polarization, dashed line: measured
cross-polarization, dash dot line: simulated co-polarization.
6.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS
192
S11< −10dB
BW = 70MHz
→
←
0
Antenna return loss S
11
(dB)
10
−10
−20
−30
−40
2
2.2
2.4
Frequency (GHz)
2.6
2.8
Figure 6.14: Input return loss, S11 , of the antenna array versus frequency for all the
different bias conditions given by Fig. 6.11.
This flat gain is a consequence of using the constant-impedance tunable TL PRI/NRI
interstage phase shifters employing both varactors and TAIs. The constant-impedance
feature is important to minimize reflections and also to minimize the mismatch in the
power level feeding the different antennas, since the power splitting ratios depend on
the phase shifters’ impedances. Figure 6.12 also shows that the HPBW changes from
a nominal value of 25o at broadside to a worst case of 29o for positive scan angles.
The measured co- and cross-polarization gain patterns of the antenna array in the y-z
plane are plotted in Fig. 6.13 together with the simulated co-polarization gain pattern.
These patterns were obtained with the array biased for broadside radiation.
Return Loss
Figure 6.14 shows the measured input return loss of the antenna array, S11 , for all the
different bias conditions given by Fig. 6.11. Across the entire 49o scan angle range the
antenna array return loss changes from a best case of -24dB to a worst case of -10dB.
This low return loss is a consequence of combining the use of varactors and TAIs to
design the constant-impedance tunable PRI/NRI interstage phase shifters. However,
the variation in the value of the antenna array return loss for different scan angles can
6.4. PHYSICAL IMPLEMENTATION AND EXPERIMENTAL RESULTS
30
193
10
→
5
−5
p
0
→
−10
−10
θ = ±2o
BW = 0.3GHz
←
−15
←
−20
−20
−30
−40
Peak Gain G (dBi)
0
10
p
Main Lobe Angle θ (deg)
20
−25
2.1
2.2
2.3
2.4
2.5
Frequency (GHz)
2.6
2.7
−30
Figure 6.15: Beam squinting characteristics: antenna array main-lobe angle, θp , and
the peak gain, Gp , versus frequency.
be attributed to two main factors; first, as indicated by Fig. 6.9 the input impedance
of the interstage phase shifters slightly varies for different phase shifts. Another source
of variation for the reflection coefficient of the antenna array is the mutual coupling
between the antenna array elements, as typically characterized by the active reflection
coefficient. However, this design uses alternating patch antennas which minimizes the
coupling between the adjacent array elements.
Figure 6.14 also shows that the return loss of the array is less than -10dB across a
bandwidth of 70MHz, which corresponds to a fractional bandwidth of approximately
3%. The relatively small bandwidth of the proposed design, is attributed to the narrowband characteristics of the patch antennas and can be extended by using a more broadband antenna element.
Beam Squinting
To demonstrate the low beam squinting capability of the proposed series-fed antenna
array, the array was biased to produce its main beam at the broadside direction for
the design frequency (2.4GHz). Then the frequency of the transmitter was swept
6.5. ANTENNA ARRAY LINEARITY
194
from 2 to 2.8GHz, and for each frequency point the co-polarization gain pattern was
measured, and these results were used to find the angle of the main lobe, i.e. the peak
gain angle θP , and the corresponding peak gain Gp . The resulting main lobe angles
and peak gains are shown in Fig. 6.15 versus the transmitter frequency. Figure 6.15
shows that the angle of the main beam, θp , remains within ±2o across a relatively wide
bandwidth of 0.3GHz, confirming that the beam squinting is low within this bandwidth.
To be precise, the beam squints by an angle of 1.3o for each 100MHz change in the
input frequency around the 2.4GHz design frequency, which, as mentioned earlier, is
due to the small group delay of the TL PRI/NRI phase shifters used in the design
of the series-fed array. The beam squinting can also be estimated from Eq.(A-3) in
Appendix A. The value of the group delay, Tgd , of the TL PRI/NRI phase shifters can
be obtained by evaluating the derivative of the measured phase responses in Fig. 6.8.
For the broadside case, the measured group delay at 2.4GHz is 0.5ns. Using this value
for Tgd , the theoretical expression of Eq.(A-3) results in an estimated beam squinting
of 1.29o /100MHz. This shows the very good agreement between the theoretical and
measured beam squinting, as well as the accuracy of Eq.(A-3).
Also, Fig. 6.15 shows the measured peak gain Gp versus the transmitter frequency.
The peak gain drops at a faster rate compared to the changes occurring in the main
lobe angle θp . This, however, is attributed to the narrow band characteristics of the
patch antennas, and can be solved by using more wide band antenna elements.
6.5 Antenna Array Linearity
Combining the use of the varactors and the 0.13µm CMOS TAIs to build the TL
PRI/NRI interstage phase shifters allowed increasing the scan angle range as opposed
to a varactor-based implementation [98–100]. Furthermore, tuning both the inductance
and capacitance allowed the antenna array to achieve a low return loss and maintain
a relatively flat gain response across this wide scan angle range. However, using these
active components imposes limitations on the antenna array’s linearity, especially since
the CMOS TAIs operate from a 1.5V supply voltage. To this end, the TAIs have been
designed to achieve good linearity by selecting appropriate transistor sizes and bias
points, and the linearity performance of the TAIs was reported in chapter 3.
To characterize the linearity of the proposed antenna array, the setup shown in
6.5. ANTENNA ARRAY LINEARITY
195
Antenna Anechoic
Chamber
TX:
Antenna array
RX:
Horn Antenna
RF signal
sources
f1
f2
+
RF signal
combiner
Agilent E4403B
Spectrum Analyzer
~6m
Figure 6.16: Experimental setup used to characterize the linearity of the steerable antenna array.
Horn output power Pout (dBm)
−30
−35
−40
−45
−50
P1−dB = 4.54dBm
−55
−60
−15
−10
−5
0
5
Array input power P (dBm)
in
10
Figure 6.17: Measured output power, Pout , of the horn antenna at 2.4GHz versus the
antenna array input power Pin .
6.5. ANTENNA ARRAY LINEARITY
196
−30
Horn output power (dBm)
−40
−50
P
out
at f
1
−60
−70
−80
Pout at 2f1−f2
IIP3 = 8.85dBm
−90
−100
−110
−15
−10
−5
0
Array input power (dBm)
5
10
Figure 6.18: Measured horn output power at the fundamental frequency f1 and at thirdorder intermodulation frequency 2f1 − f2 versus the antenna array input
power.
Fig. 6.16 was used. The antenna array was used as a transmitter, and a standard horn
antenna was used as a receiver. For the IIP3 measurement, two input tones at f1 and
f2 were applied to the antenna array though an RF signal combiner. On the other
hand, for the 1-dB compression point measurement, only one input tone was required,
and hence the RF signal combiner was removed. For both measurements, the received
signal by the horn antenna was detected using a spectrum analyzer to measure the
power at the different frequency components.
A single tone at 2.4GHz was used for the 1-dB compression point measurement,
and the input signal power was swept from -15dBm to 10dBm. Figure 6.17 shows the
measured output power Pout , received by the horn antenna, versus the input power
of the antenna array Pin . The measured results shows that the output power of the
antenna array reaches its 1-dB compression point at 4.5dBm, which corresponds to a
1.1Vpp signal swing at the antenna array input. Note that, not all of this signal swing is
seen at the TAI input port, as part of the input power is radiated by the first patch.This
points out the fact that the linearity of the proposed antenna array is mainly limited by
the low supply voltage of the CMOS TAI chips, as it sets a limit on the maximum peakto-peak signal swing at the TAI input port. For the IIP3 measurement the antenna
6.6. DISCUSSION AND COMPARISON
197
array is used to transmit two tones f1 and f2 at 2.4GHz and 2.41GHz, respectively,
and the intermodulation products in the received signal are analyzed. The frequency
separation was selected to put the two tones and their third-order intermodulation
products within the antenna array bandwidth. The measured output power at the
fundamental frequency f1 and at the third-order intermodulation product at 2f1 − f2
are plotted in Fig. 6.18 versus the input power level. By extrapolating the measured
results, one can show that the antenna array achieves an IIP3 of 8.8dBm.
6.6 Discussion and Comparison
In the fabricated prototype of the steerable antenna array, the varactors’ and the TAIs’
control voltages going to each of the interstage phase shifters are supplied manually
in order to achieve the desired scan angle. However, if this steerable array is used in
a practical transceiver, a look-up table together with multiple DACs can be used to
set the control voltages for each interstage phase shifter according to a single control
voltage. Here, one can see the importance of having identical interstage phase shifters,
as all the stages can share a single control voltage. Furthermore, the look-up tables
and the DACs can be integrated on the same die with the TAI circuit, which is one of
the main advantages of using a standard CMOS technology for the TAIs as opposed
to using other high ft technologies such as GaAs.
0
2.9λo ×1.35λo
0
1.55λo ×0.49λo (Ant. PCB)
Ave. power dissipation
Size
o
4.26λo ×0.33λo
0
18V
N/A
-6dB⇒-12.5dB
–
-5.5dB
22 ⇒35
o
13dB
18dBi
-39 ⇒+21
o
o
1.81λo ×0.57λo
450mW@1.5V
15V
3%
-10dB⇒-24dB
-14.7dB
-10dB
25o ⇒29o
1.5dB
8.4dBi
-27o ⇒+22o
2.4GHz
√
√
3.33GHz
4 Patches
√
This work
30 cell Leaky-Wave
√
[101]
This is based on the ability to electronically scan in both directions off the broadside, i.e. without physically switching the input and
terminating ports.
b
Gain variation is defined here as the change in the peak gain across the entire scan angle range.
c
Bandwidth measurement criterion: S11 <-10dB across the entire scan angle range. Bandwidth was not reported for the design of [101]
since S11 >-10dB for some of the reported scan angles.
a
30V
+ 0.31λo ×0.16λo (PS PCB)
4.6%
3.5V
Fractional bandwidth
1.02%
-18dB⇒-22dB
-13dB⇒-17dB
Return loss (S11 )
Max control voltage
-12dB
–
Rel. cross-pol.
c
-10dB
-9dB
Rel. side-lobe
–
0.4dB
24
o
11.3dBi
+10 ⇒+32
o
HPBW
Gain variation
–
–
Max gain
b
0 ⇒+30
o
5.8GHz
o
2.45GHz
Electronic scan-angle range
Operating frequency
X
5 Patches
√
[99, 100]
X
o
X
Single PCB impl.
Broadside scanning
4 Patches
Antenna elements
a
[98]
Specification
Table 6.2: Comparison Between The Proposed Steerable Patch Array And Other Published Series-Fed Steerable
Antenna Arrays.
6.6. DISCUSSION AND COMPARISON
198
6.6. DISCUSSION AND COMPARISON
199
Table 6.2 summarizes the performance of the proposed electronically steerable patch
array with other series-fed steerable arrays presented in the literature [98–101]. The
proposed design is capable of centering its radiation about the broadside direction as
opposed to the designs in [98–100], which can only achieve this by physically switching
the input and terminating ports. Furthermore, the proposed antenna array achieves a
much wider electronic scan-angle range compared to the designs presented in [98–100].
This is due to the use of both varactors and TAIs to design the interstage phase
shifters. To the author’s knowledge, the proposed antenna array is the first resonant
antenna-element structure that demonstrates electronic beam steering utilizing tunable
PRI/NRI phase shifters. Consequently, this series-fed design is capable of centering
its radiation at the broadside direction without the need for physically switching the
input and terminating ports. Moreover, in this PRI/NRI-based design, the compact
size of the TL PRI/NRI phase shifters allows them to fit between the antenna elements,
resulting in a compact, planar, PCB implementation. Although the leaky-wave design
in [101] achieves a wider scan angle range compared to the proposed resonant antenna
design, the proposed design has a relatively flat gain and HPBW across its entire scan
angle range. On the other hand, the leaky-wave design in [101] has very large variations
in both gain and HPBW as its beam is steered. In addition, the proposed antenna array
has a much lower relative side-lobe level and input return loss across its entire scan
angle range compared to the design in [101].
The idea of minimizing beam squinting by using PRI/NRI phase shifters for the feed
network of series-fed antenna arrays was originally proposed in [103]. Following that,
this principle was demonstrated in [6, 104] for a microstrip series-fed dipole antenna
array, and then in [105, 106] for a coplanar strip-line leaky-wave antenna array. Table
6.3 summarizes the achieved beam squinting by the proposed antenna array and other
published designs in the literature. It is worth mentioning that achieving a lower
beam squinting is more challenging at lower frequencies, as evident from Eq.(A-3) in
Appendix A. The beam squinting reported in the Table 6.3 is defined as the variation in
the main beam angle in degrees for a 100MHz change in the frequency centered around
the operating frequency. Compared to the other designs, the proposed design achieves
the lowest beam squinting. However, to be fair, note that in the proposed design, the
slope of the main beam angle, θp , increases beyond the 300MHz bandwidth, which
is evident from Fig. 6.15. Nonetheless, this should not be a big concern since the
6.6. DISCUSSION AND COMPARISON
200
Table 6.3: Comparison Between The Measured Beam Squinting Of The Proposed Array
And Other Published Antenna Arrays.
Design
Array type
Squintinga
Oper.
(deg/100MHz)
freq.
[100]
Series-fed patch array
9.5o
5GHz
[101]b
Leaky-wave array
8o
3.3GHz
o
[104]
Series-fed dipole array 5.7
[106]
Leaky-wave array
3.1o
5GHz
This work
Series-fed patch array
1.3o
2.4GHz
5.2GHz
a
Beam squinting is reported as degrees/100MHz variation in frequency centered at the operating
frequency.
b
For this design, the beam squinting is theoretically estimated by differentiating Eq.(10) in [101].
This is carried-out using the extracted parameters provided in Table I of [101] at a varactor voltage
of 5V.
bandwidth of the proposed design is limited to 70MHz by its input impedance.
The 1-dB compression of the proposed antenna array, as it stands, makes it capable
of handling the transmit power for only short range wireless devices. For example it,
can be used for wireless devices using Bluetooth or ZigBee. One potential solution
to extend the power handling capability of the proposed antenna array is to couple
the input signal to the TAI circuits using an on-chip transformer that steps down the
voltage swing by the turns ratio. The corresponding increase in the TAI input current
swing can be accommodated by increasing the TAI’s bias currents. This, however, will
increase the value of the TAI inductance with the square of the turns ratio. But this
could be accounted for during the design of the TAI circuit. A related approach has
been recently proposed in [107] to couple the outputs of four CMOS power amplifiers
to achieve a higher voltage swings than that allowed at the drain of each transistor
before breakdown occurs.
As described in chapter 3, noise is one of the critical performance limits which should
be quantified for TAI-based applications. This was carried out for the 2-port phase
shifters in chapter 4 and the 4-port coupler in chapter 5. However, antennas converts
electrical signals into electro-magnetic radiation and vise versa. Therefore, from an
6.6. DISCUSSION AND COMPARISON
201
electrical point of view, antennas can be considered 1-port devices. To the author’s
knowledge, there is no standard procedure for the experimental characterization of the
noise performance of active antennas. However, it is worth mentioning that, in the
proposed steerable antenna array, the effect of the added noise generated by the TAIs
can be counterbalanced, from a system’s point of view, by having a highly-directive
antenna. This highly-directive antenna, when compared to an omni-directional one,
would result in a higher signal to noise and interference ratio, and consequently in a
lower bit error rate since it minimizes the effect of interference with undesired signals.
To know which one of the two effects would dominate, and determine if using TAIs
improves the the overall performance requires knowledge of the environment in which
the antenna is used and is outside the scope of this thesis.
CHAPTER
7
Conclusion
T
his chapter summarizes the thesis and outlines its main contributions. In addition,
some areas are suggested for future research.
7.1 Summary
This thesis presented the design of RF CMOS TAIs and their applications towards
the design of RF metamaterial-based tunable phase shifters, directional couplers, and
series-fed steerable antenna arrays for 2.4GHz ISM band applications. The design of
the CMOS TAIs was based on a modified gyrator-C architecture utilizing a feedback
resistance, which allows independent control over the inductance and quality factor.
The TAI was fabricated in the 1.5V, 0.13µm CMOS process, and its inductance can
be tuned from 0.93nH to 2.7nH at 2.4GHz, with a peak-Q of 100 across the entire
inductance tuning range. Furthermore, the Q of the TAI can be tuned from a value of
10 to 200 at 2.4GHz with less than 6.7% variation in its inductance.
Chapter 4 presented a variety of implementations for bi-directional phase shifters
utilizing varactors and TAIs. The focus was directed more towards PRI/NRI phase
shifters, which are capable of achieving positive, negative and zero phase shifts without
202
7.1. SUMMARY
203
going through an entire 360o rotation. Hence, they have the capability to achieve low
group delays compared to standard low-pass or high-pass phase shifters, which is a
necessary feature to minimize the beam squinting in series-fed antenna arrays. Both
printed and 0.13µm CMOS, fully-integrated implementations were presented. The former synthesizes the PRI section using microstrip TLs, whereas the latter replaces the
TL sections with lumped L−C sections; thus, allowing for a single MMIC implementation. Compared to other implementations having only one tunable element, using varactors and TAIs extended the phase tuning range and at the same time maintained the
input and output matching of the phase shifters. The TL PRI/NRI phase shifter presented in this thesis achieved an electronically tunable phase of -40o to +34o at 2.5GHz
with less than -19dB return loss from a single stage occupying 10.8mm×10.4mm. On
the other hand, the MMIC PRI/NRI phase shifter achieved a phase of -35o to +59o at
2.6GHz with less than -19dB return loss from a single stage occupying 550µm×1300µm.
Furthermore, a passive fully-integrated PRI/NRI phase shifter was presented to address some of the drawbacks of the active designs (DC power consumption, noise, and
linearity) by eliminating the TAI and using instead a shunt varactor. The resulting
topology still exhibits phase compensation properties, which allows one to center its
phase response around the zero-degree mark while having a small group delay. Furthermore, it is also capable of maintaining the phase shifter matching. The passive
MMIC PRI/NRI phase shifter achieved an electronically tunable phase from -25.5o to
27o at 2.6GHz, from a single stage, with better than -21dB return loss across the entire
tuning range, while occupying an area of 700µm×1300µm.
In chapter 5, a compact, metamaterial-inspired, highly-reconfigurable directional
coupler was presented. The coupler was implemented in a standard 0.13µm CMOS
process and operates from a 1.5V supply. A lumped-element approach is used to
build the directional coupler, which makes it possible to integrate the entire coupler
onto a single MMIC. The MMIC coupler occupies an area of 730µm×600µm, which
is much smaller compared to printed designs operating at the same frequency range.
The MMIC coupler is based on the high-pass architecture and utilizes both varactors
and tunable active inductors, which allows simultaneous electronic control over the
coupling coefficient as well as the operating frequency of the coupler, while insuring a
low return loss and a very high isolation. Furthermore, the symmetric configuration
of the coupler allows it to electronically switch from forward to backward operation
7.2. CONTRIBUTIONS
204
by simply exchanging the bias voltages applied across the varactors. The different
modes of operation of the proposed MMIC coupler were experimentally verified, and
the measured results show that the coupler is capable of achieving a tunable coupling
coefficient from 1.4dB to 7.1dB, while maintaining the isolation higher than 41dB. The
MMIC coupler is also capable of operating at any center frequency over the 2.1GHz3.1GHz frequency range with higher than 40dB isolation. The linearity of the proposed
MMIC coupler was experimentally characterized.
Chapter 6 of this thesis presented a planar electronically steerable series-fed patch
array for 2.4GHz ISM band applications. The proposed steerable array used the zerodegree tunable TL PRI/NRI phase shifters to center its radiation about the broadside direction and allow scanning in both directions off the broadside. Also, using the
PRI/NRI phase shifters minimizes the squinting of the main beam across the operating
bandwidth. The feed network of the proposed array used λ/4 impedance transformers.
This allows using identical interstage phase shifters, which share the same control voltages to tune all stages. Furthermore, using the impedance transformers in combination
with the CMOS-based constant-impedance TL PRI/NRI phase shifters guarantees a
low return loss for the antenna array across its entire scan angle range. The antenna
array was fabricated, and is capable of continuously steering its main beam from -27o
to +22o off the broadside direction with a gain of 8.4dBi at 2.4GHz. This was achieved
by changing the varactors’ control voltage from 3V to 15V. Across this 49o scan angle
range, the array return loss is less than -10dB across a bandwidth of 70MHz, and the
side-lobe level is always 10dB lower than the main lobe. Furthermore, the proposed
design achieves very low beam squinting of 1.3o /100MHz at broadside and a 1-dB
compression point of 4.5dBm.
7.2 Contributions
The main contributions of this thesis are summarized as follows:
1. Development of a novel generalized method, based on the gyrator-C architecture,
to design grounded TAIs with independent L and Q tuning capability.
2. Evaluation of the performance of the proposed modified gyrator-C architecture,
by presenting the design and experimental characterization of a grounded 0.13µm
CMOS TAI.
7.3. FUTURE WORK
205
3. Design and implementation of four novel wide tuning range phase shifters,
a) Fully-integrated, tunable, active high-pass phase shifter.
b) Tunable, active, TL PRI/NRI phase shifter.
c) Tunable, active, MMIC PRI/NRI phase shifter.
d) Tunable, passive, MMIC PRI/NRI phase shifter.
4. Design and implementation of a novel highly-reconfigurable directional coupler,
which is simultaneously capable of operating with a variable coupling coefficient
and a variable center frequency. As well as switching the input power among the
through and isolated ports.
5. Design and implementation a 4-element, PCB, electronically steerable, series-fed
antenna array. The array is capable of centering its radiation about the broadside
direction, and achieves very low beam squinting by utilizing the TL PRI/NRI
phase shifters.
7.3 Future Work
There are many areas that can be further investigated. First of all, the generalized
gyrator-C architecture with resistive feedback, which was presented in this thesis, can
be applied to the different TAI circuit topologies discussed in chapter 2 to obtain a
variety of new TAI designs with independent L and Q tuning capability.
Secondly, metamaterials is a relatively new research area. In this thesis only two of
its applications were extensively investigated; phase shifters and directional couplers.
However, there is a broad range of different applications that can use metamaterial
concepts and combine them with the capabilities offered by active circuits. For instance,
one may replace the fixed capacitors and inductors in the series power divider presented
in [13] to make it operate at an arbitrary frequency. Also, TAIs and/or varactors can be
used to electronically control the resonance frequency of an antenna. For example, this
can be used to electronically tune the resonance of a planar inverted F antenna (PIFA),
enabling the design of re-configurable antennas for multi-standard applications. The
series-fed patch array presented in this thesis can be very easily modified to achieve a
wider bandwidth by replacing the narrow-band patch antennas with more wide-band
antenna elements, such as stacked patches. Another possibility is to replace the bulky
patch antennas with small metamaterial-based antennas [19, 20].
7.3. FUTURE WORK
206
Furthermore, another area that has not been fully investigated yet is the integration
of the entire phased antenna array transceiver on-chip. Scaling-up the operating frequency to the millimeter-wave region allows shrinking the antenna dimensions and the
inter-element distance of the array making it feasible to fit onto a single MMIC. One
such attempt was reported in [108], where a 16-element 30-50GHz transmit phased array is integrated with the beam forming network on a single chip. However, in order to
scale-up the operating frequency appropriate technology nodes with higher transistor
ft s would be required. For instance, the 30-50GHz design in [108] is fabricated in a
0.18µm SiGe BiCMOS technology, which offers transistors with peak ft s of 155GHz.
Another example of frequency scaling is the 12.7GHz and 30GHz metamaterial phase
shifter designs which were recently presented in [109] and [110, 111] respectively. Since
the phase shifters published in [109–111] mostly relay on passive devices such high operating frequencies were possible to achieve using a standard 0.18µm CMOS technology.
The majority of the circuits presented in this thesis use the TAI circuit, which will become the design bottleneck when it comes to scaling-up the operating frequency. The
0.13µm CMOS technology provides transistors with peak ft s close to 80GHz, which
indicates that there should be some room for speed improvement. However, note that
other specifications such as the inductance tuning range or the power handling capability might be the limiting factors that determine the speed of the TAI circuit in
a specific technology node. In this case, migrating to new technologies with smaller
feature sizes and higher ft s would be beneficial.
In addition, techniques to extend the linearity and noise limitations of TAIs have
yet to be investigated. One potential solution to extend the power handling capability
of TAIs is by coupling the input signal to the TAIs using an on-chip transformer that
steps down the voltage swing by the turns ratio. The corresponding increase in the
TAI input current swing can be accommodated by increasing the TAI’s bias currents.
This, however, will increase the value of the TAI inductance with the square of the
turns ratio, but could be accounted for during the design of the TAI circuit. A similar
approach was proposed in [107] to couple the outputs of four CMOS power amplifiers
to achieve a higher voltage swing than that allowed at the drain of each transistor
before breakdown occurs.
Also, a detailed sensitivity analysis of the TAI, and the subsequent circuits presented
here using the TAI, would be necessary for determining whether these circuits are
7.3. FUTURE WORK
207
sufficiently robust for use in commercial applications. Any limitations, once identified,
could be the subject of further research for developing new tuning and compensation
techniques.
Finally, the contribution of this thesis has been to establish the feasibility of metamaterial-inspired circuits for wireless applications. This work has demonstrated the
strengths of these circuits in enhancing tunability and matching. At the same time,
this work has characterized to some extent, some of the limitations of these circuits in
terms of noise and distortion. In doing so, this work has laid the foundation for future
research aimed at identifying specific, wireless applications that can benefit from these
circuits.
Appendix A: Beam Squinting Analysis For
The Proposed Series-Fed Antenna Array
T
his appendix analyzes the relationship between the squinting of the main beam
of the proposed series-fed alternating antenna array and the group delay of the
interstage phase shifters. The scan angle, θ, of the series-fed antenna array having an
inter-element spacing dE can be expressed as:
θ = sin−1 (−c ×
π + φT L + φP S
),
ωdE
(A-1)
where c is the speed of light, φT L is the interconnecting λ/4 TLs phase shift, and φP S
is the phase shift of the interstage phase shifters. For broadside radiation, the antenna
elements of the alternating architecture should be fed out-of-phase, i.e. φT L = −π and
φP S = 0o . To evaluate the beam squinting around the broadside direction, Eq.(A-1) is
used to find the derivative of θ with respect to frequency. For small variations in the
scan angle, one can approximate the rate of change of the scan angle as:
c π + φP S Tgd
dθ
≈
(
+
),
dω
dE
ω2
ω
(A-2)
where Tgd is the group delay of the interstage phase shifters. Evaluated at broadside,
208
Appendix A: Beam Squinting Analysis
209
i.e. φP S = 0o , the expression of Eq.(A-2) results in the following:
¯
Tgd
dθ ¯¯
c π
( 2+
).
≈
¯
dω broadside dE ω
ω
(A-3)
Hence, feeding the antenna elements with interstage phase shifters that have small
group delays will result in less beam squinting.
Appendix B: Simulation Procedure
T
his appendix presents two flow charts to demonstrate the method used to simulate
and consequently design the TL PRI/NRI metamaterial phase shifter and the
steerable antenna array. Figure B-1 shows the procedure used to simulate the single
stage and the 2-stage TL PRI/NRI metamaterial phase shifters. Whereas, Fig. B-2
shows the procedure used to obtain the simulated radiation patterns of the steerable
antenna array.
210
Appendix B: Simulation Procedure
211
Electromagnetic
simulations
Simulate the printed structure of the
TL phase shifter in Momentum ADS
(without varactors and TAI)
Experimental
characterization
TAI S-parameters files for
different bias conditions
(obtained from experimental
characterization)
Model the printed structure of the TL
phase shifter with a multi-port Sparameter file (using the ADS EM/
Circuit co-simulation tool)
SPICE models of discrete
varactors (obtained from
vendor)
Combine the S-parameters of TAIs with SPICE models of
the varactors and the S-parameters of the printed
structure of the TL phase shifter in ADS’s circuit simulator
Circuit
simulations
Obtain phase response,
insertion, and return loss of TL
metamaterial phase shifters
Figure B-1: Flow chart showing the procedure used to simulate the TL PRI/NRI metamaterial phase shifters.
Electro-magnetic
simulations
Simulate the feed network of the
steerable array together with the patch
antennas in Momentum ADS, but
without the PRI/NRI phase shifters
EM/Circuit co-simulations
plus measurements
Obtain the phase response,
insertion, and return loss of the
2-stage TL PRI/NRI
metamaterial phase shifters
Model the entire printed structure
with a multi-port S-parameter file
(using the ADS EM/Circuit cosimulation tool)
Combine the 2-stage PRI/NRI phase shifters with the Sparameters of the steerable array in ADS’s circuit
simulation, and obtain the antenna array’s return loss and
the maximum and minimum phase states.
Circuit
simulations
Using the information on the maximum and minimum
phase states to feed the input ports of the steerable array
with the appropriate signal amplitudes and phases in an
EM simulation to obtain the radiation patterns
Electromagnetic
simulations
Figure B-2: Flow chart showing the procedure used to simulate the steerable antenna
array.
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