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Integration issues associated with monolithic silicon -germanium microwave radar systems

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Integration Issues Associated with Monolithic
Silicon-Germanium Microwave Radar Systems
A Thesis
Presented to
The Academic Faculty
by
Jonathan P. Comeau
In Partial Fulfillment
of the Requirements for the Degree
Doctorate of Philosophy
in Electrical and Computer Engineering
Georgia Institute of Technology
December 2006
UMI Number: 3248676
Copyright 2007 by
Comeau, Jonathan P.
All rights reserved.
UMI Microform 3248676
Copyright 2007 by ProQuest Information and Learning Company.
All rights reserved. This microform edition is protected against
unauthorized copying under Title 17, United States Code.
ProQuest Information and Learning Company
300 North Zeeb Road
P.O. Box 1346
Ann Arbor, MI 48106-1346
Integration Issues Associated with Monolithic
Silicon-Germanium Microwave Radar Systems
Approved by:
Professor John D. Cressler, Advisor
School of Electrical and Computer
Engineering
Georgia Institute of Technology
Professor Madhavan Swaminathan
School of Electrical and Computer
Engineering
Georgia Institute of Technology
Professor Joy Laskar
School of Electrical and Computer
Engineering
Georgia Institute of Technology
Professor Dennis Hess
School of Chemical and Biomolecular
Engineering
Georgia Institute of Technology
Professor John Papapolymerou
School of Electrical and Computer
Engineering
Georgia Institute of Technology
Date Approved: October 2006
ACKNOWLEDGEMENTS
I would like to express my gratitude to all who have assisted me during the course of
my academic career.
I would like to thank my advisor, Dr. John D. Cressler, who has given me guidance
and reassurance during my time here at Georgia Tech. I am especially appreciative
of the amount of freedom he has extended to me over the years, in terms of research
topics and areas of investigation. It has greatly enhanced my experience as a graduate
student.
I am also very grateful to all of my committee members, Dr. Joy Laskar, Dr. John
Papapolymerou, Dr. Madhavan Swaminathan, and Dr. Dennis Hess. All have been
extremely generous in sharing their time and expertise during this process. I know
my work has improved significantly from their input and suggestions.
I would also like to thank Mark Mitchell, Tracy Wallace, and the Georgia Tech
Research Institute for their help and guidance during these past years. I am also
extremely grateful to Jazz Semiconductor and IBM Microelectronics, both of which
have allowed me access to their excellent technologies, which this work is based on.
I would also like to thank Dr. Sally Doherty, Dr. Clark T.-C. Nguyen, Dr.
Cherrice Traver, and Dr. Ekram Hassib. They are all responsible, in one way or
another, for my success and accomplishments in electrical engineering. I never would
have made it to Georgia Tech without their help and guidance over the years.
I would also be remiss, if I did not thank all of my colleagues at Georgia Tech. Special thanks to Matt Morton, Akil Sutton, Becca Haugerud, Ramkumar Krithivasan,
Joel Andrews, Lance Kuo, Yuan Lu, Bhaskar Banerjee, Sunitha Venkataraman, Curtis Grens, Laleh Najafizadeh, Zhenrong Jin, Tianbing Chen, QingQing Liang, Pete
iii
Kirby, and Bongim Jun.
I would also like to thank all of my family, especially my parents and sister, Phillip
Comeau, Penelope Comeau, and Alisa Comeau, for their support and encouragement
over the years. They have always been there for me, and I am truly grateful for the
love they have shown me during my life. I am also very grateful to Hong-Hsiang
(Harry) Kou, Ph.D., Maggie Kuo and Amy Kuo, who have also supported me during
my time here at Georgia Tech, and have welcomed me into their family as well.
Finally, I would like to thank my beautiful wife, Benita M. Comeau, for her
inspiration, support, and encouragement. I would not have returned to graduate
school had she not suggested it, and I surely would have quit several years ago had
she not been here with me.
iv
TABLE OF CONTENTS
ACKNOWLEDGEMENTS . . . . . . . . . . . . . . . . . . . . . . . . . .
LIST OF TABLES
LIST OF FIGURES
iii
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ix
SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii
1
2
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
1.1
Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
1.2
Objective of Work . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
1.3
Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
SIGE TECHNOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . .
4
2.1
Overview of SiGe Technology . . . . . . . . . . . . . . . . . . . . . .
4
2.2
Technology Limitations . . . . . . . . . . . . . . . . . . . . . . . . .
6
2.2.1
Active Device Tradeoffs . . . . . . . . . . . . . . . . . . . . .
7
2.2.2
Passive Performance . . . . . . . . . . . . . . . . . . . . . . .
8
2.2.3
Undesired Coupling . . . . . . . . . . . . . . . . . . . . . . .
9
Silicon-Germanium Technologies Under Investigation . . . . . . . . .
10
RADAR APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . .
13
3.1
Overview of Radar Systems . . . . . . . . . . . . . . . . . . . . . . .
13
3.2
X-Band Radar Applications . . . . . . . . . . . . . . . . . . . . . . .
15
3.2.1
SiGe X-Band Phased Array Radar Systems . . . . . . . . . .
16
K-Band Radar Applications . . . . . . . . . . . . . . . . . . . . . . .
18
3.3.1
SiGe K-Band Radar Systems . . . . . . . . . . . . . . . . . .
19
X-BAND PHASE SHIFTERS . . . . . . . . . . . . . . . . . . . . . .
23
4.1
Silicon Based Phase Shifters . . . . . . . . . . . . . . . . . . . . . .
23
4.2
Comparison of Technological Capabilities of MOS and HBT Phase
Shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
4.2.1
25
2.3
3
3.3
4
SiGe HBT Switch Design . . . . . . . . . . . . . . . . . . . .
v
4.2.2
CMOS Switch Design . . . . . . . . . . . . . . . . . . . . . .
30
4.2.3
Comparison of SiGe HBT and CMOS Switch Capabilities . .
36
4.2.4
Comparison of CMOS and HBT Based 4 Bit Digital Phase
Shifters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38
5-Bit SiGe HBT X-Band Phase Shifter . . . . . . . . . . . . . . . .
42
4.3.1
Measured Results . . . . . . . . . . . . . . . . . . . . . . . .
42
X-BAND DOWN-CONVERSION MIXER . . . . . . . . . . . . . .
46
5.1
Introduction to Down-Conversion Mixers . . . . . . . . . . . . . . .
46
5.2
Down-Conversion Mixer Circuit Design . . . . . . . . . . . . . . . .
48
5.3
Measured Performance . . . . . . . . . . . . . . . . . . . . . . . . .
48
5.4
Down-Conversion Mixer Figure-of-Merit . . . . . . . . . . . . . . . .
51
5.4.1
Conversion Gain . . . . . . . . . . . . . . . . . . . . . . . . .
52
5.4.2
Noise Figure and Linearity . . . . . . . . . . . . . . . . . . .
53
5.4.3
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . .
54
5.4.4
Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
55
5.4.5
Comparison to other Mixer Figures of Merit . . . . . . . . .
55
K-BAND UP-CONVERSION MIXER . . . . . . . . . . . . . . . .
57
6.1
Introduction to Up-Conversion Mixers . . . . . . . . . . . . . . . . .
57
6.2
Up-Conversion Mixer Circuit Design . . . . . . . . . . . . . . . . . .
58
6.3
Circuit Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . .
61
6.4
Measured Performance . . . . . . . . . . . . . . . . . . . . . . . . .
64
6.5
Performance Comparison . . . . . . . . . . . . . . . . . . . . . . . .
65
K-BAND POWER AMPLIFIER . . . . . . . . . . . . . . . . . . . .
68
7.1
Introduction to Microwave Power Amplifiers . . . . . . . . . . . . .
68
7.2
Benefits of the Cascode Architecture . . . . . . . . . . . . . . . . . .
68
7.3
SiGe Power Amplifier Design . . . . . . . . . . . . . . . . . . . . . .
72
7.4
Measured Results . . . . . . . . . . . . . . . . . . . . . . . . . . . .
74
7.5
Performance Comparison . . . . . . . . . . . . . . . . . . . . . . . .
79
4.3
5
6
7
vi
8
SUBSTRATE COUPLING . . . . . . . . . . . . . . . . . . . . . . . .
80
8.1
Introduction to Substrate Coupling for Silicon Based Technologies .
80
8.1.1
Overview of Substrate Modeling . . . . . . . . . . . . . . . .
81
Substrate Coupling Characterization . . . . . . . . . . . . . . . . . .
83
8.2.1
Substrate Measurements . . . . . . . . . . . . . . . . . . . .
84
8.2.2
Substrate Modeling . . . . . . . . . . . . . . . . . . . . . . .
86
8.3
Circuit Sensitivity to Substrate Noise . . . . . . . . . . . . . . . . .
88
8.4
Circuit-to-Circuit Coupling via the Substrate . . . . . . . . . . . . .
93
8.4.1
93
8.2
8.5
9
Case Study: PA to VCO Substrate Coupling at K-Band . . .
Summary of Substrate Coupling Concerns . . . . . . . . . . . . . . . 101
CONCLUSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
9.1
Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
9.2
Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
VITA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
vii
LIST OF TABLES
1
Characteristics of Jazz SiGe120 and IBM 8HP SiGe HBT BiCMOS technologies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
Summary of FCC Regulations for 24 GHz Vehicular Radar Applications
[33]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
3
Simulation Results for nMOS Switch Modeling. . . . . . . . . . . . . . .
32
4
Summary of nMOS and SiGe HBT Phase Shifter Performance. . . . . . .
39
5
Performance comparison of SiGe microwave down-conversion mixers . . .
51
6
Comparison of Reported X-Band SiGe Mixers Based on Proposed FigureOf-Merit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
56
7
Performance comparison of K-band up-conversion active mixers . . . . .
67
8
Performance comparison of silicon-based microwave power amplifiers. . .
77
9
Measured performance of microwave VCOs . . . . . . . . . . . . . . . . .
89
10
Coupling Results for Different Measurement Configurations for PA to VCO
Coupling Study . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
99
VCO Coupling Results when Injected Signal is Applied to the PA Output
99
2
11
viii
LIST OF FIGURES
1
Example of npn SiGe HBT device. . . . . . . . . . . . . . . . . . . . . .
4
2
Example of various HBT device options in a commercially available SiGe
HBT BiCMOS technology [13]. . . . . . . . . . . . . . . . . . . . . . . .
8
3
Cross sectional diagram of Jazz SiGe120 technology. . . . . . . . . . . . .
10
4
Cross sectional diagram of IBM 8HP technology. . . . . . . . . . . . . . .
11
5
Diagram of a general phased array radar system. . . . . . . . . . . . . .
15
6
Typical system of an X-band phased array radar incorporating T/R modules. 16
7
Potential applications for automotive short-range radar systems. . . . . .
19
8
Simplified block diagram of a 24 GHz phased array radar system reported
in [32]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
9
Simplified block diagram of 24 GHz radar system reported in [35]. . . . .
22
10
Block diagram of typical T/R module for X-band systems. . . . . . . . .
24
11
Block diagram of high-pass/low-pass phase shifter topology. . . . . . . .
25
12
Schematic of series-connected SiGe HBT SPDT X-band switches. . . . .
26
13
Simulation results for a SiGe HBT based series-connected SPDT switch
for varying IC bias currents. . . . . . . . . . . . . . . . . . . . . . . . . .
27
Simulation results for a SiGe HBT based series-connected SPDT switch
for varying emitter lengths. . . . . . . . . . . . . . . . . . . . . . . . . .
28
Overlay of measured and simulated S-parameters for the HBT based SPDT
switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29
Open-collector measurement results and corresponding emitter resistance
values of various high-speed 8HP HBT devices. . . . . . . . . . . . . . .
30
Schematic and equivalent circuit for series-connected nMOS SPDT X-band
switches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
Calculated S-parameters versus frequency for nMOS equivalent circuit,
with a Q = 20, varying RM , and a nominal design frequency of 10 GHz. .
34
19
Layout photo of nMOS devices for nMOS SPDT switch. . . . . . . . . .
35
20
Overlay of measured and simulated S-parameters for the MOS based SPDT
switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
36
Measured S-parameters for HBT SPDT switch and nMOS SPDT switch.
37
14
15
16
17
18
21
ix
22
Die photos of the HBT and nMOS 4-bit X-band phase shifters. . . . . .
39
23
Insertion loss for nMOS and SiGe HBT X-band 4-bit phase shifters. . . .
40
24
Compression point for nMOS and SiGe HBT X-band 4-bit phase shifters.
40
25
Absolute phase error for nMOS and SiGe HBT X-Band 4-bit phase shifters. 41
26
Noise Figure for nMOS and SiGe HBT X-Band 4-bit phase shifters. . . .
41
27
Die photo (4.1 x 2.4 mm2 ) of 5-bit X-band HBT phase shifter. . . . . . .
43
28
Insertion loss for 5-bit X-band HBT phase shifter. . . . . . . . . . . . . .
43
29
Phase shift for 5-bit X-band HBT phase shifter. . . . . . . . . . . . . . .
44
30
Example of Gilbert cell down-conversion mixer. . . . . . . . . . . . . . .
47
31
Die photo (1.2 x 1.2 mm2 ) and schematic of the X-band down-conversion
mixer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
48
Conversion gain, noise figure and RF port return loss for X-band downconversion mixer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
49
Output power versus input power and intermodulation distortion for the
X-band down-conversion mixer. . . . . . . . . . . . . . . . . . . . . . . .
49
34
Conversion gain versus LO power for the X-band down-conversion mixer.
50
35
Port-to-port isolation versus frequency for the X-band down-conversion
mixer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50
Die photo (1.0 x 1.0 mm2 ) and conceptual schematic of the SiGe K-band
up-conversion mixer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
59
37
Schematic of simulation template for IF stage simulations. . . . . . . . .
62
38
Simulation results comparing the performance of the IF stage of the present
work, to that of a standard differential pair, and a differential pair with
degeneration resistors. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
63
39
Return loss performance for the K-band SiGe up-conversion mixer. . . .
64
40
Upper side band conversion gain and LO to RF isolation for the upconversion mixer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
65
Output power and intermodulation power versus input power for the upconversion mixer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
66
Output spectrum for the K-band up-conversion mixer at the 1dB compression point for a 28 GHz output signal. . . . . . . . . . . . . . . . . .
66
Example of common emitter and cascode power amplifier architectures
with voltage biasing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
69
32
33
36
41
42
43
x
44
Output characteristics of common emitter and cascode architectures with
voltage biasing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
Simulated K-factor versus frequency for common emitter and cascode architectures biased for class-A operation. . . . . . . . . . . . . . . . . . .
71
46
Stability circles for common emitter class-A amplifier simulated at 1 GHz.
72
47
Schematic of the 24 GHz SiGe power amplifier. . . . . . . . . . . . . . .
73
48
Schematic cross-section of the thin-film microstrip transmission line. . . .
74
49
Die photo of the 24 GHz SiGe power amplifier (0.85 x 1.2 mm2 ). . . . . .
75
50
Output power and ICC versus input power for the 24 GHz power amplifier. 75
51
Gain and power added efficiency versus output power for the 24 GHz power
amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
76
Output power and intermodulation products versus input power for the
24 GHz power amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . .
77
53
S11 , S22 , and S21 versus frequency for the 24 GHz power amplifier. . . . .
78
54
Output characteristics for various biasing configurations for the 24 GHz
power amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
78
55
Conceptual layout of the substrate characterization test structure. . . . .
83
56
Measured S21 of the substrate characterization test structures. . . . . . .
85
57
Measured Y21 of the substrate characterization test structures. . . . . . .
85
58
Model for substrate characterization structure. . . . . . . . . . . . . . . .
86
59
Correlation between measured data and substrate model for S11 . . . . .
87
60
Correlation between measured data and substrate model for the magnitude
and phase of Y21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
88
Die photo of the substrate characterization structures with VCO designs,
and simplified circuit schematic of the inductor-based VCO. . . . . . . .
89
62
Spectrum photo and phase noise plot for the inductor-based VCO. . . . .
90
63
Spectrum photo and phase noise plot for the microstrip-based VCO. . . .
90
64
Spectrum plot of inductor VCO with -7 dBm of injected signal applied at
20 MHz offset from fOSC with Vcontrol =0. . . . . . . . . . . . . . . . . . .
91
Variation in coupled power present at the VCO output versus injected
power and frequency offset between oscillation frequency and injected frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
92
45
52
61
65
xi
66
Power coupled to the output of the inductor and the microstrip VCO
versus Vcontrol with injected signal 20 MHz offset from fOSC . . . . . . . .
93
Schematic of 24 GHz power amplifier and 23 GHz VCO fabricated on the
same die. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
95
Die photo of 24 GHz power amplifier and 23 GHz VCO fabricated on the
same die. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
96
69
Block diagram of set up for testing of VCO and power amplifier. . . . . .
96
70
Spectrum photo of VCO output when both the VCO and PA are operating
at the same time and on the same die. . . . . . . . . . . . . . . . . . . .
97
Spectrum photo of PA output when both the VCO and PA are operating
at the same time and on the same die. . . . . . . . . . . . . . . . . . . .
97
67
68
71
72
Coupled power measured at VCO output and PA output power versus
frequency offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
xii
SUMMARY
The desire for low cost X-band and K-band radar systems has fueled interest in monolithic silicon-germanium radar systems. These systems can leverage the
performance capabilities and cost savings of silicon-germanium technology, but must
also address several integration issues in order to become a viable solution for these
applications. This work will investigate some of these integration issues, focusing on
silicon-germanium circuits typically utilized in X-band and K-band radar systems, as
well as the potential for circuit-to-circuit coupling to occur in a silicon-based technology at these frequencies of operation.
Circuits that are not typically designed in silicon-germanium technologies, such as
phase shifters, high-linearity switches, and microwave power amplifiers will be investigated. Various topologies and implementations for these circuits will be analyzed and
discussed. Similarly, three port frequency conversion circuits, such as up-conversion
and down-conversion mixers, required for most radar or transceiver systems will also
be examined. Design tradeoffs for these circuits will be highlighted, primarily focusing on the coupling of undesired signals between adjacent blocks. Potential circuit
topologies which alleviate these coupling concerns will also be investigated.
The undesired coupling of signals between separate circuit blocks via the silicon
substrate (i.e. substrate coupling) will also be investigated. Measured results for
substrate characterization structures will be presented, along with a semi-physical
model for the substrate. Additional studies examining the potential for circuit performance degradation due to substrate noise, as well as circuit-to-circuit coupling via
the substrate, will also be presented.
xiii
CHAPTER 1
INTRODUCTION
1.1
Motivation
Since the birth of the transistor, scientists and engineers have worked diligently to
unleash its full potential by optimizing its structure and incorporating it strategically
into new designs and inventions. The ability to integrate several transistors onto a
single piece of silicon was accomplished in the late 1950s, opening the flood gates for
fully-integrated solutions. Since this discovery, the number of transistors fabricated
onto a single die has increased exponentially, and the complexity, performance, and
frequency of operation of the systems based on these transistors has also increased.
These technological advancements have inspired years of research focused on device
optimization and monolithic solutions.
Silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) technology is
a by-product of these efforts, developing into a mature technology utilized by companies all over the world. Silicon-germanium has also become the popular technology
of choice in wireless systems, ranging from military radar applications to commercial
point-to-point communication systems. SiGe HBT technology provides high performance devices with the ability to integrate multiple circuit blocks or systems onto a
single die. This capability translates into a reduction of system size and an increase
in cost savings. Phased array radar systems have also become quite popular as of
late, due to the benefits of antenna arrays and advances in monolithic technologies
needed to support them. The combination of a relatively low-cost high-performance
technology, such as silicon-germanium, with new system design methodologies for
phased array radar systems, enables a multitude of new applications and system
1
improvements.
However, certain obstacles must be overcome in order to achieve this enhanced
level of system integration for wireless applications. Components traditionally designed in III-V technologies (phase shifters, limiters, power amplifiers, etc.) forces
designers to investigate the limitations of the technology, as well as investigate new
system architectures and non-standard design topologies. Also, as the number of
components and blocks that are integrated onto a single die increase, so does the potential for circuit-to-circuit coupling and circuit-to-circuit loading. These challenges
are further exasperated by the desire to design and utilize these wireless systems at
higher frequency bands of operation.
1.2
Objective of Work
This work investigates integration issues associated with monolithic silicon-germanium
radar systems for military (8-12 GHz) and automotive (24 GHz) applications. The design and implementation of critical circuits, such as phase shifters, power amplifiers,
and mixers will be investigated, along with the system level considerations associated with these components. Investigations into substrate coupling associated with
these BiCMOS technologies and the potential for circuit-to-circuit coupling via the
substrate will also be addressed.
1.3
Contributions
The following items represent the contributions made by this work.
1. Analysis and comparison of high-pass/low-pass 4-bit digital X-band CMOS and
HBT based silicon phase shifters (Chapter 4).
2. Demonstration of a high-linearity 5-bit digital X-band HBT based phase shifter(Chapter
5, also published in [1]).
2
3. Demonstration of an X-band down-conversion mixer achieving a balanced set
of performance metrics(Chapter 5, also published in [2]).
4. Proposal of a new down-conversion mixer figure-of-merit that captures the
mixer?s gain, noise figure, linearity, and isolation capabilities(Chapter 5, also
published in [2]).
5. Analysis and design of a high-linearity K-band up-conversion mixer based on a
series-connected common-base triplet (Chapter 6, also published in [3]).
6. Analysis and design of a 20 dBm, 14 % PAE, 24 GHz SiGe HBT power amplifier
(Chapter 7, also published in [4]).
7. Investigation of substrate coupling, substrate-to-circuit coupling, and circuitto-circuit coupling, associated with a commercially available SiGe BiCMOS
technology (Chapter 8, also published in [5]).
3
CHAPTER 2
SIGE TECHNOLOGY
2.1
Overview of SiGe Technology
Silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) technology is based
on the utilization of a SiGe alloy for the base region of a bipolar junction transistor
(BJT) (Figure 1). This SiGe alloy will have a smaller bandgap than the silicon used
for the emitter and collector terminals, allowing for bandgap engineering in the design of the transistor [6]. The amount of germanium introduced into the device can
be varied across the base region creating a gradient induced drift field, and further
optimizing the structure [6]. The combination of this drift field and the bandgap
offsets present in the device allow for significant enhancements in overall transistor
performance.
The speed of a device is typically quantified by its maximum unity gain cut-off
frequency (fT ) or maximum oscillation frequency (fmax ). The fT of a SiGe HBT
operated in low-injection (i.e. the changes in the carrier concentration are much less
than the majority carrier concentration) can be expressed as
Figure 1: Example of npn SiGe HBT device.
4
fT
▓
│?1
1 kT
WCB
=
(Cte + Ctc ) + ?b + ?e +
+ rc Ctc
,
2? qIC
2vsat
(1)
where Ctc and Cte are the collector-base and emitter-base depletion capacitances
respectively, ?e is the emitter charge storage delay time, ?b is the base transit time, k
is Boltzmann?s constant, T is temperature, q is electronic charge, IC is the collector
current, vsat is the electron saturation velocity, rc is the dynamic collector resistance,
and WCB is the width of the collector-base space charge region [6]. The introduction
of a graded germanium profile into the base region of a typical BJT creates a built-in
drift electric field, which accelerates the electrons in the base and reduces the ?b of
the device[6]. The ?e of the device is also reduced due to the introduction of this
silicon-germanium alloy. However, the reduction of ?e correlates to the valence band
offset between the emitter and base regions created by the Si to SiGe interface [6].
Clearly, the reduction of the ?b and ?e of a HBT device will improve its frequency
response capabilities for this region of operation.
These improvements in fT also benefit the fmax of the device, which can be expressed as
fmax =
r
fT
,
8?Cbc rb
(2)
where Cbc is the base-collector capacitance and rb is the parasitic base resistance of
the device. Assuming all of the other parameters remain constant, the fmax of the
device should increase as the fT is increased. However the fmax of a SiGe HBT can
be further improved from lateral scaling of the device, which results in a reduction of
rb [7]. The leveraging of these physical attributes associated with silicon-germanium
technology has enabled SiGe HBTs to achieve fT ?s and fmax ?s greater than 300 GHz
[8], giving the technology a decided advantage over a pure silicon solution.
The noise performance (or sensitivity) of a BJT also benefits from the inclusion
5
of this SiGe alloy. The minimum noise figure (N Fmin ) of a SiGe HBT can be approximated as
N Fmin
1 p
= 1 + + 2gm rb
?
s
1
+
?
▓
f
fT
│2
,
(3)
where gm is the transconductance of the device equal to qIC /kT , f the frequency of
operation, and ? the current gain [6]. The bandgap offset between the emitter and
base regions of the device (due to the Si-SiGe interface) will increase the current gain
of the transistor, correlating to lower noise figure performance [6]. The noise figure
of the device will also benefit from lateral scaling, which will reduce its parasitic base
resistance (rb ). However, what is of even more consequence, is the increase in fT
mentioned earlier. As seen in equation 3, this increase in frequency response enables
the transistor to maintain low-noise performance at high frequencies of operation,
which is obviously critical for microwave applications.
Another attractive feature of silicon-germanium technology is its ability to be fabricated on silicon wafers along with passive devices (such as resistors, capacitors and
inductors) and complementary metal oxide semiconductor (CMOS) transistors. This
integration capability facilitates the design of digital signal processing circuits, digital
control circuits, reference circuits, analog circuits, and radio frequency (rf ) circuits
on a single silicon-germanium BiCMOS die. Hence, silicon-germanium technology
enables significant speed, gain, and noise enhancements while maintaining the lowcost and high-yield capabilities associated with standard silicon processing. These
attractive features have propelled SiGe BiCMOS technology into the world of rf and
wireless design [9]-[11].
2.2
Technology Limitations
Although there are many advantages associated with SiGe BiCMOS technologies,
there are also some limitations. These limitations stem from the physics and material
properties associated with the technology, and can be lumped into three categories:
6
active device tradeoffs, passive capabilities, and undesired coupling between components.
2.2.1
Active Device Tradeoffs
A fundamental technology limitation for SiGe HBT technology is the breakdown voltage (BVCEO ) associated with the HBT itself. The breakdown voltage of a SiGe HBT
is dominated by avalanche multiplication, the act of electron-hole pair generation (and
then acceleration) by a highly energized electron impacting with the semiconductor
lattice [6]. The threshold energy for this process is related to the semiconductor?s energy bandgap (Eg ). Technologies based on higher bandgap materials, such as GaAs
(Eg = 1.42eV), can withstand significantly more voltage applied to their terminals,
giving them a decided advantage for high-voltage and high-power applications. Silicon has a bandgap of only 1.12eV (and germanium of only 0.63eV)[12], hindering its
ability to withstand large voltage swings. Clearly this creates challenges for circuits
and applications requiring large-signal driving capabilities.
The breakdown voltage of the HBT is also coupled to the speed or frequency response of the device. The collector doping of the HBT will typically be increased to
achieve higher fT values. However, this elevated doping level increases the electric
field in the collector-base junction, thus reducing the BVCEO of the transistor [6].
As SiGe technologies advance in frequency performance, the HBT breakdown voltages are reduced. This tradeoff has obvious consequences for high-speed, high-power
circuits, such as microwave power amplifiers. SiGe technologies generally offer variations of HBT devices (Figure 2) allowing designers to choose between high-speed,
low-breakdown devices or low-speed, high-breakdown devices, alleviating some of
the inherent technological tradeoffs. Obviously, more research examining high-speed,
high-power SiGe circuits would be beneficial.
7
150
100
200
Medium
Breakdown
75
IC (mA)
fT (GHz)
125
50
250
Low
Breakdown
High
Breakdown
0.1
High
Medium
Breakdown
Breakdown
150
100
50
25
0
Low
Breakdown
1
10
JC (mA/хm2)
0
50
0
1
2
3
4
VC (V)
5
6
Figure 2: Example of various HBT device options in a commercially available SiGe
HBT BiCMOS technology [13].
2.2.2
Passive Performance
Spiral inductors, resistors, capacitors, and varactors are also available in SiGe BiCMOS technologies. Thin-film microstrip transmission lines, transformers and baluns
constructed from the available metal layers are also possible (as demonstrated in
[14] and [15]) but may not be modeled or provided as a pre-determined cell in the
technology. All of these components can be extremely useful in rf circuit design for
impedance matching, resonant circuits, filters, and providing (or blocking) dc biases.
However, metal thickness and conductivity, oxide thickness and permitivity, and the
lossy silicon substrate define the performance of these components. As expected,
these passive performance limitations can impede the capabilities of a given circuit.
Inductive components (such as transmission lines, transformers, baluns and inductors) typically have the lowest quality factor (Q) for a given circuit. There has
been significant research over the years looking for techniques to improve the performance of these passives. The use of pattern ground-shields, thicker top-metal layers,
and high resistivity silicon substrates have demonstrated improvements in inductor
and transmission line performance, as shown in previous studies [16]-[18]. However
even with these enhancements, SiGe BiCMOS technologies still struggle to achieve
8
inductor Q values greater than 35.
2.2.3
Undesired Coupling
Coupling between circuit blocks can also be quite problematic in a fully-integrated
solution. Unwanted signals originating from the digital, intermediate frequency (IF)
or rf circuitry can couple into sensitive circuits (i.e. VCO, LNA, Mixer) producing
"spurs" in the band of interest and degrade the system performance. If enough gain
and coupling exists in the system this can quickly lead to oscillations, eliminating
the entire system functionality. Coupled signals can also shift the desired dc biasing
points of a circuit, further altering its performance.
Circuit-to-circuit coupling can occur through many paths. Undesired signals can
couple through shared power supply metal traces or through the silicon substrate
itself. Signal can also "leak" between blocks via 3-port circuits (e.g. mixers, baluns,
power-combiners) or by shared dc bias circuits, such as current mirrors or reference
circuits. Differential designs, the use of separate power supply lines, power supply decoupling capacitors, and additional supply pins are common design practices used to
minimize the magnitude of coupling which occurs via the power supply metal traces
and shared dc circuitry.
Up-conversion and down-conversion active mixers are the primary 3-port circuits
associated with signal leakage in SiGe BiCMOS transceiver systems. These circuits
typically incorporate a Gilbert cell mixer [19] and can suffer from local oscillator
(LO) to rf leakage. This leakage is due to the asymmetry of the circuit and input
signals, as well as the finite impedances of the circuit?s core transistors. Most mixer
coupling can be mitigated by the use of IF and rf filters, and various types of system
architectures (such as dual-IF, low-IF, or image-reject transceivers)[20]. These system
level solutions attenuate the undesired signals or shift the frequency in which they
exist to an inconsequential frequency band, thus minimizing their impact on the
9
Figure 3: Cross sectional diagram of Jazz SiGe120 technology.
system. Although these solutions address the issue of spurs in the signal path, they
do not fully eliminate the problem or guard against loading effects and the shift in
dc operating points that can occur due to signal leakage. They also can increase the
complexity and size of the system, creating new design challenges and an increase
in cost. Obviously further investigations into the undesirable coupling of monolithic
silicon-based systems would be of value.
2.3
Silicon-Germanium Technologies Under Investigation
Two different commercially available silicon-germanium HBT BiCMOS technologies
have been utilized for this study, the Jazz SiGe120 technology (Figure 3) and the
IBM 8HP technology (Figure 4). Both technologies are based on an 8-12 ?-cm
p-type silicon substrate and do not incorporate an epi-layer at the silicon surface.
Both technologies also offer shallow and deep trench isolation, high-speed and highbreakdown SiGe HBTs, low-loss spiral inductors, low-loss MIM capacitors, varactors,
CMOS transistors, and different types of integrated resistors[13],[21].
10
Figure 4: Cross sectional diagram of IBM 8HP technology.
The SiGe120 technology utilizes six layers of aluminum metalization and provides
various models and layouts for spiral inductors and spiral transformer designs. The
SiGe HBT technology incorporates a sacrificial emitter to create a self-aligned emitterbase region [13]. This sacrificial emitter structure is then removed and replaced by
an in-situ doped emitter, resulting in an HBT device with both low base resistance
and reduced capacitive parasitics [13].
The 8HP technology offers five layers of copper metalization and two additional
layers of thick aluminum. The technology also provides various models and layouts
for spiral inductors and thin-film microstrip transmission lines. The SiGe HBT for
this technology incorporates a raised extrinsic base structure along with an in-situ
doped polysilicon emitter to achieve high-frequency and low-noise performance [21].
Typical device performance metrics for both processes are summarized in Table
1 [13],[21]. As seen from Table 1, both technologies provide a sufficiently high HBT
unity gain cut-off frequency and maximum oscillation frequency for the frequencies
of operation targeted for this work.
11
Table 1: Characteristics of Jazz SiGe120 and IBM 8HP SiGe HBT BiCMOS technologies.
SiGe120 IBM8HP
NPN
fT (GHz)
150
209
fmax (GHz)
180
285
BVCEO (V)
2.3
1.7
CMOS VDD (V)
1.8
1.2
Lef f (хm)
0.18
0.13
12
CHAPTER 3
RADAR APPLICATIONS
3.1
Overview of Radar Systems
Radar systems are a fundamental component in many applications used today. They
are used in military applications, such as air defense systems, defense tracking, and
navigation, as well as commercial applications, such as weather monitoring, vehicular
speed detection, and air traffic control [22]. All of these radar systems function on
the same principle of radiating electromagnetic energy away from a source and then
waiting to receive any reflected signals. The direction that the receive antenna is
pointed, the time delay between radiation and sensing, and any frequency variation
between the two signals, determines the location of the object that the radiated pulse
reflected off of [22]. This process allows the radar system to detect any targets within
a given distance or range.
Obviously, there is a limited distance or range (RM AX ) in which the system can
successfully locate a target. At this distance of separation, the received signal power
level will be equal in magnitude to the radar?s minimum detectable signal (Smin ) [22].
This RM AX can be calculated as,
RM AX =
▓
Pt GAe ?
(4?)2 Smin
│1/4
,
(4)
where Pt is the transmitted power, G the transmitting gain, Ae the effective area of
the antenna, and ? the radar cross section of the target [22]. The Pt GAe product is
typically called the power-aperture-gain product (P AG). The P AG can be expressed
as,
P AG = Pt GAe =
13
4?Pt A2e
?2
(5)
using the relationship G =
4?Ae
,
?2
where ? corresponds to the wavelength of the fre-
quency of operation [22].
As seen from (4) and (5), once the frequency of operation for the radar system
is specified, only the radiated power, system sensitivity, and effective aperture area
can be varied to achieve a given performance. One technique used to significantly
improve the sensitivity of the system is to incorporate an array of antennae (Figure
5) as opposed to a single radiating element.
The radiation pattern of an antenna array can be manipulated (either electronically or mechanically) to position the main lobe (the lobe containing the maximum
radiated power) in the direction of interest. The ability to steer the main lobe (and
consequently the nulls), results in improvements in the signal-to-noise ratio (SNR)
and distortion of the system [24]. This functionality can be accomplished by adjusting the phase and amplitude of the individual signals fed into each antenna element
electronically, resulting in a phased array radar system [23]. These systems typically
enjoy the benefits of lower radar cross sections, rapid beam steering, very accurate
target location, and the ability to perform multiple functions at the same frequency
of operation [22].
However, the ability to interact electronically with all of the antenna elements can
be quite complicated and cumbersome. As shown in Figure 5, each radiating element
will now require a programmable phase shifting component to allow for this control
of the radiation pattern. The electronics associated with this capability can become
quite expensive, as well as large in size and weight. Therefore, a small, low-cost,
light-weight electronic solution capable of phase shifting the feed signals is needed for
phased array radar systems to become a viable solution for any radar application.
14
Figure 5: Diagram of a general phased array radar system.
3.2
X-Band Radar Applications
The majority of X-band (8-12 GHz) radar applications are for military or government
use, for sensing or tracking objects from satellites, flying aircraft, or mobile ground
based systems. These systems are typically based on electronically scanned array
(ESA) radar systems. Examples of such systems are, the US "Joint Surveillance
Target Attack Radar System" (JSTARS)[25], and the "Theatre High Altitude Area
Defense" (THAAD) radar system [26]. The JSTARS radar system is used to locate,
classify, and track ground targets in all weather conditions from airborne systems [25].
The THAAD radar is part of the THAAD missile defence system used for protection
against ballistic missiles from ground based systems[27]. Both of these systems are
targeting (or sensing) objects that are relatively far away and potentially do not want
to be monitored.
The majority of these military radar systems utilize transmit/receive (T/R) modules (Figure 6) to interact electronically with each antenna element, resulting in an
active electronically scanned array (AESA) system. These T/R modules generally
15
Figure 6: Typical system of an X-band phased array radar incorporating T/R
modules.
incorporate a low-noise amplifier (LNA), power amplifier (PA), phase shifter, singlepole double-throw (SPDT) switches, and transmit/receive switches. The modules
also interface with manifold circuitry that handles the combination and distribution
of the feed signals, provides frequency conversion, and analog to digital conversion.
The requirements on these T/R modules can be quite stringent, demanding low
noise figure (less than 5 dB) and low distortion during receive (RX) mode, as well
as high output power (greater than 1W) during transmit (TX) [27]-[30]. The entire
system must be robust and not suffer performance degradation due to "jamming"
signals, or other undesired high-power input signals. The system must also be small,
light weight, and low in power dissipation, to allow for easy transportation to various
locations.
3.2.1
SiGe X-Band Phased Array Radar Systems
Recent studies have investigated highly-integrated T/R modules based on III-V technologies for these radar applications [29],[31]. These modules incorporate the LNA,
16
PA, T/R switch and phase shifter onto a single III-V monolithic microwave integrated circuit (MMIC), and transmit ? 10 W of power per T/R module. However,
this topology does not fully leverage the benefits of a phased array system and the
performance dependence on the number of radiating elements (N).
The total radiated power (Pt ) of an antenna array is approximately equal to N Pe ,
where Pe is the radiated power per element. Similarly, the equivalent aperture area
(Ae ) is approximately equal to N Aes , with Aes being the equivalent aperture area of
a single antenna element. Introducing these relationships into the P AG, results in
P AG =
2
4?Pt A2e
3 4?Pe Aes
?
N
.
?2
?2
(6)
Hence, for a modest increase in radiating elements (N) the magnitude of Pe can be
reduced significantly for a given P AG. More importantly, the dc power needed for
the system will be reduced.
The total dc power needed to bias all of T/R modules (PT RA ) can be expressed as
PT RA = N Pe О T Ref f ,
(7)
where T Ref f is the efficiency of a single T/R module for a given output power.
Assuming a module with less output power will have an equal (if not better) T Ref f ,
we can conclude that the total power dissipated for all of the T/R modules (PT RA )
will also be reduced. Even though the number of T/R modules may be increased
(say by a factor of x), the dc power needed by each module will be reduced by x3 ,
resulting in a T/R system power decrease (or PT RA ) of x2 . What is of even more
consequence, is the reduction of raw materials (i.e. fuel) needed to power the system,
as well as the reduction of support equipment needed to transport, store, and convert
those raw materials.
To further leverage this new system paradigm, a lower-cost technology with higher
integration capabilities can be utilized for the T/R module to further reduce the
overall system cost. Typically, the relatively high transmit powers (> 1 W) needed
17
for a T/R module require a non-silicon solution. However with more manageable
output powers, a silicon-germanium BiCMOS technology capable of delivering 0.5 1 W of output power at 10 GHz becomes a more viable and cost-effective solution
than the current III-V technologies used today. The versatility of SiGe BiCMOS
technology allows for the integration of all the critical T/R module components (i.e.
low-noise amplifier, power amplifier, phase shifter, and switches) and digital control
circuitry onto a single die, maximizing cost savings and integration capabilities.
3.3
K-Band Radar Applications
There are several advantages to operating wireless systems at higher frequencies,
such as more available bandwidth, the reduction of antenna size, and the reduction of
spacing between antenna elements in an array [32]. Therefore, is not surprising that
many researchers, scientists, and entrepreneurs have expressed interest in the use of
higher frequency bands for new applications. In 2002 the FCC released the 22-29
GHz band for automotive radar systems to explore some of these ideas [33]. Since
this decision, there have been several investigations in short-range radar systems for
automotive applications [34]-[38]. These automotive short-range radar (SRR) systems
only have a range of ? 30m, but can still be used in numerous tasks such as parking,
detection of objects located in a cars blind spot, and pre-crash detection (Figure 7)
[36]. The utilization of these automotive SRR systems could significantly reduce the
number of intersection and rear-end collisions that occur today [35].
The specifications for these systems are strikingly different than the military T/R
modules mentioned earlier. Most of the SRR systems currently being pursued operate
at the global industrial, scientific, and medical (ISM) frequency band located at 24.125
GHz [35]. This frequency of operation is driven by many factors, such as bandwidth
requirements, technology cost, and antenna size [35]. However, due to the utilization
of adjacent frequency bands (such as the 23.6 - 24 GHz band for radio astronomy
18
Figure 7: Potential applications for automotive short-range radar systems.
Table 2: Summary of FCC Regulations for 24 GHz Vehicular Radar Applications
[33].
FCC UWB Ruling, FCC 02-48, Section 15.515
Sensor operating only when engine running, or upon specific activation
Minimum signal bandwidth 20% or 500 MHz (whichever is smaller)
(Bandwidth defined as -10dB below peak emission points)
Bandwidth contained between 22 GHz to 29 GHz,
with a center frequency greater than 24.075 GHz
Average Radiated Emission (22 GHz - 29 GHz) limited to
-41.3 dBm EIRP, 1 MHz BW, 1ms average
Peak Radiated Emission 0dBm EIRP in 50 MHz
around highest emission frequency
EIRP = Effective Isotropic Radiated Power
and remote sensing), there is a definite need to minimize the amount of out-of-band
signals generated by these SRR systems. To protect these sensitive adjacent bands,
the FCC has imposed specific regulations for these vehicular radar applications (Table
2).
3.3.1
SiGe K-Band Radar Systems
Although there has been significant work done on 24 GHz automotive radar systems,
it is still a relatively new product application. Except for the FCC specifications over
the band, there is no single topology or architecture that has presented itself as the
19
design of choice. In the past few years, two fully-integrated automotive radar systems
have been presented, both based on significantly different architectures [32], [38].
The work presented in [32] demonstrated a fully-integrated 24 GHz SiGe BiCMOS
phased array radar system. This system was based on a transmit IC and a separate
receive IC, both functioning with an antenna array (Figure 8)[32]. Instead of incorporating a phase shifter for each antenna element, the circuit generates 16 selectable
phase shifted local oscillator (LO) signals, and then selects the desired signal during
the frequency conversion of the transmitted or received signal. This LO signal was
also divided by four to generate a second LO reference signal, resulting in a dualheterodyne architecture for both the receiver and transmitter. The results for [32]
are quite impressive, demonstrating an eight element phased array receiver with a
noise figure of 7.4 dB per element, and a four element phased array transmitter with
a maximum output power of 14.5 dBm at each output.
However, [38] has also demonstrated an automotive 24 GHz radar system in a
SiGe BiCMOS technology (Figure 9). In this implementation the radar system does
not involve a phased array system, but is based on a psuedorandom noise (PN) coded
continuous-wave (CW) radar system [38]. The system also incorporates separate ICs,
for receive, transmit, and digital control and processing. The transmit IC utilizes
a 24.15 GHz continuous-wave (CW) source, which is either selected for transmit or
terminated into a load. The transmit signal is then sent through a binary phase-shift
keyed (BPSK) modulator and driven through the antenna [35]. During receive mode
the BPSK modulated signal is used as the LO drive for the receiver, which is based
on a homodyne (or direct down-conversion) architecture [35]. The final system was
capable of delivering 12 dBm of output power to the transmit antenna, and has a
receive noise figure of 6.5 dB with more than 40 dB of gain [35].
Both of these works have demonstrated very exciting results and are excellent
benchmarks to be used for future work. This is not to say that all of the integration
20
Figure 8: Simplified block diagram of a 24 GHz phased array radar system reported
in [32].
21
Figure 9: Simplified block diagram of 24 GHz radar system reported in [35].
issues associated with K-band systems have been investigated and addressed. As
stated earlier, both implementations incorporate separate RX and TX ICs. Obviously,
the combination of these two different functionalities onto a single die will be an
arduous task, with many obstacles to overcome. Also, both designs incorporated
power amplifiers with relatively high dc power consumption, resulting in power added
efficiencies (PAE) less than 5%. The ability to improve on this performance, as well
as investigate some of the challenges associated with a monolithic system for this
application, would be extremely helpful in the development of this new application
space.
22
CHAPTER 4
X-BAND PHASE SHIFTERS
4.1
Silicon Based Phase Shifters
The ability to generate a phase shift between antenna elements is a fundamental
requirement for phased array radar systems and is typically accomplished with the
use of a phase shifter. Although alternative methods for generating a phase shift
between radiating elements in K-band radar applications exist , this is not the case
for X-band applications. X-band radar applications typically incorporate tens of
thousand radiating elements (as opposed to only a dozen radiating elements in Kband applications), and have traditionally incorporated a T/R module (Figure 10)
with each element. Hence, a compact, wide-bandwidth, high-linearity, low-loss siliconbased phase shifter is a potential bottle-neck for monolithic SiGe BiCMOS X-band
radar applications.
Most high performance phase shifters are implemented using III-V technologies,
which can produce low-loss, high-linearity switches that are required for most phase
shifter designs. Unfortunately, the majority of SiGe HBT BiCMOS technologies do
not incorporate p-i-n diodes or Schottky diodes because of processing challenges or
an increase in fabrication cost. These devices are better suited for single-pole doublethrow (SPDT) switch designs than standard SiGe HBT or CMOS devices, due to their
low series "on" resistance and high isolation when in the "off" state. However with
SiGe HBT device performance constantly improving (achieving fT ?s > 200 GHz),
it is possible to design a robust SPDT switch based on a diode-connected HBT [1].
Similarly, as CMOS technologies scale down to smaller gate lengths the parasitics
of the device are reduced, enabling CMOS devices to become a viable solution for
23
Figure 10: Block diagram of typical T/R module for X-band systems.
microwave switch design as well.
It is essential to understand the design tradeoffs and device limitations for both
implementations, to allow one to select the proper device for a given application.
This work will investigate these differences and the impact these limitations have on
a 4-bit silicon-based phase shifter.
4.2
Comparison of Technological Capabilities of
MOS and HBT Phase Shifter
A high-pass/low-pass phase shifter topology was used for this study due to its ability
to produce a reliable phase shift over a wide frequency range of operation [40], which
is generally needed for X-band (8-12 GHz) applications. A high-pass/low-pass phase
shifter (Figure 11) incorporates series-connected SPDT switches to select between
high-pass or low-pass filter sections, creating a relative phase shift between the two
signal paths [40]. These filter sections and switching elements must have a high return
loss (> 15 dB) over the band of operation in order to minimize loading effects and
phase error. In addition to the return loss specification, it is also desireable for the
phase shifter to demonstrate low insertion loss and low noise figure. However as
seen from Figure 11, the LNA will generally precede the phase shifter and reduce
the impact of the phase shifter?s noise and loss on the system?s overall noise figure.
Similarly, the gain of the LNA requires the phase shifter to be very linear, to prevent it
24
Figure 11: Block diagram of high-pass/low-pass phase shifter topology.
from dominating the T/R module linearity. These system level specifications require
wide-bandwidth, matched, low-loss switches, capable of high-linearity performance.
4.2.1
SiGe HBT Switch Design
A single-pole single-throw (SPST) switch based on a diode-connected SiGe HBT is
shown in Figure 12 [1]. The SiGe HBT switch can be toggled "on" by enabling a
current source and forward-biasing the base-emitter junction, resulting in a low series
resistance and allowing signal to pass through the device [1]. In the unselected (or
"off") state the current source for the switch is turned off, and a pMOS transistor
pulls the emitter voltage of the SiGe HBT to the VCC rail. This forces a zero volt bias
across the emitter-base junction of the unselected HBT and eliminates any dc current
flow through the device [1]. Therefore, only the parasitic reversed-biased junction
capacitance will act as a leakage path for the unselected device.
In this configuration the insertion loss of a single SiGe HBT can be expressed as
S21 =
2Zo
2Zo + re +
1+rb /Z?
gm +1/Z?
,
(8)
where re and rb are the SiGe HBT?s emitter and base resistance, Zo is the characteristic impedance of the system, and gm is the transconductance of the device. The Z?
term can be expressed as
Z? =
r?
r?
?
,
1 + jCbe r?
1 + jf ?/fT
(9)
where ? is the current gain, f is the frequency of operation, fT is the unity-gain
cut-off frequency of the device, Cbe is the base-emitter capacitance, and r? =
25
?
.
gm
Figure 12: Schematic of series-connected SiGe HBT SPDT X-band switches.
Hence, for SiGe HBTs with sufficiently high fT and adequate current gain, the
insertion loss of the SiGe HBT diode will be dominated by the device?s emitter resistance and collector current (IC ). One can also conclude that the insertion loss will
remain constant over a very wide bandwidth, assuming the frequency of operation is
significantly less than the fT of the technology.
Although the base resistance of the device has a negligible effect on the switch
insertion loss, it does contribute to the switch noise figure. In the insertion loss
expression (equation 8), the rb term is divided by ? , minimizing its impact on the
insertion loss. However, the thermal noise generated by this base resistance is located
in series with the feedback loop of the diode connection. This results in a different
transfer function for the rb thermal noise generator and increases the noise figure of
the switch. Taking this into account, the noise figure of the switch can be expressed
as,
N F ? 10Log
└
Zo + rb + re +
Zo
1
2gm
!
.
(10)
Two SPST switches can be placed in parallel to create a SPDT switch, which
can then be duplicated, resulting in two series-connected SPDT switches (Figure 12).
This configuration allows sharing of the dc feed inductor connected to V CC, and the
26
?0.75
S21 (dB)
IC= 10mA
?1.25
IC= 7mA
?1.50
?1.75
?2.00
8.0
Q=20
IC= 13mA
?1.00
IC= 4mA
9.0
AE = 0.12X20хm2
VCC = 2V
10.0
11.0
Frequency (GHz)
12.0
?10
S11 (dB)
?15
?20
?25
IC= 4mA
IC= 7mA
IC= 10mA
?30
?35
8.0
Q=20
AE = 0.12X20хm2
VCC = 2V
IC= 13mA
9.0
10.0
11.0
Frequency (GHz)
12.0
Figure 13: Simulation results for a SiGe HBT based series-connected SPDT switch
for varying IC bias currents.
ability to further optimize all of the components for use in a phase shifter design.
The insertion loss of this series-connected SPDT structure can be expressed as
▓
│
2Zo
1
S21 =
,
(11)
RN +Zo
2RN + 2Zo 1 + 2R
eq
where RN = re +
1
,
gm
and Req correlates to the equivalent shunt resistance associated
with the loading of the unselected SiGe HBTs. The finite Q of inductors LDC and
LF will also load the circuit to some extent, but the effect of these parasitics are
negligible compared to that of the unselected SiGe HBTs.
Simulation results for the series-connected SiGe HBT SPDT switches are shown
in Figures 13 and 14 for varying bias currents and device sizes. As seen in Figure 13, a
larger biasing current will result in better return loss and insertion loss performance.
However, this increase in performance is eventually limited by the parasitics of the
27
0.00
VCC = 2V
IC = 10mA
Q = 20
4
?0.50
3
WE= 0.12хm
LE = 5хm
LE = 10хm
LE = 15хm
?0.75
?1.00
?1.25
8.0
9.0
10.0
11.0
Frequency (GHz)
2
NF (dB)
S21 (dB)
?0.25
5
1
0
12.0
Figure 14: Simulation results for a SiGe HBT based series-connected SPDT switch
for varying emitter lengths.
device, and results in additional dc power consumption for the overall design.
Optimal device sizing is also critical to the circuit?s overall performance. Most
SiGe HBT BiCMOS technologies give designers some selection freedom in different
emitter lengths (LE ) and emitter widths (WE ), to properly size the SiGe HBTs overall
emitter area (AE ). Larger devices will typically have smaller rb and re values, which
will result in a lower noise figure (as seen in Figure 14). However, these larger devices will also result in larger parasitic capacitances (e.g., the zero-biased base-emitter
capacitance (Cjeo ) and the collector-substrate capacitance (CCS )). These additional
capacitances will further load the circuit, resulting in a degradation of available bandwidth and eventually insertion loss.
4.2.1.1
Correlation Between Measured and Simulated HBT Switch Performance
A final consideration for switch design is the capability of the models and simulation
tools to accurately predict the overall switch performance. Even modest discrepancies
between simulated and measured performance can propagate into larger system level
issues when several of these switches are cascaded for the full shifter design.
28
?10
?1.00
?20
S11 & S22 (dB)
S21 (dB)
?0.75
?1.25
?1.50
?1.75
8.0
Measured HBT SPDT
Original Sim
Modified Sim
9.0
VCC = 2.1V
ICC = 8.9mA
10.0
11.0
Frequency (GHz)
12.0
Measured HBT SPDT
Original Sim
Modified Sim
?30
?40
?50
8.0
VCC = 2.1V
ICC = 8.9mA
9.0
10.0
11.0
Frequency (GHz)
12.0
Figure 15: Overlay of measured and simulated S-parameters for the HBT based
SPDT switch.
A single HBT based SPDT switch was fabricated in the IBM 8HP technology and
tested at die level to allow for a precise comparison between the HBT switch performance and simulated results. This SPDT switch design incorporated two 0.12x10.0
хm2 high-speed HBT transistors in parallel for the switch core, as well as the dc
biasing circuitry and digital logic control. The circuit operated off of a 2.1V voltage
supply and dissipated 18.7 mW of power. The measured and simulated S-parameters
are presented in Figure 15. As seen in Figure 15, there is a significant discrepancy
in insertion loss performance (i.e. S21 ) between the measured results and original
simulation results.
In attempt to reduce this margin of error an additional simulation was performed.
This simulation incorporated S-parameter files based on sonnet simulations [41] that
modeled transmission line effects of short routing sections and disconnects in the
ground plane. These subtle layout issues can not be modeled directly with the IBM
8HP design kit. The simulation also incorporated an additional 2.5 ? of emitter
resistance (re ), resulting in a total emitter resistance of 4 ?. The incorporation of
these additional losses reduces the error between measured and simulated results to
be less than 5% for the insertion loss magnitude (not in dB).
29
120
12.5
2
AE= 0.12X5.0 хm , re = 10 ?
AE= 0.12X12.0 хm2, re = 7 ?
AE= 0.12X18.0 хm2, re = 6 ?
80
60
40
0
0
1
2
3
4
5 6
IE (mA)
7
8
9
7.5
5.0
Model
Measured
2.5
High Speed HBTs
CBEBC Configuration
20
High Speed HBTs
CBEBC Configuration
10.0
re (?)
VCE (mV)
100
0.0
2.5
10
5.0
7.5
10.0 12.5 15.0 17.5 20.0
LE (хm)
Figure 16: Open-collector measurement results and corresponding emitter resistance
values of various high-speed 8HP HBT devices.
The amount of additional emitter resistance incorporated in the simulation was
determined from open collector measurements [42] performed on a variety of HBTs
in the technology under investigation. As seen in Figure 16, the measured re does not
correlate to the model parameters of the design kit. Admittedly, these results do not
account for the series resistance incorporated in the test setup, which was measured
to be around 3 ?. However even when the additional setup resistance is accounted
for in the calculations, larger emitter resistance values are still expected.
Although the majority of the additional loss for the HBT SPDT switch can be
accounted for, these results do illuminate the challenges associated with switch design.
Even slight layout imperfections and modest model errors can result in a significant
(and unacceptable) discrepancy between measured and simulated switch performance.
4.2.2
CMOS Switch Design
As stated earlier, CMOS devices can also be utilized in switch design for phase shifter
applications. However, due to the physics and properties associated with the device
it is better suited to be implemented as a simple pass-gate, as opposed to a diode
connected transistor. MOSFET devices typically have a lower transconductance than
bipolar devices (thus resulting in a higher "on" resistance) for a given bias current, but
30
Figure 17: Schematic and equivalent circuit for series-connected nMOS SPDT Xband switches.
have the ability to achieve a low series-resistance when biased as a simple pass-gate
or switch.
Again, it is beneficial to examine the CMOS based switch design from the standpoint of two series-connected SPDT switches (Figure 17a), since this lumped circuit
determines the majority of the loss and overall performance of the phase shifter. This
approach also leverages the integration capabilities of the technology and allows for
better optimization of the switches for this application.
As seen in Figure 17a, the nMOS transistors are utilized in a series-shunt switch
design, where a series nMOS device acts as a pass-gate and a shunt nMOS device acts
as a short. This is similar to the SiGe HBT topology, except that the MOS pass-gate
is functioning more as a passive switch. Therefore, the switch does not require any
dc bias current and the noise figure of the circuit correlates directly with its insertion
loss.
Simulated values for the nMOS device?s "on" and "off" resistance and capacitance
31
Table 3: Simulation Results for nMOS Switch Modeling.
WT otal
хm
50
80
160
L = 0.12хm
W/L
Ron Con
хm/хm
?
fF
417
9.4
60
833
5.9 100
1667
3.0 190
Rof f
?
7200
4700
1100
Cof f
fF
57
93
185
values are shown in Table 3 for the IBM 8HP BiCMOS technology (130 nm CMOS).
From this data, it is apparent that switches with low series-resistance can be achieved
in this technology. However, the parasitic capacitances associated with these switches
must be addressed if they are to be incorporated in high-frequency designs.
These parasitic capacitances occur between the nMOS?s drain and bulk (CDB ),
source and bulk (CSB ), drain and gate (CDG ), and source and gate (CGS ) terminals.
Different design techniques, such as biasing the device?s drain and source, the utilization of a high-impedance substrate [43], or a triple-well device [44], have been
investigated in previous studies. These techniques offer some improvement in the
mitigation of MOSFET device parasitics, but in no way eliminate the problem and
can result in a more complicated (and costly) design and layout. The most direct
way to manage these parasitics is to resonate them out with a shunt inductor or
incorporate them in a matching network with a series inductor, as shown in Figure
17a.
An equivalent circuit for the nMOS series-connected switches is shown in Figure
17b, where CM represents the "on" parasitic capacitances, RM is the "on" resistance
of the nMOS device, and ZOF F is the "off" impedance of the unselected device,
expressed as
ZOF F =
1
YOF F
=
jwCOF F
1
.
+ 1/ROF F
(12)
As observed from Table 3, the parasitic "on" and "off" capacitances are similar
for a given device size, resulting in COF F ? CM . Therefore, the total output shunt
32
capacitance (COU T ) seen on both sides of the series inductor LSE is approximately
equal to 2CM . These parasitics can be incorporated in a matching network (essentially
forming a bandpass filter) with a series inductor value of
LSE =
2
wo2 COU T +
1
,
(13)
Zo2 COU T
where wo is the design center frequency. Similarly, the series-connected SPDT input
parasitics can be resonated out with a shunt inductor, with a value of
LSH =
1
wo2 CM
.
(14)
Assuming ideal inductors, the S21 of these series-connected SPDT switches can
be expressed as
S21 =
2Zo
.
2Zo + 2RM
(15)
However, since the inductors are used as actual matching elements, their finite
Q?s can be the dominating factor in the overall switch performance. As shown in
Figure 18, for a finite inductor Q there is an optimal design point at which the "on"
resistance of the nMOS device is balanced with the loss incurred by the inductors (for
this case the optimal value is 4?). This is true for both the insertion loss and return
loss performance. Bandwidth considerations for this design can also be seen from
Figure 18. Circuits with too much parasitic capacitance will struggle to achieve a
sufficiently wide bandwidth of operation. However, more bandwidth can be achieved
for a slight degradation in switch performance if the circuit is designed at a higher
center frequency, as seen in the 4? case and the 4? @ fDES =12 GHz case.
4.2.2.1
Correlation Between Measured and Simulated MOS Switch Performance
It is also beneficial to examine the modeling capabilities and challenges associated
with the MOSFET based SPDT switch. To facilitate this study, a single SPDT
switch based on an nMOS design was fabricated and tested. The circuit incorporated
33
?1.25
S21 (dB)
Q = 20
?1.50
RM = 2.5 ?
RM = 4.0 ?
RM = 5.5 ?
RM = 4.0 ?, fDES= 12 GHz
?1.75
?2.00
8.0
9.0
10.0
11.0
Frequency (GHz)
12.0
?10
S11 (dB)
?20
?30
RM = 2.5 ?
RM = 4.0 ?
RM = 5.5 ?
RM = 4.0 ?, fDES= 12 GHz
?40
Q = 20
?50
8.0
9.0
10.0
11.0
Frequency (GHz)
12.0
Figure 18: Calculated S-parameters versus frequency for nMOS equivalent circuit,
with a Q = 20, varying RM , and a nominal design frequency of 10 GHz.
two eight-finger nMOS devices, with a gate length of 0.12 хm and a gate width of 5.0
хm (as seen in Figure 19). The switch operated off of a 1.4V supply and dissipated
negligible (< 1 хW) dc power. As seen in Figure 20, the measured performance of the
nMOS based SPDT switch was also significantly worse than simulations predicted.
To minimize the discrepancy between these results, an additional simulation was
incorporated in the study. This simulation involved sonnet based S-parameter files
accounting for short routing traces and discontinuities in the ground trace. The
simulation also investigated the impact of additional resistance between the bulk
node of the nMOS device and the actual ground of the circuit. The 8HP design kit
assumes that the resistance between the substrate immediately under the device (or
the bulk node of the nMOS transistor) and the metal ground trace of the circuit is
34
Figure 19: Layout photo of nMOS devices for nMOS SPDT switch.
determined by the number of substrate contacts that exist on the die (regardless of
location). By extracting only specific portions of the layout which contain a finite
number of substrate contacts (as shown in Figure 19), one can introduce additional
resistance (approximately 73 ? in this case) between the bulk node of the device and
the ground of the circuit.
The inclusion of these additional loss mechanisms significantly reduces the error
between simulated and measured data. There is less than 5% of error between the
magnitude of the measured and simulated insertion loss, and the correlation of the
S11 data improves as well. Although the exact magnitude of resistance between the
nMOS bulk node and ground can not be easily extracted experimentally (as done
for the HBT?s emitter resistance), one can infer that additional characterization and
modeling of the nMOS device would help in accurately predicting the overall circuit?s
performance.
35
?1.00
VDD = 1.4V
S21 (dB)
?1.25
?1.50
S11 Data
VDD = 1.4V
Measured MOS SPDT
Original Sim
Modified Sim
Measured MOS SPDT
Original Sim
Modified Sim
?1.75
?2.00
?2.25
8.0
9.0
10.0
11.0
Frequency (GHz)
12.0
Figure 20: Overlay of measured and simulated S-parameters for the MOS based
SPDT switch.
4.2.3
Comparison of SiGe HBT and CMOS Switch Capabilities
As demonstrated from Figures 13 and 18, the SiGe HBT series-connected SPDT
switches are capable of lower insertion losses and wider bandwidths of operation for
the technology investigated here. This can also be observed from the measured results
(Figure 21) for these SPDT switches fabricated and tested at wafer level.
This superior performance stems from the smaller SiGe HBT area for a given
switch compared to the amount of active area needed for nMOS switches. As shown
in Figure 13, a SiGe HBT emitter area (AE ) of only 2.4 хm2 is needed for each diodeconnected SiGe HBT to achieve low-loss performance. The nMOS series-connected
SPDT switch requires a gate area of 13 хm2 per series nMOS transistor to achieve a
similar loss performance. Although these sizes do not capture the transistor?s overall
area (this would be determined by the SiGe HBT?s deep-trenches, and the MOS?s
source and drain areas, as well as transistor configuration), they do highlight the
drastic difference in transistor size between these two implementations. These larger
device sizes will correlate to larger parasitic capacitances to the substrate, hindering
bandwidth and insertion loss performance.
36
?1.25
S21 (dB)
?1.50
?1.75
MOS SPDT
VDD = 1.4V
HBT SPDT
VCC = 2.1V
ICC = 8.9mA
?2.00
?2.25
8.0
9.0
10.0
11.0
Frequency (GHz)
12.0
S11 & S22 (dB)
?10
MOS SPDT
VDD = 1.4V
?20
?30
?40
8.0
HBT SPDT
VCC = 2.1V
ICC = 8.9mA
9.0
10.0
11.0
Frequency (GHz)
12.0
Figure 21: Measured S-parameters for HBT SPDT switch and nMOS SPDT switch.
The SiGe HBTs also benefit from the fact that they are vertical transport devices,
whereas the CMOS devices are lateral transport devices. The vertical structure of the
SiGe HBT eliminates any parasitic capacitances between the base or emitter terminal
and the substrate at the device level (obviously metal connections and routing will
create parasitic capacitances at the circuit level). In contrast the nMOS transistor
is a lateral device, resulting in parasitic capacitances between both the source and
drain implants and the substrate. These additional capacitances result in a larger
dependence on matching elements with finite Q?s, and result in bandwidth limitations
and an increase in loss.
For the technology investigated here, it is expected that a phase shifter based
on SiGe HBTs should have inherently lower loss and wider bandwidth capabilities
than a nMOS based phase shifter. However, the SiGe HBT shifter will inherently
dissipate significantly more power and could be larger in size to accomodate dc biasing
37
inductors, additional current sources, and dc blocking capacitors. The noise figure of
the SiGe HBT phase shifter will be larger than its insertion loss, but it might not
exceed the noise figure of the nMOS based phase shifter due to the relationship of
cascaded stages and noise figure (as demonstrated in Friis formula [20]). Depending
on system level specifications, either implementation could be a viable solution for a
phase shifter for T/R module applications.
4.2.4
Comparison of CMOS and HBT Based 4 Bit Digital Phase Shifters
Two 4-bit X-band phase shifters were designed, fabricated, and tested using the
IBM 8HP SiGe HBT BiCMOS technology to quantitatively demonstrate the tradeoffs
between a SiGe HBT based phase shifter and a CMOS based phase shifter. Both
circuits incorporated four digital inputs to select between the 22.5? , 45? , 90? and 180?
high-pass/low-pass sections. Similar passive component filter sections were used for
both shifters to facilitate a fair comparison, varying only slightly in component values
to allow for performance optimization. The SiGe HBT phase shifter required three
dc supplies (VCC, GND, and BIAS) and had a simulated insertion loss of 9.5 dB,
and an absolute phase error < 5? . The nMOS shifter only required a VDD and GND
supply and had a simulated insertion loss of 13.5 dB, and an absolute phase error <
5? .
4.2.4.1
4-Bit Shifter Results
The measured insertion loss of both phase shifters is contained in Figure 23, and the
measured IP1dB in Figure 24. As seen from these two figures, the SiGe HBT phase
shifter demonstrated a lower and flatter insertion loss over the band of interest. Both
circuits suffered an increase in insertion loss performance compared to their simulated
results due to model inaccuracies, as discussed earlier.
Both circuits demonstrated sufficient linearity, with input referred compression
points greater than 5dBm. The absolute phase error for the SiGe HBT and nMOS
38
Figure 22: Die photos of the HBT and nMOS 4-bit X-band phase shifters.
phase shifters (Figure 25) was less than +/- 14? from 8-12 GHz for both circuits.
The SiGe HBT phase shifter demonstrated an average noise figure of 14.1 dB, and
the MOS based shifter had an average noise figure of 17.8 dB, as seen in Figure 26.
A summary of the two circuits? performance over a 4 GHz and 2 GHz bandwidth is
reported in Table 4.
Table 4: Summary of nMOS and SiGe HBT Phase Shifter Performance.
Frequency (GHz)
IL (dB)
Return Loss (dB)
Phase Error (deg.)
Noise Figure (dB)
IP1dB (dBm)
IIP3 (dBm)
Power Diss. (mW)
Die Area (mm2 )
HBT Shifter
8.0-12.0 8.5-10.5
-12.5
-12.3
> 10
> 13
< 12
<7
14.1
13.7
5.7
20
194
9.6
39
MOS Shifter
8.0-12.0 8.5-10.5
-18.0
-17.2
> 10
> 10
< 14
<5
17.8
17.2
8.6
21
3 О 10?4
8.1
?10
?12
HBT Shifter
S21 (dB)
?14
?16
?18
MOS Shifter
?20
?22
8.0
8.5
9.0
9.5 10.0 10.5
Frequency (GHz)
11.0
11.5
12.0
Figure 23: Insertion loss for nMOS and SiGe HBT X-band 4-bit phase shifters.
Output Power (dBm)
?5
HBT Shifter
IP1?dB = 5.7 dBm
?10
?15
MOS Shifter
IP1?dB = 8.6 dBm
?20
?25
?30
?15
fs = 9.5 GHz
Digital = 0000
?10
?5
0
5
Input Power (dBm)
10
15
Figure 24: Compression point for nMOS and SiGe HBT X-band 4-bit phase shifters.
40
Phase Error (degrees)
Phase Error (degrees)
15
10
MOS Shifter
5
0
?5
?10
8.0
9.0
10.0
11.0
Frequency (GHz)
12.0
15
HBT Shifter
10
5
0
?5
?10
8.0
9.0
10.0
11.0
Frequency (GHz)
12.0
Figure 25: Absolute phase error for nMOS and SiGe HBT X-Band 4-bit phase
shifters.
22
Noise Figure (dB)
20
18
MOS Shifter
16
HBT Shifter
14
12
10
8.0
Digital = 0000
8.5
9.0
9.5 10.0 10.5
Frequency (GHz)
11.0
11.5
12.0
Figure 26: Noise Figure for nMOS and SiGe HBT X-Band 4-bit phase shifters.
41
As seen from Table 4, the SiGe HBT and nMOS phase shifters have similar performance capabilities in terms of return loss, phase error, compression point, and
linearity. As expected, the SiGe HBT shifter demonstrates better insertion loss and
noise figure performance, and maintains a flatter response over a wider frequency of
operation. However, the nMOS shifter is smaller in size and dissipates significantly
less dc power, clearly an important consideration for system design.
4.3
5-Bit SiGe HBT X-Band Phase Shifter
For phased array radar applications a finer resolution of phase shift (i.e. higher
number of selectable states in the phase shifter) is desirable for enhanced performance
of the overall system. Although a 6-bit or 7-bit phase shifter might be more desirable
from a system/phase shift resolution point of view, it would not be worth the amount
of loss the system would have to overcome due to these additional bits. Therefore, a
5-bit high-pass/low-pass X-band phase shifter design (Figure 27) based on the HBTswitch design has also been investigated. The HBT based design was utilized due to
its superior bandwidth and insertion loss capabilities as highlighted in the previous
section.
4.3.1
Measured Results
The circuit demonstrated an average measured insertion loss of ?16.2 dB (Figure
28)and an absolute phase error < +/- 15? (Figure 29). The expected phase shift
of the circuit correlated well with simulation results. As discussed earlier, there
is approximately a 0.5 dB discrepancy between the simulated switch insertion loss
and the measured insertion loss. Again this modeling error resulted in a significant
difference between the simulated insertion loss (11 dB) and the actual measured
results.
The return loss of the phase shifter was greater than 10 dB across the band
of operation and agreed well with simulation. The circuit demonstrated an input
42
Figure 27: Die photo (4.1 x 2.4 mm2 ) of 5-bit X-band HBT phase shifter.
?14
S21 (dB)
?15
?16
?17
?18
?19
8.0
8.5
9.0
9.5 10.0 10.5
Frequency (GHz)
11.0
11.5
12.0
Figure 28: Insertion loss for 5-bit X-band HBT phase shifter.
43
360
Phase Shift (degrees)
320
280
240
200
160
120
80
40
0
8.0
8.5
9.0
9.5 10.0 10.5
Frequency (GHz)
11.0
11.5
12.0
Figure 29: Phase shift for 5-bit X-band HBT phase shifter.
compression point (IP1dB ) of 4 dBm, and an input referred third order intercept
point (IIP3 ) of 18 dBm, while dissipating 248 mW from a 2.3 V supply. The 32
states of the phase shifter were controlled with digital inputs, which drove digital
CMOS inverters and switches used to control the HBT current sources.
Assuming that this SiGe phase shifter was integrated with a LNA with a gain of 20
dB, a noise figure of 2 dB, and an IIP3 of ?9 dBm (this level of performance has been
presented in [45] and [46] using an earlier generation of SiGe BiCMOS technology),
the combined performance of the LNA and phase shifter would yield a gain of 3.8 dB,
a noise figure less than 3.5 dB, and an IIP3 of ?9.8 dBm. The circuit would also have
five bits of phase shifting resolution, with an absolute phase error < +/- 15? . From
these results it is apparent that the phase shifter has successfully achieved the phase
shifting functionality needed for a phased array radar system, while only having a
modest impact on the system?s overall noise figure and linearity performance.
These results are also significantly better than the performance of previously published silicon-based phase shifters utilizing commercially available technologies for
this frequency of operation, such as those reported in [47]. The work presented in
44
[47] demonstrated a 4-bit phase shifter with an integrated LNA in a SiGe BiCMOS
technology, but only achieved an IIP3 of -17dBm and a noise figure of 4.4 dB. The
circuit also only functioned over a 1 GHz bandwidth and had an absolute phase error
of 18? [47]. Admittedly, the phase shifters presented in this work do not outperform
those based on III-V technologies [48], MEMS technologies [49], or even p-i-n diodes
[50]. However, all of these other implementations require the use of non-standard
silicon fabrication technologies, and therefore suffer from additional fabrication cost
and the challenge of integrating various technologies into a single package. The work
presented here demonstrates a phase shifter that could be integrated on chip with
other T/R module building blocks, resulting in a monolithic T/R module for X-band
phased array radar systems.
45
CHAPTER 5
X-BAND DOWN-CONVERSION MIXER
5.1
Introduction to Down-Conversion Mixers
Down-conversion mixers are a fundamental component to any transceiver system design. They provide frequency translation of the received signal to a lower intermediate
or baseband frequency, where gain control, filtering, and analog-to-digital conversion
circuitry is more easily implemented. Although down-conversion mixers are not typically incorporated in X-band T/R modules, they are required for the overall system.
It is also possible that as SiGe based radar systems evolve, frequency conversion
capabilities could be added to the the T/R module functionality.
Most SiGe down-conversion mixers are based on the Gilbert cell [19] architecture
(Figure 30), which utilizes a driving stage (Q1 and Q2) and a switching stage (Q3 Q6). The driving stage converts the input signal to a current and drives it into the
switching stage. The switching stage rapidly transitions from one possible output
path to another at a specified frequency. This process results in the multiplication of
the input (RF) signal and the switching (LO) signal, approximated as
Vout = VRF cos(?RF t) О gm О RL О
▓
│
2
2
cos(?LO t) ?
cos(3?LO t) + . . . , (16)
?
3?
where gm is the driving transistor?s transconductance, ?RF and ?LO are the frequency
of the RF signal and the LO signal respectively, RL is the value of the load resistor,
and VRF is the voltage amplitude of the RF input signal [51]. This expression can be
further simplified to
46
Figure 30: Example of Gilbert cell down-conversion mixer.
Vout
▓
│
1
?
VRF gm RL О cos(?LO ? ?RF )t + cos(?LO + ?RF )t ,
?
(17)
with the use of trigonometric functions and the elimination of higher order terms
[51]. This result gives the frequency conversion of the RF input to a lower frequency,
where either the upper sideband or lower sideband signal can be selected for further
processing.
Down-conversion mixers are typically preceded by a low-noise amplifier in the
receive path of a transceiver. It is critical that they have both low-noise and highlinearity capabilities, to prevent them from hindering either the system level noise
figure performance or the system level linearity performance. It is also important
that they have sufficient isolation between the LO port and the RF and IF ports. If
LO signal leaks to the RF port, it could eventually couple back to the antenna and
possibly corrupt or mix with other received signals [51]. Obviously, the ability to
implement a high-linearity, low-noise, down-conversion mixer with good port-to-port
isolation is critical for SiGe based transceiver systems.
47
Figure 31: Die photo (1.2 x 1.2 mm2 ) and schematic of the X-band down-conversion
mixer.
5.2
Down-Conversion Mixer Circuit Design
An X-band down-conversion mixer (Figure 31) has been designed, fabricated and
tested using the IBM 7HP process [52] (the IBM 7HP process is very similar to the
8HP process, but with a peak fT of 120 GHz). The circuit is based on a standard
Gilbert cell topology, but utilizes the emitter terminal of a quasi-balanced differential
pair for the RF input. This topology minimizes the parasitic capacitance between
the RF and LO inputs, thus reducing the potential for LO to RF leakage. The circuit
also targeted a balanced set of performance metrics (i.e. gain, noise, linearity, and
isolation). This type of design methodology is advantageous, in that the resulting
circuit has a relatively low noise figure, but enough dynamic range and port-to-port
isolation to minimize unwanted coupling between adjacent blocks.
5.3
Measured Performance
The circuit operates from a 3.0 V supply and uses only 4.0 mA of bias current for
the mixer core (18.0 mA for the entire circuit). The mixer?s conversion gain (CG),
return loss (RL), and double side band noise figure (DSB NF) remain very flat across
the intended frequency band of operation (Figure 32) and agree well with simulation,
which predicted a conversion gain of 13.6 dB and a noise figure of 11.5 dB.
48
16
14
14
12
12
10
10
8
8
6
6
4
2
0
4
Noise Figure
Return Loss
Conversion Gain
8
9
IF = 1.25 GHz
LO Power = ?8.7 dBm
10
11
Frequency (GHz)
Return Loss (dB)
Conversion Gain, Noise Figure (dB)
16
2
0
13
12
Figure 32: Conversion gain, noise figure and RF port return loss for X-band downconversion mixer.
20
6
Output Power (dBm)
Output Power (dBm)
Output P1dB = 2.1 dBm
2
0
?2
?4
?6
RF = 11.2 GHz
IF = 1.25 GHz
LO Power = ?8 dBm
?8
?10
?20
IIP3 = ?0.45 dBm
10
4
?18
?16
?14
?12
?10
Input Power (dBm)
?8
Fundamental Power
0
?10
?20
IM Power
?30
?40
LO = 9.95 GHz
IF = 1.25 GHz
fs1 = 11.21 GHz
fs2 = 11.19 GHz
LO Power = ?9 dBm
?50
?60
?6
?70
?30
?25
?20
?15
?10
?5
Input Power (dBm)
0
5
Figure 33: Output power versus input power and intermodulation distortion for the
X-band down-conversion mixer.
The mixer also demonstrated an output 1-dB compression point (OP1dB ) of 2.1
dBm, as well as an IIP3 of ?0.45 dBm (Figure 33), while only requiring an LO
power level of ?6 dBm (Figure 34). The circuit also exhibited good port-to-port
isolation demonstrating an LO to RF suppression greater than 25 dB across the band
of operation, as seen in Figure 35. This performance results in a balanced design,
competitive with other previously published SiGe down-conversion mixers, as shown
in Table 5.
49
14
Conversion Gain (dB)
12
10
8
6
4
RF = 11.2 GHz
IF = 1.25 GHz
RF Power = ?30 dBm
2
0
?20
?18
?16
?14 ?12 ?10 ?8
LO Power (dBm)
?6
?4
?2
Figure 34: Conversion gain versus LO power for the X-band down-conversion mixer.
Port to Port Isolation (dB)
40
35
30
25
20
RF to IF
LO to IF
LO to RF
15
10
RF Power = ?18 dBm
LO Power = ?8.7 dBm
5
0
7
8
9
10
11
Frequency (GHz)
12
13
Figure 35: Port-to-port isolation versus frequency for the X-band down-conversion
mixer.
50
Table 5: Performance comparison of SiGe microwave down-conversion mixers
Literature
Freq. of
CG Output IIP3 DSB Power
SiGe
Operation
P1dB
NF
Technology
GHz
dB
dBm
dBm dB
mW
This Work
8.4-12
12.6
2.1
-0.45 11.9 54 / 12* fT =120 GHz
[53]
10.8-11.8 16.1
NR
NR
9.4
53
fT =50 GHz
[54]
12-42
25
3.5
-11.5
15
365
fT =85 GHz
[55]
20
10
1
-1
17
32
fT =50 GHz
[56]
17
9
-13
-10
11.5
17.8*
fT =47 GHz
[57]
18
4.5
-12.2
-1
7.1
16.5*
fT =45 GHz
NR = Not Reported, * denotes mixer core power only
5.4
Down-Conversion Mixer Figure-of-Merit
There have been numerous papers published on different mixers, utilizing different
technologies or new topologies [53] - [61]. In examining these works, it is challenging
to understand how these new developments have actually furthered the performance
capabilities of mixers. In many instances, the design may have been optimized for
one performance metric (such as noise figure, conversion gain, or linearity), at the
expense of the other metrics. By establishing an encompassing single mixer figure-ofmerit (FOM), it is possible to more accurately compare new technologies and design
techniques. This FOM could also assist designers in evaluating new mixer designs
and implementation methods for a given technology.
The proposed down-conversion mixer FOM is presented in equation 18. This mixer
FOM takes into account power dissipation, noise figure, conversion gain, linearity, and
isolation. An ideal active mixer would produce a FOM equal to zero. However due
to non-idealities and losses, a real mixer will produce a negative number (the less
negative the better). An explanation of these parameters, and the rational for why
they are needed and how they are weighted, will be outlined in the following sections.
F OMM IX = (CG ? N F ) + (M IXLIN ? N F ) ? M IXpwr ? M IXISO
51
(18)
M IXLIN
▓
(IP1dB )mW ? (IIP3 ? 9.6)mW
= 10Log
(IP1dB )mW + (IIP3 ? 9.6)mW
M IXpwr
▓
Pdiss
= 10Log
1mW
│
│
(19)
(20)
M IXISO = 10Log(ISOLO?RF ) + 10Log(ISOLO?IF ) + 10Log(ISORF ?IF ) (21)
ISOLO?RF =
?
?
?
? (LOpwr?RF )mW
(IP1dB ?10)mW
?
?
?0
ISOLO?IF =
?
?
?
? (LOpwr?IF )mW
(OP1dB ?10)mW
=1
(22)
if
(LOpwr?IF )mW
(OP1dB ?10)mW
=1
(23)
otherwise
?
?
?
? (RFpwr?IF )mW
(OP1dB ?10)mW
?
?
?0
5.4.1
(LOpwr?RF )mW
(IP1dB ?10)mW
otherwise
?
?
?0
ISORF ?IF =
if
if
(RFpwr?IF )mW
(OP1dB ?10)mW
=1
(24)
otherwise
Conversion Gain
The mixer?s conversion gain is critical to its performance, in that it represents the
mixer?s ability to transfer the RF input signal to the desired IF output signal. Depending on the mixer topology and device technology, this could result in an amplification
or attenuation of the signal. The primary benefit of having a high conversion gain is
the reduction of the receiver?s overall noise figure.
As seen from the Friis equation,
Ftot = 1 + (F1 ? 1) +
Fm ? 1
F2 ? 1
+ иии +
,
Ap1
Ap1 и и и Ap(m?1)
52
the total noise figure (not in dB) of a cascaded system (Ftot ) is dominated by the first
component (F1 ), but can also be impacted by other noisy components located later
in the system [20]. The gain of each preceding stage (Ap1 и и и Ap(m?1) ) will reduce the
effects of noise associated with the latter stages (F2 и и и Fm ) .
There is no way of predicting what the noise figure of the latter stages will be,
without having details about the system and the technology being investigated. However in an optimized receiver system, the noise figure of each building block will likely
increase as it is located further from the antenna. Assuming that the noise figure of
the IF circuitry is (in the best case) equal to that of the mixer, then this value can
be used to estimate the benefit of the mixer?s conversion gain.
Assuming
FM ixer >> 1,
allows the simplification of Friis equation to
FIF ?
FM ixer
.
AM ixer
This can also be expressed in dB as
N FIF = N Fmixer ? CGmixer ,
where N FIF represents the equivalent noise figure of the IF circuitry referenced to
the input of the mixer. Hence, the conversion gain of the mixer is being normalized
to its own noise figure.
5.4.2
Noise Figure and Linearity
The noise figure and linearity of a mixer are also critical performance metrics. The
combination of these two parameters is usually represented by the spurious free dynamic range (SFDR) [20]. However, the SFDR utilizes the minimum acceptable
signal-to-noise ratio of the system, as well as the bandwidth. In essence, this specification is more valuable for a system level comparison rather than a block level
53
comparison. A similar concept to the SFDR is proposed, by simply normalizing the
noise figure of the mixer to its linearity.
The linearity and 1-dB compression point of the mixer have been combined since
they are strongly correlated. The rule-of-thumb relationship between compression
point and IIP3 is that IIP3 is equal to IP1dB + 9.6 [20]. However, since the LO
signal driving the mixer is no longer truly small signal, it is possible that these two
parameters do not track one another as first-order theory predicts. A parallel combination of the two (in milliwatt power) is used to determine the limiting parameter
(as seen in equation 19). For system-level design, the ability of the down-conversion
mixer to handle a wide range of input power levels will often be more crucial than
its ability to deliver a large output power. Therefore, the linearity term has been
input-referred.
5.4.3
Power Dissipation
Power dissipation is always a critical specification in any wireless integrated circuit
design and is taken into account as well (equation 20). The power dissipation term in
the mixer FOM should be based only on the mixer core. Power dissipation associated
with non-amplifying, non-filtering components should not be incorporated, to facilitate more meaningful comparisons between various mixers. The power dissipation
associated with emitter followers, or other active buffers, generally masks the true efficiency of the mixer. However, if IF amplifying stages are incorporated in the design
to help achieve a higher conversion gain and lower noise figure, the power dissipation
associated with those components should be included. For passive mixer designs or
those which dissipate less than 1 mW of power, this term should be set to zero.
54
5.4.4
Isolation
The last term of the FOM takes into account the isolation capabilities of the mixer.
In general, good port-to-port isolation is critical to ensure that no components connected to the mixer are pushed into saturation, or perturbed from their nominal
dc operating point due to unwanted signals coupling through the mixer [51]. It is
also possible that these undesired signals could up-convert or down-convert to critical frequencies utilized in the receiver and become a limiting constraint. Since the
linearity of adjacent components is directly related to these phenomena, the absolute
power level of the unwanted signal is more telling than the transmission coefficient or
isolation numbers.
By normalizing the power level of the unwanted signal to the RF (or IF) power
level when the mixer is operated at 10dB backed-off, one is able to determine the
severity of signals coupling between ports. This is accomplished in equations 22 - 24,
where the LO power that couples to the RF port is normalized to the expected input
power when operated at 10 dB backed-off. Similarly, the LO power that couples to
the IF port of the mixer will be normalized to the expected output power of the mixer
when operated at 10 dB backed-off.
Equations 22 - 24 have been made conditional for practical reasons. It can be
challenging to accurately measure isolation characteristics larger than 30 dB at microwave frequencies. In addition, when the coupled signal is equal in magnitude to
the desired signal at 10 dB backed-off, it can be considered small signal. At this
point, the coupling of these signals becomes more of a second-order characteristic,
and is not nearly as grievous as large-signal coupling.
5.4.5
Comparison to other Mixer Figures of Merit
This new mixer FOM has been used to compare the mixer presented in the previous
section to other reported works (Table 6). Different mixer FOMs have been calculated,
55
Table 6: Comparison of Reported X-Band SiGe Mixers Based on Proposed FigureOf-Merit
Literature
Freq. of
F OMM IX
Operation
GHz
This Work
8.4-12
-42 / -35* / -35**
[54]
12-42
-54
[55]
20
-51
[56]
17
-48* / -58**
[57]
18
-39**
** denotes mixer core power only, and
inclusion of isolation calculation
* denotes mixer core power only
due to limited information included in the various publications. However in all of these
scenarios, the down-conversion mixer presented in this work always demonstrates the
least negative (and therefore better) mixer FOM. Again, this highlights the balanced
set of performance metrics achieved by the SiGe down-conversion mixer presented
here.
This table also demonstrates the benefit of this mixer FOM over other methods,
such as gain-bandwidth products or a gain, noise figure, and linearity ratio. As seen
from Table 6, the isolation term was included for [56] to demonstrate its effect on the
FOM calculation. The mixer presented in [56] reported an input compression point of
-24 dBm, with an LO-RF leakage of 20 dB utilizing a -4 dBm LO signal. Therefore, the
amount of LO power coupling into the RF port (-24 dBm) is equal in magnitude to the
maximum allowable mixer input signal (also -24 dBm). This will generate challenges
in the receiver system level design, and is undesirable in mixer performance. This
drawback would be overlooked in more traditional mixer comparisons. The proposed
mixer figure-of-merit provides an encompassing standardization, which conveys the
mixer?s overall performance, as opposed to a limited subset of metrics.
56
CHAPTER 6
K-BAND UP-CONVERSION MIXER
6.1
Introduction to Up-Conversion Mixers
A key building block in fully-integrated microwave transceiver systems is the upconversion mixer. This circuit functions similarly to a down-conversion mixer, but frequency shifts an IF input to the desired RF output frequency. The signal would then
be amplified by a power amplifier and transmitted via the antenna. The transceiver
architecture and circuit topology used for the application will determine the type of
up-conversion mixer needed for the system.
The transmission of unwanted signals and spurs by these transceiver systems can
pollute a frequency spectra, thus hindering the performance of other systems operating in adjacent frequency bands. This is especially true for K-band applications
operating at frequencies adjacent to radio astronomy and remote sensing frequency
bands. These concerns have resulted in strict regulations on out-of-band emissions
imposed by the FCC. To minimize these undesired signals, the transmitter must limit
the amplitude of unwanted spurs and digital noise that are driven to the antenna.
Although filtering stages can be incorporated at the RF output of the transceiver, it
is more efficient to attenuate these signals at the lower intermediate frequency where
passive and active devices are less lossy. This is only beneficial if the up-conversion
mixer does not generate additional spurs and intermodulation products when upconverting the signal. Therefore, it is essential for a robust microwave up-conversion
mixer to have a high dynamic range while simultaneously maintaining a low spurious
response[20].
57
To date, the state-of-the-art in microwave up-conversion mixers have been dominated by III-V technologies such as GaAs, which is problematic for implementing
low-cost, highly-integrated, single chip transceiver system solutions. Although SiGe
BiCMOS technology has been ear-marked for various K-band applications [10], there
is still limited work on SiGe up-conversion mixers for these frequencies of operation.
Further exploration of K-band up-conversion mixers with enhanced dynamic range is
needed to address the challenges and concerns facing K-band monolithic transceivers.
6.2
Up-Conversion Mixer Circuit Design
The Gilbert cell mixer [19] has established itself as one of the primary bipolar-based
circuit topologies for up-conversion mixers. As accomplished as the Gilbert cell mixer
is, the topology still presents design challenges for microwave transceivers. In particular, the achievable dynamic range in a Gilbert cell mixer is primarily limited by the
linearity of a single HBT or BJT [62]. Another challenge of the standard Gilbert cell
mixer is the high input impedance created at the IF port of the circuit. This high
input impedance makes it difficult to match the IF port, which is desirable to allow
for a seamless integration between the up-conversion mixer and an IF band-pass filter
or balun.
A new up-conversion mixer circuit topology has been investigated to address the
limitations associated with the standard Gilbert cell mixer. This SiGe up-conversion
mixer is based on a standard Gilbert cell topology, but incorporates a novel commonbase series-connected triplet on the IF port, as seen in Figure 36. This circuit is the
simplest form of the triplet, in that it does not incorporate any offset mechanisms to
take advantage of the multi-tanh principle[62]. Each transistor associated with the
IF stage (Q1A-Q2C) has the same emitter area and bias current. The configuration
of the triplet has been further modified resulting in a common-base configuration,
utilizing the emitters of the bipolar transistors as the input terminals. This variation
58
Figure 36: Die photo (1.0 x 1.0 mm2 ) and conceptual schematic of the SiGe K-band
up-conversion mixer.
on the standard mixer topology allows for a matched impedance at the IF port, while
simultaneously enhancing the dynamic range and bandwidth of the mixer. The RF
output is taken single-ended, to eliminate the need for a high-frequency, low-loss,
high-linearity balun.
The differential IF input impedance (Zmix ) of the circuit is related to the transconductance (gm ), and the unity gain cut-off frequency (fT ) of transistors Q1A-Q2C,
as well as the frequency of operation. Assuming the current gain (?) is й 1 and
fT ? gm /(2?C? ) (where C? is the base-emitter capacitance of the device), then the
differential input impedance of the circuit can be written as
▓
│
6
1
Zmix =
.
gmQ1A 1 + jf /fT
(25)
Similarly, the effective transconductance (gmmix ) of the IF stage (assuming a differential input voltage and a single ended output current) is
▓
│
gmQ1A + gmQ1B + gmQ1C
,
gmmix =
6
(26)
which will simplify to gmQ1A /2 since the transistors are operating at the same bias
59
point.
The dynamic range of the mixer is dominated by the linearity of the input transistors (Q1A-Q2C) on the IF port. It has been shown that the compression point
of a bipolar transistor is related to a compression point voltage (V1dB ), in which
the transistor leaves the region of small-signal operation and experiences 1-dB gain
compression[62]. This compression point voltage is a result of the non-linearity associated with the transconductance of a bipolar transistor, expressed as
▓
│
2
1 qvbe 1 q 2 vbe
ic
= gm 1 +
+
+ ... ,
gm =
vbe
2 kT
6 (kT )2
(27)
where vbe is the ac voltage applied to the base-emitter junction, k is Boltzmann?s
constant, and T is temperature[6].
The input voltage applied to the IF stage of the series-connected triplet is divided
evenly across all six transistors, resulting in an effective compression point voltage
(V1dB?mix ) equal to six times the nominal V1dB for a single bipolar transistor. Transistors Q1B-Q2C degenerate the common-base differential pair created by transistors
Q1A and Q2A, resulting in
1
3
of the input voltage being dropped across the differential
pair of Q1A and Q2A (resulting in
1
6
of the input voltage being dropped across each
individual transistor). Similar analysis can be used on transistors Q1B-Q2C to verify
this reduction in voltage drop across their base-emitter junctions.
The IP1dB of the mixer can be approximated as
IP1dB =
2
V1dB?mix
.
RIN
(28)
Incorporating (25) and (28) results in an input referred 1-dB compression point of
IP1dB?mix =
gmQ1A 2
2
,
V1dB?mix = 6gmQ1A V1dB
6
(29)
where V1dB correlates to the 1-dB compression point voltage of an individual transistor.
60
The actual up-conversion of the IF output current (i.e. the collector currents of
Q1A-Q2C) to the RF output, and how this relates to the mixer?s conversion gain and
available output power is consistent with that of the standard Gilbert mixer. The
LO terminals of the mixer are driven differentially, and the RF output is matched
single-ended to a 50 ? load using passive elements. The dc bias currents of the
mixer are created using degenerated current mirrors, which are also used to create
the common-mode reference voltages for the LO stage and the IF stage.
6.3
Circuit Comparison
Simulation comparisons of the IF stage of the present work to that of the standard
differential pair, and the differential pair with resistive degeneration, have been investigated to gain insight into the benefits of the proposed topology. Total power
dissipation and collector current density was maintained for all three topologies to
allow for a fair comparison. The degeneration resistor value for the degenerated differential pair was chosen such that the effective transconductance of the circuit was
equal to the effective transconductance of the series-connected triplet. An example of
the simulation template can be seen in Figure 37, where two 1 GHz IF input signals
(180 degrees out of phase) were applied to the input terminals. Both signals were
driven with 50 ? sources, resulting in a differential impedance of 100 ?. The output
of the circuit is a single ended output current (sampled through a short), and then
injected into a 50 ? load via a current controlled current source (CCCS).
The simulation results for the three circuits are shown in Figure 38. Without the
use of any matching elements the common-base series-connected triplet is capable of
a matched differential impedance. The circuit can achieve a return loss greater than
10 dB for a total bias current ranging from 5.1 mA up to 17.4 mA, allowing for a
reasonable amount of design freedom. The high input impedance associated with the
61
Figure 37: Schematic of simulation template for IF stage simulations.
differential pair (equation 30),
Zdif f pair
▓
│
1
2?
=
gmQD1 1 + jf ?/fT
(30)
and the degenerated differential pair result in reflections at the IF port. Obviously
these circuits can be impedance matched with the use of passive elements, but this
comes at the expense of added area.
From (25) and (30), we can also observe the frequency dependence of the input
impedance for both circuits. The common-base series-connected triplet is capable
of maintaining a constant input impedance over a very wide frequency range (thus
maintaining a reasonable return loss over a wide frequency range). Whereas the
differential pair?s input impedance will vary at a frequency ? times lower.
Ideal inductors and capacitors were incorporated with the differential pair and
degenerated differential pair to impedance match them for the compression point
simulations. As seen from Figure 38, the current design is capable of a significantly
larger input 1-dB compression point than both the standard differential pair and
degenerated differential pair. Similar to the common-base series-connected triplet,
the differential pair?s input compression point is determined by the V1dB of the input
62
?5
40
Output Referred
30
?10
?15
?20
20
Input Referred
10
Return Loss (dB)
1?dB Compression Point (dBm)
0
?25
?30
Return Loss
Differential
Pair
Degenerated
Differential Pair
This Work
0
Figure 38: Simulation results comparing the performance of the IF stage of the
present work, to that of a standard differential pair, and a differential pair with
degeneration resistors.
transistors and can be expressed as
IP1dB?dif f pair
2 ? gmQD1 ? (V1dB )2
.
=
?
(31)
Comparing (29) and (31) (recalling that gmQD1 = 3*gmQ1A ) we can predict an
IP1dB?mix to be ? times larger than the IP1dB?dif f pair , which agrees with the simulation results. Also seen from Figure 38, the current work?s increase in dynamic
range does not come at the (undesirable) expense of available output power, but does
translate directly to a decrease in conversion gain.
The current work allows for an increase in dynamic range and improved IF port
return loss without the need for degeneration resistors or external matching elements.
The circuit accomplishes this without an increase in power dissipation or a reduction
in available output power. The circuit is well suited for dual-IF systems, where the
IF signal could be relatively high in frequency (> 2 GHz) or in systems requiring IF
63
RF Port Return Loss (dB)
IF Return Loss (dB)
18
16
14
12
10
8
6
4
2
0
Differential IF Port Return Loss
0
4.0
8.0 12.0 16.0
IF Frequency (GHz)
20.0
16
14
12
10
8
6
4
2
0
18
Single?ended RF Port Return Loss
20
22 24 26
28
RF Frequency (GHz)
30
Figure 39: Return loss performance for the K-band SiGe up-conversion mixer.
filtering before up-conversion.
6.4
Measured Performance
The circuit was fabricated in the Jazz SiGe120 technology and tested at wafer level,
using external baluns to drive the differential IF and LO terminals. One port of the
RF terminal was terminated into a 50? load and the other port was used as the
single-ended RF output. It is possible to take the output of the mixer differentially
and increase its gain by 3dB. However, this would require either the use of external
components or a silicon-based monolithic K-band balun or transformer. Although
this type of passive is possible in this technology, the significant loss associated with
it could out-weigh its benefits.
The differential S-parameters of the IF port were measured using the Agilent 4port system and demonstrated a differential IF return loss greater than 10 dB from
500 MHz to 20 GHz (Figure 39). This wide-band matching capability enabled the upconversion mixer to operate over a wide range of IF frequencies, with an IF bandwidth
from 1 GHz to 10 GHz. The S-parameters of the RF port were also measured and
demonstrated a return loss greater than 10 dB from 19.5 GHz to 26 GHz (Figure 39).
The mixer was biased from a 3.3 V supply, dissipating only 38mW of dc power.
64
25
2
20
1
15
0
10
?1
Conversion Gain
Lo to RF Rejection
?2
?3
18
5
IF = 1.25 GHz
LO Power = ?4 dBm
20
22
24
26
28
RF Frequency (GHz)
30
Lo to RF Rejection (dB)
Conversion Gain (dB)
3
0
32
Figure 40: Upper side band conversion gain and LO to RF isolation for the upconversion mixer.
The nominal testing configuration incorporated a 1.25 GHz IF input, with a 26.75
GHz LO input, resulting in a 28 GHz RF output. The mixer has a maximum upper
side band conversion gain of 1 dB, with a 3 dB bandwidth from 19 GHz to 31 GHz
(Figure 40) while maintaining an LO to RF isolation greater than 18 dB across the
band of operation. The up-conversion mixer also demonstrates a high dynamic range
as seen in Figure 41, achieving an IP1dB of -6.8 dBm, a maximum output power of
-5.8 dBm and an IIP3 of 2.2 dBm for a 28 GHz output signal. The circuit requires a
nominal LO drive power of -4 dBm and achieves a spur rejection better than 25 dBc
(Figure 42) when operated at the 1-dB compression point.
6.5
Performance Comparison
The performance of this up-conversion mixer has been compared to other mixers operating in similar frequencies of operation, as seen in Table 7. Although up-conversion
mixers based on III-V technologies (such as the commercially available HMC578LC3B
from Hittite [67]) can handle and deliver significantly more input and output power,
they also require significantly more dc power. Obviously these tradeoffs must be taken
into consideration when evaluating the full system performance.
65
?2
?6
?8
?10
10
Output P1dB = ?8.6 dBm
?12
?14
?16
?18
?20
RF = 28 GHz
IF = 1.25 GHz
LO Power = ?4 dBm
?22
?22 ?20 ?18 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2
Input Power (dBm)
0
2
IIP3 = 2.2 dBm
0
Poutmax = ?5.8 dBm
Output Power (dBm)
Output Power (dBm)
?4
?10
Fundamental Power
?20
?30
?40
?50
IM Power
fs1 = 1.245 GHz
fs2 = 1.255 GHz
LO = 26.75 GHz
LO Power = ?4 dBm
?60
4
?70
?22
?18
?14
?10
?6
?2
Input Power (dBm)
2
6
Figure 41: Output power and intermodulation power versus input power for the
up-conversion mixer.
Figure 42: Output spectrum for the K-band up-conversion mixer at the 1dB compression point for a 28 GHz output signal.
66
Table 7: Performance comparison of K-band up-conversion active mixers
Literature
Freq. of
CG IP1dB IIP3 Power
Technology
Operation
GHz
dB dBm dBm mW
This Work
19 - 31
-0.8 -6.8
2.2
38
SiGe (fT =150 GHz)
[63]
12 - 27
2.5
NR
-2.5
9.8
3-D MMIC on Si
(fT =40 GHz)
[64]
24 - 28
3
0
NR
770
PHEMT MMIC (PH25)
[65]
21 - 24
-6
2
NR
NR
AlGaAs/InGaAs
HJFET (fT =70 GHz)
[66]
35 - 65
-7
-17
-9
14
SiGe (fT =120 GHz)
[67]
24 - 33
13
1
NR
405
GaAS PHEMT MMIC
NR = Not Reported
It should also be noted that the Gilbert MICROMIXER [68] has recently been
proposed as a new mixer topology. This circuit utilizes a class-AB input stage, which
allows for an extremely high dynamic range [68]. Unfortunately, the output of this
circuit must be taken differentially in order to utilize the linearity capabilities [68].
Despite this caveat, a few up-conversion mixers operating at lower RF frequencies (<
6 GHz) have incorporated this topology [69], [70]. However for K-band frequencies,
the design of silicon-based differential to single-ended conversion circuits with highlinearity and phase-balance becomes much more challenging. The inclusion of these
circuits would likely come at the expense of additional power and die size, and may
not perform well enough to leverage the benefits of the MICROMIXER.
The up-conversion mixer presented here delivers competitive performance with
previously published works, in terms of conversion gain, frequency band of operation,
and power dissipation. The circuit achieved this performance without the use of IIIV technologies, post-processing steps, or the inclusion of large (and possibly lossy)
differential to single-ended conversion circuits.
67
CHAPTER 7
K-BAND POWER AMPLIFIER
7.1
Introduction to Microwave Power Amplifiers
Power amplifiers amplify and drive the desired output signal of a transceiver to the
antenna. The amplitude of this output signal must be high enough, such that the
signal is still detectable over the range (or distance) of the system. Generating this
large output signal becomes more challenging at higher frequencies of operation due
to an increase in parasitic losses, as well as a decrease in active device performance.
To date, most microwave PA?s are based on III-V technologies, which can operate
at high voltage levels (> 15 V) and deliver a significant amount of output power
[71], [72]. However, for automotive K-band radar systems, a fully-integrated silicon
solution is desired to help minimize system cost. Although there has been some
work investigating SiGe K-band power amplifiers [73]-[77], this is still a relatively
unexplored area, with significant room for improvement. This work will investigate
the capabilities of a K-band SiGe PA, focusing on high (> 18 dBm) output power
and high power added efficiency (PAE) performance.
7.2
Benefits of the Cascode Architecture
A simple common emitter topology and a cascode topology (Figure 43) are two standard power amplifier topologies. The common emitter topology utilizes a single transistor (or bank of transistors) to convert the input signal into current. The transistor
then drives this current into a passive matching network which enables maximum
voltage and current swing capabilities via impedance transformation. Similarly, the
cascode topology incorporates a drive transistor (Q1) to convert the input signal into
68
Figure 43: Example of common emitter and cascode power amplifier architectures
with voltage biasing.
current, and then utilizes a cascode (or buffer) transistor (Q2) to drive the current
into the passive matching network.
The maximum output voltage swing of both architectures is limited by the breakdown voltage associated with the SiGe HBTs. As stated in Chapter 2, the breakdown
voltage of a SiGe HBT is typically denoted by the BVCEO of the device and dominated by avalanche multiplication. However, this value assumes a current source (or
dc open) is driving the base of the device. If a voltage source is used to bias the
base of the device, the extra current created in the base region can be absorbed into
the base voltage bias [6]. The elimination of this extra current increases the voltage
swing capabilities of the HBT, roughly by a factor of two.
Obviously both topologies would benefit from this type of dc biasing configuration.
However, it has been shown that the breakdown voltage of a SiGe HBT is further
increased when the emitter is driven with a current source and the base is biased
with a voltage source [78]. Therefore, the voltage swing capabilities of the cascode
topology is even further increased. This can seen from simulated dc-IV characteristics
(Figure 44), which predicts a breakdown voltage of approximately 7V for the cascode
architecture and 3.5V for the common emitter architecture.
This increase in voltage swing allows the cascode architecture to operate at a
69
1000
800
600
400
200
0
AE = 0.12 x 10.16 x 20 хm2
Cascode Simulation
400
IC (mA)
IC (mA)
500
AE = 0.12 x 10.16 x 40 хm2
Common Emitter Simulation
300
200
100
0
1
2
3
VC (V)
4
0
5
0
1
2
3
4 5 6
VC (V)
7
8
9
Figure 44: Output characteristics of common emitter and cascode architectures
with voltage biasing.
significantly lower bias current to achieve the same amount of output power. As
stated earlier, the maximum output power a circuit can deliver is determined by its
voltage and current swing capabilities. For a PA biased in a class-A configuration,
this output power can be expressed as
PM AX =
1
1
(VCC ? VK ) О IM AX ? VCC О IM AX ,
4
4
(32)
where VCC is the supply voltage, VK is the knee voltage, and IM AX is the maximum
bias current. Using load line analysis, the optimum load resistance for maximum
output power can be approximated as,
ROP T =
2VCC
2(VCC ? VK )
?
.
IM AX
IM AX
(33)
As seen in Figure 44, the cascode architecture has approximately twice the voltage
swing capability as the common emitter architecture. This allows the circuit to
operate with half of the bias current (and therefore use half as many transistors)
and results in an optimum load resistance that is four times larger than the common
emitter topology.
70
7
Common Emitter Simulation
AE = 0.12 x 10.16 x 40 хm2
VCC = 2.1 V, ICC = 295 mA
6
5
Stability Factor
Stability Factor
7
4
3
2
1
0
0
10
20
30
40
Frequency (GHz)
5
4
3
2
1
0
50
Cascode Simulation
AE = 0.12 x 10.16 x 20 хm2
VCC = 4.2 V, ICC = 145 mA
6
0
10
20
30
40
Frequency (GHz)
50
Figure 45: Simulated K-factor versus frequency for common emitter and cascode
architectures biased for class-A operation.
Admittedly, this increase in optimum load impedance is negated at high frequencies of operation. Harmonic balance load-pull simulations predict essentially equivalent output power (24 dBm), efficiencies (28%), and optimum load impedances (2+5j)
for both topologies when operated at 24 GHz in a class-A mode of operation. However
the stability (or K factor) of the two architectures is significantly different, as seen in
Figure 45. The cascode architecture is un-conditionally stable for all load and source
impedances, whereas the common emitter topology has the potential for oscillations
at lower frequencies for certain termination impedances. These impedances can be
seen in Figure 46, where the source and load stability circles for the common emitter
topology are shown on the smith chart (the circuit is stable for impedance values
outside of the circles).
The regions of instability for the common emitter topology at 1 GHz are quite
problematic, since they occur for low impedance values. In order to obtain dc operation the circuit needs to be biased by a voltage source for both the collector
(output) and base (input) terminals, resulting in a low impedance termination for
both ports. Therefore, a feed inductor of 8 nH will be needed for the collector terminal and 2 nH for the base terminal to prevent oscillations from occurring. This
71
Frequency = 1 GHz
Common Emitter Simulation
AE = 0.12x10.16 x 40 хm2
VCC = 2.1 V, ICC = 295 mA
Stable Outside Circle
Load Circle
Source Circle
Figure 46: Stability circles for common emitter class-A amplifier simulated at 1
GHz.
will require significant space and likely degrade the circuit performance, due to the
finite Q and self-resonant frequency of high inductance on-chip spiral inductors. The
cascode topology will not need to provide such large value inductive chokes for the
dc biasing of the circuit due to its inherent stability. The cascode circuit design can
actually incorporate these passives into the matching structure for the circuit, giving
it a decided advantage.
7.3
SiGe Power Amplifier Design
A cascode power amplifier design was investigated (Figure 47) to determine the efficacy of silicon based microwave power amplifiers. The cascode topology provides high
isolation between the output and the input ports, and allows for an increase in the
available operating voltage for the circuit. This topology also allows the designer to
utilize higher breakdown transistors for Q2, increasing the available voltage swing at
the output. Higher speed (and therefore higher gain) transistors can still be utilized
72
Figure 47: Schematic of the 24 GHz SiGe power amplifier.
for the driving transistor (Q1) to simultaneously achieve both high gain and high
output power for the power amplifier.
The driving transistor (Q1) consists of 20 single-stripe high-speed (150 GHz fT )
0.20x10.16 хm2 HBTs, resulting in a total emitter area (AE ) of 40.64 хm2 . The top
transistor (Q2) consists of 16 multi-stripe medium-breakdown (75 GHz fT and 3.5
V BVCEO ) HBTs with a total emitter area of 113.8 хm2 . The significant increase in
AE for Q2 results from the decrease in current density for the medium-breakdown
transistor (as compared to the high-speed transistor).
The matching for the amplifier is accomplished with on-chip passives consisting
of MIM capacitors, spiral inductors, and thin-film microstrip transmission lines. The
microstrip transmission lines utilize the top-metal (M6) for the signal path and the
lower metals (M4-M1) shorted with vias for the ground path (Figure 48). These
transmission lines were designed and modeled using ADS and Momentum simulators
in conjunction with the SiGe120 design kit. Different types (i.e. high-pass and lowpass) of matching networks are used for the input and output of the amplifier to
improve the broadband stability. Additional de-coupling capacitors were also placed
on chip at the base of Q2 and at VCC to achieve a good on-chip RF short at high
73
Figure 48: Schematic cross-section of the thin-film microstrip transmission line.
frequencies.
The simulated circuit was biased from a 5.1 V supply, and dissipated 56 mA for
the nominal dc operation. The simulated gain of the amplifier was 12.2 dB, with an
OP1dB of 22 dBm, and a peak PAE of 14 %. The simulated circuit also demonstrated
a return loss greater than 10 dB for both the input and output ports at 24 GHz.
7.4
Measured Results
The 24 GHz SiGe power amplifier (Figure 49) was fabricated in the Jazz SiGe120
technology and measured at the die level with an Agilent 8510C VNA, a 8565E
spectrum analyzer, a 4419B power meter, a 8485A power sensor, and two frequency
sweepers. The circuit was biased from a 5.1 V dc power supply, with 1.9 V applied
to the base of Q2, and 0.88 V applied to the base of Q1, resulting in a nominal ICC
of 38mA.
The amplifier was biased in a class-AB mode of operation, allowing the ICC dc
current to increase with the input power, as seen in Figure 50. The circuit achieved
an OP1dB of 20 dBm, with a gain of 10 dB, and a PAE of 14% (Figure 51). It should
be noted that the cable losses of the test setup were accounted for in the power and
efficiency measurements, but the probe losses (estimated to be approximately 0.85
dB per probe at 24 GHz) were not, and thus the reported numbers are conservative.
74
22
20
18
16
14
12
10
8
6
4
2
0
?10
150
120
90
OP1dB = 20 dBm
ICC?1dB = 123 mA
Frequency = 24 GHz
?6
?2
2
PIN (dBm)
6
10
ICC (mA)
POUT (dBm)
Figure 49: Die photo of the 24 GHz SiGe power amplifier (0.85 x 1.2 mm2 ).
60
30
14
Figure 50: Output power and ICC versus input power for the 24 GHz power amplifier.
75
12
16
14
10
10
6
8
6
4
OP1dB = 20 dBm
Frequency = 24 GHz
2
0
0
2
4
6
8
10
12 14
POUT (dBm)
16
18
20
PAE (%)
Gain (dB)
12
8
4
2
0
22
Figure 51: Gain and power added efficiency versus output power for the 24 GHz
power amplifier.
The intermodulation distortion of the amplifier was also quantified, as seen in
Figure 52. The circuit demonstrated 18 dBc of rejection for the third-order intermodulation product for output powers as high as 13 dBm. The small-signal output
third order intercept point (OIP3 ) was calculated to be 15 dBm from the two-tone
measurements. Higher-order intermodulation products were also observed, as shown
in Figure 52, but remained lower in power than the third-order product.
The S-parameters of the circuit were measured at die level from 1 GHz to 40
GHz for accurate gain, return loss, and stability characterization. Both the input
and output of the power amplifier were matched to 50 ? at 24 GHz, as seen in
Figure 53, achieving a return loss better than 9 dB for both ports from 23 GHz to 26
GHz. The circuit also achieved a gain of 12 dB (Figure 53) for the nominal dc bias
point, with a 3-dB bandwidth from 23.3 GHz to 25.8 GHz. The discrepancy between
the measured gain from S-parameters and the measured gain originating from the
power measurements is attributed to probe loss, which was not accounted for during
the power measurements. The amplifier?s stability factor (K) was also measured for
several bias points (ICC = 38, 101, 151 mA), and observed to remain greater than
76
20
FS1
10
POUT (dBm)
0
2FS1?FS2
?10
?20
3FS1?2FS2
?30
?40
FS1
?50
?60
?14 ?12 ?10 ?8
2FS1?FS2
FS1 = 24.000 GHz
FS2 = 24.001 GHz
?6
?4 ?2 0
PIN (dBm)
2
3FS1?2FS2
4
6
8
Figure 52: Output power and intermodulation products versus input power for the
24 GHz power amplifier.
unity for all measured frequencies (1 GHz - 40 GHz).
The breakdown voltage of the amplifier was also characterized for different biasing
conditions. As shown in Figure 54, the circuit can operate with a VCC up to 8V when
biased with a dc voltage source at the base of Q2. However when a higher impedance
source is incorporated at the base of Q2 (i.e., a voltage source with 300 ? of series
resistance), the circuit can only withstand voltages of 6V before breakdown occurs.
These results highlight the voltage swing benefits that the cascode topology allows
for SiGe HBT power amplifiers.
Table 8: Performance comparison of silicon-based microwave power amplifiers.
Ref. Freq. POU T Gain PAE Size
Technology
2
GHz dBm
dB
%
mm
This
work
24
20
12
14
1.02 150 GHz SiGe
[74]
24
14.5*
7
4.5* 1.26 0.18 хm CMOS
[75]
24
12*
18
3*
NR
80 GHz SiGe
[76]
24
12
17.7
2.6
0.25
80 GHz SiGe
[77]
24
21*
19
13* 6.00 120 GHz SiGe
* Correlates to saturated output power.
77
0
14
?10
S11 & S22 (dB)
12
S11
S22
S21
10
?15
8
?20
6
?25
4
VCC = 5.1 V
ICC = 38 mA
VB2 = 1.9 V
?30
?35
12
S21 (dB)
?5
2
16
20
24
0
32
28
Frequency (GHz)
Figure 53: S11 , S22 , and S21 versus frequency for the 24 GHz power amplifier.
150
IB1 = 2.3 mA
120
ICC (mA)
IB1 = 1.7 mA
90
RB2= 0 ?
RB2= 300 ?
IB1 = 1.1 mA
60
IB1 = 0.7 mA
IB1 = 0.5 mA
30
IB1 = 0.3 mA
VB2 = 1.9 V
0
1
2
3
4
5
VCC (V)
6
7
8
9
Figure 54: Output characteristics for various biasing configurations for the 24 GHz
power amplifier.
78
7.5
Performance Comparison
The performance of this 24 GHz SiGe HBT power amplifier has been compared to
other silicon-based power amplifiers (Table 8) and is competitive with previously
published SiGe power amplifiers in terms of POU T , PAE, and total die size. As
expected, the present SiGe PA does not out-perform PA?s based on GaAs pHEMT
technology [71] or InP DHBT [72] technology. However the present solution is 100%
Si foundry compatible, and thus should offer a path to low-cost, highly integrated
solutions. In addition, the performance of microwave SiGe HBT PAs can be further
enhanced using more advanced layout techniques to achieve better power combining
and overall passive performance (as demonstrated in [77]), as well as targeting more
aggressive PA topologies (such as class E or F designs). These improvements will
help close the gap between SiGe and III-V power amplifier performance, enabling
silicon-germanium technology to be utilized in emerging microwave applications.
79
CHAPTER 8
SUBSTRATE COUPLING
8.1
Introduction to Substrate Coupling for Silicon Based Technologies
Silicon-germanium HBT devices are fabricated on a lossy silicon substrate along with
their CMOS counter-parts and passive structures. This lossy substrate can hinder a
circuits performance by shunting (or stealing) energy from critical portions of a circuit,
thus lowering the signal level by unintentional and undesirable means. This lossy
silicon substrate can also enable coupling to occur between two separate circuits or
devices on the same die. Depending on the magnitude of this unintentional coupling,
it can lead to excessive feedback or oscillations, as well as spur generation. There
has been significant research on the topic of substrate coupling for different silicon
technologies over the past years, focusing on the coupling of digital signals [79], the
modeling of the substrate [80]-[82], and the coupling of RF signals via the substrate
[83]-[85].
Techniques such as the incorporation of p+ guard rings, the use of extra deep
trench isolation structures, and controlling the physical placement of different circuits
are general guidelines designers use to help minimize the effects of substrate coupling
[86]. However unless the specific path of coupling is understood, these techniques can
become quite ineffective and result in wasted space. Substrate modeling tools have
also been developed, but still have not found their way into mainstream design.
Obviously the ability to model and predict the effects of substrate coupling can be
extremely beneficial for any monolithic design. However, as will be discussed in this
chapter, substrate modeling tools do not lend themselves to large scale monolithic
80
rf design. This chapter analyzes substrate coupling from a measurement standpoint,
focusing on measured results for substrate characterization, and test cases demonstrating circuit susceptibility to substrate noise and circuit-to-circuit coupling via the
substrate.
8.1.1
Overview of Substrate Modeling
Most SiGe BiCMOS processes are based on a p-type bulk substrate, with a resistivity on the order of 10 ?-cm. The majority of the tools developed for modeling a
silicon substrate utilize a mesh of impedances to represent the substrate, which are
then connected to active and passive circuit components. This mesh of impedances
originates from the physical and material specifications of the substrate. The combination of Poisson?s equation, the continuity equation for electrons and holes, and the
assumption that the substrate can be modeled as several layers of dielectric material
with varying dielectric constants [87], yields the equation
»sub
1
?
(4 ? E) +
4 ? E = 0.
?t
?sub
(34)
Equation 34 can be solved in differential form, with the electric field vector (E)
approximated using the finite difference method [87], as well as in integral form, with
the electrostatic potential determined from the boundary element method. The finite
difference method generally requires significantly more computational resources, but
can result in more accurate results [87]. The boundary element method utilizes a
substrate Green?s function [88] and is considered the more efficient methodology for
modeling and simulating the substrate.
This mesh of substrate impedances can be further simplified depending on the
doping of the substrate and the frequency of interest. At low frequencies of operation the substrate can be modeled as a simple resistive mesh, as opposed to a
resistor-capacitor (RC) mesh. This simpler resistive mesh can be used at frequencies
81
lower than the substrate?s cut-off frequency (fc ), where the capacitive portion of this
impedance is negligible[82]. At frequencies at or above this cut-off frequency, the RC
model is needed, essentially doubling the number of components needed in the mesh
of impedances used to model the substrate.
This cut-off frequency is related to the resistivity (?sub ) and permitivity (»sub ) of
the substrate [82], defined as
fc =
1
2??sub »sub
.
(35)
As seen from equations 34 and 35, detailed characterization of the substrate from
the surface down to the back side is needed to accurately capture the magnitude and
frequency response of substrate coupling in a silicon based technology.
The two primary challenges facing substrate modeling tools are versatility and
efficiency. Substrate coupling is a problem for both CMOS and SiGe BiCMOS technologies, however the substrate profiles for these technologies can be quite different.
Details such as backside metalization, channel stop implants, epi-layers, substrate
thickness, and substrate doping level can vary significantly between a pure CMOS
technology and a SiGe BiCMOS technology. Therefore, the methodology and modeling tools must be tailored to each technology in order to accurately capture the
coupling that occurs via the substrate.
The other hurdle substrate modeling tools face are the computational resources
(i.e. CPU time and memory) required for extraction and simulation. Even though
most tools are based on the boundary element method, and may include windowing
techniques [87] or matrix simplification techniques [88] to further enhance simulation
efficiency, substrate modeling tools are still under utilized due to the large simulation
times and a lack of confidence of the tools ability at microwave frequencies.
82
Figure 55: Conceptual layout of the substrate characterization test structure.
8.2
Substrate Coupling Characterization
To gain further insight into substrate coupling for silicon technologies, substrate characterization structures were fabricated and tested using the Jazz SiGe120 technology.
These structures can be used to draw comparisons between different isolation schemes
available in the technology, as well as quantify the distance dependence of coupling.
The nominal structure used for this study consisted of two ac ground-signal-ground
(G-S-G) pad sets, with the signal connected to a large 130хm by 120хm "paddle,"
and a separation distance of 100хm between paddles. Half of the ac test structure
is depicted in Figure 55. The injection paddles consist of an n+ region that is based
on the same processing steps associated with the sub-collector formation of a SiGe
HBT, and are surrounded by deep trench isolation and a p+ substrate contact ring
(also consistent with the HBT structure).
One isolation scheme investigated was a "p-ring", which utilized a p+ substrate
contact ring running down the center of the structure. Another scheme studied was
a "DT-ring", consisting of two p+ substrate contact rings with two deep trench rings
sandwiched inside, and a single n+ sub-collector ring in the center. Both types of
83
guard rings were tied to the ground paths of the test structure. In addition, a nominal
substrate characterization structure with a spacing of 50 хm was fabricated and tested
to assess the effects of separation distance on substrate coupling.
8.2.1
Substrate Measurements
The structures were measured using an 8510C vector network analyzer (VNA) with
LRRM calibration, with the pad parasitics de-embedded. The resulting S21 and Y21
of these structures are depicted in Figures 56 and 57. As seen in the S21 plot, there
is a slight resonance or notch around 30 GHz for all of the test structures. This is
believed to be a layout or de-embedding issue, as opposed to an indication of some
sort of resonance in the substrate itself. It should also be mentioned that the increase
of isolation at lower frequencies ( < 1 GHz) is related to the injection network, as
opposed to the behavior of the substrate. The substrate injection network utilizes an
un-biased p-n junction that is capacitively coupled to the substrate. Therefore, it is
not surprising that these structures have a series-capacitance like behavior (for the
S21 and Y21 ) at lower frequencies.
It is also interesting to note that there is essentially equal improvement in isolation
with the incorporation of either guard ring type. This is contrary to what one might
expect, since the DT-ring structure penetrates deeper into the substrate than the
p-ring structure. This highlights one of the challenges of substrate coupling in silicon
technologies, in that the signal can travel in the lower region of the substrate. This
makes it difficult to shunt-out or block unwanted high frequency signals with typical
processing steps. Figure 57 also demonstrates the significant increase in coupling at
frequencies above a few gigahertz.
84
?30
S21 (dB)
?40
?50
Nominal Structure
50 хm Structure
p?ring Structure
DT?ring Structure
?60
?70
0.1
1
Frequency (GHz)
10
50
Figure 56: Measured S21 of the substrate characterization test structures.
Magnitude of Y21 (1/?)
5x10?3
Nominal Structure
50 хm Structure
p?ring Structure
DT?ring Structure
1x10?3
1x10?4
5x10?5
1
2
10
Frequency (GHz)
20
50
Figure 57: Measured Y21 of the substrate characterization test structures.
85
Figure 58: Model for substrate characterization structure.
8.2.2
Substrate Modeling
A preliminary semi-physical model for the substrate characterization structure has
been investigated (Figure 58), using a methodology similar to that of [80]. Initial values for this model were determined from the electrical specifications of the technology,
but final values were determined from the measured data. All of the impedances used
to model the substrate (ZV 1 , ZV 2 and ZC ) maintained the same RC time constant.
This time constant was consistent with the substrate?s cut-off frequency (fc ) defined
as
fc =
1
2??sub »sub
,
(36)
where ?sub is the substrate resistivity and »sub is the substrate and permitivity [82].
The S11 and S22 of the structure are dominated by the injection capacitance of the
un-biased p-n junction (Cinj ), the parasitic capacitance of the deep trench (CDT ), the
parasitic resistance of the ground trace (Rring ), and the substrate impedance itself
(ZV 1 and ZV 2 ). The optimization of these parameters allow for good model to data
correlation for the S11 parameter, as seen in Figure 59.
The coupling between the two injection networks is determined from ZC and the
ratio of ZV 1 to ZV 2 , as well as the loading effects of the injection network itself. The
distance dependence of the substrate coupling is determined by the ZC impedance,
86
Measured Data
Simulation of Model
Figure 59: Correlation between measured data and substrate model for S11 .
and how this impedance changes as the separation distance changes.
It was shown in [87] that the impedance matrix between two surface-panel areas
(i and j), separated by a distance "d", can be represented as,
zii = K1
(37)
zjj = K2
(38)
zij (d) = k0 +
k1 k2
km
+ 2 + ... + m
d
d
d
(39)
with K1 , K2 , ki , and m defined as constants based on technology parameters and curve
fitting. Assuming a large separation distance and that the coupling between the two
surface-panels (or injection networks) is small compared to their shunt impedance,
results in
Yij =
?zij
?(k0 + k1 /d)
?
.
zii zjj
K1 K2
87
(40)
0
Phase of Y21 (degrees)
Magnitude of Y21 (1/?)
1x10?3
50 хm Structure
1x10?4
100 хm Structure
?45
100 хm Structure
?90
?135
Measured Data
Simulation of Model
Measured Data
Simulation of Model
?5
1x10
0.1
0.5
1
5
Frequency (GHz)
10
50
?180
0.1
0.5
50 хm Structure
1
5
Frequency (GHz)
10
50
Figure 60: Correlation between measured data and substrate model for the magnitude and phase of Y21 .
With this approximation, one can assume a linear relationship between the ZC term
and the separation distance of the two coupling structures. This linear approximation
agreed well with the 100хm and 50хm measured results, yielding good correlation
between the simulated model and measured data (Figure 60).
8.3
Circuit Sensitivity to Substrate Noise
Although substrate characterization structures give insight into the magnitude and
frequency response of substrate coupling, they do not give insight into how substrate
noise or substrate coupling will actually impact a circuit. To do this, one can simply
inject signal into the substrate and observe the output of a critical or sensitive circuit,
looking for a degradation of performance.
To investigate a circuit?s sensitivity to substrate noise, two different microwave
VCOs were fabricated and tested utilizing the Jazz SiGe120 technology. Voltage
controlled oscillators are excellent circuits for substrate coupling investigations, since
they are notoriously sensitive to any external sources of noise. As seen from Figure 61,
the substrate characterization structures were incorporated in the top-level layout, to
allow the injection of a signal into the substrate while simultaneously monitoring the
VCO?s output.
The two circuits were based on a negative resistance topology (Figure 61), with
88
Figure 61: Die photo of the substrate characterization structures with VCO designs,
and simplified circuit schematic of the inductor-based VCO.
Table 9: Measured performance of microwave VCOs
Inductor Microstrip
Parameter
Units
VCO
VCO
Frequency
GHz
22.6
26.3
Output Power
dBm
-5.6
-7.6
Phase Noise
@ 1MHz offset
dBc/Hz
-104
-100
Bandwidth
MHz
280
260
Core
Power Dissipation
mW
36.3
36.3
identical bias conditions, device geometries, and layout. The circuits only differed in
the design of the resonant tank circuit [5]. The inductor-based VCO incorporated
two spiral inductors for its tank circuit, whereas the microstrip VCO incorporated
two thin film transmission lines acting as inductive elements [5]. The performance of
these microwave VCOs is summarized in Table 9, along with phase noise plots and
output spectrum plots in Figures 62 and 63.
A single tone signal (finj ) was injected into the substrate by way of the substrate
characterization structures located 1.3 mm from the VCO center [5]. An injected
89
Figure 62: Spectrum photo and phase noise plot for the inductor-based VCO.
Figure 63: Spectrum photo and phase noise plot for the microstrip-based VCO.
90
Figure 64: Spectrum plot of inductor VCO with -7 dBm of injected signal applied
at 20 MHz offset from fOSC with Vcontrol =0.
power level of ?7 dBm was used for the majority of the noise injection testing. Signal
coupling was observed for both VCOs, with the injected signal appearing as a pair
of spurs in the output spectrum of the VCO (Figure 64) and a degradation of phase
noise performance at an offset of fOSC -finj .
The coupling of this injected signal was much larger for the inductor based VCO
than the microstrip based VCO, as shown in Figure 65. Also, the magnitude of the
coupled signal increased linearly with the increase of injected input power (at least for
input powers up to 7 dBm). It was also observed that the magnitude of the coupled
signal was greatest at injected frequencies close to the VCO?s oscillation frequency
(fOSC ). As shown in Figure 65, the magnitude of the coupled signal decreases at
a rate of ?20 dB/decade as the injected signal is swept away from the oscillation
frequency [5]. This behaviour is expected, since the loop gain of the oscillator is
greatest at its frequency of oscillation and decreases for frequencies offset from its
91
Coupled Power (dBm)
?15
finjected = fOSC + 20 MHz
VTune = 0 V
LC fOSC = 22.59 GHz
TL fOSC = 26.31 GHz
?25
?35
?45
Inductor VCO
Microstrip VCO
?55
?20
?15
?10
?5
0
Injected Power (dBm)
Coupled Power (dBm)
10
Pinjected = ?7.33 dBm
LC fOSC = 22.59 GHz
TL fOSC = 26.31 GHz
VTune = 0 V
?20
Slope =
?25 dB/Decade
?30
5
?40
Slope =
?20 dB/Decade
?50
?60
Inductor VCO
Microstrip VCO
5
10
50
Offset Frequency from fOSC (MHz)
100
Figure 65: Variation in coupled power present at the VCO output versus injected
power and frequency offset between oscillation frequency and injected frequency.
fOSC .
The magnitude of the substrate noise coupling also appeared to have a strong
dependence on the control voltage (Vcontrol ), as shown in Figure 66 [5]. Since coupling
was present for both the inductor based VCO and the microstrip based VCO, one can
infer that the spiral inductors are not the only circuit components in which coupling is
occurring. It is very likely that the buried-layer varactor incorporated in both designs
is sampling noise from the substrate and injecting it into the feedback loop of the
VCO. These findings magnify the potential for system level performance degradation
due to undesirable coupling via the substrate.
92
Coupled Power (dBm)
?20
?30
?40
?50
Inductor VCO
Microstrip VCO
finjected = fOSC + 20 MHz
Pinjected = ?7.5 dBm
?60
0
0.5
1
1.5
2
2.5
Control Voltage (V)
3
3.5
Figure 66: Power coupled to the output of the inductor and the microstrip VCO
versus Vcontrol with injected signal 20 MHz offset from fOSC .
8.4
Circuit-to-Circuit Coupling via the Substrate
It is apparent that a circuit can suffer performance degradation from the coupling of
unwanted signals via the substrate. However the next question is, whether this same
effect will occur if the substrate noise is coming from an actual circuit as opposed to
a substrate injection network. To facilitate this investigation, a case study will be
presented demonstrating the magnitude of substrate coupling between two circuits
fabricated on the same silicon die and operating concurrently.
8.4.1
Case Study: PA to VCO Substrate Coupling at K-Band
To demonstrate the potential for substrate coupling to occur between two circuits,
a K-band SiGe HBT power amplifier has been fabricated on the same silicon die as
a K-band SiGe HBT VCO (Figure 67). The power amplifier is based on the same
topology, design, and layout as presented in Chapter 7, and the VCO is based on
the same topology, design, and layout as the inductor based VCO presented in the
previous section. The circuits were fabricated using the Jazz SiGe120 technology
(Figure 68), with the center of the power amplifier approximately 1mm from the
center of the VCO.
93
The power amplifier was given its own VCC supply, and biasing pads and traces.
The GND of the power amplifier was also routed on its own metal bus and input
into the circuit with its own pad (Figure 68). However the GND bus of the power
amplifier was connected to the substrate, creating a parasitic path to the VCO. The
VCO was also given its own VCC supply, and biasing pads and traces. Again, the
GND metal traces of the VCO were only connected to the VCO circuit itself, but it
too was connected to the silicon substrate. Therefore, the GND traces of both circuits
were isolated from each other from a metal point of view, but were connected via the
substrate.
The circuit was tested in a shielded room with two spectrum analyzers, a signal
generator, and several dc power supplies, as seen in Figure 69. The output of the VCO
was taken differentially and converted to a single-ended signal via a 180? hybrid. The
cable and external hybrid losses were accounted for in the measurement results, and
all of the power levels were referenced to the spectrum analyzer connected to the
VCO output.
The nominal testing configuration for the power amplifier consisted of a 5 V bias
applied to the VCC , 1.8 V applied to VB2 , and 0.865 V applied to VB1 , resulting in
a PA ICC current of 43 mA. An input signal was also applied to the input of the
PA, with an input frequency (fin ) of 22.78 GHz and an input power level (Pin ) of
-7.8 dBm, resulting in a PA output power of 1.3 dBm. The VCO was biased from a
3.0 V supply and an input reference current of 1.55 mA was used to bias the circuit,
resulting in a total VCO current draw of 22mA. The control voltage of the VCO was
also biased to 3.0 V, resulting in an oscillation frequency (fosc ) of 22.68 GHz and an
output power of -1.8 dBm. The output spectrum of the VCO and PA when operated
at the same time and on the same die can be seen in Figures 70 and 71.
As seen from Figure 70, there are two spurs (located at fin and 2fosc ? fin ) present
in the VCO?s output spectrum. This behaviour agrees with the results reported in
94
Figure 67: Schematic of 24 GHz power amplifier and 23 GHz VCO fabricated on
the same die.
95
Figure 68: Die photo of 24 GHz power amplifier and 23 GHz VCO fabricated on
the same die.
Figure 69: Block diagram of set up for testing of VCO and power amplifier.
96
Figure 70: Spectrum photo of VCO output when both the VCO and PA are operating at the same time and on the same die.
Figure 71: Spectrum photo of PA output when both the VCO and PA are operating
at the same time and on the same die.
97
the previous section and suggests that the power amplifier is coupling signal into
the VCO via the substrate. A small spur was also observed in the PA output at a
frequency fosc . It is difficult to determine (at this stage) whether this spur is some
sort of non-linear effect, probe-to-probe coupling, or an example of signal coupling
through the substrate.
Different testing setups were investigated, with the results reported in Tables 10
and 11. In all of these testing configurations, the PA input frequency (fin ) was set to
be 100 MHz higher than the VCO frequency of oscillation (fosc ).
The first row of Table 10 reports the coupled power (VCO Pcple ) present at the
VCO output and the coupled power (PA Pcple ) present at the PA output for the
nominal testing configuration (i.e. both the PA and VCO on). The data in the
second row correlates to the setup in which the VCO is un-biased, but with the PA
biased and a PA input signal applied. As seen from these results, there is an 18
dB decrease in coupled signal appearing at the VCO output. This confirms that the
spurs present at the VCO output for the nominal case are a result of the feedback
loop amplification associated with the VCO circuit. These results also confirm that
the small spur observed at the output of the PA for the nominal testing case was due
to the VCO circuit (with the VCO circuit turned off, this spur no longer exists).
A 9 dB reduction of coupling is also observed when the PA is un-biased, but the
input signal of the PA is still applied to the input pad (as reported in the third row
of Table 10). This result verifies that the coupled signal apparent at the VCO output
is not merely due to coupling between the PA input probe and the VCO. The biasing
and amplification of the PA significantly increases the coupling between these two
circuits.
To further scrutinize these observations, the testing configuration was changed
again with the results reported in Table 11. Instead of applying signal to the input of
the power amplifier, signal was applied to the output of the power amplifier (PA-OUT
98
Table 10: Coupling Results for Different Measurement Configurations for PA to
VCO Coupling Study
Set Up
VCO VCO PA
PA
PA
Freq. VCO PA
Info
fosc
Pout
Pin
Pout
fin
Delta Pcple Pcple
GHz dBm dBm dBm GHz
MHz dBm dBm
VCO ON
PA ON
22.685 -1.8
-7.8
2.0 22.783
98
-31.1 -49
VCO OFF
PA ON
NA
NA
-7.8
1.3 22.783 NA -59.5 NA
VCO ON
PA OFF
22.697 -2.2
-7.8 -41.0 22.796
99
-40.1 NR
NR = Not Reported, NA = Not Applicable
Table 11: VCO Coupling Results when Injected Signal is Applied to the PA Output
Set Up
VCO PA-OUT
PA
Freq. VCO
Info
fosc
Papplied
fin
Delta Pcple
GHz
dBm
GHz
MHz dBm
VCO ON, PA OFF
PA-OUT probe elevated
22.694
2.17
22.794 100 -40.0
VCO ON, PA OFF
PA-OUT probe down
22.694
2.17
22.794 100 -47.5
VCO ON, PA pseudo-ON
PA-OUT probe down
22.694
2.17
22.794 100 -44.5
PA pseudo-ON correlates to the following PA biasing conditions:
VCC = 4V, VB2 = 1.8V, VB1 = 0V, no power amplifier ICC current.
Papplied ). This applied signal was increased in power level, to make it closer in value
to the output power of the PA in the nominal configuration. Three cases for this
configuration were tested. One with the applied probe elevated and slightly offset
from the PA output pad, one with the applied probe touched down on the PA output
pad, and one with the probe down and the cascode transistor in the PA slightly biased
(but with no dc collector current).
As seen from all of these testing scenarios, the magnitude of coupled power measured at the VCO output is significantly less than what was experienced in the nominal
test case. This confirms the theory that the coupling from the PA to the VCO is not
99
2
0
?30
?2
?4
?40
?50
?6
VCO on
fosc = 22.68 GHz
?8
PA on
Pin = ?7.33 dBm
Sweep fin
?60
20
PA Output Power (dBm)
VCO Coupled Power (dBm)
?20
?10
100
200
fin ? fosc (MHz)
1000
?12
2000
Figure 72: Coupled power measured at VCO output and PA output power versus
frequency offset.
simply probe-to-probe coupling. If this had been the primary coupling mechanism,
then the magnitude of coupling shown in Table 11 would correlate to the magnitude
of coupled power observed at the VCO output for the nominal case. Therefore, we can
conclude that the coupled power at the output of the VCO is due to signal injected
into the substrate by the power amplifier.
Although these results seem disastrous for any microwave silicon-based monolithic
design, the incorporation of frequency planning can significantly improve the situation. As seen from Figure 72, when the PA input frequency (fin ) is varied (resulting
in an increase in frequency offset between the fosc and fin ) the magnitude of coupled
power present at the VCO output decreases significantly. This agrees with previously reported results [5], and highlights one of the benefits of frequency planning for
monolithic microwave design.
100
8.5
Summary of Substrate Coupling Concerns
This work has demonstrated the potential for substrate noise to couple into sensitive circuits, as well as the possibility for two circuits to couple to each other when
fabricated on the same die and operating at the same time. However, it has also
been shown that substrate coupling will decrease as the separation distance between
injection networks is increased, and that frequency planning of sensitive circuits can
also minimize the impact of substrate coupling.
All of this work was completed on bare die approximately 11 mils thick and with no
backside metalization. Needless to say, it is likely these results will change when the
die are packaged and if the backside is metalized. Previous studies have demonstrated
that highly-doped lower layers of the substrate can also act as a coupling path for
signals in a silicon process [89]. This new coupling path can significantly change the
magnitude and distance dependance of the coupling. Also, bondwire inductance can
increase the impedance between the IC ground and the true ground of the system.
This increase in impedance will also affect the magnitude and frequency response of
substrate coupling.
Further studies are needed to truly understand all of the potential coupling paths
for SiGe BiCMOS monolithic systems operating at these frequencies of operation.
However, the work presented here has given useful insight into the potential for this
problem and how it may manifest itself in a given system.
101
CHAPTER 9
CONCLUSION
9.1
Contributions
The contributions of this work can be summarized as follows:
1. A detailed analysis of both CMOS and HBT based phase shifter design for Xband applications has been presented. It was shown that a phase shifter based
on SiGe HBT switches will typically have better bandwidth, insertion loss, and
possibly noise figure performance. However, a CMOS implementation will have
significantly less power dissipation and has the potential to be smaller in size.
These observations were further demonstrated by the comparison of two 4-bit
digital X-band phase shifters.
2. A high-linearity 5-bit digital X-band phase shifter was demonstrated in a commercially available SiGe BiCMOS technology. This phase shifter was based on a
high-pass/low-pass topology and targeted specifications for phased array radar
T/R modules. The impact of this circuit on the overall system noise figure and
linearity performance was examined, along with a comparison to previously
published phase shifters in commercially available SiGe BiCMOS technologies.
3. A SiGe BiCMOS X-band down-conversion mixer demonstrating a conversion
gain of 12.6 dB, noise figure of 11.9 dB, and IIP3 of -0.45 dBm was presented.
The mixer core dissipated only 12 mW of power and achieved an LO to RF
isolation of 25 dB across the band of operation. The circuit targeted a balance
set of performance metrics and was compared to other silicon based downconversion mixers in this frequency of operation.
102
4. A new down-conversion mixer figure-of-merit has been proposed. This new
FOM takes into account gain, noise figure, linearity, power dissipation, and
isolation. This comprehensive analysis of mixer performance enables designers
to quantify the entire functionality of the mixer, as opposed to only examining individual capabilities. This FOM has the added benefit of accounting for
signal leakage between ports, which could be overlooked in other mixer figureof-merits.
5. A high-linearity K-band SiGe BiCMOS up-conversion mixer has been presented.
This mixer utilizes a series-connected common-base triplet to achieve a significant improvement in allowable input power. This increase in input power
enables a larger signal-to-spur ratio capability at the input of the mixer, in an
attempt to limit the magnitude of unwanted spurs in the transmitted signal.
6. The analysis and design of a 20 dBm, 14 % PAE, 24 GHz SiGe HBT power
amplifier has been presented. The circuit utilized a cascode topology to achieve
higher output voltage swing capabilities while simultaneously addressing stability issues at lower frequencies. The circuit also benefited from the use of
both high-speed and high-breakdown devices strategically placed in the design
to achieve even better performance.
7. Preliminary investigations of substrate coupling, substrate-to-circuit coupling,
and circuit-to-circuit coupling has been presented for the Jazz SiGe120 technology. These studies were completed on bare die with no backside metalization, and highlighted the significant challenges associated with the integration
of large-signal noisy circuits with sensitive circuits operating at the same frequency.
103
9.2
Future Work
The work presented here has established several good starting points for future work.
These additional studies are discussed here.
Further work is needed on the optimization and analysis of passive structures for
these frequencies of operation. As discussed earlier, the use of baluns, transformers,
and other metal structures can be extremely beneficial to rf circuit design. These
structures also assist in the incorporation of differential designs, which can leverage
the symmetry and balanced design of a circuit to achieve even better performance.
The inclusion of full-wave solvers into a standard design flow is also needed to enhance
the simulation capabilities of the design tools.
The inclusion of the phase shifters presented here, with the other T/R module
components (such as the LNA, T/R switch, and power amplifier) would also be
beneficial. As full system level integration is pursued, there will be modest design
changes needed for all of these blocks to achieve the desired performance for the
full module. Special attention will need to be given to the modal transitions of this
module, as it will incorporate many rf blocks onto a single die.
Lastly, further studies into substrate coupling would be of value. An attempt was
made in this work to determine the noise injected into the substrate by the power
amplifier. Unfortunately, the probe-to-probe coupling for this test setup was too
large to allow for viable conclusions. The incorporation of shielding around the rf
probes would significantly reduce this probe-to-probe coupling and may prove helpful
in future substrate coupling studies. Also, the impact of packaging and backside
metalization needs to be examined to increase the relevance of these types of studies.
104
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112
VITA
Jonathan P. Comeau was born in Baltimore, MD in 1975. He received the B.S. degree
in electrical engineering from Union College, Schenectady, NY in 1997, and the M.S.
degree in electrical engineering from the University of Michigan, Ann Arbor, MI in
1999.
He worked for Agere Systems as an Analog IC Designer from 1999 - 2002, where
he focused on preamplifer design for hard disc drive applications. Since fall of 2002,
he has been a doctoral student at the Georgia Institute of Technology, Atlanta, GA,
working on silicon-germanium circuits for microwave, radar, and space applications.
113
ple common emitter topology and a cascode topology (Figure 43) are two standard power amplifier topologies. The common emitter topology utilizes a single transistor (or bank of transistors) to convert the input signal into current. The transistor
then drives this current into a passive matching network which enables maximum
voltage and current swing capabilities via impedance transformation. Similarly, the
cascode topology incorporates a drive transistor (Q1) to convert the input signal into
68
Figure 43: Example of common emitter and cascode power amplifier architectures
with voltage biasing.
current, and then utilizes a cascode (or buffer) transistor (Q2) to drive the current
into the passive matching network.
The maximum output voltage swing of both architectures is limited by the breakdown voltage associated with the SiGe HBTs. As stated in Chapter 2, the breakdown
voltage of a SiGe HBT is typically denoted by the BVCEO of the device and dominated by avalanche multiplication. However, this value assumes a current source (or
dc open) is driving the base of the device. If a voltage source is used to bias the
base of the device, the extra current created in the base region can be absorbed into
the base voltage bias [6]. The elimination of this extra current increases the voltage
swing capabilities of the HBT, roughly by a factor of two.
Obviously both topologies would benefit from this type of dc biasing configuration.
However, it has been shown that the breakdown voltage of a SiGe HBT is further
increased when the emitter is driven with a current source and the base is biased
with a voltage source [78]. Therefore, the voltage swing capabilities of the cascode
topology is even further increased. This can seen from simulated dc-IV characteristics
(Figure 44), which predicts a breakdown voltage of approximately 7V for the cascode
architecture and 3.5V for the common emitter architecture.
This increase in voltage swing allows the cascode architecture to operate at a
69
1000
800
600
400
200
0
AE = 0.12 x 10.16 x 20 хm2
Cascode Simulation
400
IC (mA)
IC (mA)
500
AE = 0.12 x 10.16 x 40 хm2
Common Emitter Simulation
300
200
100
0
1
2
3
VC (V)
4
0
5
0
1
2
3
4 5 6
VC (V)
7
8
9
Figure 44: Output characteristics of common emitter and cascode architectures
with voltage biasing.
significantly lower bias current to achieve the same amount of output power. As
stated earlier, the maximum output power a circuit can deliver is determined by its
voltage and current swing capabilities. For a PA biased in a class-A configuration,
this output power can be expressed as
PM AX =
1
1
(VCC ? VK ) О IM AX ? VCC О IM AX ,
4
4
(32)
where VCC is the supply voltage, VK is the knee voltage, and IM AX is the maximum
bias current. Using load line analysis, the optimum load resistance for maximum
output power can be approximated as,
ROP T =
2VCC
2(VCC ? VK )
?
.
IM AX
IM AX
(33)
As seen in Figure 44, the cascode architecture has approximately twice the voltage
swing capability as the common emitter architecture. This allows the circuit to
operate with half of the bias current (and therefore use half as many transistors)
and results in an optimum load resistance that is four times larger than the common
emitter topology.
70
7
Common Emitter Simulation
AE = 0.12 x 10.16 x 40 хm2
VCC = 2.1 V, ICC = 295 mA
6
5
Stability Factor
Stability Factor
7
4
3
2
1
0
0
10
20
30
40
Frequency (GHz)
5
4
3
2
1
0
50
Cascode Simulation
AE = 0.12 x 10.16 x 20 хm2
VCC = 4.2 V, ICC = 145 mA
6
0
10
20
30
40
Frequency (GHz)
50
Figure 45: Simulated K-factor versus frequency for common emitter and cascode
architectures biased for class-A operation.
Admittedly, this increase in optimum load impedance is negated at high frequencies of operation. Harmonic balance load-pull simulations predict essentially equivalent output power (24 dBm), efficiencies (28%), and optimum load impedances (2+5j)
for both topologies when operated at 24 GHz in a class-A mode of operation. However
the stability (or K factor) of the two architectures is significantly different, as seen in
Figure 45. The cascode architecture is un-conditionally stable for all load and source
impedances, whereas the common emitter topology has the potential for oscillations
at lower frequencies for certain termination impedances. These impedances can be
seen in Figure 46, where the source and load stability circles for the common emitter
topology are shown on the smith chart (the circuit is stable for impedance values
outside of the circles).
The regions of instability for the common emitter topology at 1 GHz are quite
problematic, since they occur for low impedance values. In order to obtain dc operation the circuit needs to be biased by a voltage source for both the collector
(output) and base (input) terminals, resulting in a low impedance termination for
both ports. Therefore, a feed inductor of 8 nH will be needed for the collector terminal and 2 nH for the base terminal to prevent oscillations from occurring. This
71
Frequency = 1 GHz
Common Emitter Simulation
AE = 0.12x10.16 x 40 хm2
VCC = 2.1 V, ICC = 295 mA
Stable Outside Circle
Load Circle
Source Circle
Figure 46: Stability circles for common emitter class-A amplifier simulated at 1
GHz.
will require significant space and likely degrade the circuit performance, due to the
finite Q and self-resonant frequency of high inductance on-chip spiral inductors. The
cascode topology will not need to provide such large value inductive chokes for the
dc biasing of the circuit due to its inherent stability. The cascode circuit design can
actually incorporate these passives into the matching structure for the circuit, giving
it a decided advantage.
7.3
SiGe Power Amplifier Design
A cascode power amplifier design was investigated (Figure 47) to determine the efficacy of silicon based microwave power amplifiers. The cascode topology provides high
isolation between the output and the input ports, and allows for an increase in the
available operating voltage for the circuit. This topology also allows the designer to
utilize higher breakdown transistors for Q2, increasing the available voltage swing at
the output. Higher speed (and therefore higher gain) transistors can still be utilized
72
Figure 47: Schematic of the 24 GHz SiGe power amplifier.
for the driving transistor (Q1) to simultaneously achieve both high gain and high
output power for the power amplifier.
The driving transistor (Q1) consists of 20 single-stripe high-speed (150 GHz fT )
0.20x10.16 хm2 HBTs, resulting in a total emitter area (AE ) of 40.64 хm2 . The top
transistor (Q2) consists of 16 multi-stripe medium-breakdown (75 GHz fT and 3.5
V BVCEO ) HBTs with a total emitter area of 113.8 хm2 . The significant increase in
AE for Q2 results from the decrease in current density for the medium-breakdown
transistor (as compared to the high-speed transistor).
The matching for the amplifier is accomplished with on-chip passives consisting
of MIM capacitors, spiral inductors, and thin-film microstrip transmission lines. The
microstrip transmission lines utilize the top-metal (M6) for the signal path and the
lower metals (M4-M1) shorted with vias for the ground path (Figure 48). These
transmission lines were designed and modeled using ADS and Momentum simulators
in conjunction with the SiGe120 design kit. Different types (i.e. high-pass and lowpass) of matching networks are used for the input and output of the amplifier to
improve the broadband stability. Additional de-coupling capacitors were also placed
on chip at the base of Q2 and at VCC to achieve a good on-chip RF short at high
73
Figure 48: Schematic cross-section of the thin-film microstrip transmission line.
frequencies.
The simulated circuit was biased from a 5.1 V supply, and dissipated 56 mA for
the nominal dc operation. The simulated gain of the amplifier was 12.2 dB, with an
OP1dB of 22 dBm, and a peak PAE of 14 %. The simulated circuit also demonstrated
a return loss greater than 10 dB for both the input and output ports at 24 GHz.
7.4
Measured Results
The 24 GHz SiGe power amplifier (Figure 49) was fabricated in the Jazz SiGe120
technology and measured at the die level with an Agilent 8510C VNA, a 8565E
spectrum analyzer, a 4419B power meter, a 8485A power sensor, and two frequency
sweepers. The circuit was biased from a 5.1 V dc power supply, with 1.9 V applied
to the base of Q2, and 0.88 V applied to the base of Q1, resulting in a nominal ICC
of 38mA.
The amplifier was biased in a class-AB mode of operation, allowing the ICC dc
current to increase with the input power, as seen in Figure 50. The circuit achieved
an OP1dB of 20 dBm, with a gain of 10 dB, and a PAE of 14% (Figure 51). It should
be noted that the cable losses of the test setup were accounted for in the power and
efficiency measurements, but the probe losses (estimated to be approximately 0.85
dB per probe at 24 GHz) were not, and thus the reported numbers are conservative.
74
22
20
18
16
14
12
10
8
6
4
2
0
?10
150
120
90
OP1dB = 20 dBm
ICC?1dB = 123 mA
Frequency = 24 GHz
?6
?2
2
PIN (dBm)
6
10
ICC (mA)
POUT (dBm)
Figure 49: Die photo of the 24 GHz SiGe power amplifier (0.85 x 1.2 mm2 ).
60
30
14
Figure 50: Output power and ICC versus input power for the 24 GHz power amplifier.
75
12
16
14
10
10
6
8
6
4
OP1dB = 20 dBm
Frequency = 24 GHz
2
0
0
2
4
6
8
10
12 14
POUT (dBm)
16
18
20
PAE (%)
Gain (dB)
12
8
4
2
0
22
Figure 51: Gain and power added efficiency versus output power for the 24 GHz
power amplifier.
The intermodulation distortion of the amplifier was also quantified, as seen in
Figure 52. The circuit demonstrated 18 dBc of rejection for the third-order intermodulation product for output powers as high as 13 dBm. The small-signal output
third order intercept point (OIP3 ) was calculated to be 15 dBm from the two-tone
measurements. Higher-order intermodulation products were also observed, as shown
in Figure 52, but remained lower in power than the third-order product.
The S-parameters of the circuit were measured at die level from 1 GHz to 40
GHz for accurate gain, return loss, and stability characterization. Both the input
and output of the power amplifier were matched to 50 ? at 24 GHz, as seen in
Figure 53, achieving a return loss better than 9 dB for both ports from 23 GHz to 26
GHz. The circuit also achieved a gain of 12 dB (Figure 53) for the nominal dc bias
point, with a 3-dB bandwidth from 23.3 GHz to 25.8 GHz. The discrepancy between
the measured gain from S-parameters and the measured gain originating from the
power measurements is attributed to probe loss, which was not accounted for during
the power measurements. The amplifier?s stability factor (K) was also measured for
several bias points (ICC = 38, 101, 151 mA), and observed to remain greater than
76
20
FS1
10
POUT (dBm)
0
2FS1?FS2
?10
?20
3FS1?2FS2
?30
?40
FS1
?50
?60
?14 ?12 ?10 ?8
2FS1?FS2
FS1 = 24.000 GHz
FS2 = 24.001 GHz
?6
?4 ?2 0
PIN (dBm)
2
3FS1?2FS2
4
6
8
Figure 52: Output power and intermodulation products versus input power for the
24 GHz power amplifier.
unity for all measured frequencies (1 GHz - 40 GHz).
The breakdown voltage of the amplifier was also characterized for different biasing
conditions. As shown in Figure 54, the circuit can operate with a VCC up to 8V when
biased with a dc voltage source at the base of Q2. However when a higher impedance
source is incorporated at the base of Q2 (i.e., a voltage source with 300 ? of series
resistance), the circuit can only withstand voltages of 6V before breakdown occurs.
These results highlight the voltage swing benefits that the cascode topology allows
for SiGe HBT power amplifiers.
Table 8: Performance comparison of silicon-based microwave power amplifiers.
Ref. Freq. POU T Gain PAE Size
Technology
2
GHz dBm
dB
%
mm
This
work
24
20
12
14
1.02 150 GHz SiGe
[74]
24
14.5*
7
4.5* 1.26 0.18 хm CMOS
[75]
24
12*
18
3*
NR
80 GHz SiGe
[76]
24
12
17.7
2.6
0.25
80 GHz SiGe
[77]
24
21*
19
13* 6.00 120 GHz SiGe
* Correlates to saturated output power.
77
0
14
?10
S11 & S22 (dB)
12
S11
S22
S21
10
?15
8
?20
6
?25
4
VCC = 5.1 V
ICC = 38 mA
VB2 = 1.9 V
?30
?35
12
S21 (dB)
?5
2
16
20
24
0
32
28
Frequency (GHz)
Figure 53: S11 , S22 , and S21 versus frequency for the 24 GHz power amplifier.
150
IB1 = 2.3 mA
120
ICC (mA)
IB1 = 1.7 mA
90
RB2= 0 ?
RB2= 300 ?
IB1 = 1.1 mA
60
IB1 = 0.7 mA
IB1 = 0.5 mA
30
IB1 = 0.3 mA
VB2 = 1.9 V
0
1
2
3
4
5
VCC (V)
6
7
8
9
Figure 54: Output characteristics for various biasing configurations for the 24 GHz
power amplifier.
78
7.5
Performance Comparison
The performance of this 24 GHz SiGe HBT power amplifier has been compared to
other silicon-based power amplifiers (Table 8) and is competitive with previously
published SiGe power amplifiers in terms of POU T , PAE, and total die size. As
expected, the present SiGe PA does not out-perform PA?s based on GaAs pHEMT
technology [71] or InP DHBT [72] technology. However the present solution is 100%
Si foundry compatible, and thus should offer a path to low-cost, highly integrated
solutions. In addition, the performance of microwave SiGe HBT PAs can be further
enhanced using more advanced layout techniques to achieve better power combining
and overall passive performance (as demonstrated in [77]), as well as targeting more
aggressive PA topologies (such as class E or F designs). These improvements will
help close the gap between SiGe and III-V power amplifier performance, enabling
silicon-germanium technology to be utilized in emerging microwave applications.
79
CHAPTER 8
SUBSTRATE COUPLING
8.1
Introduction to Substrate Coupling for Silicon Based Technologies
Silicon-germanium HBT devices are fabricated on a lossy silicon substrate along with
their CMOS counter-parts and passive structures. This lossy substrate can hinder a
circuits
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